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ARM64: zynqmp: zcu102: Modifying GTR lane-0 to PCIe
authorBharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
Mon, 30 Jan 2017 06:36:02 +0000 (12:06 +0530)
committerMichal Simek <michal.simek@xilinx.com>
Thu, 9 Feb 2017 14:01:59 +0000 (15:01 +0100)
commite64259c957d82c6d0130967bc0315b100582a84c
tree78bd4ed5879ca3bc08951a1f1b5c03415b32d9c7tree | snapshot
parent046c438908e669572c12e21408faa1dad94a7e03commit | diff
ARM64: zynqmp: zcu102: Modifying GTR lane-0 to PCIe

- Enabling GTR lane-0 to PCIe
- Enabling PCIe node in device tree

Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arch/arm/dts/zynqmp-zcu102.dts diff | blob | blame | history
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