net: pcs: airoha: fix swapped JCPLL SDM DI_LS/DI_EN REG_FIELD entries

net: pcs: airoha: fix swapped JCPLL SDM DI_LS/DI_EN REG_FIELD entries

The JCPLL SDM DI_LS and DI_EN REG_FIELD entries have their bit
positions swapped compared to the #define macros:

  #define JCPLL_SDM_DI_LS   GENMASK(25,24)  → bits 24-25
  #define JCPLL_SDM_DI_EN   BIT(16)          → bit 16

But the REG_FIELD mapping is:
  DI_LS → REG_FIELD(..., 16, 16)  ← wrong, should be (24, 25)
  DI_EN → REG_FIELD(..., 24, 25)  ← wrong, should be (16, 16)

Fix by swapping the enum and REG_FIELD order so DI_EN comes before
DI_LS, keeping the bit values in ascending order and matching the
register layout. This way:

  [DI_EN] = REG_FIELD(..., 16, 16)  ← BIT(16) ✓
  [DI_LS] = REG_FIELD(..., 24, 25)  ← GENMASK(25,24) ✓

The TXPLL section in the same file already follows this bit-order
convention (DI_EN at bit 0, DI_LS at bits 8-9).

Signed-off-by: Wayen Yan <win847@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/23876
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>