# Boyuan Yang <073plan@gmail.com>, 2019, 2023-2025.
# Zixing Zhou <zixingzhou@foxmail.com>, 2023.
# Zhanhaoxiang Zhang <zzhx2006@outlook.com>, 2024, 2026.
# Boyuan Yang <073plan@gmail.com>, 2019, 2023-2025.
# Zixing Zhou <zixingzhou@foxmail.com>, 2023.
# Zhanhaoxiang Zhang <zzhx2006@outlook.com>, 2024, 2026.
-"PO-Revision-Date: 2026-04-08 19:22+0800\n"
-"Last-Translator: Zhanhaoxiang Zhang <zzhx2006@outlook.com>\n"
+"PO-Revision-Date: 2026-07-28 20:15-0400\n"
+"Last-Translator: Boyuan Yang <073plan@gmail.com>\n"
"Content-Transfer-Encoding: 8bit\n"
"Plural-Forms: nplurals=1; plural=0;\n"
"X-Bugs: Report translation errors to the Language-Team address.\n"
"Content-Transfer-Encoding: 8bit\n"
"Plural-Forms: nplurals=1; plural=0;\n"
"X-Bugs: Report translation errors to the Language-Team address.\n"
#: config/nds32/nds32-elf.opt:3 config/nds32/nds32-linux.opt:3
#, no-c-format
msgid "Specify the address generation strategy for code model."
#: config/nds32/nds32-elf.opt:3 config/nds32/nds32-linux.opt:3
#, no-c-format
msgid "Specify the address generation strategy for code model."
#: config/nds32/nds32.opt:47
#, no-c-format
msgid "Specify which ABI type to generate code for: 2, 2fp+."
#: config/nds32/nds32.opt:47
#, no-c-format
msgid "Specify which ABI type to generate code for: 2, 2fp+."
msgstr "支持 MMX、SSE、SSE2、SSE3、SSSE3、SSE4.1、SSE4.2、AVX、AVX2 和 AVX512F 内建函数及代码生成。"
#: config/i386/i386.opt:737
msgstr "支持 MMX、SSE、SSE2、SSE3、SSSE3、SSE4.1、SSE4.2、AVX、AVX2 和 AVX512F 内建函数及代码生成。"
#: config/i386/i386.opt:737
-#, fuzzy, no-c-format
-#| msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512CD built-in functions and code generation."
msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512CD built-in functions and code generation."
msgstr "支持 MMX、SSE、SSE2、SSE3、SSSE3、SSE4.1、SSE4.2、AVX、AVX2、AVX512F 和 AVX512CD 内建函数及代码生成。"
#: config/i386/i386.opt:741
msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512CD built-in functions and code generation."
msgstr "支持 MMX、SSE、SSE2、SSE3、SSSE3、SSE4.1、SSE4.2、AVX、AVX2、AVX512F 和 AVX512CD 内建函数及代码生成。"
#: config/i386/i386.opt:741
-#, fuzzy, no-c-format
-#| msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512DQ built-in functions and code generation."
msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512DQ built-in functions and code generation."
msgstr "支持 MMX、SSE、SSE2、SSE3、SSSE3、SSE4.1、SSE4.2、AVX、AVX2、AVX512F 和 AVX512DQ 内建函数及代码生成。"
#: config/i386/i386.opt:745
msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512DQ built-in functions and code generation."
msgstr "支持 MMX、SSE、SSE2、SSE3、SSSE3、SSE4.1、SSE4.2、AVX、AVX2、AVX512F 和 AVX512DQ 内建函数及代码生成。"
#: config/i386/i386.opt:745
-#, fuzzy, no-c-format
-#| msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512BF16 built-in functions and code generation."
msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512BW built-in functions and code generation."
msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512BW built-in functions and code generation."
-#, fuzzy, no-c-format
-#| msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512VL built-in functions and code generation."
msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512VL built-in functions and code generation."
msgstr "支持 MMX、SSE、SSE2、SSE3、SSSE3、SSE4.1、SSE4.2、AVX、AVX2、AVX512F 和 AVX512VL 内建函数及代码生成。"
#: config/i386/i386.opt:753
msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512VL built-in functions and code generation."
msgstr "支持 MMX、SSE、SSE2、SSE3、SSSE3、SSE4.1、SSE4.2、AVX、AVX2、AVX512F 和 AVX512VL 内建函数及代码生成。"
#: config/i386/i386.opt:753
-#, fuzzy, no-c-format
-#| msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX5124FMAPS built-in functions and code generation."
msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512IFMA built-in functions and code generation."
msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512IFMA built-in functions and code generation."
-#, fuzzy, no-c-format
-#| msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512VBMI2 built-in functions and code generation."
msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512VBMI built-in functions and code generation."
msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512VBMI built-in functions and code generation."
#: config/i386/i386.opt:956
#, no-c-format
msgid "Generate __mcount_loc section with all mcount or __fentry__ calls."
#: config/i386/i386.opt:956
#, no-c-format
msgid "Generate __mcount_loc section with all mcount or __fentry__ calls."
#: config/i386/i386.opt:960 config/s390/s390.opt:332
#, no-c-format
msgid "Generate mcount/__fentry__ calls as nops. To activate they need to be patched in."
#: config/i386/i386.opt:960 config/s390/s390.opt:332
#, no-c-format
msgid "Generate mcount/__fentry__ calls as nops. To activate they need to be patched in."
#: config/i386/i386.opt:1048
#, no-c-format
msgid "Enable shadow stack built-in functions from Control-flow Enforcement Technology (CET)."
#: config/i386/i386.opt:1048
#, no-c-format
msgid "Enable shadow stack built-in functions from Control-flow Enforcement Technology (CET)."
#: config/i386/i386.opt:1053
#, no-c-format
msgid "Turn on CET instrumentation for switch statements that use a jump table and an indirect jump."
#: config/i386/i386.opt:1053
#, no-c-format
msgid "Turn on CET instrumentation for switch statements that use a jump table and an indirect jump."
#: config/i386/i386.opt:1058
#, no-c-format
msgid "Insert ENDBR instruction at function entry only via cf_check attribute for CET instrumentation."
#: config/i386/i386.opt:1058
#, no-c-format
msgid "Insert ENDBR instruction at function entry only via cf_check attribute for CET instrumentation."
#: config/i386/i386.opt:1091
#, no-c-format
msgid "Add CS prefix to call and jmp to indirect thunk with branch target in r8-r15 registers."
#: config/i386/i386.opt:1091
#, no-c-format
msgid "Add CS prefix to call and jmp to indirect thunk with branch target in r8-r15 registers."
#: config/i386/i386.opt:1119
#, no-c-format
msgid "Known choices for return instrumentation with -minstrument-return=:"
#: config/i386/i386.opt:1119
#, no-c-format
msgid "Known choices for return instrumentation with -minstrument-return=:"
#: config/i386/i386.opt:1132
#, no-c-format
msgid "Generate a __return_loc section pointing to all return instrumentation code."
#: config/i386/i386.opt:1132
#, no-c-format
msgid "Generate a __return_loc section pointing to all return instrumentation code."
#: config/i386/i386.opt:1140
#, no-c-format
msgid "Known choices for mitigation against straight line speculation with -mharden-sls=:"
#: config/i386/i386.opt:1140
#, no-c-format
msgid "Known choices for mitigation against straight line speculation with -mharden-sls=:"
msgstr "支持 MMX、SSE、SSE2、SSE3、SSSE3、SSE4.1、SSE4.2、AVX、AVX2、AVX512F 和 AVX512-FP16 内建函数及代码生成。"
#: config/i386/i386.opt:1214
msgstr "支持 MMX、SSE、SSE2、SSE3、SSSE3、SSE4.1、SSE4.2、AVX、AVX2、AVX512F 和 AVX512-FP16 内建函数及代码生成。"
#: config/i386/i386.opt:1214
#: config/i386/i386.opt:1258 config/aarch64/aarch64.opt:426
#, no-c-format
msgid "Limit how much the autovectorizer may unroll a loop."
#: config/i386/i386.opt:1258 config/aarch64/aarch64.opt:426
#, no-c-format
msgid "Limit how much the autovectorizer may unroll a loop."
#: config/i386/i386.opt:1262
#, no-c-format
msgid "Whether x86 vectorizer cost modeling compares costs of different vector sizes."
#: config/i386/i386.opt:1262
#, no-c-format
msgid "Whether x86 vectorizer cost modeling compares costs of different vector sizes."
#: config/i386/i386.opt:1266
#, no-c-format
msgid "-mlam=[none|u48|u57] Instrument meta data position in user data pointers."
#: config/i386/i386.opt:1266
#, no-c-format
msgid "-mlam=[none|u48|u57] Instrument meta data position in user data pointers."
#: config/i386/i386.opt:1314
#, no-c-format
msgid "Support code generation for APX features, including EGPR, PUSH2POP2, NDD, PPX, NF, CCMP and ZU."
#: config/i386/i386.opt:1314
#, no-c-format
msgid "Support code generation for APX features, including EGPR, PUSH2POP2, NDD, PPX, NF, CCMP and ZU."
msgstr "支持 MMX、SSE、SSE2、SSE3、SSSE3、SSE4.1、SSE4.2、AVX、AVX2 和 AVX10.1 内建函数及代码生成。"
#: config/i386/i386.opt:1365
msgstr "支持 MMX、SSE、SSE2、SSE3、SSSE3、SSE4.1、SSE4.2、AVX、AVX2 和 AVX10.1 内建函数及代码生成。"
#: config/i386/i386.opt:1365
-#, fuzzy, no-c-format
-#| msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512BF16 built-in functions and code generation."
msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX10.1 and AVX10.2 built-in functions and code generation."
msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX10.1 and AVX10.2 built-in functions and code generation."
-#, fuzzy, no-c-format
-#| msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512BF16 built-in functions and code generation."
msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX10.1, AVX10.2 and AMX-AVX512 built-in functions and code generation."
msgid "Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX10.1, AVX10.2 and AMX-AVX512 built-in functions and code generation."
#: config/arm/arm.opt:123
#, no-c-format
msgid "Specify that the compiler should target secure code as per ARMv8-M Security Extensions."
#: config/arm/arm.opt:123
#, no-c-format
msgid "Specify that the compiler should target secure code as per ARMv8-M Security Extensions."
#: config/arm/arm.opt:253
#, no-c-format
msgid "Print CPU tuning information as comment in assembler file. This is an option used only for regression testing of the compiler and not intended for ordinary use in compiling code."
#: config/arm/arm.opt:253
#, no-c-format
msgid "Print CPU tuning information as comment in assembler file. This is an option used only for regression testing of the compiler and not intended for ordinary use in compiling code."
#: config/arm/arm.opt:272
#, no-c-format
msgid "Enable more verbose RTX cost dumps during debug. For GCC developers use only."
#: config/arm/arm.opt:272
#, no-c-format
msgid "Enable more verbose RTX cost dumps during debug. For GCC developers use only."
#: config/arm/arm.opt:289
#, no-c-format
msgid "Mitigate issues with VLLDM on some M-profile devices (CVE-2021-35465)."
#: config/arm/arm.opt:289
#, no-c-format
msgid "Mitigate issues with VLLDM on some M-profile devices (CVE-2021-35465)."
#: config/arm/arm.opt:293
#, no-c-format
msgid "Mitigate issues with AES instructions on Cortex-A57 and Cortex-A72 (Arm erratum #1742098)."
#: config/arm/arm.opt:293
#, no-c-format
msgid "Mitigate issues with AES instructions on Cortex-A57 and Cortex-A72 (Arm erratum #1742098)."
#: config/arm/arm.opt:298
#, no-c-format
msgid "Mitigate issues with AES instructions on Cortex-A57 and Cortex-A72 (Arm erratum #1655431)."
#: config/arm/arm.opt:298
#, no-c-format
msgid "Mitigate issues with AES instructions on Cortex-A57 and Cortex-A72 (Arm erratum #1655431)."
#: config/arm/arm.opt:311
#, no-c-format
msgid "Assume loading data from flash is slower than fetching instructions."
#: config/arm/arm.opt:311
#, no-c-format
msgid "Assume loading data from flash is slower than fetching instructions."
#: config/arm/arm.opt:323
#, no-c-format
msgid "When linking for big-endian targets, generate a BE8 format image."
#: config/arm/arm.opt:323
#, no-c-format
msgid "When linking for big-endian targets, generate a BE8 format image."
#: config/arm/arm.opt:327
#, no-c-format
msgid "When linking for big-endian targets, generate a legacy BE32 format image."
#: config/arm/arm.opt:327
#, no-c-format
msgid "When linking for big-endian targets, generate a legacy BE32 format image."
#: config/arm/arm.opt:361
#, no-c-format
msgid "Use an immediate to offset from the TLS register. This option is for use with fstack-protector-guard=tls and not for use in user-land code."
#: config/arm/arm.opt:361
#, no-c-format
msgid "Use an immediate to offset from the TLS register. This option is for use with fstack-protector-guard=tls and not for use in user-land code."
#: config/aarch64/aarch64.opt:70 config/loongarch/loongarch.opt:276
#, no-c-format
msgid "The code model option names for -mcmodel:"
#: config/aarch64/aarch64.opt:70 config/loongarch/loongarch.opt:276
#, no-c-format
msgid "The code model option names for -mcmodel:"
#: config/aarch64/aarch64.opt:87
#, no-c-format
msgid "Generates an error message if an attempt is made to access a system register which is not available on the target architecture."
#: config/aarch64/aarch64.opt:87
#, no-c-format
msgid "Generates an error message if an attempt is made to access a system register which is not available on the target architecture."
#: config/aarch64/aarch64.opt:108
#, no-c-format
msgid "Enable narrowing of 64-bit general purpose register writes to 32-bit when upper 32 bits of the register are unused."
#: config/aarch64/aarch64.opt:108
#, no-c-format
msgid "Enable narrowing of 64-bit general purpose register writes to 32-bit when upper 32 bits of the register are unused."
#: config/aarch64/aarch64.opt:156
#, no-c-format
msgid "Don't assume that unaligned accesses are handled by the system."
#: config/aarch64/aarch64.opt:156
#, no-c-format
msgid "Don't assume that unaligned accesses are handled by the system."
msgid "Specifies bit size of immediate TLS offsets. Valid values are 12, 24, 32, 48."
msgid "Specifies bit size of immediate TLS offsets. Valid values are 12, 24, 32, 48."
#: config/aarch64/aarch64.opt:203
#, no-c-format
msgid "-fdump-tuning-model=<filename> Dump current tuning model to a JSON file."
#: config/aarch64/aarch64.opt:203
#, no-c-format
msgid "-fdump-tuning-model=<filename> Dump current tuning model to a JSON file."
#: config/aarch64/aarch64.opt:207
#, no-c-format
msgid "-muser-provided-CPU=<json-tuning-file> User specific CPU tunings."
#: config/aarch64/aarch64.opt:207
#, no-c-format
msgid "-muser-provided-CPU=<json-tuning-file> User specific CPU tunings."
#: config/aarch64/aarch64.opt:211
#, no-c-format
msgid "-moverride=<string>\tPower users only! Override CPU optimization parameters."
#: config/aarch64/aarch64.opt:211
#, no-c-format
msgid "-moverride=<string>\tPower users only! Override CPU optimization parameters."
#: config/aarch64/aarch64.opt:250
#, no-c-format
msgid "Enable the reciprocal square root approximation. Enabling this reduces precision of reciprocal square root results to about 16 bits for single precision and to 32 bits for double precision."
#: config/aarch64/aarch64.opt:250
#, no-c-format
msgid "Enable the reciprocal square root approximation. Enabling this reduces precision of reciprocal square root results to about 16 bits for single precision and to 32 bits for double precision."
#: config/aarch64/aarch64.opt:256
#, no-c-format
msgid "Enable the square root approximation. Enabling this reduces precision of square root results to about 16 bits for single precision and to 32 bits for double precision. If enabled, it implies -mlow-precision-recip-sqrt."
#: config/aarch64/aarch64.opt:256
#, no-c-format
msgid "Enable the square root approximation. Enabling this reduces precision of square root results to about 16 bits for single precision and to 32 bits for double precision. If enabled, it implies -mlow-precision-recip-sqrt."
#: config/aarch64/aarch64.opt:263
#, no-c-format
msgid "Enable the division approximation. Enabling this reduces precision of division results to about 16 bits for single precision and to 32 bits for double precision."
#: config/aarch64/aarch64.opt:263
#, no-c-format
msgid "Enable the division approximation. Enabling this reduces precision of division results to about 16 bits for single precision and to 32 bits for double precision."
#: config/aarch64/aarch64.opt:309
#, no-c-format
msgid "-msve-vector-bits=<number>\tSet the number of bits in an SVE vector register."
#: config/aarch64/aarch64.opt:309
#, no-c-format
msgid "-msve-vector-bits=<number>\tSet the number of bits in an SVE vector register."
#: c-family/c-ada-spec.cc:3030
#, fuzzy, gcc-internal-format
#: c-family/c-ada-spec.cc:3030
#, fuzzy, gcc-internal-format
#: c-family/c-attribs.cc:749 c-family/c-attribs.cc:754
#, gcc-internal-format
msgid "cannot tail-call: return value must be a call"
#: c-family/c-attribs.cc:749 c-family/c-attribs.cc:754
#, gcc-internal-format
msgid "cannot tail-call: return value must be a call"
#: c-family/c-attribs.cc:787 d/d-attribs.cc:1198
#, fuzzy, gcc-internal-format
#: c-family/c-attribs.cc:787 d/d-attribs.cc:1198
#, fuzzy, gcc-internal-format
#: rust/resolve/rust-late-name-resolver-2.0.cc:351
#, gcc-internal-format, gfc-internal-format
msgid "are you trying to break %s? how dare you?"
#: rust/resolve/rust-late-name-resolver-2.0.cc:351
#, gcc-internal-format, gfc-internal-format
msgid "are you trying to break %s? how dare you?"
#, fuzzy, gcc-internal-format
#~ msgid "%qT is not consteval-only"
#, fuzzy, gcc-internal-format
#~ msgid "%qT is not consteval-only"