arm64: dts: rockchip: add #power-domain-cells to power domain nodes

[ Upstream commit 837188d49823230f47afdbbec7556740e89a8557 ]

Add #power-domain-cells to power domain nodes, because they
are required by power-domain.yaml

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Link: https://lore.kernel.org/r/20210417112952.8516-9-jbx6244@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Stable-dep-of: 3699f2c43ea9 ("arm64: dts: rockchip: add hevc power domain clock to rk3328")
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi
index f241e7c318bcdd2e36da19c44e2415b6988fe05f..91e4d92d2ab2fb700c1b0fd3172ffe896e7e1b3a 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/px30.dtsi
+++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
@@ -250,12 +250,14 @@
                                         <&cru HCLK_OTG>,
                                         <&cru SCLK_OTG_ADP>;
                                pm_qos = <&qos_usb_host>, <&qos_usb_otg>;
+                               #power-domain-cells = <0>;
                        };
                        power-domain@PX30_PD_SDCARD {
                                reg = <PX30_PD_SDCARD>;
                                clocks = <&cru HCLK_SDMMC>,
                                         <&cru SCLK_SDMMC>;
                                pm_qos = <&qos_sdmmc>;
+                               #power-domain-cells = <0>;
                        };
                        power-domain@PX30_PD_GMAC {
                                reg = <PX30_PD_GMAC>;
@@ -264,6 +266,7 @@
                                         <&cru SCLK_MAC_REF>,
                                         <&cru SCLK_GMAC_RX_TX>;
                                pm_qos = <&qos_gmac>;
+                               #power-domain-cells = <0>;
                        };
                        power-domain@PX30_PD_MMC_NAND {
                                reg = <PX30_PD_MMC_NAND>;
@@ -277,6 +280,7 @@
                                          <&cru SCLK_SFC>;
                                pm_qos = <&qos_emmc>, <&qos_nand>,
                                         <&qos_sdio>, <&qos_sfc>;
+                               #power-domain-cells = <0>;
                        };
                        power-domain@PX30_PD_VPU {
                                reg = <PX30_PD_VPU>;
@@ -284,6 +288,7 @@
                                         <&cru HCLK_VPU>,
                                         <&cru SCLK_CORE_VPU>;
                                pm_qos = <&qos_vpu>, <&qos_vpu_r128>;
+                               #power-domain-cells = <0>;
                        };
                        power-domain@PX30_PD_VO {
                                reg = <PX30_PD_VO>;
@@ -300,6 +305,7 @@
                                         <&cru SCLK_VOPB_PWM>;
                                pm_qos = <&qos_rga_rd>, <&qos_rga_wr>,
                                         <&qos_vop_m0>, <&qos_vop_m1>;
+                               #power-domain-cells = <0>;
                        };
                        power-domain@PX30_PD_VI {
                                reg = <PX30_PD_VI>;
@@ -311,11 +317,13 @@
                                pm_qos = <&qos_isp_128>, <&qos_isp_rd>,
                                         <&qos_isp_wr>, <&qos_isp_m1>,
                                         <&qos_vip>;
+                               #power-domain-cells = <0>;
                        };
                        power-domain@PX30_PD_GPU {
                                reg = <PX30_PD_GPU>;
                                clocks = <&cru SCLK_GPU>;
                                pm_qos = <&qos_gpu>;
+                               #power-domain-cells = <0>;
                        };
                };
        };

diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index 9e1701f4218418468afcf2f4cb9eb54e122dfe69..5a706b8ffc72ae5e63f407b914de64c3ca899c45 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -320,13 +320,16 @@
 
                        power-domain@RK3328_PD_HEVC {
                                reg = <RK3328_PD_HEVC>;
+                               #power-domain-cells = <0>;
                        };
                        power-domain@RK3328_PD_VIDEO {
                                reg = <RK3328_PD_VIDEO>;
+                               #power-domain-cells = <0>;
                        };
                        power-domain@RK3328_PD_VPU {
                                reg = <RK3328_PD_VPU>;
                                clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+                               #power-domain-cells = <0>;
                        };
                };
 

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index e2515218ff734366512737b02bd796f5f37a5039..bf71f390f8a634e8fb2e3d7a619f8200d6ff99f6 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1005,6 +1005,7 @@
                                clocks = <&cru ACLK_IEP>,
                                         <&cru HCLK_IEP>;
                                pm_qos = <&qos_iep>;
+                               #power-domain-cells = <0>;
                        };
                        power-domain@RK3399_PD_RGA {
                                reg = <RK3399_PD_RGA>;
@@ -1012,12 +1013,14 @@
                                         <&cru HCLK_RGA>;
                                pm_qos = <&qos_rga_r>,
                                         <&qos_rga_w>;
+                               #power-domain-cells = <0>;
                        };
                        power-domain@RK3399_PD_VCODEC {
                                reg = <RK3399_PD_VCODEC>;
                                clocks = <&cru ACLK_VCODEC>,
                                         <&cru HCLK_VCODEC>;
                                pm_qos = <&qos_video_m0>;
+                               #power-domain-cells = <0>;
                        };
                        power-domain@RK3399_PD_VDU {
                                reg = <RK3399_PD_VDU>;
@@ -1027,6 +1030,7 @@
                                         <&cru SCLK_VDU_CORE>;
                                pm_qos = <&qos_video_m1_r>,
                                         <&qos_video_m1_w>;
+                               #power-domain-cells = <0>;
                        };
 
                        /* These power domains are grouped by VD_GPU */
@@ -1034,53 +1038,63 @@
                                reg = <RK3399_PD_GPU>;
                                clocks = <&cru ACLK_GPU>;
                                pm_qos = <&qos_gpu>;
+                               #power-domain-cells = <0>;
                        };
 
                        /* These power domains are grouped by VD_LOGIC */
                        power-domain@RK3399_PD_EDP {
                                reg = <RK3399_PD_EDP>;
                                clocks = <&cru PCLK_EDP_CTRL>;
+                               #power-domain-cells = <0>;
                        };
                        power-domain@RK3399_PD_EMMC {
                                reg = <RK3399_PD_EMMC>;
                                clocks = <&cru ACLK_EMMC>;
                                pm_qos = <&qos_emmc>;
+                               #power-domain-cells = <0>;
                        };
                        power-domain@RK3399_PD_GMAC {
                                reg = <RK3399_PD_GMAC>;
                                clocks = <&cru ACLK_GMAC>,
                                         <&cru PCLK_GMAC>;
                                pm_qos = <&qos_gmac>;
+                               #power-domain-cells = <0>;
                        };
                        power-domain@RK3399_PD_SD {
                                reg = <RK3399_PD_SD>;
                                clocks = <&cru HCLK_SDMMC>,
                                         <&cru SCLK_SDMMC>;
                                pm_qos = <&qos_sd>;
+                               #power-domain-cells = <0>;
                        };
                        power-domain@RK3399_PD_SDIOAUDIO {
                                reg = <RK3399_PD_SDIOAUDIO>;
                                clocks = <&cru HCLK_SDIO>;
                                pm_qos = <&qos_sdioaudio>;
+                               #power-domain-cells = <0>;
                        };
                        power-domain@RK3399_PD_TCPD0 {
                                reg = <RK3399_PD_TCPD0>;
                                clocks = <&cru SCLK_UPHY0_TCPDCORE>,
                                         <&cru SCLK_UPHY0_TCPDPHY_REF>;
+                               #power-domain-cells = <0>;
                        };
                        power-domain@RK3399_PD_TCPD1 {
                                reg = <RK3399_PD_TCPD1>;
                                clocks = <&cru SCLK_UPHY1_TCPDCORE>,
                                         <&cru SCLK_UPHY1_TCPDPHY_REF>;
+                               #power-domain-cells = <0>;
                        };
                        power-domain@RK3399_PD_USB3 {
                                reg = <RK3399_PD_USB3>;
                                clocks = <&cru ACLK_USB3>;
                                pm_qos = <&qos_usb_otg0>,
                                         <&qos_usb_otg1>;
+                               #power-domain-cells = <0>;
                        };
                        power-domain@RK3399_PD_VIO {
                                reg = <RK3399_PD_VIO>;
+                               #power-domain-cells = <1>;
                                #address-cells = <1>;
                                #size-cells = <0>;
 
@@ -1090,6 +1104,7 @@
                                                 <&cru HCLK_HDCP>,
                                                 <&cru PCLK_HDCP>;
                                        pm_qos = <&qos_hdcp>;
+                                       #power-domain-cells = <0>;
                                };
                                power-domain@RK3399_PD_ISP0 {
                                        reg = <RK3399_PD_ISP0>;
@@ -1097,6 +1112,7 @@
                                                 <&cru HCLK_ISP0>;
                                        pm_qos = <&qos_isp0_m0>,
                                                 <&qos_isp0_m1>;
+                                       #power-domain-cells = <0>;
                                };
                                power-domain@RK3399_PD_ISP1 {
                                        reg = <RK3399_PD_ISP1>;
@@ -1104,9 +1120,11 @@
                                                 <&cru HCLK_ISP1>;
                                        pm_qos = <&qos_isp1_m0>,
                                                 <&qos_isp1_m1>;
+                                       #power-domain-cells = <0>;
                                };
                                power-domain@RK3399_PD_VO {
                                        reg = <RK3399_PD_VO>;
+                                       #power-domain-cells = <1>;
                                        #address-cells = <1>;
                                        #size-cells = <0>;
 
@@ -1116,12 +1134,14 @@
                                                         <&cru HCLK_VOP0>;
                                                pm_qos = <&qos_vop_big_r>,
                                                         <&qos_vop_big_w>;
+                                               #power-domain-cells = <0>;
                                        };
                                        power-domain@RK3399_PD_VOPL {
                                                reg = <RK3399_PD_VOPL>;
                                                clocks = <&cru ACLK_VOP1>,
                                                         <&cru HCLK_VOP1>;
                                                pm_qos = <&qos_vop_little>;
+                                               #power-domain-cells = <0>;
                                        };
                                };
                        };