arm64: dts: qcom: qcs8300: Add gpu and gmu nodes

Add gpu and gmu nodes for qcs8300 chipset.

Signed-off-by: Jie Zhang <quic_jiezh@quicinc.com>
Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250903-a623-gpu-support-v5-3-5398585e2981@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
index d35bfece60d1afa5205d71c3b1b621dce49c805e..8d78ccac411e495592a6ff532c99e7aba087d18c 100644 (file)
--- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
@@ -924,9 +924,14 @@
 
                qfprom: efuse@784000 {
                        compatible = "qcom,qcs8300-qfprom", "qcom,qfprom";
-                       reg = <0x0 0x00784000 0x0 0x1200>;
+                       reg = <0x0 0x00784000 0x0 0x2410>;
                        #address-cells = <1>;
                        #size-cells = <1>;
+
+                       gpu_speed_bin: gpu_speed_bin@240c {
+                               reg = <0x240c 0x1>;
+                               bits = <0 8>;
+                       };
                };
 
                gpi_dma0: dma-controller@900000 {
@@ -4289,6 +4294,104 @@
                        status = "disabled";
                };
 
+               gpu: gpu@3d00000 {
+                       compatible = "qcom,adreno-623.0", "qcom,adreno";
+                       reg = <0x0 0x03d00000 0x0 0x40000>,
+                             <0x0 0x03d9e000 0x0 0x1000>,
+                             <0x0 0x03d61000 0x0 0x800>;
+                       reg-names = "kgsl_3d0_reg_memory",
+                                   "cx_mem",
+                                   "cx_dbgc";
+                       interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+                       iommus = <&adreno_smmu 0 0xc00>,
+                                <&adreno_smmu 1 0xc00>;
+                       operating-points-v2 = <&gpu_opp_table>;
+                       qcom,gmu = <&gmu>;
+                       interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS
+                                        &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+                       interconnect-names = "gfx-mem";
+                       #cooling-cells = <2>;
+
+                       nvmem-cells = <&gpu_speed_bin>;
+                       nvmem-cell-names = "speed_bin";
+
+                       status = "disabled";
+
+                       gpu_zap_shader: zap-shader {
+                               memory-region = <&gpu_microcode_mem>;
+                       };
+
+                       gpu_opp_table: opp-table {
+                               compatible = "operating-points-v2";
+
+                               opp-877000000 {
+                                       opp-hz = /bits/ 64 <877000000>;
+                                       opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+                                       opp-peak-kBps = <12484375>;
+                                       opp-supported-hw = <0x1>;
+                               };
+
+                               opp-780000000 {
+                                       opp-hz = /bits/ 64 <780000000>;
+                                       opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+                                       opp-peak-kBps = <10687500>;
+                                       opp-supported-hw = <0x1>;
+                               };
+
+                               opp-599000000 {
+                                       opp-hz = /bits/ 64 <599000000>;
+                                       opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+                                       opp-peak-kBps = <8171875>;
+                                       opp-supported-hw = <0x3>;
+                               };
+
+                               opp-479000000 {
+                                       opp-hz = /bits/ 64 <479000000>;
+                                       opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+                                       opp-peak-kBps = <5285156>;
+                                       opp-supported-hw = <0x3>;
+                               };
+                       };
+               };
+
+               gmu: gmu@3d6a000 {
+                       compatible = "qcom,adreno-gmu-623.0", "qcom,adreno-gmu";
+                       reg = <0x0 0x03d6a000 0x0 0x34000>,
+                             <0x0 0x03de0000 0x0 0x10000>,
+                             <0x0 0x0b290000 0x0 0x10000>;
+                       reg-names = "gmu", "rscc", "gmu_pdc";
+                       interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "hfi", "gmu";
+                       clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
+                                <&gpucc GPU_CC_CXO_CLK>,
+                                <&gcc GCC_DDRSS_GPU_AXI_CLK>,
+                                <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+                                <&gpucc GPU_CC_AHB_CLK>,
+                                <&gpucc GPU_CC_HUB_CX_INT_CLK>;
+                       clock-names = "gmu",
+                                     "cxo",
+                                     "axi",
+                                     "memnoc",
+                                     "ahb",
+                                     "hub";
+                       power-domains = <&gpucc GPU_CC_CX_GDSC>,
+                                       <&gpucc GPU_CC_GX_GDSC>;
+                       power-domain-names = "cx",
+                                            "gx";
+                       iommus = <&adreno_smmu 5 0xc00>;
+                       operating-points-v2 = <&gmu_opp_table>;
+
+                       gmu_opp_table: opp-table {
+                               compatible = "operating-points-v2";
+
+                               opp-500000000 {
+                                       opp-hz = /bits/ 64 <500000000>;
+                                       opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+                               };
+                       };
+               };
+
                gpucc: clock-controller@3d90000 {
                        compatible = "qcom,qcs8300-gpucc";
                        reg = <0x0 0x03d90000 0x0 0xa000>;