clk: tegra: Fix clock rate computation

The PLL output frequency is multiplied during the P-divider computation,
so it needs to be divided by the P-divider again before returning.

This fixes an issue where clk_round_rate() would return the multiplied
frequency instead of the real one after the P-divider.

Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index c9d1e5c68dbce3908b8aa19e6b2448ce0d5eaadf..25734348242f6f815536eb2ca96bb98c0cb9bf89 100644 (file)
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -411,6 +411,8 @@ static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
                return -EINVAL;
        }
 
+       cfg->output_rate >>= p_div;
+
        if (pll->params->pdiv_tohw) {
                ret = _p_div_to_hw(hw, 1 << p_div);
                if (ret < 0)