runtime(systemverilog): Add syntax highlighting for 1800-2023 block strings

closes: #18056

Signed-off-by: Ayan Banerjee <ayanbanrj@gmail.com>
Signed-off-by: Christian Brabandt <cb@256bit.org>

diff --git a/runtime/syntax/systemverilog.vim b/runtime/syntax/systemverilog.vim
index f99ea8d88966b7a22e804bbe111472bfb0ae5c6a..94c343e01a68f38785b1e1b28bfa91b52fce9b06 100644 (file)
--- a/runtime/syntax/systemverilog.vim
+++ b/runtime/syntax/systemverilog.vim
@@ -1,7 +1,8 @@
 " Vim syntax file
 " Language:    SystemVerilog
 " Maintainer:  kocha <kocha.lsifrontend@gmail.com>
-" Last Change: 12-Aug-2013. 
+" Last Change: 12-Aug-2013.
+" 2025 Aug 20 by Vim project: Add IEE1800-2023 block #18056
 
 " quit when a syntax file was already loaded
 if exists("b:current_syntax")
@@ -68,6 +69,9 @@ syn keyword systemverilogConditional unique0
 syn keyword systemverilogStatement   implements
 syn keyword systemverilogStatement   interconnect soft nettype
 
+" IEEE1800-2023 add
+syn region systemverilogBlockString start=+"""+ end=+"""+ contains=verilogEscape,@Spell
+
 " Define the default highlighting.
 
 " The default highlighting.
@@ -78,6 +82,7 @@ hi def link systemverilogRepeat          Repeat
 hi def link systemverilogLabel           Label
 hi def link systemverilogGlobal          Define
 hi def link systemverilogNumber          Number
+hi def link systemverilogBlockString     String
 
 
 let b:current_syntax = "systemverilog"