arm64: dts: mediatek: mt8390-genio-700-evk: Enable Mali GPU

Configure GPU regulator supplies and enable GPU for GENIO 700 EVK.

The GPU in MT8390 & MT8188 has two power inputs: "DVDD_GPU" and
"DVDD_SRAM_GPU". In Genio 700 EVK, DVDD_GPU is supplied by
mt6359_vproc2_buck_reg, and DVDD_SRAM_GPU is supplied by
mt6359_vsram_others_ldo_reg.

According to section 5.2 "Recommended Operating Conditions" in
MT8390 IoT Application Processor Datasheet v1.9, The recommended
operating voltage ranges are:

- DVDD_GPU: min 0.55V, max 0.86V, typical 0.75V
- DVDD_SRAM_GPU: min 0.71V, max 0.92V, typical 0.85V

To further optimize power saving, we couple DVDD_SRAM_GPU to
DVDD_GPU according to the following relation:

- For opp-880000000 or lower frequency, keep 0.75V
- For opp-915000000 and higher, DVDD_SRAM_GPU should follow
  DVDD_GPU. The exact voltage for DVDD_GPU should be decided by
  speed binning.

This rule is derived from the OPP table in the link.

In addition, set the voltage spread to 6250 uV, the step size of
'ldo_vsram_others' regulator of mt6359, otherwise the regulator
set_voltage operation fails.

Link: https://gitlab.com/mediatek/aiot/rity/meta-mediatek-bsp/-/blob/eedd6aedd4b0cfc0ee79b9c9b9650dfa73cf87f6/recipes-kernel/dtbo/mt8390/gpu-mali.dts
Signed-off-by: Pablo Sun <pablo.sun@mediatek.com>
Suggested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20241002022138.29241-7-pablo.sun@mediatek.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

diff --git a/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts b/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts
index 1474bef7e754d08141cbcdc22d32494d586b3bb6..0a6c9871b41e5f913740e68853aea78bc33d02aa 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts
@@ -190,6 +190,11 @@
        };
 };
 
+&gpu {
+       mali-supply = <&mt6359_vproc2_buck_reg>;
+       status = "okay";
+};
+
 &i2c0 {
        pinctrl-names = "default";
        pinctrl-0 = <&i2c0_pins>;
@@ -253,6 +258,14 @@
        status = "okay";
 };
 
+&mfg0 {
+       domain-supply = <&mt6359_vproc2_buck_reg>;
+};
+
+&mfg1 {
+       domain-supply = <&mt6359_vsram_others_ldo_reg>;
+};
+
 &mmc0 {
        status = "okay";
        pinctrl-names = "default", "state_uhs";
@@ -314,6 +327,15 @@
        regulator-max-microvolt = <3100000>;
 };
 
+&mt6359_vproc2_buck_reg {
+       /* The name "vgpu" is required by mtk-regulator-coupler */
+       regulator-name = "vgpu";
+       regulator-min-microvolt = <550000>;
+       regulator-max-microvolt = <800000>;
+       regulator-coupled-with = <&mt6359_vsram_others_ldo_reg>;
+       regulator-coupled-max-spread = <6250>;
+};
+
 &mt6359_vpu_buck_reg {
        regulator-always-on;
 };
@@ -326,6 +348,15 @@
        regulator-enable-ramp-delay = <480>;
 };
 
+&mt6359_vsram_others_ldo_reg {
+       /* The name "vsram_gpu" is required by mtk-regulator-coupler */
+       regulator-name = "vsram_gpu";
+       regulator-min-microvolt = <750000>;
+       regulator-max-microvolt = <800000>;
+       regulator-coupled-with = <&mt6359_vproc2_buck_reg>;
+       regulator-coupled-max-spread = <6250>;
+};
+
 &mt6359_vufs_ldo_reg {
        regulator-always-on;
 };