return hpll;
}
+int vlv_clock_get_gpll(struct drm_device *drm)
+{
+ struct drm_i915_private *i915 = to_i915(drm);
+
+ return vlv_get_cck_clock(drm, "GPLL ref", CCK_GPLL_CLOCK_CONTROL,
+ i915->czclk_freq);
+}
+
void intel_update_czclk(struct intel_display *display)
{
struct drm_i915_private *dev_priv = to_i915(display->drm);
const char *name, u32 reg, int ref_freq);
int vlv_get_cck_clock_hpll(struct drm_device *drm,
const char *name, u32 reg);
+int vlv_clock_get_gpll(struct drm_device *drm);
bool intel_has_pending_fb_unpin(struct intel_display *display);
void intel_encoder_destroy(struct drm_encoder *encoder);
struct drm_display_mode *
{
struct drm_i915_private *i915 = rps_to_i915(rps);
- rps->gpll_ref_freq =
- vlv_get_cck_clock(&i915->drm, "GPLL ref",
- CCK_GPLL_CLOCK_CONTROL,
- i915->czclk_freq);
+ rps->gpll_ref_freq = vlv_clock_get_gpll(&i915->drm);
drm_dbg(&i915->drm, "GPLL reference freq: %d kHz\n",
rps->gpll_ref_freq);