drm/admgpu: Add support for ATHUB 3.4.2

Add ATHUB 3_4_2

Signed-off-by: Shubhankar Milind Sardeshpande <Shubhankar.MilindSardeshpande@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/athub_v3_0.c b/drivers/gpu/drm/amd/amdgpu/athub_v3_0.c
index d1bba9c64e16d808fbaafd4e01d8764cb77b1a86..b42d9876e0a190361ced68c9e8f371310e901eda 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/athub_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/athub_v3_0.c
@@ -43,6 +43,7 @@ static uint32_t athub_v3_0_get_cg_cntl(struct amdgpu_device *adev)
                data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL_V3_0_1);
                break;
        case IP_VERSION(3, 3, 0):
+       case IP_VERSION(3, 4, 2):
                data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL_V3_3_0);
                break;
        default:
@@ -59,6 +60,7 @@ static void athub_v3_0_set_cg_cntl(struct amdgpu_device *adev, uint32_t data)
                WREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL_V3_0_1, data);
                break;
        case IP_VERSION(3, 3, 0):
+       case IP_VERSION(3, 4, 2):
                WREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL_V3_3_0, data);
                break;
        default:
@@ -112,6 +114,7 @@ int athub_v3_0_set_clockgating(struct amdgpu_device *adev,
        case IP_VERSION(3, 0, 1):
        case IP_VERSION(3, 0, 2):
        case IP_VERSION(3, 3, 0):
+       case IP_VERSION(3, 4, 2):
                athub_v3_0_update_medium_grain_clock_gating(adev,
                                state == AMD_CG_STATE_GATE);
                athub_v3_0_update_medium_grain_light_sleep(adev,