5.4-stable patches

added patches:
	counter-stm32-timer-cnt-fix-ceiling-miss-alignment-with-reload-register.patch

diff --git a/queue-5.4/counter-stm32-timer-cnt-fix-ceiling-miss-alignment-with-reload-register.patch b/queue-5.4/counter-stm32-timer-cnt-fix-ceiling-miss-alignment-with-reload-register.patch
new file mode 100644 (file)
index 0000000..8cb008c
--- /dev/null
+++ b/queue-5.4/counter-stm32-timer-cnt-fix-ceiling-miss-alignment-with-reload-register.patch
@@ -0,0 +1,93 @@
+From foo@baz Sat Apr 10 01:37:31 PM CEST 2021
+From: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
+Date: Wed, 3 Mar 2021 18:49:49 +0100
+Subject: counter: stm32-timer-cnt: fix ceiling miss-alignment with reload register
+
+From: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
+
+commit b14d72ac731753708a7c1a6b3657b9312b6f0042 upstream
+
+Ceiling value may be miss-aligned with what's actually configured into the
+ARR register. This is seen after probe as currently the ARR value is zero,
+whereas ceiling value is set to the maximum. So:
+- reading ceiling reports zero
+- in case the counter gets enabled without any prior configuration,
+  it won't count.
+- in case the function gets set by the user 1st, (priv->ceiling) is used.
+
+Fix it by getting rid of the cached "priv->ceiling" variable. Rather use
+the ARR register value directly by using regmap read or write when needed.
+There should be no drawback on performance as priv->ceiling isn't used in
+performance critical path.
+There's also no point in writing ARR while setting function (sms), so
+it can be safely removed.
+
+Fixes: ad29937e206f ("counter: Add STM32 Timer quadrature encoder")
+Suggested-by: William Breathitt Gray <vilhelm.gray@gmail.com>
+Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
+Acked-by: William Breathitt Gray <vilhelm.gray@gmail.com>
+Cc: <Stable@vger.kernel.org>
+Link: https://lore.kernel.org/r/1614793789-10346-1-git-send-email-fabrice.gasnier@foss.st.com
+Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
+[sudip: adjuct context]
+Signed-off-by: Sudip Mukherjee <sudipm.mukherjee@gmail.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/counter/stm32-timer-cnt.c |   12 +++---------
+ 1 file changed, 3 insertions(+), 9 deletions(-)
+
+--- a/drivers/counter/stm32-timer-cnt.c
++++ b/drivers/counter/stm32-timer-cnt.c
+@@ -24,7 +24,6 @@ struct stm32_timer_cnt {
+       struct counter_device counter;
+       struct regmap *regmap;
+       struct clk *clk;
+-      u32 ceiling;
+       u32 max_arr;
+ };
+ 
+@@ -67,14 +66,15 @@ static int stm32_count_write(struct coun
+                            struct counter_count_write_value *val)
+ {
+       struct stm32_timer_cnt *const priv = counter->priv;
+-      u32 cnt;
++      u32 cnt, ceiling;
+       int err;
+ 
+       err = counter_count_write_value_get(&cnt, COUNTER_COUNT_POSITION, val);
+       if (err)
+               return err;
+ 
+-      if (cnt > priv->ceiling)
++      regmap_read(priv->regmap, TIM_ARR, &ceiling);
++      if (cnt > ceiling)
+               return -EINVAL;
+ 
+       return regmap_write(priv->regmap, TIM_CNT, cnt);
+@@ -136,10 +136,6 @@ static int stm32_count_function_set(stru
+ 
+       regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
+ 
+-      /* TIMx_ARR register shouldn't be buffered (ARPE=0) */
+-      regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);
+-      regmap_write(priv->regmap, TIM_ARR, priv->ceiling);
+-
+       regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, sms);
+ 
+       /* Make sure that registers are updated */
+@@ -197,7 +193,6 @@ static ssize_t stm32_count_ceiling_write
+       regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);
+       regmap_write(priv->regmap, TIM_ARR, ceiling);
+ 
+-      priv->ceiling = ceiling;
+       return len;
+ }
+ 
+@@ -369,7 +364,6 @@ static int stm32_timer_cnt_probe(struct
+ 
+       priv->regmap = ddata->regmap;
+       priv->clk = ddata->clk;
+-      priv->ceiling = ddata->max_arr;
+       priv->max_arr = ddata->max_arr;
+ 
+       priv->counter.name = dev_name(dev);

diff --git a/queue-5.4/series b/queue-5.4/series
new file mode 100644 (file)
index 0000000..a59f836
--- /dev/null
+++ b/queue-5.4/series
@@ -0,0 +1 @@
+counter-stm32-timer-cnt-fix-ceiling-miss-alignment-with-reload-register.patch