RISC-V: Update Xsfvfnrclip implementation.

Update implementation of Xsfvfnrclip, using return type as iterator.

gcc/ChangeLog:

	* config/riscv/genrvv-type-indexer.cc (expand_floattype): New func.
	(main): New type.
	* config/riscv/riscv-vector-builtins-types.def (DEF_RVV_XFQF_OPS): New def.
	(vint8mf8_t): Ditto.
	(vint8mf4_t): Ditto.
	(vint8mf2_t): Ditto.
	(vint8m1_t): Ditto.
	(vint8m2_t): Ditto.
	* config/riscv/riscv-vector-builtins.cc (DEF_RVV_XFQF_OPS): Ditto.
	(rvv_arg_type_info::get_xfqf_float_type): Ditto.
	* config/riscv/riscv-vector-builtins.def (xfqf_vector): Ditto.
	(xfqf_float): Ditto.
	* config/riscv/riscv-vector-builtins.h
	(struct rvv_arg_type_info): New function prototype.
	* config/riscv/sifive-vector.md: Update iterator.
	* config/riscv/vector-iterators.md: Ditto.

diff --git a/gcc/config/riscv/genrvv-type-indexer.cc b/gcc/config/riscv/genrvv-type-indexer.cc
index 9d2abaf487ac603a9ed6e066d3aeab8b14b0fea3..6de23cb6e1cb62d38f523a1aec781adb489c536e 100644 (file)
--- a/gcc/config/riscv/genrvv-type-indexer.cc
+++ b/gcc/config/riscv/genrvv-type-indexer.cc
@@ -164,6 +164,18 @@ floattype (unsigned sew, int lmul_log2)
   return mode.str ();
 }
 
+std::string
+expand_floattype (unsigned sew, int lmul_log2, unsigned nf)
+{
+  if (sew != 8 || nf!= 1
+      || (!valid_type (sew * 4, lmul_log2 + 2, /*float_t*/ true)))
+    return "INVALID";
+
+  std::stringstream mode;
+  mode << "vfloat" << sew * 4 << to_lmul (lmul_log2 + 2) << "_t";
+  return mode.str ();
+}
+
 std::string
 floattype (unsigned sew, int lmul_log2, unsigned nf)
 {
@@ -276,6 +288,7 @@ main (int argc, const char **argv)
       fprintf (fp, "  /*QLMUL1*/ INVALID,\n");
       fprintf (fp, "  /*QLMUL1_SIGNED*/ INVALID,\n");
       fprintf (fp, "  /*QLMUL1_UNSIGNED*/ INVALID,\n");
+      fprintf (fp, "  /*XFQF*/ INVALID,\n");
       for (unsigned eew : {8, 16, 32, 64})
        fprintf (fp, "  /*EEW%d_INTERPRET*/ INVALID,\n", eew);
 
@@ -384,6 +397,8 @@ main (int argc, const char **argv)
                     inttype (8, /*lmul_log2*/ 0, false).c_str ());
            fprintf (fp, "  /*QLMUL1_UNSIGNED*/ %s,\n",
                     inttype (8, /*lmul_log2*/ 0, true).c_str ());
+           fprintf (fp, "  /*XFQF*/ %s,\n",
+                    expand_floattype (sew, lmul_log2, nf).c_str ());
            for (unsigned eew : {8, 16, 32, 64})
              {
                if (eew == sew)
@@ -473,6 +488,7 @@ main (int argc, const char **argv)
                 bfloat16_wide_type (/*lmul_log2*/ 0).c_str ());
        fprintf (fp, "  /*QLMUL1_SIGNED*/ INVALID,\n");
        fprintf (fp, "  /*QLMUL1_UNSIGNED*/ INVALID,\n");
+       fprintf (fp, "  /*XFQF*/ INVALID,\n");
        for (unsigned eew : {8, 16, 32, 64})
          fprintf (fp, "  /*EEW%d_INTERPRET*/ INVALID,\n", eew);
 
@@ -558,6 +574,7 @@ main (int argc, const char **argv)
                   floattype (sew / 4, /*lmul_log2*/ 0).c_str ());
          fprintf (fp, "  /*QLMUL1_SIGNED*/ INVALID,\n");
          fprintf (fp, "  /*QLMUL1_UNSIGNED*/ INVALID,\n");
+         fprintf (fp, "  /*XFQF*/ INVALID,\n");
          for (unsigned eew : {8, 16, 32, 64})
            fprintf (fp, "  /*EEW%d_INTERPRET*/ INVALID,\n", eew);
 

diff --git a/gcc/config/riscv/riscv-vector-builtins-types.def b/gcc/config/riscv/riscv-vector-builtins-types.def
index 5d2dc8d42ed03bdace700089a61091f3f3a52192..6b98b93dfb60355b4cdc407a09420df877c677eb 100644 (file)
--- a/gcc/config/riscv/riscv-vector-builtins-types.def
+++ b/gcc/config/riscv/riscv-vector-builtins-types.def
@@ -363,6 +363,12 @@ along with GCC; see the file COPYING3. If not see
 #define DEF_RVV_QMACC_OPS(TYPE, REQUIRE)
 #endif
 
+/* Use "DEF_RVV_XFQF_OPS" macro include signed integer which will
+   be iterated and registered as intrinsic functions.  */
+#ifndef DEF_RVV_XFQF_OPS
+#define DEF_RVV_XFQF_OPS(TYPE, REQUIRE)
+#endif
+
 DEF_RVV_I_OPS (vint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
 DEF_RVV_I_OPS (vint8mf4_t, 0)
 DEF_RVV_I_OPS (vint8mf2_t, 0)
@@ -1451,6 +1457,12 @@ DEF_RVV_QMACC_OPS (vint32m2_t, 0)
 DEF_RVV_QMACC_OPS (vint32m4_t, 0)
 DEF_RVV_QMACC_OPS (vint32m8_t, 0)
 
+DEF_RVV_XFQF_OPS (vint8mf8_t, 0)
+DEF_RVV_XFQF_OPS (vint8mf4_t, 0)
+DEF_RVV_XFQF_OPS (vint8mf2_t, 0)
+DEF_RVV_XFQF_OPS (vint8m1_t, 0)
+DEF_RVV_XFQF_OPS (vint8m2_t, 0)
+
 #undef DEF_RVV_I_OPS
 #undef DEF_RVV_U_OPS
 #undef DEF_RVV_F_OPS
@@ -1506,3 +1518,4 @@ DEF_RVV_QMACC_OPS (vint32m8_t, 0)
 #undef DEF_RVV_CRYPTO_SEW64_OPS
 #undef DEF_RVV_F32_OPS
 #undef DEF_RVV_QMACC_OPS
+#undef DEF_RVV_XFQF_OPS

diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc
index 844b922efbf5432bee85140e3a1ae1cdfd69cc71..d2fe849c693eeffe90d6a399d382d5ca7e4e9cda 100644 (file)
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -551,6 +551,12 @@ static const rvv_type_info qmacc_ops[] = {
 #include "riscv-vector-builtins-types.def"
   {NUM_VECTOR_TYPES, 0}};
 
+/* A list of signed integer will be registered for intrinsic functions. */
+static const rvv_type_info xfqf_ops[] = {
+#define DEF_RVV_XFQF_OPS(TYPE, REQUIRE) {VECTOR_TYPE_##TYPE, REQUIRE},
+#include "riscv-vector-builtins-types.def"
+  {NUM_VECTOR_TYPES, 0}};
+
 static CONSTEXPR const rvv_arg_type_info rvv_arg_type_info_end
   = rvv_arg_type_info (NUM_BASE_TYPES);
 
@@ -720,7 +726,8 @@ static CONSTEXPR const rvv_arg_type_info shift_wv_args[]
      rvv_arg_type_info_end};
 
 static CONSTEXPR const rvv_arg_type_info clip_args[]
-  = {rvv_arg_type_info (RVV_BASE_vector), rvv_arg_type_info (RVV_BASE_scalar),
+  = {rvv_arg_type_info (RVV_BASE_xfqf_vector),
+     rvv_arg_type_info (RVV_BASE_xfqf_float),
      rvv_arg_type_info_end};
 
 /* A list of args for vector_type func (vector_type) function.  */
@@ -2549,17 +2556,17 @@ static CONSTEXPR const rvv_op_info i_narrow_shift_vwx_ops
 /* A static operand information for double demote type func (vector_type,
  * shift_type) function registration. */
 static CONSTEXPR const rvv_op_info u_clip_qf_ops
-  = {f32_ops,                                /* Types */
+  = {xfqf_ops,                               /* Types */
      OP_TYPE_none,                           /* Suffix */
-     rvv_arg_type_info (RVV_BASE_eew8_index), /* Return type */
+     rvv_arg_type_info (RVV_BASE_unsigned_vector), /* Return type */
      clip_args /* Args */};
 
 /* A static operand information for double demote type func (vector_type,
  * shift_type) function registration. */
 static CONSTEXPR const rvv_op_info i_clip_qf_ops
-  = {f32_ops,                                       /* Types */
+  = {xfqf_ops,                                      /* Types */
      OP_TYPE_none,                                  /* Suffix */
-     rvv_arg_type_info (RVV_BASE_signed_eew8_index), /* Return type */
+     rvv_arg_type_info (RVV_BASE_vector), /* Return type */
      clip_args /* Args */};
 
 /* A static operand information for double demote type func (vector_type,
@@ -3008,7 +3015,7 @@ static CONSTEXPR const function_type_info function_types[] = {
   QUAD_FIX_UNSIGNED, OCT_TRUNC, DOUBLE_TRUNC_SCALAR, DOUBLE_TRUNC_SIGNED,      \
   DOUBLE_TRUNC_UNSIGNED, DOUBLE_TRUNC_UNSIGNED_SCALAR,                         \
   DOUBLE_TRUNC_BFLOAT_SCALAR, DOUBLE_TRUNC_BFLOAT, DOUBLE_TRUNC_FLOAT, FLOAT,  \
-  LMUL1, WLMUL1, QLMUL1, QLMUL1_SIGNED, QLMUL1_UNSIGNED, EEW8_INTERPRET,       \
+  LMUL1, WLMUL1, QLMUL1, QLMUL1_SIGNED, QLMUL1_UNSIGNED, XFQF, EEW8_INTERPRET, \
   EEW16_INTERPRET, EEW32_INTERPRET, EEW64_INTERPRET, BOOL1_INTERPRET,          \
   BOOL2_INTERPRET, BOOL4_INTERPRET, BOOL8_INTERPRET, BOOL16_INTERPRET,         \
   BOOL32_INTERPRET, BOOL64_INTERPRET, SIGNED_EEW8_LMUL1_INTERPRET,             \
@@ -3060,6 +3067,7 @@ static CONSTEXPR const function_type_info function_types[] = {
     VECTOR_TYPE_##QLMUL1,                                                      \
     VECTOR_TYPE_##QLMUL1_SIGNED,                                               \
     VECTOR_TYPE_##QLMUL1_UNSIGNED,                                             \
+    VECTOR_TYPE_##XFQF,                                                        \
     VECTOR_TYPE_##EEW8_INTERPRET,                                              \
     VECTOR_TYPE_##EEW16_INTERPRET,                                             \
     VECTOR_TYPE_##EEW32_INTERPRET,                                             \
@@ -3579,6 +3587,19 @@ rvv_arg_type_info::get_scalar_const_ptr_type (vector_type_index type_idx) const
     return builtin_types[type_idx].scalar_const_ptr;
 }
 
+tree
+rvv_arg_type_info::get_xfqf_float_type (vector_type_index type_idx) const
+{
+  /* Convert vint8 types into float types.
+     Note:
+     - According to riscv-vector-builtins-types.def, the index of an unsigned
+       type is always one greater than its corresponding signed type.  */
+  if (type_idx >= VECTOR_TYPE_vint8mf8_t && type_idx <= VECTOR_TYPE_vuint8m2_t)
+    return builtin_types[VECTOR_TYPE_vfloat32m1_t].scalar;
+  else
+    return NULL_TREE;
+}
+
 vector_type_index
 rvv_arg_type_info::get_function_type_index (vector_type_index type_idx) const
 {

diff --git a/gcc/config/riscv/riscv-vector-builtins.def b/gcc/config/riscv/riscv-vector-builtins.def
index 338786121a35b5b37d0f68ea51673834a9bcfe45..3a62869a2b77dc51bb48b97464f6fa2253d08df8 100644 (file)
--- a/gcc/config/riscv/riscv-vector-builtins.def
+++ b/gcc/config/riscv/riscv-vector-builtins.def
@@ -75,7 +75,7 @@ along with GCC; see the file COPYING3.  If not see
   QUAD_FIX_UNSIGNED, OCT_TRUNC, DOUBLE_TRUNC_SCALAR, DOUBLE_TRUNC_SIGNED,      \
   DOUBLE_TRUNC_UNSIGNED, DOUBLE_TRUNC_UNSIGNED_SCALAR,                         \
   DOUBLE_TRUNC_BFLOAT_SCALAR, DOUBLE_TRUNC_BFLOAT, DOUBLE_TRUNC_FLOAT, FLOAT,  \
-  LMUL1, WLMUL1, QLMUL1, QLMUL1_SIGNED, QLMUL1_UNSIGNED, EEW8_INTERPRET,       \
+  LMUL1, WLMUL1, QLMUL1, QLMUL1_SIGNED, QLMUL1_UNSIGNED, XFQF, EEW8_INTERPRET, \
   EEW16_INTERPRET, EEW32_INTERPRET, EEW64_INTERPRET, BOOL1_INTERPRET,          \
   BOOL2_INTERPRET, BOOL4_INTERPRET, BOOL8_INTERPRET, BOOL16_INTERPRET,         \
   BOOL32_INTERPRET, BOOL64_INTERPRET, SIGNED_EEW8_LMUL1_INTERPRET,             \
@@ -700,6 +700,7 @@ DEF_RVV_BASE_TYPE (widen_lmul1_vector, get_vector_type (type_idx))
 DEF_RVV_BASE_TYPE (quad_lmul1_vector, get_vector_type (type_idx))
 DEF_RVV_BASE_TYPE (quad_lmul1_signed_vector, get_vector_type (type_idx))
 DEF_RVV_BASE_TYPE (quad_lmul1_unsigned_vector, get_vector_type (type_idx))
+DEF_RVV_BASE_TYPE (xfqf_vector, get_vector_type (type_idx))
 DEF_RVV_BASE_TYPE (eew8_interpret, get_vector_type (type_idx))
 DEF_RVV_BASE_TYPE (eew16_interpret, get_vector_type (type_idx))
 DEF_RVV_BASE_TYPE (eew32_interpret, get_vector_type (type_idx))
@@ -727,6 +728,7 @@ DEF_RVV_BASE_TYPE (vlmul_ext_x32, get_vector_type (type_idx))
 DEF_RVV_BASE_TYPE (vlmul_ext_x64, get_vector_type (type_idx))
 DEF_RVV_BASE_TYPE (size_ptr, build_pointer_type (size_type_node))
 DEF_RVV_BASE_TYPE (tuple_subpart, get_tuple_subpart_type (type_idx))
+DEF_RVV_BASE_TYPE (xfqf_float, get_xfqf_float_type (type_idx))
 
 DEF_RVV_VXRM_ENUM (RNU, VXRM_RNU)
 DEF_RVV_VXRM_ENUM (RNE, VXRM_RNE)

diff --git a/gcc/config/riscv/riscv-vector-builtins.h b/gcc/config/riscv/riscv-vector-builtins.h
index 3fa5381694a9f69cb9376f12ba3920f44d37478f..42ba90577079364c835117957f5510ed0f18c8ce 100644 (file)
--- a/gcc/config/riscv/riscv-vector-builtins.h
+++ b/gcc/config/riscv/riscv-vector-builtins.h
@@ -296,6 +296,7 @@ struct rvv_arg_type_info
   tree get_vector_type (vector_type_index) const;
   tree get_tree_type (vector_type_index) const;
   tree get_tuple_subpart_type (vector_type_index) const;
+  tree get_xfqf_float_type (vector_type_index) const;
 };
 
 /* Static information for each operand.  */

diff --git a/gcc/config/riscv/sifive-vector.md b/gcc/config/riscv/sifive-vector.md
index 0c9018a45cefc3713d4b354649ce0b08eab9b8bc..2975b1e7a47a9580d3748fcaa4491a289736e820 100644 (file)
--- a/gcc/config/riscv/sifive-vector.md
+++ b/gcc/config/riscv/sifive-vector.md
@@ -164,8 +164,8 @@
    (set_attr "mode" "<MODE>")])
 
 (define_insn "@pred_sf_vfnrclip<v_su><mode>_x_f_qf"
-  [(set (match_operand:<SF_XFQF> 0 "register_operand"        "=vd, vd, vr, vr")
-       (if_then_else:<SF_XFQF>
+  [(set (match_operand:SF_XF 0 "register_operand"        "=vd, vd, vr, vr")
+       (if_then_else:SF_XF
          (unspec:<VM>
            [(match_operand:<VM> 1 "vector_mask_operand"     " vm, vm,Wc1,Wc1")
             (match_operand 5 "vector_length_operand"        " rK, rK, rK, rK")
@@ -174,10 +174,10 @@
             (match_operand 8 "const_int_operand"            "  i,  i,  i,  i")
             (reg:SI VL_REGNUM)
             (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-         (unspec:<SF_XFQF>
+         (unspec:SF_XF
            [(match_operand:SF 4 "register_operand"          "  f,  f,  f,  f")
-            (match_operand:SF_VF 3 "register_operand"       " vr, vr, vr, vr")] SF_VFNRCLIP)
-         (match_operand:<SF_XFQF> 2 "vector_merge_operand"  " vu,  0, vu,  0")))]
+            (match_operand:<SF_XFQF> 3 "register_operand"       " vr, vr, vr, vr")] SF_VFNRCLIP)
+         (match_operand:SF_XF 2 "vector_merge_operand"  " vu,  0, vu,  0")))]
   "TARGET_VECTOR && TARGET_XSFVFNRCLIPXFQF"
   "sf.vfnrclip.x<v_su>.f.qf\t%0,%3,%4%p1"
   [(set_attr "type" "sf_vfnrclip")

diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index 3c8da66cebf465cb2e76f4979464eea2dc0eef8d..c1bd7397441d9f316343cddb5ff272f6becf9f77 100644 (file)
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -4853,24 +4853,23 @@
   (RVVM1SI "rvvm1qi")
 ])
 
-(define_mode_iterator SF_VF [
-  (RVVM8SF "TARGET_VECTOR_ELEN_FP_32") (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") (RVVM2SF "TARGET_VECTOR_ELEN_FP_32")
-  (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
+(define_mode_iterator SF_XF [
+  RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32")
 ])
 
 
 (define_mode_attr SF_XFQF [
-  (RVVMF2SF "RVVMF8QI")
-  (RVVM1SF "RVVMF4QI")
-  (RVVM2SF "RVVMF2QI")
-  (RVVM4SF "RVVM1QI")
-  (RVVM8SF "RVVM2QI")
+  (RVVMF8QI "RVVMF2SF")
+  (RVVMF4QI "RVVM1SF")
+  (RVVMF2QI "RVVM2SF")
+  (RVVM1QI  "RVVM4SF")
+  (RVVM2QI  "RVVM8SF")
 ])
 
 (define_mode_attr sf_xfqf [
-  (RVVMF2SF "rvvmf8qi")
-  (RVVM1SF "rvvmf4qi")
-  (RVVM2SF "rvvmf2qi")
-  (RVVM4SF "rvvm1qi")
-  (RVVM8SF "rvvm2qi")
+  (RVVMF8QI "rvvmf2sf")
+  (RVVMF4QI "rvvm1sf")
+  (RVVMF2QI "rvvm2sf")
+  (RVVM1QI  "rvvm4sf")
+  (RVVM2QI  "rvvm8sf")
 ])