RISC-V: KVM: Fix to allow hpmcounter31 from the guest

[ Upstream commit 5aa09297a3dcc798d038bd7436f8c90f664045a6 ]

The csr_fun defines a count parameter which defines the total number
CSRs emulated in KVM starting from the base. This value should be
equal to total number of counters possible for trap/emulation (32).

Fixes: a9ac6c37521f ("RISC-V: KVM: Implement trap & emulate for hpmcounters")
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20240816-kvm_pmu_fixes-v1-2-cdfce386dd93@rivosinc.com
Signed-off-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/arch/riscv/include/asm/kvm_vcpu_pmu.h b/arch/riscv/include/asm/kvm_vcpu_pmu.h
index 6823271bce322cb3f1f0fa963ce55d06cd8304d7..a50a1d23523fea1573b8efe12c935b3b54b24f62 100644 (file)
--- a/arch/riscv/include/asm/kvm_vcpu_pmu.h
+++ b/arch/riscv/include/asm/kvm_vcpu_pmu.h
@@ -58,11 +58,11 @@ struct kvm_pmu {
 
 #if defined(CONFIG_32BIT)
 #define KVM_RISCV_VCPU_HPMCOUNTER_CSR_FUNCS \
-{.base = CSR_CYCLEH,   .count = 31,    .func = kvm_riscv_vcpu_pmu_read_hpm }, \
-{.base = CSR_CYCLE,    .count = 31,    .func = kvm_riscv_vcpu_pmu_read_hpm },
+{.base = CSR_CYCLEH,   .count = 32,    .func = kvm_riscv_vcpu_pmu_read_hpm }, \
+{.base = CSR_CYCLE,    .count = 32,    .func = kvm_riscv_vcpu_pmu_read_hpm },
 #else
 #define KVM_RISCV_VCPU_HPMCOUNTER_CSR_FUNCS \
-{.base = CSR_CYCLE,    .count = 31,    .func = kvm_riscv_vcpu_pmu_read_hpm },
+{.base = CSR_CYCLE,    .count = 32,    .func = kvm_riscv_vcpu_pmu_read_hpm },
 #endif
 
 int kvm_riscv_vcpu_pmu_incr_fw(struct kvm_vcpu *vcpu, unsigned long fid);