+From c436e3e9c265a1f012008ef5da6fd28863f8025c Mon Sep 17 00:00:00 2001
From: Devi Priya <quic_devipriy@quicinc.com>
-Date: Thu, 5 Oct 2023 21:35:47 +0530
-Subject: [PATCH] pwm: driver for qualcomm ipq6018 pwm block
+Date: Mon, 6 Apr 2026 22:24:39 +0200
+Subject: [PATCH] pwm: Driver for qualcomm ipq6018 pwm block
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
Driver for the PWM block in Qualcomm IPQ6018 line of SoCs. Based on
driver from downstream Codeaurora kernel tree. Removed support for older
(V1) variants because I have no access to that hardware.
-Tested on IPQ6010 based hardware.
+Tested on IPQ5018 and IPQ6010 based hardware.
Co-developed-by: Baruch Siach <baruch.siach@siklu.com>
Signed-off-by: Baruch Siach <baruch.siach@siklu.com>
Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
+Reviewed-by: Bjorn Andersson <andersson@kernel.org>
+Signed-off-by: George Moussalem <george.moussalem@outlook.com>
+Link: https://patch.msgid.link/20260406-ipq-pwm-v21-2-6ed1e868e4c2@outlook.com
+[ukleinek: Fixed a few nitpicks as agreed on the mailing list]
+Signed-off-by: Uwe Kleine-König <ukleinek@kernel.org>
---
drivers/pwm/Kconfig | 12 ++
drivers/pwm/Makefile | 1 +
- drivers/pwm/pwm-ipq.c | 282 ++++++++++++++++++++++++++++++++++++++++++
- 3 files changed, 295 insertions(+)
+ drivers/pwm/pwm-ipq.c | 263 ++++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 276 insertions(+)
create mode 100644 drivers/pwm/pwm-ipq.c
--- a/drivers/pwm/Kconfig
obj-$(CONFIG_PWM_KEEMBAY) += pwm-keembay.o
--- /dev/null
+++ b/drivers/pwm/pwm-ipq.c
-@@ -0,0 +1,261 @@
+@@ -0,0 +1,263 @@
+// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
+/*
+ * Copyright (c) 2016-2017, 2020 The Linux Foundation. All rights reserved.
++ *
++ * Limitations:
++ * - The PWM controller has no publicly available datasheet.
++ * - Each of the four channels is programmed via two 32-bit registers
++ * (REG0 and REG1 at 8-byte stride).
++ * - Period and duty-cycle reconfiguration is fully atomic: new divider,
++ * pre-divider, and high-duration values are latched by setting the
++ * UPDATE bit (bit 30 in REG1). The hardware applies the new settings
++ * at the beginning of the next period without disabling the output,
++ * so the currently running period is always completed.
++ * - On disable (clearing the ENABLE bit 31 in REG1), the hardware
++ * finishes the current period before stopping the output. The pin
++ * is then driven to the inactive (low) level.
++ * - Upon disabling, the hardware resets the pre-divider (PRE_DIV) and divider
++ * fields (PWM_DIV) in REG0 and REG1 to 0x0000 and 0x0001 respectively.
++ * - Only normal polarity is supported.
+ */
+
+#include <linux/module.h>
+#include <linux/bitfield.h>
+#include <linux/units.h>
+
-+/* The frequency range supported is 1 Hz to clock rate */
++/* The frequency range supported is 1 Hz to 100 Mhz (clock rate) */
+#define IPQ_PWM_MAX_PERIOD_NS ((u64)NSEC_PER_SEC)
-+
-+/*
-+ * The max value specified for each field is based on the number of bits
-+ * in the pwm control register for that field
-+ */
-+#define IPQ_PWM_MAX_DIV 0xFFFF
++#define IPQ_PWM_MIN_PERIOD_NS 10
+
+/*
+ * Two 32-bit registers for each PWM: REG0, and REG1.
+#define IPQ_PWM_REG1_PRE_DIV GENMASK(15, 0)
+/*
+ * Enable bit is set to enable output toggling in pwm device.
-+ * Update bit is set to reflect the changed divider and high duration
-+ * values in register.
++ * Update bit is set to trigger the change and is unset automatically
++ * to reflect the changed divider and high duration values in register.
+ */
+#define IPQ_PWM_REG1_UPDATE BIT(30)
+#define IPQ_PWM_REG1_ENABLE BIT(31)
+
++/*
++ * The max value specified for each field is based on the number of bits
++ * in the pwm control register for that field (16-bit)
++ */
++#define IPQ_PWM_MAX_DIV FIELD_MAX(IPQ_PWM_REG0_PWM_DIV)
++
+struct ipq_pwm_chip {
-+ struct clk *clk;
+ void __iomem *mem;
++ unsigned long clk_rate;
+};
+
+static struct ipq_pwm_chip *ipq_pwm_from_chip(struct pwm_chip *chip)
+ writel(val, ipq_chip->mem + off);
+}
+
-+static void config_div_and_duty(struct pwm_device *pwm, unsigned int pre_div,
-+ unsigned int pwm_div, unsigned long rate, u64 duty_ns,
-+ bool enable)
-+{
-+ unsigned long hi_dur;
-+ unsigned long val = 0;
-+
-+ /*
-+ * high duration = pwm duty * (pwm div + 1)
-+ * pwm duty = duty_ns / period_ns
-+ */
-+ hi_dur = div64_u64(duty_ns * rate, (pre_div + 1) * NSEC_PER_SEC);
-+
-+ val = FIELD_PREP(IPQ_PWM_REG0_HI_DURATION, hi_dur) |
-+ FIELD_PREP(IPQ_PWM_REG0_PWM_DIV, pwm_div);
-+ ipq_pwm_reg_write(pwm, IPQ_PWM_REG0, val);
-+
-+ val = FIELD_PREP(IPQ_PWM_REG1_PRE_DIV, pre_div);
-+ ipq_pwm_reg_write(pwm, IPQ_PWM_REG1, val);
-+
-+ /* PWM enable toggle needs a separate write to REG1 */
-+ val |= IPQ_PWM_REG1_UPDATE;
-+ if (enable)
-+ val |= IPQ_PWM_REG1_ENABLE;
-+ ipq_pwm_reg_write(pwm, IPQ_PWM_REG1, val);
-+}
-+
+static int ipq_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+ const struct pwm_state *state)
+{
+ struct ipq_pwm_chip *ipq_chip = ipq_pwm_from_chip(chip);
-+ unsigned int pre_div, pwm_div, best_pre_div, best_pwm_div;
-+ unsigned long rate = clk_get_rate(ipq_chip->clk);
-+ u64 period_ns, duty_ns, period_rate;
-+ u64 min_diff;
++ unsigned int pre_div, pwm_div;
++ u64 period_ns, duty_ns;
++ unsigned long val = 0;
++ unsigned long hi_dur;
++
++ if (!state->enabled) {
++ /* clear IPQ_PWM_REG1_ENABLE */
++ ipq_pwm_reg_write(pwm, IPQ_PWM_REG1, IPQ_PWM_REG1_UPDATE);
++ return 0;
++ }
+
+ if (state->polarity != PWM_POLARITY_NORMAL)
+ return -EINVAL;
+
-+ if (state->period < DIV64_U64_ROUND_UP(NSEC_PER_SEC, rate))
++ /*
++ * Check the upper and lower bounds for the period as per
++ * hardware limits
++ */
++ if (state->period < IPQ_PWM_MIN_PERIOD_NS)
+ return -ERANGE;
-+
+ period_ns = min(state->period, IPQ_PWM_MAX_PERIOD_NS);
+ duty_ns = min(state->duty_cycle, period_ns);
+
+ /*
-+ * period_ns is 1G or less. As long as rate is less than 16 GHz,
-+ * period_rate does not overflow. Make that explicit.
++ * Pick the maximal value for PWM_DIV that still allows a
++ * 100% relative duty cycle. This allows a fine grained
++ * selection of duty cycles.
+ */
-+ if ((unsigned long long)rate > 16ULL * GIGA)
-+ return -EINVAL;
-+ period_rate = period_ns * rate;
-+ best_pre_div = IPQ_PWM_MAX_DIV;
-+ best_pwm_div = IPQ_PWM_MAX_DIV;
++ pwm_div = IPQ_PWM_MAX_DIV - 1;
++
+ /*
-+ * We don't need to consider pre_div values smaller than
-+ *
-+ * period_rate
-+ * pre_div_min := ------------------------------------
-+ * NSEC_PER_SEC * (IPQ_PWM_MAX_DIV + 1)
-+ *
-+ * because pre_div = pre_div_min results in a better
-+ * approximation.
++ * although mul_u64_u64_div_u64 returns a u64, in practice it
++ * won't overflow due to above constraints. Take the max period
++ * of 10^9 (NSEC_PER_SEC) and the pwm_div + 1 (IPQ_PWM_MAX_DIV)
++ * 10^9 * 10^8
++ * ------------- => which fits well into a 32-bit unsigned int.
++ * 10^9 * 65,535
+ */
-+ pre_div = div64_u64(period_rate,
-+ (u64)NSEC_PER_SEC * (IPQ_PWM_MAX_DIV + 1));
-+ min_diff = period_rate;
-+
-+ for (; pre_div <= IPQ_PWM_MAX_DIV; pre_div++) {
-+ u64 remainder;
-+
-+ pwm_div = div64_u64_rem(period_rate,
-+ (u64)NSEC_PER_SEC * (pre_div + 1), &remainder);
-+ /* pwm_div is unsigned; the check below catches underflow */
-+ pwm_div--;
-+
-+ /*
-+ * Swapping values for pre_div and pwm_div produces the same
-+ * period length. So we can skip all settings with pre_div >
-+ * pwm_div which results in bigger constraints for selecting
-+ * the duty_cycle than with the two values swapped.
-+ */
-+ if (pre_div > pwm_div)
-+ break;
-+
-+ /*
-+ * Make sure we can do 100% duty cycle where
-+ * hi_dur == pwm_div + 1
-+ */
-+ if (pwm_div > IPQ_PWM_MAX_DIV - 1)
-+ continue;
-+
-+ if (remainder < min_diff) {
-+ best_pre_div = pre_div;
-+ best_pwm_div = pwm_div;
-+ min_diff = remainder;
-+
-+ if (min_diff == 0) /* bingo */
-+ break;
-+ }
-+ }
++ pre_div = mul_u64_u64_div_u64(period_ns, ipq_chip->clk_rate,
++ (u64)NSEC_PER_SEC * (pwm_div + 1));
++
++ if (!pre_div)
++ return -ERANGE;
++
++ pre_div -= 1;
++
++ if (pre_div > IPQ_PWM_MAX_DIV)
++ pre_div = IPQ_PWM_MAX_DIV;
++
++ /* pwm duty = HI_DUR * (PRE_DIV + 1) / clk_rate */
++ hi_dur = mul_u64_u64_div_u64(duty_ns, ipq_chip->clk_rate,
++ (u64)NSEC_PER_SEC * (pre_div + 1));
++
++ val = FIELD_PREP(IPQ_PWM_REG0_HI_DURATION, hi_dur) |
++ FIELD_PREP(IPQ_PWM_REG0_PWM_DIV, pwm_div);
++ ipq_pwm_reg_write(pwm, IPQ_PWM_REG0, val);
+
-+ /* config divider values for the closest possible frequency */
-+ config_div_and_duty(pwm, best_pre_div, best_pwm_div,
-+ rate, duty_ns, state->enabled);
++ val = FIELD_PREP(IPQ_PWM_REG1_PRE_DIV, pre_div);
++ ipq_pwm_reg_write(pwm, IPQ_PWM_REG1, val);
++
++ /* PWM enable toggle needs a separate write to REG1 */
++ val |= IPQ_PWM_REG1_UPDATE | IPQ_PWM_REG1_ENABLE;
++ ipq_pwm_reg_write(pwm, IPQ_PWM_REG1, val);
+
+ return 0;
+}
+ struct pwm_state *state)
+{
+ struct ipq_pwm_chip *ipq_chip = ipq_pwm_from_chip(chip);
-+ unsigned long rate = clk_get_rate(ipq_chip->clk);
+ unsigned int pre_div, pwm_div, hi_dur;
+ u64 effective_div, hi_div;
+ u32 reg0, reg1;
+
-+ reg0 = ipq_pwm_reg_read(pwm, IPQ_PWM_REG0);
+ reg1 = ipq_pwm_reg_read(pwm, IPQ_PWM_REG1);
++ state->enabled = reg1 & IPQ_PWM_REG1_ENABLE;
++
++ if (!state->enabled)
++ return 0;
++
++ reg0 = ipq_pwm_reg_read(pwm, IPQ_PWM_REG0);
+
+ state->polarity = PWM_POLARITY_NORMAL;
-+ state->enabled = reg1 & IPQ_PWM_REG1_ENABLE;
+
+ pwm_div = FIELD_GET(IPQ_PWM_REG0_PWM_DIV, reg0);
+ hi_dur = FIELD_GET(IPQ_PWM_REG0_HI_DURATION, reg0);
+ pre_div = FIELD_GET(IPQ_PWM_REG1_PRE_DIV, reg1);
+
-+ /* No overflow here, both pre_div and pwm_div <= 0xffff */
-+ effective_div = (u64)(pre_div + 1) * (pwm_div + 1);
-+ state->period = DIV64_U64_ROUND_UP(effective_div * NSEC_PER_SEC, rate);
++ effective_div = (u64)(pwm_div + 1) * (pre_div + 1);
++
++ /*
++ * effective_div <= 0x100000000, so the multiplication doesn't overflow.
++ */
++ state->period = DIV64_U64_ROUND_UP(effective_div * NSEC_PER_SEC,
++ ipq_chip->clk_rate);
+
+ hi_div = hi_dur * (pre_div + 1);
-+ state->duty_cycle = DIV64_U64_ROUND_UP(hi_div * NSEC_PER_SEC, rate);
++ state->duty_cycle = DIV64_U64_ROUND_UP(hi_div * NSEC_PER_SEC,
++ ipq_chip->clk_rate);
++
++ /*
++ * ensure a valid config is passed back to PWM core in case duty_cycle
++ * is > period (>100%)
++ */
++ state->duty_cycle = min(state->duty_cycle, state->period);
+
+ return 0;
+}
+
+static int ipq_pwm_probe(struct platform_device *pdev)
+{
-+ struct pwm_chip *chip;
-+ struct ipq_pwm_chip *pwm;
+ struct device *dev = &pdev->dev;
++ struct ipq_pwm_chip *pwm;
++ struct pwm_chip *chip;
++ struct clk *clk;
+ int ret;
+
+ chip = devm_pwmchip_alloc(dev, 4, sizeof(*pwm));
+ pwm->mem = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(pwm->mem))
+ return dev_err_probe(dev, PTR_ERR(pwm->mem),
-+ "regs map failed");
++ "Failed to acquire resource\n");
++
++ clk = devm_clk_get_enabled(dev, NULL);
++ if (IS_ERR(clk))
++ return dev_err_probe(dev, PTR_ERR(clk),
++ "Failed to get clock\n");
+
-+ pwm->clk = devm_clk_get_enabled(dev, NULL);
-+ if (IS_ERR(pwm->clk))
-+ return dev_err_probe(dev, PTR_ERR(pwm->clk),
-+ "failed to get clock");
++ ret = devm_clk_rate_exclusive_get(dev, clk);
++ if (ret)
++ return dev_err_probe(dev, ret, "Failed to lock clock rate\n");
++
++ pwm->clk_rate = clk_get_rate(clk);
++ if (!pwm->clk_rate)
++ return dev_err_probe(dev, -EINVAL, "Failed due to clock rate being zero\n");
+
+ chip->ops = &ipq_pwm_ops;
+
+ ret = devm_pwmchip_add(dev, chip);
+ if (ret < 0)
-+ dev_err_probe(dev, ret, "devm_pwmchip_add() failed\n");
++ return dev_err_probe(dev, ret, "Failed to add pwm chip\n");
+
-+ return ret;
++ return 0;
+}
+
+static const struct of_device_id pwm_ipq_dt_match[] = {
+
+module_platform_driver(ipq_pwm_driver);
+
-+MODULE_LICENSE("Dual BSD/GPL");
++MODULE_LICENSE("GPL");
projects / thirdparty / openwrt.git / commitdiff
