--- /dev/null
+From f965b68188ab59a40a421ced1b05a2fea638465c Mon Sep 17 00:00:00 2001
+From: Colin Xu <colin.xu@intel.com>
+Date: Fri, 8 May 2020 14:05:06 +0800
+Subject: drm/i915/gvt: Init DPLL/DDI vreg for virtual display instead of inheritance.
+
+From: Colin Xu <colin.xu@intel.com>
+
+commit f965b68188ab59a40a421ced1b05a2fea638465c upstream.
+
+Init value of some display vregs rea inherited from host pregs. When
+host display in different status, i.e. all monitors unpluged, different
+display configurations, etc., GVT virtual display setup don't consistent
+thus may lead to guest driver consider display goes malfunctional.
+
+The added init vreg values are based on PRMs and fixed by calcuation
+from current configuration (only PIPE_A) and the virtual EDID.
+
+Fixes: 04d348ae3f0a ("drm/i915/gvt: vGPU display virtualization")
+Acked-by: Zhenyu Wang <zhenyuw@linux.intel.com>
+Signed-off-by: Colin Xu <colin.xu@intel.com>
+Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
+Link: http://patchwork.freedesktop.org/patch/msgid/20200508060506.216250-1-colin.xu@intel.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/i915/gvt/display.c | 49 +++++++++++++++++++++++++++++++++----
+ 1 file changed, 44 insertions(+), 5 deletions(-)
+
+--- a/drivers/gpu/drm/i915/gvt/display.c
++++ b/drivers/gpu/drm/i915/gvt/display.c
+@@ -207,14 +207,41 @@ static void emulate_monitor_status_chang
+ SKL_FUSE_PG_DIST_STATUS(SKL_PG0) |
+ SKL_FUSE_PG_DIST_STATUS(SKL_PG1) |
+ SKL_FUSE_PG_DIST_STATUS(SKL_PG2);
+- vgpu_vreg_t(vgpu, LCPLL1_CTL) |=
+- LCPLL_PLL_ENABLE |
+- LCPLL_PLL_LOCK;
+- vgpu_vreg_t(vgpu, LCPLL2_CTL) |= LCPLL_PLL_ENABLE;
+-
++ /*
++ * Only 1 PIPE enabled in current vGPU display and PIPE_A is
++ * tied to TRANSCODER_A in HW, so it's safe to assume PIPE_A,
++ * TRANSCODER_A can be enabled. PORT_x depends on the input of
++ * setup_virtual_dp_monitor, we can bind DPLL0 to any PORT_x
++ * so we fixed to DPLL0 here.
++ * Setup DPLL0: DP link clk 1620 MHz, non SSC, DP Mode
++ */
++ vgpu_vreg_t(vgpu, DPLL_CTRL1) =
++ DPLL_CTRL1_OVERRIDE(DPLL_ID_SKL_DPLL0);
++ vgpu_vreg_t(vgpu, DPLL_CTRL1) |=
++ DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, DPLL_ID_SKL_DPLL0);
++ vgpu_vreg_t(vgpu, LCPLL1_CTL) =
++ LCPLL_PLL_ENABLE | LCPLL_PLL_LOCK;
++ vgpu_vreg_t(vgpu, DPLL_STATUS) = DPLL_LOCK(DPLL_ID_SKL_DPLL0);
++ /*
++ * Golden M/N are calculated based on:
++ * 24 bpp, 4 lanes, 154000 pixel clk (from virtual EDID),
++ * DP link clk 1620 MHz and non-constant_n.
++ * TODO: calculate DP link symbol clk and stream clk m/n.
++ */
++ vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = 63 << TU_SIZE_SHIFT;
++ vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e;
++ vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000;
++ vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e;
++ vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000;
+ }
+
+ if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
++ vgpu_vreg_t(vgpu, DPLL_CTRL2) &=
++ ~DPLL_CTRL2_DDI_CLK_OFF(PORT_B);
++ vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
++ DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_B);
++ vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
++ DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_B);
+ vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED;
+ vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
+ ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
+@@ -235,6 +262,12 @@ static void emulate_monitor_status_chang
+ }
+
+ if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
++ vgpu_vreg_t(vgpu, DPLL_CTRL2) &=
++ ~DPLL_CTRL2_DDI_CLK_OFF(PORT_C);
++ vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
++ DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_C);
++ vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
++ DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_C);
+ vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT;
+ vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
+ ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
+@@ -255,6 +288,12 @@ static void emulate_monitor_status_chang
+ }
+
+ if (intel_vgpu_has_monitor_on_port(vgpu, PORT_D)) {
++ vgpu_vreg_t(vgpu, DPLL_CTRL2) &=
++ ~DPLL_CTRL2_DDI_CLK_OFF(PORT_D);
++ vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
++ DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_D);
++ vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
++ DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_D);
+ vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT;
+ vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
+ ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
--- /dev/null
+From bc850943486887e3859597a266767f95db90aa72 Mon Sep 17 00:00:00 2001
+From: Chris Wilson <chris@chris-wilson.co.uk>
+Date: Wed, 6 May 2020 17:21:36 +0100
+Subject: drm/i915: Propagate error from completed fences
+
+From: Chris Wilson <chris@chris-wilson.co.uk>
+
+commit bc850943486887e3859597a266767f95db90aa72 upstream.
+
+We need to preserve fatal errors from fences that are being terminated
+as we hook them up.
+
+Fixes: ef4688497512 ("drm/i915: Propagate fence errors")
+Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
+Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
+Cc: Matthew Auld <matthew.auld@intel.com>
+Reviewed-by: Matthew Auld <matthew.auld@intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20200506162136.3325-1-chris@chris-wilson.co.uk
+(cherry picked from commit 24fe5f2ab2478053d50a3bc629ada895903a5cbc)
+Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/i915/i915_request.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/i915/i915_request.c
++++ b/drivers/gpu/drm/i915/i915_request.c
+@@ -947,8 +947,10 @@ i915_request_await_request(struct i915_r
+ GEM_BUG_ON(to == from);
+ GEM_BUG_ON(to->timeline == from->timeline);
+
+- if (i915_request_completed(from))
++ if (i915_request_completed(from)) {
++ i915_sw_fence_set_error_once(&to->submit, from->fence.error);
+ return 0;
++ }
+
+ if (to->engine->schedule) {
+ ret = i915_sched_node_add_dependency(&to->sched,