--- /dev/null
+From 8c91bc3d44dfef8284af384877fbe61117e8b7d1 Mon Sep 17 00:00:00 2001
+From: Sergey Shtylyov <s.shtylyov@omprussia.ru>
+Date: Sun, 28 Feb 2021 23:25:43 +0300
+Subject: sh_eth: fix TRSCER mask for SH771x
+
+From: Sergey Shtylyov <s.shtylyov@omprussia.ru>
+
+commit 8c91bc3d44dfef8284af384877fbe61117e8b7d1 upstream.
+
+According to the SH7710, SH7712, SH7713 Group User's Manual: Hardware,
+Rev. 3.00, the TRSCER register actually has only bit 7 valid (and named
+differently), with all the other bits reserved. Apparently, this was not
+the case with some early revisions of the manual as we have the other
+bits declared (and set) in the original driver. Follow the suit and add
+the explicit sh_eth_cpu_data::trscer_err_mask initializer for SH771x...
+
+Fixes: 86a74ff21a7a ("net: sh_eth: add support for Renesas SuperH Ethernet")
+Signed-off-by: Sergey Shtylyov <s.shtylyov@omprussia.ru>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/net/ethernet/renesas/sh_eth.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/drivers/net/ethernet/renesas/sh_eth.c
++++ b/drivers/net/ethernet/renesas/sh_eth.c
+@@ -935,6 +935,9 @@ static struct sh_eth_cpu_data sh771x_dat
+ EESIPR_CEEFIP | EESIPR_CELFIP |
+ EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
+ EESIPR_PREIP | EESIPR_CERFIP,
++
++ .trscer_err_mask = DESC_I_RINT8,
++
+ .tsu = 1,
+ .dual_port = 1,
+ };