AMD/Xilinx/FPGA changes for v2026.07-rc1 v3. The biggest part is new
pcie driver for Versal Gen 2 SOC. Others are small fixes and
adjustments.
versal2:
- Wire PCIe IP
cmd/fpga:
- Fix loadb help text guarding
- Add support for skipping fpga ID check
zynqmp:
- Describe missing devices/IDs
- Fix issue around zu63dr_SE
clk/versal:
- Fix out-of-bounds parent id for DUMMY_PARENT
net/gem:
- Add support for 10GBE
- Clear stale speed bits in NWCFG
net/axi_emac:
- Filter out broadcast and multicast packets
pci:
- Add driver for AMD PCIe IP based on DesignWare core