return (ctz16(addr >> 11) << 11) | (addr & 0x7ff);
}
-static void raven_pci_io_write(void *opaque, hwaddr addr,
- uint64_t val, unsigned int size)
+static void raven_mmcfg_write(void *opaque, hwaddr addr, uint64_t val,
+ unsigned int size)
{
PREPPCIState *s = opaque;
PCIHostState *phb = PCI_HOST_BRIDGE(s);
pci_data_write(phb->bus, raven_idsel_to_addr(addr), val, size);
}
-static uint64_t raven_pci_io_read(void *opaque, hwaddr addr,
- unsigned int size)
+static uint64_t raven_mmcfg_read(void *opaque, hwaddr addr, unsigned int size)
{
PREPPCIState *s = opaque;
PCIHostState *phb = PCI_HOST_BRIDGE(s);
return pci_data_read(phb->bus, raven_idsel_to_addr(addr), size);
}
-static const MemoryRegionOps raven_pci_io_ops = {
- .read = raven_pci_io_read,
- .write = raven_pci_io_write,
+static const MemoryRegionOps raven_mmcfg_ops = {
+ .read = raven_mmcfg_read,
+ .write = raven_mmcfg_write,
.endianness = DEVICE_LITTLE_ENDIAN,
};
"pci-conf-data", 4);
memory_region_add_subregion(&s->pci_io, 0xcfc, &h->data_mem);
- memory_region_init_io(&h->mmcfg, OBJECT(s), &raven_pci_io_ops, s,
- "pciio", 0x00400000);
+ memory_region_init_io(&h->mmcfg, OBJECT(s), &raven_mmcfg_ops, s,
+ "pci-mmcfg", 0x00400000);
memory_region_add_subregion(address_space_mem, 0x80800000, &h->mmcfg);
memory_region_init_io(&s->pci_intack, OBJECT(s), &raven_intack_ops, s,