+++ /dev/null
-From 7e70a5189bac48492d93da79cafced4d5ef44e16 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Wed, 8 Jun 2022 00:35:32 +0300
-Subject: phy: qcom-qmp: create copies of QMP PHY driver
-
-From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-
-[ Upstream commit 94a407cc17a445ddb3f7315cee0b0916d35d177c ]
-
-In order to split and cleanup the single monstrous QMP PHY driver,
-create blind copies of the current file. They will be used for:
-- PCIe (and a separate msm8996 PCIe PHY driver)
-- UFS
-- USB
-- Combo DP + USB
-
-Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> # UFS, PCIe and USB on SC8180X
-Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Link: https://lore.kernel.org/r/20220607213203.2819885-2-dmitry.baryshkov@linaro.org
-Signed-off-by: Vinod Koul <vkoul@kernel.org>
-Stable-dep-of: 4382d518d188 ("phy: qcom-qmp-combo: disable runtime PM on unbind")
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 6350 +++++++++++++++++
- .../phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 6350 +++++++++++++++++
- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 6350 +++++++++++++++++
- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 6350 +++++++++++++++++
- drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 6350 +++++++++++++++++
- 5 files changed, 31750 insertions(+)
- create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-combo.c
- create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
- create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
- create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
- create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-usb.c
-
-diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
-new file mode 100644
-index 000000000000..c7309e981bfb
---- /dev/null
-+++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
-@@ -0,0 +1,6350 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/clk-provider.h>
-+#include <linux/delay.h>
-+#include <linux/err.h>
-+#include <linux/io.h>
-+#include <linux/iopoll.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/of_device.h>
-+#include <linux/of_address.h>
-+#include <linux/phy/phy.h>
-+#include <linux/platform_device.h>
-+#include <linux/regulator/consumer.h>
-+#include <linux/reset.h>
-+#include <linux/slab.h>
-+
-+#include <dt-bindings/phy/phy.h>
-+
-+#include "phy-qcom-qmp.h"
-+
-+/* QPHY_SW_RESET bit */
-+#define SW_RESET BIT(0)
-+/* QPHY_POWER_DOWN_CONTROL */
-+#define SW_PWRDN BIT(0)
-+#define REFCLK_DRV_DSBL BIT(1)
-+/* QPHY_START_CONTROL bits */
-+#define SERDES_START BIT(0)
-+#define PCS_START BIT(1)
-+#define PLL_READY_GATE_EN BIT(3)
-+/* QPHY_PCS_STATUS bit */
-+#define PHYSTATUS BIT(6)
-+#define PHYSTATUS_4_20 BIT(7)
-+/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */
-+#define PCS_READY BIT(0)
-+
-+/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
-+/* DP PHY soft reset */
-+#define SW_DPPHY_RESET BIT(0)
-+/* mux to select DP PHY reset control, 0:HW control, 1: software reset */
-+#define SW_DPPHY_RESET_MUX BIT(1)
-+/* USB3 PHY soft reset */
-+#define SW_USB3PHY_RESET BIT(2)
-+/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
-+#define SW_USB3PHY_RESET_MUX BIT(3)
-+
-+/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
-+#define USB3_MODE BIT(0) /* enables USB3 mode */
-+#define DP_MODE BIT(1) /* enables DP mode */
-+
-+/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
-+#define ARCVR_DTCT_EN BIT(0)
-+#define ALFPS_DTCT_EN BIT(1)
-+#define ARCVR_DTCT_EVENT_SEL BIT(4)
-+
-+/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
-+#define IRQ_CLEAR BIT(0)
-+
-+/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
-+#define RCVR_DETECT BIT(0)
-+
-+/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
-+#define CLAMP_EN BIT(0) /* enables i/o clamp_n */
-+
-+#define PHY_INIT_COMPLETE_TIMEOUT 10000
-+#define POWER_DOWN_DELAY_US_MIN 10
-+#define POWER_DOWN_DELAY_US_MAX 11
-+
-+#define MAX_PROP_NAME 32
-+
-+/* Define the assumed distance between lanes for underspecified device trees. */
-+#define QMP_PHY_LEGACY_LANE_STRIDE 0x400
-+
-+struct qmp_phy_init_tbl {
-+ unsigned int offset;
-+ unsigned int val;
-+ /*
-+ * register part of layout ?
-+ * if yes, then offset gives index in the reg-layout
-+ */
-+ bool in_layout;
-+ /*
-+ * mask of lanes for which this register is written
-+ * for cases when second lane needs different values
-+ */
-+ u8 lane_mask;
-+};
-+
-+#define QMP_PHY_INIT_CFG(o, v) \
-+ { \
-+ .offset = o, \
-+ .val = v, \
-+ .lane_mask = 0xff, \
-+ }
-+
-+#define QMP_PHY_INIT_CFG_L(o, v) \
-+ { \
-+ .offset = o, \
-+ .val = v, \
-+ .in_layout = true, \
-+ .lane_mask = 0xff, \
-+ }
-+
-+#define QMP_PHY_INIT_CFG_LANE(o, v, l) \
-+ { \
-+ .offset = o, \
-+ .val = v, \
-+ .lane_mask = l, \
-+ }
-+
-+/* set of registers with offsets different per-PHY */
-+enum qphy_reg_layout {
-+ /* Common block control registers */
-+ QPHY_COM_SW_RESET,
-+ QPHY_COM_POWER_DOWN_CONTROL,
-+ QPHY_COM_START_CONTROL,
-+ QPHY_COM_PCS_READY_STATUS,
-+ /* PCS registers */
-+ QPHY_PLL_LOCK_CHK_DLY_TIME,
-+ QPHY_FLL_CNTRL1,
-+ QPHY_FLL_CNTRL2,
-+ QPHY_FLL_CNT_VAL_L,
-+ QPHY_FLL_CNT_VAL_H_TOL,
-+ QPHY_FLL_MAN_CODE,
-+ QPHY_SW_RESET,
-+ QPHY_START_CTRL,
-+ QPHY_PCS_READY_STATUS,
-+ QPHY_PCS_STATUS,
-+ QPHY_PCS_AUTONOMOUS_MODE_CTRL,
-+ QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
-+ QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
-+ QPHY_PCS_POWER_DOWN_CONTROL,
-+ /* PCS_MISC registers */
-+ QPHY_PCS_MISC_TYPEC_CTRL,
-+ /* Keep last to ensure regs_layout arrays are properly initialized */
-+ QPHY_LAYOUT_SIZE
-+};
-+
-+static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_START_CTRL] = 0x00,
-+ [QPHY_PCS_READY_STATUS] = 0x168,
-+};
-+
-+static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x44,
-+ [QPHY_PCS_STATUS] = 0x14,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
-+};
-+
-+static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_COM_SW_RESET] = 0x400,
-+ [QPHY_COM_POWER_DOWN_CONTROL] = 0x404,
-+ [QPHY_COM_START_CONTROL] = 0x408,
-+ [QPHY_COM_PCS_READY_STATUS] = 0x448,
-+ [QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8,
-+ [QPHY_FLL_CNTRL1] = 0xc4,
-+ [QPHY_FLL_CNTRL2] = 0xc8,
-+ [QPHY_FLL_CNT_VAL_L] = 0xcc,
-+ [QPHY_FLL_CNT_VAL_H_TOL] = 0xd0,
-+ [QPHY_FLL_MAN_CODE] = 0xd4,
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_STATUS] = 0x174,
-+};
-+
-+static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_FLL_CNTRL1] = 0xc0,
-+ [QPHY_FLL_CNTRL2] = 0xc4,
-+ [QPHY_FLL_CNT_VAL_L] = 0xc8,
-+ [QPHY_FLL_CNT_VAL_H_TOL] = 0xcc,
-+ [QPHY_FLL_MAN_CODE] = 0xd0,
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_STATUS] = 0x17c,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
-+};
-+
-+static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_STATUS] = 0x174,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
-+};
-+
-+static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_STATUS] = 0x174,
-+};
-+
-+static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_STATUS] = 0x2ac,
-+};
-+
-+static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x44,
-+ [QPHY_PCS_STATUS] = 0x14,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314,
-+};
-+
-+static const unsigned int qmp_v4_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x44,
-+ [QPHY_PCS_STATUS] = 0x14,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x608,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x614,
-+};
-+
-+static const unsigned int sm8350_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x44,
-+ [QPHY_PCS_STATUS] = 0x14,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x1008,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x1014,
-+};
-+
-+static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0xd8,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc,
-+ [QPHY_PCS_STATUS] = 0x174,
-+ [QPHY_PCS_MISC_TYPEC_CTRL] = 0x00,
-+};
-+
-+static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_START_CTRL] = 0x00,
-+ [QPHY_PCS_READY_STATUS] = 0x160,
-+};
-+
-+static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_START_CTRL] = 0x00,
-+ [QPHY_PCS_READY_STATUS] = 0x168,
-+};
-+
-+static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x44,
-+ [QPHY_PCS_STATUS] = 0x14,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
-+};
-+
-+static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START,
-+ [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS,
-+ [QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET,
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
-+ /* PLL and Loop filter settings */
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-+ /* SSC settings */
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
-+ QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
-+
-+ QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
-+
-+ QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
-+ QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
-+ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
-+ /* PLL and Loop filter settings */
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-+ /* SSC settings */
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
-+ /* FLL settings */
-+ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03),
-+ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02),
-+ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42),
-+ QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
-+
-+ /* Lock Det settings */
-+ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x61),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d),
-+ QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10),
-+ QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_PRE, 0x00),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_POST, 0x58),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
-+ QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
-+ QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
-+ QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
-+ QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
-+ QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
-+ QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
-+ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
-+ QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
-+ QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = {
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
-+ /* FLL settings */
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+
-+ /* Lock Det settings */
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
-+ /* FLL settings */
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+
-+ /* Lock Det settings */
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
-+};
-+
-+static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
-+
-+ /* Rate B */
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),
-+};
-+
-+static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B),
-+};
-+
-+static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_RX_PWM_GEAR_BAND, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_CTRL2, 0x6d),
-+ QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_DRV_LVL, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_DRV_LVL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
-+ QMP_PHY_INIT_CFG(QPHY_RX_SYM_RESYNC_CTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
-+ QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
-+
-+ /* Rate B */
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
-+
-+ /* Rate B */
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
-+
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
-+ /* Lock Det settings */
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20),
-+};
-+
-+static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
-+};
-+
-+static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5),
-+};
-+
-+static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
-+};
-+
-+static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),
-+};
-+
-+static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
-+
-+ /* Rate B */
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+};
-+
-+static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01),
-+};
-+
-+static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
-+
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05),
-+
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
-+
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
-+
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
-+};
-+
-+/* Register names should be validated, they might be different for this PHY */
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
-+};
-+
-+struct qmp_phy;
-+
-+/* struct qmp_phy_cfg - per-PHY initialization config */
-+struct qmp_phy_cfg {
-+ /* phy-type - PCIE/UFS/USB */
-+ unsigned int type;
-+ /* number of lanes provided by phy */
-+ int nlanes;
-+
-+ /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
-+ const struct qmp_phy_init_tbl *serdes_tbl;
-+ int serdes_tbl_num;
-+ const struct qmp_phy_init_tbl *serdes_tbl_sec;
-+ int serdes_tbl_num_sec;
-+ const struct qmp_phy_init_tbl *tx_tbl;
-+ int tx_tbl_num;
-+ const struct qmp_phy_init_tbl *tx_tbl_sec;
-+ int tx_tbl_num_sec;
-+ const struct qmp_phy_init_tbl *rx_tbl;
-+ int rx_tbl_num;
-+ const struct qmp_phy_init_tbl *rx_tbl_sec;
-+ int rx_tbl_num_sec;
-+ const struct qmp_phy_init_tbl *pcs_tbl;
-+ int pcs_tbl_num;
-+ const struct qmp_phy_init_tbl *pcs_tbl_sec;
-+ int pcs_tbl_num_sec;
-+ const struct qmp_phy_init_tbl *pcs_misc_tbl;
-+ int pcs_misc_tbl_num;
-+ const struct qmp_phy_init_tbl *pcs_misc_tbl_sec;
-+ int pcs_misc_tbl_num_sec;
-+
-+ /* Init sequence for DP PHY block link rates */
-+ const struct qmp_phy_init_tbl *serdes_tbl_rbr;
-+ int serdes_tbl_rbr_num;
-+ const struct qmp_phy_init_tbl *serdes_tbl_hbr;
-+ int serdes_tbl_hbr_num;
-+ const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
-+ int serdes_tbl_hbr2_num;
-+ const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
-+ int serdes_tbl_hbr3_num;
-+
-+ /* DP PHY callbacks */
-+ int (*configure_dp_phy)(struct qmp_phy *qphy);
-+ void (*configure_dp_tx)(struct qmp_phy *qphy);
-+ int (*calibrate_dp_phy)(struct qmp_phy *qphy);
-+ void (*dp_aux_init)(struct qmp_phy *qphy);
-+
-+ /* clock ids to be requested */
-+ const char * const *clk_list;
-+ int num_clks;
-+ /* resets to be requested */
-+ const char * const *reset_list;
-+ int num_resets;
-+ /* regulators to be requested */
-+ const char * const *vreg_list;
-+ int num_vregs;
-+
-+ /* array of registers with different offsets */
-+ const unsigned int *regs;
-+
-+ unsigned int start_ctrl;
-+ unsigned int pwrdn_ctrl;
-+ unsigned int mask_com_pcs_ready;
-+ /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
-+ unsigned int phy_status;
-+
-+ /* true, if PHY has a separate PHY_COM control block */
-+ bool has_phy_com_ctrl;
-+ /* true, if PHY has a reset for individual lanes */
-+ bool has_lane_rst;
-+ /* true, if PHY needs delay after POWER_DOWN */
-+ bool has_pwrdn_delay;
-+ /* power_down delay in usec */
-+ int pwrdn_delay_min;
-+ int pwrdn_delay_max;
-+
-+ /* true, if PHY has a separate DP_COM control block */
-+ bool has_phy_dp_com_ctrl;
-+ /* true, if PHY has secondary tx/rx lanes to be configured */
-+ bool is_dual_lane_phy;
-+
-+ /* true, if PCS block has no separate SW_RESET register */
-+ bool no_pcs_sw_reset;
-+};
-+
-+struct qmp_phy_combo_cfg {
-+ const struct qmp_phy_cfg *usb_cfg;
-+ const struct qmp_phy_cfg *dp_cfg;
-+};
-+
-+/**
-+ * struct qmp_phy - per-lane phy descriptor
-+ *
-+ * @phy: generic phy
-+ * @cfg: phy specific configuration
-+ * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
-+ * @tx: iomapped memory space for lane's tx
-+ * @rx: iomapped memory space for lane's rx
-+ * @pcs: iomapped memory space for lane's pcs
-+ * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
-+ * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
-+ * @pcs_misc: iomapped memory space for lane's pcs_misc
-+ * @pipe_clk: pipe clock
-+ * @index: lane index
-+ * @qmp: QMP phy to which this lane belongs
-+ * @lane_rst: lane's reset controller
-+ * @mode: current PHY mode
-+ * @dp_aux_cfg: Display port aux config
-+ * @dp_opts: Display port optional config
-+ * @dp_clks: Display port clocks
-+ */
-+struct qmp_phy {
-+ struct phy *phy;
-+ const struct qmp_phy_cfg *cfg;
-+ void __iomem *serdes;
-+ void __iomem *tx;
-+ void __iomem *rx;
-+ void __iomem *pcs;
-+ void __iomem *tx2;
-+ void __iomem *rx2;
-+ void __iomem *pcs_misc;
-+ struct clk *pipe_clk;
-+ unsigned int index;
-+ struct qcom_qmp *qmp;
-+ struct reset_control *lane_rst;
-+ enum phy_mode mode;
-+ unsigned int dp_aux_cfg;
-+ struct phy_configure_opts_dp dp_opts;
-+ struct qmp_phy_dp_clks *dp_clks;
-+};
-+
-+struct qmp_phy_dp_clks {
-+ struct qmp_phy *qphy;
-+ struct clk_hw dp_link_hw;
-+ struct clk_hw dp_pixel_hw;
-+};
-+
-+/**
-+ * struct qcom_qmp - structure holding QMP phy block attributes
-+ *
-+ * @dev: device
-+ * @dp_com: iomapped memory space for phy's dp_com control block
-+ *
-+ * @clks: array of clocks required by phy
-+ * @resets: array of resets required by phy
-+ * @vregs: regulator supplies bulk data
-+ *
-+ * @phys: array of per-lane phy descriptors
-+ * @phy_mutex: mutex lock for PHY common block initialization
-+ * @init_count: phy common block initialization count
-+ * @ufs_reset: optional UFS PHY reset handle
-+ */
-+struct qcom_qmp {
-+ struct device *dev;
-+ void __iomem *dp_com;
-+
-+ struct clk_bulk_data *clks;
-+ struct reset_control **resets;
-+ struct regulator_bulk_data *vregs;
-+
-+ struct qmp_phy **phys;
-+
-+ struct mutex phy_mutex;
-+ int init_count;
-+
-+ struct reset_control *ufs_reset;
-+};
-+
-+static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy);
-+static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy);
-+static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy);
-+static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy);
-+
-+static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy);
-+static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy);
-+static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy);
-+static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy);
-+
-+static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
-+{
-+ u32 reg;
-+
-+ reg = readl(base + offset);
-+ reg |= val;
-+ writel(reg, base + offset);
-+
-+ /* ensure that above write is through */
-+ readl(base + offset);
-+}
-+
-+static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
-+{
-+ u32 reg;
-+
-+ reg = readl(base + offset);
-+ reg &= ~val;
-+ writel(reg, base + offset);
-+
-+ /* ensure that above write is through */
-+ readl(base + offset);
-+}
-+
-+/* list of clocks required by phy */
-+static const char * const msm8996_phy_clk_l[] = {
-+ "aux", "cfg_ahb", "ref",
-+};
-+
-+static const char * const msm8996_ufs_phy_clk_l[] = {
-+ "ref",
-+};
-+
-+static const char * const qmp_v3_phy_clk_l[] = {
-+ "aux", "cfg_ahb", "ref", "com_aux",
-+};
-+
-+static const char * const sdm845_pciephy_clk_l[] = {
-+ "aux", "cfg_ahb", "ref", "refgen",
-+};
-+
-+static const char * const qmp_v4_phy_clk_l[] = {
-+ "aux", "ref_clk_src", "ref", "com_aux",
-+};
-+
-+/* the primary usb3 phy on sm8250 doesn't have a ref clock */
-+static const char * const qmp_v4_sm8250_usbphy_clk_l[] = {
-+ "aux", "ref_clk_src", "com_aux"
-+};
-+
-+static const char * const sm8450_ufs_phy_clk_l[] = {
-+ "qref", "ref", "ref_aux",
-+};
-+
-+static const char * const sdm845_ufs_phy_clk_l[] = {
-+ "ref", "ref_aux",
-+};
-+
-+/* usb3 phy on sdx55 doesn't have com_aux clock */
-+static const char * const qmp_v4_sdx55_usbphy_clk_l[] = {
-+ "aux", "cfg_ahb", "ref"
-+};
-+
-+static const char * const qcm2290_usb3phy_clk_l[] = {
-+ "cfg_ahb", "ref", "com_aux",
-+};
-+
-+/* list of resets */
-+static const char * const msm8996_pciephy_reset_l[] = {
-+ "phy", "common", "cfg",
-+};
-+
-+static const char * const msm8996_usb3phy_reset_l[] = {
-+ "phy", "common",
-+};
-+
-+static const char * const sc7180_usb3phy_reset_l[] = {
-+ "phy",
-+};
-+
-+static const char * const qcm2290_usb3phy_reset_l[] = {
-+ "phy_phy", "phy",
-+};
-+
-+static const char * const sdm845_pciephy_reset_l[] = {
-+ "phy",
-+};
-+
-+/* list of regulators */
-+static const char * const qmp_phy_vreg_l[] = {
-+ "vdda-phy", "vdda-pll",
-+};
-+
-+static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = ipq8074_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
-+ .tx_tbl = msm8996_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
-+ .rx_tbl = ipq8074_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
-+ .pcs_tbl = ipq8074_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
-+ .clk_list = msm8996_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+};
-+
-+static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 3,
-+
-+ .serdes_tbl = msm8996_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
-+ .tx_tbl = msm8996_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8996_pcie_tx_tbl),
-+ .rx_tbl = msm8996_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(msm8996_pcie_rx_tbl),
-+ .pcs_tbl = msm8996_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
-+ .clk_list = msm8996_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-+ .reset_list = msm8996_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = pciephy_regs_layout,
-+
-+ .start_ctrl = PCS_START | PLL_READY_GATE_EN,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .mask_com_pcs_ready = PCS_READY,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_phy_com_ctrl = true,
-+ .has_lane_rst = true,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg msm8996_ufs_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = msm8996_ufs_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(msm8996_ufs_serdes_tbl),
-+ .tx_tbl = msm8996_ufs_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8996_ufs_tx_tbl),
-+ .rx_tbl = msm8996_ufs_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(msm8996_ufs_rx_tbl),
-+
-+ .clk_list = msm8996_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
-+
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+
-+ .regs = msm8996_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .no_pcs_sw_reset = true,
-+};
-+
-+static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = msm8996_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
-+ .tx_tbl = msm8996_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
-+ .rx_tbl = msm8996_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl),
-+ .pcs_tbl = msm8996_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
-+ .clk_list = msm8996_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+};
-+
-+static const char * const ipq8074_pciephy_clk_l[] = {
-+ "aux", "cfg_ahb",
-+};
-+/* list of resets */
-+static const char * const ipq8074_pciephy_reset_l[] = {
-+ "phy", "common",
-+};
-+
-+static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = ipq8074_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
-+ .tx_tbl = ipq8074_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
-+ .rx_tbl = ipq8074_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
-+ .pcs_tbl = ipq8074_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
-+ .clk_list = ipq8074_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
-+ .reset_list = ipq8074_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
-+ .vreg_list = NULL,
-+ .num_vregs = 0,
-+ .regs = pciephy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_phy_com_ctrl = false,
-+ .has_lane_rst = false,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = ipq6018_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl),
-+ .tx_tbl = ipq6018_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl),
-+ .rx_tbl = ipq6018_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
-+ .pcs_tbl = ipq6018_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
-+ .clk_list = ipq8074_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
-+ .reset_list = ipq8074_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
-+ .vreg_list = NULL,
-+ .num_vregs = 0,
-+ .regs = ipq_pciephy_gen3_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+
-+ .has_phy_com_ctrl = false,
-+ .has_lane_rst = false,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sdm845_qmp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
-+ .tx_tbl = sdm845_qmp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),
-+ .rx_tbl = sdm845_qmp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),
-+ .pcs_tbl = sdm845_qmp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sdm845_qmp_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sdm845_qmp_pciephy_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sdm845_qhp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
-+ .tx_tbl = sdm845_qhp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
-+ .rx_tbl = sdm845_qhp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl),
-+ .pcs_tbl = sdm845_qhp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sdm845_qhp_pciephy_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
-+ .serdes_tbl_sec = sm8250_qmp_gen3x1_pcie_serdes_tbl,
-+ .serdes_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
-+ .tx_tbl = sm8250_qmp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
-+ .rx_tbl = sm8250_qmp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
-+ .rx_tbl_sec = sm8250_qmp_gen3x1_pcie_rx_tbl,
-+ .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),
-+ .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
-+ .pcs_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_tbl,
-+ .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
-+ .pcs_misc_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
-+ .tx_tbl = sm8250_qmp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
-+ .tx_tbl_sec = sm8250_qmp_gen3x2_pcie_tx_tbl,
-+ .tx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),
-+ .rx_tbl = sm8250_qmp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
-+ .rx_tbl_sec = sm8250_qmp_gen3x2_pcie_rx_tbl,
-+ .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl),
-+ .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
-+ .pcs_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_tbl,
-+ .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
-+ .pcs_misc_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v3_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
-+ .tx_tbl = qmp_v3_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
-+ .rx_tbl = qmp_v3_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
-+ .pcs_tbl = qmp_v3_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
-+ .clk_list = qmp_v3_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v3_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
-+ .tx_tbl = qmp_v3_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
-+ .rx_tbl = qmp_v3_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
-+ .pcs_tbl = qmp_v3_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
-+ .clk_list = qmp_v3_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-+ .reset_list = sc7180_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sc7180_dpphy_cfg = {
-+ .type = PHY_TYPE_DP,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v3_dp_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
-+ .tx_tbl = qmp_v3_dp_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
-+
-+ .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr,
-+ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
-+ .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr,
-+ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
-+ .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2,
-+ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
-+ .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3,
-+ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
-+
-+ .clk_list = qmp_v3_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-+ .reset_list = sc7180_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+
-+ .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init,
-+ .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx,
-+ .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy,
-+ .calibrate_dp_phy = qcom_qmp_v3_dp_phy_calibrate,
-+};
-+
-+static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = {
-+ .usb_cfg = &sc7180_usb3phy_cfg,
-+ .dp_cfg = &sc7180_dpphy_cfg,
-+};
-+
-+static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
-+ .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v3_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sdm845_ufsphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
-+ .tx_tbl = sdm845_ufsphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
-+ .rx_tbl = sdm845_ufsphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
-+ .pcs_tbl = sdm845_ufsphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
-+ .clk_list = sdm845_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sdm845_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+ .no_pcs_sw_reset = true,
-+};
-+
-+static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm6115_ufsphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl),
-+ .tx_tbl = sm6115_ufsphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_tx_tbl),
-+ .rx_tbl = sm6115_ufsphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_rx_tbl),
-+ .pcs_tbl = sm6115_ufsphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl),
-+ .clk_list = sdm845_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm6115_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+
-+ .is_dual_lane_phy = false,
-+ .no_pcs_sw_reset = true,
-+};
-+
-+static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = msm8998_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
-+ .tx_tbl = msm8998_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8998_pcie_tx_tbl),
-+ .rx_tbl = msm8998_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(msm8998_pcie_rx_tbl),
-+ .pcs_tbl = msm8998_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
-+ .clk_list = msm8996_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-+ .reset_list = ipq8074_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = pciephy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+};
-+
-+static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = msm8998_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
-+ .tx_tbl = msm8998_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl),
-+ .rx_tbl = msm8998_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl),
-+ .pcs_tbl = msm8998_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
-+ .clk_list = msm8996_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sm8150_ufsphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl),
-+ .tx_tbl = sm8150_ufsphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx_tbl),
-+ .rx_tbl = sm8150_ufsphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx_tbl),
-+ .pcs_tbl = sm8150_ufsphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl),
-+ .clk_list = sdm845_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8150_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
-+ .tx_tbl = sm8150_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl),
-+ .rx_tbl = sm8150_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl),
-+ .pcs_tbl = sm8150_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
-+ .clk_list = qmp_v4_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sc8180x_qmp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl),
-+ .tx_tbl = sc8180x_qmp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl),
-+ .rx_tbl = sc8180x_qmp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl),
-+ .pcs_tbl = sc8180x_qmp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sc8180x_qmp_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sc8180x_dpphy_cfg = {
-+ .type = PHY_TYPE_DP,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v4_dp_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
-+ .tx_tbl = qmp_v4_dp_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
-+
-+ .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
-+ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
-+ .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
-+ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
-+ .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
-+ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
-+ .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
-+ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
-+
-+ .clk_list = qmp_v3_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-+ .reset_list = sc7180_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+
-+ .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
-+ .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
-+ .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
-+ .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
-+};
-+
-+static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = {
-+ .usb_cfg = &sm8150_usb3phy_cfg,
-+ .dp_cfg = &sc8180x_dpphy_cfg,
-+};
-+
-+static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = sm8150_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),
-+ .rx_tbl = sm8150_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = sm8150_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v4_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3_uniphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
-+ .tx_tbl = sm8250_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl),
-+ .rx_tbl = sm8250_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl),
-+ .pcs_tbl = sm8250_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
-+ .clk_list = qmp_v4_sm8250_usbphy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = sm8250_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),
-+ .rx_tbl = sm8250_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v4_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3_uniphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sm8250_dpphy_cfg = {
-+ .type = PHY_TYPE_DP,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v4_dp_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
-+ .tx_tbl = qmp_v4_dp_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
-+
-+ .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
-+ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
-+ .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
-+ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
-+ .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
-+ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
-+ .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
-+ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
-+
-+ .clk_list = qmp_v4_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3phy_regs_layout,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+
-+ .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
-+ .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
-+ .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
-+ .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
-+};
-+
-+static const struct qmp_phy_combo_cfg sm8250_usb3dpphy_cfg = {
-+ .usb_cfg = &sm8250_usb3phy_cfg,
-+ .dp_cfg = &sm8250_dpphy_cfg,
-+};
-+
-+static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = sdx55_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl),
-+ .rx_tbl = sdx55_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v4_sdx55_usbphy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3_uniphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sdx55_qmp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl),
-+ .tx_tbl = sdx55_qmp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl),
-+ .rx_tbl = sdx55_qmp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl),
-+ .pcs_tbl = sdx55_qmp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sdx55_qmp_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS_4_20,
-+
-+ .is_dual_lane_phy = true,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = sdx65_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl),
-+ .rx_tbl = sdx65_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v4_sdx55_usbphy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8350_usb3_uniphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sm8350_ufsphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
-+ .tx_tbl = sm8350_ufsphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
-+ .rx_tbl = sm8350_ufsphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
-+ .pcs_tbl = sm8350_ufsphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
-+ .clk_list = sdm845_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8150_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
-+ .tx_tbl = sm8350_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl),
-+ .rx_tbl = sm8350_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl),
-+ .pcs_tbl = sm8350_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl),
-+ .clk_list = qmp_v4_sm8250_usbphy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = sm8350_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),
-+ .rx_tbl = sm8350_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v4_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8350_usb3_uniphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sm8350_ufsphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
-+ .tx_tbl = sm8350_ufsphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
-+ .rx_tbl = sm8350_ufsphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
-+ .pcs_tbl = sm8350_ufsphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
-+ .clk_list = sm8450_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8150_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8450_qmp_gen3x1_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl),
-+ .tx_tbl = sm8450_qmp_gen3x1_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl),
-+ .rx_tbl = sm8450_qmp_gen3x1_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl),
-+ .pcs_tbl = sm8450_qmp_gen3x1_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sm8450_qmp_gen4x2_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl),
-+ .tx_tbl = sm8450_qmp_gen4x2_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl),
-+ .rx_tbl = sm8450_qmp_gen4x2_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl),
-+ .pcs_tbl = sm8450_qmp_gen4x2_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS_4_20,
-+
-+ .is_dual_lane_phy = true,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qcm2290_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl),
-+ .tx_tbl = qcm2290_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl),
-+ .rx_tbl = qcm2290_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(qcm2290_usb3_rx_tbl),
-+ .pcs_tbl = qcm2290_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl),
-+ .clk_list = qcm2290_usb3phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qcm2290_usb3phy_clk_l),
-+ .reset_list = qcm2290_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qcm2290_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+};
-+
-+static void qcom_qmp_phy_configure_lane(void __iomem *base,
-+ const unsigned int *regs,
-+ const struct qmp_phy_init_tbl tbl[],
-+ int num,
-+ u8 lane_mask)
-+{
-+ int i;
-+ const struct qmp_phy_init_tbl *t = tbl;
-+
-+ if (!t)
-+ return;
-+
-+ for (i = 0; i < num; i++, t++) {
-+ if (!(t->lane_mask & lane_mask))
-+ continue;
-+
-+ if (t->in_layout)
-+ writel(t->val, base + regs[t->offset]);
-+ else
-+ writel(t->val, base + t->offset);
-+ }
-+}
-+
-+static void qcom_qmp_phy_configure(void __iomem *base,
-+ const unsigned int *regs,
-+ const struct qmp_phy_init_tbl tbl[],
-+ int num)
-+{
-+ qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff);
-+}
-+
-+static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
-+{
-+ struct qcom_qmp *qmp = qphy->qmp;
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *serdes = qphy->serdes;
-+ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-+ const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
-+ int serdes_tbl_num = cfg->serdes_tbl_num;
-+ int ret;
-+
-+ qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
-+ if (cfg->serdes_tbl_sec)
-+ qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
-+ cfg->serdes_tbl_num_sec);
-+
-+ if (cfg->type == PHY_TYPE_DP) {
-+ switch (dp_opts->link_rate) {
-+ case 1620:
-+ qcom_qmp_phy_configure(serdes, cfg->regs,
-+ cfg->serdes_tbl_rbr,
-+ cfg->serdes_tbl_rbr_num);
-+ break;
-+ case 2700:
-+ qcom_qmp_phy_configure(serdes, cfg->regs,
-+ cfg->serdes_tbl_hbr,
-+ cfg->serdes_tbl_hbr_num);
-+ break;
-+ case 5400:
-+ qcom_qmp_phy_configure(serdes, cfg->regs,
-+ cfg->serdes_tbl_hbr2,
-+ cfg->serdes_tbl_hbr2_num);
-+ break;
-+ case 8100:
-+ qcom_qmp_phy_configure(serdes, cfg->regs,
-+ cfg->serdes_tbl_hbr3,
-+ cfg->serdes_tbl_hbr3_num);
-+ break;
-+ default:
-+ /* Other link rates aren't supported */
-+ return -EINVAL;
-+ }
-+ }
-+
-+
-+ if (cfg->has_phy_com_ctrl) {
-+ void __iomem *status;
-+ unsigned int mask, val;
-+
-+ qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
-+ qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
-+ SERDES_START | PCS_START);
-+
-+ status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
-+ mask = cfg->mask_com_pcs_ready;
-+
-+ ret = readl_poll_timeout(status, val, (val & mask), 10,
-+ PHY_INIT_COMPLETE_TIMEOUT);
-+ if (ret) {
-+ dev_err(qmp->dev,
-+ "phy common block init timed-out\n");
-+ return ret;
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy)
-+{
-+ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
-+ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
-+ qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+
-+ /* Turn on BIAS current for PHY/PLL */
-+ writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
-+ QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
-+ qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
-+
-+ writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+
-+ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
-+ DP_PHY_PD_CTL_LANE_0_1_PWRDN |
-+ DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
-+ DP_PHY_PD_CTL_DP_CLAMP_EN,
-+ qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+
-+ writel(QSERDES_V3_COM_BIAS_EN |
-+ QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
-+ QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL |
-+ QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
-+ qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
-+
-+ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
-+ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-+ writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
-+ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
-+ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
-+ writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
-+ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
-+ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
-+ writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
-+ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
-+ qphy->dp_aux_cfg = 0;
-+
-+ writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
-+ PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
-+ PHY_AUX_REQ_ERR_MASK,
-+ qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
-+}
-+
-+static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = {
-+ { 0x00, 0x0c, 0x15, 0x1a },
-+ { 0x02, 0x0e, 0x16, 0xff },
-+ { 0x02, 0x11, 0xff, 0xff },
-+ { 0x04, 0xff, 0xff, 0xff }
-+};
-+
-+static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = {
-+ { 0x02, 0x12, 0x16, 0x1a },
-+ { 0x09, 0x19, 0x1f, 0xff },
-+ { 0x10, 0x1f, 0xff, 0xff },
-+ { 0x1f, 0xff, 0xff, 0xff }
-+};
-+
-+static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = {
-+ { 0x00, 0x0c, 0x14, 0x19 },
-+ { 0x00, 0x0b, 0x12, 0xff },
-+ { 0x00, 0x0b, 0xff, 0xff },
-+ { 0x04, 0xff, 0xff, 0xff }
-+};
-+
-+static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = {
-+ { 0x08, 0x0f, 0x16, 0x1f },
-+ { 0x11, 0x1e, 0x1f, 0xff },
-+ { 0x19, 0x1f, 0xff, 0xff },
-+ { 0x1f, 0xff, 0xff, 0xff }
-+};
-+
-+static int qcom_qmp_phy_configure_dp_swing(struct qmp_phy *qphy,
-+ unsigned int drv_lvl_reg, unsigned int emp_post_reg)
-+{
-+ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-+ unsigned int v_level = 0, p_level = 0;
-+ u8 voltage_swing_cfg, pre_emphasis_cfg;
-+ int i;
-+
-+ for (i = 0; i < dp_opts->lanes; i++) {
-+ v_level = max(v_level, dp_opts->voltage[i]);
-+ p_level = max(p_level, dp_opts->pre[i]);
-+ }
-+
-+ if (dp_opts->link_rate <= 2700) {
-+ voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level];
-+ pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level];
-+ } else {
-+ voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr3_hbr2[v_level][p_level];
-+ pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr3_hbr2[v_level][p_level];
-+ }
-+
-+ /* TODO: Move check to config check */
-+ if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF)
-+ return -EINVAL;
-+
-+ /* Enable MUX to use Cursor values from these registers */
-+ voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
-+ pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
-+
-+ writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg);
-+ writel(pre_emphasis_cfg, qphy->tx + emp_post_reg);
-+ writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg);
-+ writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg);
-+
-+ return 0;
-+}
-+
-+static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy)
-+{
-+ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-+ u32 bias_en, drvr_en;
-+
-+ if (qcom_qmp_phy_configure_dp_swing(qphy,
-+ QSERDES_V3_TX_TX_DRV_LVL,
-+ QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0)
-+ return;
-+
-+ if (dp_opts->lanes == 1) {
-+ bias_en = 0x3e;
-+ drvr_en = 0x13;
-+ } else {
-+ bias_en = 0x3f;
-+ drvr_en = 0x10;
-+ }
-+
-+ writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN);
-+ writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
-+ writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN);
-+ writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
-+}
-+
-+static bool qcom_qmp_phy_configure_dp_mode(struct qmp_phy *qphy)
-+{
-+ u32 val;
-+ bool reverse = false;
-+
-+ val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
-+ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN;
-+
-+ /*
-+ * TODO: Assume orientation is CC1 for now and two lanes, need to
-+ * use type-c connector to understand orientation and lanes.
-+ *
-+ * Otherwise val changes to be like below if this code understood
-+ * the orientation of the type-c cable.
-+ *
-+ * if (lane_cnt == 4 || orientation == ORIENTATION_CC2)
-+ * val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN;
-+ * if (lane_cnt == 4 || orientation == ORIENTATION_CC1)
-+ * val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
-+ * if (orientation == ORIENTATION_CC2)
-+ * writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
-+ */
-+ val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
-+ writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+
-+ writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE);
-+
-+ return reverse;
-+}
-+
-+static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy)
-+{
-+ const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
-+ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-+ u32 phy_vco_div, status;
-+ unsigned long pixel_freq;
-+
-+ qcom_qmp_phy_configure_dp_mode(qphy);
-+
-+ writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
-+ writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
-+
-+ switch (dp_opts->link_rate) {
-+ case 1620:
-+ phy_vco_div = 0x1;
-+ pixel_freq = 1620000000UL / 2;
-+ break;
-+ case 2700:
-+ phy_vco_div = 0x1;
-+ pixel_freq = 2700000000UL / 2;
-+ break;
-+ case 5400:
-+ phy_vco_div = 0x2;
-+ pixel_freq = 5400000000UL / 4;
-+ break;
-+ case 8100:
-+ phy_vco_div = 0x0;
-+ pixel_freq = 8100000000UL / 6;
-+ break;
-+ default:
-+ /* Other link rates aren't supported */
-+ return -EINVAL;
-+ }
-+ writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV);
-+
-+ clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
-+ clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
-+
-+ writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
-+ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL);
-+
-+ if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS,
-+ status,
-+ ((status & BIT(0)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
-+ status,
-+ ((status & BIT(1)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ udelay(2000);
-+ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
-+ status,
-+ ((status & BIT(1)) > 0),
-+ 500,
-+ 10000);
-+}
-+
-+/*
-+ * We need to calibrate the aux setting here as many times
-+ * as the caller tries
-+ */
-+static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy)
-+{
-+ static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d };
-+ u8 val;
-+
-+ qphy->dp_aux_cfg++;
-+ qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
-+ val = cfg1_settings[qphy->dp_aux_cfg];
-+
-+ writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-+
-+ return 0;
-+}
-+
-+static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy)
-+{
-+ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
-+ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
-+ qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+
-+ /* Turn on BIAS current for PHY/PLL */
-+ writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN);
-+
-+ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
-+ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-+ writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
-+ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
-+ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
-+ writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
-+ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
-+ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
-+ writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
-+ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
-+ qphy->dp_aux_cfg = 0;
-+
-+ writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
-+ PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
-+ PHY_AUX_REQ_ERR_MASK,
-+ qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
-+}
-+
-+static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy)
-+{
-+ /* Program default values before writing proper values */
-+ writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
-+ writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
-+
-+ writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
-+ writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
-+
-+ qcom_qmp_phy_configure_dp_swing(qphy,
-+ QSERDES_V4_TX_TX_DRV_LVL,
-+ QSERDES_V4_TX_TX_EMP_POST1_LVL);
-+}
-+
-+static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy)
-+{
-+ const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
-+ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-+ u32 phy_vco_div, status;
-+ unsigned long pixel_freq;
-+ u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
-+ bool reverse;
-+
-+ writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1);
-+
-+ reverse = qcom_qmp_phy_configure_dp_mode(qphy);
-+
-+ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-+ writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
-+
-+ writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL);
-+ writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL);
-+
-+ switch (dp_opts->link_rate) {
-+ case 1620:
-+ phy_vco_div = 0x1;
-+ pixel_freq = 1620000000UL / 2;
-+ break;
-+ case 2700:
-+ phy_vco_div = 0x1;
-+ pixel_freq = 2700000000UL / 2;
-+ break;
-+ case 5400:
-+ phy_vco_div = 0x2;
-+ pixel_freq = 5400000000UL / 4;
-+ break;
-+ case 8100:
-+ phy_vco_div = 0x0;
-+ pixel_freq = 8100000000UL / 6;
-+ break;
-+ default:
-+ /* Other link rates aren't supported */
-+ return -EINVAL;
-+ }
-+ writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV);
-+
-+ clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
-+ clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
-+
-+ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL);
-+
-+ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS,
-+ status,
-+ ((status & BIT(0)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
-+ status,
-+ ((status & BIT(0)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
-+ status,
-+ ((status & BIT(1)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
-+ status,
-+ ((status & BIT(0)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
-+ status,
-+ ((status & BIT(1)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ /*
-+ * At least for 7nm DP PHY this has to be done after enabling link
-+ * clock.
-+ */
-+
-+ if (dp_opts->lanes == 1) {
-+ bias0_en = reverse ? 0x3e : 0x15;
-+ bias1_en = reverse ? 0x15 : 0x3e;
-+ drvr0_en = reverse ? 0x13 : 0x10;
-+ drvr1_en = reverse ? 0x10 : 0x13;
-+ } else if (dp_opts->lanes == 2) {
-+ bias0_en = reverse ? 0x3f : 0x15;
-+ bias1_en = reverse ? 0x15 : 0x3f;
-+ drvr0_en = 0x10;
-+ drvr1_en = 0x10;
-+ } else {
-+ bias0_en = 0x3f;
-+ bias1_en = 0x3f;
-+ drvr0_en = 0x10;
-+ drvr1_en = 0x10;
-+ }
-+
-+ writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN);
-+ writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
-+ writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN);
-+ writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
-+
-+ writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ udelay(2000);
-+ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
-+ status,
-+ ((status & BIT(1)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV);
-+ writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV);
-+
-+ writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
-+ writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
-+
-+ writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
-+ writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
-+
-+ return 0;
-+}
-+
-+/*
-+ * We need to calibrate the aux setting here as many times
-+ * as the caller tries
-+ */
-+static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy)
-+{
-+ static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d };
-+ u8 val;
-+
-+ qphy->dp_aux_cfg++;
-+ qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
-+ val = cfg1_settings[qphy->dp_aux_cfg];
-+
-+ writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
-+{
-+ const struct phy_configure_opts_dp *dp_opts = &opts->dp;
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+
-+ memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts));
-+ if (qphy->dp_opts.set_voltages) {
-+ cfg->configure_dp_tx(qphy);
-+ qphy->dp_opts.set_voltages = 0;
-+ }
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_dp_phy_calibrate(struct phy *phy)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+
-+ if (cfg->calibrate_dp_phy)
-+ return cfg->calibrate_dp_phy(qphy);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
-+{
-+ struct qcom_qmp *qmp = qphy->qmp;
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *serdes = qphy->serdes;
-+ void __iomem *pcs = qphy->pcs;
-+ void __iomem *dp_com = qmp->dp_com;
-+ int ret, i;
-+
-+ mutex_lock(&qmp->phy_mutex);
-+ if (qmp->init_count++) {
-+ mutex_unlock(&qmp->phy_mutex);
-+ return 0;
-+ }
-+
-+ /* turn on regulator supplies */
-+ ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
-+ if (ret) {
-+ dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
-+ goto err_unlock;
-+ }
-+
-+ for (i = 0; i < cfg->num_resets; i++) {
-+ ret = reset_control_assert(qmp->resets[i]);
-+ if (ret) {
-+ dev_err(qmp->dev, "%s reset assert failed\n",
-+ cfg->reset_list[i]);
-+ goto err_disable_regulators;
-+ }
-+ }
-+
-+ for (i = cfg->num_resets - 1; i >= 0; i--) {
-+ ret = reset_control_deassert(qmp->resets[i]);
-+ if (ret) {
-+ dev_err(qmp->dev, "%s reset deassert failed\n",
-+ qphy->cfg->reset_list[i]);
-+ goto err_assert_reset;
-+ }
-+ }
-+
-+ ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
-+ if (ret)
-+ goto err_assert_reset;
-+
-+ if (cfg->has_phy_dp_com_ctrl) {
-+ qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
-+ SW_PWRDN);
-+ /* override hardware control for reset of qmp phy */
-+ qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
-+ SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
-+ SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
-+
-+ /* Default type-c orientation, i.e CC1 */
-+ qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02);
-+
-+ qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
-+ USB3_MODE | DP_MODE);
-+
-+ /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
-+ qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
-+ SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
-+ SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
-+
-+ qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
-+ qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
-+ }
-+
-+ if (cfg->has_phy_com_ctrl) {
-+ qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
-+ SW_PWRDN);
-+ } else {
-+ if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
-+ qphy_setbits(pcs,
-+ cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
-+ cfg->pwrdn_ctrl);
-+ else
-+ qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
-+ cfg->pwrdn_ctrl);
-+ }
-+
-+ mutex_unlock(&qmp->phy_mutex);
-+
-+ return 0;
-+
-+err_assert_reset:
-+ while (++i < cfg->num_resets)
-+ reset_control_assert(qmp->resets[i]);
-+err_disable_regulators:
-+ regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
-+err_unlock:
-+ mutex_unlock(&qmp->phy_mutex);
-+
-+ return ret;
-+}
-+
-+static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy)
-+{
-+ struct qcom_qmp *qmp = qphy->qmp;
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *serdes = qphy->serdes;
-+ int i = cfg->num_resets;
-+
-+ mutex_lock(&qmp->phy_mutex);
-+ if (--qmp->init_count) {
-+ mutex_unlock(&qmp->phy_mutex);
-+ return 0;
-+ }
-+
-+ reset_control_assert(qmp->ufs_reset);
-+ if (cfg->has_phy_com_ctrl) {
-+ qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
-+ SERDES_START | PCS_START);
-+ qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
-+ SW_RESET);
-+ qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
-+ SW_PWRDN);
-+ }
-+
-+ while (--i >= 0)
-+ reset_control_assert(qmp->resets[i]);
-+
-+ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
-+
-+ regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
-+
-+ mutex_unlock(&qmp->phy_mutex);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_init(struct phy *phy)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ struct qcom_qmp *qmp = qphy->qmp;
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ int ret;
-+ dev_vdbg(qmp->dev, "Initializing QMP phy\n");
-+
-+ if (cfg->no_pcs_sw_reset) {
-+ /*
-+ * Get UFS reset, which is delayed until now to avoid a
-+ * circular dependency where UFS needs its PHY, but the PHY
-+ * needs this UFS reset.
-+ */
-+ if (!qmp->ufs_reset) {
-+ qmp->ufs_reset =
-+ devm_reset_control_get_exclusive(qmp->dev,
-+ "ufsphy");
-+
-+ if (IS_ERR(qmp->ufs_reset)) {
-+ ret = PTR_ERR(qmp->ufs_reset);
-+ dev_err(qmp->dev,
-+ "failed to get UFS reset: %d\n",
-+ ret);
-+
-+ qmp->ufs_reset = NULL;
-+ return ret;
-+ }
-+ }
-+
-+ ret = reset_control_assert(qmp->ufs_reset);
-+ if (ret)
-+ return ret;
-+ }
-+
-+ ret = qcom_qmp_phy_com_init(qphy);
-+ if (ret)
-+ return ret;
-+
-+ if (cfg->type == PHY_TYPE_DP)
-+ cfg->dp_aux_init(qphy);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_power_on(struct phy *phy)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ struct qcom_qmp *qmp = qphy->qmp;
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *tx = qphy->tx;
-+ void __iomem *rx = qphy->rx;
-+ void __iomem *pcs = qphy->pcs;
-+ void __iomem *pcs_misc = qphy->pcs_misc;
-+ void __iomem *status;
-+ unsigned int mask, val, ready;
-+ int ret;
-+
-+ qcom_qmp_phy_serdes_init(qphy);
-+
-+ if (cfg->has_lane_rst) {
-+ ret = reset_control_deassert(qphy->lane_rst);
-+ if (ret) {
-+ dev_err(qmp->dev, "lane%d reset deassert failed\n",
-+ qphy->index);
-+ return ret;
-+ }
-+ }
-+
-+ ret = clk_prepare_enable(qphy->pipe_clk);
-+ if (ret) {
-+ dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
-+ goto err_reset_lane;
-+ }
-+
-+ /* Tx, Rx, and PCS configurations */
-+ qcom_qmp_phy_configure_lane(tx, cfg->regs,
-+ cfg->tx_tbl, cfg->tx_tbl_num, 1);
-+ if (cfg->tx_tbl_sec)
-+ qcom_qmp_phy_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
-+ cfg->tx_tbl_num_sec, 1);
-+
-+ /* Configuration for other LANE for USB-DP combo PHY */
-+ if (cfg->is_dual_lane_phy) {
-+ qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
-+ cfg->tx_tbl, cfg->tx_tbl_num, 2);
-+ if (cfg->tx_tbl_sec)
-+ qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
-+ cfg->tx_tbl_sec,
-+ cfg->tx_tbl_num_sec, 2);
-+ }
-+
-+ /* Configure special DP tx tunings */
-+ if (cfg->type == PHY_TYPE_DP)
-+ cfg->configure_dp_tx(qphy);
-+
-+ qcom_qmp_phy_configure_lane(rx, cfg->regs,
-+ cfg->rx_tbl, cfg->rx_tbl_num, 1);
-+ if (cfg->rx_tbl_sec)
-+ qcom_qmp_phy_configure_lane(rx, cfg->regs,
-+ cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1);
-+
-+ if (cfg->is_dual_lane_phy) {
-+ qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
-+ cfg->rx_tbl, cfg->rx_tbl_num, 2);
-+ if (cfg->rx_tbl_sec)
-+ qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
-+ cfg->rx_tbl_sec,
-+ cfg->rx_tbl_num_sec, 2);
-+ }
-+
-+ /* Configure link rate, swing, etc. */
-+ if (cfg->type == PHY_TYPE_DP) {
-+ cfg->configure_dp_phy(qphy);
-+ } else {
-+ qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
-+ if (cfg->pcs_tbl_sec)
-+ qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
-+ cfg->pcs_tbl_num_sec);
-+ }
-+
-+ ret = reset_control_deassert(qmp->ufs_reset);
-+ if (ret)
-+ goto err_disable_pipe_clk;
-+
-+ qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
-+ cfg->pcs_misc_tbl_num);
-+ if (cfg->pcs_misc_tbl_sec)
-+ qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
-+ cfg->pcs_misc_tbl_num_sec);
-+
-+ /*
-+ * Pull out PHY from POWER DOWN state.
-+ * This is active low enable signal to power-down PHY.
-+ */
-+ if(cfg->type == PHY_TYPE_PCIE)
-+ qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
-+
-+ if (cfg->has_pwrdn_delay)
-+ usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
-+
-+ if (cfg->type != PHY_TYPE_DP) {
-+ /* Pull PHY out of reset state */
-+ if (!cfg->no_pcs_sw_reset)
-+ qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
-+ /* start SerDes and Phy-Coding-Sublayer */
-+ qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
-+
-+ if (cfg->type == PHY_TYPE_UFS) {
-+ status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
-+ mask = PCS_READY;
-+ ready = PCS_READY;
-+ } else {
-+ status = pcs + cfg->regs[QPHY_PCS_STATUS];
-+ mask = cfg->phy_status;
-+ ready = 0;
-+ }
-+
-+ ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
-+ PHY_INIT_COMPLETE_TIMEOUT);
-+ if (ret) {
-+ dev_err(qmp->dev, "phy initialization timed-out\n");
-+ goto err_disable_pipe_clk;
-+ }
-+ }
-+ return 0;
-+
-+err_disable_pipe_clk:
-+ clk_disable_unprepare(qphy->pipe_clk);
-+err_reset_lane:
-+ if (cfg->has_lane_rst)
-+ reset_control_assert(qphy->lane_rst);
-+
-+ return ret;
-+}
-+
-+static int qcom_qmp_phy_power_off(struct phy *phy)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+
-+ clk_disable_unprepare(qphy->pipe_clk);
-+
-+ if (cfg->type == PHY_TYPE_DP) {
-+ /* Assert DP PHY power down */
-+ writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+ } else {
-+ /* PHY reset */
-+ if (!cfg->no_pcs_sw_reset)
-+ qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
-+
-+ /* stop SerDes and Phy-Coding-Sublayer */
-+ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
-+
-+ /* Put PHY into POWER DOWN state: active low */
-+ if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
-+ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
-+ cfg->pwrdn_ctrl);
-+ } else {
-+ qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
-+ cfg->pwrdn_ctrl);
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_exit(struct phy *phy)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+
-+ if (cfg->has_lane_rst)
-+ reset_control_assert(qphy->lane_rst);
-+
-+ qcom_qmp_phy_com_exit(qphy);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_enable(struct phy *phy)
-+{
-+ int ret;
-+
-+ ret = qcom_qmp_phy_init(phy);
-+ if (ret)
-+ return ret;
-+
-+ ret = qcom_qmp_phy_power_on(phy);
-+ if (ret)
-+ qcom_qmp_phy_exit(phy);
-+
-+ return ret;
-+}
-+
-+static int qcom_qmp_phy_disable(struct phy *phy)
-+{
-+ int ret;
-+
-+ ret = qcom_qmp_phy_power_off(phy);
-+ if (ret)
-+ return ret;
-+ return qcom_qmp_phy_exit(phy);
-+}
-+
-+static int qcom_qmp_phy_set_mode(struct phy *phy,
-+ enum phy_mode mode, int submode)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+
-+ qphy->mode = mode;
-+
-+ return 0;
-+}
-+
-+static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
-+{
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *pcs = qphy->pcs;
-+ void __iomem *pcs_misc = qphy->pcs_misc;
-+ u32 intr_mask;
-+
-+ if (qphy->mode == PHY_MODE_USB_HOST_SS ||
-+ qphy->mode == PHY_MODE_USB_DEVICE_SS)
-+ intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
-+ else
-+ intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
-+
-+ /* Clear any pending interrupts status */
-+ qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
-+ /* Writing 1 followed by 0 clears the interrupt */
-+ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
-+
-+ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
-+ ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
-+
-+ /* Enable required PHY autonomous mode interrupts */
-+ qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
-+
-+ /* Enable i/o clamp_n for autonomous mode */
-+ if (pcs_misc)
-+ qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
-+}
-+
-+static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
-+{
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *pcs = qphy->pcs;
-+ void __iomem *pcs_misc = qphy->pcs_misc;
-+
-+ /* Disable i/o clamp_n on resume for normal mode */
-+ if (pcs_misc)
-+ qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
-+
-+ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
-+ ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
-+
-+ qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
-+ /* Writing 1 followed by 0 clears the interrupt */
-+ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
-+}
-+
-+static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ struct qmp_phy *qphy = qmp->phys[0];
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+
-+ dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode);
-+
-+ /* Supported only for USB3 PHY and luckily USB3 is the first phy */
-+ if (cfg->type != PHY_TYPE_USB3)
-+ return 0;
-+
-+ if (!qmp->init_count) {
-+ dev_vdbg(dev, "PHY not initialized, bailing out\n");
-+ return 0;
-+ }
-+
-+ qcom_qmp_phy_enable_autonomous_mode(qphy);
-+
-+ clk_disable_unprepare(qphy->pipe_clk);
-+ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
-+
-+ return 0;
-+}
-+
-+static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ struct qmp_phy *qphy = qmp->phys[0];
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ int ret = 0;
-+
-+ dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode);
-+
-+ /* Supported only for USB3 PHY and luckily USB3 is the first phy */
-+ if (cfg->type != PHY_TYPE_USB3)
-+ return 0;
-+
-+ if (!qmp->init_count) {
-+ dev_vdbg(dev, "PHY not initialized, bailing out\n");
-+ return 0;
-+ }
-+
-+ ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
-+ if (ret)
-+ return ret;
-+
-+ ret = clk_prepare_enable(qphy->pipe_clk);
-+ if (ret) {
-+ dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
-+ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
-+ return ret;
-+ }
-+
-+ qcom_qmp_phy_disable_autonomous_mode(qphy);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ int num = cfg->num_vregs;
-+ int i;
-+
-+ qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
-+ if (!qmp->vregs)
-+ return -ENOMEM;
-+
-+ for (i = 0; i < num; i++)
-+ qmp->vregs[i].supply = cfg->vreg_list[i];
-+
-+ return devm_regulator_bulk_get(dev, num, qmp->vregs);
-+}
-+
-+static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ int i;
-+
-+ qmp->resets = devm_kcalloc(dev, cfg->num_resets,
-+ sizeof(*qmp->resets), GFP_KERNEL);
-+ if (!qmp->resets)
-+ return -ENOMEM;
-+
-+ for (i = 0; i < cfg->num_resets; i++) {
-+ struct reset_control *rst;
-+ const char *name = cfg->reset_list[i];
-+
-+ rst = devm_reset_control_get_exclusive(dev, name);
-+ if (IS_ERR(rst)) {
-+ dev_err(dev, "failed to get %s reset\n", name);
-+ return PTR_ERR(rst);
-+ }
-+ qmp->resets[i] = rst;
-+ }
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ int num = cfg->num_clks;
-+ int i;
-+
-+ qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
-+ if (!qmp->clks)
-+ return -ENOMEM;
-+
-+ for (i = 0; i < num; i++)
-+ qmp->clks[i].id = cfg->clk_list[i];
-+
-+ return devm_clk_bulk_get(dev, num, qmp->clks);
-+}
-+
-+static void phy_clk_release_provider(void *res)
-+{
-+ of_clk_del_provider(res);
-+}
-+
-+/*
-+ * Register a fixed rate pipe clock.
-+ *
-+ * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
-+ * controls it. The <s>_pipe_clk coming out of the GCC is requested
-+ * by the PHY driver for its operations.
-+ * We register the <s>_pipe_clksrc here. The gcc driver takes care
-+ * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
-+ * Below picture shows this relationship.
-+ *
-+ * +---------------+
-+ * | PHY block |<<---------------------------------------+
-+ * | | |
-+ * | +-------+ | +-----+ |
-+ * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
-+ * clk | +-------+ | +-----+
-+ * +---------------+
-+ */
-+static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
-+{
-+ struct clk_fixed_rate *fixed;
-+ struct clk_init_data init = { };
-+ int ret;
-+
-+ ret = of_property_read_string(np, "clock-output-names", &init.name);
-+ if (ret) {
-+ dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
-+ return ret;
-+ }
-+
-+ fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
-+ if (!fixed)
-+ return -ENOMEM;
-+
-+ init.ops = &clk_fixed_rate_ops;
-+
-+ /* controllers using QMP phys use 125MHz pipe clock interface */
-+ fixed->fixed_rate = 125000000;
-+ fixed->hw.init = &init;
-+
-+ ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
-+ if (ret)
-+ return ret;
-+
-+ ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
-+ if (ret)
-+ return ret;
-+
-+ /*
-+ * Roll a devm action because the clock provider is the child node, but
-+ * the child node is not actually a device.
-+ */
-+ return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
-+}
-+
-+/*
-+ * Display Port PLL driver block diagram for branch clocks
-+ *
-+ * +------------------------------+
-+ * | DP_VCO_CLK |
-+ * | |
-+ * | +-------------------+ |
-+ * | | (DP PLL/VCO) | |
-+ * | +---------+---------+ |
-+ * | v |
-+ * | +----------+-----------+ |
-+ * | | hsclk_divsel_clk_src | |
-+ * | +----------+-----------+ |
-+ * +------------------------------+
-+ * |
-+ * +---------<---------v------------>----------+
-+ * | |
-+ * +--------v----------------+ |
-+ * | dp_phy_pll_link_clk | |
-+ * | link_clk | |
-+ * +--------+----------------+ |
-+ * | |
-+ * | |
-+ * v v
-+ * Input to DISPCC block |
-+ * for link clk, crypto clk |
-+ * and interface clock |
-+ * |
-+ * |
-+ * +--------<------------+-----------------+---<---+
-+ * | | |
-+ * +----v---------+ +--------v-----+ +--------v------+
-+ * | vco_divided | | vco_divided | | vco_divided |
-+ * | _clk_src | | _clk_src | | _clk_src |
-+ * | | | | | |
-+ * |divsel_six | | divsel_two | | divsel_four |
-+ * +-------+------+ +-----+--------+ +--------+------+
-+ * | | |
-+ * v---->----------v-------------<------v
-+ * |
-+ * +----------+-----------------+
-+ * | dp_phy_pll_vco_div_clk |
-+ * +---------+------------------+
-+ * |
-+ * v
-+ * Input to DISPCC block
-+ * for DP pixel clock
-+ *
-+ */
-+static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw,
-+ struct clk_rate_request *req)
-+{
-+ switch (req->rate) {
-+ case 1620000000UL / 2:
-+ case 2700000000UL / 2:
-+ /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */
-+ return 0;
-+ default:
-+ return -EINVAL;
-+ }
-+}
-+
-+static unsigned long
-+qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
-+{
-+ const struct qmp_phy_dp_clks *dp_clks;
-+ const struct qmp_phy *qphy;
-+ const struct phy_configure_opts_dp *dp_opts;
-+
-+ dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw);
-+ qphy = dp_clks->qphy;
-+ dp_opts = &qphy->dp_opts;
-+
-+ switch (dp_opts->link_rate) {
-+ case 1620:
-+ return 1620000000UL / 2;
-+ case 2700:
-+ return 2700000000UL / 2;
-+ case 5400:
-+ return 5400000000UL / 4;
-+ case 8100:
-+ return 8100000000UL / 6;
-+ default:
-+ return 0;
-+ }
-+}
-+
-+static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = {
-+ .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate,
-+ .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate,
-+};
-+
-+static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw,
-+ struct clk_rate_request *req)
-+{
-+ switch (req->rate) {
-+ case 162000000:
-+ case 270000000:
-+ case 540000000:
-+ case 810000000:
-+ return 0;
-+ default:
-+ return -EINVAL;
-+ }
-+}
-+
-+static unsigned long
-+qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
-+{
-+ const struct qmp_phy_dp_clks *dp_clks;
-+ const struct qmp_phy *qphy;
-+ const struct phy_configure_opts_dp *dp_opts;
-+
-+ dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw);
-+ qphy = dp_clks->qphy;
-+ dp_opts = &qphy->dp_opts;
-+
-+ switch (dp_opts->link_rate) {
-+ case 1620:
-+ case 2700:
-+ case 5400:
-+ case 8100:
-+ return dp_opts->link_rate * 100000;
-+ default:
-+ return 0;
-+ }
-+}
-+
-+static const struct clk_ops qcom_qmp_dp_link_clk_ops = {
-+ .determine_rate = qcom_qmp_dp_link_clk_determine_rate,
-+ .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate,
-+};
-+
-+static struct clk_hw *
-+qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data)
-+{
-+ struct qmp_phy_dp_clks *dp_clks = data;
-+ unsigned int idx = clkspec->args[0];
-+
-+ if (idx >= 2) {
-+ pr_err("%s: invalid index %u\n", __func__, idx);
-+ return ERR_PTR(-EINVAL);
-+ }
-+
-+ if (idx == 0)
-+ return &dp_clks->dp_link_hw;
-+
-+ return &dp_clks->dp_pixel_hw;
-+}
-+
-+static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy,
-+ struct device_node *np)
-+{
-+ struct clk_init_data init = { };
-+ struct qmp_phy_dp_clks *dp_clks;
-+ char name[64];
-+ int ret;
-+
-+ dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL);
-+ if (!dp_clks)
-+ return -ENOMEM;
-+
-+ dp_clks->qphy = qphy;
-+ qphy->dp_clks = dp_clks;
-+
-+ snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev));
-+ init.ops = &qcom_qmp_dp_link_clk_ops;
-+ init.name = name;
-+ dp_clks->dp_link_hw.init = &init;
-+ ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw);
-+ if (ret)
-+ return ret;
-+
-+ snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev));
-+ init.ops = &qcom_qmp_dp_pixel_clk_ops;
-+ init.name = name;
-+ dp_clks->dp_pixel_hw.init = &init;
-+ ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw);
-+ if (ret)
-+ return ret;
-+
-+ ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks);
-+ if (ret)
-+ return ret;
-+
-+ /*
-+ * Roll a devm action because the clock provider is the child node, but
-+ * the child node is not actually a device.
-+ */
-+ return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
-+}
-+
-+static const struct phy_ops qcom_qmp_phy_gen_ops = {
-+ .init = qcom_qmp_phy_enable,
-+ .exit = qcom_qmp_phy_disable,
-+ .set_mode = qcom_qmp_phy_set_mode,
-+ .owner = THIS_MODULE,
-+};
-+
-+static const struct phy_ops qcom_qmp_phy_dp_ops = {
-+ .init = qcom_qmp_phy_init,
-+ .configure = qcom_qmp_dp_phy_configure,
-+ .power_on = qcom_qmp_phy_power_on,
-+ .calibrate = qcom_qmp_dp_phy_calibrate,
-+ .power_off = qcom_qmp_phy_power_off,
-+ .exit = qcom_qmp_phy_exit,
-+ .set_mode = qcom_qmp_phy_set_mode,
-+ .owner = THIS_MODULE,
-+};
-+
-+static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
-+ .power_on = qcom_qmp_phy_enable,
-+ .power_off = qcom_qmp_phy_disable,
-+ .set_mode = qcom_qmp_phy_set_mode,
-+ .owner = THIS_MODULE,
-+};
-+
-+static void qcom_qmp_reset_control_put(void *data)
-+{
-+ reset_control_put(data);
-+}
-+
-+static
-+int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
-+ void __iomem *serdes, const struct qmp_phy_cfg *cfg)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ struct phy *generic_phy;
-+ struct qmp_phy *qphy;
-+ const struct phy_ops *ops;
-+ char prop_name[MAX_PROP_NAME];
-+ int ret;
-+
-+ qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
-+ if (!qphy)
-+ return -ENOMEM;
-+
-+ qphy->cfg = cfg;
-+ qphy->serdes = serdes;
-+ /*
-+ * Get memory resources for each phy lane:
-+ * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
-+ * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
-+ * For single lane PHYs: pcs_misc (optional) -> 3.
-+ */
-+ qphy->tx = of_iomap(np, 0);
-+ if (!qphy->tx)
-+ return -ENOMEM;
-+
-+ qphy->rx = of_iomap(np, 1);
-+ if (!qphy->rx)
-+ return -ENOMEM;
-+
-+ qphy->pcs = of_iomap(np, 2);
-+ if (!qphy->pcs)
-+ return -ENOMEM;
-+
-+ /*
-+ * If this is a dual-lane PHY, then there should be registers for the
-+ * second lane. Some old device trees did not specify this, so fall
-+ * back to old legacy behavior of assuming they can be reached at an
-+ * offset from the first lane.
-+ */
-+ if (cfg->is_dual_lane_phy) {
-+ qphy->tx2 = of_iomap(np, 3);
-+ qphy->rx2 = of_iomap(np, 4);
-+ if (!qphy->tx2 || !qphy->rx2) {
-+ dev_warn(dev,
-+ "Underspecified device tree, falling back to legacy register regions\n");
-+
-+ /* In the old version, pcs_misc is at index 3. */
-+ qphy->pcs_misc = qphy->tx2;
-+ qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE;
-+ qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
-+
-+ } else {
-+ qphy->pcs_misc = of_iomap(np, 5);
-+ }
-+
-+ } else {
-+ qphy->pcs_misc = of_iomap(np, 3);
-+ }
-+
-+ if (!qphy->pcs_misc)
-+ dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
-+
-+ /*
-+ * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3
-+ * based phys, so they essentially have pipe clock. So,
-+ * we return error in case phy is USB3 or PIPE type.
-+ * Otherwise, we initialize pipe clock to NULL for
-+ * all phys that don't need this.
-+ */
-+ snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
-+ qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name);
-+ if (IS_ERR(qphy->pipe_clk)) {
-+ if (cfg->type == PHY_TYPE_PCIE ||
-+ cfg->type == PHY_TYPE_USB3) {
-+ ret = PTR_ERR(qphy->pipe_clk);
-+ if (ret != -EPROBE_DEFER)
-+ dev_err(dev,
-+ "failed to get lane%d pipe_clk, %d\n",
-+ id, ret);
-+ return ret;
-+ }
-+ qphy->pipe_clk = NULL;
-+ }
-+
-+ /* Get lane reset, if any */
-+ if (cfg->has_lane_rst) {
-+ snprintf(prop_name, sizeof(prop_name), "lane%d", id);
-+ qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name);
-+ if (IS_ERR(qphy->lane_rst)) {
-+ dev_err(dev, "failed to get lane%d reset\n", id);
-+ return PTR_ERR(qphy->lane_rst);
-+ }
-+ ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put,
-+ qphy->lane_rst);
-+ if (ret)
-+ return ret;
-+ }
-+
-+ if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE)
-+ ops = &qcom_qmp_pcie_ufs_ops;
-+ else if (cfg->type == PHY_TYPE_DP)
-+ ops = &qcom_qmp_phy_dp_ops;
-+ else
-+ ops = &qcom_qmp_phy_gen_ops;
-+
-+ generic_phy = devm_phy_create(dev, np, ops);
-+ if (IS_ERR(generic_phy)) {
-+ ret = PTR_ERR(generic_phy);
-+ dev_err(dev, "failed to create qphy %d\n", ret);
-+ return ret;
-+ }
-+
-+ qphy->phy = generic_phy;
-+ qphy->index = id;
-+ qphy->qmp = qmp;
-+ qmp->phys[id] = qphy;
-+ phy_set_drvdata(generic_phy, qphy);
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
-+ {
-+ .compatible = "qcom,ipq8074-qmp-usb3-phy",
-+ .data = &ipq8074_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,msm8996-qmp-pcie-phy",
-+ .data = &msm8996_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,msm8996-qmp-ufs-phy",
-+ .data = &msm8996_ufs_cfg,
-+ }, {
-+ .compatible = "qcom,msm8996-qmp-usb3-phy",
-+ .data = &msm8996_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,msm8998-qmp-pcie-phy",
-+ .data = &msm8998_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,msm8998-qmp-ufs-phy",
-+ .data = &sdm845_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,ipq8074-qmp-pcie-phy",
-+ .data = &ipq8074_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,ipq6018-qmp-pcie-phy",
-+ .data = &ipq6018_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,ipq6018-qmp-usb3-phy",
-+ .data = &ipq8074_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sc7180-qmp-usb3-phy",
-+ .data = &sc7180_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
-+ /* It's a combo phy */
-+ }, {
-+ .compatible = "qcom,sc8180x-qmp-pcie-phy",
-+ .data = &sc8180x_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sc8180x-qmp-ufs-phy",
-+ .data = &sm8150_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sc8280xp-qmp-ufs-phy",
-+ .data = &sm8350_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sc8180x-qmp-usb3-phy",
-+ .data = &sm8150_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
-+ /* It's a combo phy */
-+ }, {
-+ .compatible = "qcom,sdm845-qhp-pcie-phy",
-+ .data = &sdm845_qhp_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sdm845-qmp-pcie-phy",
-+ .data = &sdm845_qmp_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sdm845-qmp-usb3-phy",
-+ .data = &qmp_v3_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
-+ .data = &qmp_v3_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sdm845-qmp-ufs-phy",
-+ .data = &sdm845_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,msm8998-qmp-usb3-phy",
-+ .data = &msm8998_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sm6115-qmp-ufs-phy",
-+ .data = &sm6115_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm6350-qmp-ufs-phy",
-+ .data = &sdm845_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8150-qmp-ufs-phy",
-+ .data = &sm8150_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-ufs-phy",
-+ .data = &sm8150_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8150-qmp-usb3-phy",
-+ .data = &sm8150_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8150-qmp-usb3-uni-phy",
-+ .data = &sm8150_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-usb3-phy",
-+ .data = &sm8250_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
-+ /* It's a combo phy */
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-usb3-uni-phy",
-+ .data = &sm8250_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
-+ .data = &sm8250_qmp_gen3x1_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
-+ .data = &sm8250_qmp_gen3x2_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8350-qmp-ufs-phy",
-+ .data = &sm8350_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
-+ .data = &sm8250_qmp_gen3x2_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sdx55-qmp-pcie-phy",
-+ .data = &sdx55_qmp_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sdx55-qmp-usb3-uni-phy",
-+ .data = &sdx55_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sdx65-qmp-usb3-uni-phy",
-+ .data = &sdx65_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8350-qmp-usb3-phy",
-+ .data = &sm8350_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8350-qmp-usb3-uni-phy",
-+ .data = &sm8350_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
-+ .data = &sm8450_qmp_gen3x1_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
-+ .data = &sm8450_qmp_gen4x2_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8450-qmp-ufs-phy",
-+ .data = &sm8450_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8450-qmp-usb3-phy",
-+ .data = &sm8350_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,qcm2290-qmp-usb3-phy",
-+ .data = &qcm2290_usb3phy_cfg,
-+ },
-+ { },
-+};
-+MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
-+
-+static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = {
-+ {
-+ .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
-+ .data = &sc7180_usb3dpphy_cfg,
-+ },
-+ {
-+ .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
-+ .data = &sm8250_usb3dpphy_cfg,
-+ },
-+ {
-+ .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
-+ .data = &sc8180x_usb3dpphy_cfg,
-+ },
-+ { }
-+};
-+
-+static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
-+ SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
-+ qcom_qmp_phy_runtime_resume, NULL)
-+};
-+
-+static int qcom_qmp_phy_probe(struct platform_device *pdev)
-+{
-+ struct qcom_qmp *qmp;
-+ struct device *dev = &pdev->dev;
-+ struct device_node *child;
-+ struct phy_provider *phy_provider;
-+ void __iomem *serdes;
-+ void __iomem *usb_serdes;
-+ void __iomem *dp_serdes = NULL;
-+ const struct qmp_phy_combo_cfg *combo_cfg = NULL;
-+ const struct qmp_phy_cfg *cfg = NULL;
-+ const struct qmp_phy_cfg *usb_cfg = NULL;
-+ const struct qmp_phy_cfg *dp_cfg = NULL;
-+ int num, id, expected_phys;
-+ int ret;
-+
-+ qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
-+ if (!qmp)
-+ return -ENOMEM;
-+
-+ qmp->dev = dev;
-+ dev_set_drvdata(dev, qmp);
-+
-+ /* Get the specific init parameters of QMP phy */
-+ cfg = of_device_get_match_data(dev);
-+ if (!cfg) {
-+ const struct of_device_id *match;
-+
-+ match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev);
-+ if (!match)
-+ return -EINVAL;
-+
-+ combo_cfg = match->data;
-+ if (!combo_cfg)
-+ return -EINVAL;
-+
-+ usb_cfg = combo_cfg->usb_cfg;
-+ cfg = usb_cfg; /* Setup clks and regulators */
-+ }
-+
-+ /* per PHY serdes; usually located at base address */
-+ usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0);
-+ if (IS_ERR(serdes))
-+ return PTR_ERR(serdes);
-+
-+ /* per PHY dp_com; if PHY has dp_com control block */
-+ if (combo_cfg || cfg->has_phy_dp_com_ctrl) {
-+ qmp->dp_com = devm_platform_ioremap_resource(pdev, 1);
-+ if (IS_ERR(qmp->dp_com))
-+ return PTR_ERR(qmp->dp_com);
-+ }
-+
-+ if (combo_cfg) {
-+ /* Only two serdes for combo PHY */
-+ dp_serdes = devm_platform_ioremap_resource(pdev, 2);
-+ if (IS_ERR(dp_serdes))
-+ return PTR_ERR(dp_serdes);
-+
-+ dp_cfg = combo_cfg->dp_cfg;
-+ expected_phys = 2;
-+ } else {
-+ expected_phys = cfg->nlanes;
-+ }
-+
-+ mutex_init(&qmp->phy_mutex);
-+
-+ ret = qcom_qmp_phy_clk_init(dev, cfg);
-+ if (ret)
-+ return ret;
-+
-+ ret = qcom_qmp_phy_reset_init(dev, cfg);
-+ if (ret)
-+ return ret;
-+
-+ ret = qcom_qmp_phy_vreg_init(dev, cfg);
-+ if (ret) {
-+ if (ret != -EPROBE_DEFER)
-+ dev_err(dev, "failed to get regulator supplies: %d\n",
-+ ret);
-+ return ret;
-+ }
-+
-+ num = of_get_available_child_count(dev->of_node);
-+ /* do we have a rogue child node ? */
-+ if (num > expected_phys)
-+ return -EINVAL;
-+
-+ qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
-+ if (!qmp->phys)
-+ return -ENOMEM;
-+
-+ pm_runtime_set_active(dev);
-+ pm_runtime_enable(dev);
-+ /*
-+ * Prevent runtime pm from being ON by default. Users can enable
-+ * it using power/control in sysfs.
-+ */
-+ pm_runtime_forbid(dev);
-+
-+ id = 0;
-+ for_each_available_child_of_node(dev->of_node, child) {
-+ if (of_node_name_eq(child, "dp-phy")) {
-+ cfg = dp_cfg;
-+ serdes = dp_serdes;
-+ } else if (of_node_name_eq(child, "usb3-phy")) {
-+ cfg = usb_cfg;
-+ serdes = usb_serdes;
-+ }
-+
-+ /* Create per-lane phy */
-+ ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg);
-+ if (ret) {
-+ dev_err(dev, "failed to create lane%d phy, %d\n",
-+ id, ret);
-+ goto err_node_put;
-+ }
-+
-+ /*
-+ * Register the pipe clock provided by phy.
-+ * See function description to see details of this pipe clock.
-+ */
-+ if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) {
-+ ret = phy_pipe_clk_register(qmp, child);
-+ if (ret) {
-+ dev_err(qmp->dev,
-+ "failed to register pipe clock source\n");
-+ goto err_node_put;
-+ }
-+ } else if (cfg->type == PHY_TYPE_DP) {
-+ ret = phy_dp_clks_register(qmp, qmp->phys[id], child);
-+ if (ret) {
-+ dev_err(qmp->dev,
-+ "failed to register DP clock source\n");
-+ goto err_node_put;
-+ }
-+ }
-+ id++;
-+ }
-+
-+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
-+ if (!IS_ERR(phy_provider))
-+ dev_info(dev, "Registered Qcom-QMP phy\n");
-+ else
-+ pm_runtime_disable(dev);
-+
-+ return PTR_ERR_OR_ZERO(phy_provider);
-+
-+err_node_put:
-+ pm_runtime_disable(dev);
-+ of_node_put(child);
-+ return ret;
-+}
-+
-+static struct platform_driver qcom_qmp_phy_driver = {
-+ .probe = qcom_qmp_phy_probe,
-+ .driver = {
-+ .name = "qcom-qmp-phy",
-+ .pm = &qcom_qmp_phy_pm_ops,
-+ .of_match_table = qcom_qmp_phy_of_match_table,
-+ },
-+};
-+
-+module_platform_driver(qcom_qmp_phy_driver);
-+
-+MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
-+MODULE_DESCRIPTION("Qualcomm QMP PHY driver");
-+MODULE_LICENSE("GPL v2");
-diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
-new file mode 100644
-index 000000000000..c7309e981bfb
---- /dev/null
-+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
-@@ -0,0 +1,6350 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/clk-provider.h>
-+#include <linux/delay.h>
-+#include <linux/err.h>
-+#include <linux/io.h>
-+#include <linux/iopoll.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/of_device.h>
-+#include <linux/of_address.h>
-+#include <linux/phy/phy.h>
-+#include <linux/platform_device.h>
-+#include <linux/regulator/consumer.h>
-+#include <linux/reset.h>
-+#include <linux/slab.h>
-+
-+#include <dt-bindings/phy/phy.h>
-+
-+#include "phy-qcom-qmp.h"
-+
-+/* QPHY_SW_RESET bit */
-+#define SW_RESET BIT(0)
-+/* QPHY_POWER_DOWN_CONTROL */
-+#define SW_PWRDN BIT(0)
-+#define REFCLK_DRV_DSBL BIT(1)
-+/* QPHY_START_CONTROL bits */
-+#define SERDES_START BIT(0)
-+#define PCS_START BIT(1)
-+#define PLL_READY_GATE_EN BIT(3)
-+/* QPHY_PCS_STATUS bit */
-+#define PHYSTATUS BIT(6)
-+#define PHYSTATUS_4_20 BIT(7)
-+/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */
-+#define PCS_READY BIT(0)
-+
-+/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
-+/* DP PHY soft reset */
-+#define SW_DPPHY_RESET BIT(0)
-+/* mux to select DP PHY reset control, 0:HW control, 1: software reset */
-+#define SW_DPPHY_RESET_MUX BIT(1)
-+/* USB3 PHY soft reset */
-+#define SW_USB3PHY_RESET BIT(2)
-+/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
-+#define SW_USB3PHY_RESET_MUX BIT(3)
-+
-+/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
-+#define USB3_MODE BIT(0) /* enables USB3 mode */
-+#define DP_MODE BIT(1) /* enables DP mode */
-+
-+/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
-+#define ARCVR_DTCT_EN BIT(0)
-+#define ALFPS_DTCT_EN BIT(1)
-+#define ARCVR_DTCT_EVENT_SEL BIT(4)
-+
-+/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
-+#define IRQ_CLEAR BIT(0)
-+
-+/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
-+#define RCVR_DETECT BIT(0)
-+
-+/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
-+#define CLAMP_EN BIT(0) /* enables i/o clamp_n */
-+
-+#define PHY_INIT_COMPLETE_TIMEOUT 10000
-+#define POWER_DOWN_DELAY_US_MIN 10
-+#define POWER_DOWN_DELAY_US_MAX 11
-+
-+#define MAX_PROP_NAME 32
-+
-+/* Define the assumed distance between lanes for underspecified device trees. */
-+#define QMP_PHY_LEGACY_LANE_STRIDE 0x400
-+
-+struct qmp_phy_init_tbl {
-+ unsigned int offset;
-+ unsigned int val;
-+ /*
-+ * register part of layout ?
-+ * if yes, then offset gives index in the reg-layout
-+ */
-+ bool in_layout;
-+ /*
-+ * mask of lanes for which this register is written
-+ * for cases when second lane needs different values
-+ */
-+ u8 lane_mask;
-+};
-+
-+#define QMP_PHY_INIT_CFG(o, v) \
-+ { \
-+ .offset = o, \
-+ .val = v, \
-+ .lane_mask = 0xff, \
-+ }
-+
-+#define QMP_PHY_INIT_CFG_L(o, v) \
-+ { \
-+ .offset = o, \
-+ .val = v, \
-+ .in_layout = true, \
-+ .lane_mask = 0xff, \
-+ }
-+
-+#define QMP_PHY_INIT_CFG_LANE(o, v, l) \
-+ { \
-+ .offset = o, \
-+ .val = v, \
-+ .lane_mask = l, \
-+ }
-+
-+/* set of registers with offsets different per-PHY */
-+enum qphy_reg_layout {
-+ /* Common block control registers */
-+ QPHY_COM_SW_RESET,
-+ QPHY_COM_POWER_DOWN_CONTROL,
-+ QPHY_COM_START_CONTROL,
-+ QPHY_COM_PCS_READY_STATUS,
-+ /* PCS registers */
-+ QPHY_PLL_LOCK_CHK_DLY_TIME,
-+ QPHY_FLL_CNTRL1,
-+ QPHY_FLL_CNTRL2,
-+ QPHY_FLL_CNT_VAL_L,
-+ QPHY_FLL_CNT_VAL_H_TOL,
-+ QPHY_FLL_MAN_CODE,
-+ QPHY_SW_RESET,
-+ QPHY_START_CTRL,
-+ QPHY_PCS_READY_STATUS,
-+ QPHY_PCS_STATUS,
-+ QPHY_PCS_AUTONOMOUS_MODE_CTRL,
-+ QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
-+ QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
-+ QPHY_PCS_POWER_DOWN_CONTROL,
-+ /* PCS_MISC registers */
-+ QPHY_PCS_MISC_TYPEC_CTRL,
-+ /* Keep last to ensure regs_layout arrays are properly initialized */
-+ QPHY_LAYOUT_SIZE
-+};
-+
-+static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_START_CTRL] = 0x00,
-+ [QPHY_PCS_READY_STATUS] = 0x168,
-+};
-+
-+static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x44,
-+ [QPHY_PCS_STATUS] = 0x14,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
-+};
-+
-+static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_COM_SW_RESET] = 0x400,
-+ [QPHY_COM_POWER_DOWN_CONTROL] = 0x404,
-+ [QPHY_COM_START_CONTROL] = 0x408,
-+ [QPHY_COM_PCS_READY_STATUS] = 0x448,
-+ [QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8,
-+ [QPHY_FLL_CNTRL1] = 0xc4,
-+ [QPHY_FLL_CNTRL2] = 0xc8,
-+ [QPHY_FLL_CNT_VAL_L] = 0xcc,
-+ [QPHY_FLL_CNT_VAL_H_TOL] = 0xd0,
-+ [QPHY_FLL_MAN_CODE] = 0xd4,
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_STATUS] = 0x174,
-+};
-+
-+static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_FLL_CNTRL1] = 0xc0,
-+ [QPHY_FLL_CNTRL2] = 0xc4,
-+ [QPHY_FLL_CNT_VAL_L] = 0xc8,
-+ [QPHY_FLL_CNT_VAL_H_TOL] = 0xcc,
-+ [QPHY_FLL_MAN_CODE] = 0xd0,
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_STATUS] = 0x17c,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
-+};
-+
-+static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_STATUS] = 0x174,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
-+};
-+
-+static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_STATUS] = 0x174,
-+};
-+
-+static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_STATUS] = 0x2ac,
-+};
-+
-+static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x44,
-+ [QPHY_PCS_STATUS] = 0x14,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314,
-+};
-+
-+static const unsigned int qmp_v4_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x44,
-+ [QPHY_PCS_STATUS] = 0x14,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x608,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x614,
-+};
-+
-+static const unsigned int sm8350_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x44,
-+ [QPHY_PCS_STATUS] = 0x14,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x1008,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x1014,
-+};
-+
-+static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0xd8,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc,
-+ [QPHY_PCS_STATUS] = 0x174,
-+ [QPHY_PCS_MISC_TYPEC_CTRL] = 0x00,
-+};
-+
-+static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_START_CTRL] = 0x00,
-+ [QPHY_PCS_READY_STATUS] = 0x160,
-+};
-+
-+static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_START_CTRL] = 0x00,
-+ [QPHY_PCS_READY_STATUS] = 0x168,
-+};
-+
-+static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x44,
-+ [QPHY_PCS_STATUS] = 0x14,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
-+};
-+
-+static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START,
-+ [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS,
-+ [QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET,
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
-+ /* PLL and Loop filter settings */
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-+ /* SSC settings */
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
-+ QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
-+
-+ QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
-+
-+ QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
-+ QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
-+ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
-+ /* PLL and Loop filter settings */
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-+ /* SSC settings */
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
-+ /* FLL settings */
-+ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03),
-+ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02),
-+ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42),
-+ QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
-+
-+ /* Lock Det settings */
-+ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x61),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d),
-+ QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10),
-+ QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_PRE, 0x00),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_POST, 0x58),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
-+ QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
-+ QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
-+ QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
-+ QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
-+ QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
-+ QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
-+ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
-+ QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
-+ QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = {
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
-+ /* FLL settings */
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+
-+ /* Lock Det settings */
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
-+ /* FLL settings */
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+
-+ /* Lock Det settings */
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
-+};
-+
-+static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
-+
-+ /* Rate B */
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),
-+};
-+
-+static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B),
-+};
-+
-+static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_RX_PWM_GEAR_BAND, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_CTRL2, 0x6d),
-+ QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_DRV_LVL, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_DRV_LVL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
-+ QMP_PHY_INIT_CFG(QPHY_RX_SYM_RESYNC_CTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
-+ QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
-+
-+ /* Rate B */
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
-+
-+ /* Rate B */
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
-+
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
-+ /* Lock Det settings */
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20),
-+};
-+
-+static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
-+};
-+
-+static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5),
-+};
-+
-+static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
-+};
-+
-+static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),
-+};
-+
-+static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
-+
-+ /* Rate B */
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+};
-+
-+static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01),
-+};
-+
-+static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
-+
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05),
-+
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
-+
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
-+
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
-+};
-+
-+/* Register names should be validated, they might be different for this PHY */
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
-+};
-+
-+struct qmp_phy;
-+
-+/* struct qmp_phy_cfg - per-PHY initialization config */
-+struct qmp_phy_cfg {
-+ /* phy-type - PCIE/UFS/USB */
-+ unsigned int type;
-+ /* number of lanes provided by phy */
-+ int nlanes;
-+
-+ /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
-+ const struct qmp_phy_init_tbl *serdes_tbl;
-+ int serdes_tbl_num;
-+ const struct qmp_phy_init_tbl *serdes_tbl_sec;
-+ int serdes_tbl_num_sec;
-+ const struct qmp_phy_init_tbl *tx_tbl;
-+ int tx_tbl_num;
-+ const struct qmp_phy_init_tbl *tx_tbl_sec;
-+ int tx_tbl_num_sec;
-+ const struct qmp_phy_init_tbl *rx_tbl;
-+ int rx_tbl_num;
-+ const struct qmp_phy_init_tbl *rx_tbl_sec;
-+ int rx_tbl_num_sec;
-+ const struct qmp_phy_init_tbl *pcs_tbl;
-+ int pcs_tbl_num;
-+ const struct qmp_phy_init_tbl *pcs_tbl_sec;
-+ int pcs_tbl_num_sec;
-+ const struct qmp_phy_init_tbl *pcs_misc_tbl;
-+ int pcs_misc_tbl_num;
-+ const struct qmp_phy_init_tbl *pcs_misc_tbl_sec;
-+ int pcs_misc_tbl_num_sec;
-+
-+ /* Init sequence for DP PHY block link rates */
-+ const struct qmp_phy_init_tbl *serdes_tbl_rbr;
-+ int serdes_tbl_rbr_num;
-+ const struct qmp_phy_init_tbl *serdes_tbl_hbr;
-+ int serdes_tbl_hbr_num;
-+ const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
-+ int serdes_tbl_hbr2_num;
-+ const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
-+ int serdes_tbl_hbr3_num;
-+
-+ /* DP PHY callbacks */
-+ int (*configure_dp_phy)(struct qmp_phy *qphy);
-+ void (*configure_dp_tx)(struct qmp_phy *qphy);
-+ int (*calibrate_dp_phy)(struct qmp_phy *qphy);
-+ void (*dp_aux_init)(struct qmp_phy *qphy);
-+
-+ /* clock ids to be requested */
-+ const char * const *clk_list;
-+ int num_clks;
-+ /* resets to be requested */
-+ const char * const *reset_list;
-+ int num_resets;
-+ /* regulators to be requested */
-+ const char * const *vreg_list;
-+ int num_vregs;
-+
-+ /* array of registers with different offsets */
-+ const unsigned int *regs;
-+
-+ unsigned int start_ctrl;
-+ unsigned int pwrdn_ctrl;
-+ unsigned int mask_com_pcs_ready;
-+ /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
-+ unsigned int phy_status;
-+
-+ /* true, if PHY has a separate PHY_COM control block */
-+ bool has_phy_com_ctrl;
-+ /* true, if PHY has a reset for individual lanes */
-+ bool has_lane_rst;
-+ /* true, if PHY needs delay after POWER_DOWN */
-+ bool has_pwrdn_delay;
-+ /* power_down delay in usec */
-+ int pwrdn_delay_min;
-+ int pwrdn_delay_max;
-+
-+ /* true, if PHY has a separate DP_COM control block */
-+ bool has_phy_dp_com_ctrl;
-+ /* true, if PHY has secondary tx/rx lanes to be configured */
-+ bool is_dual_lane_phy;
-+
-+ /* true, if PCS block has no separate SW_RESET register */
-+ bool no_pcs_sw_reset;
-+};
-+
-+struct qmp_phy_combo_cfg {
-+ const struct qmp_phy_cfg *usb_cfg;
-+ const struct qmp_phy_cfg *dp_cfg;
-+};
-+
-+/**
-+ * struct qmp_phy - per-lane phy descriptor
-+ *
-+ * @phy: generic phy
-+ * @cfg: phy specific configuration
-+ * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
-+ * @tx: iomapped memory space for lane's tx
-+ * @rx: iomapped memory space for lane's rx
-+ * @pcs: iomapped memory space for lane's pcs
-+ * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
-+ * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
-+ * @pcs_misc: iomapped memory space for lane's pcs_misc
-+ * @pipe_clk: pipe clock
-+ * @index: lane index
-+ * @qmp: QMP phy to which this lane belongs
-+ * @lane_rst: lane's reset controller
-+ * @mode: current PHY mode
-+ * @dp_aux_cfg: Display port aux config
-+ * @dp_opts: Display port optional config
-+ * @dp_clks: Display port clocks
-+ */
-+struct qmp_phy {
-+ struct phy *phy;
-+ const struct qmp_phy_cfg *cfg;
-+ void __iomem *serdes;
-+ void __iomem *tx;
-+ void __iomem *rx;
-+ void __iomem *pcs;
-+ void __iomem *tx2;
-+ void __iomem *rx2;
-+ void __iomem *pcs_misc;
-+ struct clk *pipe_clk;
-+ unsigned int index;
-+ struct qcom_qmp *qmp;
-+ struct reset_control *lane_rst;
-+ enum phy_mode mode;
-+ unsigned int dp_aux_cfg;
-+ struct phy_configure_opts_dp dp_opts;
-+ struct qmp_phy_dp_clks *dp_clks;
-+};
-+
-+struct qmp_phy_dp_clks {
-+ struct qmp_phy *qphy;
-+ struct clk_hw dp_link_hw;
-+ struct clk_hw dp_pixel_hw;
-+};
-+
-+/**
-+ * struct qcom_qmp - structure holding QMP phy block attributes
-+ *
-+ * @dev: device
-+ * @dp_com: iomapped memory space for phy's dp_com control block
-+ *
-+ * @clks: array of clocks required by phy
-+ * @resets: array of resets required by phy
-+ * @vregs: regulator supplies bulk data
-+ *
-+ * @phys: array of per-lane phy descriptors
-+ * @phy_mutex: mutex lock for PHY common block initialization
-+ * @init_count: phy common block initialization count
-+ * @ufs_reset: optional UFS PHY reset handle
-+ */
-+struct qcom_qmp {
-+ struct device *dev;
-+ void __iomem *dp_com;
-+
-+ struct clk_bulk_data *clks;
-+ struct reset_control **resets;
-+ struct regulator_bulk_data *vregs;
-+
-+ struct qmp_phy **phys;
-+
-+ struct mutex phy_mutex;
-+ int init_count;
-+
-+ struct reset_control *ufs_reset;
-+};
-+
-+static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy);
-+static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy);
-+static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy);
-+static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy);
-+
-+static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy);
-+static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy);
-+static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy);
-+static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy);
-+
-+static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
-+{
-+ u32 reg;
-+
-+ reg = readl(base + offset);
-+ reg |= val;
-+ writel(reg, base + offset);
-+
-+ /* ensure that above write is through */
-+ readl(base + offset);
-+}
-+
-+static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
-+{
-+ u32 reg;
-+
-+ reg = readl(base + offset);
-+ reg &= ~val;
-+ writel(reg, base + offset);
-+
-+ /* ensure that above write is through */
-+ readl(base + offset);
-+}
-+
-+/* list of clocks required by phy */
-+static const char * const msm8996_phy_clk_l[] = {
-+ "aux", "cfg_ahb", "ref",
-+};
-+
-+static const char * const msm8996_ufs_phy_clk_l[] = {
-+ "ref",
-+};
-+
-+static const char * const qmp_v3_phy_clk_l[] = {
-+ "aux", "cfg_ahb", "ref", "com_aux",
-+};
-+
-+static const char * const sdm845_pciephy_clk_l[] = {
-+ "aux", "cfg_ahb", "ref", "refgen",
-+};
-+
-+static const char * const qmp_v4_phy_clk_l[] = {
-+ "aux", "ref_clk_src", "ref", "com_aux",
-+};
-+
-+/* the primary usb3 phy on sm8250 doesn't have a ref clock */
-+static const char * const qmp_v4_sm8250_usbphy_clk_l[] = {
-+ "aux", "ref_clk_src", "com_aux"
-+};
-+
-+static const char * const sm8450_ufs_phy_clk_l[] = {
-+ "qref", "ref", "ref_aux",
-+};
-+
-+static const char * const sdm845_ufs_phy_clk_l[] = {
-+ "ref", "ref_aux",
-+};
-+
-+/* usb3 phy on sdx55 doesn't have com_aux clock */
-+static const char * const qmp_v4_sdx55_usbphy_clk_l[] = {
-+ "aux", "cfg_ahb", "ref"
-+};
-+
-+static const char * const qcm2290_usb3phy_clk_l[] = {
-+ "cfg_ahb", "ref", "com_aux",
-+};
-+
-+/* list of resets */
-+static const char * const msm8996_pciephy_reset_l[] = {
-+ "phy", "common", "cfg",
-+};
-+
-+static const char * const msm8996_usb3phy_reset_l[] = {
-+ "phy", "common",
-+};
-+
-+static const char * const sc7180_usb3phy_reset_l[] = {
-+ "phy",
-+};
-+
-+static const char * const qcm2290_usb3phy_reset_l[] = {
-+ "phy_phy", "phy",
-+};
-+
-+static const char * const sdm845_pciephy_reset_l[] = {
-+ "phy",
-+};
-+
-+/* list of regulators */
-+static const char * const qmp_phy_vreg_l[] = {
-+ "vdda-phy", "vdda-pll",
-+};
-+
-+static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = ipq8074_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
-+ .tx_tbl = msm8996_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
-+ .rx_tbl = ipq8074_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
-+ .pcs_tbl = ipq8074_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
-+ .clk_list = msm8996_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+};
-+
-+static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 3,
-+
-+ .serdes_tbl = msm8996_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
-+ .tx_tbl = msm8996_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8996_pcie_tx_tbl),
-+ .rx_tbl = msm8996_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(msm8996_pcie_rx_tbl),
-+ .pcs_tbl = msm8996_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
-+ .clk_list = msm8996_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-+ .reset_list = msm8996_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = pciephy_regs_layout,
-+
-+ .start_ctrl = PCS_START | PLL_READY_GATE_EN,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .mask_com_pcs_ready = PCS_READY,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_phy_com_ctrl = true,
-+ .has_lane_rst = true,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg msm8996_ufs_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = msm8996_ufs_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(msm8996_ufs_serdes_tbl),
-+ .tx_tbl = msm8996_ufs_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8996_ufs_tx_tbl),
-+ .rx_tbl = msm8996_ufs_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(msm8996_ufs_rx_tbl),
-+
-+ .clk_list = msm8996_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
-+
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+
-+ .regs = msm8996_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .no_pcs_sw_reset = true,
-+};
-+
-+static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = msm8996_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
-+ .tx_tbl = msm8996_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
-+ .rx_tbl = msm8996_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl),
-+ .pcs_tbl = msm8996_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
-+ .clk_list = msm8996_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+};
-+
-+static const char * const ipq8074_pciephy_clk_l[] = {
-+ "aux", "cfg_ahb",
-+};
-+/* list of resets */
-+static const char * const ipq8074_pciephy_reset_l[] = {
-+ "phy", "common",
-+};
-+
-+static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = ipq8074_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
-+ .tx_tbl = ipq8074_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
-+ .rx_tbl = ipq8074_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
-+ .pcs_tbl = ipq8074_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
-+ .clk_list = ipq8074_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
-+ .reset_list = ipq8074_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
-+ .vreg_list = NULL,
-+ .num_vregs = 0,
-+ .regs = pciephy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_phy_com_ctrl = false,
-+ .has_lane_rst = false,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = ipq6018_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl),
-+ .tx_tbl = ipq6018_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl),
-+ .rx_tbl = ipq6018_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
-+ .pcs_tbl = ipq6018_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
-+ .clk_list = ipq8074_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
-+ .reset_list = ipq8074_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
-+ .vreg_list = NULL,
-+ .num_vregs = 0,
-+ .regs = ipq_pciephy_gen3_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+
-+ .has_phy_com_ctrl = false,
-+ .has_lane_rst = false,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sdm845_qmp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
-+ .tx_tbl = sdm845_qmp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),
-+ .rx_tbl = sdm845_qmp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),
-+ .pcs_tbl = sdm845_qmp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sdm845_qmp_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sdm845_qmp_pciephy_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sdm845_qhp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
-+ .tx_tbl = sdm845_qhp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
-+ .rx_tbl = sdm845_qhp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl),
-+ .pcs_tbl = sdm845_qhp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sdm845_qhp_pciephy_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
-+ .serdes_tbl_sec = sm8250_qmp_gen3x1_pcie_serdes_tbl,
-+ .serdes_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
-+ .tx_tbl = sm8250_qmp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
-+ .rx_tbl = sm8250_qmp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
-+ .rx_tbl_sec = sm8250_qmp_gen3x1_pcie_rx_tbl,
-+ .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),
-+ .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
-+ .pcs_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_tbl,
-+ .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
-+ .pcs_misc_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
-+ .tx_tbl = sm8250_qmp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
-+ .tx_tbl_sec = sm8250_qmp_gen3x2_pcie_tx_tbl,
-+ .tx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),
-+ .rx_tbl = sm8250_qmp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
-+ .rx_tbl_sec = sm8250_qmp_gen3x2_pcie_rx_tbl,
-+ .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl),
-+ .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
-+ .pcs_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_tbl,
-+ .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
-+ .pcs_misc_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v3_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
-+ .tx_tbl = qmp_v3_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
-+ .rx_tbl = qmp_v3_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
-+ .pcs_tbl = qmp_v3_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
-+ .clk_list = qmp_v3_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v3_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
-+ .tx_tbl = qmp_v3_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
-+ .rx_tbl = qmp_v3_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
-+ .pcs_tbl = qmp_v3_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
-+ .clk_list = qmp_v3_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-+ .reset_list = sc7180_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sc7180_dpphy_cfg = {
-+ .type = PHY_TYPE_DP,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v3_dp_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
-+ .tx_tbl = qmp_v3_dp_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
-+
-+ .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr,
-+ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
-+ .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr,
-+ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
-+ .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2,
-+ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
-+ .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3,
-+ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
-+
-+ .clk_list = qmp_v3_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-+ .reset_list = sc7180_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+
-+ .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init,
-+ .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx,
-+ .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy,
-+ .calibrate_dp_phy = qcom_qmp_v3_dp_phy_calibrate,
-+};
-+
-+static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = {
-+ .usb_cfg = &sc7180_usb3phy_cfg,
-+ .dp_cfg = &sc7180_dpphy_cfg,
-+};
-+
-+static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
-+ .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v3_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sdm845_ufsphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
-+ .tx_tbl = sdm845_ufsphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
-+ .rx_tbl = sdm845_ufsphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
-+ .pcs_tbl = sdm845_ufsphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
-+ .clk_list = sdm845_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sdm845_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+ .no_pcs_sw_reset = true,
-+};
-+
-+static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm6115_ufsphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl),
-+ .tx_tbl = sm6115_ufsphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_tx_tbl),
-+ .rx_tbl = sm6115_ufsphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_rx_tbl),
-+ .pcs_tbl = sm6115_ufsphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl),
-+ .clk_list = sdm845_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm6115_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+
-+ .is_dual_lane_phy = false,
-+ .no_pcs_sw_reset = true,
-+};
-+
-+static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = msm8998_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
-+ .tx_tbl = msm8998_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8998_pcie_tx_tbl),
-+ .rx_tbl = msm8998_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(msm8998_pcie_rx_tbl),
-+ .pcs_tbl = msm8998_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
-+ .clk_list = msm8996_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-+ .reset_list = ipq8074_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = pciephy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+};
-+
-+static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = msm8998_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
-+ .tx_tbl = msm8998_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl),
-+ .rx_tbl = msm8998_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl),
-+ .pcs_tbl = msm8998_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
-+ .clk_list = msm8996_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sm8150_ufsphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl),
-+ .tx_tbl = sm8150_ufsphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx_tbl),
-+ .rx_tbl = sm8150_ufsphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx_tbl),
-+ .pcs_tbl = sm8150_ufsphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl),
-+ .clk_list = sdm845_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8150_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
-+ .tx_tbl = sm8150_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl),
-+ .rx_tbl = sm8150_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl),
-+ .pcs_tbl = sm8150_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
-+ .clk_list = qmp_v4_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sc8180x_qmp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl),
-+ .tx_tbl = sc8180x_qmp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl),
-+ .rx_tbl = sc8180x_qmp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl),
-+ .pcs_tbl = sc8180x_qmp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sc8180x_qmp_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sc8180x_dpphy_cfg = {
-+ .type = PHY_TYPE_DP,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v4_dp_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
-+ .tx_tbl = qmp_v4_dp_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
-+
-+ .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
-+ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
-+ .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
-+ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
-+ .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
-+ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
-+ .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
-+ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
-+
-+ .clk_list = qmp_v3_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-+ .reset_list = sc7180_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+
-+ .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
-+ .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
-+ .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
-+ .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
-+};
-+
-+static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = {
-+ .usb_cfg = &sm8150_usb3phy_cfg,
-+ .dp_cfg = &sc8180x_dpphy_cfg,
-+};
-+
-+static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = sm8150_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),
-+ .rx_tbl = sm8150_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = sm8150_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v4_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3_uniphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
-+ .tx_tbl = sm8250_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl),
-+ .rx_tbl = sm8250_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl),
-+ .pcs_tbl = sm8250_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
-+ .clk_list = qmp_v4_sm8250_usbphy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = sm8250_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),
-+ .rx_tbl = sm8250_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v4_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3_uniphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sm8250_dpphy_cfg = {
-+ .type = PHY_TYPE_DP,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v4_dp_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
-+ .tx_tbl = qmp_v4_dp_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
-+
-+ .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
-+ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
-+ .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
-+ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
-+ .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
-+ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
-+ .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
-+ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
-+
-+ .clk_list = qmp_v4_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3phy_regs_layout,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+
-+ .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
-+ .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
-+ .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
-+ .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
-+};
-+
-+static const struct qmp_phy_combo_cfg sm8250_usb3dpphy_cfg = {
-+ .usb_cfg = &sm8250_usb3phy_cfg,
-+ .dp_cfg = &sm8250_dpphy_cfg,
-+};
-+
-+static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = sdx55_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl),
-+ .rx_tbl = sdx55_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v4_sdx55_usbphy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3_uniphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sdx55_qmp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl),
-+ .tx_tbl = sdx55_qmp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl),
-+ .rx_tbl = sdx55_qmp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl),
-+ .pcs_tbl = sdx55_qmp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sdx55_qmp_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS_4_20,
-+
-+ .is_dual_lane_phy = true,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = sdx65_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl),
-+ .rx_tbl = sdx65_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v4_sdx55_usbphy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8350_usb3_uniphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sm8350_ufsphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
-+ .tx_tbl = sm8350_ufsphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
-+ .rx_tbl = sm8350_ufsphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
-+ .pcs_tbl = sm8350_ufsphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
-+ .clk_list = sdm845_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8150_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
-+ .tx_tbl = sm8350_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl),
-+ .rx_tbl = sm8350_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl),
-+ .pcs_tbl = sm8350_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl),
-+ .clk_list = qmp_v4_sm8250_usbphy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = sm8350_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),
-+ .rx_tbl = sm8350_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v4_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8350_usb3_uniphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sm8350_ufsphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
-+ .tx_tbl = sm8350_ufsphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
-+ .rx_tbl = sm8350_ufsphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
-+ .pcs_tbl = sm8350_ufsphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
-+ .clk_list = sm8450_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8150_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8450_qmp_gen3x1_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl),
-+ .tx_tbl = sm8450_qmp_gen3x1_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl),
-+ .rx_tbl = sm8450_qmp_gen3x1_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl),
-+ .pcs_tbl = sm8450_qmp_gen3x1_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sm8450_qmp_gen4x2_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl),
-+ .tx_tbl = sm8450_qmp_gen4x2_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl),
-+ .rx_tbl = sm8450_qmp_gen4x2_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl),
-+ .pcs_tbl = sm8450_qmp_gen4x2_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS_4_20,
-+
-+ .is_dual_lane_phy = true,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qcm2290_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl),
-+ .tx_tbl = qcm2290_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl),
-+ .rx_tbl = qcm2290_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(qcm2290_usb3_rx_tbl),
-+ .pcs_tbl = qcm2290_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl),
-+ .clk_list = qcm2290_usb3phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qcm2290_usb3phy_clk_l),
-+ .reset_list = qcm2290_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qcm2290_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+};
-+
-+static void qcom_qmp_phy_configure_lane(void __iomem *base,
-+ const unsigned int *regs,
-+ const struct qmp_phy_init_tbl tbl[],
-+ int num,
-+ u8 lane_mask)
-+{
-+ int i;
-+ const struct qmp_phy_init_tbl *t = tbl;
-+
-+ if (!t)
-+ return;
-+
-+ for (i = 0; i < num; i++, t++) {
-+ if (!(t->lane_mask & lane_mask))
-+ continue;
-+
-+ if (t->in_layout)
-+ writel(t->val, base + regs[t->offset]);
-+ else
-+ writel(t->val, base + t->offset);
-+ }
-+}
-+
-+static void qcom_qmp_phy_configure(void __iomem *base,
-+ const unsigned int *regs,
-+ const struct qmp_phy_init_tbl tbl[],
-+ int num)
-+{
-+ qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff);
-+}
-+
-+static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
-+{
-+ struct qcom_qmp *qmp = qphy->qmp;
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *serdes = qphy->serdes;
-+ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-+ const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
-+ int serdes_tbl_num = cfg->serdes_tbl_num;
-+ int ret;
-+
-+ qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
-+ if (cfg->serdes_tbl_sec)
-+ qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
-+ cfg->serdes_tbl_num_sec);
-+
-+ if (cfg->type == PHY_TYPE_DP) {
-+ switch (dp_opts->link_rate) {
-+ case 1620:
-+ qcom_qmp_phy_configure(serdes, cfg->regs,
-+ cfg->serdes_tbl_rbr,
-+ cfg->serdes_tbl_rbr_num);
-+ break;
-+ case 2700:
-+ qcom_qmp_phy_configure(serdes, cfg->regs,
-+ cfg->serdes_tbl_hbr,
-+ cfg->serdes_tbl_hbr_num);
-+ break;
-+ case 5400:
-+ qcom_qmp_phy_configure(serdes, cfg->regs,
-+ cfg->serdes_tbl_hbr2,
-+ cfg->serdes_tbl_hbr2_num);
-+ break;
-+ case 8100:
-+ qcom_qmp_phy_configure(serdes, cfg->regs,
-+ cfg->serdes_tbl_hbr3,
-+ cfg->serdes_tbl_hbr3_num);
-+ break;
-+ default:
-+ /* Other link rates aren't supported */
-+ return -EINVAL;
-+ }
-+ }
-+
-+
-+ if (cfg->has_phy_com_ctrl) {
-+ void __iomem *status;
-+ unsigned int mask, val;
-+
-+ qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
-+ qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
-+ SERDES_START | PCS_START);
-+
-+ status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
-+ mask = cfg->mask_com_pcs_ready;
-+
-+ ret = readl_poll_timeout(status, val, (val & mask), 10,
-+ PHY_INIT_COMPLETE_TIMEOUT);
-+ if (ret) {
-+ dev_err(qmp->dev,
-+ "phy common block init timed-out\n");
-+ return ret;
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy)
-+{
-+ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
-+ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
-+ qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+
-+ /* Turn on BIAS current for PHY/PLL */
-+ writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
-+ QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
-+ qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
-+
-+ writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+
-+ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
-+ DP_PHY_PD_CTL_LANE_0_1_PWRDN |
-+ DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
-+ DP_PHY_PD_CTL_DP_CLAMP_EN,
-+ qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+
-+ writel(QSERDES_V3_COM_BIAS_EN |
-+ QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
-+ QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL |
-+ QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
-+ qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
-+
-+ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
-+ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-+ writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
-+ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
-+ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
-+ writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
-+ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
-+ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
-+ writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
-+ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
-+ qphy->dp_aux_cfg = 0;
-+
-+ writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
-+ PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
-+ PHY_AUX_REQ_ERR_MASK,
-+ qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
-+}
-+
-+static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = {
-+ { 0x00, 0x0c, 0x15, 0x1a },
-+ { 0x02, 0x0e, 0x16, 0xff },
-+ { 0x02, 0x11, 0xff, 0xff },
-+ { 0x04, 0xff, 0xff, 0xff }
-+};
-+
-+static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = {
-+ { 0x02, 0x12, 0x16, 0x1a },
-+ { 0x09, 0x19, 0x1f, 0xff },
-+ { 0x10, 0x1f, 0xff, 0xff },
-+ { 0x1f, 0xff, 0xff, 0xff }
-+};
-+
-+static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = {
-+ { 0x00, 0x0c, 0x14, 0x19 },
-+ { 0x00, 0x0b, 0x12, 0xff },
-+ { 0x00, 0x0b, 0xff, 0xff },
-+ { 0x04, 0xff, 0xff, 0xff }
-+};
-+
-+static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = {
-+ { 0x08, 0x0f, 0x16, 0x1f },
-+ { 0x11, 0x1e, 0x1f, 0xff },
-+ { 0x19, 0x1f, 0xff, 0xff },
-+ { 0x1f, 0xff, 0xff, 0xff }
-+};
-+
-+static int qcom_qmp_phy_configure_dp_swing(struct qmp_phy *qphy,
-+ unsigned int drv_lvl_reg, unsigned int emp_post_reg)
-+{
-+ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-+ unsigned int v_level = 0, p_level = 0;
-+ u8 voltage_swing_cfg, pre_emphasis_cfg;
-+ int i;
-+
-+ for (i = 0; i < dp_opts->lanes; i++) {
-+ v_level = max(v_level, dp_opts->voltage[i]);
-+ p_level = max(p_level, dp_opts->pre[i]);
-+ }
-+
-+ if (dp_opts->link_rate <= 2700) {
-+ voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level];
-+ pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level];
-+ } else {
-+ voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr3_hbr2[v_level][p_level];
-+ pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr3_hbr2[v_level][p_level];
-+ }
-+
-+ /* TODO: Move check to config check */
-+ if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF)
-+ return -EINVAL;
-+
-+ /* Enable MUX to use Cursor values from these registers */
-+ voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
-+ pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
-+
-+ writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg);
-+ writel(pre_emphasis_cfg, qphy->tx + emp_post_reg);
-+ writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg);
-+ writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg);
-+
-+ return 0;
-+}
-+
-+static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy)
-+{
-+ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-+ u32 bias_en, drvr_en;
-+
-+ if (qcom_qmp_phy_configure_dp_swing(qphy,
-+ QSERDES_V3_TX_TX_DRV_LVL,
-+ QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0)
-+ return;
-+
-+ if (dp_opts->lanes == 1) {
-+ bias_en = 0x3e;
-+ drvr_en = 0x13;
-+ } else {
-+ bias_en = 0x3f;
-+ drvr_en = 0x10;
-+ }
-+
-+ writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN);
-+ writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
-+ writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN);
-+ writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
-+}
-+
-+static bool qcom_qmp_phy_configure_dp_mode(struct qmp_phy *qphy)
-+{
-+ u32 val;
-+ bool reverse = false;
-+
-+ val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
-+ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN;
-+
-+ /*
-+ * TODO: Assume orientation is CC1 for now and two lanes, need to
-+ * use type-c connector to understand orientation and lanes.
-+ *
-+ * Otherwise val changes to be like below if this code understood
-+ * the orientation of the type-c cable.
-+ *
-+ * if (lane_cnt == 4 || orientation == ORIENTATION_CC2)
-+ * val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN;
-+ * if (lane_cnt == 4 || orientation == ORIENTATION_CC1)
-+ * val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
-+ * if (orientation == ORIENTATION_CC2)
-+ * writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
-+ */
-+ val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
-+ writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+
-+ writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE);
-+
-+ return reverse;
-+}
-+
-+static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy)
-+{
-+ const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
-+ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-+ u32 phy_vco_div, status;
-+ unsigned long pixel_freq;
-+
-+ qcom_qmp_phy_configure_dp_mode(qphy);
-+
-+ writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
-+ writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
-+
-+ switch (dp_opts->link_rate) {
-+ case 1620:
-+ phy_vco_div = 0x1;
-+ pixel_freq = 1620000000UL / 2;
-+ break;
-+ case 2700:
-+ phy_vco_div = 0x1;
-+ pixel_freq = 2700000000UL / 2;
-+ break;
-+ case 5400:
-+ phy_vco_div = 0x2;
-+ pixel_freq = 5400000000UL / 4;
-+ break;
-+ case 8100:
-+ phy_vco_div = 0x0;
-+ pixel_freq = 8100000000UL / 6;
-+ break;
-+ default:
-+ /* Other link rates aren't supported */
-+ return -EINVAL;
-+ }
-+ writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV);
-+
-+ clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
-+ clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
-+
-+ writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
-+ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL);
-+
-+ if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS,
-+ status,
-+ ((status & BIT(0)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
-+ status,
-+ ((status & BIT(1)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ udelay(2000);
-+ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
-+ status,
-+ ((status & BIT(1)) > 0),
-+ 500,
-+ 10000);
-+}
-+
-+/*
-+ * We need to calibrate the aux setting here as many times
-+ * as the caller tries
-+ */
-+static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy)
-+{
-+ static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d };
-+ u8 val;
-+
-+ qphy->dp_aux_cfg++;
-+ qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
-+ val = cfg1_settings[qphy->dp_aux_cfg];
-+
-+ writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-+
-+ return 0;
-+}
-+
-+static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy)
-+{
-+ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
-+ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
-+ qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+
-+ /* Turn on BIAS current for PHY/PLL */
-+ writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN);
-+
-+ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
-+ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-+ writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
-+ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
-+ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
-+ writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
-+ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
-+ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
-+ writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
-+ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
-+ qphy->dp_aux_cfg = 0;
-+
-+ writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
-+ PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
-+ PHY_AUX_REQ_ERR_MASK,
-+ qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
-+}
-+
-+static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy)
-+{
-+ /* Program default values before writing proper values */
-+ writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
-+ writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
-+
-+ writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
-+ writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
-+
-+ qcom_qmp_phy_configure_dp_swing(qphy,
-+ QSERDES_V4_TX_TX_DRV_LVL,
-+ QSERDES_V4_TX_TX_EMP_POST1_LVL);
-+}
-+
-+static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy)
-+{
-+ const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
-+ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-+ u32 phy_vco_div, status;
-+ unsigned long pixel_freq;
-+ u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
-+ bool reverse;
-+
-+ writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1);
-+
-+ reverse = qcom_qmp_phy_configure_dp_mode(qphy);
-+
-+ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-+ writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
-+
-+ writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL);
-+ writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL);
-+
-+ switch (dp_opts->link_rate) {
-+ case 1620:
-+ phy_vco_div = 0x1;
-+ pixel_freq = 1620000000UL / 2;
-+ break;
-+ case 2700:
-+ phy_vco_div = 0x1;
-+ pixel_freq = 2700000000UL / 2;
-+ break;
-+ case 5400:
-+ phy_vco_div = 0x2;
-+ pixel_freq = 5400000000UL / 4;
-+ break;
-+ case 8100:
-+ phy_vco_div = 0x0;
-+ pixel_freq = 8100000000UL / 6;
-+ break;
-+ default:
-+ /* Other link rates aren't supported */
-+ return -EINVAL;
-+ }
-+ writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV);
-+
-+ clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
-+ clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
-+
-+ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL);
-+
-+ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS,
-+ status,
-+ ((status & BIT(0)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
-+ status,
-+ ((status & BIT(0)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
-+ status,
-+ ((status & BIT(1)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
-+ status,
-+ ((status & BIT(0)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
-+ status,
-+ ((status & BIT(1)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ /*
-+ * At least for 7nm DP PHY this has to be done after enabling link
-+ * clock.
-+ */
-+
-+ if (dp_opts->lanes == 1) {
-+ bias0_en = reverse ? 0x3e : 0x15;
-+ bias1_en = reverse ? 0x15 : 0x3e;
-+ drvr0_en = reverse ? 0x13 : 0x10;
-+ drvr1_en = reverse ? 0x10 : 0x13;
-+ } else if (dp_opts->lanes == 2) {
-+ bias0_en = reverse ? 0x3f : 0x15;
-+ bias1_en = reverse ? 0x15 : 0x3f;
-+ drvr0_en = 0x10;
-+ drvr1_en = 0x10;
-+ } else {
-+ bias0_en = 0x3f;
-+ bias1_en = 0x3f;
-+ drvr0_en = 0x10;
-+ drvr1_en = 0x10;
-+ }
-+
-+ writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN);
-+ writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
-+ writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN);
-+ writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
-+
-+ writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ udelay(2000);
-+ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
-+ status,
-+ ((status & BIT(1)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV);
-+ writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV);
-+
-+ writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
-+ writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
-+
-+ writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
-+ writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
-+
-+ return 0;
-+}
-+
-+/*
-+ * We need to calibrate the aux setting here as many times
-+ * as the caller tries
-+ */
-+static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy)
-+{
-+ static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d };
-+ u8 val;
-+
-+ qphy->dp_aux_cfg++;
-+ qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
-+ val = cfg1_settings[qphy->dp_aux_cfg];
-+
-+ writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
-+{
-+ const struct phy_configure_opts_dp *dp_opts = &opts->dp;
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+
-+ memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts));
-+ if (qphy->dp_opts.set_voltages) {
-+ cfg->configure_dp_tx(qphy);
-+ qphy->dp_opts.set_voltages = 0;
-+ }
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_dp_phy_calibrate(struct phy *phy)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+
-+ if (cfg->calibrate_dp_phy)
-+ return cfg->calibrate_dp_phy(qphy);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
-+{
-+ struct qcom_qmp *qmp = qphy->qmp;
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *serdes = qphy->serdes;
-+ void __iomem *pcs = qphy->pcs;
-+ void __iomem *dp_com = qmp->dp_com;
-+ int ret, i;
-+
-+ mutex_lock(&qmp->phy_mutex);
-+ if (qmp->init_count++) {
-+ mutex_unlock(&qmp->phy_mutex);
-+ return 0;
-+ }
-+
-+ /* turn on regulator supplies */
-+ ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
-+ if (ret) {
-+ dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
-+ goto err_unlock;
-+ }
-+
-+ for (i = 0; i < cfg->num_resets; i++) {
-+ ret = reset_control_assert(qmp->resets[i]);
-+ if (ret) {
-+ dev_err(qmp->dev, "%s reset assert failed\n",
-+ cfg->reset_list[i]);
-+ goto err_disable_regulators;
-+ }
-+ }
-+
-+ for (i = cfg->num_resets - 1; i >= 0; i--) {
-+ ret = reset_control_deassert(qmp->resets[i]);
-+ if (ret) {
-+ dev_err(qmp->dev, "%s reset deassert failed\n",
-+ qphy->cfg->reset_list[i]);
-+ goto err_assert_reset;
-+ }
-+ }
-+
-+ ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
-+ if (ret)
-+ goto err_assert_reset;
-+
-+ if (cfg->has_phy_dp_com_ctrl) {
-+ qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
-+ SW_PWRDN);
-+ /* override hardware control for reset of qmp phy */
-+ qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
-+ SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
-+ SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
-+
-+ /* Default type-c orientation, i.e CC1 */
-+ qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02);
-+
-+ qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
-+ USB3_MODE | DP_MODE);
-+
-+ /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
-+ qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
-+ SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
-+ SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
-+
-+ qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
-+ qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
-+ }
-+
-+ if (cfg->has_phy_com_ctrl) {
-+ qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
-+ SW_PWRDN);
-+ } else {
-+ if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
-+ qphy_setbits(pcs,
-+ cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
-+ cfg->pwrdn_ctrl);
-+ else
-+ qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
-+ cfg->pwrdn_ctrl);
-+ }
-+
-+ mutex_unlock(&qmp->phy_mutex);
-+
-+ return 0;
-+
-+err_assert_reset:
-+ while (++i < cfg->num_resets)
-+ reset_control_assert(qmp->resets[i]);
-+err_disable_regulators:
-+ regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
-+err_unlock:
-+ mutex_unlock(&qmp->phy_mutex);
-+
-+ return ret;
-+}
-+
-+static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy)
-+{
-+ struct qcom_qmp *qmp = qphy->qmp;
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *serdes = qphy->serdes;
-+ int i = cfg->num_resets;
-+
-+ mutex_lock(&qmp->phy_mutex);
-+ if (--qmp->init_count) {
-+ mutex_unlock(&qmp->phy_mutex);
-+ return 0;
-+ }
-+
-+ reset_control_assert(qmp->ufs_reset);
-+ if (cfg->has_phy_com_ctrl) {
-+ qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
-+ SERDES_START | PCS_START);
-+ qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
-+ SW_RESET);
-+ qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
-+ SW_PWRDN);
-+ }
-+
-+ while (--i >= 0)
-+ reset_control_assert(qmp->resets[i]);
-+
-+ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
-+
-+ regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
-+
-+ mutex_unlock(&qmp->phy_mutex);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_init(struct phy *phy)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ struct qcom_qmp *qmp = qphy->qmp;
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ int ret;
-+ dev_vdbg(qmp->dev, "Initializing QMP phy\n");
-+
-+ if (cfg->no_pcs_sw_reset) {
-+ /*
-+ * Get UFS reset, which is delayed until now to avoid a
-+ * circular dependency where UFS needs its PHY, but the PHY
-+ * needs this UFS reset.
-+ */
-+ if (!qmp->ufs_reset) {
-+ qmp->ufs_reset =
-+ devm_reset_control_get_exclusive(qmp->dev,
-+ "ufsphy");
-+
-+ if (IS_ERR(qmp->ufs_reset)) {
-+ ret = PTR_ERR(qmp->ufs_reset);
-+ dev_err(qmp->dev,
-+ "failed to get UFS reset: %d\n",
-+ ret);
-+
-+ qmp->ufs_reset = NULL;
-+ return ret;
-+ }
-+ }
-+
-+ ret = reset_control_assert(qmp->ufs_reset);
-+ if (ret)
-+ return ret;
-+ }
-+
-+ ret = qcom_qmp_phy_com_init(qphy);
-+ if (ret)
-+ return ret;
-+
-+ if (cfg->type == PHY_TYPE_DP)
-+ cfg->dp_aux_init(qphy);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_power_on(struct phy *phy)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ struct qcom_qmp *qmp = qphy->qmp;
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *tx = qphy->tx;
-+ void __iomem *rx = qphy->rx;
-+ void __iomem *pcs = qphy->pcs;
-+ void __iomem *pcs_misc = qphy->pcs_misc;
-+ void __iomem *status;
-+ unsigned int mask, val, ready;
-+ int ret;
-+
-+ qcom_qmp_phy_serdes_init(qphy);
-+
-+ if (cfg->has_lane_rst) {
-+ ret = reset_control_deassert(qphy->lane_rst);
-+ if (ret) {
-+ dev_err(qmp->dev, "lane%d reset deassert failed\n",
-+ qphy->index);
-+ return ret;
-+ }
-+ }
-+
-+ ret = clk_prepare_enable(qphy->pipe_clk);
-+ if (ret) {
-+ dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
-+ goto err_reset_lane;
-+ }
-+
-+ /* Tx, Rx, and PCS configurations */
-+ qcom_qmp_phy_configure_lane(tx, cfg->regs,
-+ cfg->tx_tbl, cfg->tx_tbl_num, 1);
-+ if (cfg->tx_tbl_sec)
-+ qcom_qmp_phy_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
-+ cfg->tx_tbl_num_sec, 1);
-+
-+ /* Configuration for other LANE for USB-DP combo PHY */
-+ if (cfg->is_dual_lane_phy) {
-+ qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
-+ cfg->tx_tbl, cfg->tx_tbl_num, 2);
-+ if (cfg->tx_tbl_sec)
-+ qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
-+ cfg->tx_tbl_sec,
-+ cfg->tx_tbl_num_sec, 2);
-+ }
-+
-+ /* Configure special DP tx tunings */
-+ if (cfg->type == PHY_TYPE_DP)
-+ cfg->configure_dp_tx(qphy);
-+
-+ qcom_qmp_phy_configure_lane(rx, cfg->regs,
-+ cfg->rx_tbl, cfg->rx_tbl_num, 1);
-+ if (cfg->rx_tbl_sec)
-+ qcom_qmp_phy_configure_lane(rx, cfg->regs,
-+ cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1);
-+
-+ if (cfg->is_dual_lane_phy) {
-+ qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
-+ cfg->rx_tbl, cfg->rx_tbl_num, 2);
-+ if (cfg->rx_tbl_sec)
-+ qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
-+ cfg->rx_tbl_sec,
-+ cfg->rx_tbl_num_sec, 2);
-+ }
-+
-+ /* Configure link rate, swing, etc. */
-+ if (cfg->type == PHY_TYPE_DP) {
-+ cfg->configure_dp_phy(qphy);
-+ } else {
-+ qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
-+ if (cfg->pcs_tbl_sec)
-+ qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
-+ cfg->pcs_tbl_num_sec);
-+ }
-+
-+ ret = reset_control_deassert(qmp->ufs_reset);
-+ if (ret)
-+ goto err_disable_pipe_clk;
-+
-+ qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
-+ cfg->pcs_misc_tbl_num);
-+ if (cfg->pcs_misc_tbl_sec)
-+ qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
-+ cfg->pcs_misc_tbl_num_sec);
-+
-+ /*
-+ * Pull out PHY from POWER DOWN state.
-+ * This is active low enable signal to power-down PHY.
-+ */
-+ if(cfg->type == PHY_TYPE_PCIE)
-+ qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
-+
-+ if (cfg->has_pwrdn_delay)
-+ usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
-+
-+ if (cfg->type != PHY_TYPE_DP) {
-+ /* Pull PHY out of reset state */
-+ if (!cfg->no_pcs_sw_reset)
-+ qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
-+ /* start SerDes and Phy-Coding-Sublayer */
-+ qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
-+
-+ if (cfg->type == PHY_TYPE_UFS) {
-+ status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
-+ mask = PCS_READY;
-+ ready = PCS_READY;
-+ } else {
-+ status = pcs + cfg->regs[QPHY_PCS_STATUS];
-+ mask = cfg->phy_status;
-+ ready = 0;
-+ }
-+
-+ ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
-+ PHY_INIT_COMPLETE_TIMEOUT);
-+ if (ret) {
-+ dev_err(qmp->dev, "phy initialization timed-out\n");
-+ goto err_disable_pipe_clk;
-+ }
-+ }
-+ return 0;
-+
-+err_disable_pipe_clk:
-+ clk_disable_unprepare(qphy->pipe_clk);
-+err_reset_lane:
-+ if (cfg->has_lane_rst)
-+ reset_control_assert(qphy->lane_rst);
-+
-+ return ret;
-+}
-+
-+static int qcom_qmp_phy_power_off(struct phy *phy)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+
-+ clk_disable_unprepare(qphy->pipe_clk);
-+
-+ if (cfg->type == PHY_TYPE_DP) {
-+ /* Assert DP PHY power down */
-+ writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+ } else {
-+ /* PHY reset */
-+ if (!cfg->no_pcs_sw_reset)
-+ qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
-+
-+ /* stop SerDes and Phy-Coding-Sublayer */
-+ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
-+
-+ /* Put PHY into POWER DOWN state: active low */
-+ if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
-+ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
-+ cfg->pwrdn_ctrl);
-+ } else {
-+ qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
-+ cfg->pwrdn_ctrl);
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_exit(struct phy *phy)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+
-+ if (cfg->has_lane_rst)
-+ reset_control_assert(qphy->lane_rst);
-+
-+ qcom_qmp_phy_com_exit(qphy);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_enable(struct phy *phy)
-+{
-+ int ret;
-+
-+ ret = qcom_qmp_phy_init(phy);
-+ if (ret)
-+ return ret;
-+
-+ ret = qcom_qmp_phy_power_on(phy);
-+ if (ret)
-+ qcom_qmp_phy_exit(phy);
-+
-+ return ret;
-+}
-+
-+static int qcom_qmp_phy_disable(struct phy *phy)
-+{
-+ int ret;
-+
-+ ret = qcom_qmp_phy_power_off(phy);
-+ if (ret)
-+ return ret;
-+ return qcom_qmp_phy_exit(phy);
-+}
-+
-+static int qcom_qmp_phy_set_mode(struct phy *phy,
-+ enum phy_mode mode, int submode)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+
-+ qphy->mode = mode;
-+
-+ return 0;
-+}
-+
-+static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
-+{
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *pcs = qphy->pcs;
-+ void __iomem *pcs_misc = qphy->pcs_misc;
-+ u32 intr_mask;
-+
-+ if (qphy->mode == PHY_MODE_USB_HOST_SS ||
-+ qphy->mode == PHY_MODE_USB_DEVICE_SS)
-+ intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
-+ else
-+ intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
-+
-+ /* Clear any pending interrupts status */
-+ qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
-+ /* Writing 1 followed by 0 clears the interrupt */
-+ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
-+
-+ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
-+ ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
-+
-+ /* Enable required PHY autonomous mode interrupts */
-+ qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
-+
-+ /* Enable i/o clamp_n for autonomous mode */
-+ if (pcs_misc)
-+ qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
-+}
-+
-+static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
-+{
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *pcs = qphy->pcs;
-+ void __iomem *pcs_misc = qphy->pcs_misc;
-+
-+ /* Disable i/o clamp_n on resume for normal mode */
-+ if (pcs_misc)
-+ qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
-+
-+ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
-+ ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
-+
-+ qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
-+ /* Writing 1 followed by 0 clears the interrupt */
-+ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
-+}
-+
-+static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ struct qmp_phy *qphy = qmp->phys[0];
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+
-+ dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode);
-+
-+ /* Supported only for USB3 PHY and luckily USB3 is the first phy */
-+ if (cfg->type != PHY_TYPE_USB3)
-+ return 0;
-+
-+ if (!qmp->init_count) {
-+ dev_vdbg(dev, "PHY not initialized, bailing out\n");
-+ return 0;
-+ }
-+
-+ qcom_qmp_phy_enable_autonomous_mode(qphy);
-+
-+ clk_disable_unprepare(qphy->pipe_clk);
-+ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
-+
-+ return 0;
-+}
-+
-+static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ struct qmp_phy *qphy = qmp->phys[0];
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ int ret = 0;
-+
-+ dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode);
-+
-+ /* Supported only for USB3 PHY and luckily USB3 is the first phy */
-+ if (cfg->type != PHY_TYPE_USB3)
-+ return 0;
-+
-+ if (!qmp->init_count) {
-+ dev_vdbg(dev, "PHY not initialized, bailing out\n");
-+ return 0;
-+ }
-+
-+ ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
-+ if (ret)
-+ return ret;
-+
-+ ret = clk_prepare_enable(qphy->pipe_clk);
-+ if (ret) {
-+ dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
-+ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
-+ return ret;
-+ }
-+
-+ qcom_qmp_phy_disable_autonomous_mode(qphy);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ int num = cfg->num_vregs;
-+ int i;
-+
-+ qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
-+ if (!qmp->vregs)
-+ return -ENOMEM;
-+
-+ for (i = 0; i < num; i++)
-+ qmp->vregs[i].supply = cfg->vreg_list[i];
-+
-+ return devm_regulator_bulk_get(dev, num, qmp->vregs);
-+}
-+
-+static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ int i;
-+
-+ qmp->resets = devm_kcalloc(dev, cfg->num_resets,
-+ sizeof(*qmp->resets), GFP_KERNEL);
-+ if (!qmp->resets)
-+ return -ENOMEM;
-+
-+ for (i = 0; i < cfg->num_resets; i++) {
-+ struct reset_control *rst;
-+ const char *name = cfg->reset_list[i];
-+
-+ rst = devm_reset_control_get_exclusive(dev, name);
-+ if (IS_ERR(rst)) {
-+ dev_err(dev, "failed to get %s reset\n", name);
-+ return PTR_ERR(rst);
-+ }
-+ qmp->resets[i] = rst;
-+ }
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ int num = cfg->num_clks;
-+ int i;
-+
-+ qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
-+ if (!qmp->clks)
-+ return -ENOMEM;
-+
-+ for (i = 0; i < num; i++)
-+ qmp->clks[i].id = cfg->clk_list[i];
-+
-+ return devm_clk_bulk_get(dev, num, qmp->clks);
-+}
-+
-+static void phy_clk_release_provider(void *res)
-+{
-+ of_clk_del_provider(res);
-+}
-+
-+/*
-+ * Register a fixed rate pipe clock.
-+ *
-+ * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
-+ * controls it. The <s>_pipe_clk coming out of the GCC is requested
-+ * by the PHY driver for its operations.
-+ * We register the <s>_pipe_clksrc here. The gcc driver takes care
-+ * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
-+ * Below picture shows this relationship.
-+ *
-+ * +---------------+
-+ * | PHY block |<<---------------------------------------+
-+ * | | |
-+ * | +-------+ | +-----+ |
-+ * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
-+ * clk | +-------+ | +-----+
-+ * +---------------+
-+ */
-+static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
-+{
-+ struct clk_fixed_rate *fixed;
-+ struct clk_init_data init = { };
-+ int ret;
-+
-+ ret = of_property_read_string(np, "clock-output-names", &init.name);
-+ if (ret) {
-+ dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
-+ return ret;
-+ }
-+
-+ fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
-+ if (!fixed)
-+ return -ENOMEM;
-+
-+ init.ops = &clk_fixed_rate_ops;
-+
-+ /* controllers using QMP phys use 125MHz pipe clock interface */
-+ fixed->fixed_rate = 125000000;
-+ fixed->hw.init = &init;
-+
-+ ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
-+ if (ret)
-+ return ret;
-+
-+ ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
-+ if (ret)
-+ return ret;
-+
-+ /*
-+ * Roll a devm action because the clock provider is the child node, but
-+ * the child node is not actually a device.
-+ */
-+ return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
-+}
-+
-+/*
-+ * Display Port PLL driver block diagram for branch clocks
-+ *
-+ * +------------------------------+
-+ * | DP_VCO_CLK |
-+ * | |
-+ * | +-------------------+ |
-+ * | | (DP PLL/VCO) | |
-+ * | +---------+---------+ |
-+ * | v |
-+ * | +----------+-----------+ |
-+ * | | hsclk_divsel_clk_src | |
-+ * | +----------+-----------+ |
-+ * +------------------------------+
-+ * |
-+ * +---------<---------v------------>----------+
-+ * | |
-+ * +--------v----------------+ |
-+ * | dp_phy_pll_link_clk | |
-+ * | link_clk | |
-+ * +--------+----------------+ |
-+ * | |
-+ * | |
-+ * v v
-+ * Input to DISPCC block |
-+ * for link clk, crypto clk |
-+ * and interface clock |
-+ * |
-+ * |
-+ * +--------<------------+-----------------+---<---+
-+ * | | |
-+ * +----v---------+ +--------v-----+ +--------v------+
-+ * | vco_divided | | vco_divided | | vco_divided |
-+ * | _clk_src | | _clk_src | | _clk_src |
-+ * | | | | | |
-+ * |divsel_six | | divsel_two | | divsel_four |
-+ * +-------+------+ +-----+--------+ +--------+------+
-+ * | | |
-+ * v---->----------v-------------<------v
-+ * |
-+ * +----------+-----------------+
-+ * | dp_phy_pll_vco_div_clk |
-+ * +---------+------------------+
-+ * |
-+ * v
-+ * Input to DISPCC block
-+ * for DP pixel clock
-+ *
-+ */
-+static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw,
-+ struct clk_rate_request *req)
-+{
-+ switch (req->rate) {
-+ case 1620000000UL / 2:
-+ case 2700000000UL / 2:
-+ /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */
-+ return 0;
-+ default:
-+ return -EINVAL;
-+ }
-+}
-+
-+static unsigned long
-+qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
-+{
-+ const struct qmp_phy_dp_clks *dp_clks;
-+ const struct qmp_phy *qphy;
-+ const struct phy_configure_opts_dp *dp_opts;
-+
-+ dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw);
-+ qphy = dp_clks->qphy;
-+ dp_opts = &qphy->dp_opts;
-+
-+ switch (dp_opts->link_rate) {
-+ case 1620:
-+ return 1620000000UL / 2;
-+ case 2700:
-+ return 2700000000UL / 2;
-+ case 5400:
-+ return 5400000000UL / 4;
-+ case 8100:
-+ return 8100000000UL / 6;
-+ default:
-+ return 0;
-+ }
-+}
-+
-+static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = {
-+ .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate,
-+ .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate,
-+};
-+
-+static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw,
-+ struct clk_rate_request *req)
-+{
-+ switch (req->rate) {
-+ case 162000000:
-+ case 270000000:
-+ case 540000000:
-+ case 810000000:
-+ return 0;
-+ default:
-+ return -EINVAL;
-+ }
-+}
-+
-+static unsigned long
-+qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
-+{
-+ const struct qmp_phy_dp_clks *dp_clks;
-+ const struct qmp_phy *qphy;
-+ const struct phy_configure_opts_dp *dp_opts;
-+
-+ dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw);
-+ qphy = dp_clks->qphy;
-+ dp_opts = &qphy->dp_opts;
-+
-+ switch (dp_opts->link_rate) {
-+ case 1620:
-+ case 2700:
-+ case 5400:
-+ case 8100:
-+ return dp_opts->link_rate * 100000;
-+ default:
-+ return 0;
-+ }
-+}
-+
-+static const struct clk_ops qcom_qmp_dp_link_clk_ops = {
-+ .determine_rate = qcom_qmp_dp_link_clk_determine_rate,
-+ .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate,
-+};
-+
-+static struct clk_hw *
-+qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data)
-+{
-+ struct qmp_phy_dp_clks *dp_clks = data;
-+ unsigned int idx = clkspec->args[0];
-+
-+ if (idx >= 2) {
-+ pr_err("%s: invalid index %u\n", __func__, idx);
-+ return ERR_PTR(-EINVAL);
-+ }
-+
-+ if (idx == 0)
-+ return &dp_clks->dp_link_hw;
-+
-+ return &dp_clks->dp_pixel_hw;
-+}
-+
-+static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy,
-+ struct device_node *np)
-+{
-+ struct clk_init_data init = { };
-+ struct qmp_phy_dp_clks *dp_clks;
-+ char name[64];
-+ int ret;
-+
-+ dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL);
-+ if (!dp_clks)
-+ return -ENOMEM;
-+
-+ dp_clks->qphy = qphy;
-+ qphy->dp_clks = dp_clks;
-+
-+ snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev));
-+ init.ops = &qcom_qmp_dp_link_clk_ops;
-+ init.name = name;
-+ dp_clks->dp_link_hw.init = &init;
-+ ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw);
-+ if (ret)
-+ return ret;
-+
-+ snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev));
-+ init.ops = &qcom_qmp_dp_pixel_clk_ops;
-+ init.name = name;
-+ dp_clks->dp_pixel_hw.init = &init;
-+ ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw);
-+ if (ret)
-+ return ret;
-+
-+ ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks);
-+ if (ret)
-+ return ret;
-+
-+ /*
-+ * Roll a devm action because the clock provider is the child node, but
-+ * the child node is not actually a device.
-+ */
-+ return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
-+}
-+
-+static const struct phy_ops qcom_qmp_phy_gen_ops = {
-+ .init = qcom_qmp_phy_enable,
-+ .exit = qcom_qmp_phy_disable,
-+ .set_mode = qcom_qmp_phy_set_mode,
-+ .owner = THIS_MODULE,
-+};
-+
-+static const struct phy_ops qcom_qmp_phy_dp_ops = {
-+ .init = qcom_qmp_phy_init,
-+ .configure = qcom_qmp_dp_phy_configure,
-+ .power_on = qcom_qmp_phy_power_on,
-+ .calibrate = qcom_qmp_dp_phy_calibrate,
-+ .power_off = qcom_qmp_phy_power_off,
-+ .exit = qcom_qmp_phy_exit,
-+ .set_mode = qcom_qmp_phy_set_mode,
-+ .owner = THIS_MODULE,
-+};
-+
-+static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
-+ .power_on = qcom_qmp_phy_enable,
-+ .power_off = qcom_qmp_phy_disable,
-+ .set_mode = qcom_qmp_phy_set_mode,
-+ .owner = THIS_MODULE,
-+};
-+
-+static void qcom_qmp_reset_control_put(void *data)
-+{
-+ reset_control_put(data);
-+}
-+
-+static
-+int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
-+ void __iomem *serdes, const struct qmp_phy_cfg *cfg)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ struct phy *generic_phy;
-+ struct qmp_phy *qphy;
-+ const struct phy_ops *ops;
-+ char prop_name[MAX_PROP_NAME];
-+ int ret;
-+
-+ qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
-+ if (!qphy)
-+ return -ENOMEM;
-+
-+ qphy->cfg = cfg;
-+ qphy->serdes = serdes;
-+ /*
-+ * Get memory resources for each phy lane:
-+ * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
-+ * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
-+ * For single lane PHYs: pcs_misc (optional) -> 3.
-+ */
-+ qphy->tx = of_iomap(np, 0);
-+ if (!qphy->tx)
-+ return -ENOMEM;
-+
-+ qphy->rx = of_iomap(np, 1);
-+ if (!qphy->rx)
-+ return -ENOMEM;
-+
-+ qphy->pcs = of_iomap(np, 2);
-+ if (!qphy->pcs)
-+ return -ENOMEM;
-+
-+ /*
-+ * If this is a dual-lane PHY, then there should be registers for the
-+ * second lane. Some old device trees did not specify this, so fall
-+ * back to old legacy behavior of assuming they can be reached at an
-+ * offset from the first lane.
-+ */
-+ if (cfg->is_dual_lane_phy) {
-+ qphy->tx2 = of_iomap(np, 3);
-+ qphy->rx2 = of_iomap(np, 4);
-+ if (!qphy->tx2 || !qphy->rx2) {
-+ dev_warn(dev,
-+ "Underspecified device tree, falling back to legacy register regions\n");
-+
-+ /* In the old version, pcs_misc is at index 3. */
-+ qphy->pcs_misc = qphy->tx2;
-+ qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE;
-+ qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
-+
-+ } else {
-+ qphy->pcs_misc = of_iomap(np, 5);
-+ }
-+
-+ } else {
-+ qphy->pcs_misc = of_iomap(np, 3);
-+ }
-+
-+ if (!qphy->pcs_misc)
-+ dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
-+
-+ /*
-+ * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3
-+ * based phys, so they essentially have pipe clock. So,
-+ * we return error in case phy is USB3 or PIPE type.
-+ * Otherwise, we initialize pipe clock to NULL for
-+ * all phys that don't need this.
-+ */
-+ snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
-+ qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name);
-+ if (IS_ERR(qphy->pipe_clk)) {
-+ if (cfg->type == PHY_TYPE_PCIE ||
-+ cfg->type == PHY_TYPE_USB3) {
-+ ret = PTR_ERR(qphy->pipe_clk);
-+ if (ret != -EPROBE_DEFER)
-+ dev_err(dev,
-+ "failed to get lane%d pipe_clk, %d\n",
-+ id, ret);
-+ return ret;
-+ }
-+ qphy->pipe_clk = NULL;
-+ }
-+
-+ /* Get lane reset, if any */
-+ if (cfg->has_lane_rst) {
-+ snprintf(prop_name, sizeof(prop_name), "lane%d", id);
-+ qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name);
-+ if (IS_ERR(qphy->lane_rst)) {
-+ dev_err(dev, "failed to get lane%d reset\n", id);
-+ return PTR_ERR(qphy->lane_rst);
-+ }
-+ ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put,
-+ qphy->lane_rst);
-+ if (ret)
-+ return ret;
-+ }
-+
-+ if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE)
-+ ops = &qcom_qmp_pcie_ufs_ops;
-+ else if (cfg->type == PHY_TYPE_DP)
-+ ops = &qcom_qmp_phy_dp_ops;
-+ else
-+ ops = &qcom_qmp_phy_gen_ops;
-+
-+ generic_phy = devm_phy_create(dev, np, ops);
-+ if (IS_ERR(generic_phy)) {
-+ ret = PTR_ERR(generic_phy);
-+ dev_err(dev, "failed to create qphy %d\n", ret);
-+ return ret;
-+ }
-+
-+ qphy->phy = generic_phy;
-+ qphy->index = id;
-+ qphy->qmp = qmp;
-+ qmp->phys[id] = qphy;
-+ phy_set_drvdata(generic_phy, qphy);
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
-+ {
-+ .compatible = "qcom,ipq8074-qmp-usb3-phy",
-+ .data = &ipq8074_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,msm8996-qmp-pcie-phy",
-+ .data = &msm8996_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,msm8996-qmp-ufs-phy",
-+ .data = &msm8996_ufs_cfg,
-+ }, {
-+ .compatible = "qcom,msm8996-qmp-usb3-phy",
-+ .data = &msm8996_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,msm8998-qmp-pcie-phy",
-+ .data = &msm8998_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,msm8998-qmp-ufs-phy",
-+ .data = &sdm845_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,ipq8074-qmp-pcie-phy",
-+ .data = &ipq8074_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,ipq6018-qmp-pcie-phy",
-+ .data = &ipq6018_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,ipq6018-qmp-usb3-phy",
-+ .data = &ipq8074_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sc7180-qmp-usb3-phy",
-+ .data = &sc7180_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
-+ /* It's a combo phy */
-+ }, {
-+ .compatible = "qcom,sc8180x-qmp-pcie-phy",
-+ .data = &sc8180x_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sc8180x-qmp-ufs-phy",
-+ .data = &sm8150_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sc8280xp-qmp-ufs-phy",
-+ .data = &sm8350_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sc8180x-qmp-usb3-phy",
-+ .data = &sm8150_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
-+ /* It's a combo phy */
-+ }, {
-+ .compatible = "qcom,sdm845-qhp-pcie-phy",
-+ .data = &sdm845_qhp_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sdm845-qmp-pcie-phy",
-+ .data = &sdm845_qmp_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sdm845-qmp-usb3-phy",
-+ .data = &qmp_v3_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
-+ .data = &qmp_v3_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sdm845-qmp-ufs-phy",
-+ .data = &sdm845_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,msm8998-qmp-usb3-phy",
-+ .data = &msm8998_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sm6115-qmp-ufs-phy",
-+ .data = &sm6115_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm6350-qmp-ufs-phy",
-+ .data = &sdm845_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8150-qmp-ufs-phy",
-+ .data = &sm8150_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-ufs-phy",
-+ .data = &sm8150_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8150-qmp-usb3-phy",
-+ .data = &sm8150_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8150-qmp-usb3-uni-phy",
-+ .data = &sm8150_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-usb3-phy",
-+ .data = &sm8250_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
-+ /* It's a combo phy */
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-usb3-uni-phy",
-+ .data = &sm8250_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
-+ .data = &sm8250_qmp_gen3x1_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
-+ .data = &sm8250_qmp_gen3x2_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8350-qmp-ufs-phy",
-+ .data = &sm8350_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
-+ .data = &sm8250_qmp_gen3x2_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sdx55-qmp-pcie-phy",
-+ .data = &sdx55_qmp_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sdx55-qmp-usb3-uni-phy",
-+ .data = &sdx55_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sdx65-qmp-usb3-uni-phy",
-+ .data = &sdx65_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8350-qmp-usb3-phy",
-+ .data = &sm8350_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8350-qmp-usb3-uni-phy",
-+ .data = &sm8350_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
-+ .data = &sm8450_qmp_gen3x1_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
-+ .data = &sm8450_qmp_gen4x2_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8450-qmp-ufs-phy",
-+ .data = &sm8450_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8450-qmp-usb3-phy",
-+ .data = &sm8350_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,qcm2290-qmp-usb3-phy",
-+ .data = &qcm2290_usb3phy_cfg,
-+ },
-+ { },
-+};
-+MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
-+
-+static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = {
-+ {
-+ .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
-+ .data = &sc7180_usb3dpphy_cfg,
-+ },
-+ {
-+ .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
-+ .data = &sm8250_usb3dpphy_cfg,
-+ },
-+ {
-+ .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
-+ .data = &sc8180x_usb3dpphy_cfg,
-+ },
-+ { }
-+};
-+
-+static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
-+ SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
-+ qcom_qmp_phy_runtime_resume, NULL)
-+};
-+
-+static int qcom_qmp_phy_probe(struct platform_device *pdev)
-+{
-+ struct qcom_qmp *qmp;
-+ struct device *dev = &pdev->dev;
-+ struct device_node *child;
-+ struct phy_provider *phy_provider;
-+ void __iomem *serdes;
-+ void __iomem *usb_serdes;
-+ void __iomem *dp_serdes = NULL;
-+ const struct qmp_phy_combo_cfg *combo_cfg = NULL;
-+ const struct qmp_phy_cfg *cfg = NULL;
-+ const struct qmp_phy_cfg *usb_cfg = NULL;
-+ const struct qmp_phy_cfg *dp_cfg = NULL;
-+ int num, id, expected_phys;
-+ int ret;
-+
-+ qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
-+ if (!qmp)
-+ return -ENOMEM;
-+
-+ qmp->dev = dev;
-+ dev_set_drvdata(dev, qmp);
-+
-+ /* Get the specific init parameters of QMP phy */
-+ cfg = of_device_get_match_data(dev);
-+ if (!cfg) {
-+ const struct of_device_id *match;
-+
-+ match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev);
-+ if (!match)
-+ return -EINVAL;
-+
-+ combo_cfg = match->data;
-+ if (!combo_cfg)
-+ return -EINVAL;
-+
-+ usb_cfg = combo_cfg->usb_cfg;
-+ cfg = usb_cfg; /* Setup clks and regulators */
-+ }
-+
-+ /* per PHY serdes; usually located at base address */
-+ usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0);
-+ if (IS_ERR(serdes))
-+ return PTR_ERR(serdes);
-+
-+ /* per PHY dp_com; if PHY has dp_com control block */
-+ if (combo_cfg || cfg->has_phy_dp_com_ctrl) {
-+ qmp->dp_com = devm_platform_ioremap_resource(pdev, 1);
-+ if (IS_ERR(qmp->dp_com))
-+ return PTR_ERR(qmp->dp_com);
-+ }
-+
-+ if (combo_cfg) {
-+ /* Only two serdes for combo PHY */
-+ dp_serdes = devm_platform_ioremap_resource(pdev, 2);
-+ if (IS_ERR(dp_serdes))
-+ return PTR_ERR(dp_serdes);
-+
-+ dp_cfg = combo_cfg->dp_cfg;
-+ expected_phys = 2;
-+ } else {
-+ expected_phys = cfg->nlanes;
-+ }
-+
-+ mutex_init(&qmp->phy_mutex);
-+
-+ ret = qcom_qmp_phy_clk_init(dev, cfg);
-+ if (ret)
-+ return ret;
-+
-+ ret = qcom_qmp_phy_reset_init(dev, cfg);
-+ if (ret)
-+ return ret;
-+
-+ ret = qcom_qmp_phy_vreg_init(dev, cfg);
-+ if (ret) {
-+ if (ret != -EPROBE_DEFER)
-+ dev_err(dev, "failed to get regulator supplies: %d\n",
-+ ret);
-+ return ret;
-+ }
-+
-+ num = of_get_available_child_count(dev->of_node);
-+ /* do we have a rogue child node ? */
-+ if (num > expected_phys)
-+ return -EINVAL;
-+
-+ qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
-+ if (!qmp->phys)
-+ return -ENOMEM;
-+
-+ pm_runtime_set_active(dev);
-+ pm_runtime_enable(dev);
-+ /*
-+ * Prevent runtime pm from being ON by default. Users can enable
-+ * it using power/control in sysfs.
-+ */
-+ pm_runtime_forbid(dev);
-+
-+ id = 0;
-+ for_each_available_child_of_node(dev->of_node, child) {
-+ if (of_node_name_eq(child, "dp-phy")) {
-+ cfg = dp_cfg;
-+ serdes = dp_serdes;
-+ } else if (of_node_name_eq(child, "usb3-phy")) {
-+ cfg = usb_cfg;
-+ serdes = usb_serdes;
-+ }
-+
-+ /* Create per-lane phy */
-+ ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg);
-+ if (ret) {
-+ dev_err(dev, "failed to create lane%d phy, %d\n",
-+ id, ret);
-+ goto err_node_put;
-+ }
-+
-+ /*
-+ * Register the pipe clock provided by phy.
-+ * See function description to see details of this pipe clock.
-+ */
-+ if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) {
-+ ret = phy_pipe_clk_register(qmp, child);
-+ if (ret) {
-+ dev_err(qmp->dev,
-+ "failed to register pipe clock source\n");
-+ goto err_node_put;
-+ }
-+ } else if (cfg->type == PHY_TYPE_DP) {
-+ ret = phy_dp_clks_register(qmp, qmp->phys[id], child);
-+ if (ret) {
-+ dev_err(qmp->dev,
-+ "failed to register DP clock source\n");
-+ goto err_node_put;
-+ }
-+ }
-+ id++;
-+ }
-+
-+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
-+ if (!IS_ERR(phy_provider))
-+ dev_info(dev, "Registered Qcom-QMP phy\n");
-+ else
-+ pm_runtime_disable(dev);
-+
-+ return PTR_ERR_OR_ZERO(phy_provider);
-+
-+err_node_put:
-+ pm_runtime_disable(dev);
-+ of_node_put(child);
-+ return ret;
-+}
-+
-+static struct platform_driver qcom_qmp_phy_driver = {
-+ .probe = qcom_qmp_phy_probe,
-+ .driver = {
-+ .name = "qcom-qmp-phy",
-+ .pm = &qcom_qmp_phy_pm_ops,
-+ .of_match_table = qcom_qmp_phy_of_match_table,
-+ },
-+};
-+
-+module_platform_driver(qcom_qmp_phy_driver);
-+
-+MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
-+MODULE_DESCRIPTION("Qualcomm QMP PHY driver");
-+MODULE_LICENSE("GPL v2");
-diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
-new file mode 100644
-index 000000000000..c7309e981bfb
---- /dev/null
-+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
-@@ -0,0 +1,6350 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/clk-provider.h>
-+#include <linux/delay.h>
-+#include <linux/err.h>
-+#include <linux/io.h>
-+#include <linux/iopoll.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/of_device.h>
-+#include <linux/of_address.h>
-+#include <linux/phy/phy.h>
-+#include <linux/platform_device.h>
-+#include <linux/regulator/consumer.h>
-+#include <linux/reset.h>
-+#include <linux/slab.h>
-+
-+#include <dt-bindings/phy/phy.h>
-+
-+#include "phy-qcom-qmp.h"
-+
-+/* QPHY_SW_RESET bit */
-+#define SW_RESET BIT(0)
-+/* QPHY_POWER_DOWN_CONTROL */
-+#define SW_PWRDN BIT(0)
-+#define REFCLK_DRV_DSBL BIT(1)
-+/* QPHY_START_CONTROL bits */
-+#define SERDES_START BIT(0)
-+#define PCS_START BIT(1)
-+#define PLL_READY_GATE_EN BIT(3)
-+/* QPHY_PCS_STATUS bit */
-+#define PHYSTATUS BIT(6)
-+#define PHYSTATUS_4_20 BIT(7)
-+/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */
-+#define PCS_READY BIT(0)
-+
-+/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
-+/* DP PHY soft reset */
-+#define SW_DPPHY_RESET BIT(0)
-+/* mux to select DP PHY reset control, 0:HW control, 1: software reset */
-+#define SW_DPPHY_RESET_MUX BIT(1)
-+/* USB3 PHY soft reset */
-+#define SW_USB3PHY_RESET BIT(2)
-+/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
-+#define SW_USB3PHY_RESET_MUX BIT(3)
-+
-+/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
-+#define USB3_MODE BIT(0) /* enables USB3 mode */
-+#define DP_MODE BIT(1) /* enables DP mode */
-+
-+/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
-+#define ARCVR_DTCT_EN BIT(0)
-+#define ALFPS_DTCT_EN BIT(1)
-+#define ARCVR_DTCT_EVENT_SEL BIT(4)
-+
-+/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
-+#define IRQ_CLEAR BIT(0)
-+
-+/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
-+#define RCVR_DETECT BIT(0)
-+
-+/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
-+#define CLAMP_EN BIT(0) /* enables i/o clamp_n */
-+
-+#define PHY_INIT_COMPLETE_TIMEOUT 10000
-+#define POWER_DOWN_DELAY_US_MIN 10
-+#define POWER_DOWN_DELAY_US_MAX 11
-+
-+#define MAX_PROP_NAME 32
-+
-+/* Define the assumed distance between lanes for underspecified device trees. */
-+#define QMP_PHY_LEGACY_LANE_STRIDE 0x400
-+
-+struct qmp_phy_init_tbl {
-+ unsigned int offset;
-+ unsigned int val;
-+ /*
-+ * register part of layout ?
-+ * if yes, then offset gives index in the reg-layout
-+ */
-+ bool in_layout;
-+ /*
-+ * mask of lanes for which this register is written
-+ * for cases when second lane needs different values
-+ */
-+ u8 lane_mask;
-+};
-+
-+#define QMP_PHY_INIT_CFG(o, v) \
-+ { \
-+ .offset = o, \
-+ .val = v, \
-+ .lane_mask = 0xff, \
-+ }
-+
-+#define QMP_PHY_INIT_CFG_L(o, v) \
-+ { \
-+ .offset = o, \
-+ .val = v, \
-+ .in_layout = true, \
-+ .lane_mask = 0xff, \
-+ }
-+
-+#define QMP_PHY_INIT_CFG_LANE(o, v, l) \
-+ { \
-+ .offset = o, \
-+ .val = v, \
-+ .lane_mask = l, \
-+ }
-+
-+/* set of registers with offsets different per-PHY */
-+enum qphy_reg_layout {
-+ /* Common block control registers */
-+ QPHY_COM_SW_RESET,
-+ QPHY_COM_POWER_DOWN_CONTROL,
-+ QPHY_COM_START_CONTROL,
-+ QPHY_COM_PCS_READY_STATUS,
-+ /* PCS registers */
-+ QPHY_PLL_LOCK_CHK_DLY_TIME,
-+ QPHY_FLL_CNTRL1,
-+ QPHY_FLL_CNTRL2,
-+ QPHY_FLL_CNT_VAL_L,
-+ QPHY_FLL_CNT_VAL_H_TOL,
-+ QPHY_FLL_MAN_CODE,
-+ QPHY_SW_RESET,
-+ QPHY_START_CTRL,
-+ QPHY_PCS_READY_STATUS,
-+ QPHY_PCS_STATUS,
-+ QPHY_PCS_AUTONOMOUS_MODE_CTRL,
-+ QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
-+ QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
-+ QPHY_PCS_POWER_DOWN_CONTROL,
-+ /* PCS_MISC registers */
-+ QPHY_PCS_MISC_TYPEC_CTRL,
-+ /* Keep last to ensure regs_layout arrays are properly initialized */
-+ QPHY_LAYOUT_SIZE
-+};
-+
-+static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_START_CTRL] = 0x00,
-+ [QPHY_PCS_READY_STATUS] = 0x168,
-+};
-+
-+static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x44,
-+ [QPHY_PCS_STATUS] = 0x14,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
-+};
-+
-+static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_COM_SW_RESET] = 0x400,
-+ [QPHY_COM_POWER_DOWN_CONTROL] = 0x404,
-+ [QPHY_COM_START_CONTROL] = 0x408,
-+ [QPHY_COM_PCS_READY_STATUS] = 0x448,
-+ [QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8,
-+ [QPHY_FLL_CNTRL1] = 0xc4,
-+ [QPHY_FLL_CNTRL2] = 0xc8,
-+ [QPHY_FLL_CNT_VAL_L] = 0xcc,
-+ [QPHY_FLL_CNT_VAL_H_TOL] = 0xd0,
-+ [QPHY_FLL_MAN_CODE] = 0xd4,
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_STATUS] = 0x174,
-+};
-+
-+static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_FLL_CNTRL1] = 0xc0,
-+ [QPHY_FLL_CNTRL2] = 0xc4,
-+ [QPHY_FLL_CNT_VAL_L] = 0xc8,
-+ [QPHY_FLL_CNT_VAL_H_TOL] = 0xcc,
-+ [QPHY_FLL_MAN_CODE] = 0xd0,
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_STATUS] = 0x17c,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
-+};
-+
-+static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_STATUS] = 0x174,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
-+};
-+
-+static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_STATUS] = 0x174,
-+};
-+
-+static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_STATUS] = 0x2ac,
-+};
-+
-+static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x44,
-+ [QPHY_PCS_STATUS] = 0x14,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314,
-+};
-+
-+static const unsigned int qmp_v4_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x44,
-+ [QPHY_PCS_STATUS] = 0x14,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x608,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x614,
-+};
-+
-+static const unsigned int sm8350_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x44,
-+ [QPHY_PCS_STATUS] = 0x14,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x1008,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x1014,
-+};
-+
-+static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0xd8,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc,
-+ [QPHY_PCS_STATUS] = 0x174,
-+ [QPHY_PCS_MISC_TYPEC_CTRL] = 0x00,
-+};
-+
-+static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_START_CTRL] = 0x00,
-+ [QPHY_PCS_READY_STATUS] = 0x160,
-+};
-+
-+static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_START_CTRL] = 0x00,
-+ [QPHY_PCS_READY_STATUS] = 0x168,
-+};
-+
-+static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x44,
-+ [QPHY_PCS_STATUS] = 0x14,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
-+};
-+
-+static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START,
-+ [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS,
-+ [QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET,
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
-+ /* PLL and Loop filter settings */
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-+ /* SSC settings */
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
-+ QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
-+
-+ QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
-+
-+ QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
-+ QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
-+ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
-+ /* PLL and Loop filter settings */
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-+ /* SSC settings */
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
-+ /* FLL settings */
-+ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03),
-+ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02),
-+ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42),
-+ QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
-+
-+ /* Lock Det settings */
-+ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x61),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d),
-+ QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10),
-+ QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_PRE, 0x00),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_POST, 0x58),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
-+ QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
-+ QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
-+ QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
-+ QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
-+ QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
-+ QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
-+ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
-+ QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
-+ QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = {
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
-+ /* FLL settings */
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+
-+ /* Lock Det settings */
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
-+ /* FLL settings */
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+
-+ /* Lock Det settings */
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
-+};
-+
-+static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
-+
-+ /* Rate B */
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),
-+};
-+
-+static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B),
-+};
-+
-+static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_RX_PWM_GEAR_BAND, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_CTRL2, 0x6d),
-+ QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_DRV_LVL, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_DRV_LVL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
-+ QMP_PHY_INIT_CFG(QPHY_RX_SYM_RESYNC_CTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
-+ QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
-+
-+ /* Rate B */
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
-+
-+ /* Rate B */
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
-+
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
-+ /* Lock Det settings */
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20),
-+};
-+
-+static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
-+};
-+
-+static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5),
-+};
-+
-+static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
-+};
-+
-+static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),
-+};
-+
-+static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
-+
-+ /* Rate B */
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+};
-+
-+static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01),
-+};
-+
-+static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
-+
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05),
-+
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
-+
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
-+
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
-+};
-+
-+/* Register names should be validated, they might be different for this PHY */
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
-+};
-+
-+struct qmp_phy;
-+
-+/* struct qmp_phy_cfg - per-PHY initialization config */
-+struct qmp_phy_cfg {
-+ /* phy-type - PCIE/UFS/USB */
-+ unsigned int type;
-+ /* number of lanes provided by phy */
-+ int nlanes;
-+
-+ /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
-+ const struct qmp_phy_init_tbl *serdes_tbl;
-+ int serdes_tbl_num;
-+ const struct qmp_phy_init_tbl *serdes_tbl_sec;
-+ int serdes_tbl_num_sec;
-+ const struct qmp_phy_init_tbl *tx_tbl;
-+ int tx_tbl_num;
-+ const struct qmp_phy_init_tbl *tx_tbl_sec;
-+ int tx_tbl_num_sec;
-+ const struct qmp_phy_init_tbl *rx_tbl;
-+ int rx_tbl_num;
-+ const struct qmp_phy_init_tbl *rx_tbl_sec;
-+ int rx_tbl_num_sec;
-+ const struct qmp_phy_init_tbl *pcs_tbl;
-+ int pcs_tbl_num;
-+ const struct qmp_phy_init_tbl *pcs_tbl_sec;
-+ int pcs_tbl_num_sec;
-+ const struct qmp_phy_init_tbl *pcs_misc_tbl;
-+ int pcs_misc_tbl_num;
-+ const struct qmp_phy_init_tbl *pcs_misc_tbl_sec;
-+ int pcs_misc_tbl_num_sec;
-+
-+ /* Init sequence for DP PHY block link rates */
-+ const struct qmp_phy_init_tbl *serdes_tbl_rbr;
-+ int serdes_tbl_rbr_num;
-+ const struct qmp_phy_init_tbl *serdes_tbl_hbr;
-+ int serdes_tbl_hbr_num;
-+ const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
-+ int serdes_tbl_hbr2_num;
-+ const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
-+ int serdes_tbl_hbr3_num;
-+
-+ /* DP PHY callbacks */
-+ int (*configure_dp_phy)(struct qmp_phy *qphy);
-+ void (*configure_dp_tx)(struct qmp_phy *qphy);
-+ int (*calibrate_dp_phy)(struct qmp_phy *qphy);
-+ void (*dp_aux_init)(struct qmp_phy *qphy);
-+
-+ /* clock ids to be requested */
-+ const char * const *clk_list;
-+ int num_clks;
-+ /* resets to be requested */
-+ const char * const *reset_list;
-+ int num_resets;
-+ /* regulators to be requested */
-+ const char * const *vreg_list;
-+ int num_vregs;
-+
-+ /* array of registers with different offsets */
-+ const unsigned int *regs;
-+
-+ unsigned int start_ctrl;
-+ unsigned int pwrdn_ctrl;
-+ unsigned int mask_com_pcs_ready;
-+ /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
-+ unsigned int phy_status;
-+
-+ /* true, if PHY has a separate PHY_COM control block */
-+ bool has_phy_com_ctrl;
-+ /* true, if PHY has a reset for individual lanes */
-+ bool has_lane_rst;
-+ /* true, if PHY needs delay after POWER_DOWN */
-+ bool has_pwrdn_delay;
-+ /* power_down delay in usec */
-+ int pwrdn_delay_min;
-+ int pwrdn_delay_max;
-+
-+ /* true, if PHY has a separate DP_COM control block */
-+ bool has_phy_dp_com_ctrl;
-+ /* true, if PHY has secondary tx/rx lanes to be configured */
-+ bool is_dual_lane_phy;
-+
-+ /* true, if PCS block has no separate SW_RESET register */
-+ bool no_pcs_sw_reset;
-+};
-+
-+struct qmp_phy_combo_cfg {
-+ const struct qmp_phy_cfg *usb_cfg;
-+ const struct qmp_phy_cfg *dp_cfg;
-+};
-+
-+/**
-+ * struct qmp_phy - per-lane phy descriptor
-+ *
-+ * @phy: generic phy
-+ * @cfg: phy specific configuration
-+ * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
-+ * @tx: iomapped memory space for lane's tx
-+ * @rx: iomapped memory space for lane's rx
-+ * @pcs: iomapped memory space for lane's pcs
-+ * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
-+ * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
-+ * @pcs_misc: iomapped memory space for lane's pcs_misc
-+ * @pipe_clk: pipe clock
-+ * @index: lane index
-+ * @qmp: QMP phy to which this lane belongs
-+ * @lane_rst: lane's reset controller
-+ * @mode: current PHY mode
-+ * @dp_aux_cfg: Display port aux config
-+ * @dp_opts: Display port optional config
-+ * @dp_clks: Display port clocks
-+ */
-+struct qmp_phy {
-+ struct phy *phy;
-+ const struct qmp_phy_cfg *cfg;
-+ void __iomem *serdes;
-+ void __iomem *tx;
-+ void __iomem *rx;
-+ void __iomem *pcs;
-+ void __iomem *tx2;
-+ void __iomem *rx2;
-+ void __iomem *pcs_misc;
-+ struct clk *pipe_clk;
-+ unsigned int index;
-+ struct qcom_qmp *qmp;
-+ struct reset_control *lane_rst;
-+ enum phy_mode mode;
-+ unsigned int dp_aux_cfg;
-+ struct phy_configure_opts_dp dp_opts;
-+ struct qmp_phy_dp_clks *dp_clks;
-+};
-+
-+struct qmp_phy_dp_clks {
-+ struct qmp_phy *qphy;
-+ struct clk_hw dp_link_hw;
-+ struct clk_hw dp_pixel_hw;
-+};
-+
-+/**
-+ * struct qcom_qmp - structure holding QMP phy block attributes
-+ *
-+ * @dev: device
-+ * @dp_com: iomapped memory space for phy's dp_com control block
-+ *
-+ * @clks: array of clocks required by phy
-+ * @resets: array of resets required by phy
-+ * @vregs: regulator supplies bulk data
-+ *
-+ * @phys: array of per-lane phy descriptors
-+ * @phy_mutex: mutex lock for PHY common block initialization
-+ * @init_count: phy common block initialization count
-+ * @ufs_reset: optional UFS PHY reset handle
-+ */
-+struct qcom_qmp {
-+ struct device *dev;
-+ void __iomem *dp_com;
-+
-+ struct clk_bulk_data *clks;
-+ struct reset_control **resets;
-+ struct regulator_bulk_data *vregs;
-+
-+ struct qmp_phy **phys;
-+
-+ struct mutex phy_mutex;
-+ int init_count;
-+
-+ struct reset_control *ufs_reset;
-+};
-+
-+static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy);
-+static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy);
-+static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy);
-+static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy);
-+
-+static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy);
-+static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy);
-+static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy);
-+static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy);
-+
-+static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
-+{
-+ u32 reg;
-+
-+ reg = readl(base + offset);
-+ reg |= val;
-+ writel(reg, base + offset);
-+
-+ /* ensure that above write is through */
-+ readl(base + offset);
-+}
-+
-+static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
-+{
-+ u32 reg;
-+
-+ reg = readl(base + offset);
-+ reg &= ~val;
-+ writel(reg, base + offset);
-+
-+ /* ensure that above write is through */
-+ readl(base + offset);
-+}
-+
-+/* list of clocks required by phy */
-+static const char * const msm8996_phy_clk_l[] = {
-+ "aux", "cfg_ahb", "ref",
-+};
-+
-+static const char * const msm8996_ufs_phy_clk_l[] = {
-+ "ref",
-+};
-+
-+static const char * const qmp_v3_phy_clk_l[] = {
-+ "aux", "cfg_ahb", "ref", "com_aux",
-+};
-+
-+static const char * const sdm845_pciephy_clk_l[] = {
-+ "aux", "cfg_ahb", "ref", "refgen",
-+};
-+
-+static const char * const qmp_v4_phy_clk_l[] = {
-+ "aux", "ref_clk_src", "ref", "com_aux",
-+};
-+
-+/* the primary usb3 phy on sm8250 doesn't have a ref clock */
-+static const char * const qmp_v4_sm8250_usbphy_clk_l[] = {
-+ "aux", "ref_clk_src", "com_aux"
-+};
-+
-+static const char * const sm8450_ufs_phy_clk_l[] = {
-+ "qref", "ref", "ref_aux",
-+};
-+
-+static const char * const sdm845_ufs_phy_clk_l[] = {
-+ "ref", "ref_aux",
-+};
-+
-+/* usb3 phy on sdx55 doesn't have com_aux clock */
-+static const char * const qmp_v4_sdx55_usbphy_clk_l[] = {
-+ "aux", "cfg_ahb", "ref"
-+};
-+
-+static const char * const qcm2290_usb3phy_clk_l[] = {
-+ "cfg_ahb", "ref", "com_aux",
-+};
-+
-+/* list of resets */
-+static const char * const msm8996_pciephy_reset_l[] = {
-+ "phy", "common", "cfg",
-+};
-+
-+static const char * const msm8996_usb3phy_reset_l[] = {
-+ "phy", "common",
-+};
-+
-+static const char * const sc7180_usb3phy_reset_l[] = {
-+ "phy",
-+};
-+
-+static const char * const qcm2290_usb3phy_reset_l[] = {
-+ "phy_phy", "phy",
-+};
-+
-+static const char * const sdm845_pciephy_reset_l[] = {
-+ "phy",
-+};
-+
-+/* list of regulators */
-+static const char * const qmp_phy_vreg_l[] = {
-+ "vdda-phy", "vdda-pll",
-+};
-+
-+static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = ipq8074_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
-+ .tx_tbl = msm8996_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
-+ .rx_tbl = ipq8074_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
-+ .pcs_tbl = ipq8074_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
-+ .clk_list = msm8996_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+};
-+
-+static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 3,
-+
-+ .serdes_tbl = msm8996_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
-+ .tx_tbl = msm8996_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8996_pcie_tx_tbl),
-+ .rx_tbl = msm8996_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(msm8996_pcie_rx_tbl),
-+ .pcs_tbl = msm8996_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
-+ .clk_list = msm8996_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-+ .reset_list = msm8996_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = pciephy_regs_layout,
-+
-+ .start_ctrl = PCS_START | PLL_READY_GATE_EN,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .mask_com_pcs_ready = PCS_READY,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_phy_com_ctrl = true,
-+ .has_lane_rst = true,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg msm8996_ufs_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = msm8996_ufs_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(msm8996_ufs_serdes_tbl),
-+ .tx_tbl = msm8996_ufs_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8996_ufs_tx_tbl),
-+ .rx_tbl = msm8996_ufs_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(msm8996_ufs_rx_tbl),
-+
-+ .clk_list = msm8996_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
-+
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+
-+ .regs = msm8996_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .no_pcs_sw_reset = true,
-+};
-+
-+static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = msm8996_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
-+ .tx_tbl = msm8996_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
-+ .rx_tbl = msm8996_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl),
-+ .pcs_tbl = msm8996_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
-+ .clk_list = msm8996_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+};
-+
-+static const char * const ipq8074_pciephy_clk_l[] = {
-+ "aux", "cfg_ahb",
-+};
-+/* list of resets */
-+static const char * const ipq8074_pciephy_reset_l[] = {
-+ "phy", "common",
-+};
-+
-+static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = ipq8074_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
-+ .tx_tbl = ipq8074_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
-+ .rx_tbl = ipq8074_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
-+ .pcs_tbl = ipq8074_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
-+ .clk_list = ipq8074_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
-+ .reset_list = ipq8074_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
-+ .vreg_list = NULL,
-+ .num_vregs = 0,
-+ .regs = pciephy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_phy_com_ctrl = false,
-+ .has_lane_rst = false,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = ipq6018_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl),
-+ .tx_tbl = ipq6018_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl),
-+ .rx_tbl = ipq6018_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
-+ .pcs_tbl = ipq6018_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
-+ .clk_list = ipq8074_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
-+ .reset_list = ipq8074_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
-+ .vreg_list = NULL,
-+ .num_vregs = 0,
-+ .regs = ipq_pciephy_gen3_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+
-+ .has_phy_com_ctrl = false,
-+ .has_lane_rst = false,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sdm845_qmp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
-+ .tx_tbl = sdm845_qmp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),
-+ .rx_tbl = sdm845_qmp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),
-+ .pcs_tbl = sdm845_qmp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sdm845_qmp_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sdm845_qmp_pciephy_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sdm845_qhp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
-+ .tx_tbl = sdm845_qhp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
-+ .rx_tbl = sdm845_qhp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl),
-+ .pcs_tbl = sdm845_qhp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sdm845_qhp_pciephy_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
-+ .serdes_tbl_sec = sm8250_qmp_gen3x1_pcie_serdes_tbl,
-+ .serdes_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
-+ .tx_tbl = sm8250_qmp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
-+ .rx_tbl = sm8250_qmp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
-+ .rx_tbl_sec = sm8250_qmp_gen3x1_pcie_rx_tbl,
-+ .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),
-+ .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
-+ .pcs_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_tbl,
-+ .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
-+ .pcs_misc_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
-+ .tx_tbl = sm8250_qmp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
-+ .tx_tbl_sec = sm8250_qmp_gen3x2_pcie_tx_tbl,
-+ .tx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),
-+ .rx_tbl = sm8250_qmp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
-+ .rx_tbl_sec = sm8250_qmp_gen3x2_pcie_rx_tbl,
-+ .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl),
-+ .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
-+ .pcs_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_tbl,
-+ .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
-+ .pcs_misc_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v3_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
-+ .tx_tbl = qmp_v3_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
-+ .rx_tbl = qmp_v3_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
-+ .pcs_tbl = qmp_v3_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
-+ .clk_list = qmp_v3_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v3_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
-+ .tx_tbl = qmp_v3_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
-+ .rx_tbl = qmp_v3_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
-+ .pcs_tbl = qmp_v3_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
-+ .clk_list = qmp_v3_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-+ .reset_list = sc7180_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sc7180_dpphy_cfg = {
-+ .type = PHY_TYPE_DP,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v3_dp_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
-+ .tx_tbl = qmp_v3_dp_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
-+
-+ .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr,
-+ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
-+ .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr,
-+ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
-+ .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2,
-+ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
-+ .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3,
-+ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
-+
-+ .clk_list = qmp_v3_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-+ .reset_list = sc7180_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+
-+ .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init,
-+ .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx,
-+ .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy,
-+ .calibrate_dp_phy = qcom_qmp_v3_dp_phy_calibrate,
-+};
-+
-+static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = {
-+ .usb_cfg = &sc7180_usb3phy_cfg,
-+ .dp_cfg = &sc7180_dpphy_cfg,
-+};
-+
-+static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
-+ .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v3_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sdm845_ufsphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
-+ .tx_tbl = sdm845_ufsphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
-+ .rx_tbl = sdm845_ufsphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
-+ .pcs_tbl = sdm845_ufsphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
-+ .clk_list = sdm845_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sdm845_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+ .no_pcs_sw_reset = true,
-+};
-+
-+static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm6115_ufsphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl),
-+ .tx_tbl = sm6115_ufsphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_tx_tbl),
-+ .rx_tbl = sm6115_ufsphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_rx_tbl),
-+ .pcs_tbl = sm6115_ufsphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl),
-+ .clk_list = sdm845_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm6115_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+
-+ .is_dual_lane_phy = false,
-+ .no_pcs_sw_reset = true,
-+};
-+
-+static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = msm8998_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
-+ .tx_tbl = msm8998_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8998_pcie_tx_tbl),
-+ .rx_tbl = msm8998_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(msm8998_pcie_rx_tbl),
-+ .pcs_tbl = msm8998_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
-+ .clk_list = msm8996_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-+ .reset_list = ipq8074_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = pciephy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+};
-+
-+static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = msm8998_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
-+ .tx_tbl = msm8998_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl),
-+ .rx_tbl = msm8998_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl),
-+ .pcs_tbl = msm8998_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
-+ .clk_list = msm8996_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sm8150_ufsphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl),
-+ .tx_tbl = sm8150_ufsphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx_tbl),
-+ .rx_tbl = sm8150_ufsphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx_tbl),
-+ .pcs_tbl = sm8150_ufsphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl),
-+ .clk_list = sdm845_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8150_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
-+ .tx_tbl = sm8150_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl),
-+ .rx_tbl = sm8150_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl),
-+ .pcs_tbl = sm8150_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
-+ .clk_list = qmp_v4_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sc8180x_qmp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl),
-+ .tx_tbl = sc8180x_qmp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl),
-+ .rx_tbl = sc8180x_qmp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl),
-+ .pcs_tbl = sc8180x_qmp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sc8180x_qmp_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sc8180x_dpphy_cfg = {
-+ .type = PHY_TYPE_DP,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v4_dp_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
-+ .tx_tbl = qmp_v4_dp_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
-+
-+ .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
-+ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
-+ .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
-+ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
-+ .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
-+ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
-+ .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
-+ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
-+
-+ .clk_list = qmp_v3_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-+ .reset_list = sc7180_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+
-+ .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
-+ .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
-+ .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
-+ .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
-+};
-+
-+static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = {
-+ .usb_cfg = &sm8150_usb3phy_cfg,
-+ .dp_cfg = &sc8180x_dpphy_cfg,
-+};
-+
-+static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = sm8150_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),
-+ .rx_tbl = sm8150_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = sm8150_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v4_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3_uniphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
-+ .tx_tbl = sm8250_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl),
-+ .rx_tbl = sm8250_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl),
-+ .pcs_tbl = sm8250_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
-+ .clk_list = qmp_v4_sm8250_usbphy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = sm8250_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),
-+ .rx_tbl = sm8250_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v4_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3_uniphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sm8250_dpphy_cfg = {
-+ .type = PHY_TYPE_DP,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v4_dp_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
-+ .tx_tbl = qmp_v4_dp_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
-+
-+ .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
-+ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
-+ .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
-+ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
-+ .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
-+ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
-+ .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
-+ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
-+
-+ .clk_list = qmp_v4_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3phy_regs_layout,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+
-+ .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
-+ .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
-+ .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
-+ .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
-+};
-+
-+static const struct qmp_phy_combo_cfg sm8250_usb3dpphy_cfg = {
-+ .usb_cfg = &sm8250_usb3phy_cfg,
-+ .dp_cfg = &sm8250_dpphy_cfg,
-+};
-+
-+static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = sdx55_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl),
-+ .rx_tbl = sdx55_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v4_sdx55_usbphy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3_uniphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sdx55_qmp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl),
-+ .tx_tbl = sdx55_qmp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl),
-+ .rx_tbl = sdx55_qmp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl),
-+ .pcs_tbl = sdx55_qmp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sdx55_qmp_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS_4_20,
-+
-+ .is_dual_lane_phy = true,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = sdx65_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl),
-+ .rx_tbl = sdx65_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v4_sdx55_usbphy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8350_usb3_uniphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sm8350_ufsphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
-+ .tx_tbl = sm8350_ufsphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
-+ .rx_tbl = sm8350_ufsphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
-+ .pcs_tbl = sm8350_ufsphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
-+ .clk_list = sdm845_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8150_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
-+ .tx_tbl = sm8350_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl),
-+ .rx_tbl = sm8350_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl),
-+ .pcs_tbl = sm8350_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl),
-+ .clk_list = qmp_v4_sm8250_usbphy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = sm8350_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),
-+ .rx_tbl = sm8350_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v4_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8350_usb3_uniphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sm8350_ufsphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
-+ .tx_tbl = sm8350_ufsphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
-+ .rx_tbl = sm8350_ufsphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
-+ .pcs_tbl = sm8350_ufsphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
-+ .clk_list = sm8450_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8150_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8450_qmp_gen3x1_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl),
-+ .tx_tbl = sm8450_qmp_gen3x1_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl),
-+ .rx_tbl = sm8450_qmp_gen3x1_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl),
-+ .pcs_tbl = sm8450_qmp_gen3x1_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sm8450_qmp_gen4x2_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl),
-+ .tx_tbl = sm8450_qmp_gen4x2_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl),
-+ .rx_tbl = sm8450_qmp_gen4x2_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl),
-+ .pcs_tbl = sm8450_qmp_gen4x2_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS_4_20,
-+
-+ .is_dual_lane_phy = true,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qcm2290_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl),
-+ .tx_tbl = qcm2290_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl),
-+ .rx_tbl = qcm2290_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(qcm2290_usb3_rx_tbl),
-+ .pcs_tbl = qcm2290_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl),
-+ .clk_list = qcm2290_usb3phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qcm2290_usb3phy_clk_l),
-+ .reset_list = qcm2290_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qcm2290_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+};
-+
-+static void qcom_qmp_phy_configure_lane(void __iomem *base,
-+ const unsigned int *regs,
-+ const struct qmp_phy_init_tbl tbl[],
-+ int num,
-+ u8 lane_mask)
-+{
-+ int i;
-+ const struct qmp_phy_init_tbl *t = tbl;
-+
-+ if (!t)
-+ return;
-+
-+ for (i = 0; i < num; i++, t++) {
-+ if (!(t->lane_mask & lane_mask))
-+ continue;
-+
-+ if (t->in_layout)
-+ writel(t->val, base + regs[t->offset]);
-+ else
-+ writel(t->val, base + t->offset);
-+ }
-+}
-+
-+static void qcom_qmp_phy_configure(void __iomem *base,
-+ const unsigned int *regs,
-+ const struct qmp_phy_init_tbl tbl[],
-+ int num)
-+{
-+ qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff);
-+}
-+
-+static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
-+{
-+ struct qcom_qmp *qmp = qphy->qmp;
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *serdes = qphy->serdes;
-+ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-+ const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
-+ int serdes_tbl_num = cfg->serdes_tbl_num;
-+ int ret;
-+
-+ qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
-+ if (cfg->serdes_tbl_sec)
-+ qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
-+ cfg->serdes_tbl_num_sec);
-+
-+ if (cfg->type == PHY_TYPE_DP) {
-+ switch (dp_opts->link_rate) {
-+ case 1620:
-+ qcom_qmp_phy_configure(serdes, cfg->regs,
-+ cfg->serdes_tbl_rbr,
-+ cfg->serdes_tbl_rbr_num);
-+ break;
-+ case 2700:
-+ qcom_qmp_phy_configure(serdes, cfg->regs,
-+ cfg->serdes_tbl_hbr,
-+ cfg->serdes_tbl_hbr_num);
-+ break;
-+ case 5400:
-+ qcom_qmp_phy_configure(serdes, cfg->regs,
-+ cfg->serdes_tbl_hbr2,
-+ cfg->serdes_tbl_hbr2_num);
-+ break;
-+ case 8100:
-+ qcom_qmp_phy_configure(serdes, cfg->regs,
-+ cfg->serdes_tbl_hbr3,
-+ cfg->serdes_tbl_hbr3_num);
-+ break;
-+ default:
-+ /* Other link rates aren't supported */
-+ return -EINVAL;
-+ }
-+ }
-+
-+
-+ if (cfg->has_phy_com_ctrl) {
-+ void __iomem *status;
-+ unsigned int mask, val;
-+
-+ qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
-+ qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
-+ SERDES_START | PCS_START);
-+
-+ status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
-+ mask = cfg->mask_com_pcs_ready;
-+
-+ ret = readl_poll_timeout(status, val, (val & mask), 10,
-+ PHY_INIT_COMPLETE_TIMEOUT);
-+ if (ret) {
-+ dev_err(qmp->dev,
-+ "phy common block init timed-out\n");
-+ return ret;
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy)
-+{
-+ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
-+ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
-+ qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+
-+ /* Turn on BIAS current for PHY/PLL */
-+ writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
-+ QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
-+ qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
-+
-+ writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+
-+ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
-+ DP_PHY_PD_CTL_LANE_0_1_PWRDN |
-+ DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
-+ DP_PHY_PD_CTL_DP_CLAMP_EN,
-+ qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+
-+ writel(QSERDES_V3_COM_BIAS_EN |
-+ QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
-+ QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL |
-+ QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
-+ qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
-+
-+ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
-+ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-+ writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
-+ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
-+ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
-+ writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
-+ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
-+ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
-+ writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
-+ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
-+ qphy->dp_aux_cfg = 0;
-+
-+ writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
-+ PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
-+ PHY_AUX_REQ_ERR_MASK,
-+ qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
-+}
-+
-+static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = {
-+ { 0x00, 0x0c, 0x15, 0x1a },
-+ { 0x02, 0x0e, 0x16, 0xff },
-+ { 0x02, 0x11, 0xff, 0xff },
-+ { 0x04, 0xff, 0xff, 0xff }
-+};
-+
-+static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = {
-+ { 0x02, 0x12, 0x16, 0x1a },
-+ { 0x09, 0x19, 0x1f, 0xff },
-+ { 0x10, 0x1f, 0xff, 0xff },
-+ { 0x1f, 0xff, 0xff, 0xff }
-+};
-+
-+static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = {
-+ { 0x00, 0x0c, 0x14, 0x19 },
-+ { 0x00, 0x0b, 0x12, 0xff },
-+ { 0x00, 0x0b, 0xff, 0xff },
-+ { 0x04, 0xff, 0xff, 0xff }
-+};
-+
-+static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = {
-+ { 0x08, 0x0f, 0x16, 0x1f },
-+ { 0x11, 0x1e, 0x1f, 0xff },
-+ { 0x19, 0x1f, 0xff, 0xff },
-+ { 0x1f, 0xff, 0xff, 0xff }
-+};
-+
-+static int qcom_qmp_phy_configure_dp_swing(struct qmp_phy *qphy,
-+ unsigned int drv_lvl_reg, unsigned int emp_post_reg)
-+{
-+ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-+ unsigned int v_level = 0, p_level = 0;
-+ u8 voltage_swing_cfg, pre_emphasis_cfg;
-+ int i;
-+
-+ for (i = 0; i < dp_opts->lanes; i++) {
-+ v_level = max(v_level, dp_opts->voltage[i]);
-+ p_level = max(p_level, dp_opts->pre[i]);
-+ }
-+
-+ if (dp_opts->link_rate <= 2700) {
-+ voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level];
-+ pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level];
-+ } else {
-+ voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr3_hbr2[v_level][p_level];
-+ pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr3_hbr2[v_level][p_level];
-+ }
-+
-+ /* TODO: Move check to config check */
-+ if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF)
-+ return -EINVAL;
-+
-+ /* Enable MUX to use Cursor values from these registers */
-+ voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
-+ pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
-+
-+ writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg);
-+ writel(pre_emphasis_cfg, qphy->tx + emp_post_reg);
-+ writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg);
-+ writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg);
-+
-+ return 0;
-+}
-+
-+static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy)
-+{
-+ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-+ u32 bias_en, drvr_en;
-+
-+ if (qcom_qmp_phy_configure_dp_swing(qphy,
-+ QSERDES_V3_TX_TX_DRV_LVL,
-+ QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0)
-+ return;
-+
-+ if (dp_opts->lanes == 1) {
-+ bias_en = 0x3e;
-+ drvr_en = 0x13;
-+ } else {
-+ bias_en = 0x3f;
-+ drvr_en = 0x10;
-+ }
-+
-+ writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN);
-+ writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
-+ writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN);
-+ writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
-+}
-+
-+static bool qcom_qmp_phy_configure_dp_mode(struct qmp_phy *qphy)
-+{
-+ u32 val;
-+ bool reverse = false;
-+
-+ val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
-+ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN;
-+
-+ /*
-+ * TODO: Assume orientation is CC1 for now and two lanes, need to
-+ * use type-c connector to understand orientation and lanes.
-+ *
-+ * Otherwise val changes to be like below if this code understood
-+ * the orientation of the type-c cable.
-+ *
-+ * if (lane_cnt == 4 || orientation == ORIENTATION_CC2)
-+ * val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN;
-+ * if (lane_cnt == 4 || orientation == ORIENTATION_CC1)
-+ * val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
-+ * if (orientation == ORIENTATION_CC2)
-+ * writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
-+ */
-+ val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
-+ writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+
-+ writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE);
-+
-+ return reverse;
-+}
-+
-+static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy)
-+{
-+ const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
-+ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-+ u32 phy_vco_div, status;
-+ unsigned long pixel_freq;
-+
-+ qcom_qmp_phy_configure_dp_mode(qphy);
-+
-+ writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
-+ writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
-+
-+ switch (dp_opts->link_rate) {
-+ case 1620:
-+ phy_vco_div = 0x1;
-+ pixel_freq = 1620000000UL / 2;
-+ break;
-+ case 2700:
-+ phy_vco_div = 0x1;
-+ pixel_freq = 2700000000UL / 2;
-+ break;
-+ case 5400:
-+ phy_vco_div = 0x2;
-+ pixel_freq = 5400000000UL / 4;
-+ break;
-+ case 8100:
-+ phy_vco_div = 0x0;
-+ pixel_freq = 8100000000UL / 6;
-+ break;
-+ default:
-+ /* Other link rates aren't supported */
-+ return -EINVAL;
-+ }
-+ writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV);
-+
-+ clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
-+ clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
-+
-+ writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
-+ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL);
-+
-+ if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS,
-+ status,
-+ ((status & BIT(0)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
-+ status,
-+ ((status & BIT(1)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ udelay(2000);
-+ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
-+ status,
-+ ((status & BIT(1)) > 0),
-+ 500,
-+ 10000);
-+}
-+
-+/*
-+ * We need to calibrate the aux setting here as many times
-+ * as the caller tries
-+ */
-+static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy)
-+{
-+ static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d };
-+ u8 val;
-+
-+ qphy->dp_aux_cfg++;
-+ qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
-+ val = cfg1_settings[qphy->dp_aux_cfg];
-+
-+ writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-+
-+ return 0;
-+}
-+
-+static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy)
-+{
-+ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
-+ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
-+ qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+
-+ /* Turn on BIAS current for PHY/PLL */
-+ writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN);
-+
-+ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
-+ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-+ writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
-+ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
-+ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
-+ writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
-+ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
-+ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
-+ writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
-+ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
-+ qphy->dp_aux_cfg = 0;
-+
-+ writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
-+ PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
-+ PHY_AUX_REQ_ERR_MASK,
-+ qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
-+}
-+
-+static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy)
-+{
-+ /* Program default values before writing proper values */
-+ writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
-+ writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
-+
-+ writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
-+ writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
-+
-+ qcom_qmp_phy_configure_dp_swing(qphy,
-+ QSERDES_V4_TX_TX_DRV_LVL,
-+ QSERDES_V4_TX_TX_EMP_POST1_LVL);
-+}
-+
-+static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy)
-+{
-+ const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
-+ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-+ u32 phy_vco_div, status;
-+ unsigned long pixel_freq;
-+ u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
-+ bool reverse;
-+
-+ writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1);
-+
-+ reverse = qcom_qmp_phy_configure_dp_mode(qphy);
-+
-+ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-+ writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
-+
-+ writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL);
-+ writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL);
-+
-+ switch (dp_opts->link_rate) {
-+ case 1620:
-+ phy_vco_div = 0x1;
-+ pixel_freq = 1620000000UL / 2;
-+ break;
-+ case 2700:
-+ phy_vco_div = 0x1;
-+ pixel_freq = 2700000000UL / 2;
-+ break;
-+ case 5400:
-+ phy_vco_div = 0x2;
-+ pixel_freq = 5400000000UL / 4;
-+ break;
-+ case 8100:
-+ phy_vco_div = 0x0;
-+ pixel_freq = 8100000000UL / 6;
-+ break;
-+ default:
-+ /* Other link rates aren't supported */
-+ return -EINVAL;
-+ }
-+ writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV);
-+
-+ clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
-+ clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
-+
-+ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL);
-+
-+ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS,
-+ status,
-+ ((status & BIT(0)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
-+ status,
-+ ((status & BIT(0)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
-+ status,
-+ ((status & BIT(1)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
-+ status,
-+ ((status & BIT(0)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
-+ status,
-+ ((status & BIT(1)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ /*
-+ * At least for 7nm DP PHY this has to be done after enabling link
-+ * clock.
-+ */
-+
-+ if (dp_opts->lanes == 1) {
-+ bias0_en = reverse ? 0x3e : 0x15;
-+ bias1_en = reverse ? 0x15 : 0x3e;
-+ drvr0_en = reverse ? 0x13 : 0x10;
-+ drvr1_en = reverse ? 0x10 : 0x13;
-+ } else if (dp_opts->lanes == 2) {
-+ bias0_en = reverse ? 0x3f : 0x15;
-+ bias1_en = reverse ? 0x15 : 0x3f;
-+ drvr0_en = 0x10;
-+ drvr1_en = 0x10;
-+ } else {
-+ bias0_en = 0x3f;
-+ bias1_en = 0x3f;
-+ drvr0_en = 0x10;
-+ drvr1_en = 0x10;
-+ }
-+
-+ writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN);
-+ writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
-+ writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN);
-+ writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
-+
-+ writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ udelay(2000);
-+ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
-+ status,
-+ ((status & BIT(1)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV);
-+ writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV);
-+
-+ writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
-+ writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
-+
-+ writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
-+ writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
-+
-+ return 0;
-+}
-+
-+/*
-+ * We need to calibrate the aux setting here as many times
-+ * as the caller tries
-+ */
-+static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy)
-+{
-+ static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d };
-+ u8 val;
-+
-+ qphy->dp_aux_cfg++;
-+ qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
-+ val = cfg1_settings[qphy->dp_aux_cfg];
-+
-+ writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
-+{
-+ const struct phy_configure_opts_dp *dp_opts = &opts->dp;
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+
-+ memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts));
-+ if (qphy->dp_opts.set_voltages) {
-+ cfg->configure_dp_tx(qphy);
-+ qphy->dp_opts.set_voltages = 0;
-+ }
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_dp_phy_calibrate(struct phy *phy)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+
-+ if (cfg->calibrate_dp_phy)
-+ return cfg->calibrate_dp_phy(qphy);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
-+{
-+ struct qcom_qmp *qmp = qphy->qmp;
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *serdes = qphy->serdes;
-+ void __iomem *pcs = qphy->pcs;
-+ void __iomem *dp_com = qmp->dp_com;
-+ int ret, i;
-+
-+ mutex_lock(&qmp->phy_mutex);
-+ if (qmp->init_count++) {
-+ mutex_unlock(&qmp->phy_mutex);
-+ return 0;
-+ }
-+
-+ /* turn on regulator supplies */
-+ ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
-+ if (ret) {
-+ dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
-+ goto err_unlock;
-+ }
-+
-+ for (i = 0; i < cfg->num_resets; i++) {
-+ ret = reset_control_assert(qmp->resets[i]);
-+ if (ret) {
-+ dev_err(qmp->dev, "%s reset assert failed\n",
-+ cfg->reset_list[i]);
-+ goto err_disable_regulators;
-+ }
-+ }
-+
-+ for (i = cfg->num_resets - 1; i >= 0; i--) {
-+ ret = reset_control_deassert(qmp->resets[i]);
-+ if (ret) {
-+ dev_err(qmp->dev, "%s reset deassert failed\n",
-+ qphy->cfg->reset_list[i]);
-+ goto err_assert_reset;
-+ }
-+ }
-+
-+ ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
-+ if (ret)
-+ goto err_assert_reset;
-+
-+ if (cfg->has_phy_dp_com_ctrl) {
-+ qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
-+ SW_PWRDN);
-+ /* override hardware control for reset of qmp phy */
-+ qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
-+ SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
-+ SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
-+
-+ /* Default type-c orientation, i.e CC1 */
-+ qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02);
-+
-+ qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
-+ USB3_MODE | DP_MODE);
-+
-+ /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
-+ qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
-+ SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
-+ SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
-+
-+ qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
-+ qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
-+ }
-+
-+ if (cfg->has_phy_com_ctrl) {
-+ qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
-+ SW_PWRDN);
-+ } else {
-+ if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
-+ qphy_setbits(pcs,
-+ cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
-+ cfg->pwrdn_ctrl);
-+ else
-+ qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
-+ cfg->pwrdn_ctrl);
-+ }
-+
-+ mutex_unlock(&qmp->phy_mutex);
-+
-+ return 0;
-+
-+err_assert_reset:
-+ while (++i < cfg->num_resets)
-+ reset_control_assert(qmp->resets[i]);
-+err_disable_regulators:
-+ regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
-+err_unlock:
-+ mutex_unlock(&qmp->phy_mutex);
-+
-+ return ret;
-+}
-+
-+static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy)
-+{
-+ struct qcom_qmp *qmp = qphy->qmp;
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *serdes = qphy->serdes;
-+ int i = cfg->num_resets;
-+
-+ mutex_lock(&qmp->phy_mutex);
-+ if (--qmp->init_count) {
-+ mutex_unlock(&qmp->phy_mutex);
-+ return 0;
-+ }
-+
-+ reset_control_assert(qmp->ufs_reset);
-+ if (cfg->has_phy_com_ctrl) {
-+ qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
-+ SERDES_START | PCS_START);
-+ qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
-+ SW_RESET);
-+ qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
-+ SW_PWRDN);
-+ }
-+
-+ while (--i >= 0)
-+ reset_control_assert(qmp->resets[i]);
-+
-+ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
-+
-+ regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
-+
-+ mutex_unlock(&qmp->phy_mutex);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_init(struct phy *phy)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ struct qcom_qmp *qmp = qphy->qmp;
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ int ret;
-+ dev_vdbg(qmp->dev, "Initializing QMP phy\n");
-+
-+ if (cfg->no_pcs_sw_reset) {
-+ /*
-+ * Get UFS reset, which is delayed until now to avoid a
-+ * circular dependency where UFS needs its PHY, but the PHY
-+ * needs this UFS reset.
-+ */
-+ if (!qmp->ufs_reset) {
-+ qmp->ufs_reset =
-+ devm_reset_control_get_exclusive(qmp->dev,
-+ "ufsphy");
-+
-+ if (IS_ERR(qmp->ufs_reset)) {
-+ ret = PTR_ERR(qmp->ufs_reset);
-+ dev_err(qmp->dev,
-+ "failed to get UFS reset: %d\n",
-+ ret);
-+
-+ qmp->ufs_reset = NULL;
-+ return ret;
-+ }
-+ }
-+
-+ ret = reset_control_assert(qmp->ufs_reset);
-+ if (ret)
-+ return ret;
-+ }
-+
-+ ret = qcom_qmp_phy_com_init(qphy);
-+ if (ret)
-+ return ret;
-+
-+ if (cfg->type == PHY_TYPE_DP)
-+ cfg->dp_aux_init(qphy);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_power_on(struct phy *phy)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ struct qcom_qmp *qmp = qphy->qmp;
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *tx = qphy->tx;
-+ void __iomem *rx = qphy->rx;
-+ void __iomem *pcs = qphy->pcs;
-+ void __iomem *pcs_misc = qphy->pcs_misc;
-+ void __iomem *status;
-+ unsigned int mask, val, ready;
-+ int ret;
-+
-+ qcom_qmp_phy_serdes_init(qphy);
-+
-+ if (cfg->has_lane_rst) {
-+ ret = reset_control_deassert(qphy->lane_rst);
-+ if (ret) {
-+ dev_err(qmp->dev, "lane%d reset deassert failed\n",
-+ qphy->index);
-+ return ret;
-+ }
-+ }
-+
-+ ret = clk_prepare_enable(qphy->pipe_clk);
-+ if (ret) {
-+ dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
-+ goto err_reset_lane;
-+ }
-+
-+ /* Tx, Rx, and PCS configurations */
-+ qcom_qmp_phy_configure_lane(tx, cfg->regs,
-+ cfg->tx_tbl, cfg->tx_tbl_num, 1);
-+ if (cfg->tx_tbl_sec)
-+ qcom_qmp_phy_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
-+ cfg->tx_tbl_num_sec, 1);
-+
-+ /* Configuration for other LANE for USB-DP combo PHY */
-+ if (cfg->is_dual_lane_phy) {
-+ qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
-+ cfg->tx_tbl, cfg->tx_tbl_num, 2);
-+ if (cfg->tx_tbl_sec)
-+ qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
-+ cfg->tx_tbl_sec,
-+ cfg->tx_tbl_num_sec, 2);
-+ }
-+
-+ /* Configure special DP tx tunings */
-+ if (cfg->type == PHY_TYPE_DP)
-+ cfg->configure_dp_tx(qphy);
-+
-+ qcom_qmp_phy_configure_lane(rx, cfg->regs,
-+ cfg->rx_tbl, cfg->rx_tbl_num, 1);
-+ if (cfg->rx_tbl_sec)
-+ qcom_qmp_phy_configure_lane(rx, cfg->regs,
-+ cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1);
-+
-+ if (cfg->is_dual_lane_phy) {
-+ qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
-+ cfg->rx_tbl, cfg->rx_tbl_num, 2);
-+ if (cfg->rx_tbl_sec)
-+ qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
-+ cfg->rx_tbl_sec,
-+ cfg->rx_tbl_num_sec, 2);
-+ }
-+
-+ /* Configure link rate, swing, etc. */
-+ if (cfg->type == PHY_TYPE_DP) {
-+ cfg->configure_dp_phy(qphy);
-+ } else {
-+ qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
-+ if (cfg->pcs_tbl_sec)
-+ qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
-+ cfg->pcs_tbl_num_sec);
-+ }
-+
-+ ret = reset_control_deassert(qmp->ufs_reset);
-+ if (ret)
-+ goto err_disable_pipe_clk;
-+
-+ qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
-+ cfg->pcs_misc_tbl_num);
-+ if (cfg->pcs_misc_tbl_sec)
-+ qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
-+ cfg->pcs_misc_tbl_num_sec);
-+
-+ /*
-+ * Pull out PHY from POWER DOWN state.
-+ * This is active low enable signal to power-down PHY.
-+ */
-+ if(cfg->type == PHY_TYPE_PCIE)
-+ qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
-+
-+ if (cfg->has_pwrdn_delay)
-+ usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
-+
-+ if (cfg->type != PHY_TYPE_DP) {
-+ /* Pull PHY out of reset state */
-+ if (!cfg->no_pcs_sw_reset)
-+ qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
-+ /* start SerDes and Phy-Coding-Sublayer */
-+ qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
-+
-+ if (cfg->type == PHY_TYPE_UFS) {
-+ status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
-+ mask = PCS_READY;
-+ ready = PCS_READY;
-+ } else {
-+ status = pcs + cfg->regs[QPHY_PCS_STATUS];
-+ mask = cfg->phy_status;
-+ ready = 0;
-+ }
-+
-+ ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
-+ PHY_INIT_COMPLETE_TIMEOUT);
-+ if (ret) {
-+ dev_err(qmp->dev, "phy initialization timed-out\n");
-+ goto err_disable_pipe_clk;
-+ }
-+ }
-+ return 0;
-+
-+err_disable_pipe_clk:
-+ clk_disable_unprepare(qphy->pipe_clk);
-+err_reset_lane:
-+ if (cfg->has_lane_rst)
-+ reset_control_assert(qphy->lane_rst);
-+
-+ return ret;
-+}
-+
-+static int qcom_qmp_phy_power_off(struct phy *phy)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+
-+ clk_disable_unprepare(qphy->pipe_clk);
-+
-+ if (cfg->type == PHY_TYPE_DP) {
-+ /* Assert DP PHY power down */
-+ writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+ } else {
-+ /* PHY reset */
-+ if (!cfg->no_pcs_sw_reset)
-+ qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
-+
-+ /* stop SerDes and Phy-Coding-Sublayer */
-+ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
-+
-+ /* Put PHY into POWER DOWN state: active low */
-+ if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
-+ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
-+ cfg->pwrdn_ctrl);
-+ } else {
-+ qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
-+ cfg->pwrdn_ctrl);
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_exit(struct phy *phy)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+
-+ if (cfg->has_lane_rst)
-+ reset_control_assert(qphy->lane_rst);
-+
-+ qcom_qmp_phy_com_exit(qphy);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_enable(struct phy *phy)
-+{
-+ int ret;
-+
-+ ret = qcom_qmp_phy_init(phy);
-+ if (ret)
-+ return ret;
-+
-+ ret = qcom_qmp_phy_power_on(phy);
-+ if (ret)
-+ qcom_qmp_phy_exit(phy);
-+
-+ return ret;
-+}
-+
-+static int qcom_qmp_phy_disable(struct phy *phy)
-+{
-+ int ret;
-+
-+ ret = qcom_qmp_phy_power_off(phy);
-+ if (ret)
-+ return ret;
-+ return qcom_qmp_phy_exit(phy);
-+}
-+
-+static int qcom_qmp_phy_set_mode(struct phy *phy,
-+ enum phy_mode mode, int submode)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+
-+ qphy->mode = mode;
-+
-+ return 0;
-+}
-+
-+static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
-+{
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *pcs = qphy->pcs;
-+ void __iomem *pcs_misc = qphy->pcs_misc;
-+ u32 intr_mask;
-+
-+ if (qphy->mode == PHY_MODE_USB_HOST_SS ||
-+ qphy->mode == PHY_MODE_USB_DEVICE_SS)
-+ intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
-+ else
-+ intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
-+
-+ /* Clear any pending interrupts status */
-+ qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
-+ /* Writing 1 followed by 0 clears the interrupt */
-+ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
-+
-+ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
-+ ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
-+
-+ /* Enable required PHY autonomous mode interrupts */
-+ qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
-+
-+ /* Enable i/o clamp_n for autonomous mode */
-+ if (pcs_misc)
-+ qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
-+}
-+
-+static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
-+{
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *pcs = qphy->pcs;
-+ void __iomem *pcs_misc = qphy->pcs_misc;
-+
-+ /* Disable i/o clamp_n on resume for normal mode */
-+ if (pcs_misc)
-+ qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
-+
-+ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
-+ ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
-+
-+ qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
-+ /* Writing 1 followed by 0 clears the interrupt */
-+ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
-+}
-+
-+static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ struct qmp_phy *qphy = qmp->phys[0];
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+
-+ dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode);
-+
-+ /* Supported only for USB3 PHY and luckily USB3 is the first phy */
-+ if (cfg->type != PHY_TYPE_USB3)
-+ return 0;
-+
-+ if (!qmp->init_count) {
-+ dev_vdbg(dev, "PHY not initialized, bailing out\n");
-+ return 0;
-+ }
-+
-+ qcom_qmp_phy_enable_autonomous_mode(qphy);
-+
-+ clk_disable_unprepare(qphy->pipe_clk);
-+ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
-+
-+ return 0;
-+}
-+
-+static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ struct qmp_phy *qphy = qmp->phys[0];
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ int ret = 0;
-+
-+ dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode);
-+
-+ /* Supported only for USB3 PHY and luckily USB3 is the first phy */
-+ if (cfg->type != PHY_TYPE_USB3)
-+ return 0;
-+
-+ if (!qmp->init_count) {
-+ dev_vdbg(dev, "PHY not initialized, bailing out\n");
-+ return 0;
-+ }
-+
-+ ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
-+ if (ret)
-+ return ret;
-+
-+ ret = clk_prepare_enable(qphy->pipe_clk);
-+ if (ret) {
-+ dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
-+ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
-+ return ret;
-+ }
-+
-+ qcom_qmp_phy_disable_autonomous_mode(qphy);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ int num = cfg->num_vregs;
-+ int i;
-+
-+ qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
-+ if (!qmp->vregs)
-+ return -ENOMEM;
-+
-+ for (i = 0; i < num; i++)
-+ qmp->vregs[i].supply = cfg->vreg_list[i];
-+
-+ return devm_regulator_bulk_get(dev, num, qmp->vregs);
-+}
-+
-+static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ int i;
-+
-+ qmp->resets = devm_kcalloc(dev, cfg->num_resets,
-+ sizeof(*qmp->resets), GFP_KERNEL);
-+ if (!qmp->resets)
-+ return -ENOMEM;
-+
-+ for (i = 0; i < cfg->num_resets; i++) {
-+ struct reset_control *rst;
-+ const char *name = cfg->reset_list[i];
-+
-+ rst = devm_reset_control_get_exclusive(dev, name);
-+ if (IS_ERR(rst)) {
-+ dev_err(dev, "failed to get %s reset\n", name);
-+ return PTR_ERR(rst);
-+ }
-+ qmp->resets[i] = rst;
-+ }
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ int num = cfg->num_clks;
-+ int i;
-+
-+ qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
-+ if (!qmp->clks)
-+ return -ENOMEM;
-+
-+ for (i = 0; i < num; i++)
-+ qmp->clks[i].id = cfg->clk_list[i];
-+
-+ return devm_clk_bulk_get(dev, num, qmp->clks);
-+}
-+
-+static void phy_clk_release_provider(void *res)
-+{
-+ of_clk_del_provider(res);
-+}
-+
-+/*
-+ * Register a fixed rate pipe clock.
-+ *
-+ * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
-+ * controls it. The <s>_pipe_clk coming out of the GCC is requested
-+ * by the PHY driver for its operations.
-+ * We register the <s>_pipe_clksrc here. The gcc driver takes care
-+ * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
-+ * Below picture shows this relationship.
-+ *
-+ * +---------------+
-+ * | PHY block |<<---------------------------------------+
-+ * | | |
-+ * | +-------+ | +-----+ |
-+ * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
-+ * clk | +-------+ | +-----+
-+ * +---------------+
-+ */
-+static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
-+{
-+ struct clk_fixed_rate *fixed;
-+ struct clk_init_data init = { };
-+ int ret;
-+
-+ ret = of_property_read_string(np, "clock-output-names", &init.name);
-+ if (ret) {
-+ dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
-+ return ret;
-+ }
-+
-+ fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
-+ if (!fixed)
-+ return -ENOMEM;
-+
-+ init.ops = &clk_fixed_rate_ops;
-+
-+ /* controllers using QMP phys use 125MHz pipe clock interface */
-+ fixed->fixed_rate = 125000000;
-+ fixed->hw.init = &init;
-+
-+ ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
-+ if (ret)
-+ return ret;
-+
-+ ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
-+ if (ret)
-+ return ret;
-+
-+ /*
-+ * Roll a devm action because the clock provider is the child node, but
-+ * the child node is not actually a device.
-+ */
-+ return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
-+}
-+
-+/*
-+ * Display Port PLL driver block diagram for branch clocks
-+ *
-+ * +------------------------------+
-+ * | DP_VCO_CLK |
-+ * | |
-+ * | +-------------------+ |
-+ * | | (DP PLL/VCO) | |
-+ * | +---------+---------+ |
-+ * | v |
-+ * | +----------+-----------+ |
-+ * | | hsclk_divsel_clk_src | |
-+ * | +----------+-----------+ |
-+ * +------------------------------+
-+ * |
-+ * +---------<---------v------------>----------+
-+ * | |
-+ * +--------v----------------+ |
-+ * | dp_phy_pll_link_clk | |
-+ * | link_clk | |
-+ * +--------+----------------+ |
-+ * | |
-+ * | |
-+ * v v
-+ * Input to DISPCC block |
-+ * for link clk, crypto clk |
-+ * and interface clock |
-+ * |
-+ * |
-+ * +--------<------------+-----------------+---<---+
-+ * | | |
-+ * +----v---------+ +--------v-----+ +--------v------+
-+ * | vco_divided | | vco_divided | | vco_divided |
-+ * | _clk_src | | _clk_src | | _clk_src |
-+ * | | | | | |
-+ * |divsel_six | | divsel_two | | divsel_four |
-+ * +-------+------+ +-----+--------+ +--------+------+
-+ * | | |
-+ * v---->----------v-------------<------v
-+ * |
-+ * +----------+-----------------+
-+ * | dp_phy_pll_vco_div_clk |
-+ * +---------+------------------+
-+ * |
-+ * v
-+ * Input to DISPCC block
-+ * for DP pixel clock
-+ *
-+ */
-+static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw,
-+ struct clk_rate_request *req)
-+{
-+ switch (req->rate) {
-+ case 1620000000UL / 2:
-+ case 2700000000UL / 2:
-+ /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */
-+ return 0;
-+ default:
-+ return -EINVAL;
-+ }
-+}
-+
-+static unsigned long
-+qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
-+{
-+ const struct qmp_phy_dp_clks *dp_clks;
-+ const struct qmp_phy *qphy;
-+ const struct phy_configure_opts_dp *dp_opts;
-+
-+ dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw);
-+ qphy = dp_clks->qphy;
-+ dp_opts = &qphy->dp_opts;
-+
-+ switch (dp_opts->link_rate) {
-+ case 1620:
-+ return 1620000000UL / 2;
-+ case 2700:
-+ return 2700000000UL / 2;
-+ case 5400:
-+ return 5400000000UL / 4;
-+ case 8100:
-+ return 8100000000UL / 6;
-+ default:
-+ return 0;
-+ }
-+}
-+
-+static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = {
-+ .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate,
-+ .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate,
-+};
-+
-+static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw,
-+ struct clk_rate_request *req)
-+{
-+ switch (req->rate) {
-+ case 162000000:
-+ case 270000000:
-+ case 540000000:
-+ case 810000000:
-+ return 0;
-+ default:
-+ return -EINVAL;
-+ }
-+}
-+
-+static unsigned long
-+qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
-+{
-+ const struct qmp_phy_dp_clks *dp_clks;
-+ const struct qmp_phy *qphy;
-+ const struct phy_configure_opts_dp *dp_opts;
-+
-+ dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw);
-+ qphy = dp_clks->qphy;
-+ dp_opts = &qphy->dp_opts;
-+
-+ switch (dp_opts->link_rate) {
-+ case 1620:
-+ case 2700:
-+ case 5400:
-+ case 8100:
-+ return dp_opts->link_rate * 100000;
-+ default:
-+ return 0;
-+ }
-+}
-+
-+static const struct clk_ops qcom_qmp_dp_link_clk_ops = {
-+ .determine_rate = qcom_qmp_dp_link_clk_determine_rate,
-+ .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate,
-+};
-+
-+static struct clk_hw *
-+qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data)
-+{
-+ struct qmp_phy_dp_clks *dp_clks = data;
-+ unsigned int idx = clkspec->args[0];
-+
-+ if (idx >= 2) {
-+ pr_err("%s: invalid index %u\n", __func__, idx);
-+ return ERR_PTR(-EINVAL);
-+ }
-+
-+ if (idx == 0)
-+ return &dp_clks->dp_link_hw;
-+
-+ return &dp_clks->dp_pixel_hw;
-+}
-+
-+static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy,
-+ struct device_node *np)
-+{
-+ struct clk_init_data init = { };
-+ struct qmp_phy_dp_clks *dp_clks;
-+ char name[64];
-+ int ret;
-+
-+ dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL);
-+ if (!dp_clks)
-+ return -ENOMEM;
-+
-+ dp_clks->qphy = qphy;
-+ qphy->dp_clks = dp_clks;
-+
-+ snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev));
-+ init.ops = &qcom_qmp_dp_link_clk_ops;
-+ init.name = name;
-+ dp_clks->dp_link_hw.init = &init;
-+ ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw);
-+ if (ret)
-+ return ret;
-+
-+ snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev));
-+ init.ops = &qcom_qmp_dp_pixel_clk_ops;
-+ init.name = name;
-+ dp_clks->dp_pixel_hw.init = &init;
-+ ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw);
-+ if (ret)
-+ return ret;
-+
-+ ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks);
-+ if (ret)
-+ return ret;
-+
-+ /*
-+ * Roll a devm action because the clock provider is the child node, but
-+ * the child node is not actually a device.
-+ */
-+ return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
-+}
-+
-+static const struct phy_ops qcom_qmp_phy_gen_ops = {
-+ .init = qcom_qmp_phy_enable,
-+ .exit = qcom_qmp_phy_disable,
-+ .set_mode = qcom_qmp_phy_set_mode,
-+ .owner = THIS_MODULE,
-+};
-+
-+static const struct phy_ops qcom_qmp_phy_dp_ops = {
-+ .init = qcom_qmp_phy_init,
-+ .configure = qcom_qmp_dp_phy_configure,
-+ .power_on = qcom_qmp_phy_power_on,
-+ .calibrate = qcom_qmp_dp_phy_calibrate,
-+ .power_off = qcom_qmp_phy_power_off,
-+ .exit = qcom_qmp_phy_exit,
-+ .set_mode = qcom_qmp_phy_set_mode,
-+ .owner = THIS_MODULE,
-+};
-+
-+static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
-+ .power_on = qcom_qmp_phy_enable,
-+ .power_off = qcom_qmp_phy_disable,
-+ .set_mode = qcom_qmp_phy_set_mode,
-+ .owner = THIS_MODULE,
-+};
-+
-+static void qcom_qmp_reset_control_put(void *data)
-+{
-+ reset_control_put(data);
-+}
-+
-+static
-+int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
-+ void __iomem *serdes, const struct qmp_phy_cfg *cfg)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ struct phy *generic_phy;
-+ struct qmp_phy *qphy;
-+ const struct phy_ops *ops;
-+ char prop_name[MAX_PROP_NAME];
-+ int ret;
-+
-+ qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
-+ if (!qphy)
-+ return -ENOMEM;
-+
-+ qphy->cfg = cfg;
-+ qphy->serdes = serdes;
-+ /*
-+ * Get memory resources for each phy lane:
-+ * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
-+ * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
-+ * For single lane PHYs: pcs_misc (optional) -> 3.
-+ */
-+ qphy->tx = of_iomap(np, 0);
-+ if (!qphy->tx)
-+ return -ENOMEM;
-+
-+ qphy->rx = of_iomap(np, 1);
-+ if (!qphy->rx)
-+ return -ENOMEM;
-+
-+ qphy->pcs = of_iomap(np, 2);
-+ if (!qphy->pcs)
-+ return -ENOMEM;
-+
-+ /*
-+ * If this is a dual-lane PHY, then there should be registers for the
-+ * second lane. Some old device trees did not specify this, so fall
-+ * back to old legacy behavior of assuming they can be reached at an
-+ * offset from the first lane.
-+ */
-+ if (cfg->is_dual_lane_phy) {
-+ qphy->tx2 = of_iomap(np, 3);
-+ qphy->rx2 = of_iomap(np, 4);
-+ if (!qphy->tx2 || !qphy->rx2) {
-+ dev_warn(dev,
-+ "Underspecified device tree, falling back to legacy register regions\n");
-+
-+ /* In the old version, pcs_misc is at index 3. */
-+ qphy->pcs_misc = qphy->tx2;
-+ qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE;
-+ qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
-+
-+ } else {
-+ qphy->pcs_misc = of_iomap(np, 5);
-+ }
-+
-+ } else {
-+ qphy->pcs_misc = of_iomap(np, 3);
-+ }
-+
-+ if (!qphy->pcs_misc)
-+ dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
-+
-+ /*
-+ * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3
-+ * based phys, so they essentially have pipe clock. So,
-+ * we return error in case phy is USB3 or PIPE type.
-+ * Otherwise, we initialize pipe clock to NULL for
-+ * all phys that don't need this.
-+ */
-+ snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
-+ qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name);
-+ if (IS_ERR(qphy->pipe_clk)) {
-+ if (cfg->type == PHY_TYPE_PCIE ||
-+ cfg->type == PHY_TYPE_USB3) {
-+ ret = PTR_ERR(qphy->pipe_clk);
-+ if (ret != -EPROBE_DEFER)
-+ dev_err(dev,
-+ "failed to get lane%d pipe_clk, %d\n",
-+ id, ret);
-+ return ret;
-+ }
-+ qphy->pipe_clk = NULL;
-+ }
-+
-+ /* Get lane reset, if any */
-+ if (cfg->has_lane_rst) {
-+ snprintf(prop_name, sizeof(prop_name), "lane%d", id);
-+ qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name);
-+ if (IS_ERR(qphy->lane_rst)) {
-+ dev_err(dev, "failed to get lane%d reset\n", id);
-+ return PTR_ERR(qphy->lane_rst);
-+ }
-+ ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put,
-+ qphy->lane_rst);
-+ if (ret)
-+ return ret;
-+ }
-+
-+ if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE)
-+ ops = &qcom_qmp_pcie_ufs_ops;
-+ else if (cfg->type == PHY_TYPE_DP)
-+ ops = &qcom_qmp_phy_dp_ops;
-+ else
-+ ops = &qcom_qmp_phy_gen_ops;
-+
-+ generic_phy = devm_phy_create(dev, np, ops);
-+ if (IS_ERR(generic_phy)) {
-+ ret = PTR_ERR(generic_phy);
-+ dev_err(dev, "failed to create qphy %d\n", ret);
-+ return ret;
-+ }
-+
-+ qphy->phy = generic_phy;
-+ qphy->index = id;
-+ qphy->qmp = qmp;
-+ qmp->phys[id] = qphy;
-+ phy_set_drvdata(generic_phy, qphy);
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
-+ {
-+ .compatible = "qcom,ipq8074-qmp-usb3-phy",
-+ .data = &ipq8074_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,msm8996-qmp-pcie-phy",
-+ .data = &msm8996_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,msm8996-qmp-ufs-phy",
-+ .data = &msm8996_ufs_cfg,
-+ }, {
-+ .compatible = "qcom,msm8996-qmp-usb3-phy",
-+ .data = &msm8996_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,msm8998-qmp-pcie-phy",
-+ .data = &msm8998_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,msm8998-qmp-ufs-phy",
-+ .data = &sdm845_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,ipq8074-qmp-pcie-phy",
-+ .data = &ipq8074_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,ipq6018-qmp-pcie-phy",
-+ .data = &ipq6018_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,ipq6018-qmp-usb3-phy",
-+ .data = &ipq8074_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sc7180-qmp-usb3-phy",
-+ .data = &sc7180_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
-+ /* It's a combo phy */
-+ }, {
-+ .compatible = "qcom,sc8180x-qmp-pcie-phy",
-+ .data = &sc8180x_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sc8180x-qmp-ufs-phy",
-+ .data = &sm8150_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sc8280xp-qmp-ufs-phy",
-+ .data = &sm8350_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sc8180x-qmp-usb3-phy",
-+ .data = &sm8150_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
-+ /* It's a combo phy */
-+ }, {
-+ .compatible = "qcom,sdm845-qhp-pcie-phy",
-+ .data = &sdm845_qhp_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sdm845-qmp-pcie-phy",
-+ .data = &sdm845_qmp_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sdm845-qmp-usb3-phy",
-+ .data = &qmp_v3_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
-+ .data = &qmp_v3_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sdm845-qmp-ufs-phy",
-+ .data = &sdm845_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,msm8998-qmp-usb3-phy",
-+ .data = &msm8998_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sm6115-qmp-ufs-phy",
-+ .data = &sm6115_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm6350-qmp-ufs-phy",
-+ .data = &sdm845_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8150-qmp-ufs-phy",
-+ .data = &sm8150_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-ufs-phy",
-+ .data = &sm8150_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8150-qmp-usb3-phy",
-+ .data = &sm8150_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8150-qmp-usb3-uni-phy",
-+ .data = &sm8150_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-usb3-phy",
-+ .data = &sm8250_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
-+ /* It's a combo phy */
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-usb3-uni-phy",
-+ .data = &sm8250_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
-+ .data = &sm8250_qmp_gen3x1_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
-+ .data = &sm8250_qmp_gen3x2_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8350-qmp-ufs-phy",
-+ .data = &sm8350_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
-+ .data = &sm8250_qmp_gen3x2_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sdx55-qmp-pcie-phy",
-+ .data = &sdx55_qmp_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sdx55-qmp-usb3-uni-phy",
-+ .data = &sdx55_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sdx65-qmp-usb3-uni-phy",
-+ .data = &sdx65_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8350-qmp-usb3-phy",
-+ .data = &sm8350_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8350-qmp-usb3-uni-phy",
-+ .data = &sm8350_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
-+ .data = &sm8450_qmp_gen3x1_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
-+ .data = &sm8450_qmp_gen4x2_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8450-qmp-ufs-phy",
-+ .data = &sm8450_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8450-qmp-usb3-phy",
-+ .data = &sm8350_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,qcm2290-qmp-usb3-phy",
-+ .data = &qcm2290_usb3phy_cfg,
-+ },
-+ { },
-+};
-+MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
-+
-+static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = {
-+ {
-+ .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
-+ .data = &sc7180_usb3dpphy_cfg,
-+ },
-+ {
-+ .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
-+ .data = &sm8250_usb3dpphy_cfg,
-+ },
-+ {
-+ .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
-+ .data = &sc8180x_usb3dpphy_cfg,
-+ },
-+ { }
-+};
-+
-+static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
-+ SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
-+ qcom_qmp_phy_runtime_resume, NULL)
-+};
-+
-+static int qcom_qmp_phy_probe(struct platform_device *pdev)
-+{
-+ struct qcom_qmp *qmp;
-+ struct device *dev = &pdev->dev;
-+ struct device_node *child;
-+ struct phy_provider *phy_provider;
-+ void __iomem *serdes;
-+ void __iomem *usb_serdes;
-+ void __iomem *dp_serdes = NULL;
-+ const struct qmp_phy_combo_cfg *combo_cfg = NULL;
-+ const struct qmp_phy_cfg *cfg = NULL;
-+ const struct qmp_phy_cfg *usb_cfg = NULL;
-+ const struct qmp_phy_cfg *dp_cfg = NULL;
-+ int num, id, expected_phys;
-+ int ret;
-+
-+ qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
-+ if (!qmp)
-+ return -ENOMEM;
-+
-+ qmp->dev = dev;
-+ dev_set_drvdata(dev, qmp);
-+
-+ /* Get the specific init parameters of QMP phy */
-+ cfg = of_device_get_match_data(dev);
-+ if (!cfg) {
-+ const struct of_device_id *match;
-+
-+ match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev);
-+ if (!match)
-+ return -EINVAL;
-+
-+ combo_cfg = match->data;
-+ if (!combo_cfg)
-+ return -EINVAL;
-+
-+ usb_cfg = combo_cfg->usb_cfg;
-+ cfg = usb_cfg; /* Setup clks and regulators */
-+ }
-+
-+ /* per PHY serdes; usually located at base address */
-+ usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0);
-+ if (IS_ERR(serdes))
-+ return PTR_ERR(serdes);
-+
-+ /* per PHY dp_com; if PHY has dp_com control block */
-+ if (combo_cfg || cfg->has_phy_dp_com_ctrl) {
-+ qmp->dp_com = devm_platform_ioremap_resource(pdev, 1);
-+ if (IS_ERR(qmp->dp_com))
-+ return PTR_ERR(qmp->dp_com);
-+ }
-+
-+ if (combo_cfg) {
-+ /* Only two serdes for combo PHY */
-+ dp_serdes = devm_platform_ioremap_resource(pdev, 2);
-+ if (IS_ERR(dp_serdes))
-+ return PTR_ERR(dp_serdes);
-+
-+ dp_cfg = combo_cfg->dp_cfg;
-+ expected_phys = 2;
-+ } else {
-+ expected_phys = cfg->nlanes;
-+ }
-+
-+ mutex_init(&qmp->phy_mutex);
-+
-+ ret = qcom_qmp_phy_clk_init(dev, cfg);
-+ if (ret)
-+ return ret;
-+
-+ ret = qcom_qmp_phy_reset_init(dev, cfg);
-+ if (ret)
-+ return ret;
-+
-+ ret = qcom_qmp_phy_vreg_init(dev, cfg);
-+ if (ret) {
-+ if (ret != -EPROBE_DEFER)
-+ dev_err(dev, "failed to get regulator supplies: %d\n",
-+ ret);
-+ return ret;
-+ }
-+
-+ num = of_get_available_child_count(dev->of_node);
-+ /* do we have a rogue child node ? */
-+ if (num > expected_phys)
-+ return -EINVAL;
-+
-+ qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
-+ if (!qmp->phys)
-+ return -ENOMEM;
-+
-+ pm_runtime_set_active(dev);
-+ pm_runtime_enable(dev);
-+ /*
-+ * Prevent runtime pm from being ON by default. Users can enable
-+ * it using power/control in sysfs.
-+ */
-+ pm_runtime_forbid(dev);
-+
-+ id = 0;
-+ for_each_available_child_of_node(dev->of_node, child) {
-+ if (of_node_name_eq(child, "dp-phy")) {
-+ cfg = dp_cfg;
-+ serdes = dp_serdes;
-+ } else if (of_node_name_eq(child, "usb3-phy")) {
-+ cfg = usb_cfg;
-+ serdes = usb_serdes;
-+ }
-+
-+ /* Create per-lane phy */
-+ ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg);
-+ if (ret) {
-+ dev_err(dev, "failed to create lane%d phy, %d\n",
-+ id, ret);
-+ goto err_node_put;
-+ }
-+
-+ /*
-+ * Register the pipe clock provided by phy.
-+ * See function description to see details of this pipe clock.
-+ */
-+ if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) {
-+ ret = phy_pipe_clk_register(qmp, child);
-+ if (ret) {
-+ dev_err(qmp->dev,
-+ "failed to register pipe clock source\n");
-+ goto err_node_put;
-+ }
-+ } else if (cfg->type == PHY_TYPE_DP) {
-+ ret = phy_dp_clks_register(qmp, qmp->phys[id], child);
-+ if (ret) {
-+ dev_err(qmp->dev,
-+ "failed to register DP clock source\n");
-+ goto err_node_put;
-+ }
-+ }
-+ id++;
-+ }
-+
-+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
-+ if (!IS_ERR(phy_provider))
-+ dev_info(dev, "Registered Qcom-QMP phy\n");
-+ else
-+ pm_runtime_disable(dev);
-+
-+ return PTR_ERR_OR_ZERO(phy_provider);
-+
-+err_node_put:
-+ pm_runtime_disable(dev);
-+ of_node_put(child);
-+ return ret;
-+}
-+
-+static struct platform_driver qcom_qmp_phy_driver = {
-+ .probe = qcom_qmp_phy_probe,
-+ .driver = {
-+ .name = "qcom-qmp-phy",
-+ .pm = &qcom_qmp_phy_pm_ops,
-+ .of_match_table = qcom_qmp_phy_of_match_table,
-+ },
-+};
-+
-+module_platform_driver(qcom_qmp_phy_driver);
-+
-+MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
-+MODULE_DESCRIPTION("Qualcomm QMP PHY driver");
-+MODULE_LICENSE("GPL v2");
-diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
-new file mode 100644
-index 000000000000..c7309e981bfb
---- /dev/null
-+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
-@@ -0,0 +1,6350 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/clk-provider.h>
-+#include <linux/delay.h>
-+#include <linux/err.h>
-+#include <linux/io.h>
-+#include <linux/iopoll.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/of_device.h>
-+#include <linux/of_address.h>
-+#include <linux/phy/phy.h>
-+#include <linux/platform_device.h>
-+#include <linux/regulator/consumer.h>
-+#include <linux/reset.h>
-+#include <linux/slab.h>
-+
-+#include <dt-bindings/phy/phy.h>
-+
-+#include "phy-qcom-qmp.h"
-+
-+/* QPHY_SW_RESET bit */
-+#define SW_RESET BIT(0)
-+/* QPHY_POWER_DOWN_CONTROL */
-+#define SW_PWRDN BIT(0)
-+#define REFCLK_DRV_DSBL BIT(1)
-+/* QPHY_START_CONTROL bits */
-+#define SERDES_START BIT(0)
-+#define PCS_START BIT(1)
-+#define PLL_READY_GATE_EN BIT(3)
-+/* QPHY_PCS_STATUS bit */
-+#define PHYSTATUS BIT(6)
-+#define PHYSTATUS_4_20 BIT(7)
-+/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */
-+#define PCS_READY BIT(0)
-+
-+/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
-+/* DP PHY soft reset */
-+#define SW_DPPHY_RESET BIT(0)
-+/* mux to select DP PHY reset control, 0:HW control, 1: software reset */
-+#define SW_DPPHY_RESET_MUX BIT(1)
-+/* USB3 PHY soft reset */
-+#define SW_USB3PHY_RESET BIT(2)
-+/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
-+#define SW_USB3PHY_RESET_MUX BIT(3)
-+
-+/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
-+#define USB3_MODE BIT(0) /* enables USB3 mode */
-+#define DP_MODE BIT(1) /* enables DP mode */
-+
-+/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
-+#define ARCVR_DTCT_EN BIT(0)
-+#define ALFPS_DTCT_EN BIT(1)
-+#define ARCVR_DTCT_EVENT_SEL BIT(4)
-+
-+/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
-+#define IRQ_CLEAR BIT(0)
-+
-+/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
-+#define RCVR_DETECT BIT(0)
-+
-+/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
-+#define CLAMP_EN BIT(0) /* enables i/o clamp_n */
-+
-+#define PHY_INIT_COMPLETE_TIMEOUT 10000
-+#define POWER_DOWN_DELAY_US_MIN 10
-+#define POWER_DOWN_DELAY_US_MAX 11
-+
-+#define MAX_PROP_NAME 32
-+
-+/* Define the assumed distance between lanes for underspecified device trees. */
-+#define QMP_PHY_LEGACY_LANE_STRIDE 0x400
-+
-+struct qmp_phy_init_tbl {
-+ unsigned int offset;
-+ unsigned int val;
-+ /*
-+ * register part of layout ?
-+ * if yes, then offset gives index in the reg-layout
-+ */
-+ bool in_layout;
-+ /*
-+ * mask of lanes for which this register is written
-+ * for cases when second lane needs different values
-+ */
-+ u8 lane_mask;
-+};
-+
-+#define QMP_PHY_INIT_CFG(o, v) \
-+ { \
-+ .offset = o, \
-+ .val = v, \
-+ .lane_mask = 0xff, \
-+ }
-+
-+#define QMP_PHY_INIT_CFG_L(o, v) \
-+ { \
-+ .offset = o, \
-+ .val = v, \
-+ .in_layout = true, \
-+ .lane_mask = 0xff, \
-+ }
-+
-+#define QMP_PHY_INIT_CFG_LANE(o, v, l) \
-+ { \
-+ .offset = o, \
-+ .val = v, \
-+ .lane_mask = l, \
-+ }
-+
-+/* set of registers with offsets different per-PHY */
-+enum qphy_reg_layout {
-+ /* Common block control registers */
-+ QPHY_COM_SW_RESET,
-+ QPHY_COM_POWER_DOWN_CONTROL,
-+ QPHY_COM_START_CONTROL,
-+ QPHY_COM_PCS_READY_STATUS,
-+ /* PCS registers */
-+ QPHY_PLL_LOCK_CHK_DLY_TIME,
-+ QPHY_FLL_CNTRL1,
-+ QPHY_FLL_CNTRL2,
-+ QPHY_FLL_CNT_VAL_L,
-+ QPHY_FLL_CNT_VAL_H_TOL,
-+ QPHY_FLL_MAN_CODE,
-+ QPHY_SW_RESET,
-+ QPHY_START_CTRL,
-+ QPHY_PCS_READY_STATUS,
-+ QPHY_PCS_STATUS,
-+ QPHY_PCS_AUTONOMOUS_MODE_CTRL,
-+ QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
-+ QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
-+ QPHY_PCS_POWER_DOWN_CONTROL,
-+ /* PCS_MISC registers */
-+ QPHY_PCS_MISC_TYPEC_CTRL,
-+ /* Keep last to ensure regs_layout arrays are properly initialized */
-+ QPHY_LAYOUT_SIZE
-+};
-+
-+static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_START_CTRL] = 0x00,
-+ [QPHY_PCS_READY_STATUS] = 0x168,
-+};
-+
-+static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x44,
-+ [QPHY_PCS_STATUS] = 0x14,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
-+};
-+
-+static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_COM_SW_RESET] = 0x400,
-+ [QPHY_COM_POWER_DOWN_CONTROL] = 0x404,
-+ [QPHY_COM_START_CONTROL] = 0x408,
-+ [QPHY_COM_PCS_READY_STATUS] = 0x448,
-+ [QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8,
-+ [QPHY_FLL_CNTRL1] = 0xc4,
-+ [QPHY_FLL_CNTRL2] = 0xc8,
-+ [QPHY_FLL_CNT_VAL_L] = 0xcc,
-+ [QPHY_FLL_CNT_VAL_H_TOL] = 0xd0,
-+ [QPHY_FLL_MAN_CODE] = 0xd4,
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_STATUS] = 0x174,
-+};
-+
-+static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_FLL_CNTRL1] = 0xc0,
-+ [QPHY_FLL_CNTRL2] = 0xc4,
-+ [QPHY_FLL_CNT_VAL_L] = 0xc8,
-+ [QPHY_FLL_CNT_VAL_H_TOL] = 0xcc,
-+ [QPHY_FLL_MAN_CODE] = 0xd0,
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_STATUS] = 0x17c,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
-+};
-+
-+static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_STATUS] = 0x174,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
-+};
-+
-+static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_STATUS] = 0x174,
-+};
-+
-+static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_STATUS] = 0x2ac,
-+};
-+
-+static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x44,
-+ [QPHY_PCS_STATUS] = 0x14,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314,
-+};
-+
-+static const unsigned int qmp_v4_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x44,
-+ [QPHY_PCS_STATUS] = 0x14,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x608,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x614,
-+};
-+
-+static const unsigned int sm8350_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x44,
-+ [QPHY_PCS_STATUS] = 0x14,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x1008,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x1014,
-+};
-+
-+static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0xd8,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc,
-+ [QPHY_PCS_STATUS] = 0x174,
-+ [QPHY_PCS_MISC_TYPEC_CTRL] = 0x00,
-+};
-+
-+static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_START_CTRL] = 0x00,
-+ [QPHY_PCS_READY_STATUS] = 0x160,
-+};
-+
-+static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_START_CTRL] = 0x00,
-+ [QPHY_PCS_READY_STATUS] = 0x168,
-+};
-+
-+static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x44,
-+ [QPHY_PCS_STATUS] = 0x14,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
-+};
-+
-+static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START,
-+ [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS,
-+ [QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET,
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
-+ /* PLL and Loop filter settings */
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-+ /* SSC settings */
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
-+ QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
-+
-+ QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
-+
-+ QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
-+ QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
-+ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
-+ /* PLL and Loop filter settings */
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-+ /* SSC settings */
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
-+ /* FLL settings */
-+ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03),
-+ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02),
-+ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42),
-+ QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
-+
-+ /* Lock Det settings */
-+ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x61),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d),
-+ QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10),
-+ QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_PRE, 0x00),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_POST, 0x58),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
-+ QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
-+ QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
-+ QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
-+ QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
-+ QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
-+ QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
-+ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
-+ QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
-+ QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = {
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
-+ /* FLL settings */
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+
-+ /* Lock Det settings */
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
-+ /* FLL settings */
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+
-+ /* Lock Det settings */
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
-+};
-+
-+static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
-+
-+ /* Rate B */
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),
-+};
-+
-+static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B),
-+};
-+
-+static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_RX_PWM_GEAR_BAND, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_CTRL2, 0x6d),
-+ QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_DRV_LVL, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_DRV_LVL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
-+ QMP_PHY_INIT_CFG(QPHY_RX_SYM_RESYNC_CTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
-+ QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
-+
-+ /* Rate B */
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
-+
-+ /* Rate B */
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
-+
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
-+ /* Lock Det settings */
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20),
-+};
-+
-+static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
-+};
-+
-+static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5),
-+};
-+
-+static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
-+};
-+
-+static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),
-+};
-+
-+static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
-+
-+ /* Rate B */
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+};
-+
-+static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01),
-+};
-+
-+static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
-+
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05),
-+
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
-+
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
-+
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
-+};
-+
-+/* Register names should be validated, they might be different for this PHY */
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
-+};
-+
-+struct qmp_phy;
-+
-+/* struct qmp_phy_cfg - per-PHY initialization config */
-+struct qmp_phy_cfg {
-+ /* phy-type - PCIE/UFS/USB */
-+ unsigned int type;
-+ /* number of lanes provided by phy */
-+ int nlanes;
-+
-+ /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
-+ const struct qmp_phy_init_tbl *serdes_tbl;
-+ int serdes_tbl_num;
-+ const struct qmp_phy_init_tbl *serdes_tbl_sec;
-+ int serdes_tbl_num_sec;
-+ const struct qmp_phy_init_tbl *tx_tbl;
-+ int tx_tbl_num;
-+ const struct qmp_phy_init_tbl *tx_tbl_sec;
-+ int tx_tbl_num_sec;
-+ const struct qmp_phy_init_tbl *rx_tbl;
-+ int rx_tbl_num;
-+ const struct qmp_phy_init_tbl *rx_tbl_sec;
-+ int rx_tbl_num_sec;
-+ const struct qmp_phy_init_tbl *pcs_tbl;
-+ int pcs_tbl_num;
-+ const struct qmp_phy_init_tbl *pcs_tbl_sec;
-+ int pcs_tbl_num_sec;
-+ const struct qmp_phy_init_tbl *pcs_misc_tbl;
-+ int pcs_misc_tbl_num;
-+ const struct qmp_phy_init_tbl *pcs_misc_tbl_sec;
-+ int pcs_misc_tbl_num_sec;
-+
-+ /* Init sequence for DP PHY block link rates */
-+ const struct qmp_phy_init_tbl *serdes_tbl_rbr;
-+ int serdes_tbl_rbr_num;
-+ const struct qmp_phy_init_tbl *serdes_tbl_hbr;
-+ int serdes_tbl_hbr_num;
-+ const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
-+ int serdes_tbl_hbr2_num;
-+ const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
-+ int serdes_tbl_hbr3_num;
-+
-+ /* DP PHY callbacks */
-+ int (*configure_dp_phy)(struct qmp_phy *qphy);
-+ void (*configure_dp_tx)(struct qmp_phy *qphy);
-+ int (*calibrate_dp_phy)(struct qmp_phy *qphy);
-+ void (*dp_aux_init)(struct qmp_phy *qphy);
-+
-+ /* clock ids to be requested */
-+ const char * const *clk_list;
-+ int num_clks;
-+ /* resets to be requested */
-+ const char * const *reset_list;
-+ int num_resets;
-+ /* regulators to be requested */
-+ const char * const *vreg_list;
-+ int num_vregs;
-+
-+ /* array of registers with different offsets */
-+ const unsigned int *regs;
-+
-+ unsigned int start_ctrl;
-+ unsigned int pwrdn_ctrl;
-+ unsigned int mask_com_pcs_ready;
-+ /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
-+ unsigned int phy_status;
-+
-+ /* true, if PHY has a separate PHY_COM control block */
-+ bool has_phy_com_ctrl;
-+ /* true, if PHY has a reset for individual lanes */
-+ bool has_lane_rst;
-+ /* true, if PHY needs delay after POWER_DOWN */
-+ bool has_pwrdn_delay;
-+ /* power_down delay in usec */
-+ int pwrdn_delay_min;
-+ int pwrdn_delay_max;
-+
-+ /* true, if PHY has a separate DP_COM control block */
-+ bool has_phy_dp_com_ctrl;
-+ /* true, if PHY has secondary tx/rx lanes to be configured */
-+ bool is_dual_lane_phy;
-+
-+ /* true, if PCS block has no separate SW_RESET register */
-+ bool no_pcs_sw_reset;
-+};
-+
-+struct qmp_phy_combo_cfg {
-+ const struct qmp_phy_cfg *usb_cfg;
-+ const struct qmp_phy_cfg *dp_cfg;
-+};
-+
-+/**
-+ * struct qmp_phy - per-lane phy descriptor
-+ *
-+ * @phy: generic phy
-+ * @cfg: phy specific configuration
-+ * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
-+ * @tx: iomapped memory space for lane's tx
-+ * @rx: iomapped memory space for lane's rx
-+ * @pcs: iomapped memory space for lane's pcs
-+ * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
-+ * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
-+ * @pcs_misc: iomapped memory space for lane's pcs_misc
-+ * @pipe_clk: pipe clock
-+ * @index: lane index
-+ * @qmp: QMP phy to which this lane belongs
-+ * @lane_rst: lane's reset controller
-+ * @mode: current PHY mode
-+ * @dp_aux_cfg: Display port aux config
-+ * @dp_opts: Display port optional config
-+ * @dp_clks: Display port clocks
-+ */
-+struct qmp_phy {
-+ struct phy *phy;
-+ const struct qmp_phy_cfg *cfg;
-+ void __iomem *serdes;
-+ void __iomem *tx;
-+ void __iomem *rx;
-+ void __iomem *pcs;
-+ void __iomem *tx2;
-+ void __iomem *rx2;
-+ void __iomem *pcs_misc;
-+ struct clk *pipe_clk;
-+ unsigned int index;
-+ struct qcom_qmp *qmp;
-+ struct reset_control *lane_rst;
-+ enum phy_mode mode;
-+ unsigned int dp_aux_cfg;
-+ struct phy_configure_opts_dp dp_opts;
-+ struct qmp_phy_dp_clks *dp_clks;
-+};
-+
-+struct qmp_phy_dp_clks {
-+ struct qmp_phy *qphy;
-+ struct clk_hw dp_link_hw;
-+ struct clk_hw dp_pixel_hw;
-+};
-+
-+/**
-+ * struct qcom_qmp - structure holding QMP phy block attributes
-+ *
-+ * @dev: device
-+ * @dp_com: iomapped memory space for phy's dp_com control block
-+ *
-+ * @clks: array of clocks required by phy
-+ * @resets: array of resets required by phy
-+ * @vregs: regulator supplies bulk data
-+ *
-+ * @phys: array of per-lane phy descriptors
-+ * @phy_mutex: mutex lock for PHY common block initialization
-+ * @init_count: phy common block initialization count
-+ * @ufs_reset: optional UFS PHY reset handle
-+ */
-+struct qcom_qmp {
-+ struct device *dev;
-+ void __iomem *dp_com;
-+
-+ struct clk_bulk_data *clks;
-+ struct reset_control **resets;
-+ struct regulator_bulk_data *vregs;
-+
-+ struct qmp_phy **phys;
-+
-+ struct mutex phy_mutex;
-+ int init_count;
-+
-+ struct reset_control *ufs_reset;
-+};
-+
-+static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy);
-+static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy);
-+static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy);
-+static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy);
-+
-+static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy);
-+static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy);
-+static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy);
-+static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy);
-+
-+static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
-+{
-+ u32 reg;
-+
-+ reg = readl(base + offset);
-+ reg |= val;
-+ writel(reg, base + offset);
-+
-+ /* ensure that above write is through */
-+ readl(base + offset);
-+}
-+
-+static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
-+{
-+ u32 reg;
-+
-+ reg = readl(base + offset);
-+ reg &= ~val;
-+ writel(reg, base + offset);
-+
-+ /* ensure that above write is through */
-+ readl(base + offset);
-+}
-+
-+/* list of clocks required by phy */
-+static const char * const msm8996_phy_clk_l[] = {
-+ "aux", "cfg_ahb", "ref",
-+};
-+
-+static const char * const msm8996_ufs_phy_clk_l[] = {
-+ "ref",
-+};
-+
-+static const char * const qmp_v3_phy_clk_l[] = {
-+ "aux", "cfg_ahb", "ref", "com_aux",
-+};
-+
-+static const char * const sdm845_pciephy_clk_l[] = {
-+ "aux", "cfg_ahb", "ref", "refgen",
-+};
-+
-+static const char * const qmp_v4_phy_clk_l[] = {
-+ "aux", "ref_clk_src", "ref", "com_aux",
-+};
-+
-+/* the primary usb3 phy on sm8250 doesn't have a ref clock */
-+static const char * const qmp_v4_sm8250_usbphy_clk_l[] = {
-+ "aux", "ref_clk_src", "com_aux"
-+};
-+
-+static const char * const sm8450_ufs_phy_clk_l[] = {
-+ "qref", "ref", "ref_aux",
-+};
-+
-+static const char * const sdm845_ufs_phy_clk_l[] = {
-+ "ref", "ref_aux",
-+};
-+
-+/* usb3 phy on sdx55 doesn't have com_aux clock */
-+static const char * const qmp_v4_sdx55_usbphy_clk_l[] = {
-+ "aux", "cfg_ahb", "ref"
-+};
-+
-+static const char * const qcm2290_usb3phy_clk_l[] = {
-+ "cfg_ahb", "ref", "com_aux",
-+};
-+
-+/* list of resets */
-+static const char * const msm8996_pciephy_reset_l[] = {
-+ "phy", "common", "cfg",
-+};
-+
-+static const char * const msm8996_usb3phy_reset_l[] = {
-+ "phy", "common",
-+};
-+
-+static const char * const sc7180_usb3phy_reset_l[] = {
-+ "phy",
-+};
-+
-+static const char * const qcm2290_usb3phy_reset_l[] = {
-+ "phy_phy", "phy",
-+};
-+
-+static const char * const sdm845_pciephy_reset_l[] = {
-+ "phy",
-+};
-+
-+/* list of regulators */
-+static const char * const qmp_phy_vreg_l[] = {
-+ "vdda-phy", "vdda-pll",
-+};
-+
-+static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = ipq8074_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
-+ .tx_tbl = msm8996_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
-+ .rx_tbl = ipq8074_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
-+ .pcs_tbl = ipq8074_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
-+ .clk_list = msm8996_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+};
-+
-+static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 3,
-+
-+ .serdes_tbl = msm8996_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
-+ .tx_tbl = msm8996_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8996_pcie_tx_tbl),
-+ .rx_tbl = msm8996_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(msm8996_pcie_rx_tbl),
-+ .pcs_tbl = msm8996_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
-+ .clk_list = msm8996_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-+ .reset_list = msm8996_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = pciephy_regs_layout,
-+
-+ .start_ctrl = PCS_START | PLL_READY_GATE_EN,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .mask_com_pcs_ready = PCS_READY,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_phy_com_ctrl = true,
-+ .has_lane_rst = true,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg msm8996_ufs_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = msm8996_ufs_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(msm8996_ufs_serdes_tbl),
-+ .tx_tbl = msm8996_ufs_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8996_ufs_tx_tbl),
-+ .rx_tbl = msm8996_ufs_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(msm8996_ufs_rx_tbl),
-+
-+ .clk_list = msm8996_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
-+
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+
-+ .regs = msm8996_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .no_pcs_sw_reset = true,
-+};
-+
-+static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = msm8996_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
-+ .tx_tbl = msm8996_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
-+ .rx_tbl = msm8996_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl),
-+ .pcs_tbl = msm8996_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
-+ .clk_list = msm8996_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+};
-+
-+static const char * const ipq8074_pciephy_clk_l[] = {
-+ "aux", "cfg_ahb",
-+};
-+/* list of resets */
-+static const char * const ipq8074_pciephy_reset_l[] = {
-+ "phy", "common",
-+};
-+
-+static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = ipq8074_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
-+ .tx_tbl = ipq8074_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
-+ .rx_tbl = ipq8074_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
-+ .pcs_tbl = ipq8074_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
-+ .clk_list = ipq8074_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
-+ .reset_list = ipq8074_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
-+ .vreg_list = NULL,
-+ .num_vregs = 0,
-+ .regs = pciephy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_phy_com_ctrl = false,
-+ .has_lane_rst = false,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = ipq6018_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl),
-+ .tx_tbl = ipq6018_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl),
-+ .rx_tbl = ipq6018_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
-+ .pcs_tbl = ipq6018_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
-+ .clk_list = ipq8074_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
-+ .reset_list = ipq8074_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
-+ .vreg_list = NULL,
-+ .num_vregs = 0,
-+ .regs = ipq_pciephy_gen3_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+
-+ .has_phy_com_ctrl = false,
-+ .has_lane_rst = false,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sdm845_qmp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
-+ .tx_tbl = sdm845_qmp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),
-+ .rx_tbl = sdm845_qmp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),
-+ .pcs_tbl = sdm845_qmp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sdm845_qmp_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sdm845_qmp_pciephy_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sdm845_qhp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
-+ .tx_tbl = sdm845_qhp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
-+ .rx_tbl = sdm845_qhp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl),
-+ .pcs_tbl = sdm845_qhp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sdm845_qhp_pciephy_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
-+ .serdes_tbl_sec = sm8250_qmp_gen3x1_pcie_serdes_tbl,
-+ .serdes_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
-+ .tx_tbl = sm8250_qmp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
-+ .rx_tbl = sm8250_qmp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
-+ .rx_tbl_sec = sm8250_qmp_gen3x1_pcie_rx_tbl,
-+ .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),
-+ .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
-+ .pcs_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_tbl,
-+ .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
-+ .pcs_misc_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
-+ .tx_tbl = sm8250_qmp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
-+ .tx_tbl_sec = sm8250_qmp_gen3x2_pcie_tx_tbl,
-+ .tx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),
-+ .rx_tbl = sm8250_qmp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
-+ .rx_tbl_sec = sm8250_qmp_gen3x2_pcie_rx_tbl,
-+ .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl),
-+ .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
-+ .pcs_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_tbl,
-+ .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
-+ .pcs_misc_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v3_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
-+ .tx_tbl = qmp_v3_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
-+ .rx_tbl = qmp_v3_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
-+ .pcs_tbl = qmp_v3_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
-+ .clk_list = qmp_v3_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v3_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
-+ .tx_tbl = qmp_v3_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
-+ .rx_tbl = qmp_v3_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
-+ .pcs_tbl = qmp_v3_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
-+ .clk_list = qmp_v3_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-+ .reset_list = sc7180_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sc7180_dpphy_cfg = {
-+ .type = PHY_TYPE_DP,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v3_dp_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
-+ .tx_tbl = qmp_v3_dp_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
-+
-+ .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr,
-+ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
-+ .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr,
-+ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
-+ .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2,
-+ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
-+ .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3,
-+ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
-+
-+ .clk_list = qmp_v3_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-+ .reset_list = sc7180_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+
-+ .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init,
-+ .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx,
-+ .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy,
-+ .calibrate_dp_phy = qcom_qmp_v3_dp_phy_calibrate,
-+};
-+
-+static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = {
-+ .usb_cfg = &sc7180_usb3phy_cfg,
-+ .dp_cfg = &sc7180_dpphy_cfg,
-+};
-+
-+static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
-+ .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v3_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sdm845_ufsphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
-+ .tx_tbl = sdm845_ufsphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
-+ .rx_tbl = sdm845_ufsphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
-+ .pcs_tbl = sdm845_ufsphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
-+ .clk_list = sdm845_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sdm845_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+ .no_pcs_sw_reset = true,
-+};
-+
-+static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm6115_ufsphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl),
-+ .tx_tbl = sm6115_ufsphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_tx_tbl),
-+ .rx_tbl = sm6115_ufsphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_rx_tbl),
-+ .pcs_tbl = sm6115_ufsphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl),
-+ .clk_list = sdm845_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm6115_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+
-+ .is_dual_lane_phy = false,
-+ .no_pcs_sw_reset = true,
-+};
-+
-+static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = msm8998_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
-+ .tx_tbl = msm8998_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8998_pcie_tx_tbl),
-+ .rx_tbl = msm8998_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(msm8998_pcie_rx_tbl),
-+ .pcs_tbl = msm8998_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
-+ .clk_list = msm8996_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-+ .reset_list = ipq8074_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = pciephy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+};
-+
-+static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = msm8998_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
-+ .tx_tbl = msm8998_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl),
-+ .rx_tbl = msm8998_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl),
-+ .pcs_tbl = msm8998_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
-+ .clk_list = msm8996_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sm8150_ufsphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl),
-+ .tx_tbl = sm8150_ufsphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx_tbl),
-+ .rx_tbl = sm8150_ufsphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx_tbl),
-+ .pcs_tbl = sm8150_ufsphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl),
-+ .clk_list = sdm845_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8150_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
-+ .tx_tbl = sm8150_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl),
-+ .rx_tbl = sm8150_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl),
-+ .pcs_tbl = sm8150_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
-+ .clk_list = qmp_v4_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sc8180x_qmp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl),
-+ .tx_tbl = sc8180x_qmp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl),
-+ .rx_tbl = sc8180x_qmp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl),
-+ .pcs_tbl = sc8180x_qmp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sc8180x_qmp_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sc8180x_dpphy_cfg = {
-+ .type = PHY_TYPE_DP,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v4_dp_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
-+ .tx_tbl = qmp_v4_dp_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
-+
-+ .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
-+ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
-+ .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
-+ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
-+ .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
-+ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
-+ .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
-+ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
-+
-+ .clk_list = qmp_v3_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-+ .reset_list = sc7180_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+
-+ .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
-+ .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
-+ .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
-+ .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
-+};
-+
-+static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = {
-+ .usb_cfg = &sm8150_usb3phy_cfg,
-+ .dp_cfg = &sc8180x_dpphy_cfg,
-+};
-+
-+static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = sm8150_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),
-+ .rx_tbl = sm8150_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = sm8150_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v4_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3_uniphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
-+ .tx_tbl = sm8250_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl),
-+ .rx_tbl = sm8250_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl),
-+ .pcs_tbl = sm8250_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
-+ .clk_list = qmp_v4_sm8250_usbphy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = sm8250_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),
-+ .rx_tbl = sm8250_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v4_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3_uniphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sm8250_dpphy_cfg = {
-+ .type = PHY_TYPE_DP,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v4_dp_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
-+ .tx_tbl = qmp_v4_dp_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
-+
-+ .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
-+ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
-+ .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
-+ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
-+ .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
-+ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
-+ .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
-+ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
-+
-+ .clk_list = qmp_v4_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3phy_regs_layout,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+
-+ .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
-+ .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
-+ .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
-+ .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
-+};
-+
-+static const struct qmp_phy_combo_cfg sm8250_usb3dpphy_cfg = {
-+ .usb_cfg = &sm8250_usb3phy_cfg,
-+ .dp_cfg = &sm8250_dpphy_cfg,
-+};
-+
-+static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = sdx55_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl),
-+ .rx_tbl = sdx55_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v4_sdx55_usbphy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3_uniphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sdx55_qmp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl),
-+ .tx_tbl = sdx55_qmp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl),
-+ .rx_tbl = sdx55_qmp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl),
-+ .pcs_tbl = sdx55_qmp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sdx55_qmp_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS_4_20,
-+
-+ .is_dual_lane_phy = true,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = sdx65_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl),
-+ .rx_tbl = sdx65_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v4_sdx55_usbphy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8350_usb3_uniphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sm8350_ufsphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
-+ .tx_tbl = sm8350_ufsphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
-+ .rx_tbl = sm8350_ufsphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
-+ .pcs_tbl = sm8350_ufsphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
-+ .clk_list = sdm845_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8150_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
-+ .tx_tbl = sm8350_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl),
-+ .rx_tbl = sm8350_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl),
-+ .pcs_tbl = sm8350_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl),
-+ .clk_list = qmp_v4_sm8250_usbphy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = sm8350_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),
-+ .rx_tbl = sm8350_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v4_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8350_usb3_uniphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sm8350_ufsphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
-+ .tx_tbl = sm8350_ufsphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
-+ .rx_tbl = sm8350_ufsphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
-+ .pcs_tbl = sm8350_ufsphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
-+ .clk_list = sm8450_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8150_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8450_qmp_gen3x1_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl),
-+ .tx_tbl = sm8450_qmp_gen3x1_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl),
-+ .rx_tbl = sm8450_qmp_gen3x1_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl),
-+ .pcs_tbl = sm8450_qmp_gen3x1_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sm8450_qmp_gen4x2_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl),
-+ .tx_tbl = sm8450_qmp_gen4x2_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl),
-+ .rx_tbl = sm8450_qmp_gen4x2_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl),
-+ .pcs_tbl = sm8450_qmp_gen4x2_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS_4_20,
-+
-+ .is_dual_lane_phy = true,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qcm2290_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl),
-+ .tx_tbl = qcm2290_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl),
-+ .rx_tbl = qcm2290_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(qcm2290_usb3_rx_tbl),
-+ .pcs_tbl = qcm2290_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl),
-+ .clk_list = qcm2290_usb3phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qcm2290_usb3phy_clk_l),
-+ .reset_list = qcm2290_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qcm2290_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+};
-+
-+static void qcom_qmp_phy_configure_lane(void __iomem *base,
-+ const unsigned int *regs,
-+ const struct qmp_phy_init_tbl tbl[],
-+ int num,
-+ u8 lane_mask)
-+{
-+ int i;
-+ const struct qmp_phy_init_tbl *t = tbl;
-+
-+ if (!t)
-+ return;
-+
-+ for (i = 0; i < num; i++, t++) {
-+ if (!(t->lane_mask & lane_mask))
-+ continue;
-+
-+ if (t->in_layout)
-+ writel(t->val, base + regs[t->offset]);
-+ else
-+ writel(t->val, base + t->offset);
-+ }
-+}
-+
-+static void qcom_qmp_phy_configure(void __iomem *base,
-+ const unsigned int *regs,
-+ const struct qmp_phy_init_tbl tbl[],
-+ int num)
-+{
-+ qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff);
-+}
-+
-+static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
-+{
-+ struct qcom_qmp *qmp = qphy->qmp;
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *serdes = qphy->serdes;
-+ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-+ const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
-+ int serdes_tbl_num = cfg->serdes_tbl_num;
-+ int ret;
-+
-+ qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
-+ if (cfg->serdes_tbl_sec)
-+ qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
-+ cfg->serdes_tbl_num_sec);
-+
-+ if (cfg->type == PHY_TYPE_DP) {
-+ switch (dp_opts->link_rate) {
-+ case 1620:
-+ qcom_qmp_phy_configure(serdes, cfg->regs,
-+ cfg->serdes_tbl_rbr,
-+ cfg->serdes_tbl_rbr_num);
-+ break;
-+ case 2700:
-+ qcom_qmp_phy_configure(serdes, cfg->regs,
-+ cfg->serdes_tbl_hbr,
-+ cfg->serdes_tbl_hbr_num);
-+ break;
-+ case 5400:
-+ qcom_qmp_phy_configure(serdes, cfg->regs,
-+ cfg->serdes_tbl_hbr2,
-+ cfg->serdes_tbl_hbr2_num);
-+ break;
-+ case 8100:
-+ qcom_qmp_phy_configure(serdes, cfg->regs,
-+ cfg->serdes_tbl_hbr3,
-+ cfg->serdes_tbl_hbr3_num);
-+ break;
-+ default:
-+ /* Other link rates aren't supported */
-+ return -EINVAL;
-+ }
-+ }
-+
-+
-+ if (cfg->has_phy_com_ctrl) {
-+ void __iomem *status;
-+ unsigned int mask, val;
-+
-+ qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
-+ qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
-+ SERDES_START | PCS_START);
-+
-+ status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
-+ mask = cfg->mask_com_pcs_ready;
-+
-+ ret = readl_poll_timeout(status, val, (val & mask), 10,
-+ PHY_INIT_COMPLETE_TIMEOUT);
-+ if (ret) {
-+ dev_err(qmp->dev,
-+ "phy common block init timed-out\n");
-+ return ret;
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy)
-+{
-+ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
-+ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
-+ qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+
-+ /* Turn on BIAS current for PHY/PLL */
-+ writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
-+ QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
-+ qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
-+
-+ writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+
-+ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
-+ DP_PHY_PD_CTL_LANE_0_1_PWRDN |
-+ DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
-+ DP_PHY_PD_CTL_DP_CLAMP_EN,
-+ qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+
-+ writel(QSERDES_V3_COM_BIAS_EN |
-+ QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
-+ QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL |
-+ QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
-+ qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
-+
-+ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
-+ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-+ writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
-+ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
-+ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
-+ writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
-+ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
-+ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
-+ writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
-+ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
-+ qphy->dp_aux_cfg = 0;
-+
-+ writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
-+ PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
-+ PHY_AUX_REQ_ERR_MASK,
-+ qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
-+}
-+
-+static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = {
-+ { 0x00, 0x0c, 0x15, 0x1a },
-+ { 0x02, 0x0e, 0x16, 0xff },
-+ { 0x02, 0x11, 0xff, 0xff },
-+ { 0x04, 0xff, 0xff, 0xff }
-+};
-+
-+static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = {
-+ { 0x02, 0x12, 0x16, 0x1a },
-+ { 0x09, 0x19, 0x1f, 0xff },
-+ { 0x10, 0x1f, 0xff, 0xff },
-+ { 0x1f, 0xff, 0xff, 0xff }
-+};
-+
-+static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = {
-+ { 0x00, 0x0c, 0x14, 0x19 },
-+ { 0x00, 0x0b, 0x12, 0xff },
-+ { 0x00, 0x0b, 0xff, 0xff },
-+ { 0x04, 0xff, 0xff, 0xff }
-+};
-+
-+static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = {
-+ { 0x08, 0x0f, 0x16, 0x1f },
-+ { 0x11, 0x1e, 0x1f, 0xff },
-+ { 0x19, 0x1f, 0xff, 0xff },
-+ { 0x1f, 0xff, 0xff, 0xff }
-+};
-+
-+static int qcom_qmp_phy_configure_dp_swing(struct qmp_phy *qphy,
-+ unsigned int drv_lvl_reg, unsigned int emp_post_reg)
-+{
-+ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-+ unsigned int v_level = 0, p_level = 0;
-+ u8 voltage_swing_cfg, pre_emphasis_cfg;
-+ int i;
-+
-+ for (i = 0; i < dp_opts->lanes; i++) {
-+ v_level = max(v_level, dp_opts->voltage[i]);
-+ p_level = max(p_level, dp_opts->pre[i]);
-+ }
-+
-+ if (dp_opts->link_rate <= 2700) {
-+ voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level];
-+ pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level];
-+ } else {
-+ voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr3_hbr2[v_level][p_level];
-+ pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr3_hbr2[v_level][p_level];
-+ }
-+
-+ /* TODO: Move check to config check */
-+ if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF)
-+ return -EINVAL;
-+
-+ /* Enable MUX to use Cursor values from these registers */
-+ voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
-+ pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
-+
-+ writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg);
-+ writel(pre_emphasis_cfg, qphy->tx + emp_post_reg);
-+ writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg);
-+ writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg);
-+
-+ return 0;
-+}
-+
-+static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy)
-+{
-+ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-+ u32 bias_en, drvr_en;
-+
-+ if (qcom_qmp_phy_configure_dp_swing(qphy,
-+ QSERDES_V3_TX_TX_DRV_LVL,
-+ QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0)
-+ return;
-+
-+ if (dp_opts->lanes == 1) {
-+ bias_en = 0x3e;
-+ drvr_en = 0x13;
-+ } else {
-+ bias_en = 0x3f;
-+ drvr_en = 0x10;
-+ }
-+
-+ writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN);
-+ writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
-+ writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN);
-+ writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
-+}
-+
-+static bool qcom_qmp_phy_configure_dp_mode(struct qmp_phy *qphy)
-+{
-+ u32 val;
-+ bool reverse = false;
-+
-+ val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
-+ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN;
-+
-+ /*
-+ * TODO: Assume orientation is CC1 for now and two lanes, need to
-+ * use type-c connector to understand orientation and lanes.
-+ *
-+ * Otherwise val changes to be like below if this code understood
-+ * the orientation of the type-c cable.
-+ *
-+ * if (lane_cnt == 4 || orientation == ORIENTATION_CC2)
-+ * val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN;
-+ * if (lane_cnt == 4 || orientation == ORIENTATION_CC1)
-+ * val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
-+ * if (orientation == ORIENTATION_CC2)
-+ * writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
-+ */
-+ val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
-+ writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+
-+ writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE);
-+
-+ return reverse;
-+}
-+
-+static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy)
-+{
-+ const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
-+ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-+ u32 phy_vco_div, status;
-+ unsigned long pixel_freq;
-+
-+ qcom_qmp_phy_configure_dp_mode(qphy);
-+
-+ writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
-+ writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
-+
-+ switch (dp_opts->link_rate) {
-+ case 1620:
-+ phy_vco_div = 0x1;
-+ pixel_freq = 1620000000UL / 2;
-+ break;
-+ case 2700:
-+ phy_vco_div = 0x1;
-+ pixel_freq = 2700000000UL / 2;
-+ break;
-+ case 5400:
-+ phy_vco_div = 0x2;
-+ pixel_freq = 5400000000UL / 4;
-+ break;
-+ case 8100:
-+ phy_vco_div = 0x0;
-+ pixel_freq = 8100000000UL / 6;
-+ break;
-+ default:
-+ /* Other link rates aren't supported */
-+ return -EINVAL;
-+ }
-+ writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV);
-+
-+ clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
-+ clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
-+
-+ writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
-+ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL);
-+
-+ if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS,
-+ status,
-+ ((status & BIT(0)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
-+ status,
-+ ((status & BIT(1)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ udelay(2000);
-+ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
-+ status,
-+ ((status & BIT(1)) > 0),
-+ 500,
-+ 10000);
-+}
-+
-+/*
-+ * We need to calibrate the aux setting here as many times
-+ * as the caller tries
-+ */
-+static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy)
-+{
-+ static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d };
-+ u8 val;
-+
-+ qphy->dp_aux_cfg++;
-+ qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
-+ val = cfg1_settings[qphy->dp_aux_cfg];
-+
-+ writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-+
-+ return 0;
-+}
-+
-+static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy)
-+{
-+ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
-+ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
-+ qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+
-+ /* Turn on BIAS current for PHY/PLL */
-+ writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN);
-+
-+ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
-+ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-+ writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
-+ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
-+ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
-+ writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
-+ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
-+ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
-+ writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
-+ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
-+ qphy->dp_aux_cfg = 0;
-+
-+ writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
-+ PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
-+ PHY_AUX_REQ_ERR_MASK,
-+ qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
-+}
-+
-+static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy)
-+{
-+ /* Program default values before writing proper values */
-+ writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
-+ writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
-+
-+ writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
-+ writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
-+
-+ qcom_qmp_phy_configure_dp_swing(qphy,
-+ QSERDES_V4_TX_TX_DRV_LVL,
-+ QSERDES_V4_TX_TX_EMP_POST1_LVL);
-+}
-+
-+static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy)
-+{
-+ const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
-+ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-+ u32 phy_vco_div, status;
-+ unsigned long pixel_freq;
-+ u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
-+ bool reverse;
-+
-+ writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1);
-+
-+ reverse = qcom_qmp_phy_configure_dp_mode(qphy);
-+
-+ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-+ writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
-+
-+ writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL);
-+ writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL);
-+
-+ switch (dp_opts->link_rate) {
-+ case 1620:
-+ phy_vco_div = 0x1;
-+ pixel_freq = 1620000000UL / 2;
-+ break;
-+ case 2700:
-+ phy_vco_div = 0x1;
-+ pixel_freq = 2700000000UL / 2;
-+ break;
-+ case 5400:
-+ phy_vco_div = 0x2;
-+ pixel_freq = 5400000000UL / 4;
-+ break;
-+ case 8100:
-+ phy_vco_div = 0x0;
-+ pixel_freq = 8100000000UL / 6;
-+ break;
-+ default:
-+ /* Other link rates aren't supported */
-+ return -EINVAL;
-+ }
-+ writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV);
-+
-+ clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
-+ clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
-+
-+ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL);
-+
-+ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS,
-+ status,
-+ ((status & BIT(0)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
-+ status,
-+ ((status & BIT(0)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
-+ status,
-+ ((status & BIT(1)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
-+ status,
-+ ((status & BIT(0)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
-+ status,
-+ ((status & BIT(1)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ /*
-+ * At least for 7nm DP PHY this has to be done after enabling link
-+ * clock.
-+ */
-+
-+ if (dp_opts->lanes == 1) {
-+ bias0_en = reverse ? 0x3e : 0x15;
-+ bias1_en = reverse ? 0x15 : 0x3e;
-+ drvr0_en = reverse ? 0x13 : 0x10;
-+ drvr1_en = reverse ? 0x10 : 0x13;
-+ } else if (dp_opts->lanes == 2) {
-+ bias0_en = reverse ? 0x3f : 0x15;
-+ bias1_en = reverse ? 0x15 : 0x3f;
-+ drvr0_en = 0x10;
-+ drvr1_en = 0x10;
-+ } else {
-+ bias0_en = 0x3f;
-+ bias1_en = 0x3f;
-+ drvr0_en = 0x10;
-+ drvr1_en = 0x10;
-+ }
-+
-+ writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN);
-+ writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
-+ writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN);
-+ writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
-+
-+ writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ udelay(2000);
-+ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
-+ status,
-+ ((status & BIT(1)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV);
-+ writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV);
-+
-+ writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
-+ writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
-+
-+ writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
-+ writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
-+
-+ return 0;
-+}
-+
-+/*
-+ * We need to calibrate the aux setting here as many times
-+ * as the caller tries
-+ */
-+static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy)
-+{
-+ static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d };
-+ u8 val;
-+
-+ qphy->dp_aux_cfg++;
-+ qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
-+ val = cfg1_settings[qphy->dp_aux_cfg];
-+
-+ writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
-+{
-+ const struct phy_configure_opts_dp *dp_opts = &opts->dp;
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+
-+ memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts));
-+ if (qphy->dp_opts.set_voltages) {
-+ cfg->configure_dp_tx(qphy);
-+ qphy->dp_opts.set_voltages = 0;
-+ }
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_dp_phy_calibrate(struct phy *phy)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+
-+ if (cfg->calibrate_dp_phy)
-+ return cfg->calibrate_dp_phy(qphy);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
-+{
-+ struct qcom_qmp *qmp = qphy->qmp;
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *serdes = qphy->serdes;
-+ void __iomem *pcs = qphy->pcs;
-+ void __iomem *dp_com = qmp->dp_com;
-+ int ret, i;
-+
-+ mutex_lock(&qmp->phy_mutex);
-+ if (qmp->init_count++) {
-+ mutex_unlock(&qmp->phy_mutex);
-+ return 0;
-+ }
-+
-+ /* turn on regulator supplies */
-+ ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
-+ if (ret) {
-+ dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
-+ goto err_unlock;
-+ }
-+
-+ for (i = 0; i < cfg->num_resets; i++) {
-+ ret = reset_control_assert(qmp->resets[i]);
-+ if (ret) {
-+ dev_err(qmp->dev, "%s reset assert failed\n",
-+ cfg->reset_list[i]);
-+ goto err_disable_regulators;
-+ }
-+ }
-+
-+ for (i = cfg->num_resets - 1; i >= 0; i--) {
-+ ret = reset_control_deassert(qmp->resets[i]);
-+ if (ret) {
-+ dev_err(qmp->dev, "%s reset deassert failed\n",
-+ qphy->cfg->reset_list[i]);
-+ goto err_assert_reset;
-+ }
-+ }
-+
-+ ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
-+ if (ret)
-+ goto err_assert_reset;
-+
-+ if (cfg->has_phy_dp_com_ctrl) {
-+ qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
-+ SW_PWRDN);
-+ /* override hardware control for reset of qmp phy */
-+ qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
-+ SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
-+ SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
-+
-+ /* Default type-c orientation, i.e CC1 */
-+ qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02);
-+
-+ qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
-+ USB3_MODE | DP_MODE);
-+
-+ /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
-+ qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
-+ SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
-+ SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
-+
-+ qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
-+ qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
-+ }
-+
-+ if (cfg->has_phy_com_ctrl) {
-+ qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
-+ SW_PWRDN);
-+ } else {
-+ if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
-+ qphy_setbits(pcs,
-+ cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
-+ cfg->pwrdn_ctrl);
-+ else
-+ qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
-+ cfg->pwrdn_ctrl);
-+ }
-+
-+ mutex_unlock(&qmp->phy_mutex);
-+
-+ return 0;
-+
-+err_assert_reset:
-+ while (++i < cfg->num_resets)
-+ reset_control_assert(qmp->resets[i]);
-+err_disable_regulators:
-+ regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
-+err_unlock:
-+ mutex_unlock(&qmp->phy_mutex);
-+
-+ return ret;
-+}
-+
-+static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy)
-+{
-+ struct qcom_qmp *qmp = qphy->qmp;
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *serdes = qphy->serdes;
-+ int i = cfg->num_resets;
-+
-+ mutex_lock(&qmp->phy_mutex);
-+ if (--qmp->init_count) {
-+ mutex_unlock(&qmp->phy_mutex);
-+ return 0;
-+ }
-+
-+ reset_control_assert(qmp->ufs_reset);
-+ if (cfg->has_phy_com_ctrl) {
-+ qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
-+ SERDES_START | PCS_START);
-+ qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
-+ SW_RESET);
-+ qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
-+ SW_PWRDN);
-+ }
-+
-+ while (--i >= 0)
-+ reset_control_assert(qmp->resets[i]);
-+
-+ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
-+
-+ regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
-+
-+ mutex_unlock(&qmp->phy_mutex);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_init(struct phy *phy)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ struct qcom_qmp *qmp = qphy->qmp;
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ int ret;
-+ dev_vdbg(qmp->dev, "Initializing QMP phy\n");
-+
-+ if (cfg->no_pcs_sw_reset) {
-+ /*
-+ * Get UFS reset, which is delayed until now to avoid a
-+ * circular dependency where UFS needs its PHY, but the PHY
-+ * needs this UFS reset.
-+ */
-+ if (!qmp->ufs_reset) {
-+ qmp->ufs_reset =
-+ devm_reset_control_get_exclusive(qmp->dev,
-+ "ufsphy");
-+
-+ if (IS_ERR(qmp->ufs_reset)) {
-+ ret = PTR_ERR(qmp->ufs_reset);
-+ dev_err(qmp->dev,
-+ "failed to get UFS reset: %d\n",
-+ ret);
-+
-+ qmp->ufs_reset = NULL;
-+ return ret;
-+ }
-+ }
-+
-+ ret = reset_control_assert(qmp->ufs_reset);
-+ if (ret)
-+ return ret;
-+ }
-+
-+ ret = qcom_qmp_phy_com_init(qphy);
-+ if (ret)
-+ return ret;
-+
-+ if (cfg->type == PHY_TYPE_DP)
-+ cfg->dp_aux_init(qphy);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_power_on(struct phy *phy)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ struct qcom_qmp *qmp = qphy->qmp;
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *tx = qphy->tx;
-+ void __iomem *rx = qphy->rx;
-+ void __iomem *pcs = qphy->pcs;
-+ void __iomem *pcs_misc = qphy->pcs_misc;
-+ void __iomem *status;
-+ unsigned int mask, val, ready;
-+ int ret;
-+
-+ qcom_qmp_phy_serdes_init(qphy);
-+
-+ if (cfg->has_lane_rst) {
-+ ret = reset_control_deassert(qphy->lane_rst);
-+ if (ret) {
-+ dev_err(qmp->dev, "lane%d reset deassert failed\n",
-+ qphy->index);
-+ return ret;
-+ }
-+ }
-+
-+ ret = clk_prepare_enable(qphy->pipe_clk);
-+ if (ret) {
-+ dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
-+ goto err_reset_lane;
-+ }
-+
-+ /* Tx, Rx, and PCS configurations */
-+ qcom_qmp_phy_configure_lane(tx, cfg->regs,
-+ cfg->tx_tbl, cfg->tx_tbl_num, 1);
-+ if (cfg->tx_tbl_sec)
-+ qcom_qmp_phy_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
-+ cfg->tx_tbl_num_sec, 1);
-+
-+ /* Configuration for other LANE for USB-DP combo PHY */
-+ if (cfg->is_dual_lane_phy) {
-+ qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
-+ cfg->tx_tbl, cfg->tx_tbl_num, 2);
-+ if (cfg->tx_tbl_sec)
-+ qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
-+ cfg->tx_tbl_sec,
-+ cfg->tx_tbl_num_sec, 2);
-+ }
-+
-+ /* Configure special DP tx tunings */
-+ if (cfg->type == PHY_TYPE_DP)
-+ cfg->configure_dp_tx(qphy);
-+
-+ qcom_qmp_phy_configure_lane(rx, cfg->regs,
-+ cfg->rx_tbl, cfg->rx_tbl_num, 1);
-+ if (cfg->rx_tbl_sec)
-+ qcom_qmp_phy_configure_lane(rx, cfg->regs,
-+ cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1);
-+
-+ if (cfg->is_dual_lane_phy) {
-+ qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
-+ cfg->rx_tbl, cfg->rx_tbl_num, 2);
-+ if (cfg->rx_tbl_sec)
-+ qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
-+ cfg->rx_tbl_sec,
-+ cfg->rx_tbl_num_sec, 2);
-+ }
-+
-+ /* Configure link rate, swing, etc. */
-+ if (cfg->type == PHY_TYPE_DP) {
-+ cfg->configure_dp_phy(qphy);
-+ } else {
-+ qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
-+ if (cfg->pcs_tbl_sec)
-+ qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
-+ cfg->pcs_tbl_num_sec);
-+ }
-+
-+ ret = reset_control_deassert(qmp->ufs_reset);
-+ if (ret)
-+ goto err_disable_pipe_clk;
-+
-+ qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
-+ cfg->pcs_misc_tbl_num);
-+ if (cfg->pcs_misc_tbl_sec)
-+ qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
-+ cfg->pcs_misc_tbl_num_sec);
-+
-+ /*
-+ * Pull out PHY from POWER DOWN state.
-+ * This is active low enable signal to power-down PHY.
-+ */
-+ if(cfg->type == PHY_TYPE_PCIE)
-+ qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
-+
-+ if (cfg->has_pwrdn_delay)
-+ usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
-+
-+ if (cfg->type != PHY_TYPE_DP) {
-+ /* Pull PHY out of reset state */
-+ if (!cfg->no_pcs_sw_reset)
-+ qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
-+ /* start SerDes and Phy-Coding-Sublayer */
-+ qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
-+
-+ if (cfg->type == PHY_TYPE_UFS) {
-+ status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
-+ mask = PCS_READY;
-+ ready = PCS_READY;
-+ } else {
-+ status = pcs + cfg->regs[QPHY_PCS_STATUS];
-+ mask = cfg->phy_status;
-+ ready = 0;
-+ }
-+
-+ ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
-+ PHY_INIT_COMPLETE_TIMEOUT);
-+ if (ret) {
-+ dev_err(qmp->dev, "phy initialization timed-out\n");
-+ goto err_disable_pipe_clk;
-+ }
-+ }
-+ return 0;
-+
-+err_disable_pipe_clk:
-+ clk_disable_unprepare(qphy->pipe_clk);
-+err_reset_lane:
-+ if (cfg->has_lane_rst)
-+ reset_control_assert(qphy->lane_rst);
-+
-+ return ret;
-+}
-+
-+static int qcom_qmp_phy_power_off(struct phy *phy)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+
-+ clk_disable_unprepare(qphy->pipe_clk);
-+
-+ if (cfg->type == PHY_TYPE_DP) {
-+ /* Assert DP PHY power down */
-+ writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+ } else {
-+ /* PHY reset */
-+ if (!cfg->no_pcs_sw_reset)
-+ qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
-+
-+ /* stop SerDes and Phy-Coding-Sublayer */
-+ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
-+
-+ /* Put PHY into POWER DOWN state: active low */
-+ if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
-+ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
-+ cfg->pwrdn_ctrl);
-+ } else {
-+ qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
-+ cfg->pwrdn_ctrl);
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_exit(struct phy *phy)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+
-+ if (cfg->has_lane_rst)
-+ reset_control_assert(qphy->lane_rst);
-+
-+ qcom_qmp_phy_com_exit(qphy);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_enable(struct phy *phy)
-+{
-+ int ret;
-+
-+ ret = qcom_qmp_phy_init(phy);
-+ if (ret)
-+ return ret;
-+
-+ ret = qcom_qmp_phy_power_on(phy);
-+ if (ret)
-+ qcom_qmp_phy_exit(phy);
-+
-+ return ret;
-+}
-+
-+static int qcom_qmp_phy_disable(struct phy *phy)
-+{
-+ int ret;
-+
-+ ret = qcom_qmp_phy_power_off(phy);
-+ if (ret)
-+ return ret;
-+ return qcom_qmp_phy_exit(phy);
-+}
-+
-+static int qcom_qmp_phy_set_mode(struct phy *phy,
-+ enum phy_mode mode, int submode)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+
-+ qphy->mode = mode;
-+
-+ return 0;
-+}
-+
-+static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
-+{
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *pcs = qphy->pcs;
-+ void __iomem *pcs_misc = qphy->pcs_misc;
-+ u32 intr_mask;
-+
-+ if (qphy->mode == PHY_MODE_USB_HOST_SS ||
-+ qphy->mode == PHY_MODE_USB_DEVICE_SS)
-+ intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
-+ else
-+ intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
-+
-+ /* Clear any pending interrupts status */
-+ qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
-+ /* Writing 1 followed by 0 clears the interrupt */
-+ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
-+
-+ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
-+ ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
-+
-+ /* Enable required PHY autonomous mode interrupts */
-+ qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
-+
-+ /* Enable i/o clamp_n for autonomous mode */
-+ if (pcs_misc)
-+ qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
-+}
-+
-+static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
-+{
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *pcs = qphy->pcs;
-+ void __iomem *pcs_misc = qphy->pcs_misc;
-+
-+ /* Disable i/o clamp_n on resume for normal mode */
-+ if (pcs_misc)
-+ qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
-+
-+ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
-+ ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
-+
-+ qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
-+ /* Writing 1 followed by 0 clears the interrupt */
-+ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
-+}
-+
-+static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ struct qmp_phy *qphy = qmp->phys[0];
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+
-+ dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode);
-+
-+ /* Supported only for USB3 PHY and luckily USB3 is the first phy */
-+ if (cfg->type != PHY_TYPE_USB3)
-+ return 0;
-+
-+ if (!qmp->init_count) {
-+ dev_vdbg(dev, "PHY not initialized, bailing out\n");
-+ return 0;
-+ }
-+
-+ qcom_qmp_phy_enable_autonomous_mode(qphy);
-+
-+ clk_disable_unprepare(qphy->pipe_clk);
-+ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
-+
-+ return 0;
-+}
-+
-+static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ struct qmp_phy *qphy = qmp->phys[0];
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ int ret = 0;
-+
-+ dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode);
-+
-+ /* Supported only for USB3 PHY and luckily USB3 is the first phy */
-+ if (cfg->type != PHY_TYPE_USB3)
-+ return 0;
-+
-+ if (!qmp->init_count) {
-+ dev_vdbg(dev, "PHY not initialized, bailing out\n");
-+ return 0;
-+ }
-+
-+ ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
-+ if (ret)
-+ return ret;
-+
-+ ret = clk_prepare_enable(qphy->pipe_clk);
-+ if (ret) {
-+ dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
-+ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
-+ return ret;
-+ }
-+
-+ qcom_qmp_phy_disable_autonomous_mode(qphy);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ int num = cfg->num_vregs;
-+ int i;
-+
-+ qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
-+ if (!qmp->vregs)
-+ return -ENOMEM;
-+
-+ for (i = 0; i < num; i++)
-+ qmp->vregs[i].supply = cfg->vreg_list[i];
-+
-+ return devm_regulator_bulk_get(dev, num, qmp->vregs);
-+}
-+
-+static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ int i;
-+
-+ qmp->resets = devm_kcalloc(dev, cfg->num_resets,
-+ sizeof(*qmp->resets), GFP_KERNEL);
-+ if (!qmp->resets)
-+ return -ENOMEM;
-+
-+ for (i = 0; i < cfg->num_resets; i++) {
-+ struct reset_control *rst;
-+ const char *name = cfg->reset_list[i];
-+
-+ rst = devm_reset_control_get_exclusive(dev, name);
-+ if (IS_ERR(rst)) {
-+ dev_err(dev, "failed to get %s reset\n", name);
-+ return PTR_ERR(rst);
-+ }
-+ qmp->resets[i] = rst;
-+ }
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ int num = cfg->num_clks;
-+ int i;
-+
-+ qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
-+ if (!qmp->clks)
-+ return -ENOMEM;
-+
-+ for (i = 0; i < num; i++)
-+ qmp->clks[i].id = cfg->clk_list[i];
-+
-+ return devm_clk_bulk_get(dev, num, qmp->clks);
-+}
-+
-+static void phy_clk_release_provider(void *res)
-+{
-+ of_clk_del_provider(res);
-+}
-+
-+/*
-+ * Register a fixed rate pipe clock.
-+ *
-+ * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
-+ * controls it. The <s>_pipe_clk coming out of the GCC is requested
-+ * by the PHY driver for its operations.
-+ * We register the <s>_pipe_clksrc here. The gcc driver takes care
-+ * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
-+ * Below picture shows this relationship.
-+ *
-+ * +---------------+
-+ * | PHY block |<<---------------------------------------+
-+ * | | |
-+ * | +-------+ | +-----+ |
-+ * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
-+ * clk | +-------+ | +-----+
-+ * +---------------+
-+ */
-+static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
-+{
-+ struct clk_fixed_rate *fixed;
-+ struct clk_init_data init = { };
-+ int ret;
-+
-+ ret = of_property_read_string(np, "clock-output-names", &init.name);
-+ if (ret) {
-+ dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
-+ return ret;
-+ }
-+
-+ fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
-+ if (!fixed)
-+ return -ENOMEM;
-+
-+ init.ops = &clk_fixed_rate_ops;
-+
-+ /* controllers using QMP phys use 125MHz pipe clock interface */
-+ fixed->fixed_rate = 125000000;
-+ fixed->hw.init = &init;
-+
-+ ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
-+ if (ret)
-+ return ret;
-+
-+ ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
-+ if (ret)
-+ return ret;
-+
-+ /*
-+ * Roll a devm action because the clock provider is the child node, but
-+ * the child node is not actually a device.
-+ */
-+ return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
-+}
-+
-+/*
-+ * Display Port PLL driver block diagram for branch clocks
-+ *
-+ * +------------------------------+
-+ * | DP_VCO_CLK |
-+ * | |
-+ * | +-------------------+ |
-+ * | | (DP PLL/VCO) | |
-+ * | +---------+---------+ |
-+ * | v |
-+ * | +----------+-----------+ |
-+ * | | hsclk_divsel_clk_src | |
-+ * | +----------+-----------+ |
-+ * +------------------------------+
-+ * |
-+ * +---------<---------v------------>----------+
-+ * | |
-+ * +--------v----------------+ |
-+ * | dp_phy_pll_link_clk | |
-+ * | link_clk | |
-+ * +--------+----------------+ |
-+ * | |
-+ * | |
-+ * v v
-+ * Input to DISPCC block |
-+ * for link clk, crypto clk |
-+ * and interface clock |
-+ * |
-+ * |
-+ * +--------<------------+-----------------+---<---+
-+ * | | |
-+ * +----v---------+ +--------v-----+ +--------v------+
-+ * | vco_divided | | vco_divided | | vco_divided |
-+ * | _clk_src | | _clk_src | | _clk_src |
-+ * | | | | | |
-+ * |divsel_six | | divsel_two | | divsel_four |
-+ * +-------+------+ +-----+--------+ +--------+------+
-+ * | | |
-+ * v---->----------v-------------<------v
-+ * |
-+ * +----------+-----------------+
-+ * | dp_phy_pll_vco_div_clk |
-+ * +---------+------------------+
-+ * |
-+ * v
-+ * Input to DISPCC block
-+ * for DP pixel clock
-+ *
-+ */
-+static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw,
-+ struct clk_rate_request *req)
-+{
-+ switch (req->rate) {
-+ case 1620000000UL / 2:
-+ case 2700000000UL / 2:
-+ /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */
-+ return 0;
-+ default:
-+ return -EINVAL;
-+ }
-+}
-+
-+static unsigned long
-+qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
-+{
-+ const struct qmp_phy_dp_clks *dp_clks;
-+ const struct qmp_phy *qphy;
-+ const struct phy_configure_opts_dp *dp_opts;
-+
-+ dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw);
-+ qphy = dp_clks->qphy;
-+ dp_opts = &qphy->dp_opts;
-+
-+ switch (dp_opts->link_rate) {
-+ case 1620:
-+ return 1620000000UL / 2;
-+ case 2700:
-+ return 2700000000UL / 2;
-+ case 5400:
-+ return 5400000000UL / 4;
-+ case 8100:
-+ return 8100000000UL / 6;
-+ default:
-+ return 0;
-+ }
-+}
-+
-+static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = {
-+ .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate,
-+ .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate,
-+};
-+
-+static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw,
-+ struct clk_rate_request *req)
-+{
-+ switch (req->rate) {
-+ case 162000000:
-+ case 270000000:
-+ case 540000000:
-+ case 810000000:
-+ return 0;
-+ default:
-+ return -EINVAL;
-+ }
-+}
-+
-+static unsigned long
-+qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
-+{
-+ const struct qmp_phy_dp_clks *dp_clks;
-+ const struct qmp_phy *qphy;
-+ const struct phy_configure_opts_dp *dp_opts;
-+
-+ dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw);
-+ qphy = dp_clks->qphy;
-+ dp_opts = &qphy->dp_opts;
-+
-+ switch (dp_opts->link_rate) {
-+ case 1620:
-+ case 2700:
-+ case 5400:
-+ case 8100:
-+ return dp_opts->link_rate * 100000;
-+ default:
-+ return 0;
-+ }
-+}
-+
-+static const struct clk_ops qcom_qmp_dp_link_clk_ops = {
-+ .determine_rate = qcom_qmp_dp_link_clk_determine_rate,
-+ .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate,
-+};
-+
-+static struct clk_hw *
-+qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data)
-+{
-+ struct qmp_phy_dp_clks *dp_clks = data;
-+ unsigned int idx = clkspec->args[0];
-+
-+ if (idx >= 2) {
-+ pr_err("%s: invalid index %u\n", __func__, idx);
-+ return ERR_PTR(-EINVAL);
-+ }
-+
-+ if (idx == 0)
-+ return &dp_clks->dp_link_hw;
-+
-+ return &dp_clks->dp_pixel_hw;
-+}
-+
-+static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy,
-+ struct device_node *np)
-+{
-+ struct clk_init_data init = { };
-+ struct qmp_phy_dp_clks *dp_clks;
-+ char name[64];
-+ int ret;
-+
-+ dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL);
-+ if (!dp_clks)
-+ return -ENOMEM;
-+
-+ dp_clks->qphy = qphy;
-+ qphy->dp_clks = dp_clks;
-+
-+ snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev));
-+ init.ops = &qcom_qmp_dp_link_clk_ops;
-+ init.name = name;
-+ dp_clks->dp_link_hw.init = &init;
-+ ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw);
-+ if (ret)
-+ return ret;
-+
-+ snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev));
-+ init.ops = &qcom_qmp_dp_pixel_clk_ops;
-+ init.name = name;
-+ dp_clks->dp_pixel_hw.init = &init;
-+ ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw);
-+ if (ret)
-+ return ret;
-+
-+ ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks);
-+ if (ret)
-+ return ret;
-+
-+ /*
-+ * Roll a devm action because the clock provider is the child node, but
-+ * the child node is not actually a device.
-+ */
-+ return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
-+}
-+
-+static const struct phy_ops qcom_qmp_phy_gen_ops = {
-+ .init = qcom_qmp_phy_enable,
-+ .exit = qcom_qmp_phy_disable,
-+ .set_mode = qcom_qmp_phy_set_mode,
-+ .owner = THIS_MODULE,
-+};
-+
-+static const struct phy_ops qcom_qmp_phy_dp_ops = {
-+ .init = qcom_qmp_phy_init,
-+ .configure = qcom_qmp_dp_phy_configure,
-+ .power_on = qcom_qmp_phy_power_on,
-+ .calibrate = qcom_qmp_dp_phy_calibrate,
-+ .power_off = qcom_qmp_phy_power_off,
-+ .exit = qcom_qmp_phy_exit,
-+ .set_mode = qcom_qmp_phy_set_mode,
-+ .owner = THIS_MODULE,
-+};
-+
-+static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
-+ .power_on = qcom_qmp_phy_enable,
-+ .power_off = qcom_qmp_phy_disable,
-+ .set_mode = qcom_qmp_phy_set_mode,
-+ .owner = THIS_MODULE,
-+};
-+
-+static void qcom_qmp_reset_control_put(void *data)
-+{
-+ reset_control_put(data);
-+}
-+
-+static
-+int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
-+ void __iomem *serdes, const struct qmp_phy_cfg *cfg)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ struct phy *generic_phy;
-+ struct qmp_phy *qphy;
-+ const struct phy_ops *ops;
-+ char prop_name[MAX_PROP_NAME];
-+ int ret;
-+
-+ qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
-+ if (!qphy)
-+ return -ENOMEM;
-+
-+ qphy->cfg = cfg;
-+ qphy->serdes = serdes;
-+ /*
-+ * Get memory resources for each phy lane:
-+ * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
-+ * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
-+ * For single lane PHYs: pcs_misc (optional) -> 3.
-+ */
-+ qphy->tx = of_iomap(np, 0);
-+ if (!qphy->tx)
-+ return -ENOMEM;
-+
-+ qphy->rx = of_iomap(np, 1);
-+ if (!qphy->rx)
-+ return -ENOMEM;
-+
-+ qphy->pcs = of_iomap(np, 2);
-+ if (!qphy->pcs)
-+ return -ENOMEM;
-+
-+ /*
-+ * If this is a dual-lane PHY, then there should be registers for the
-+ * second lane. Some old device trees did not specify this, so fall
-+ * back to old legacy behavior of assuming they can be reached at an
-+ * offset from the first lane.
-+ */
-+ if (cfg->is_dual_lane_phy) {
-+ qphy->tx2 = of_iomap(np, 3);
-+ qphy->rx2 = of_iomap(np, 4);
-+ if (!qphy->tx2 || !qphy->rx2) {
-+ dev_warn(dev,
-+ "Underspecified device tree, falling back to legacy register regions\n");
-+
-+ /* In the old version, pcs_misc is at index 3. */
-+ qphy->pcs_misc = qphy->tx2;
-+ qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE;
-+ qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
-+
-+ } else {
-+ qphy->pcs_misc = of_iomap(np, 5);
-+ }
-+
-+ } else {
-+ qphy->pcs_misc = of_iomap(np, 3);
-+ }
-+
-+ if (!qphy->pcs_misc)
-+ dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
-+
-+ /*
-+ * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3
-+ * based phys, so they essentially have pipe clock. So,
-+ * we return error in case phy is USB3 or PIPE type.
-+ * Otherwise, we initialize pipe clock to NULL for
-+ * all phys that don't need this.
-+ */
-+ snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
-+ qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name);
-+ if (IS_ERR(qphy->pipe_clk)) {
-+ if (cfg->type == PHY_TYPE_PCIE ||
-+ cfg->type == PHY_TYPE_USB3) {
-+ ret = PTR_ERR(qphy->pipe_clk);
-+ if (ret != -EPROBE_DEFER)
-+ dev_err(dev,
-+ "failed to get lane%d pipe_clk, %d\n",
-+ id, ret);
-+ return ret;
-+ }
-+ qphy->pipe_clk = NULL;
-+ }
-+
-+ /* Get lane reset, if any */
-+ if (cfg->has_lane_rst) {
-+ snprintf(prop_name, sizeof(prop_name), "lane%d", id);
-+ qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name);
-+ if (IS_ERR(qphy->lane_rst)) {
-+ dev_err(dev, "failed to get lane%d reset\n", id);
-+ return PTR_ERR(qphy->lane_rst);
-+ }
-+ ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put,
-+ qphy->lane_rst);
-+ if (ret)
-+ return ret;
-+ }
-+
-+ if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE)
-+ ops = &qcom_qmp_pcie_ufs_ops;
-+ else if (cfg->type == PHY_TYPE_DP)
-+ ops = &qcom_qmp_phy_dp_ops;
-+ else
-+ ops = &qcom_qmp_phy_gen_ops;
-+
-+ generic_phy = devm_phy_create(dev, np, ops);
-+ if (IS_ERR(generic_phy)) {
-+ ret = PTR_ERR(generic_phy);
-+ dev_err(dev, "failed to create qphy %d\n", ret);
-+ return ret;
-+ }
-+
-+ qphy->phy = generic_phy;
-+ qphy->index = id;
-+ qphy->qmp = qmp;
-+ qmp->phys[id] = qphy;
-+ phy_set_drvdata(generic_phy, qphy);
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
-+ {
-+ .compatible = "qcom,ipq8074-qmp-usb3-phy",
-+ .data = &ipq8074_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,msm8996-qmp-pcie-phy",
-+ .data = &msm8996_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,msm8996-qmp-ufs-phy",
-+ .data = &msm8996_ufs_cfg,
-+ }, {
-+ .compatible = "qcom,msm8996-qmp-usb3-phy",
-+ .data = &msm8996_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,msm8998-qmp-pcie-phy",
-+ .data = &msm8998_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,msm8998-qmp-ufs-phy",
-+ .data = &sdm845_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,ipq8074-qmp-pcie-phy",
-+ .data = &ipq8074_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,ipq6018-qmp-pcie-phy",
-+ .data = &ipq6018_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,ipq6018-qmp-usb3-phy",
-+ .data = &ipq8074_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sc7180-qmp-usb3-phy",
-+ .data = &sc7180_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
-+ /* It's a combo phy */
-+ }, {
-+ .compatible = "qcom,sc8180x-qmp-pcie-phy",
-+ .data = &sc8180x_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sc8180x-qmp-ufs-phy",
-+ .data = &sm8150_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sc8280xp-qmp-ufs-phy",
-+ .data = &sm8350_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sc8180x-qmp-usb3-phy",
-+ .data = &sm8150_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
-+ /* It's a combo phy */
-+ }, {
-+ .compatible = "qcom,sdm845-qhp-pcie-phy",
-+ .data = &sdm845_qhp_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sdm845-qmp-pcie-phy",
-+ .data = &sdm845_qmp_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sdm845-qmp-usb3-phy",
-+ .data = &qmp_v3_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
-+ .data = &qmp_v3_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sdm845-qmp-ufs-phy",
-+ .data = &sdm845_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,msm8998-qmp-usb3-phy",
-+ .data = &msm8998_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sm6115-qmp-ufs-phy",
-+ .data = &sm6115_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm6350-qmp-ufs-phy",
-+ .data = &sdm845_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8150-qmp-ufs-phy",
-+ .data = &sm8150_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-ufs-phy",
-+ .data = &sm8150_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8150-qmp-usb3-phy",
-+ .data = &sm8150_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8150-qmp-usb3-uni-phy",
-+ .data = &sm8150_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-usb3-phy",
-+ .data = &sm8250_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
-+ /* It's a combo phy */
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-usb3-uni-phy",
-+ .data = &sm8250_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
-+ .data = &sm8250_qmp_gen3x1_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
-+ .data = &sm8250_qmp_gen3x2_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8350-qmp-ufs-phy",
-+ .data = &sm8350_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
-+ .data = &sm8250_qmp_gen3x2_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sdx55-qmp-pcie-phy",
-+ .data = &sdx55_qmp_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sdx55-qmp-usb3-uni-phy",
-+ .data = &sdx55_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sdx65-qmp-usb3-uni-phy",
-+ .data = &sdx65_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8350-qmp-usb3-phy",
-+ .data = &sm8350_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8350-qmp-usb3-uni-phy",
-+ .data = &sm8350_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
-+ .data = &sm8450_qmp_gen3x1_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
-+ .data = &sm8450_qmp_gen4x2_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8450-qmp-ufs-phy",
-+ .data = &sm8450_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8450-qmp-usb3-phy",
-+ .data = &sm8350_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,qcm2290-qmp-usb3-phy",
-+ .data = &qcm2290_usb3phy_cfg,
-+ },
-+ { },
-+};
-+MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
-+
-+static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = {
-+ {
-+ .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
-+ .data = &sc7180_usb3dpphy_cfg,
-+ },
-+ {
-+ .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
-+ .data = &sm8250_usb3dpphy_cfg,
-+ },
-+ {
-+ .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
-+ .data = &sc8180x_usb3dpphy_cfg,
-+ },
-+ { }
-+};
-+
-+static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
-+ SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
-+ qcom_qmp_phy_runtime_resume, NULL)
-+};
-+
-+static int qcom_qmp_phy_probe(struct platform_device *pdev)
-+{
-+ struct qcom_qmp *qmp;
-+ struct device *dev = &pdev->dev;
-+ struct device_node *child;
-+ struct phy_provider *phy_provider;
-+ void __iomem *serdes;
-+ void __iomem *usb_serdes;
-+ void __iomem *dp_serdes = NULL;
-+ const struct qmp_phy_combo_cfg *combo_cfg = NULL;
-+ const struct qmp_phy_cfg *cfg = NULL;
-+ const struct qmp_phy_cfg *usb_cfg = NULL;
-+ const struct qmp_phy_cfg *dp_cfg = NULL;
-+ int num, id, expected_phys;
-+ int ret;
-+
-+ qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
-+ if (!qmp)
-+ return -ENOMEM;
-+
-+ qmp->dev = dev;
-+ dev_set_drvdata(dev, qmp);
-+
-+ /* Get the specific init parameters of QMP phy */
-+ cfg = of_device_get_match_data(dev);
-+ if (!cfg) {
-+ const struct of_device_id *match;
-+
-+ match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev);
-+ if (!match)
-+ return -EINVAL;
-+
-+ combo_cfg = match->data;
-+ if (!combo_cfg)
-+ return -EINVAL;
-+
-+ usb_cfg = combo_cfg->usb_cfg;
-+ cfg = usb_cfg; /* Setup clks and regulators */
-+ }
-+
-+ /* per PHY serdes; usually located at base address */
-+ usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0);
-+ if (IS_ERR(serdes))
-+ return PTR_ERR(serdes);
-+
-+ /* per PHY dp_com; if PHY has dp_com control block */
-+ if (combo_cfg || cfg->has_phy_dp_com_ctrl) {
-+ qmp->dp_com = devm_platform_ioremap_resource(pdev, 1);
-+ if (IS_ERR(qmp->dp_com))
-+ return PTR_ERR(qmp->dp_com);
-+ }
-+
-+ if (combo_cfg) {
-+ /* Only two serdes for combo PHY */
-+ dp_serdes = devm_platform_ioremap_resource(pdev, 2);
-+ if (IS_ERR(dp_serdes))
-+ return PTR_ERR(dp_serdes);
-+
-+ dp_cfg = combo_cfg->dp_cfg;
-+ expected_phys = 2;
-+ } else {
-+ expected_phys = cfg->nlanes;
-+ }
-+
-+ mutex_init(&qmp->phy_mutex);
-+
-+ ret = qcom_qmp_phy_clk_init(dev, cfg);
-+ if (ret)
-+ return ret;
-+
-+ ret = qcom_qmp_phy_reset_init(dev, cfg);
-+ if (ret)
-+ return ret;
-+
-+ ret = qcom_qmp_phy_vreg_init(dev, cfg);
-+ if (ret) {
-+ if (ret != -EPROBE_DEFER)
-+ dev_err(dev, "failed to get regulator supplies: %d\n",
-+ ret);
-+ return ret;
-+ }
-+
-+ num = of_get_available_child_count(dev->of_node);
-+ /* do we have a rogue child node ? */
-+ if (num > expected_phys)
-+ return -EINVAL;
-+
-+ qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
-+ if (!qmp->phys)
-+ return -ENOMEM;
-+
-+ pm_runtime_set_active(dev);
-+ pm_runtime_enable(dev);
-+ /*
-+ * Prevent runtime pm from being ON by default. Users can enable
-+ * it using power/control in sysfs.
-+ */
-+ pm_runtime_forbid(dev);
-+
-+ id = 0;
-+ for_each_available_child_of_node(dev->of_node, child) {
-+ if (of_node_name_eq(child, "dp-phy")) {
-+ cfg = dp_cfg;
-+ serdes = dp_serdes;
-+ } else if (of_node_name_eq(child, "usb3-phy")) {
-+ cfg = usb_cfg;
-+ serdes = usb_serdes;
-+ }
-+
-+ /* Create per-lane phy */
-+ ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg);
-+ if (ret) {
-+ dev_err(dev, "failed to create lane%d phy, %d\n",
-+ id, ret);
-+ goto err_node_put;
-+ }
-+
-+ /*
-+ * Register the pipe clock provided by phy.
-+ * See function description to see details of this pipe clock.
-+ */
-+ if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) {
-+ ret = phy_pipe_clk_register(qmp, child);
-+ if (ret) {
-+ dev_err(qmp->dev,
-+ "failed to register pipe clock source\n");
-+ goto err_node_put;
-+ }
-+ } else if (cfg->type == PHY_TYPE_DP) {
-+ ret = phy_dp_clks_register(qmp, qmp->phys[id], child);
-+ if (ret) {
-+ dev_err(qmp->dev,
-+ "failed to register DP clock source\n");
-+ goto err_node_put;
-+ }
-+ }
-+ id++;
-+ }
-+
-+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
-+ if (!IS_ERR(phy_provider))
-+ dev_info(dev, "Registered Qcom-QMP phy\n");
-+ else
-+ pm_runtime_disable(dev);
-+
-+ return PTR_ERR_OR_ZERO(phy_provider);
-+
-+err_node_put:
-+ pm_runtime_disable(dev);
-+ of_node_put(child);
-+ return ret;
-+}
-+
-+static struct platform_driver qcom_qmp_phy_driver = {
-+ .probe = qcom_qmp_phy_probe,
-+ .driver = {
-+ .name = "qcom-qmp-phy",
-+ .pm = &qcom_qmp_phy_pm_ops,
-+ .of_match_table = qcom_qmp_phy_of_match_table,
-+ },
-+};
-+
-+module_platform_driver(qcom_qmp_phy_driver);
-+
-+MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
-+MODULE_DESCRIPTION("Qualcomm QMP PHY driver");
-+MODULE_LICENSE("GPL v2");
-diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
-new file mode 100644
-index 000000000000..c7309e981bfb
---- /dev/null
-+++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
-@@ -0,0 +1,6350 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/clk-provider.h>
-+#include <linux/delay.h>
-+#include <linux/err.h>
-+#include <linux/io.h>
-+#include <linux/iopoll.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/of_device.h>
-+#include <linux/of_address.h>
-+#include <linux/phy/phy.h>
-+#include <linux/platform_device.h>
-+#include <linux/regulator/consumer.h>
-+#include <linux/reset.h>
-+#include <linux/slab.h>
-+
-+#include <dt-bindings/phy/phy.h>
-+
-+#include "phy-qcom-qmp.h"
-+
-+/* QPHY_SW_RESET bit */
-+#define SW_RESET BIT(0)
-+/* QPHY_POWER_DOWN_CONTROL */
-+#define SW_PWRDN BIT(0)
-+#define REFCLK_DRV_DSBL BIT(1)
-+/* QPHY_START_CONTROL bits */
-+#define SERDES_START BIT(0)
-+#define PCS_START BIT(1)
-+#define PLL_READY_GATE_EN BIT(3)
-+/* QPHY_PCS_STATUS bit */
-+#define PHYSTATUS BIT(6)
-+#define PHYSTATUS_4_20 BIT(7)
-+/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */
-+#define PCS_READY BIT(0)
-+
-+/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
-+/* DP PHY soft reset */
-+#define SW_DPPHY_RESET BIT(0)
-+/* mux to select DP PHY reset control, 0:HW control, 1: software reset */
-+#define SW_DPPHY_RESET_MUX BIT(1)
-+/* USB3 PHY soft reset */
-+#define SW_USB3PHY_RESET BIT(2)
-+/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
-+#define SW_USB3PHY_RESET_MUX BIT(3)
-+
-+/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
-+#define USB3_MODE BIT(0) /* enables USB3 mode */
-+#define DP_MODE BIT(1) /* enables DP mode */
-+
-+/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
-+#define ARCVR_DTCT_EN BIT(0)
-+#define ALFPS_DTCT_EN BIT(1)
-+#define ARCVR_DTCT_EVENT_SEL BIT(4)
-+
-+/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
-+#define IRQ_CLEAR BIT(0)
-+
-+/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
-+#define RCVR_DETECT BIT(0)
-+
-+/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
-+#define CLAMP_EN BIT(0) /* enables i/o clamp_n */
-+
-+#define PHY_INIT_COMPLETE_TIMEOUT 10000
-+#define POWER_DOWN_DELAY_US_MIN 10
-+#define POWER_DOWN_DELAY_US_MAX 11
-+
-+#define MAX_PROP_NAME 32
-+
-+/* Define the assumed distance between lanes for underspecified device trees. */
-+#define QMP_PHY_LEGACY_LANE_STRIDE 0x400
-+
-+struct qmp_phy_init_tbl {
-+ unsigned int offset;
-+ unsigned int val;
-+ /*
-+ * register part of layout ?
-+ * if yes, then offset gives index in the reg-layout
-+ */
-+ bool in_layout;
-+ /*
-+ * mask of lanes for which this register is written
-+ * for cases when second lane needs different values
-+ */
-+ u8 lane_mask;
-+};
-+
-+#define QMP_PHY_INIT_CFG(o, v) \
-+ { \
-+ .offset = o, \
-+ .val = v, \
-+ .lane_mask = 0xff, \
-+ }
-+
-+#define QMP_PHY_INIT_CFG_L(o, v) \
-+ { \
-+ .offset = o, \
-+ .val = v, \
-+ .in_layout = true, \
-+ .lane_mask = 0xff, \
-+ }
-+
-+#define QMP_PHY_INIT_CFG_LANE(o, v, l) \
-+ { \
-+ .offset = o, \
-+ .val = v, \
-+ .lane_mask = l, \
-+ }
-+
-+/* set of registers with offsets different per-PHY */
-+enum qphy_reg_layout {
-+ /* Common block control registers */
-+ QPHY_COM_SW_RESET,
-+ QPHY_COM_POWER_DOWN_CONTROL,
-+ QPHY_COM_START_CONTROL,
-+ QPHY_COM_PCS_READY_STATUS,
-+ /* PCS registers */
-+ QPHY_PLL_LOCK_CHK_DLY_TIME,
-+ QPHY_FLL_CNTRL1,
-+ QPHY_FLL_CNTRL2,
-+ QPHY_FLL_CNT_VAL_L,
-+ QPHY_FLL_CNT_VAL_H_TOL,
-+ QPHY_FLL_MAN_CODE,
-+ QPHY_SW_RESET,
-+ QPHY_START_CTRL,
-+ QPHY_PCS_READY_STATUS,
-+ QPHY_PCS_STATUS,
-+ QPHY_PCS_AUTONOMOUS_MODE_CTRL,
-+ QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
-+ QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
-+ QPHY_PCS_POWER_DOWN_CONTROL,
-+ /* PCS_MISC registers */
-+ QPHY_PCS_MISC_TYPEC_CTRL,
-+ /* Keep last to ensure regs_layout arrays are properly initialized */
-+ QPHY_LAYOUT_SIZE
-+};
-+
-+static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_START_CTRL] = 0x00,
-+ [QPHY_PCS_READY_STATUS] = 0x168,
-+};
-+
-+static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x44,
-+ [QPHY_PCS_STATUS] = 0x14,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
-+};
-+
-+static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_COM_SW_RESET] = 0x400,
-+ [QPHY_COM_POWER_DOWN_CONTROL] = 0x404,
-+ [QPHY_COM_START_CONTROL] = 0x408,
-+ [QPHY_COM_PCS_READY_STATUS] = 0x448,
-+ [QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8,
-+ [QPHY_FLL_CNTRL1] = 0xc4,
-+ [QPHY_FLL_CNTRL2] = 0xc8,
-+ [QPHY_FLL_CNT_VAL_L] = 0xcc,
-+ [QPHY_FLL_CNT_VAL_H_TOL] = 0xd0,
-+ [QPHY_FLL_MAN_CODE] = 0xd4,
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_STATUS] = 0x174,
-+};
-+
-+static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_FLL_CNTRL1] = 0xc0,
-+ [QPHY_FLL_CNTRL2] = 0xc4,
-+ [QPHY_FLL_CNT_VAL_L] = 0xc8,
-+ [QPHY_FLL_CNT_VAL_H_TOL] = 0xcc,
-+ [QPHY_FLL_MAN_CODE] = 0xd0,
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_STATUS] = 0x17c,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
-+};
-+
-+static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_STATUS] = 0x174,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
-+};
-+
-+static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_STATUS] = 0x174,
-+};
-+
-+static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_STATUS] = 0x2ac,
-+};
-+
-+static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x44,
-+ [QPHY_PCS_STATUS] = 0x14,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314,
-+};
-+
-+static const unsigned int qmp_v4_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x44,
-+ [QPHY_PCS_STATUS] = 0x14,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x608,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x614,
-+};
-+
-+static const unsigned int sm8350_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x44,
-+ [QPHY_PCS_STATUS] = 0x14,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x1008,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x1014,
-+};
-+
-+static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0xd8,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc,
-+ [QPHY_PCS_STATUS] = 0x174,
-+ [QPHY_PCS_MISC_TYPEC_CTRL] = 0x00,
-+};
-+
-+static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_START_CTRL] = 0x00,
-+ [QPHY_PCS_READY_STATUS] = 0x160,
-+};
-+
-+static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_START_CTRL] = 0x00,
-+ [QPHY_PCS_READY_STATUS] = 0x168,
-+};
-+
-+static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x44,
-+ [QPHY_PCS_STATUS] = 0x14,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
-+};
-+
-+static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START,
-+ [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS,
-+ [QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET,
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
-+ /* PLL and Loop filter settings */
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-+ /* SSC settings */
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
-+ QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
-+
-+ QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
-+
-+ QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
-+ QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
-+ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
-+ /* PLL and Loop filter settings */
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-+ /* SSC settings */
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
-+ /* FLL settings */
-+ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03),
-+ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02),
-+ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42),
-+ QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
-+
-+ /* Lock Det settings */
-+ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x61),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d),
-+ QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10),
-+ QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_PRE, 0x00),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_POST, 0x58),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
-+ QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
-+ QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
-+ QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
-+ QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
-+ QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
-+ QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
-+ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
-+ QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
-+ QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = {
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
-+ /* FLL settings */
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+
-+ /* Lock Det settings */
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
-+ /* FLL settings */
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+
-+ /* Lock Det settings */
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
-+};
-+
-+static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
-+
-+ /* Rate B */
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),
-+};
-+
-+static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B),
-+};
-+
-+static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_RX_PWM_GEAR_BAND, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_CTRL2, 0x6d),
-+ QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_DRV_LVL, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_DRV_LVL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
-+ QMP_PHY_INIT_CFG(QPHY_RX_SYM_RESYNC_CTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
-+ QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
-+
-+ /* Rate B */
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
-+
-+ /* Rate B */
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
-+
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
-+ /* Lock Det settings */
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20),
-+};
-+
-+static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
-+};
-+
-+static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5),
-+};
-+
-+static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
-+};
-+
-+static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),
-+};
-+
-+static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
-+
-+ /* Rate B */
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+};
-+
-+static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01),
-+};
-+
-+static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
-+
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05),
-+
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
-+
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
-+
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
-+};
-+
-+/* Register names should be validated, they might be different for this PHY */
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
-+};
-+
-+struct qmp_phy;
-+
-+/* struct qmp_phy_cfg - per-PHY initialization config */
-+struct qmp_phy_cfg {
-+ /* phy-type - PCIE/UFS/USB */
-+ unsigned int type;
-+ /* number of lanes provided by phy */
-+ int nlanes;
-+
-+ /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
-+ const struct qmp_phy_init_tbl *serdes_tbl;
-+ int serdes_tbl_num;
-+ const struct qmp_phy_init_tbl *serdes_tbl_sec;
-+ int serdes_tbl_num_sec;
-+ const struct qmp_phy_init_tbl *tx_tbl;
-+ int tx_tbl_num;
-+ const struct qmp_phy_init_tbl *tx_tbl_sec;
-+ int tx_tbl_num_sec;
-+ const struct qmp_phy_init_tbl *rx_tbl;
-+ int rx_tbl_num;
-+ const struct qmp_phy_init_tbl *rx_tbl_sec;
-+ int rx_tbl_num_sec;
-+ const struct qmp_phy_init_tbl *pcs_tbl;
-+ int pcs_tbl_num;
-+ const struct qmp_phy_init_tbl *pcs_tbl_sec;
-+ int pcs_tbl_num_sec;
-+ const struct qmp_phy_init_tbl *pcs_misc_tbl;
-+ int pcs_misc_tbl_num;
-+ const struct qmp_phy_init_tbl *pcs_misc_tbl_sec;
-+ int pcs_misc_tbl_num_sec;
-+
-+ /* Init sequence for DP PHY block link rates */
-+ const struct qmp_phy_init_tbl *serdes_tbl_rbr;
-+ int serdes_tbl_rbr_num;
-+ const struct qmp_phy_init_tbl *serdes_tbl_hbr;
-+ int serdes_tbl_hbr_num;
-+ const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
-+ int serdes_tbl_hbr2_num;
-+ const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
-+ int serdes_tbl_hbr3_num;
-+
-+ /* DP PHY callbacks */
-+ int (*configure_dp_phy)(struct qmp_phy *qphy);
-+ void (*configure_dp_tx)(struct qmp_phy *qphy);
-+ int (*calibrate_dp_phy)(struct qmp_phy *qphy);
-+ void (*dp_aux_init)(struct qmp_phy *qphy);
-+
-+ /* clock ids to be requested */
-+ const char * const *clk_list;
-+ int num_clks;
-+ /* resets to be requested */
-+ const char * const *reset_list;
-+ int num_resets;
-+ /* regulators to be requested */
-+ const char * const *vreg_list;
-+ int num_vregs;
-+
-+ /* array of registers with different offsets */
-+ const unsigned int *regs;
-+
-+ unsigned int start_ctrl;
-+ unsigned int pwrdn_ctrl;
-+ unsigned int mask_com_pcs_ready;
-+ /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
-+ unsigned int phy_status;
-+
-+ /* true, if PHY has a separate PHY_COM control block */
-+ bool has_phy_com_ctrl;
-+ /* true, if PHY has a reset for individual lanes */
-+ bool has_lane_rst;
-+ /* true, if PHY needs delay after POWER_DOWN */
-+ bool has_pwrdn_delay;
-+ /* power_down delay in usec */
-+ int pwrdn_delay_min;
-+ int pwrdn_delay_max;
-+
-+ /* true, if PHY has a separate DP_COM control block */
-+ bool has_phy_dp_com_ctrl;
-+ /* true, if PHY has secondary tx/rx lanes to be configured */
-+ bool is_dual_lane_phy;
-+
-+ /* true, if PCS block has no separate SW_RESET register */
-+ bool no_pcs_sw_reset;
-+};
-+
-+struct qmp_phy_combo_cfg {
-+ const struct qmp_phy_cfg *usb_cfg;
-+ const struct qmp_phy_cfg *dp_cfg;
-+};
-+
-+/**
-+ * struct qmp_phy - per-lane phy descriptor
-+ *
-+ * @phy: generic phy
-+ * @cfg: phy specific configuration
-+ * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
-+ * @tx: iomapped memory space for lane's tx
-+ * @rx: iomapped memory space for lane's rx
-+ * @pcs: iomapped memory space for lane's pcs
-+ * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
-+ * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
-+ * @pcs_misc: iomapped memory space for lane's pcs_misc
-+ * @pipe_clk: pipe clock
-+ * @index: lane index
-+ * @qmp: QMP phy to which this lane belongs
-+ * @lane_rst: lane's reset controller
-+ * @mode: current PHY mode
-+ * @dp_aux_cfg: Display port aux config
-+ * @dp_opts: Display port optional config
-+ * @dp_clks: Display port clocks
-+ */
-+struct qmp_phy {
-+ struct phy *phy;
-+ const struct qmp_phy_cfg *cfg;
-+ void __iomem *serdes;
-+ void __iomem *tx;
-+ void __iomem *rx;
-+ void __iomem *pcs;
-+ void __iomem *tx2;
-+ void __iomem *rx2;
-+ void __iomem *pcs_misc;
-+ struct clk *pipe_clk;
-+ unsigned int index;
-+ struct qcom_qmp *qmp;
-+ struct reset_control *lane_rst;
-+ enum phy_mode mode;
-+ unsigned int dp_aux_cfg;
-+ struct phy_configure_opts_dp dp_opts;
-+ struct qmp_phy_dp_clks *dp_clks;
-+};
-+
-+struct qmp_phy_dp_clks {
-+ struct qmp_phy *qphy;
-+ struct clk_hw dp_link_hw;
-+ struct clk_hw dp_pixel_hw;
-+};
-+
-+/**
-+ * struct qcom_qmp - structure holding QMP phy block attributes
-+ *
-+ * @dev: device
-+ * @dp_com: iomapped memory space for phy's dp_com control block
-+ *
-+ * @clks: array of clocks required by phy
-+ * @resets: array of resets required by phy
-+ * @vregs: regulator supplies bulk data
-+ *
-+ * @phys: array of per-lane phy descriptors
-+ * @phy_mutex: mutex lock for PHY common block initialization
-+ * @init_count: phy common block initialization count
-+ * @ufs_reset: optional UFS PHY reset handle
-+ */
-+struct qcom_qmp {
-+ struct device *dev;
-+ void __iomem *dp_com;
-+
-+ struct clk_bulk_data *clks;
-+ struct reset_control **resets;
-+ struct regulator_bulk_data *vregs;
-+
-+ struct qmp_phy **phys;
-+
-+ struct mutex phy_mutex;
-+ int init_count;
-+
-+ struct reset_control *ufs_reset;
-+};
-+
-+static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy);
-+static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy);
-+static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy);
-+static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy);
-+
-+static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy);
-+static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy);
-+static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy);
-+static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy);
-+
-+static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
-+{
-+ u32 reg;
-+
-+ reg = readl(base + offset);
-+ reg |= val;
-+ writel(reg, base + offset);
-+
-+ /* ensure that above write is through */
-+ readl(base + offset);
-+}
-+
-+static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
-+{
-+ u32 reg;
-+
-+ reg = readl(base + offset);
-+ reg &= ~val;
-+ writel(reg, base + offset);
-+
-+ /* ensure that above write is through */
-+ readl(base + offset);
-+}
-+
-+/* list of clocks required by phy */
-+static const char * const msm8996_phy_clk_l[] = {
-+ "aux", "cfg_ahb", "ref",
-+};
-+
-+static const char * const msm8996_ufs_phy_clk_l[] = {
-+ "ref",
-+};
-+
-+static const char * const qmp_v3_phy_clk_l[] = {
-+ "aux", "cfg_ahb", "ref", "com_aux",
-+};
-+
-+static const char * const sdm845_pciephy_clk_l[] = {
-+ "aux", "cfg_ahb", "ref", "refgen",
-+};
-+
-+static const char * const qmp_v4_phy_clk_l[] = {
-+ "aux", "ref_clk_src", "ref", "com_aux",
-+};
-+
-+/* the primary usb3 phy on sm8250 doesn't have a ref clock */
-+static const char * const qmp_v4_sm8250_usbphy_clk_l[] = {
-+ "aux", "ref_clk_src", "com_aux"
-+};
-+
-+static const char * const sm8450_ufs_phy_clk_l[] = {
-+ "qref", "ref", "ref_aux",
-+};
-+
-+static const char * const sdm845_ufs_phy_clk_l[] = {
-+ "ref", "ref_aux",
-+};
-+
-+/* usb3 phy on sdx55 doesn't have com_aux clock */
-+static const char * const qmp_v4_sdx55_usbphy_clk_l[] = {
-+ "aux", "cfg_ahb", "ref"
-+};
-+
-+static const char * const qcm2290_usb3phy_clk_l[] = {
-+ "cfg_ahb", "ref", "com_aux",
-+};
-+
-+/* list of resets */
-+static const char * const msm8996_pciephy_reset_l[] = {
-+ "phy", "common", "cfg",
-+};
-+
-+static const char * const msm8996_usb3phy_reset_l[] = {
-+ "phy", "common",
-+};
-+
-+static const char * const sc7180_usb3phy_reset_l[] = {
-+ "phy",
-+};
-+
-+static const char * const qcm2290_usb3phy_reset_l[] = {
-+ "phy_phy", "phy",
-+};
-+
-+static const char * const sdm845_pciephy_reset_l[] = {
-+ "phy",
-+};
-+
-+/* list of regulators */
-+static const char * const qmp_phy_vreg_l[] = {
-+ "vdda-phy", "vdda-pll",
-+};
-+
-+static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = ipq8074_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
-+ .tx_tbl = msm8996_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
-+ .rx_tbl = ipq8074_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
-+ .pcs_tbl = ipq8074_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
-+ .clk_list = msm8996_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+};
-+
-+static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 3,
-+
-+ .serdes_tbl = msm8996_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
-+ .tx_tbl = msm8996_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8996_pcie_tx_tbl),
-+ .rx_tbl = msm8996_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(msm8996_pcie_rx_tbl),
-+ .pcs_tbl = msm8996_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
-+ .clk_list = msm8996_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-+ .reset_list = msm8996_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = pciephy_regs_layout,
-+
-+ .start_ctrl = PCS_START | PLL_READY_GATE_EN,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .mask_com_pcs_ready = PCS_READY,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_phy_com_ctrl = true,
-+ .has_lane_rst = true,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg msm8996_ufs_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = msm8996_ufs_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(msm8996_ufs_serdes_tbl),
-+ .tx_tbl = msm8996_ufs_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8996_ufs_tx_tbl),
-+ .rx_tbl = msm8996_ufs_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(msm8996_ufs_rx_tbl),
-+
-+ .clk_list = msm8996_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
-+
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+
-+ .regs = msm8996_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .no_pcs_sw_reset = true,
-+};
-+
-+static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = msm8996_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
-+ .tx_tbl = msm8996_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
-+ .rx_tbl = msm8996_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl),
-+ .pcs_tbl = msm8996_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
-+ .clk_list = msm8996_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+};
-+
-+static const char * const ipq8074_pciephy_clk_l[] = {
-+ "aux", "cfg_ahb",
-+};
-+/* list of resets */
-+static const char * const ipq8074_pciephy_reset_l[] = {
-+ "phy", "common",
-+};
-+
-+static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = ipq8074_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
-+ .tx_tbl = ipq8074_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
-+ .rx_tbl = ipq8074_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
-+ .pcs_tbl = ipq8074_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
-+ .clk_list = ipq8074_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
-+ .reset_list = ipq8074_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
-+ .vreg_list = NULL,
-+ .num_vregs = 0,
-+ .regs = pciephy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_phy_com_ctrl = false,
-+ .has_lane_rst = false,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = ipq6018_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl),
-+ .tx_tbl = ipq6018_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl),
-+ .rx_tbl = ipq6018_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
-+ .pcs_tbl = ipq6018_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
-+ .clk_list = ipq8074_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
-+ .reset_list = ipq8074_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
-+ .vreg_list = NULL,
-+ .num_vregs = 0,
-+ .regs = ipq_pciephy_gen3_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+
-+ .has_phy_com_ctrl = false,
-+ .has_lane_rst = false,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sdm845_qmp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
-+ .tx_tbl = sdm845_qmp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),
-+ .rx_tbl = sdm845_qmp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),
-+ .pcs_tbl = sdm845_qmp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sdm845_qmp_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sdm845_qmp_pciephy_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sdm845_qhp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
-+ .tx_tbl = sdm845_qhp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
-+ .rx_tbl = sdm845_qhp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl),
-+ .pcs_tbl = sdm845_qhp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sdm845_qhp_pciephy_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
-+ .serdes_tbl_sec = sm8250_qmp_gen3x1_pcie_serdes_tbl,
-+ .serdes_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
-+ .tx_tbl = sm8250_qmp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
-+ .rx_tbl = sm8250_qmp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
-+ .rx_tbl_sec = sm8250_qmp_gen3x1_pcie_rx_tbl,
-+ .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),
-+ .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
-+ .pcs_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_tbl,
-+ .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
-+ .pcs_misc_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
-+ .tx_tbl = sm8250_qmp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
-+ .tx_tbl_sec = sm8250_qmp_gen3x2_pcie_tx_tbl,
-+ .tx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),
-+ .rx_tbl = sm8250_qmp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
-+ .rx_tbl_sec = sm8250_qmp_gen3x2_pcie_rx_tbl,
-+ .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl),
-+ .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
-+ .pcs_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_tbl,
-+ .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
-+ .pcs_misc_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v3_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
-+ .tx_tbl = qmp_v3_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
-+ .rx_tbl = qmp_v3_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
-+ .pcs_tbl = qmp_v3_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
-+ .clk_list = qmp_v3_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v3_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
-+ .tx_tbl = qmp_v3_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
-+ .rx_tbl = qmp_v3_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
-+ .pcs_tbl = qmp_v3_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
-+ .clk_list = qmp_v3_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-+ .reset_list = sc7180_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sc7180_dpphy_cfg = {
-+ .type = PHY_TYPE_DP,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v3_dp_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
-+ .tx_tbl = qmp_v3_dp_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
-+
-+ .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr,
-+ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
-+ .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr,
-+ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
-+ .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2,
-+ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
-+ .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3,
-+ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
-+
-+ .clk_list = qmp_v3_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-+ .reset_list = sc7180_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+
-+ .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init,
-+ .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx,
-+ .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy,
-+ .calibrate_dp_phy = qcom_qmp_v3_dp_phy_calibrate,
-+};
-+
-+static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = {
-+ .usb_cfg = &sc7180_usb3phy_cfg,
-+ .dp_cfg = &sc7180_dpphy_cfg,
-+};
-+
-+static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
-+ .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v3_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sdm845_ufsphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
-+ .tx_tbl = sdm845_ufsphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
-+ .rx_tbl = sdm845_ufsphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
-+ .pcs_tbl = sdm845_ufsphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
-+ .clk_list = sdm845_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sdm845_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+ .no_pcs_sw_reset = true,
-+};
-+
-+static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm6115_ufsphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl),
-+ .tx_tbl = sm6115_ufsphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_tx_tbl),
-+ .rx_tbl = sm6115_ufsphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_rx_tbl),
-+ .pcs_tbl = sm6115_ufsphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl),
-+ .clk_list = sdm845_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm6115_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+
-+ .is_dual_lane_phy = false,
-+ .no_pcs_sw_reset = true,
-+};
-+
-+static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = msm8998_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
-+ .tx_tbl = msm8998_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8998_pcie_tx_tbl),
-+ .rx_tbl = msm8998_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(msm8998_pcie_rx_tbl),
-+ .pcs_tbl = msm8998_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
-+ .clk_list = msm8996_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-+ .reset_list = ipq8074_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = pciephy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+};
-+
-+static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = msm8998_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
-+ .tx_tbl = msm8998_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl),
-+ .rx_tbl = msm8998_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl),
-+ .pcs_tbl = msm8998_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
-+ .clk_list = msm8996_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sm8150_ufsphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl),
-+ .tx_tbl = sm8150_ufsphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx_tbl),
-+ .rx_tbl = sm8150_ufsphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx_tbl),
-+ .pcs_tbl = sm8150_ufsphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl),
-+ .clk_list = sdm845_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8150_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
-+ .tx_tbl = sm8150_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl),
-+ .rx_tbl = sm8150_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl),
-+ .pcs_tbl = sm8150_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
-+ .clk_list = qmp_v4_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sc8180x_qmp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl),
-+ .tx_tbl = sc8180x_qmp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl),
-+ .rx_tbl = sc8180x_qmp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl),
-+ .pcs_tbl = sc8180x_qmp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sc8180x_qmp_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sc8180x_dpphy_cfg = {
-+ .type = PHY_TYPE_DP,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v4_dp_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
-+ .tx_tbl = qmp_v4_dp_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
-+
-+ .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
-+ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
-+ .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
-+ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
-+ .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
-+ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
-+ .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
-+ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
-+
-+ .clk_list = qmp_v3_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-+ .reset_list = sc7180_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+
-+ .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
-+ .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
-+ .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
-+ .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
-+};
-+
-+static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = {
-+ .usb_cfg = &sm8150_usb3phy_cfg,
-+ .dp_cfg = &sc8180x_dpphy_cfg,
-+};
-+
-+static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = sm8150_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),
-+ .rx_tbl = sm8150_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = sm8150_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v4_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3_uniphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
-+ .tx_tbl = sm8250_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl),
-+ .rx_tbl = sm8250_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl),
-+ .pcs_tbl = sm8250_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
-+ .clk_list = qmp_v4_sm8250_usbphy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = sm8250_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),
-+ .rx_tbl = sm8250_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v4_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3_uniphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sm8250_dpphy_cfg = {
-+ .type = PHY_TYPE_DP,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v4_dp_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
-+ .tx_tbl = qmp_v4_dp_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
-+
-+ .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
-+ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
-+ .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
-+ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
-+ .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
-+ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
-+ .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
-+ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
-+
-+ .clk_list = qmp_v4_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3phy_regs_layout,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+
-+ .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
-+ .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
-+ .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
-+ .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
-+};
-+
-+static const struct qmp_phy_combo_cfg sm8250_usb3dpphy_cfg = {
-+ .usb_cfg = &sm8250_usb3phy_cfg,
-+ .dp_cfg = &sm8250_dpphy_cfg,
-+};
-+
-+static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = sdx55_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl),
-+ .rx_tbl = sdx55_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v4_sdx55_usbphy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3_uniphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sdx55_qmp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl),
-+ .tx_tbl = sdx55_qmp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl),
-+ .rx_tbl = sdx55_qmp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl),
-+ .pcs_tbl = sdx55_qmp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sdx55_qmp_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS_4_20,
-+
-+ .is_dual_lane_phy = true,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = sdx65_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl),
-+ .rx_tbl = sdx65_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v4_sdx55_usbphy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8350_usb3_uniphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sm8350_ufsphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
-+ .tx_tbl = sm8350_ufsphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
-+ .rx_tbl = sm8350_ufsphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
-+ .pcs_tbl = sm8350_ufsphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
-+ .clk_list = sdm845_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8150_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
-+ .tx_tbl = sm8350_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl),
-+ .rx_tbl = sm8350_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl),
-+ .pcs_tbl = sm8350_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl),
-+ .clk_list = qmp_v4_sm8250_usbphy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = sm8350_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),
-+ .rx_tbl = sm8350_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v4_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8350_usb3_uniphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sm8350_ufsphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
-+ .tx_tbl = sm8350_ufsphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
-+ .rx_tbl = sm8350_ufsphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
-+ .pcs_tbl = sm8350_ufsphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
-+ .clk_list = sm8450_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8150_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8450_qmp_gen3x1_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl),
-+ .tx_tbl = sm8450_qmp_gen3x1_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl),
-+ .rx_tbl = sm8450_qmp_gen3x1_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl),
-+ .pcs_tbl = sm8450_qmp_gen3x1_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sm8450_qmp_gen4x2_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl),
-+ .tx_tbl = sm8450_qmp_gen4x2_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl),
-+ .rx_tbl = sm8450_qmp_gen4x2_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl),
-+ .pcs_tbl = sm8450_qmp_gen4x2_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS_4_20,
-+
-+ .is_dual_lane_phy = true,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qcm2290_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl),
-+ .tx_tbl = qcm2290_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl),
-+ .rx_tbl = qcm2290_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(qcm2290_usb3_rx_tbl),
-+ .pcs_tbl = qcm2290_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl),
-+ .clk_list = qcm2290_usb3phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qcm2290_usb3phy_clk_l),
-+ .reset_list = qcm2290_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qcm2290_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+};
-+
-+static void qcom_qmp_phy_configure_lane(void __iomem *base,
-+ const unsigned int *regs,
-+ const struct qmp_phy_init_tbl tbl[],
-+ int num,
-+ u8 lane_mask)
-+{
-+ int i;
-+ const struct qmp_phy_init_tbl *t = tbl;
-+
-+ if (!t)
-+ return;
-+
-+ for (i = 0; i < num; i++, t++) {
-+ if (!(t->lane_mask & lane_mask))
-+ continue;
-+
-+ if (t->in_layout)
-+ writel(t->val, base + regs[t->offset]);
-+ else
-+ writel(t->val, base + t->offset);
-+ }
-+}
-+
-+static void qcom_qmp_phy_configure(void __iomem *base,
-+ const unsigned int *regs,
-+ const struct qmp_phy_init_tbl tbl[],
-+ int num)
-+{
-+ qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff);
-+}
-+
-+static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
-+{
-+ struct qcom_qmp *qmp = qphy->qmp;
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *serdes = qphy->serdes;
-+ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-+ const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
-+ int serdes_tbl_num = cfg->serdes_tbl_num;
-+ int ret;
-+
-+ qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
-+ if (cfg->serdes_tbl_sec)
-+ qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
-+ cfg->serdes_tbl_num_sec);
-+
-+ if (cfg->type == PHY_TYPE_DP) {
-+ switch (dp_opts->link_rate) {
-+ case 1620:
-+ qcom_qmp_phy_configure(serdes, cfg->regs,
-+ cfg->serdes_tbl_rbr,
-+ cfg->serdes_tbl_rbr_num);
-+ break;
-+ case 2700:
-+ qcom_qmp_phy_configure(serdes, cfg->regs,
-+ cfg->serdes_tbl_hbr,
-+ cfg->serdes_tbl_hbr_num);
-+ break;
-+ case 5400:
-+ qcom_qmp_phy_configure(serdes, cfg->regs,
-+ cfg->serdes_tbl_hbr2,
-+ cfg->serdes_tbl_hbr2_num);
-+ break;
-+ case 8100:
-+ qcom_qmp_phy_configure(serdes, cfg->regs,
-+ cfg->serdes_tbl_hbr3,
-+ cfg->serdes_tbl_hbr3_num);
-+ break;
-+ default:
-+ /* Other link rates aren't supported */
-+ return -EINVAL;
-+ }
-+ }
-+
-+
-+ if (cfg->has_phy_com_ctrl) {
-+ void __iomem *status;
-+ unsigned int mask, val;
-+
-+ qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
-+ qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
-+ SERDES_START | PCS_START);
-+
-+ status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
-+ mask = cfg->mask_com_pcs_ready;
-+
-+ ret = readl_poll_timeout(status, val, (val & mask), 10,
-+ PHY_INIT_COMPLETE_TIMEOUT);
-+ if (ret) {
-+ dev_err(qmp->dev,
-+ "phy common block init timed-out\n");
-+ return ret;
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy)
-+{
-+ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
-+ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
-+ qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+
-+ /* Turn on BIAS current for PHY/PLL */
-+ writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
-+ QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
-+ qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
-+
-+ writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+
-+ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
-+ DP_PHY_PD_CTL_LANE_0_1_PWRDN |
-+ DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
-+ DP_PHY_PD_CTL_DP_CLAMP_EN,
-+ qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+
-+ writel(QSERDES_V3_COM_BIAS_EN |
-+ QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
-+ QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL |
-+ QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
-+ qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
-+
-+ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
-+ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-+ writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
-+ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
-+ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
-+ writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
-+ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
-+ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
-+ writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
-+ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
-+ qphy->dp_aux_cfg = 0;
-+
-+ writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
-+ PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
-+ PHY_AUX_REQ_ERR_MASK,
-+ qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
-+}
-+
-+static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = {
-+ { 0x00, 0x0c, 0x15, 0x1a },
-+ { 0x02, 0x0e, 0x16, 0xff },
-+ { 0x02, 0x11, 0xff, 0xff },
-+ { 0x04, 0xff, 0xff, 0xff }
-+};
-+
-+static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = {
-+ { 0x02, 0x12, 0x16, 0x1a },
-+ { 0x09, 0x19, 0x1f, 0xff },
-+ { 0x10, 0x1f, 0xff, 0xff },
-+ { 0x1f, 0xff, 0xff, 0xff }
-+};
-+
-+static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = {
-+ { 0x00, 0x0c, 0x14, 0x19 },
-+ { 0x00, 0x0b, 0x12, 0xff },
-+ { 0x00, 0x0b, 0xff, 0xff },
-+ { 0x04, 0xff, 0xff, 0xff }
-+};
-+
-+static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = {
-+ { 0x08, 0x0f, 0x16, 0x1f },
-+ { 0x11, 0x1e, 0x1f, 0xff },
-+ { 0x19, 0x1f, 0xff, 0xff },
-+ { 0x1f, 0xff, 0xff, 0xff }
-+};
-+
-+static int qcom_qmp_phy_configure_dp_swing(struct qmp_phy *qphy,
-+ unsigned int drv_lvl_reg, unsigned int emp_post_reg)
-+{
-+ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-+ unsigned int v_level = 0, p_level = 0;
-+ u8 voltage_swing_cfg, pre_emphasis_cfg;
-+ int i;
-+
-+ for (i = 0; i < dp_opts->lanes; i++) {
-+ v_level = max(v_level, dp_opts->voltage[i]);
-+ p_level = max(p_level, dp_opts->pre[i]);
-+ }
-+
-+ if (dp_opts->link_rate <= 2700) {
-+ voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level];
-+ pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level];
-+ } else {
-+ voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr3_hbr2[v_level][p_level];
-+ pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr3_hbr2[v_level][p_level];
-+ }
-+
-+ /* TODO: Move check to config check */
-+ if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF)
-+ return -EINVAL;
-+
-+ /* Enable MUX to use Cursor values from these registers */
-+ voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
-+ pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
-+
-+ writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg);
-+ writel(pre_emphasis_cfg, qphy->tx + emp_post_reg);
-+ writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg);
-+ writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg);
-+
-+ return 0;
-+}
-+
-+static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy)
-+{
-+ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-+ u32 bias_en, drvr_en;
-+
-+ if (qcom_qmp_phy_configure_dp_swing(qphy,
-+ QSERDES_V3_TX_TX_DRV_LVL,
-+ QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0)
-+ return;
-+
-+ if (dp_opts->lanes == 1) {
-+ bias_en = 0x3e;
-+ drvr_en = 0x13;
-+ } else {
-+ bias_en = 0x3f;
-+ drvr_en = 0x10;
-+ }
-+
-+ writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN);
-+ writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
-+ writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN);
-+ writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
-+}
-+
-+static bool qcom_qmp_phy_configure_dp_mode(struct qmp_phy *qphy)
-+{
-+ u32 val;
-+ bool reverse = false;
-+
-+ val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
-+ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN;
-+
-+ /*
-+ * TODO: Assume orientation is CC1 for now and two lanes, need to
-+ * use type-c connector to understand orientation and lanes.
-+ *
-+ * Otherwise val changes to be like below if this code understood
-+ * the orientation of the type-c cable.
-+ *
-+ * if (lane_cnt == 4 || orientation == ORIENTATION_CC2)
-+ * val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN;
-+ * if (lane_cnt == 4 || orientation == ORIENTATION_CC1)
-+ * val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
-+ * if (orientation == ORIENTATION_CC2)
-+ * writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
-+ */
-+ val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
-+ writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+
-+ writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE);
-+
-+ return reverse;
-+}
-+
-+static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy)
-+{
-+ const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
-+ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-+ u32 phy_vco_div, status;
-+ unsigned long pixel_freq;
-+
-+ qcom_qmp_phy_configure_dp_mode(qphy);
-+
-+ writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
-+ writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
-+
-+ switch (dp_opts->link_rate) {
-+ case 1620:
-+ phy_vco_div = 0x1;
-+ pixel_freq = 1620000000UL / 2;
-+ break;
-+ case 2700:
-+ phy_vco_div = 0x1;
-+ pixel_freq = 2700000000UL / 2;
-+ break;
-+ case 5400:
-+ phy_vco_div = 0x2;
-+ pixel_freq = 5400000000UL / 4;
-+ break;
-+ case 8100:
-+ phy_vco_div = 0x0;
-+ pixel_freq = 8100000000UL / 6;
-+ break;
-+ default:
-+ /* Other link rates aren't supported */
-+ return -EINVAL;
-+ }
-+ writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV);
-+
-+ clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
-+ clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
-+
-+ writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
-+ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL);
-+
-+ if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS,
-+ status,
-+ ((status & BIT(0)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
-+ status,
-+ ((status & BIT(1)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ udelay(2000);
-+ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
-+ status,
-+ ((status & BIT(1)) > 0),
-+ 500,
-+ 10000);
-+}
-+
-+/*
-+ * We need to calibrate the aux setting here as many times
-+ * as the caller tries
-+ */
-+static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy)
-+{
-+ static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d };
-+ u8 val;
-+
-+ qphy->dp_aux_cfg++;
-+ qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
-+ val = cfg1_settings[qphy->dp_aux_cfg];
-+
-+ writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-+
-+ return 0;
-+}
-+
-+static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy)
-+{
-+ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
-+ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
-+ qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+
-+ /* Turn on BIAS current for PHY/PLL */
-+ writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN);
-+
-+ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
-+ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-+ writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
-+ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
-+ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
-+ writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
-+ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
-+ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
-+ writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
-+ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
-+ qphy->dp_aux_cfg = 0;
-+
-+ writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
-+ PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
-+ PHY_AUX_REQ_ERR_MASK,
-+ qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
-+}
-+
-+static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy)
-+{
-+ /* Program default values before writing proper values */
-+ writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
-+ writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
-+
-+ writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
-+ writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
-+
-+ qcom_qmp_phy_configure_dp_swing(qphy,
-+ QSERDES_V4_TX_TX_DRV_LVL,
-+ QSERDES_V4_TX_TX_EMP_POST1_LVL);
-+}
-+
-+static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy)
-+{
-+ const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
-+ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-+ u32 phy_vco_div, status;
-+ unsigned long pixel_freq;
-+ u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
-+ bool reverse;
-+
-+ writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1);
-+
-+ reverse = qcom_qmp_phy_configure_dp_mode(qphy);
-+
-+ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-+ writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
-+
-+ writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL);
-+ writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL);
-+
-+ switch (dp_opts->link_rate) {
-+ case 1620:
-+ phy_vco_div = 0x1;
-+ pixel_freq = 1620000000UL / 2;
-+ break;
-+ case 2700:
-+ phy_vco_div = 0x1;
-+ pixel_freq = 2700000000UL / 2;
-+ break;
-+ case 5400:
-+ phy_vco_div = 0x2;
-+ pixel_freq = 5400000000UL / 4;
-+ break;
-+ case 8100:
-+ phy_vco_div = 0x0;
-+ pixel_freq = 8100000000UL / 6;
-+ break;
-+ default:
-+ /* Other link rates aren't supported */
-+ return -EINVAL;
-+ }
-+ writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV);
-+
-+ clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
-+ clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
-+
-+ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL);
-+
-+ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS,
-+ status,
-+ ((status & BIT(0)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
-+ status,
-+ ((status & BIT(0)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
-+ status,
-+ ((status & BIT(1)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
-+ status,
-+ ((status & BIT(0)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
-+ status,
-+ ((status & BIT(1)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ /*
-+ * At least for 7nm DP PHY this has to be done after enabling link
-+ * clock.
-+ */
-+
-+ if (dp_opts->lanes == 1) {
-+ bias0_en = reverse ? 0x3e : 0x15;
-+ bias1_en = reverse ? 0x15 : 0x3e;
-+ drvr0_en = reverse ? 0x13 : 0x10;
-+ drvr1_en = reverse ? 0x10 : 0x13;
-+ } else if (dp_opts->lanes == 2) {
-+ bias0_en = reverse ? 0x3f : 0x15;
-+ bias1_en = reverse ? 0x15 : 0x3f;
-+ drvr0_en = 0x10;
-+ drvr1_en = 0x10;
-+ } else {
-+ bias0_en = 0x3f;
-+ bias1_en = 0x3f;
-+ drvr0_en = 0x10;
-+ drvr1_en = 0x10;
-+ }
-+
-+ writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN);
-+ writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
-+ writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN);
-+ writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
-+
-+ writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ udelay(2000);
-+ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
-+ status,
-+ ((status & BIT(1)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV);
-+ writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV);
-+
-+ writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
-+ writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
-+
-+ writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
-+ writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
-+
-+ return 0;
-+}
-+
-+/*
-+ * We need to calibrate the aux setting here as many times
-+ * as the caller tries
-+ */
-+static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy)
-+{
-+ static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d };
-+ u8 val;
-+
-+ qphy->dp_aux_cfg++;
-+ qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
-+ val = cfg1_settings[qphy->dp_aux_cfg];
-+
-+ writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
-+{
-+ const struct phy_configure_opts_dp *dp_opts = &opts->dp;
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+
-+ memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts));
-+ if (qphy->dp_opts.set_voltages) {
-+ cfg->configure_dp_tx(qphy);
-+ qphy->dp_opts.set_voltages = 0;
-+ }
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_dp_phy_calibrate(struct phy *phy)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+
-+ if (cfg->calibrate_dp_phy)
-+ return cfg->calibrate_dp_phy(qphy);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
-+{
-+ struct qcom_qmp *qmp = qphy->qmp;
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *serdes = qphy->serdes;
-+ void __iomem *pcs = qphy->pcs;
-+ void __iomem *dp_com = qmp->dp_com;
-+ int ret, i;
-+
-+ mutex_lock(&qmp->phy_mutex);
-+ if (qmp->init_count++) {
-+ mutex_unlock(&qmp->phy_mutex);
-+ return 0;
-+ }
-+
-+ /* turn on regulator supplies */
-+ ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
-+ if (ret) {
-+ dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
-+ goto err_unlock;
-+ }
-+
-+ for (i = 0; i < cfg->num_resets; i++) {
-+ ret = reset_control_assert(qmp->resets[i]);
-+ if (ret) {
-+ dev_err(qmp->dev, "%s reset assert failed\n",
-+ cfg->reset_list[i]);
-+ goto err_disable_regulators;
-+ }
-+ }
-+
-+ for (i = cfg->num_resets - 1; i >= 0; i--) {
-+ ret = reset_control_deassert(qmp->resets[i]);
-+ if (ret) {
-+ dev_err(qmp->dev, "%s reset deassert failed\n",
-+ qphy->cfg->reset_list[i]);
-+ goto err_assert_reset;
-+ }
-+ }
-+
-+ ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
-+ if (ret)
-+ goto err_assert_reset;
-+
-+ if (cfg->has_phy_dp_com_ctrl) {
-+ qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
-+ SW_PWRDN);
-+ /* override hardware control for reset of qmp phy */
-+ qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
-+ SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
-+ SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
-+
-+ /* Default type-c orientation, i.e CC1 */
-+ qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02);
-+
-+ qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
-+ USB3_MODE | DP_MODE);
-+
-+ /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
-+ qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
-+ SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
-+ SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
-+
-+ qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
-+ qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
-+ }
-+
-+ if (cfg->has_phy_com_ctrl) {
-+ qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
-+ SW_PWRDN);
-+ } else {
-+ if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
-+ qphy_setbits(pcs,
-+ cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
-+ cfg->pwrdn_ctrl);
-+ else
-+ qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
-+ cfg->pwrdn_ctrl);
-+ }
-+
-+ mutex_unlock(&qmp->phy_mutex);
-+
-+ return 0;
-+
-+err_assert_reset:
-+ while (++i < cfg->num_resets)
-+ reset_control_assert(qmp->resets[i]);
-+err_disable_regulators:
-+ regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
-+err_unlock:
-+ mutex_unlock(&qmp->phy_mutex);
-+
-+ return ret;
-+}
-+
-+static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy)
-+{
-+ struct qcom_qmp *qmp = qphy->qmp;
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *serdes = qphy->serdes;
-+ int i = cfg->num_resets;
-+
-+ mutex_lock(&qmp->phy_mutex);
-+ if (--qmp->init_count) {
-+ mutex_unlock(&qmp->phy_mutex);
-+ return 0;
-+ }
-+
-+ reset_control_assert(qmp->ufs_reset);
-+ if (cfg->has_phy_com_ctrl) {
-+ qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
-+ SERDES_START | PCS_START);
-+ qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
-+ SW_RESET);
-+ qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
-+ SW_PWRDN);
-+ }
-+
-+ while (--i >= 0)
-+ reset_control_assert(qmp->resets[i]);
-+
-+ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
-+
-+ regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
-+
-+ mutex_unlock(&qmp->phy_mutex);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_init(struct phy *phy)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ struct qcom_qmp *qmp = qphy->qmp;
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ int ret;
-+ dev_vdbg(qmp->dev, "Initializing QMP phy\n");
-+
-+ if (cfg->no_pcs_sw_reset) {
-+ /*
-+ * Get UFS reset, which is delayed until now to avoid a
-+ * circular dependency where UFS needs its PHY, but the PHY
-+ * needs this UFS reset.
-+ */
-+ if (!qmp->ufs_reset) {
-+ qmp->ufs_reset =
-+ devm_reset_control_get_exclusive(qmp->dev,
-+ "ufsphy");
-+
-+ if (IS_ERR(qmp->ufs_reset)) {
-+ ret = PTR_ERR(qmp->ufs_reset);
-+ dev_err(qmp->dev,
-+ "failed to get UFS reset: %d\n",
-+ ret);
-+
-+ qmp->ufs_reset = NULL;
-+ return ret;
-+ }
-+ }
-+
-+ ret = reset_control_assert(qmp->ufs_reset);
-+ if (ret)
-+ return ret;
-+ }
-+
-+ ret = qcom_qmp_phy_com_init(qphy);
-+ if (ret)
-+ return ret;
-+
-+ if (cfg->type == PHY_TYPE_DP)
-+ cfg->dp_aux_init(qphy);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_power_on(struct phy *phy)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ struct qcom_qmp *qmp = qphy->qmp;
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *tx = qphy->tx;
-+ void __iomem *rx = qphy->rx;
-+ void __iomem *pcs = qphy->pcs;
-+ void __iomem *pcs_misc = qphy->pcs_misc;
-+ void __iomem *status;
-+ unsigned int mask, val, ready;
-+ int ret;
-+
-+ qcom_qmp_phy_serdes_init(qphy);
-+
-+ if (cfg->has_lane_rst) {
-+ ret = reset_control_deassert(qphy->lane_rst);
-+ if (ret) {
-+ dev_err(qmp->dev, "lane%d reset deassert failed\n",
-+ qphy->index);
-+ return ret;
-+ }
-+ }
-+
-+ ret = clk_prepare_enable(qphy->pipe_clk);
-+ if (ret) {
-+ dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
-+ goto err_reset_lane;
-+ }
-+
-+ /* Tx, Rx, and PCS configurations */
-+ qcom_qmp_phy_configure_lane(tx, cfg->regs,
-+ cfg->tx_tbl, cfg->tx_tbl_num, 1);
-+ if (cfg->tx_tbl_sec)
-+ qcom_qmp_phy_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
-+ cfg->tx_tbl_num_sec, 1);
-+
-+ /* Configuration for other LANE for USB-DP combo PHY */
-+ if (cfg->is_dual_lane_phy) {
-+ qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
-+ cfg->tx_tbl, cfg->tx_tbl_num, 2);
-+ if (cfg->tx_tbl_sec)
-+ qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
-+ cfg->tx_tbl_sec,
-+ cfg->tx_tbl_num_sec, 2);
-+ }
-+
-+ /* Configure special DP tx tunings */
-+ if (cfg->type == PHY_TYPE_DP)
-+ cfg->configure_dp_tx(qphy);
-+
-+ qcom_qmp_phy_configure_lane(rx, cfg->regs,
-+ cfg->rx_tbl, cfg->rx_tbl_num, 1);
-+ if (cfg->rx_tbl_sec)
-+ qcom_qmp_phy_configure_lane(rx, cfg->regs,
-+ cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1);
-+
-+ if (cfg->is_dual_lane_phy) {
-+ qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
-+ cfg->rx_tbl, cfg->rx_tbl_num, 2);
-+ if (cfg->rx_tbl_sec)
-+ qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
-+ cfg->rx_tbl_sec,
-+ cfg->rx_tbl_num_sec, 2);
-+ }
-+
-+ /* Configure link rate, swing, etc. */
-+ if (cfg->type == PHY_TYPE_DP) {
-+ cfg->configure_dp_phy(qphy);
-+ } else {
-+ qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
-+ if (cfg->pcs_tbl_sec)
-+ qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
-+ cfg->pcs_tbl_num_sec);
-+ }
-+
-+ ret = reset_control_deassert(qmp->ufs_reset);
-+ if (ret)
-+ goto err_disable_pipe_clk;
-+
-+ qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
-+ cfg->pcs_misc_tbl_num);
-+ if (cfg->pcs_misc_tbl_sec)
-+ qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
-+ cfg->pcs_misc_tbl_num_sec);
-+
-+ /*
-+ * Pull out PHY from POWER DOWN state.
-+ * This is active low enable signal to power-down PHY.
-+ */
-+ if(cfg->type == PHY_TYPE_PCIE)
-+ qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
-+
-+ if (cfg->has_pwrdn_delay)
-+ usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
-+
-+ if (cfg->type != PHY_TYPE_DP) {
-+ /* Pull PHY out of reset state */
-+ if (!cfg->no_pcs_sw_reset)
-+ qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
-+ /* start SerDes and Phy-Coding-Sublayer */
-+ qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
-+
-+ if (cfg->type == PHY_TYPE_UFS) {
-+ status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
-+ mask = PCS_READY;
-+ ready = PCS_READY;
-+ } else {
-+ status = pcs + cfg->regs[QPHY_PCS_STATUS];
-+ mask = cfg->phy_status;
-+ ready = 0;
-+ }
-+
-+ ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
-+ PHY_INIT_COMPLETE_TIMEOUT);
-+ if (ret) {
-+ dev_err(qmp->dev, "phy initialization timed-out\n");
-+ goto err_disable_pipe_clk;
-+ }
-+ }
-+ return 0;
-+
-+err_disable_pipe_clk:
-+ clk_disable_unprepare(qphy->pipe_clk);
-+err_reset_lane:
-+ if (cfg->has_lane_rst)
-+ reset_control_assert(qphy->lane_rst);
-+
-+ return ret;
-+}
-+
-+static int qcom_qmp_phy_power_off(struct phy *phy)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+
-+ clk_disable_unprepare(qphy->pipe_clk);
-+
-+ if (cfg->type == PHY_TYPE_DP) {
-+ /* Assert DP PHY power down */
-+ writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+ } else {
-+ /* PHY reset */
-+ if (!cfg->no_pcs_sw_reset)
-+ qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
-+
-+ /* stop SerDes and Phy-Coding-Sublayer */
-+ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
-+
-+ /* Put PHY into POWER DOWN state: active low */
-+ if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
-+ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
-+ cfg->pwrdn_ctrl);
-+ } else {
-+ qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
-+ cfg->pwrdn_ctrl);
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_exit(struct phy *phy)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+
-+ if (cfg->has_lane_rst)
-+ reset_control_assert(qphy->lane_rst);
-+
-+ qcom_qmp_phy_com_exit(qphy);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_enable(struct phy *phy)
-+{
-+ int ret;
-+
-+ ret = qcom_qmp_phy_init(phy);
-+ if (ret)
-+ return ret;
-+
-+ ret = qcom_qmp_phy_power_on(phy);
-+ if (ret)
-+ qcom_qmp_phy_exit(phy);
-+
-+ return ret;
-+}
-+
-+static int qcom_qmp_phy_disable(struct phy *phy)
-+{
-+ int ret;
-+
-+ ret = qcom_qmp_phy_power_off(phy);
-+ if (ret)
-+ return ret;
-+ return qcom_qmp_phy_exit(phy);
-+}
-+
-+static int qcom_qmp_phy_set_mode(struct phy *phy,
-+ enum phy_mode mode, int submode)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+
-+ qphy->mode = mode;
-+
-+ return 0;
-+}
-+
-+static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
-+{
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *pcs = qphy->pcs;
-+ void __iomem *pcs_misc = qphy->pcs_misc;
-+ u32 intr_mask;
-+
-+ if (qphy->mode == PHY_MODE_USB_HOST_SS ||
-+ qphy->mode == PHY_MODE_USB_DEVICE_SS)
-+ intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
-+ else
-+ intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
-+
-+ /* Clear any pending interrupts status */
-+ qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
-+ /* Writing 1 followed by 0 clears the interrupt */
-+ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
-+
-+ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
-+ ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
-+
-+ /* Enable required PHY autonomous mode interrupts */
-+ qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
-+
-+ /* Enable i/o clamp_n for autonomous mode */
-+ if (pcs_misc)
-+ qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
-+}
-+
-+static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
-+{
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *pcs = qphy->pcs;
-+ void __iomem *pcs_misc = qphy->pcs_misc;
-+
-+ /* Disable i/o clamp_n on resume for normal mode */
-+ if (pcs_misc)
-+ qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
-+
-+ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
-+ ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
-+
-+ qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
-+ /* Writing 1 followed by 0 clears the interrupt */
-+ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
-+}
-+
-+static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ struct qmp_phy *qphy = qmp->phys[0];
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+
-+ dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode);
-+
-+ /* Supported only for USB3 PHY and luckily USB3 is the first phy */
-+ if (cfg->type != PHY_TYPE_USB3)
-+ return 0;
-+
-+ if (!qmp->init_count) {
-+ dev_vdbg(dev, "PHY not initialized, bailing out\n");
-+ return 0;
-+ }
-+
-+ qcom_qmp_phy_enable_autonomous_mode(qphy);
-+
-+ clk_disable_unprepare(qphy->pipe_clk);
-+ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
-+
-+ return 0;
-+}
-+
-+static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ struct qmp_phy *qphy = qmp->phys[0];
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ int ret = 0;
-+
-+ dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode);
-+
-+ /* Supported only for USB3 PHY and luckily USB3 is the first phy */
-+ if (cfg->type != PHY_TYPE_USB3)
-+ return 0;
-+
-+ if (!qmp->init_count) {
-+ dev_vdbg(dev, "PHY not initialized, bailing out\n");
-+ return 0;
-+ }
-+
-+ ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
-+ if (ret)
-+ return ret;
-+
-+ ret = clk_prepare_enable(qphy->pipe_clk);
-+ if (ret) {
-+ dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
-+ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
-+ return ret;
-+ }
-+
-+ qcom_qmp_phy_disable_autonomous_mode(qphy);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ int num = cfg->num_vregs;
-+ int i;
-+
-+ qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
-+ if (!qmp->vregs)
-+ return -ENOMEM;
-+
-+ for (i = 0; i < num; i++)
-+ qmp->vregs[i].supply = cfg->vreg_list[i];
-+
-+ return devm_regulator_bulk_get(dev, num, qmp->vregs);
-+}
-+
-+static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ int i;
-+
-+ qmp->resets = devm_kcalloc(dev, cfg->num_resets,
-+ sizeof(*qmp->resets), GFP_KERNEL);
-+ if (!qmp->resets)
-+ return -ENOMEM;
-+
-+ for (i = 0; i < cfg->num_resets; i++) {
-+ struct reset_control *rst;
-+ const char *name = cfg->reset_list[i];
-+
-+ rst = devm_reset_control_get_exclusive(dev, name);
-+ if (IS_ERR(rst)) {
-+ dev_err(dev, "failed to get %s reset\n", name);
-+ return PTR_ERR(rst);
-+ }
-+ qmp->resets[i] = rst;
-+ }
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ int num = cfg->num_clks;
-+ int i;
-+
-+ qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
-+ if (!qmp->clks)
-+ return -ENOMEM;
-+
-+ for (i = 0; i < num; i++)
-+ qmp->clks[i].id = cfg->clk_list[i];
-+
-+ return devm_clk_bulk_get(dev, num, qmp->clks);
-+}
-+
-+static void phy_clk_release_provider(void *res)
-+{
-+ of_clk_del_provider(res);
-+}
-+
-+/*
-+ * Register a fixed rate pipe clock.
-+ *
-+ * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
-+ * controls it. The <s>_pipe_clk coming out of the GCC is requested
-+ * by the PHY driver for its operations.
-+ * We register the <s>_pipe_clksrc here. The gcc driver takes care
-+ * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
-+ * Below picture shows this relationship.
-+ *
-+ * +---------------+
-+ * | PHY block |<<---------------------------------------+
-+ * | | |
-+ * | +-------+ | +-----+ |
-+ * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
-+ * clk | +-------+ | +-----+
-+ * +---------------+
-+ */
-+static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
-+{
-+ struct clk_fixed_rate *fixed;
-+ struct clk_init_data init = { };
-+ int ret;
-+
-+ ret = of_property_read_string(np, "clock-output-names", &init.name);
-+ if (ret) {
-+ dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
-+ return ret;
-+ }
-+
-+ fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
-+ if (!fixed)
-+ return -ENOMEM;
-+
-+ init.ops = &clk_fixed_rate_ops;
-+
-+ /* controllers using QMP phys use 125MHz pipe clock interface */
-+ fixed->fixed_rate = 125000000;
-+ fixed->hw.init = &init;
-+
-+ ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
-+ if (ret)
-+ return ret;
-+
-+ ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
-+ if (ret)
-+ return ret;
-+
-+ /*
-+ * Roll a devm action because the clock provider is the child node, but
-+ * the child node is not actually a device.
-+ */
-+ return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
-+}
-+
-+/*
-+ * Display Port PLL driver block diagram for branch clocks
-+ *
-+ * +------------------------------+
-+ * | DP_VCO_CLK |
-+ * | |
-+ * | +-------------------+ |
-+ * | | (DP PLL/VCO) | |
-+ * | +---------+---------+ |
-+ * | v |
-+ * | +----------+-----------+ |
-+ * | | hsclk_divsel_clk_src | |
-+ * | +----------+-----------+ |
-+ * +------------------------------+
-+ * |
-+ * +---------<---------v------------>----------+
-+ * | |
-+ * +--------v----------------+ |
-+ * | dp_phy_pll_link_clk | |
-+ * | link_clk | |
-+ * +--------+----------------+ |
-+ * | |
-+ * | |
-+ * v v
-+ * Input to DISPCC block |
-+ * for link clk, crypto clk |
-+ * and interface clock |
-+ * |
-+ * |
-+ * +--------<------------+-----------------+---<---+
-+ * | | |
-+ * +----v---------+ +--------v-----+ +--------v------+
-+ * | vco_divided | | vco_divided | | vco_divided |
-+ * | _clk_src | | _clk_src | | _clk_src |
-+ * | | | | | |
-+ * |divsel_six | | divsel_two | | divsel_four |
-+ * +-------+------+ +-----+--------+ +--------+------+
-+ * | | |
-+ * v---->----------v-------------<------v
-+ * |
-+ * +----------+-----------------+
-+ * | dp_phy_pll_vco_div_clk |
-+ * +---------+------------------+
-+ * |
-+ * v
-+ * Input to DISPCC block
-+ * for DP pixel clock
-+ *
-+ */
-+static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw,
-+ struct clk_rate_request *req)
-+{
-+ switch (req->rate) {
-+ case 1620000000UL / 2:
-+ case 2700000000UL / 2:
-+ /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */
-+ return 0;
-+ default:
-+ return -EINVAL;
-+ }
-+}
-+
-+static unsigned long
-+qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
-+{
-+ const struct qmp_phy_dp_clks *dp_clks;
-+ const struct qmp_phy *qphy;
-+ const struct phy_configure_opts_dp *dp_opts;
-+
-+ dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw);
-+ qphy = dp_clks->qphy;
-+ dp_opts = &qphy->dp_opts;
-+
-+ switch (dp_opts->link_rate) {
-+ case 1620:
-+ return 1620000000UL / 2;
-+ case 2700:
-+ return 2700000000UL / 2;
-+ case 5400:
-+ return 5400000000UL / 4;
-+ case 8100:
-+ return 8100000000UL / 6;
-+ default:
-+ return 0;
-+ }
-+}
-+
-+static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = {
-+ .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate,
-+ .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate,
-+};
-+
-+static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw,
-+ struct clk_rate_request *req)
-+{
-+ switch (req->rate) {
-+ case 162000000:
-+ case 270000000:
-+ case 540000000:
-+ case 810000000:
-+ return 0;
-+ default:
-+ return -EINVAL;
-+ }
-+}
-+
-+static unsigned long
-+qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
-+{
-+ const struct qmp_phy_dp_clks *dp_clks;
-+ const struct qmp_phy *qphy;
-+ const struct phy_configure_opts_dp *dp_opts;
-+
-+ dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw);
-+ qphy = dp_clks->qphy;
-+ dp_opts = &qphy->dp_opts;
-+
-+ switch (dp_opts->link_rate) {
-+ case 1620:
-+ case 2700:
-+ case 5400:
-+ case 8100:
-+ return dp_opts->link_rate * 100000;
-+ default:
-+ return 0;
-+ }
-+}
-+
-+static const struct clk_ops qcom_qmp_dp_link_clk_ops = {
-+ .determine_rate = qcom_qmp_dp_link_clk_determine_rate,
-+ .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate,
-+};
-+
-+static struct clk_hw *
-+qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data)
-+{
-+ struct qmp_phy_dp_clks *dp_clks = data;
-+ unsigned int idx = clkspec->args[0];
-+
-+ if (idx >= 2) {
-+ pr_err("%s: invalid index %u\n", __func__, idx);
-+ return ERR_PTR(-EINVAL);
-+ }
-+
-+ if (idx == 0)
-+ return &dp_clks->dp_link_hw;
-+
-+ return &dp_clks->dp_pixel_hw;
-+}
-+
-+static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy,
-+ struct device_node *np)
-+{
-+ struct clk_init_data init = { };
-+ struct qmp_phy_dp_clks *dp_clks;
-+ char name[64];
-+ int ret;
-+
-+ dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL);
-+ if (!dp_clks)
-+ return -ENOMEM;
-+
-+ dp_clks->qphy = qphy;
-+ qphy->dp_clks = dp_clks;
-+
-+ snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev));
-+ init.ops = &qcom_qmp_dp_link_clk_ops;
-+ init.name = name;
-+ dp_clks->dp_link_hw.init = &init;
-+ ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw);
-+ if (ret)
-+ return ret;
-+
-+ snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev));
-+ init.ops = &qcom_qmp_dp_pixel_clk_ops;
-+ init.name = name;
-+ dp_clks->dp_pixel_hw.init = &init;
-+ ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw);
-+ if (ret)
-+ return ret;
-+
-+ ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks);
-+ if (ret)
-+ return ret;
-+
-+ /*
-+ * Roll a devm action because the clock provider is the child node, but
-+ * the child node is not actually a device.
-+ */
-+ return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
-+}
-+
-+static const struct phy_ops qcom_qmp_phy_gen_ops = {
-+ .init = qcom_qmp_phy_enable,
-+ .exit = qcom_qmp_phy_disable,
-+ .set_mode = qcom_qmp_phy_set_mode,
-+ .owner = THIS_MODULE,
-+};
-+
-+static const struct phy_ops qcom_qmp_phy_dp_ops = {
-+ .init = qcom_qmp_phy_init,
-+ .configure = qcom_qmp_dp_phy_configure,
-+ .power_on = qcom_qmp_phy_power_on,
-+ .calibrate = qcom_qmp_dp_phy_calibrate,
-+ .power_off = qcom_qmp_phy_power_off,
-+ .exit = qcom_qmp_phy_exit,
-+ .set_mode = qcom_qmp_phy_set_mode,
-+ .owner = THIS_MODULE,
-+};
-+
-+static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
-+ .power_on = qcom_qmp_phy_enable,
-+ .power_off = qcom_qmp_phy_disable,
-+ .set_mode = qcom_qmp_phy_set_mode,
-+ .owner = THIS_MODULE,
-+};
-+
-+static void qcom_qmp_reset_control_put(void *data)
-+{
-+ reset_control_put(data);
-+}
-+
-+static
-+int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
-+ void __iomem *serdes, const struct qmp_phy_cfg *cfg)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ struct phy *generic_phy;
-+ struct qmp_phy *qphy;
-+ const struct phy_ops *ops;
-+ char prop_name[MAX_PROP_NAME];
-+ int ret;
-+
-+ qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
-+ if (!qphy)
-+ return -ENOMEM;
-+
-+ qphy->cfg = cfg;
-+ qphy->serdes = serdes;
-+ /*
-+ * Get memory resources for each phy lane:
-+ * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
-+ * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
-+ * For single lane PHYs: pcs_misc (optional) -> 3.
-+ */
-+ qphy->tx = of_iomap(np, 0);
-+ if (!qphy->tx)
-+ return -ENOMEM;
-+
-+ qphy->rx = of_iomap(np, 1);
-+ if (!qphy->rx)
-+ return -ENOMEM;
-+
-+ qphy->pcs = of_iomap(np, 2);
-+ if (!qphy->pcs)
-+ return -ENOMEM;
-+
-+ /*
-+ * If this is a dual-lane PHY, then there should be registers for the
-+ * second lane. Some old device trees did not specify this, so fall
-+ * back to old legacy behavior of assuming they can be reached at an
-+ * offset from the first lane.
-+ */
-+ if (cfg->is_dual_lane_phy) {
-+ qphy->tx2 = of_iomap(np, 3);
-+ qphy->rx2 = of_iomap(np, 4);
-+ if (!qphy->tx2 || !qphy->rx2) {
-+ dev_warn(dev,
-+ "Underspecified device tree, falling back to legacy register regions\n");
-+
-+ /* In the old version, pcs_misc is at index 3. */
-+ qphy->pcs_misc = qphy->tx2;
-+ qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE;
-+ qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
-+
-+ } else {
-+ qphy->pcs_misc = of_iomap(np, 5);
-+ }
-+
-+ } else {
-+ qphy->pcs_misc = of_iomap(np, 3);
-+ }
-+
-+ if (!qphy->pcs_misc)
-+ dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
-+
-+ /*
-+ * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3
-+ * based phys, so they essentially have pipe clock. So,
-+ * we return error in case phy is USB3 or PIPE type.
-+ * Otherwise, we initialize pipe clock to NULL for
-+ * all phys that don't need this.
-+ */
-+ snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
-+ qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name);
-+ if (IS_ERR(qphy->pipe_clk)) {
-+ if (cfg->type == PHY_TYPE_PCIE ||
-+ cfg->type == PHY_TYPE_USB3) {
-+ ret = PTR_ERR(qphy->pipe_clk);
-+ if (ret != -EPROBE_DEFER)
-+ dev_err(dev,
-+ "failed to get lane%d pipe_clk, %d\n",
-+ id, ret);
-+ return ret;
-+ }
-+ qphy->pipe_clk = NULL;
-+ }
-+
-+ /* Get lane reset, if any */
-+ if (cfg->has_lane_rst) {
-+ snprintf(prop_name, sizeof(prop_name), "lane%d", id);
-+ qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name);
-+ if (IS_ERR(qphy->lane_rst)) {
-+ dev_err(dev, "failed to get lane%d reset\n", id);
-+ return PTR_ERR(qphy->lane_rst);
-+ }
-+ ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put,
-+ qphy->lane_rst);
-+ if (ret)
-+ return ret;
-+ }
-+
-+ if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE)
-+ ops = &qcom_qmp_pcie_ufs_ops;
-+ else if (cfg->type == PHY_TYPE_DP)
-+ ops = &qcom_qmp_phy_dp_ops;
-+ else
-+ ops = &qcom_qmp_phy_gen_ops;
-+
-+ generic_phy = devm_phy_create(dev, np, ops);
-+ if (IS_ERR(generic_phy)) {
-+ ret = PTR_ERR(generic_phy);
-+ dev_err(dev, "failed to create qphy %d\n", ret);
-+ return ret;
-+ }
-+
-+ qphy->phy = generic_phy;
-+ qphy->index = id;
-+ qphy->qmp = qmp;
-+ qmp->phys[id] = qphy;
-+ phy_set_drvdata(generic_phy, qphy);
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
-+ {
-+ .compatible = "qcom,ipq8074-qmp-usb3-phy",
-+ .data = &ipq8074_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,msm8996-qmp-pcie-phy",
-+ .data = &msm8996_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,msm8996-qmp-ufs-phy",
-+ .data = &msm8996_ufs_cfg,
-+ }, {
-+ .compatible = "qcom,msm8996-qmp-usb3-phy",
-+ .data = &msm8996_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,msm8998-qmp-pcie-phy",
-+ .data = &msm8998_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,msm8998-qmp-ufs-phy",
-+ .data = &sdm845_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,ipq8074-qmp-pcie-phy",
-+ .data = &ipq8074_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,ipq6018-qmp-pcie-phy",
-+ .data = &ipq6018_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,ipq6018-qmp-usb3-phy",
-+ .data = &ipq8074_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sc7180-qmp-usb3-phy",
-+ .data = &sc7180_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
-+ /* It's a combo phy */
-+ }, {
-+ .compatible = "qcom,sc8180x-qmp-pcie-phy",
-+ .data = &sc8180x_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sc8180x-qmp-ufs-phy",
-+ .data = &sm8150_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sc8280xp-qmp-ufs-phy",
-+ .data = &sm8350_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sc8180x-qmp-usb3-phy",
-+ .data = &sm8150_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
-+ /* It's a combo phy */
-+ }, {
-+ .compatible = "qcom,sdm845-qhp-pcie-phy",
-+ .data = &sdm845_qhp_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sdm845-qmp-pcie-phy",
-+ .data = &sdm845_qmp_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sdm845-qmp-usb3-phy",
-+ .data = &qmp_v3_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
-+ .data = &qmp_v3_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sdm845-qmp-ufs-phy",
-+ .data = &sdm845_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,msm8998-qmp-usb3-phy",
-+ .data = &msm8998_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sm6115-qmp-ufs-phy",
-+ .data = &sm6115_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm6350-qmp-ufs-phy",
-+ .data = &sdm845_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8150-qmp-ufs-phy",
-+ .data = &sm8150_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-ufs-phy",
-+ .data = &sm8150_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8150-qmp-usb3-phy",
-+ .data = &sm8150_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8150-qmp-usb3-uni-phy",
-+ .data = &sm8150_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-usb3-phy",
-+ .data = &sm8250_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
-+ /* It's a combo phy */
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-usb3-uni-phy",
-+ .data = &sm8250_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
-+ .data = &sm8250_qmp_gen3x1_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
-+ .data = &sm8250_qmp_gen3x2_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8350-qmp-ufs-phy",
-+ .data = &sm8350_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
-+ .data = &sm8250_qmp_gen3x2_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sdx55-qmp-pcie-phy",
-+ .data = &sdx55_qmp_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sdx55-qmp-usb3-uni-phy",
-+ .data = &sdx55_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sdx65-qmp-usb3-uni-phy",
-+ .data = &sdx65_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8350-qmp-usb3-phy",
-+ .data = &sm8350_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8350-qmp-usb3-uni-phy",
-+ .data = &sm8350_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
-+ .data = &sm8450_qmp_gen3x1_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
-+ .data = &sm8450_qmp_gen4x2_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8450-qmp-ufs-phy",
-+ .data = &sm8450_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8450-qmp-usb3-phy",
-+ .data = &sm8350_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,qcm2290-qmp-usb3-phy",
-+ .data = &qcm2290_usb3phy_cfg,
-+ },
-+ { },
-+};
-+MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
-+
-+static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = {
-+ {
-+ .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
-+ .data = &sc7180_usb3dpphy_cfg,
-+ },
-+ {
-+ .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
-+ .data = &sm8250_usb3dpphy_cfg,
-+ },
-+ {
-+ .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
-+ .data = &sc8180x_usb3dpphy_cfg,
-+ },
-+ { }
-+};
-+
-+static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
-+ SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
-+ qcom_qmp_phy_runtime_resume, NULL)
-+};
-+
-+static int qcom_qmp_phy_probe(struct platform_device *pdev)
-+{
-+ struct qcom_qmp *qmp;
-+ struct device *dev = &pdev->dev;
-+ struct device_node *child;
-+ struct phy_provider *phy_provider;
-+ void __iomem *serdes;
-+ void __iomem *usb_serdes;
-+ void __iomem *dp_serdes = NULL;
-+ const struct qmp_phy_combo_cfg *combo_cfg = NULL;
-+ const struct qmp_phy_cfg *cfg = NULL;
-+ const struct qmp_phy_cfg *usb_cfg = NULL;
-+ const struct qmp_phy_cfg *dp_cfg = NULL;
-+ int num, id, expected_phys;
-+ int ret;
-+
-+ qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
-+ if (!qmp)
-+ return -ENOMEM;
-+
-+ qmp->dev = dev;
-+ dev_set_drvdata(dev, qmp);
-+
-+ /* Get the specific init parameters of QMP phy */
-+ cfg = of_device_get_match_data(dev);
-+ if (!cfg) {
-+ const struct of_device_id *match;
-+
-+ match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev);
-+ if (!match)
-+ return -EINVAL;
-+
-+ combo_cfg = match->data;
-+ if (!combo_cfg)
-+ return -EINVAL;
-+
-+ usb_cfg = combo_cfg->usb_cfg;
-+ cfg = usb_cfg; /* Setup clks and regulators */
-+ }
-+
-+ /* per PHY serdes; usually located at base address */
-+ usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0);
-+ if (IS_ERR(serdes))
-+ return PTR_ERR(serdes);
-+
-+ /* per PHY dp_com; if PHY has dp_com control block */
-+ if (combo_cfg || cfg->has_phy_dp_com_ctrl) {
-+ qmp->dp_com = devm_platform_ioremap_resource(pdev, 1);
-+ if (IS_ERR(qmp->dp_com))
-+ return PTR_ERR(qmp->dp_com);
-+ }
-+
-+ if (combo_cfg) {
-+ /* Only two serdes for combo PHY */
-+ dp_serdes = devm_platform_ioremap_resource(pdev, 2);
-+ if (IS_ERR(dp_serdes))
-+ return PTR_ERR(dp_serdes);
-+
-+ dp_cfg = combo_cfg->dp_cfg;
-+ expected_phys = 2;
-+ } else {
-+ expected_phys = cfg->nlanes;
-+ }
-+
-+ mutex_init(&qmp->phy_mutex);
-+
-+ ret = qcom_qmp_phy_clk_init(dev, cfg);
-+ if (ret)
-+ return ret;
-+
-+ ret = qcom_qmp_phy_reset_init(dev, cfg);
-+ if (ret)
-+ return ret;
-+
-+ ret = qcom_qmp_phy_vreg_init(dev, cfg);
-+ if (ret) {
-+ if (ret != -EPROBE_DEFER)
-+ dev_err(dev, "failed to get regulator supplies: %d\n",
-+ ret);
-+ return ret;
-+ }
-+
-+ num = of_get_available_child_count(dev->of_node);
-+ /* do we have a rogue child node ? */
-+ if (num > expected_phys)
-+ return -EINVAL;
-+
-+ qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
-+ if (!qmp->phys)
-+ return -ENOMEM;
-+
-+ pm_runtime_set_active(dev);
-+ pm_runtime_enable(dev);
-+ /*
-+ * Prevent runtime pm from being ON by default. Users can enable
-+ * it using power/control in sysfs.
-+ */
-+ pm_runtime_forbid(dev);
-+
-+ id = 0;
-+ for_each_available_child_of_node(dev->of_node, child) {
-+ if (of_node_name_eq(child, "dp-phy")) {
-+ cfg = dp_cfg;
-+ serdes = dp_serdes;
-+ } else if (of_node_name_eq(child, "usb3-phy")) {
-+ cfg = usb_cfg;
-+ serdes = usb_serdes;
-+ }
-+
-+ /* Create per-lane phy */
-+ ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg);
-+ if (ret) {
-+ dev_err(dev, "failed to create lane%d phy, %d\n",
-+ id, ret);
-+ goto err_node_put;
-+ }
-+
-+ /*
-+ * Register the pipe clock provided by phy.
-+ * See function description to see details of this pipe clock.
-+ */
-+ if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) {
-+ ret = phy_pipe_clk_register(qmp, child);
-+ if (ret) {
-+ dev_err(qmp->dev,
-+ "failed to register pipe clock source\n");
-+ goto err_node_put;
-+ }
-+ } else if (cfg->type == PHY_TYPE_DP) {
-+ ret = phy_dp_clks_register(qmp, qmp->phys[id], child);
-+ if (ret) {
-+ dev_err(qmp->dev,
-+ "failed to register DP clock source\n");
-+ goto err_node_put;
-+ }
-+ }
-+ id++;
-+ }
-+
-+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
-+ if (!IS_ERR(phy_provider))
-+ dev_info(dev, "Registered Qcom-QMP phy\n");
-+ else
-+ pm_runtime_disable(dev);
-+
-+ return PTR_ERR_OR_ZERO(phy_provider);
-+
-+err_node_put:
-+ pm_runtime_disable(dev);
-+ of_node_put(child);
-+ return ret;
-+}
-+
-+static struct platform_driver qcom_qmp_phy_driver = {
-+ .probe = qcom_qmp_phy_probe,
-+ .driver = {
-+ .name = "qcom-qmp-phy",
-+ .pm = &qcom_qmp_phy_pm_ops,
-+ .of_match_table = qcom_qmp_phy_of_match_table,
-+ },
-+};
-+
-+module_platform_driver(qcom_qmp_phy_driver);
-+
-+MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
-+MODULE_DESCRIPTION("Qualcomm QMP PHY driver");
-+MODULE_LICENSE("GPL v2");
---
-2.35.1
-
+++ /dev/null
-From fbbf71f3740939c44dfb5411e2daf3bf0d8e8f41 Mon Sep 17 00:00:00 2001
-From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Date: Fri, 10 Jun 2022 21:55:41 +0300
-Subject: phy: qcom-qmp: fix msm8996 PCIe PHY support
-
-From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-
-commit fbbf71f3740939c44dfb5411e2daf3bf0d8e8f41 upstream.
-
-Replace init/exit ops with power_on/power_off which should be used for
-the PCIe PHYs to fix PHY initialization.
-
-Fixes: f575ac2d64e7 ("phy: qcom-qmp-pcie-msm8996: drop support for non-PCIe PHY types")
-Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Link: https://lore.kernel.org/r/20220610185542.3662484-2-dmitry.baryshkov@linaro.org
-Signed-off-by: Vinod Koul <vkoul@kernel.org>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
-+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
-@@ -867,8 +867,8 @@ static int phy_pipe_clk_register(struct
- }
-
- static const struct phy_ops qcom_qmp_phy_pcie_msm8996_ops = {
-- .init = qcom_qmp_phy_pcie_msm8996_enable,
-- .exit = qcom_qmp_phy_pcie_msm8996_disable,
-+ .power_on = qcom_qmp_phy_pcie_msm8996_enable,
-+ .power_off = qcom_qmp_phy_pcie_msm8996_disable,
- .set_mode = qcom_qmp_phy_pcie_msm8996_set_mode,
- .owner = THIS_MODULE,
- };
+++ /dev/null
-From 199a9ad13bbfb271b3658b858314eab44445fa13 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Wed, 8 Jun 2022 00:31:42 +0300
-Subject: phy: qcom-qmp-pcie: change symbol prefix to qcom_qmp_phy_pcie_msm8996
-
-From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-
-[ Upstream commit 2abf0c8e61a900a77f2262f54596973db572cabb ]
-
-Change all symbol names to start with qcom_qmp_phy_pcie_msm8996_ rather
-than old qcom_qmp_phy_.
-
-Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> # UFS, PCIe and USB on SC8180X
-Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Link: https://lore.kernel.org/r/20220607213203.2819885-10-dmitry.baryshkov@linaro.org
-Signed-off-by: Vinod Koul <vkoul@kernel.org>
-Stable-dep-of: 1f69ededf8e8 ("phy: qcom-qmp-pcie-msm8996: fix memleak on probe deferral")
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- .../phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 158 +++++++++---------
- 1 file changed, 79 insertions(+), 79 deletions(-)
-
-diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
-index 260e534b5607..1741a5675f9a 100644
---- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
-+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
-@@ -474,7 +474,7 @@ static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
- };
-
--static void qcom_qmp_phy_configure_lane(void __iomem *base,
-+static void qcom_qmp_phy_pcie_msm8996_configure_lane(void __iomem *base,
- const unsigned int *regs,
- const struct qmp_phy_init_tbl tbl[],
- int num,
-@@ -497,15 +497,15 @@ static void qcom_qmp_phy_configure_lane(void __iomem *base,
- }
- }
-
--static void qcom_qmp_phy_configure(void __iomem *base,
-+static void qcom_qmp_phy_pcie_msm8996_configure(void __iomem *base,
- const unsigned int *regs,
- const struct qmp_phy_init_tbl tbl[],
- int num)
- {
-- qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff);
-+ qcom_qmp_phy_pcie_msm8996_configure_lane(base, regs, tbl, num, 0xff);
- }
-
--static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
-+static int qcom_qmp_phy_pcie_msm8996_serdes_init(struct qmp_phy *qphy)
- {
- struct qcom_qmp *qmp = qphy->qmp;
- const struct qmp_phy_cfg *cfg = qphy->cfg;
-@@ -515,30 +515,30 @@ static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
- int serdes_tbl_num = cfg->serdes_tbl_num;
- int ret;
-
-- qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
-+ qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
- if (cfg->serdes_tbl_sec)
-- qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
-+ qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
- cfg->serdes_tbl_num_sec);
-
- if (cfg->type == PHY_TYPE_DP) {
- switch (dp_opts->link_rate) {
- case 1620:
-- qcom_qmp_phy_configure(serdes, cfg->regs,
-+ qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs,
- cfg->serdes_tbl_rbr,
- cfg->serdes_tbl_rbr_num);
- break;
- case 2700:
-- qcom_qmp_phy_configure(serdes, cfg->regs,
-+ qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs,
- cfg->serdes_tbl_hbr,
- cfg->serdes_tbl_hbr_num);
- break;
- case 5400:
-- qcom_qmp_phy_configure(serdes, cfg->regs,
-+ qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs,
- cfg->serdes_tbl_hbr2,
- cfg->serdes_tbl_hbr2_num);
- break;
- case 8100:
-- qcom_qmp_phy_configure(serdes, cfg->regs,
-+ qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs,
- cfg->serdes_tbl_hbr3,
- cfg->serdes_tbl_hbr3_num);
- break;
-@@ -602,7 +602,7 @@ static int qcom_qmp_dp_phy_calibrate(struct phy *phy)
- return 0;
- }
-
--static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
-+static int qcom_qmp_phy_pcie_msm8996_com_init(struct qmp_phy *qphy)
- {
- struct qcom_qmp *qmp = qphy->qmp;
- const struct qmp_phy_cfg *cfg = qphy->cfg;
-@@ -697,7 +697,7 @@ static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
- return ret;
- }
-
--static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy)
-+static int qcom_qmp_phy_pcie_msm8996_com_exit(struct qmp_phy *qphy)
- {
- struct qcom_qmp *qmp = qphy->qmp;
- const struct qmp_phy_cfg *cfg = qphy->cfg;
-@@ -732,7 +732,7 @@ static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy)
- return 0;
- }
-
--static int qcom_qmp_phy_init(struct phy *phy)
-+static int qcom_qmp_phy_pcie_msm8996_init(struct phy *phy)
- {
- struct qmp_phy *qphy = phy_get_drvdata(phy);
- struct qcom_qmp *qmp = qphy->qmp;
-@@ -767,7 +767,7 @@ static int qcom_qmp_phy_init(struct phy *phy)
- return ret;
- }
-
-- ret = qcom_qmp_phy_com_init(qphy);
-+ ret = qcom_qmp_phy_pcie_msm8996_com_init(qphy);
- if (ret)
- return ret;
-
-@@ -777,7 +777,7 @@ static int qcom_qmp_phy_init(struct phy *phy)
- return 0;
- }
-
--static int qcom_qmp_phy_power_on(struct phy *phy)
-+static int qcom_qmp_phy_pcie_msm8996_power_on(struct phy *phy)
- {
- struct qmp_phy *qphy = phy_get_drvdata(phy);
- struct qcom_qmp *qmp = qphy->qmp;
-@@ -790,7 +790,7 @@ static int qcom_qmp_phy_power_on(struct phy *phy)
- unsigned int mask, val, ready;
- int ret;
-
-- qcom_qmp_phy_serdes_init(qphy);
-+ qcom_qmp_phy_pcie_msm8996_serdes_init(qphy);
-
- if (cfg->has_lane_rst) {
- ret = reset_control_deassert(qphy->lane_rst);
-@@ -808,18 +808,18 @@ static int qcom_qmp_phy_power_on(struct phy *phy)
- }
-
- /* Tx, Rx, and PCS configurations */
-- qcom_qmp_phy_configure_lane(tx, cfg->regs,
-+ qcom_qmp_phy_pcie_msm8996_configure_lane(tx, cfg->regs,
- cfg->tx_tbl, cfg->tx_tbl_num, 1);
- if (cfg->tx_tbl_sec)
-- qcom_qmp_phy_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
-+ qcom_qmp_phy_pcie_msm8996_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
- cfg->tx_tbl_num_sec, 1);
-
- /* Configuration for other LANE for USB-DP combo PHY */
- if (cfg->is_dual_lane_phy) {
-- qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
-+ qcom_qmp_phy_pcie_msm8996_configure_lane(qphy->tx2, cfg->regs,
- cfg->tx_tbl, cfg->tx_tbl_num, 2);
- if (cfg->tx_tbl_sec)
-- qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
-+ qcom_qmp_phy_pcie_msm8996_configure_lane(qphy->tx2, cfg->regs,
- cfg->tx_tbl_sec,
- cfg->tx_tbl_num_sec, 2);
- }
-@@ -828,17 +828,17 @@ static int qcom_qmp_phy_power_on(struct phy *phy)
- if (cfg->type == PHY_TYPE_DP)
- cfg->configure_dp_tx(qphy);
-
-- qcom_qmp_phy_configure_lane(rx, cfg->regs,
-+ qcom_qmp_phy_pcie_msm8996_configure_lane(rx, cfg->regs,
- cfg->rx_tbl, cfg->rx_tbl_num, 1);
- if (cfg->rx_tbl_sec)
-- qcom_qmp_phy_configure_lane(rx, cfg->regs,
-+ qcom_qmp_phy_pcie_msm8996_configure_lane(rx, cfg->regs,
- cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1);
-
- if (cfg->is_dual_lane_phy) {
-- qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
-+ qcom_qmp_phy_pcie_msm8996_configure_lane(qphy->rx2, cfg->regs,
- cfg->rx_tbl, cfg->rx_tbl_num, 2);
- if (cfg->rx_tbl_sec)
-- qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
-+ qcom_qmp_phy_pcie_msm8996_configure_lane(qphy->rx2, cfg->regs,
- cfg->rx_tbl_sec,
- cfg->rx_tbl_num_sec, 2);
- }
-@@ -847,9 +847,9 @@ static int qcom_qmp_phy_power_on(struct phy *phy)
- if (cfg->type == PHY_TYPE_DP) {
- cfg->configure_dp_phy(qphy);
- } else {
-- qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
-+ qcom_qmp_phy_pcie_msm8996_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
- if (cfg->pcs_tbl_sec)
-- qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
-+ qcom_qmp_phy_pcie_msm8996_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
- cfg->pcs_tbl_num_sec);
- }
-
-@@ -857,10 +857,10 @@ static int qcom_qmp_phy_power_on(struct phy *phy)
- if (ret)
- goto err_disable_pipe_clk;
-
-- qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
-+ qcom_qmp_phy_pcie_msm8996_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
- cfg->pcs_misc_tbl_num);
- if (cfg->pcs_misc_tbl_sec)
-- qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
-+ qcom_qmp_phy_pcie_msm8996_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
- cfg->pcs_misc_tbl_num_sec);
-
- /*
-@@ -908,7 +908,7 @@ static int qcom_qmp_phy_power_on(struct phy *phy)
- return ret;
- }
-
--static int qcom_qmp_phy_power_off(struct phy *phy)
-+static int qcom_qmp_phy_pcie_msm8996_power_off(struct phy *phy)
- {
- struct qmp_phy *qphy = phy_get_drvdata(phy);
- const struct qmp_phy_cfg *cfg = qphy->cfg;
-@@ -939,7 +939,7 @@ static int qcom_qmp_phy_power_off(struct phy *phy)
- return 0;
- }
-
--static int qcom_qmp_phy_exit(struct phy *phy)
-+static int qcom_qmp_phy_pcie_msm8996_exit(struct phy *phy)
- {
- struct qmp_phy *qphy = phy_get_drvdata(phy);
- const struct qmp_phy_cfg *cfg = qphy->cfg;
-@@ -947,37 +947,37 @@ static int qcom_qmp_phy_exit(struct phy *phy)
- if (cfg->has_lane_rst)
- reset_control_assert(qphy->lane_rst);
-
-- qcom_qmp_phy_com_exit(qphy);
-+ qcom_qmp_phy_pcie_msm8996_com_exit(qphy);
-
- return 0;
- }
-
--static int qcom_qmp_phy_enable(struct phy *phy)
-+static int qcom_qmp_phy_pcie_msm8996_enable(struct phy *phy)
- {
- int ret;
-
-- ret = qcom_qmp_phy_init(phy);
-+ ret = qcom_qmp_phy_pcie_msm8996_init(phy);
- if (ret)
- return ret;
-
-- ret = qcom_qmp_phy_power_on(phy);
-+ ret = qcom_qmp_phy_pcie_msm8996_power_on(phy);
- if (ret)
-- qcom_qmp_phy_exit(phy);
-+ qcom_qmp_phy_pcie_msm8996_exit(phy);
-
- return ret;
- }
-
--static int qcom_qmp_phy_disable(struct phy *phy)
-+static int qcom_qmp_phy_pcie_msm8996_disable(struct phy *phy)
- {
- int ret;
-
-- ret = qcom_qmp_phy_power_off(phy);
-+ ret = qcom_qmp_phy_pcie_msm8996_power_off(phy);
- if (ret)
- return ret;
-- return qcom_qmp_phy_exit(phy);
-+ return qcom_qmp_phy_pcie_msm8996_exit(phy);
- }
-
--static int qcom_qmp_phy_set_mode(struct phy *phy,
-+static int qcom_qmp_phy_pcie_msm8996_set_mode(struct phy *phy,
- enum phy_mode mode, int submode)
- {
- struct qmp_phy *qphy = phy_get_drvdata(phy);
-@@ -987,7 +987,7 @@ static int qcom_qmp_phy_set_mode(struct phy *phy,
- return 0;
- }
-
--static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
-+static void qcom_qmp_phy_pcie_msm8996_enable_autonomous_mode(struct qmp_phy *qphy)
- {
- const struct qmp_phy_cfg *cfg = qphy->cfg;
- void __iomem *pcs = qphy->pcs;
-@@ -1016,7 +1016,7 @@ static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
- qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
- }
-
--static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
-+static void qcom_qmp_phy_pcie_msm8996_disable_autonomous_mode(struct qmp_phy *qphy)
- {
- const struct qmp_phy_cfg *cfg = qphy->cfg;
- void __iomem *pcs = qphy->pcs;
-@@ -1034,7 +1034,7 @@ static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
- qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
- }
-
--static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
-+static int __maybe_unused qcom_qmp_phy_pcie_msm8996_runtime_suspend(struct device *dev)
- {
- struct qcom_qmp *qmp = dev_get_drvdata(dev);
- struct qmp_phy *qphy = qmp->phys[0];
-@@ -1051,7 +1051,7 @@ static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
- return 0;
- }
-
-- qcom_qmp_phy_enable_autonomous_mode(qphy);
-+ qcom_qmp_phy_pcie_msm8996_enable_autonomous_mode(qphy);
-
- clk_disable_unprepare(qphy->pipe_clk);
- clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
-@@ -1059,7 +1059,7 @@ static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
- return 0;
- }
-
--static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
-+static int __maybe_unused qcom_qmp_phy_pcie_msm8996_runtime_resume(struct device *dev)
- {
- struct qcom_qmp *qmp = dev_get_drvdata(dev);
- struct qmp_phy *qphy = qmp->phys[0];
-@@ -1088,12 +1088,12 @@ static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
- return ret;
- }
-
-- qcom_qmp_phy_disable_autonomous_mode(qphy);
-+ qcom_qmp_phy_pcie_msm8996_disable_autonomous_mode(qphy);
-
- return 0;
- }
-
--static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
-+static int qcom_qmp_phy_pcie_msm8996_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
- {
- struct qcom_qmp *qmp = dev_get_drvdata(dev);
- int num = cfg->num_vregs;
-@@ -1109,7 +1109,7 @@ static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *
- return devm_regulator_bulk_get(dev, num, qmp->vregs);
- }
-
--static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
-+static int qcom_qmp_phy_pcie_msm8996_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
- {
- struct qcom_qmp *qmp = dev_get_drvdata(dev);
- int i;
-@@ -1134,7 +1134,7 @@ static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg
- return 0;
- }
-
--static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
-+static int qcom_qmp_phy_pcie_msm8996_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
- {
- struct qcom_qmp *qmp = dev_get_drvdata(dev);
- int num = cfg->num_clks;
-@@ -1402,28 +1402,28 @@ static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy,
- return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
- }
-
--static const struct phy_ops qcom_qmp_phy_gen_ops = {
-- .init = qcom_qmp_phy_enable,
-- .exit = qcom_qmp_phy_disable,
-- .set_mode = qcom_qmp_phy_set_mode,
-+static const struct phy_ops qcom_qmp_phy_pcie_msm8996_gen_ops = {
-+ .init = qcom_qmp_phy_pcie_msm8996_enable,
-+ .exit = qcom_qmp_phy_pcie_msm8996_disable,
-+ .set_mode = qcom_qmp_phy_pcie_msm8996_set_mode,
- .owner = THIS_MODULE,
- };
-
--static const struct phy_ops qcom_qmp_phy_dp_ops = {
-- .init = qcom_qmp_phy_init,
-+static const struct phy_ops qcom_qmp_phy_pcie_msm8996_dp_ops = {
-+ .init = qcom_qmp_phy_pcie_msm8996_init,
- .configure = qcom_qmp_dp_phy_configure,
-- .power_on = qcom_qmp_phy_power_on,
-+ .power_on = qcom_qmp_phy_pcie_msm8996_power_on,
- .calibrate = qcom_qmp_dp_phy_calibrate,
-- .power_off = qcom_qmp_phy_power_off,
-- .exit = qcom_qmp_phy_exit,
-- .set_mode = qcom_qmp_phy_set_mode,
-+ .power_off = qcom_qmp_phy_pcie_msm8996_power_off,
-+ .exit = qcom_qmp_phy_pcie_msm8996_exit,
-+ .set_mode = qcom_qmp_phy_pcie_msm8996_set_mode,
- .owner = THIS_MODULE,
- };
-
- static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
-- .power_on = qcom_qmp_phy_enable,
-- .power_off = qcom_qmp_phy_disable,
-- .set_mode = qcom_qmp_phy_set_mode,
-+ .power_on = qcom_qmp_phy_pcie_msm8996_enable,
-+ .power_off = qcom_qmp_phy_pcie_msm8996_disable,
-+ .set_mode = qcom_qmp_phy_pcie_msm8996_set_mode,
- .owner = THIS_MODULE,
- };
-
-@@ -1433,7 +1433,7 @@ static void qcom_qmp_reset_control_put(void *data)
- }
-
- static
--int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
-+int qcom_qmp_phy_pcie_msm8996_create(struct device *dev, struct device_node *np, int id,
- void __iomem *serdes, const struct qmp_phy_cfg *cfg)
- {
- struct qcom_qmp *qmp = dev_get_drvdata(dev);
-@@ -1535,9 +1535,9 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
- if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE)
- ops = &qcom_qmp_pcie_ufs_ops;
- else if (cfg->type == PHY_TYPE_DP)
-- ops = &qcom_qmp_phy_dp_ops;
-+ ops = &qcom_qmp_phy_pcie_msm8996_dp_ops;
- else
-- ops = &qcom_qmp_phy_gen_ops;
-+ ops = &qcom_qmp_phy_pcie_msm8996_gen_ops;
-
- generic_phy = devm_phy_create(dev, np, ops);
- if (IS_ERR(generic_phy)) {
-@@ -1555,21 +1555,21 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
- return 0;
- }
-
--static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
-+static const struct of_device_id qcom_qmp_phy_pcie_msm8996_of_match_table[] = {
- {
- .compatible = "qcom,msm8996-qmp-pcie-phy",
- .data = &msm8996_pciephy_cfg,
- },
- { },
- };
--MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
-+MODULE_DEVICE_TABLE(of, qcom_qmp_phy_pcie_msm8996_of_match_table);
-
--static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
-- SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
-- qcom_qmp_phy_runtime_resume, NULL)
-+static const struct dev_pm_ops qcom_qmp_phy_pcie_msm8996_pm_ops = {
-+ SET_RUNTIME_PM_OPS(qcom_qmp_phy_pcie_msm8996_runtime_suspend,
-+ qcom_qmp_phy_pcie_msm8996_runtime_resume, NULL)
- };
-
--static int qcom_qmp_phy_probe(struct platform_device *pdev)
-+static int qcom_qmp_phy_pcie_msm8996_probe(struct platform_device *pdev)
- {
- struct qcom_qmp *qmp;
- struct device *dev = &pdev->dev;
-@@ -1623,15 +1623,15 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
-
- mutex_init(&qmp->phy_mutex);
-
-- ret = qcom_qmp_phy_clk_init(dev, cfg);
-+ ret = qcom_qmp_phy_pcie_msm8996_clk_init(dev, cfg);
- if (ret)
- return ret;
-
-- ret = qcom_qmp_phy_reset_init(dev, cfg);
-+ ret = qcom_qmp_phy_pcie_msm8996_reset_init(dev, cfg);
- if (ret)
- return ret;
-
-- ret = qcom_qmp_phy_vreg_init(dev, cfg);
-+ ret = qcom_qmp_phy_pcie_msm8996_vreg_init(dev, cfg);
- if (ret) {
- if (ret != -EPROBE_DEFER)
- dev_err(dev, "failed to get regulator supplies: %d\n",
-@@ -1667,7 +1667,7 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
- }
-
- /* Create per-lane phy */
-- ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg);
-+ ret = qcom_qmp_phy_pcie_msm8996_create(dev, child, id, serdes, cfg);
- if (ret) {
- dev_err(dev, "failed to create lane%d phy, %d\n",
- id, ret);
-@@ -1710,16 +1710,16 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
- return ret;
- }
-
--static struct platform_driver qcom_qmp_phy_driver = {
-- .probe = qcom_qmp_phy_probe,
-+static struct platform_driver qcom_qmp_phy_pcie_msm8996_driver = {
-+ .probe = qcom_qmp_phy_pcie_msm8996_probe,
- .driver = {
- .name = "qcom-qmp-msm8996-pcie-phy",
-- .pm = &qcom_qmp_phy_pm_ops,
-- .of_match_table = qcom_qmp_phy_of_match_table,
-+ .pm = &qcom_qmp_phy_pcie_msm8996_pm_ops,
-+ .of_match_table = qcom_qmp_phy_pcie_msm8996_of_match_table,
- },
- };
-
--module_platform_driver(qcom_qmp_phy_driver);
-+module_platform_driver(qcom_qmp_phy_pcie_msm8996_driver);
-
- MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
- MODULE_DESCRIPTION("Qualcomm QMP MSM8996 PCIe PHY driver");
---
-2.35.1
-
+++ /dev/null
-From 299192ee58f58e9f9b5f0cf204cf6eabf2ae7908 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Wed, 8 Jun 2022 00:31:54 +0300
-Subject: phy: qcom-qmp-pcie-msm8996: cleanup the driver
-
-From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-
-[ Upstream commit 4856865b0dec88570edfbdf3e9c3b551923c0768 ]
-
-Remove the conditionals and options that are not used by the MSM8996
-PCIe PHY device. Hardcode has_lane_rst and has_phy_com_ctrl as this is
-the case for this PHY.
-
-Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> # UFS, PCIe and USB on SC8180X
-Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Link: https://lore.kernel.org/r/20220607213203.2819885-22-dmitry.baryshkov@linaro.org
-Signed-off-by: Vinod Koul <vkoul@kernel.org>
-Stable-dep-of: 1f69ededf8e8 ("phy: qcom-qmp-pcie-msm8996: fix memleak on probe deferral")
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- .../phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 268 +++---------------
- 1 file changed, 41 insertions(+), 227 deletions(-)
-
-diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
-index 02e5ae7fa213..51da3a3a199e 100644
---- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
-+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
-@@ -266,22 +266,6 @@ struct qmp_phy_cfg {
- const struct qmp_phy_init_tbl *pcs_misc_tbl_sec;
- int pcs_misc_tbl_num_sec;
-
-- /* Init sequence for DP PHY block link rates */
-- const struct qmp_phy_init_tbl *serdes_tbl_rbr;
-- int serdes_tbl_rbr_num;
-- const struct qmp_phy_init_tbl *serdes_tbl_hbr;
-- int serdes_tbl_hbr_num;
-- const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
-- int serdes_tbl_hbr2_num;
-- const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
-- int serdes_tbl_hbr3_num;
--
-- /* DP PHY callbacks */
-- int (*configure_dp_phy)(struct qmp_phy *qphy);
-- void (*configure_dp_tx)(struct qmp_phy *qphy);
-- int (*calibrate_dp_phy)(struct qmp_phy *qphy);
-- void (*dp_aux_init)(struct qmp_phy *qphy);
--
- /* clock ids to be requested */
- const char * const *clk_list;
- int num_clks;
-@@ -301,28 +285,11 @@ struct qmp_phy_cfg {
- /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
- unsigned int phy_status;
-
-- /* true, if PHY has a separate PHY_COM control block */
-- bool has_phy_com_ctrl;
-- /* true, if PHY has a reset for individual lanes */
-- bool has_lane_rst;
- /* true, if PHY needs delay after POWER_DOWN */
- bool has_pwrdn_delay;
- /* power_down delay in usec */
- int pwrdn_delay_min;
- int pwrdn_delay_max;
--
-- /* true, if PHY has a separate DP_COM control block */
-- bool has_phy_dp_com_ctrl;
-- /* true, if PHY has secondary tx/rx lanes to be configured */
-- bool is_dual_lane_phy;
--
-- /* true, if PCS block has no separate SW_RESET register */
-- bool no_pcs_sw_reset;
--};
--
--struct qmp_phy_combo_cfg {
-- const struct qmp_phy_cfg *usb_cfg;
-- const struct qmp_phy_cfg *dp_cfg;
- };
-
- /**
-@@ -334,17 +301,12 @@ struct qmp_phy_combo_cfg {
- * @tx: iomapped memory space for lane's tx
- * @rx: iomapped memory space for lane's rx
- * @pcs: iomapped memory space for lane's pcs
-- * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
-- * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
- * @pcs_misc: iomapped memory space for lane's pcs_misc
- * @pipe_clk: pipe clock
- * @index: lane index
- * @qmp: QMP phy to which this lane belongs
- * @lane_rst: lane's reset controller
- * @mode: current PHY mode
-- * @dp_aux_cfg: Display port aux config
-- * @dp_opts: Display port optional config
-- * @dp_clks: Display port clocks
- */
- struct qmp_phy {
- struct phy *phy;
-@@ -353,30 +315,18 @@ struct qmp_phy {
- void __iomem *tx;
- void __iomem *rx;
- void __iomem *pcs;
-- void __iomem *tx2;
-- void __iomem *rx2;
- void __iomem *pcs_misc;
- struct clk *pipe_clk;
- unsigned int index;
- struct qcom_qmp *qmp;
- struct reset_control *lane_rst;
- enum phy_mode mode;
-- unsigned int dp_aux_cfg;
-- struct phy_configure_opts_dp dp_opts;
-- struct qmp_phy_dp_clks *dp_clks;
--};
--
--struct qmp_phy_dp_clks {
-- struct qmp_phy *qphy;
-- struct clk_hw dp_link_hw;
-- struct clk_hw dp_pixel_hw;
- };
-
- /**
- * struct qcom_qmp - structure holding QMP phy block attributes
- *
- * @dev: device
-- * @dp_com: iomapped memory space for phy's dp_com control block
- *
- * @clks: array of clocks required by phy
- * @resets: array of resets required by phy
-@@ -385,11 +335,9 @@ struct qmp_phy_dp_clks {
- * @phys: array of per-lane phy descriptors
- * @phy_mutex: mutex lock for PHY common block initialization
- * @init_count: phy common block initialization count
-- * @ufs_reset: optional UFS PHY reset handle
- */
- struct qcom_qmp {
- struct device *dev;
-- void __iomem *dp_com;
-
- struct clk_bulk_data *clks;
- struct reset_control **resets;
-@@ -399,8 +347,6 @@ struct qcom_qmp {
-
- struct mutex phy_mutex;
- int init_count;
--
-- struct reset_control *ufs_reset;
- };
-
- static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
-@@ -467,8 +413,6 @@ static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
- .mask_com_pcs_ready = PCS_READY,
- .phy_status = PHYSTATUS,
-
-- .has_phy_com_ctrl = true,
-- .has_lane_rst = true,
- .has_pwrdn_delay = true,
- .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-@@ -512,6 +456,8 @@ static int qcom_qmp_phy_pcie_msm8996_serdes_init(struct qmp_phy *qphy)
- void __iomem *serdes = qphy->serdes;
- const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
- int serdes_tbl_num = cfg->serdes_tbl_num;
-+ void __iomem *status;
-+ unsigned int mask, val;
- int ret;
-
- qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
-@@ -519,24 +465,20 @@ static int qcom_qmp_phy_pcie_msm8996_serdes_init(struct qmp_phy *qphy)
- qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
- cfg->serdes_tbl_num_sec);
-
-- if (cfg->has_phy_com_ctrl) {
-- void __iomem *status;
-- unsigned int mask, val;
-
-- qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
-- qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
-- SERDES_START | PCS_START);
-+ qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
-+ qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
-+ SERDES_START | PCS_START);
-
-- status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
-- mask = cfg->mask_com_pcs_ready;
-+ status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
-+ mask = cfg->mask_com_pcs_ready;
-
-- ret = readl_poll_timeout(status, val, (val & mask), 10,
-- PHY_INIT_COMPLETE_TIMEOUT);
-- if (ret) {
-- dev_err(qmp->dev,
-- "phy common block init timed-out\n");
-- return ret;
-- }
-+ ret = readl_poll_timeout(status, val, (val & mask), 10,
-+ PHY_INIT_COMPLETE_TIMEOUT);
-+ if (ret) {
-+ dev_err(qmp->dev,
-+ "phy common block init timed-out\n");
-+ return ret;
- }
-
- return 0;
-@@ -547,8 +489,6 @@ static int qcom_qmp_phy_pcie_msm8996_com_init(struct qmp_phy *qphy)
- struct qcom_qmp *qmp = qphy->qmp;
- const struct qmp_phy_cfg *cfg = qphy->cfg;
- void __iomem *serdes = qphy->serdes;
-- void __iomem *pcs = qphy->pcs;
-- void __iomem *dp_com = qmp->dp_com;
- int ret, i;
-
- mutex_lock(&qmp->phy_mutex);
-@@ -586,41 +526,8 @@ static int qcom_qmp_phy_pcie_msm8996_com_init(struct qmp_phy *qphy)
- if (ret)
- goto err_assert_reset;
-
-- if (cfg->has_phy_dp_com_ctrl) {
-- qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
-- SW_PWRDN);
-- /* override hardware control for reset of qmp phy */
-- qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
-- SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
-- SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
--
-- /* Default type-c orientation, i.e CC1 */
-- qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02);
--
-- qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
-- USB3_MODE | DP_MODE);
--
-- /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
-- qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
-- SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
-- SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
--
-- qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
-- qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
-- }
--
-- if (cfg->has_phy_com_ctrl) {
-- qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
-- SW_PWRDN);
-- } else {
-- if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
-- qphy_setbits(pcs,
-- cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
-- cfg->pwrdn_ctrl);
-- else
-- qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
-- cfg->pwrdn_ctrl);
-- }
-+ qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
-+ SW_PWRDN);
-
- mutex_unlock(&qmp->phy_mutex);
-
-@@ -650,15 +557,12 @@ static int qcom_qmp_phy_pcie_msm8996_com_exit(struct qmp_phy *qphy)
- return 0;
- }
-
-- reset_control_assert(qmp->ufs_reset);
-- if (cfg->has_phy_com_ctrl) {
-- qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
-- SERDES_START | PCS_START);
-- qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
-- SW_RESET);
-- qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
-- SW_PWRDN);
-- }
-+ qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
-+ SERDES_START | PCS_START);
-+ qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
-+ SW_RESET);
-+ qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
-+ SW_PWRDN);
-
- while (--i >= 0)
- reset_control_assert(qmp->resets[i]);
-@@ -676,37 +580,9 @@ static int qcom_qmp_phy_pcie_msm8996_init(struct phy *phy)
- {
- struct qmp_phy *qphy = phy_get_drvdata(phy);
- struct qcom_qmp *qmp = qphy->qmp;
-- const struct qmp_phy_cfg *cfg = qphy->cfg;
- int ret;
- dev_vdbg(qmp->dev, "Initializing QMP phy\n");
-
-- if (cfg->no_pcs_sw_reset) {
-- /*
-- * Get UFS reset, which is delayed until now to avoid a
-- * circular dependency where UFS needs its PHY, but the PHY
-- * needs this UFS reset.
-- */
-- if (!qmp->ufs_reset) {
-- qmp->ufs_reset =
-- devm_reset_control_get_exclusive(qmp->dev,
-- "ufsphy");
--
-- if (IS_ERR(qmp->ufs_reset)) {
-- ret = PTR_ERR(qmp->ufs_reset);
-- dev_err(qmp->dev,
-- "failed to get UFS reset: %d\n",
-- ret);
--
-- qmp->ufs_reset = NULL;
-- return ret;
-- }
-- }
--
-- ret = reset_control_assert(qmp->ufs_reset);
-- if (ret)
-- return ret;
-- }
--
- ret = qcom_qmp_phy_pcie_msm8996_com_init(qphy);
- if (ret)
- return ret;
-@@ -729,13 +605,11 @@ static int qcom_qmp_phy_pcie_msm8996_power_on(struct phy *phy)
-
- qcom_qmp_phy_pcie_msm8996_serdes_init(qphy);
-
-- if (cfg->has_lane_rst) {
-- ret = reset_control_deassert(qphy->lane_rst);
-- if (ret) {
-- dev_err(qmp->dev, "lane%d reset deassert failed\n",
-- qphy->index);
-- return ret;
-- }
-+ ret = reset_control_deassert(qphy->lane_rst);
-+ if (ret) {
-+ dev_err(qmp->dev, "lane%d reset deassert failed\n",
-+ qphy->index);
-+ return ret;
- }
-
- ret = clk_prepare_enable(qphy->pipe_clk);
-@@ -751,40 +625,17 @@ static int qcom_qmp_phy_pcie_msm8996_power_on(struct phy *phy)
- qcom_qmp_phy_pcie_msm8996_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
- cfg->tx_tbl_num_sec, 1);
-
-- /* Configuration for other LANE for USB-DP combo PHY */
-- if (cfg->is_dual_lane_phy) {
-- qcom_qmp_phy_pcie_msm8996_configure_lane(qphy->tx2, cfg->regs,
-- cfg->tx_tbl, cfg->tx_tbl_num, 2);
-- if (cfg->tx_tbl_sec)
-- qcom_qmp_phy_pcie_msm8996_configure_lane(qphy->tx2, cfg->regs,
-- cfg->tx_tbl_sec,
-- cfg->tx_tbl_num_sec, 2);
-- }
--
- qcom_qmp_phy_pcie_msm8996_configure_lane(rx, cfg->regs,
- cfg->rx_tbl, cfg->rx_tbl_num, 1);
- if (cfg->rx_tbl_sec)
- qcom_qmp_phy_pcie_msm8996_configure_lane(rx, cfg->regs,
- cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1);
-
-- if (cfg->is_dual_lane_phy) {
-- qcom_qmp_phy_pcie_msm8996_configure_lane(qphy->rx2, cfg->regs,
-- cfg->rx_tbl, cfg->rx_tbl_num, 2);
-- if (cfg->rx_tbl_sec)
-- qcom_qmp_phy_pcie_msm8996_configure_lane(qphy->rx2, cfg->regs,
-- cfg->rx_tbl_sec,
-- cfg->rx_tbl_num_sec, 2);
-- }
--
- qcom_qmp_phy_pcie_msm8996_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
- if (cfg->pcs_tbl_sec)
- qcom_qmp_phy_pcie_msm8996_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
- cfg->pcs_tbl_num_sec);
-
-- ret = reset_control_deassert(qmp->ufs_reset);
-- if (ret)
-- goto err_disable_pipe_clk;
--
- qcom_qmp_phy_pcie_msm8996_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
- cfg->pcs_misc_tbl_num);
- if (cfg->pcs_misc_tbl_sec)
-@@ -801,8 +652,8 @@ static int qcom_qmp_phy_pcie_msm8996_power_on(struct phy *phy)
- usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
-
- /* Pull PHY out of reset state */
-- if (!cfg->no_pcs_sw_reset)
-- qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
-+ qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
-+
- /* start SerDes and Phy-Coding-Sublayer */
- qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
-
-@@ -822,8 +673,7 @@ static int qcom_qmp_phy_pcie_msm8996_power_on(struct phy *phy)
- err_disable_pipe_clk:
- clk_disable_unprepare(qphy->pipe_clk);
- err_reset_lane:
-- if (cfg->has_lane_rst)
-- reset_control_assert(qphy->lane_rst);
-+ reset_control_assert(qphy->lane_rst);
-
- return ret;
- }
-@@ -836,8 +686,7 @@ static int qcom_qmp_phy_pcie_msm8996_power_off(struct phy *phy)
- clk_disable_unprepare(qphy->pipe_clk);
-
- /* PHY reset */
-- if (!cfg->no_pcs_sw_reset)
-- qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
-+ qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
-
- /* stop SerDes and Phy-Coding-Sublayer */
- qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
-@@ -857,10 +706,8 @@ static int qcom_qmp_phy_pcie_msm8996_power_off(struct phy *phy)
- static int qcom_qmp_phy_pcie_msm8996_exit(struct phy *phy)
- {
- struct qmp_phy *qphy = phy_get_drvdata(phy);
-- const struct qmp_phy_cfg *cfg = qphy->cfg;
-
-- if (cfg->has_lane_rst)
-- reset_control_assert(qphy->lane_rst);
-+ reset_control_assert(qphy->lane_rst);
-
- qcom_qmp_phy_pcie_msm8996_com_exit(qphy);
-
-@@ -1065,31 +912,7 @@ int qcom_qmp_phy_pcie_msm8996_create(struct device *dev, struct device_node *np,
- if (!qphy->pcs)
- return -ENOMEM;
-
-- /*
-- * If this is a dual-lane PHY, then there should be registers for the
-- * second lane. Some old device trees did not specify this, so fall
-- * back to old legacy behavior of assuming they can be reached at an
-- * offset from the first lane.
-- */
-- if (cfg->is_dual_lane_phy) {
-- qphy->tx2 = of_iomap(np, 3);
-- qphy->rx2 = of_iomap(np, 4);
-- if (!qphy->tx2 || !qphy->rx2) {
-- dev_warn(dev,
-- "Underspecified device tree, falling back to legacy register regions\n");
--
-- /* In the old version, pcs_misc is at index 3. */
-- qphy->pcs_misc = qphy->tx2;
-- qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE;
-- qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
--
-- } else {
-- qphy->pcs_misc = of_iomap(np, 5);
-- }
--
-- } else {
-- qphy->pcs_misc = of_iomap(np, 3);
-- }
-+ qphy->pcs_misc = of_iomap(np, 3);
-
- if (!qphy->pcs_misc)
- dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
-@@ -1117,18 +940,16 @@ int qcom_qmp_phy_pcie_msm8996_create(struct device *dev, struct device_node *np,
- }
-
- /* Get lane reset, if any */
-- if (cfg->has_lane_rst) {
-- snprintf(prop_name, sizeof(prop_name), "lane%d", id);
-- qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name);
-- if (IS_ERR(qphy->lane_rst)) {
-- dev_err(dev, "failed to get lane%d reset\n", id);
-- return PTR_ERR(qphy->lane_rst);
-- }
-- ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put,
-- qphy->lane_rst);
-- if (ret)
-- return ret;
-+ snprintf(prop_name, sizeof(prop_name), "lane%d", id);
-+ qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name);
-+ if (IS_ERR(qphy->lane_rst)) {
-+ dev_err(dev, "failed to get lane%d reset\n", id);
-+ return PTR_ERR(qphy->lane_rst);
- }
-+ ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put,
-+ qphy->lane_rst);
-+ if (ret)
-+ return ret;
-
- generic_phy = devm_phy_create(dev, np, &qcom_qmp_phy_pcie_msm8996_ops);
- if (IS_ERR(generic_phy)) {
-@@ -1183,13 +1004,6 @@ static int qcom_qmp_phy_pcie_msm8996_probe(struct platform_device *pdev)
- if (IS_ERR(serdes))
- return PTR_ERR(serdes);
-
-- /* per PHY dp_com; if PHY has dp_com control block */
-- if (cfg->has_phy_dp_com_ctrl) {
-- qmp->dp_com = devm_platform_ioremap_resource(pdev, 1);
-- if (IS_ERR(qmp->dp_com))
-- return PTR_ERR(qmp->dp_com);
-- }
--
- expected_phys = cfg->nlanes;
-
- mutex_init(&qmp->phy_mutex);
---
-2.35.1
-
+++ /dev/null
-From 7e8f57ac63c3b62c0ba9f7bf131aefa566be1b96 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Wed, 8 Jun 2022 00:31:36 +0300
-Subject: phy: qcom-qmp-pcie-msm8996: drop all compatibles except
- msm8996-pcie-phy
-
-From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-
-[ Upstream commit 9fc8fa59ef1038714a9b86259f515373a7380169 ]
-
-Drop support for all compatibles from the new qmp-pcie driver except the
-qcom,msm8996-qmp-pcie-phy. This PHY differs from the rest of PCIe PHYs,
-so it warrants a separate device driver.
-
-Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> # UFS, PCIe and USB on SC8180X
-Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Link: https://lore.kernel.org/r/20220607213203.2819885-4-dmitry.baryshkov@linaro.org
-Signed-off-by: Vinod Koul <vkoul@kernel.org>
-Stable-dep-of: 1f69ededf8e8 ("phy: qcom-qmp-pcie-msm8996: fix memleak on probe deferral")
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- .../phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 5024 +----------------
- 1 file changed, 200 insertions(+), 4824 deletions(-)
-
-diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
-index c7309e981bfb..260e534b5607 100644
---- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
-+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
-@@ -141,18 +141,6 @@ enum qphy_reg_layout {
- QPHY_LAYOUT_SIZE
- };
-
--static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-- [QPHY_START_CTRL] = 0x00,
-- [QPHY_PCS_READY_STATUS] = 0x168,
--};
--
--static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = {
-- [QPHY_SW_RESET] = 0x00,
-- [QPHY_START_CTRL] = 0x44,
-- [QPHY_PCS_STATUS] = 0x14,
-- [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
--};
--
- static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
- [QPHY_COM_SW_RESET] = 0x400,
- [QPHY_COM_POWER_DOWN_CONTROL] = 0x404,
-@@ -169,176 +157,6 @@ static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
- [QPHY_PCS_STATUS] = 0x174,
- };
-
--static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
-- [QPHY_FLL_CNTRL1] = 0xc0,
-- [QPHY_FLL_CNTRL2] = 0xc4,
-- [QPHY_FLL_CNT_VAL_L] = 0xc8,
-- [QPHY_FLL_CNT_VAL_H_TOL] = 0xcc,
-- [QPHY_FLL_MAN_CODE] = 0xd0,
-- [QPHY_SW_RESET] = 0x00,
-- [QPHY_START_CTRL] = 0x08,
-- [QPHY_PCS_STATUS] = 0x17c,
-- [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
-- [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8,
-- [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
--};
--
--static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
-- [QPHY_SW_RESET] = 0x00,
-- [QPHY_START_CTRL] = 0x08,
-- [QPHY_PCS_STATUS] = 0x174,
-- [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
-- [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc,
-- [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
--};
--
--static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
-- [QPHY_SW_RESET] = 0x00,
-- [QPHY_START_CTRL] = 0x08,
-- [QPHY_PCS_STATUS] = 0x174,
--};
--
--static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
-- [QPHY_SW_RESET] = 0x00,
-- [QPHY_START_CTRL] = 0x08,
-- [QPHY_PCS_STATUS] = 0x2ac,
--};
--
--static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
-- [QPHY_SW_RESET] = 0x00,
-- [QPHY_START_CTRL] = 0x44,
-- [QPHY_PCS_STATUS] = 0x14,
-- [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
-- [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308,
-- [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314,
--};
--
--static const unsigned int qmp_v4_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-- [QPHY_SW_RESET] = 0x00,
-- [QPHY_START_CTRL] = 0x44,
-- [QPHY_PCS_STATUS] = 0x14,
-- [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
-- [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x608,
-- [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x614,
--};
--
--static const unsigned int sm8350_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-- [QPHY_SW_RESET] = 0x00,
-- [QPHY_START_CTRL] = 0x44,
-- [QPHY_PCS_STATUS] = 0x14,
-- [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
-- [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x1008,
-- [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x1014,
--};
--
--static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
-- [QPHY_SW_RESET] = 0x00,
-- [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
-- [QPHY_START_CTRL] = 0x08,
-- [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0xd8,
-- [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc,
-- [QPHY_PCS_STATUS] = 0x174,
-- [QPHY_PCS_MISC_TYPEC_CTRL] = 0x00,
--};
--
--static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-- [QPHY_START_CTRL] = 0x00,
-- [QPHY_PCS_READY_STATUS] = 0x160,
--};
--
--static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-- [QPHY_START_CTRL] = 0x00,
-- [QPHY_PCS_READY_STATUS] = 0x168,
--};
--
--static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = {
-- [QPHY_SW_RESET] = 0x00,
-- [QPHY_START_CTRL] = 0x44,
-- [QPHY_PCS_STATUS] = 0x14,
-- [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
--};
--
--static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-- [QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START,
-- [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS,
-- [QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET,
--};
--
--static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
-- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
-- /* PLL and Loop filter settings */
-- QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-- /* SSC settings */
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
--};
--
--static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
--};
--
--static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
--};
--
- static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
-@@ -417,4078 +235,243 @@ static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
- QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
- };
-
--static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
--};
--
--static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
--};
--
--static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
--};
--
--static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
--};
--
--static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
-- QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
-- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
--};
--
--static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-- QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
--};
--
--static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
--};
--
--static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
-- /* PLL and Loop filter settings */
-- QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-- /* SSC settings */
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
--};
--
--static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-- QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
-- QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
--};
--
--static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
--};
--
--static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
-- /* FLL settings */
-- QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03),
-- QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02),
-- QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09),
-- QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42),
-- QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
--
-- /* Lock Det settings */
-- QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
-- QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
-- QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
-- QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
--};
--
--static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
--};
--
--static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12),
--};
--
--static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x61),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04),
--};
--
--static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01),
-- QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d),
-- QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10),
-- QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa),
-- QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-- QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
-- QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01),
-- QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
-- QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
-- QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-- QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-- QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-- QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-- QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11),
-- QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_PRE, 0x00),
-- QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_POST, 0x58),
--};
--
--static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
-- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
-- QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
-- QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
-- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
-- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
--};
--
--static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-- QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
-- QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
-- QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
-- QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
--};
--
--static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
-- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
-- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
--};
--
--static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
-- QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
-- QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
-- QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
-- QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
-- QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
-- QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
-- QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
-- QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
-- QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
-- QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
-- QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
-- QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
--};
--
--static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
--};
--
--static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
--};
--
--static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
--};
--
--static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
--
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
--
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
-+struct qmp_phy;
-
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
-+/* struct qmp_phy_cfg - per-PHY initialization config */
-+struct qmp_phy_cfg {
-+ /* phy-type - PCIE/UFS/USB */
-+ unsigned int type;
-+ /* number of lanes provided by phy */
-+ int nlanes;
-
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
--};
-+ /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
-+ const struct qmp_phy_init_tbl *serdes_tbl;
-+ int serdes_tbl_num;
-+ const struct qmp_phy_init_tbl *serdes_tbl_sec;
-+ int serdes_tbl_num_sec;
-+ const struct qmp_phy_init_tbl *tx_tbl;
-+ int tx_tbl_num;
-+ const struct qmp_phy_init_tbl *tx_tbl_sec;
-+ int tx_tbl_num_sec;
-+ const struct qmp_phy_init_tbl *rx_tbl;
-+ int rx_tbl_num;
-+ const struct qmp_phy_init_tbl *rx_tbl_sec;
-+ int rx_tbl_num_sec;
-+ const struct qmp_phy_init_tbl *pcs_tbl;
-+ int pcs_tbl_num;
-+ const struct qmp_phy_init_tbl *pcs_tbl_sec;
-+ int pcs_tbl_num_sec;
-+ const struct qmp_phy_init_tbl *pcs_misc_tbl;
-+ int pcs_misc_tbl_num;
-+ const struct qmp_phy_init_tbl *pcs_misc_tbl_sec;
-+ int pcs_misc_tbl_num_sec;
-
--static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
--};
-+ /* Init sequence for DP PHY block link rates */
-+ const struct qmp_phy_init_tbl *serdes_tbl_rbr;
-+ int serdes_tbl_rbr_num;
-+ const struct qmp_phy_init_tbl *serdes_tbl_hbr;
-+ int serdes_tbl_hbr_num;
-+ const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
-+ int serdes_tbl_hbr2_num;
-+ const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
-+ int serdes_tbl_hbr3_num;
-
--static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07),
--};
-+ /* DP PHY callbacks */
-+ int (*configure_dp_phy)(struct qmp_phy *qphy);
-+ void (*configure_dp_tx)(struct qmp_phy *qphy);
-+ int (*calibrate_dp_phy)(struct qmp_phy *qphy);
-+ void (*dp_aux_init)(struct qmp_phy *qphy);
-
--static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
--};
-+ /* clock ids to be requested */
-+ const char * const *clk_list;
-+ int num_clks;
-+ /* resets to be requested */
-+ const char * const *reset_list;
-+ int num_resets;
-+ /* regulators to be requested */
-+ const char * const *vreg_list;
-+ int num_vregs;
-
--static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = {
--};
-+ /* array of registers with different offsets */
-+ const unsigned int *regs;
-
--static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f),
--};
-+ unsigned int start_ctrl;
-+ unsigned int pwrdn_ctrl;
-+ unsigned int mask_com_pcs_ready;
-+ /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
-+ unsigned int phy_status;
-
--static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
--};
-+ /* true, if PHY has a separate PHY_COM control block */
-+ bool has_phy_com_ctrl;
-+ /* true, if PHY has a reset for individual lanes */
-+ bool has_lane_rst;
-+ /* true, if PHY needs delay after POWER_DOWN */
-+ bool has_pwrdn_delay;
-+ /* power_down delay in usec */
-+ int pwrdn_delay_min;
-+ int pwrdn_delay_max;
-
--static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
--};
-+ /* true, if PHY has a separate DP_COM control block */
-+ bool has_phy_dp_com_ctrl;
-+ /* true, if PHY has secondary tx/rx lanes to be configured */
-+ bool is_dual_lane_phy;
-
--static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+ /* true, if PCS block has no separate SW_RESET register */
-+ bool no_pcs_sw_reset;
- };
-
--static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
-+struct qmp_phy_combo_cfg {
-+ const struct qmp_phy_cfg *usb_cfg;
-+ const struct qmp_phy_cfg *dp_cfg;
- };
-
--static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
--};
--
--static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
--};
--
--static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08),
--};
--
--static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
--};
--
--static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
--};
--
--static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
-- /* FLL settings */
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
--
-- /* Lock Det settings */
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
--
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
--
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
--};
--
--static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
--};
--
--static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
--};
--
--static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
--};
--
--static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
-- /* FLL settings */
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
--
-- /* Lock Det settings */
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
--
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
--
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
--
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
--};
--
--static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
-- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
--
-- /* Rate B */
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),
--};
--
--static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-- QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
--};
--
--static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40),
-- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E),
-- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D),
-- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B),
--};
--
--static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_RX_PWM_GEAR_BAND, 0x15),
-- QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_CTRL2, 0x6d),
-- QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_DRV_LVL, 0x0f),
-- QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_DRV_LVL, 0x02),
-- QMP_PHY_INIT_CFG(QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
-- QMP_PHY_INIT_CFG(QPHY_RX_SYM_RESYNC_CTRL, 0x03),
-- QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
-- QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
-- QMP_PHY_INIT_CFG(QPHY_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
--};
--
--static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
--
-- /* Rate B */
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
--};
--
--static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
--};
--
--static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
--};
--
--static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
--};
--
--static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
--};
--
--static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
--};
--
--static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
--};
--
--static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
--};
--
--static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
--
-- /* Rate B */
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
--};
--
--static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
--};
--
--static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
--
--};
--
--static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
--};
--
--static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
--};
--
--static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
--};
--
--static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
--};
--
--static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
-- /* Lock Det settings */
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
--
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
--};
--
--static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
--};
--
--static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),
--};
--
--static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
--};
--
--static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
--};
--
--static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-- QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1),
-- QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2),
--};
--
--static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-- QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1),
-- QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2),
-- QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1),
-- QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
--};
--
--static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
--};
--
--static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
--};
--
--static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
--};
--
--static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
--};
--
--static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
--};
--
--static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
--};
--
--static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
--};
--
--static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
--};
--
--static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
--};
--
--static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20),
--};
--
--static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
--};
--
--static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5),
--};
--
--static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
--};
--
--static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),
--};
--
--static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
--};
--
--static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
--};
--
--static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
--};
--
--static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
--};
--
--static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
--};
--
--static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
--};
--
--static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
--};
--
--static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12),
--};
--
--static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
--};
--
--static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f),
--};
--
--static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
--};
--
--static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
--};
--
--static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f),
--};
--
--static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
--};
--
--static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08),
--};
--
--static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
--};
--
--static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22),
--};
--
--static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00),
--};
--
--static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12),
--};
--
--static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77),
-- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01),
-- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16),
-- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02),
--};
--
--static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17),
-- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13),
-- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13),
-- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01),
-- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
-- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
--};
--
--static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b),
--};
--
--static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
--};
--
--static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
--
-- /* Rate B */
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
--};
--
--static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),
--};
--
--static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
--};
--
--static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
--};
--
--static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
--};
--
--static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb),
-- QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1),
-- QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10),
--};
--
--static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
--};
--
--static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
--};
--
--static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
--};
--
--static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
--};
--
--static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01),
--};
--
--static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00),
--};
--
--static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00),
--};
--
--static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
--};
--
--static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
--};
--
--static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04),
--};
--
--static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
--};
--
--static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
--};
--
--static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
--};
--
--static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
--};
--
--static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
--};
--
--static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
--
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05),
--
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
--
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
--
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
--};
--
--/* Register names should be validated, they might be different for this PHY */
--static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99),
--};
--
--static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-- QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
-- QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
-- QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),
-- QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
--};
--
--struct qmp_phy;
--
--/* struct qmp_phy_cfg - per-PHY initialization config */
--struct qmp_phy_cfg {
-- /* phy-type - PCIE/UFS/USB */
-- unsigned int type;
-- /* number of lanes provided by phy */
-- int nlanes;
--
-- /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
-- const struct qmp_phy_init_tbl *serdes_tbl;
-- int serdes_tbl_num;
-- const struct qmp_phy_init_tbl *serdes_tbl_sec;
-- int serdes_tbl_num_sec;
-- const struct qmp_phy_init_tbl *tx_tbl;
-- int tx_tbl_num;
-- const struct qmp_phy_init_tbl *tx_tbl_sec;
-- int tx_tbl_num_sec;
-- const struct qmp_phy_init_tbl *rx_tbl;
-- int rx_tbl_num;
-- const struct qmp_phy_init_tbl *rx_tbl_sec;
-- int rx_tbl_num_sec;
-- const struct qmp_phy_init_tbl *pcs_tbl;
-- int pcs_tbl_num;
-- const struct qmp_phy_init_tbl *pcs_tbl_sec;
-- int pcs_tbl_num_sec;
-- const struct qmp_phy_init_tbl *pcs_misc_tbl;
-- int pcs_misc_tbl_num;
-- const struct qmp_phy_init_tbl *pcs_misc_tbl_sec;
-- int pcs_misc_tbl_num_sec;
--
-- /* Init sequence for DP PHY block link rates */
-- const struct qmp_phy_init_tbl *serdes_tbl_rbr;
-- int serdes_tbl_rbr_num;
-- const struct qmp_phy_init_tbl *serdes_tbl_hbr;
-- int serdes_tbl_hbr_num;
-- const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
-- int serdes_tbl_hbr2_num;
-- const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
-- int serdes_tbl_hbr3_num;
--
-- /* DP PHY callbacks */
-- int (*configure_dp_phy)(struct qmp_phy *qphy);
-- void (*configure_dp_tx)(struct qmp_phy *qphy);
-- int (*calibrate_dp_phy)(struct qmp_phy *qphy);
-- void (*dp_aux_init)(struct qmp_phy *qphy);
--
-- /* clock ids to be requested */
-- const char * const *clk_list;
-- int num_clks;
-- /* resets to be requested */
-- const char * const *reset_list;
-- int num_resets;
-- /* regulators to be requested */
-- const char * const *vreg_list;
-- int num_vregs;
--
-- /* array of registers with different offsets */
-- const unsigned int *regs;
--
-- unsigned int start_ctrl;
-- unsigned int pwrdn_ctrl;
-- unsigned int mask_com_pcs_ready;
-- /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
-- unsigned int phy_status;
--
-- /* true, if PHY has a separate PHY_COM control block */
-- bool has_phy_com_ctrl;
-- /* true, if PHY has a reset for individual lanes */
-- bool has_lane_rst;
-- /* true, if PHY needs delay after POWER_DOWN */
-- bool has_pwrdn_delay;
-- /* power_down delay in usec */
-- int pwrdn_delay_min;
-- int pwrdn_delay_max;
--
-- /* true, if PHY has a separate DP_COM control block */
-- bool has_phy_dp_com_ctrl;
-- /* true, if PHY has secondary tx/rx lanes to be configured */
-- bool is_dual_lane_phy;
--
-- /* true, if PCS block has no separate SW_RESET register */
-- bool no_pcs_sw_reset;
--};
--
--struct qmp_phy_combo_cfg {
-- const struct qmp_phy_cfg *usb_cfg;
-- const struct qmp_phy_cfg *dp_cfg;
--};
--
--/**
-- * struct qmp_phy - per-lane phy descriptor
-- *
-- * @phy: generic phy
-- * @cfg: phy specific configuration
-- * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
-- * @tx: iomapped memory space for lane's tx
-- * @rx: iomapped memory space for lane's rx
-- * @pcs: iomapped memory space for lane's pcs
-- * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
-- * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
-- * @pcs_misc: iomapped memory space for lane's pcs_misc
-- * @pipe_clk: pipe clock
-- * @index: lane index
-- * @qmp: QMP phy to which this lane belongs
-- * @lane_rst: lane's reset controller
-- * @mode: current PHY mode
-- * @dp_aux_cfg: Display port aux config
-- * @dp_opts: Display port optional config
-- * @dp_clks: Display port clocks
-- */
--struct qmp_phy {
-- struct phy *phy;
-- const struct qmp_phy_cfg *cfg;
-- void __iomem *serdes;
-- void __iomem *tx;
-- void __iomem *rx;
-- void __iomem *pcs;
-- void __iomem *tx2;
-- void __iomem *rx2;
-- void __iomem *pcs_misc;
-- struct clk *pipe_clk;
-- unsigned int index;
-- struct qcom_qmp *qmp;
-- struct reset_control *lane_rst;
-- enum phy_mode mode;
-- unsigned int dp_aux_cfg;
-- struct phy_configure_opts_dp dp_opts;
-- struct qmp_phy_dp_clks *dp_clks;
--};
--
--struct qmp_phy_dp_clks {
-- struct qmp_phy *qphy;
-- struct clk_hw dp_link_hw;
-- struct clk_hw dp_pixel_hw;
--};
--
--/**
-- * struct qcom_qmp - structure holding QMP phy block attributes
-- *
-- * @dev: device
-- * @dp_com: iomapped memory space for phy's dp_com control block
-- *
-- * @clks: array of clocks required by phy
-- * @resets: array of resets required by phy
-- * @vregs: regulator supplies bulk data
-- *
-- * @phys: array of per-lane phy descriptors
-- * @phy_mutex: mutex lock for PHY common block initialization
-- * @init_count: phy common block initialization count
-- * @ufs_reset: optional UFS PHY reset handle
-- */
--struct qcom_qmp {
-- struct device *dev;
-- void __iomem *dp_com;
--
-- struct clk_bulk_data *clks;
-- struct reset_control **resets;
-- struct regulator_bulk_data *vregs;
--
-- struct qmp_phy **phys;
--
-- struct mutex phy_mutex;
-- int init_count;
--
-- struct reset_control *ufs_reset;
--};
--
--static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy);
--static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy);
--static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy);
--static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy);
--
--static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy);
--static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy);
--static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy);
--static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy);
--
--static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
--{
-- u32 reg;
--
-- reg = readl(base + offset);
-- reg |= val;
-- writel(reg, base + offset);
--
-- /* ensure that above write is through */
-- readl(base + offset);
--}
--
--static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
--{
-- u32 reg;
--
-- reg = readl(base + offset);
-- reg &= ~val;
-- writel(reg, base + offset);
--
-- /* ensure that above write is through */
-- readl(base + offset);
--}
--
--/* list of clocks required by phy */
--static const char * const msm8996_phy_clk_l[] = {
-- "aux", "cfg_ahb", "ref",
--};
--
--static const char * const msm8996_ufs_phy_clk_l[] = {
-- "ref",
--};
--
--static const char * const qmp_v3_phy_clk_l[] = {
-- "aux", "cfg_ahb", "ref", "com_aux",
--};
--
--static const char * const sdm845_pciephy_clk_l[] = {
-- "aux", "cfg_ahb", "ref", "refgen",
--};
--
--static const char * const qmp_v4_phy_clk_l[] = {
-- "aux", "ref_clk_src", "ref", "com_aux",
--};
--
--/* the primary usb3 phy on sm8250 doesn't have a ref clock */
--static const char * const qmp_v4_sm8250_usbphy_clk_l[] = {
-- "aux", "ref_clk_src", "com_aux"
--};
--
--static const char * const sm8450_ufs_phy_clk_l[] = {
-- "qref", "ref", "ref_aux",
--};
--
--static const char * const sdm845_ufs_phy_clk_l[] = {
-- "ref", "ref_aux",
--};
--
--/* usb3 phy on sdx55 doesn't have com_aux clock */
--static const char * const qmp_v4_sdx55_usbphy_clk_l[] = {
-- "aux", "cfg_ahb", "ref"
--};
--
--static const char * const qcm2290_usb3phy_clk_l[] = {
-- "cfg_ahb", "ref", "com_aux",
--};
--
--/* list of resets */
--static const char * const msm8996_pciephy_reset_l[] = {
-- "phy", "common", "cfg",
--};
--
--static const char * const msm8996_usb3phy_reset_l[] = {
-- "phy", "common",
--};
--
--static const char * const sc7180_usb3phy_reset_l[] = {
-- "phy",
--};
--
--static const char * const qcm2290_usb3phy_reset_l[] = {
-- "phy_phy", "phy",
--};
--
--static const char * const sdm845_pciephy_reset_l[] = {
-- "phy",
--};
--
--/* list of regulators */
--static const char * const qmp_phy_vreg_l[] = {
-- "vdda-phy", "vdda-pll",
--};
--
--static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
-- .type = PHY_TYPE_USB3,
-- .nlanes = 1,
--
-- .serdes_tbl = ipq8074_usb3_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
-- .tx_tbl = msm8996_usb3_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
-- .rx_tbl = ipq8074_usb3_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
-- .pcs_tbl = ipq8074_usb3_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
-- .clk_list = msm8996_phy_clk_l,
-- .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-- .reset_list = msm8996_usb3phy_reset_l,
-- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = usb3phy_regs_layout,
--
-- .start_ctrl = SERDES_START | PCS_START,
-- .pwrdn_ctrl = SW_PWRDN,
-- .phy_status = PHYSTATUS,
--};
--
--static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
-- .type = PHY_TYPE_PCIE,
-- .nlanes = 3,
--
-- .serdes_tbl = msm8996_pcie_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
-- .tx_tbl = msm8996_pcie_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(msm8996_pcie_tx_tbl),
-- .rx_tbl = msm8996_pcie_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(msm8996_pcie_rx_tbl),
-- .pcs_tbl = msm8996_pcie_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
-- .clk_list = msm8996_phy_clk_l,
-- .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-- .reset_list = msm8996_pciephy_reset_l,
-- .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = pciephy_regs_layout,
--
-- .start_ctrl = PCS_START | PLL_READY_GATE_EN,
-- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-- .mask_com_pcs_ready = PCS_READY,
-- .phy_status = PHYSTATUS,
--
-- .has_phy_com_ctrl = true,
-- .has_lane_rst = true,
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
--};
--
--static const struct qmp_phy_cfg msm8996_ufs_cfg = {
-- .type = PHY_TYPE_UFS,
-- .nlanes = 1,
--
-- .serdes_tbl = msm8996_ufs_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(msm8996_ufs_serdes_tbl),
-- .tx_tbl = msm8996_ufs_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(msm8996_ufs_tx_tbl),
-- .rx_tbl = msm8996_ufs_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(msm8996_ufs_rx_tbl),
--
-- .clk_list = msm8996_ufs_phy_clk_l,
-- .num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
--
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
--
-- .regs = msm8996_ufsphy_regs_layout,
--
-- .start_ctrl = SERDES_START,
-- .pwrdn_ctrl = SW_PWRDN,
-- .phy_status = PHYSTATUS,
--
-- .no_pcs_sw_reset = true,
--};
--
--static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
-- .type = PHY_TYPE_USB3,
-- .nlanes = 1,
--
-- .serdes_tbl = msm8996_usb3_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
-- .tx_tbl = msm8996_usb3_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
-- .rx_tbl = msm8996_usb3_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl),
-- .pcs_tbl = msm8996_usb3_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
-- .clk_list = msm8996_phy_clk_l,
-- .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-- .reset_list = msm8996_usb3phy_reset_l,
-- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = usb3phy_regs_layout,
--
-- .start_ctrl = SERDES_START | PCS_START,
-- .pwrdn_ctrl = SW_PWRDN,
-- .phy_status = PHYSTATUS,
--};
--
--static const char * const ipq8074_pciephy_clk_l[] = {
-- "aux", "cfg_ahb",
--};
--/* list of resets */
--static const char * const ipq8074_pciephy_reset_l[] = {
-- "phy", "common",
--};
--
--static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
-- .type = PHY_TYPE_PCIE,
-- .nlanes = 1,
--
-- .serdes_tbl = ipq8074_pcie_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
-- .tx_tbl = ipq8074_pcie_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
-- .rx_tbl = ipq8074_pcie_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
-- .pcs_tbl = ipq8074_pcie_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
-- .clk_list = ipq8074_pciephy_clk_l,
-- .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
-- .reset_list = ipq8074_pciephy_reset_l,
-- .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
-- .vreg_list = NULL,
-- .num_vregs = 0,
-- .regs = pciephy_regs_layout,
--
-- .start_ctrl = SERDES_START | PCS_START,
-- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-- .phy_status = PHYSTATUS,
--
-- .has_phy_com_ctrl = false,
-- .has_lane_rst = false,
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = 995, /* us */
-- .pwrdn_delay_max = 1005, /* us */
--};
--
--static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
-- .type = PHY_TYPE_PCIE,
-- .nlanes = 1,
--
-- .serdes_tbl = ipq6018_pcie_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl),
-- .tx_tbl = ipq6018_pcie_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl),
-- .rx_tbl = ipq6018_pcie_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
-- .pcs_tbl = ipq6018_pcie_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
-- .clk_list = ipq8074_pciephy_clk_l,
-- .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
-- .reset_list = ipq8074_pciephy_reset_l,
-- .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
-- .vreg_list = NULL,
-- .num_vregs = 0,
-- .regs = ipq_pciephy_gen3_regs_layout,
--
-- .start_ctrl = SERDES_START | PCS_START,
-- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
--
-- .has_phy_com_ctrl = false,
-- .has_lane_rst = false,
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = 995, /* us */
-- .pwrdn_delay_max = 1005, /* us */
--};
--
--static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
-- .type = PHY_TYPE_PCIE,
-- .nlanes = 1,
--
-- .serdes_tbl = sdm845_qmp_pcie_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
-- .tx_tbl = sdm845_qmp_pcie_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),
-- .rx_tbl = sdm845_qmp_pcie_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),
-- .pcs_tbl = sdm845_qmp_pcie_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),
-- .pcs_misc_tbl = sdm845_qmp_pcie_pcs_misc_tbl,
-- .pcs_misc_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
-- .clk_list = sdm845_pciephy_clk_l,
-- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-- .reset_list = sdm845_pciephy_reset_l,
-- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = sdm845_qmp_pciephy_regs_layout,
--
-- .start_ctrl = PCS_START | SERDES_START,
-- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-- .phy_status = PHYSTATUS,
--
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = 995, /* us */
-- .pwrdn_delay_max = 1005, /* us */
--};
--
--static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
-- .type = PHY_TYPE_PCIE,
-- .nlanes = 1,
--
-- .serdes_tbl = sdm845_qhp_pcie_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
-- .tx_tbl = sdm845_qhp_pcie_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
-- .rx_tbl = sdm845_qhp_pcie_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl),
-- .pcs_tbl = sdm845_qhp_pcie_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
-- .clk_list = sdm845_pciephy_clk_l,
-- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-- .reset_list = sdm845_pciephy_reset_l,
-- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = sdm845_qhp_pciephy_regs_layout,
--
-- .start_ctrl = PCS_START | SERDES_START,
-- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-- .phy_status = PHYSTATUS,
--
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = 995, /* us */
-- .pwrdn_delay_max = 1005, /* us */
--};
--
--static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
-- .type = PHY_TYPE_PCIE,
-- .nlanes = 1,
--
-- .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
-- .serdes_tbl_sec = sm8250_qmp_gen3x1_pcie_serdes_tbl,
-- .serdes_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
-- .tx_tbl = sm8250_qmp_pcie_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
-- .rx_tbl = sm8250_qmp_pcie_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
-- .rx_tbl_sec = sm8250_qmp_gen3x1_pcie_rx_tbl,
-- .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),
-- .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
-- .pcs_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_tbl,
-- .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),
-- .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
-- .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
-- .pcs_misc_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,
-- .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),
-- .clk_list = sdm845_pciephy_clk_l,
-- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-- .reset_list = sdm845_pciephy_reset_l,
-- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = sm8250_pcie_regs_layout,
--
-- .start_ctrl = PCS_START | SERDES_START,
-- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-- .phy_status = PHYSTATUS,
--
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = 995, /* us */
-- .pwrdn_delay_max = 1005, /* us */
--};
--
--static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
-- .type = PHY_TYPE_PCIE,
-- .nlanes = 2,
--
-- .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
-- .tx_tbl = sm8250_qmp_pcie_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
-- .tx_tbl_sec = sm8250_qmp_gen3x2_pcie_tx_tbl,
-- .tx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),
-- .rx_tbl = sm8250_qmp_pcie_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
-- .rx_tbl_sec = sm8250_qmp_gen3x2_pcie_rx_tbl,
-- .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl),
-- .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
-- .pcs_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_tbl,
-- .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl),
-- .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
-- .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
-- .pcs_misc_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,
-- .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),
-- .clk_list = sdm845_pciephy_clk_l,
-- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-- .reset_list = sdm845_pciephy_reset_l,
-- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = sm8250_pcie_regs_layout,
--
-- .start_ctrl = PCS_START | SERDES_START,
-- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-- .phy_status = PHYSTATUS,
--
-- .is_dual_lane_phy = true,
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = 995, /* us */
-- .pwrdn_delay_max = 1005, /* us */
--};
--
--static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
-- .type = PHY_TYPE_USB3,
-- .nlanes = 1,
--
-- .serdes_tbl = qmp_v3_usb3_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
-- .tx_tbl = qmp_v3_usb3_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
-- .rx_tbl = qmp_v3_usb3_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
-- .pcs_tbl = qmp_v3_usb3_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
-- .clk_list = qmp_v3_phy_clk_l,
-- .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-- .reset_list = msm8996_usb3phy_reset_l,
-- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = qmp_v3_usb3phy_regs_layout,
--
-- .start_ctrl = SERDES_START | PCS_START,
-- .pwrdn_ctrl = SW_PWRDN,
-- .phy_status = PHYSTATUS,
--
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
--
-- .has_phy_dp_com_ctrl = true,
-- .is_dual_lane_phy = true,
--};
--
--static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
-- .type = PHY_TYPE_USB3,
-- .nlanes = 1,
--
-- .serdes_tbl = qmp_v3_usb3_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
-- .tx_tbl = qmp_v3_usb3_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
-- .rx_tbl = qmp_v3_usb3_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
-- .pcs_tbl = qmp_v3_usb3_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
-- .clk_list = qmp_v3_phy_clk_l,
-- .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-- .reset_list = sc7180_usb3phy_reset_l,
-- .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = qmp_v3_usb3phy_regs_layout,
--
-- .start_ctrl = SERDES_START | PCS_START,
-- .pwrdn_ctrl = SW_PWRDN,
-- .phy_status = PHYSTATUS,
--
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
--
-- .has_phy_dp_com_ctrl = true,
-- .is_dual_lane_phy = true,
--};
--
--static const struct qmp_phy_cfg sc7180_dpphy_cfg = {
-- .type = PHY_TYPE_DP,
-- .nlanes = 1,
--
-- .serdes_tbl = qmp_v3_dp_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
-- .tx_tbl = qmp_v3_dp_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
--
-- .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr,
-- .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
-- .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr,
-- .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
-- .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2,
-- .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
-- .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3,
-- .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
--
-- .clk_list = qmp_v3_phy_clk_l,
-- .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-- .reset_list = sc7180_usb3phy_reset_l,
-- .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = qmp_v3_usb3phy_regs_layout,
--
-- .has_phy_dp_com_ctrl = true,
-- .is_dual_lane_phy = true,
--
-- .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init,
-- .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx,
-- .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy,
-- .calibrate_dp_phy = qcom_qmp_v3_dp_phy_calibrate,
--};
--
--static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = {
-- .usb_cfg = &sc7180_usb3phy_cfg,
-- .dp_cfg = &sc7180_dpphy_cfg,
--};
--
--static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
-- .type = PHY_TYPE_USB3,
-- .nlanes = 1,
--
-- .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
-- .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
-- .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
-- .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
-- .clk_list = qmp_v3_phy_clk_l,
-- .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-- .reset_list = msm8996_usb3phy_reset_l,
-- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = qmp_v3_usb3phy_regs_layout,
--
-- .start_ctrl = SERDES_START | PCS_START,
-- .pwrdn_ctrl = SW_PWRDN,
-- .phy_status = PHYSTATUS,
--
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
--};
--
--static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
-- .type = PHY_TYPE_UFS,
-- .nlanes = 2,
--
-- .serdes_tbl = sdm845_ufsphy_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
-- .tx_tbl = sdm845_ufsphy_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
-- .rx_tbl = sdm845_ufsphy_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
-- .pcs_tbl = sdm845_ufsphy_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
-- .clk_list = sdm845_ufs_phy_clk_l,
-- .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = sdm845_ufsphy_regs_layout,
--
-- .start_ctrl = SERDES_START,
-- .pwrdn_ctrl = SW_PWRDN,
-- .phy_status = PHYSTATUS,
--
-- .is_dual_lane_phy = true,
-- .no_pcs_sw_reset = true,
--};
--
--static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
-- .type = PHY_TYPE_UFS,
-- .nlanes = 1,
--
-- .serdes_tbl = sm6115_ufsphy_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl),
-- .tx_tbl = sm6115_ufsphy_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_tx_tbl),
-- .rx_tbl = sm6115_ufsphy_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_rx_tbl),
-- .pcs_tbl = sm6115_ufsphy_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl),
-- .clk_list = sdm845_ufs_phy_clk_l,
-- .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = sm6115_ufsphy_regs_layout,
--
-- .start_ctrl = SERDES_START,
-- .pwrdn_ctrl = SW_PWRDN,
--
-- .is_dual_lane_phy = false,
-- .no_pcs_sw_reset = true,
--};
--
--static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
-- .type = PHY_TYPE_PCIE,
-- .nlanes = 1,
--
-- .serdes_tbl = msm8998_pcie_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
-- .tx_tbl = msm8998_pcie_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(msm8998_pcie_tx_tbl),
-- .rx_tbl = msm8998_pcie_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(msm8998_pcie_rx_tbl),
-- .pcs_tbl = msm8998_pcie_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
-- .clk_list = msm8996_phy_clk_l,
-- .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-- .reset_list = ipq8074_pciephy_reset_l,
-- .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = pciephy_regs_layout,
--
-- .start_ctrl = SERDES_START | PCS_START,
-- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-- .phy_status = PHYSTATUS,
--};
--
--static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
-- .type = PHY_TYPE_USB3,
-- .nlanes = 1,
--
-- .serdes_tbl = msm8998_usb3_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
-- .tx_tbl = msm8998_usb3_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl),
-- .rx_tbl = msm8998_usb3_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl),
-- .pcs_tbl = msm8998_usb3_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
-- .clk_list = msm8996_phy_clk_l,
-- .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-- .reset_list = msm8996_usb3phy_reset_l,
-- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = qmp_v3_usb3phy_regs_layout,
--
-- .start_ctrl = SERDES_START | PCS_START,
-- .pwrdn_ctrl = SW_PWRDN,
-- .phy_status = PHYSTATUS,
--
-- .is_dual_lane_phy = true,
--};
--
--static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
-- .type = PHY_TYPE_UFS,
-- .nlanes = 2,
--
-- .serdes_tbl = sm8150_ufsphy_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl),
-- .tx_tbl = sm8150_ufsphy_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx_tbl),
-- .rx_tbl = sm8150_ufsphy_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx_tbl),
-- .pcs_tbl = sm8150_ufsphy_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl),
-- .clk_list = sdm845_ufs_phy_clk_l,
-- .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = sm8150_ufsphy_regs_layout,
--
-- .start_ctrl = SERDES_START,
-- .pwrdn_ctrl = SW_PWRDN,
-- .phy_status = PHYSTATUS,
--
-- .is_dual_lane_phy = true,
--};
--
--static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
-- .type = PHY_TYPE_USB3,
-- .nlanes = 1,
--
-- .serdes_tbl = sm8150_usb3_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
-- .tx_tbl = sm8150_usb3_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl),
-- .rx_tbl = sm8150_usb3_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl),
-- .pcs_tbl = sm8150_usb3_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
-- .clk_list = qmp_v4_phy_clk_l,
-- .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-- .reset_list = msm8996_usb3phy_reset_l,
-- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = qmp_v4_usb3phy_regs_layout,
--
-- .start_ctrl = SERDES_START | PCS_START,
-- .pwrdn_ctrl = SW_PWRDN,
-- .phy_status = PHYSTATUS,
--
--
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
--
-- .has_phy_dp_com_ctrl = true,
-- .is_dual_lane_phy = true,
--};
--
--static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
-- .type = PHY_TYPE_PCIE,
-- .nlanes = 1,
--
-- .serdes_tbl = sc8180x_qmp_pcie_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl),
-- .tx_tbl = sc8180x_qmp_pcie_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl),
-- .rx_tbl = sc8180x_qmp_pcie_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl),
-- .pcs_tbl = sc8180x_qmp_pcie_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl),
-- .pcs_misc_tbl = sc8180x_qmp_pcie_pcs_misc_tbl,
-- .pcs_misc_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl),
-- .clk_list = sdm845_pciephy_clk_l,
-- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-- .reset_list = sdm845_pciephy_reset_l,
-- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = sm8250_pcie_regs_layout,
--
-- .start_ctrl = PCS_START | SERDES_START,
-- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
--
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = 995, /* us */
-- .pwrdn_delay_max = 1005, /* us */
--};
--
--static const struct qmp_phy_cfg sc8180x_dpphy_cfg = {
-- .type = PHY_TYPE_DP,
-- .nlanes = 1,
--
-- .serdes_tbl = qmp_v4_dp_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
-- .tx_tbl = qmp_v4_dp_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
--
-- .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
-- .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
-- .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
-- .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
-- .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
-- .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
-- .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
-- .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
--
-- .clk_list = qmp_v3_phy_clk_l,
-- .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-- .reset_list = sc7180_usb3phy_reset_l,
-- .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = qmp_v3_usb3phy_regs_layout,
--
-- .has_phy_dp_com_ctrl = true,
-- .is_dual_lane_phy = true,
--
-- .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
-- .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
-- .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
-- .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
--};
--
--static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = {
-- .usb_cfg = &sm8150_usb3phy_cfg,
-- .dp_cfg = &sc8180x_dpphy_cfg,
--};
--
--static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
-- .type = PHY_TYPE_USB3,
-- .nlanes = 1,
--
-- .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-- .tx_tbl = sm8150_usb3_uniphy_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),
-- .rx_tbl = sm8150_usb3_uniphy_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
-- .pcs_tbl = sm8150_usb3_uniphy_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
-- .clk_list = qmp_v4_phy_clk_l,
-- .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-- .reset_list = msm8996_usb3phy_reset_l,
-- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = qmp_v4_usb3_uniphy_regs_layout,
--
-- .start_ctrl = SERDES_START | PCS_START,
-- .pwrdn_ctrl = SW_PWRDN,
-- .phy_status = PHYSTATUS,
--
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
--};
--
--static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
-- .type = PHY_TYPE_USB3,
-- .nlanes = 1,
--
-- .serdes_tbl = sm8150_usb3_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
-- .tx_tbl = sm8250_usb3_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl),
-- .rx_tbl = sm8250_usb3_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl),
-- .pcs_tbl = sm8250_usb3_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
-- .clk_list = qmp_v4_sm8250_usbphy_clk_l,
-- .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
-- .reset_list = msm8996_usb3phy_reset_l,
-- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = qmp_v4_usb3phy_regs_layout,
--
-- .start_ctrl = SERDES_START | PCS_START,
-- .pwrdn_ctrl = SW_PWRDN,
-- .phy_status = PHYSTATUS,
--
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
--
-- .has_phy_dp_com_ctrl = true,
-- .is_dual_lane_phy = true,
--};
--
--static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
-- .type = PHY_TYPE_USB3,
-- .nlanes = 1,
--
-- .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-- .tx_tbl = sm8250_usb3_uniphy_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),
-- .rx_tbl = sm8250_usb3_uniphy_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
-- .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
-- .clk_list = qmp_v4_phy_clk_l,
-- .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-- .reset_list = msm8996_usb3phy_reset_l,
-- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = qmp_v4_usb3_uniphy_regs_layout,
--
-- .start_ctrl = SERDES_START | PCS_START,
-- .pwrdn_ctrl = SW_PWRDN,
-- .phy_status = PHYSTATUS,
--
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
--};
--
--static const struct qmp_phy_cfg sm8250_dpphy_cfg = {
-- .type = PHY_TYPE_DP,
-- .nlanes = 1,
--
-- .serdes_tbl = qmp_v4_dp_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
-- .tx_tbl = qmp_v4_dp_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
--
-- .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
-- .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
-- .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
-- .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
-- .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
-- .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
-- .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
-- .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
--
-- .clk_list = qmp_v4_phy_clk_l,
-- .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-- .reset_list = msm8996_usb3phy_reset_l,
-- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = qmp_v4_usb3phy_regs_layout,
--
-- .has_phy_dp_com_ctrl = true,
-- .is_dual_lane_phy = true,
--
-- .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
-- .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
-- .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
-- .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
--};
--
--static const struct qmp_phy_combo_cfg sm8250_usb3dpphy_cfg = {
-- .usb_cfg = &sm8250_usb3phy_cfg,
-- .dp_cfg = &sm8250_dpphy_cfg,
--};
--
--static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
-- .type = PHY_TYPE_USB3,
-- .nlanes = 1,
--
-- .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-- .tx_tbl = sdx55_usb3_uniphy_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl),
-- .rx_tbl = sdx55_usb3_uniphy_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),
-- .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
-- .clk_list = qmp_v4_sdx55_usbphy_clk_l,
-- .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
-- .reset_list = msm8996_usb3phy_reset_l,
-- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = qmp_v4_usb3_uniphy_regs_layout,
--
-- .start_ctrl = SERDES_START | PCS_START,
-- .pwrdn_ctrl = SW_PWRDN,
-- .phy_status = PHYSTATUS,
--
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
--};
--
--static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
-- .type = PHY_TYPE_PCIE,
-- .nlanes = 2,
--
-- .serdes_tbl = sdx55_qmp_pcie_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl),
-- .tx_tbl = sdx55_qmp_pcie_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl),
-- .rx_tbl = sdx55_qmp_pcie_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl),
-- .pcs_tbl = sdx55_qmp_pcie_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl),
-- .pcs_misc_tbl = sdx55_qmp_pcie_pcs_misc_tbl,
-- .pcs_misc_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl),
-- .clk_list = sdm845_pciephy_clk_l,
-- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-- .reset_list = sdm845_pciephy_reset_l,
-- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = sm8250_pcie_regs_layout,
--
-- .start_ctrl = PCS_START | SERDES_START,
-- .pwrdn_ctrl = SW_PWRDN,
-- .phy_status = PHYSTATUS_4_20,
--
-- .is_dual_lane_phy = true,
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = 995, /* us */
-- .pwrdn_delay_max = 1005, /* us */
-+/**
-+ * struct qmp_phy - per-lane phy descriptor
-+ *
-+ * @phy: generic phy
-+ * @cfg: phy specific configuration
-+ * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
-+ * @tx: iomapped memory space for lane's tx
-+ * @rx: iomapped memory space for lane's rx
-+ * @pcs: iomapped memory space for lane's pcs
-+ * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
-+ * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
-+ * @pcs_misc: iomapped memory space for lane's pcs_misc
-+ * @pipe_clk: pipe clock
-+ * @index: lane index
-+ * @qmp: QMP phy to which this lane belongs
-+ * @lane_rst: lane's reset controller
-+ * @mode: current PHY mode
-+ * @dp_aux_cfg: Display port aux config
-+ * @dp_opts: Display port optional config
-+ * @dp_clks: Display port clocks
-+ */
-+struct qmp_phy {
-+ struct phy *phy;
-+ const struct qmp_phy_cfg *cfg;
-+ void __iomem *serdes;
-+ void __iomem *tx;
-+ void __iomem *rx;
-+ void __iomem *pcs;
-+ void __iomem *tx2;
-+ void __iomem *rx2;
-+ void __iomem *pcs_misc;
-+ struct clk *pipe_clk;
-+ unsigned int index;
-+ struct qcom_qmp *qmp;
-+ struct reset_control *lane_rst;
-+ enum phy_mode mode;
-+ unsigned int dp_aux_cfg;
-+ struct phy_configure_opts_dp dp_opts;
-+ struct qmp_phy_dp_clks *dp_clks;
- };
-
--static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
-- .type = PHY_TYPE_USB3,
-- .nlanes = 1,
--
-- .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-- .tx_tbl = sdx65_usb3_uniphy_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl),
-- .rx_tbl = sdx65_usb3_uniphy_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl),
-- .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
-- .clk_list = qmp_v4_sdx55_usbphy_clk_l,
-- .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
-- .reset_list = msm8996_usb3phy_reset_l,
-- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = sm8350_usb3_uniphy_regs_layout,
-+struct qmp_phy_dp_clks {
-+ struct qmp_phy *qphy;
-+ struct clk_hw dp_link_hw;
-+ struct clk_hw dp_pixel_hw;
-+};
-
-- .start_ctrl = SERDES_START | PCS_START,
-- .pwrdn_ctrl = SW_PWRDN,
-- .phy_status = PHYSTATUS,
-+/**
-+ * struct qcom_qmp - structure holding QMP phy block attributes
-+ *
-+ * @dev: device
-+ * @dp_com: iomapped memory space for phy's dp_com control block
-+ *
-+ * @clks: array of clocks required by phy
-+ * @resets: array of resets required by phy
-+ * @vregs: regulator supplies bulk data
-+ *
-+ * @phys: array of per-lane phy descriptors
-+ * @phy_mutex: mutex lock for PHY common block initialization
-+ * @init_count: phy common block initialization count
-+ * @ufs_reset: optional UFS PHY reset handle
-+ */
-+struct qcom_qmp {
-+ struct device *dev;
-+ void __iomem *dp_com;
-
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
--};
-+ struct clk_bulk_data *clks;
-+ struct reset_control **resets;
-+ struct regulator_bulk_data *vregs;
-
--static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
-- .type = PHY_TYPE_UFS,
-- .nlanes = 2,
--
-- .serdes_tbl = sm8350_ufsphy_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
-- .tx_tbl = sm8350_ufsphy_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
-- .rx_tbl = sm8350_ufsphy_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
-- .pcs_tbl = sm8350_ufsphy_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
-- .clk_list = sdm845_ufs_phy_clk_l,
-- .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = sm8150_ufsphy_regs_layout,
-+ struct qmp_phy **phys;
-
-- .start_ctrl = SERDES_START,
-- .pwrdn_ctrl = SW_PWRDN,
-- .phy_status = PHYSTATUS,
-+ struct mutex phy_mutex;
-+ int init_count;
-
-- .is_dual_lane_phy = true,
-+ struct reset_control *ufs_reset;
- };
-
--static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
-- .type = PHY_TYPE_USB3,
-- .nlanes = 1,
--
-- .serdes_tbl = sm8150_usb3_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
-- .tx_tbl = sm8350_usb3_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl),
-- .rx_tbl = sm8350_usb3_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl),
-- .pcs_tbl = sm8350_usb3_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl),
-- .clk_list = qmp_v4_sm8250_usbphy_clk_l,
-- .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
-- .reset_list = msm8996_usb3phy_reset_l,
-- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = qmp_v4_usb3phy_regs_layout,
-+static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
-+{
-+ u32 reg;
-
-- .start_ctrl = SERDES_START | PCS_START,
-- .pwrdn_ctrl = SW_PWRDN,
-- .phy_status = PHYSTATUS,
-+ reg = readl(base + offset);
-+ reg |= val;
-+ writel(reg, base + offset);
-
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+ /* ensure that above write is through */
-+ readl(base + offset);
-+}
-
-- .has_phy_dp_com_ctrl = true,
-- .is_dual_lane_phy = true,
--};
-+static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
-+{
-+ u32 reg;
-
--static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
-- .type = PHY_TYPE_USB3,
-- .nlanes = 1,
--
-- .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-- .tx_tbl = sm8350_usb3_uniphy_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),
-- .rx_tbl = sm8350_usb3_uniphy_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),
-- .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
-- .clk_list = qmp_v4_phy_clk_l,
-- .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-- .reset_list = msm8996_usb3phy_reset_l,
-- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = sm8350_usb3_uniphy_regs_layout,
-+ reg = readl(base + offset);
-+ reg &= ~val;
-+ writel(reg, base + offset);
-
-- .start_ctrl = SERDES_START | PCS_START,
-- .pwrdn_ctrl = SW_PWRDN,
-- .phy_status = PHYSTATUS,
-+ /* ensure that above write is through */
-+ readl(base + offset);
-+}
-
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+/* list of clocks required by phy */
-+static const char * const msm8996_phy_clk_l[] = {
-+ "aux", "cfg_ahb", "ref",
- };
-
--static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
-- .type = PHY_TYPE_UFS,
-- .nlanes = 2,
--
-- .serdes_tbl = sm8350_ufsphy_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
-- .tx_tbl = sm8350_ufsphy_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
-- .rx_tbl = sm8350_ufsphy_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
-- .pcs_tbl = sm8350_ufsphy_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
-- .clk_list = sm8450_ufs_phy_clk_l,
-- .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = sm8150_ufsphy_regs_layout,
--
-- .start_ctrl = SERDES_START,
-- .pwrdn_ctrl = SW_PWRDN,
-- .phy_status = PHYSTATUS,
--
-- .is_dual_lane_phy = true,
-+/* list of resets */
-+static const char * const msm8996_pciephy_reset_l[] = {
-+ "phy", "common", "cfg",
- };
-
--static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
-- .type = PHY_TYPE_PCIE,
-- .nlanes = 1,
--
-- .serdes_tbl = sm8450_qmp_gen3x1_pcie_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl),
-- .tx_tbl = sm8450_qmp_gen3x1_pcie_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl),
-- .rx_tbl = sm8450_qmp_gen3x1_pcie_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl),
-- .pcs_tbl = sm8450_qmp_gen3x1_pcie_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl),
-- .pcs_misc_tbl = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
-- .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
-- .clk_list = sdm845_pciephy_clk_l,
-- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-- .reset_list = sdm845_pciephy_reset_l,
-- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = sm8250_pcie_regs_layout,
--
-- .start_ctrl = SERDES_START | PCS_START,
-- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-- .phy_status = PHYSTATUS,
--
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = 995, /* us */
-- .pwrdn_delay_max = 1005, /* us */
-+/* list of regulators */
-+static const char * const qmp_phy_vreg_l[] = {
-+ "vdda-phy", "vdda-pll",
- };
-
--static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
-- .type = PHY_TYPE_PCIE,
-- .nlanes = 2,
--
-- .serdes_tbl = sm8450_qmp_gen4x2_pcie_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl),
-- .tx_tbl = sm8450_qmp_gen4x2_pcie_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl),
-- .rx_tbl = sm8450_qmp_gen4x2_pcie_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl),
-- .pcs_tbl = sm8450_qmp_gen4x2_pcie_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl),
-- .pcs_misc_tbl = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl,
-- .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl),
-- .clk_list = sdm845_pciephy_clk_l,
-- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-- .reset_list = sdm845_pciephy_reset_l,
-- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = sm8250_pcie_regs_layout,
--
-- .start_ctrl = SERDES_START | PCS_START,
-- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-- .phy_status = PHYSTATUS_4_20,
--
-- .is_dual_lane_phy = true,
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = 995, /* us */
-- .pwrdn_delay_max = 1005, /* us */
--};
-+static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 3,
-
--static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
-- .type = PHY_TYPE_USB3,
-- .nlanes = 1,
--
-- .serdes_tbl = qcm2290_usb3_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl),
-- .tx_tbl = qcm2290_usb3_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl),
-- .rx_tbl = qcm2290_usb3_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(qcm2290_usb3_rx_tbl),
-- .pcs_tbl = qcm2290_usb3_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl),
-- .clk_list = qcm2290_usb3phy_clk_l,
-- .num_clks = ARRAY_SIZE(qcm2290_usb3phy_clk_l),
-- .reset_list = qcm2290_usb3phy_reset_l,
-- .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
-+ .serdes_tbl = msm8996_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
-+ .tx_tbl = msm8996_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8996_pcie_tx_tbl),
-+ .rx_tbl = msm8996_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(msm8996_pcie_rx_tbl),
-+ .pcs_tbl = msm8996_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
-+ .clk_list = msm8996_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-+ .reset_list = msm8996_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l),
- .vreg_list = qmp_phy_vreg_l,
- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = qcm2290_usb3phy_regs_layout,
-+ .regs = pciephy_regs_layout,
-
-- .start_ctrl = SERDES_START | PCS_START,
-- .pwrdn_ctrl = SW_PWRDN,
-+ .start_ctrl = PCS_START | PLL_READY_GATE_EN,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .mask_com_pcs_ready = PCS_READY,
- .phy_status = PHYSTATUS,
-
-- .is_dual_lane_phy = true,
-+ .has_phy_com_ctrl = true,
-+ .has_lane_rst = true,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
- };
-
- static void qcom_qmp_phy_configure_lane(void __iomem *base,
-@@ -4589,457 +572,10 @@ static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
- return 0;
- }
-
--static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy)
--{
-- writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
-- DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
-- qphy->pcs + QSERDES_DP_PHY_PD_CTL);
--
-- /* Turn on BIAS current for PHY/PLL */
-- writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
-- QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
-- qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
--
-- writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
--
-- writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
-- DP_PHY_PD_CTL_LANE_0_1_PWRDN |
-- DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
-- DP_PHY_PD_CTL_DP_CLAMP_EN,
-- qphy->pcs + QSERDES_DP_PHY_PD_CTL);
--
-- writel(QSERDES_V3_COM_BIAS_EN |
-- QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
-- QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL |
-- QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
-- qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
--
-- writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
-- writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-- writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
-- writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
-- writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
-- writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
-- writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
-- writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
-- writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
-- writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
-- qphy->dp_aux_cfg = 0;
--
-- writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
-- PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
-- PHY_AUX_REQ_ERR_MASK,
-- qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
--}
--
--static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = {
-- { 0x00, 0x0c, 0x15, 0x1a },
-- { 0x02, 0x0e, 0x16, 0xff },
-- { 0x02, 0x11, 0xff, 0xff },
-- { 0x04, 0xff, 0xff, 0xff }
--};
--
--static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = {
-- { 0x02, 0x12, 0x16, 0x1a },
-- { 0x09, 0x19, 0x1f, 0xff },
-- { 0x10, 0x1f, 0xff, 0xff },
-- { 0x1f, 0xff, 0xff, 0xff }
--};
--
--static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = {
-- { 0x00, 0x0c, 0x14, 0x19 },
-- { 0x00, 0x0b, 0x12, 0xff },
-- { 0x00, 0x0b, 0xff, 0xff },
-- { 0x04, 0xff, 0xff, 0xff }
--};
--
--static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = {
-- { 0x08, 0x0f, 0x16, 0x1f },
-- { 0x11, 0x1e, 0x1f, 0xff },
-- { 0x19, 0x1f, 0xff, 0xff },
-- { 0x1f, 0xff, 0xff, 0xff }
--};
--
--static int qcom_qmp_phy_configure_dp_swing(struct qmp_phy *qphy,
-- unsigned int drv_lvl_reg, unsigned int emp_post_reg)
--{
-- const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-- unsigned int v_level = 0, p_level = 0;
-- u8 voltage_swing_cfg, pre_emphasis_cfg;
-- int i;
--
-- for (i = 0; i < dp_opts->lanes; i++) {
-- v_level = max(v_level, dp_opts->voltage[i]);
-- p_level = max(p_level, dp_opts->pre[i]);
-- }
--
-- if (dp_opts->link_rate <= 2700) {
-- voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level];
-- pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level];
-- } else {
-- voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr3_hbr2[v_level][p_level];
-- pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr3_hbr2[v_level][p_level];
-- }
--
-- /* TODO: Move check to config check */
-- if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF)
-- return -EINVAL;
--
-- /* Enable MUX to use Cursor values from these registers */
-- voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
-- pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
--
-- writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg);
-- writel(pre_emphasis_cfg, qphy->tx + emp_post_reg);
-- writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg);
-- writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg);
--
-- return 0;
--}
--
--static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy)
--{
-- const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-- u32 bias_en, drvr_en;
--
-- if (qcom_qmp_phy_configure_dp_swing(qphy,
-- QSERDES_V3_TX_TX_DRV_LVL,
-- QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0)
-- return;
--
-- if (dp_opts->lanes == 1) {
-- bias_en = 0x3e;
-- drvr_en = 0x13;
-- } else {
-- bias_en = 0x3f;
-- drvr_en = 0x10;
-- }
--
-- writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN);
-- writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
-- writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN);
-- writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
--}
--
--static bool qcom_qmp_phy_configure_dp_mode(struct qmp_phy *qphy)
--{
-- u32 val;
-- bool reverse = false;
--
-- val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
-- DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN;
--
-- /*
-- * TODO: Assume orientation is CC1 for now and two lanes, need to
-- * use type-c connector to understand orientation and lanes.
-- *
-- * Otherwise val changes to be like below if this code understood
-- * the orientation of the type-c cable.
-- *
-- * if (lane_cnt == 4 || orientation == ORIENTATION_CC2)
-- * val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN;
-- * if (lane_cnt == 4 || orientation == ORIENTATION_CC1)
-- * val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
-- * if (orientation == ORIENTATION_CC2)
-- * writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
-- */
-- val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
-- writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
--
-- writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE);
--
-- return reverse;
--}
--
--static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy)
--{
-- const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
-- const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-- u32 phy_vco_div, status;
-- unsigned long pixel_freq;
--
-- qcom_qmp_phy_configure_dp_mode(qphy);
--
-- writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
-- writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
--
-- switch (dp_opts->link_rate) {
-- case 1620:
-- phy_vco_div = 0x1;
-- pixel_freq = 1620000000UL / 2;
-- break;
-- case 2700:
-- phy_vco_div = 0x1;
-- pixel_freq = 2700000000UL / 2;
-- break;
-- case 5400:
-- phy_vco_div = 0x2;
-- pixel_freq = 5400000000UL / 4;
-- break;
-- case 8100:
-- phy_vco_div = 0x0;
-- pixel_freq = 8100000000UL / 6;
-- break;
-- default:
-- /* Other link rates aren't supported */
-- return -EINVAL;
-- }
-- writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV);
--
-- clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
-- clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
--
-- writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
-- writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
-- writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
-- writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
-- writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
--
-- writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL);
--
-- if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS,
-- status,
-- ((status & BIT(0)) > 0),
-- 500,
-- 10000))
-- return -ETIMEDOUT;
--
-- writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
--
-- if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
-- status,
-- ((status & BIT(1)) > 0),
-- 500,
-- 10000))
-- return -ETIMEDOUT;
--
-- writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
-- udelay(2000);
-- writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
--
-- return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
-- status,
-- ((status & BIT(1)) > 0),
-- 500,
-- 10000);
--}
--
--/*
-- * We need to calibrate the aux setting here as many times
-- * as the caller tries
-- */
--static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy)
--{
-- static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d };
-- u8 val;
--
-- qphy->dp_aux_cfg++;
-- qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
-- val = cfg1_settings[qphy->dp_aux_cfg];
--
-- writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
--
-- return 0;
--}
--
--static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy)
--{
-- writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
-- DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
-- qphy->pcs + QSERDES_DP_PHY_PD_CTL);
--
-- /* Turn on BIAS current for PHY/PLL */
-- writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN);
--
-- writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
-- writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-- writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
-- writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
-- writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
-- writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
-- writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
-- writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
-- writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
-- writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
-- qphy->dp_aux_cfg = 0;
--
-- writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
-- PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
-- PHY_AUX_REQ_ERR_MASK,
-- qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
--}
--
--static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy)
--{
-- /* Program default values before writing proper values */
-- writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
-- writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
--
-- writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
-- writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
--
-- qcom_qmp_phy_configure_dp_swing(qphy,
-- QSERDES_V4_TX_TX_DRV_LVL,
-- QSERDES_V4_TX_TX_EMP_POST1_LVL);
--}
--
--static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy)
--{
-- const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
-- const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-- u32 phy_vco_div, status;
-- unsigned long pixel_freq;
-- u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
-- bool reverse;
--
-- writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1);
--
-- reverse = qcom_qmp_phy_configure_dp_mode(qphy);
--
-- writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-- writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
--
-- writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL);
-- writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL);
--
-- switch (dp_opts->link_rate) {
-- case 1620:
-- phy_vco_div = 0x1;
-- pixel_freq = 1620000000UL / 2;
-- break;
-- case 2700:
-- phy_vco_div = 0x1;
-- pixel_freq = 2700000000UL / 2;
-- break;
-- case 5400:
-- phy_vco_div = 0x2;
-- pixel_freq = 5400000000UL / 4;
-- break;
-- case 8100:
-- phy_vco_div = 0x0;
-- pixel_freq = 8100000000UL / 6;
-- break;
-- default:
-- /* Other link rates aren't supported */
-- return -EINVAL;
-- }
-- writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV);
--
-- clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
-- clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
--
-- writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
-- writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
-- writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
-- writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
--
-- writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL);
--
-- if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS,
-- status,
-- ((status & BIT(0)) > 0),
-- 500,
-- 10000))
-- return -ETIMEDOUT;
--
-- if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
-- status,
-- ((status & BIT(0)) > 0),
-- 500,
-- 10000))
-- return -ETIMEDOUT;
--
-- if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
-- status,
-- ((status & BIT(1)) > 0),
-- 500,
-- 10000))
-- return -ETIMEDOUT;
--
-- writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
--
-- if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
-- status,
-- ((status & BIT(0)) > 0),
-- 500,
-- 10000))
-- return -ETIMEDOUT;
--
-- if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
-- status,
-- ((status & BIT(1)) > 0),
-- 500,
-- 10000))
-- return -ETIMEDOUT;
--
-- /*
-- * At least for 7nm DP PHY this has to be done after enabling link
-- * clock.
-- */
--
-- if (dp_opts->lanes == 1) {
-- bias0_en = reverse ? 0x3e : 0x15;
-- bias1_en = reverse ? 0x15 : 0x3e;
-- drvr0_en = reverse ? 0x13 : 0x10;
-- drvr1_en = reverse ? 0x10 : 0x13;
-- } else if (dp_opts->lanes == 2) {
-- bias0_en = reverse ? 0x3f : 0x15;
-- bias1_en = reverse ? 0x15 : 0x3f;
-- drvr0_en = 0x10;
-- drvr1_en = 0x10;
-- } else {
-- bias0_en = 0x3f;
-- bias1_en = 0x3f;
-- drvr0_en = 0x10;
-- drvr1_en = 0x10;
-- }
--
-- writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN);
-- writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
-- writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN);
-- writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
--
-- writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
-- udelay(2000);
-- writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
--
-- if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
-- status,
-- ((status & BIT(1)) > 0),
-- 500,
-- 10000))
-- return -ETIMEDOUT;
--
-- writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV);
-- writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV);
--
-- writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
-- writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
--
-- writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
-- writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
--
-- return 0;
--}
--
- /*
- * We need to calibrate the aux setting here as many times
- * as the caller tries
- */
--static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy)
--{
-- static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d };
-- u8 val;
--
-- qphy->dp_aux_cfg++;
-- qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
-- val = cfg1_settings[qphy->dp_aux_cfg];
--
-- writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
--
-- return 0;
--}
--
- static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
- {
- const struct phy_configure_opts_dp *dp_opts = &opts->dp;
-@@ -6021,161 +1557,13 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
-
- static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
- {
-- .compatible = "qcom,ipq8074-qmp-usb3-phy",
-- .data = &ipq8074_usb3phy_cfg,
-- }, {
- .compatible = "qcom,msm8996-qmp-pcie-phy",
- .data = &msm8996_pciephy_cfg,
-- }, {
-- .compatible = "qcom,msm8996-qmp-ufs-phy",
-- .data = &msm8996_ufs_cfg,
-- }, {
-- .compatible = "qcom,msm8996-qmp-usb3-phy",
-- .data = &msm8996_usb3phy_cfg,
-- }, {
-- .compatible = "qcom,msm8998-qmp-pcie-phy",
-- .data = &msm8998_pciephy_cfg,
-- }, {
-- .compatible = "qcom,msm8998-qmp-ufs-phy",
-- .data = &sdm845_ufsphy_cfg,
-- }, {
-- .compatible = "qcom,ipq8074-qmp-pcie-phy",
-- .data = &ipq8074_pciephy_cfg,
-- }, {
-- .compatible = "qcom,ipq6018-qmp-pcie-phy",
-- .data = &ipq6018_pciephy_cfg,
-- }, {
-- .compatible = "qcom,ipq6018-qmp-usb3-phy",
-- .data = &ipq8074_usb3phy_cfg,
-- }, {
-- .compatible = "qcom,sc7180-qmp-usb3-phy",
-- .data = &sc7180_usb3phy_cfg,
-- }, {
-- .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
-- /* It's a combo phy */
-- }, {
-- .compatible = "qcom,sc8180x-qmp-pcie-phy",
-- .data = &sc8180x_pciephy_cfg,
-- }, {
-- .compatible = "qcom,sc8180x-qmp-ufs-phy",
-- .data = &sm8150_ufsphy_cfg,
-- }, {
-- .compatible = "qcom,sc8280xp-qmp-ufs-phy",
-- .data = &sm8350_ufsphy_cfg,
-- }, {
-- .compatible = "qcom,sc8180x-qmp-usb3-phy",
-- .data = &sm8150_usb3phy_cfg,
-- }, {
-- .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
-- /* It's a combo phy */
-- }, {
-- .compatible = "qcom,sdm845-qhp-pcie-phy",
-- .data = &sdm845_qhp_pciephy_cfg,
-- }, {
-- .compatible = "qcom,sdm845-qmp-pcie-phy",
-- .data = &sdm845_qmp_pciephy_cfg,
-- }, {
-- .compatible = "qcom,sdm845-qmp-usb3-phy",
-- .data = &qmp_v3_usb3phy_cfg,
-- }, {
-- .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
-- .data = &qmp_v3_usb3_uniphy_cfg,
-- }, {
-- .compatible = "qcom,sdm845-qmp-ufs-phy",
-- .data = &sdm845_ufsphy_cfg,
-- }, {
-- .compatible = "qcom,msm8998-qmp-usb3-phy",
-- .data = &msm8998_usb3phy_cfg,
-- }, {
-- .compatible = "qcom,sm6115-qmp-ufs-phy",
-- .data = &sm6115_ufsphy_cfg,
-- }, {
-- .compatible = "qcom,sm6350-qmp-ufs-phy",
-- .data = &sdm845_ufsphy_cfg,
-- }, {
-- .compatible = "qcom,sm8150-qmp-ufs-phy",
-- .data = &sm8150_ufsphy_cfg,
-- }, {
-- .compatible = "qcom,sm8250-qmp-ufs-phy",
-- .data = &sm8150_ufsphy_cfg,
-- }, {
-- .compatible = "qcom,sm8150-qmp-usb3-phy",
-- .data = &sm8150_usb3phy_cfg,
-- }, {
-- .compatible = "qcom,sm8150-qmp-usb3-uni-phy",
-- .data = &sm8150_usb3_uniphy_cfg,
-- }, {
-- .compatible = "qcom,sm8250-qmp-usb3-phy",
-- .data = &sm8250_usb3phy_cfg,
-- }, {
-- .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
-- /* It's a combo phy */
-- }, {
-- .compatible = "qcom,sm8250-qmp-usb3-uni-phy",
-- .data = &sm8250_usb3_uniphy_cfg,
-- }, {
-- .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
-- .data = &sm8250_qmp_gen3x1_pciephy_cfg,
-- }, {
-- .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
-- .data = &sm8250_qmp_gen3x2_pciephy_cfg,
-- }, {
-- .compatible = "qcom,sm8350-qmp-ufs-phy",
-- .data = &sm8350_ufsphy_cfg,
-- }, {
-- .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
-- .data = &sm8250_qmp_gen3x2_pciephy_cfg,
-- }, {
-- .compatible = "qcom,sdx55-qmp-pcie-phy",
-- .data = &sdx55_qmp_pciephy_cfg,
-- }, {
-- .compatible = "qcom,sdx55-qmp-usb3-uni-phy",
-- .data = &sdx55_usb3_uniphy_cfg,
-- }, {
-- .compatible = "qcom,sdx65-qmp-usb3-uni-phy",
-- .data = &sdx65_usb3_uniphy_cfg,
-- }, {
-- .compatible = "qcom,sm8350-qmp-usb3-phy",
-- .data = &sm8350_usb3phy_cfg,
-- }, {
-- .compatible = "qcom,sm8350-qmp-usb3-uni-phy",
-- .data = &sm8350_usb3_uniphy_cfg,
-- }, {
-- .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
-- .data = &sm8450_qmp_gen3x1_pciephy_cfg,
-- }, {
-- .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
-- .data = &sm8450_qmp_gen4x2_pciephy_cfg,
-- }, {
-- .compatible = "qcom,sm8450-qmp-ufs-phy",
-- .data = &sm8450_ufsphy_cfg,
-- }, {
-- .compatible = "qcom,sm8450-qmp-usb3-phy",
-- .data = &sm8350_usb3phy_cfg,
-- }, {
-- .compatible = "qcom,qcm2290-qmp-usb3-phy",
-- .data = &qcm2290_usb3phy_cfg,
- },
- { },
- };
- MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
-
--static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = {
-- {
-- .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
-- .data = &sc7180_usb3dpphy_cfg,
-- },
-- {
-- .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
-- .data = &sm8250_usb3dpphy_cfg,
-- },
-- {
-- .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
-- .data = &sc8180x_usb3dpphy_cfg,
-- },
-- { }
--};
--
- static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
- SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
- qcom_qmp_phy_runtime_resume, NULL)
-@@ -6206,20 +1594,8 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
-
- /* Get the specific init parameters of QMP phy */
- cfg = of_device_get_match_data(dev);
-- if (!cfg) {
-- const struct of_device_id *match;
--
-- match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev);
-- if (!match)
-- return -EINVAL;
--
-- combo_cfg = match->data;
-- if (!combo_cfg)
-- return -EINVAL;
--
-- usb_cfg = combo_cfg->usb_cfg;
-- cfg = usb_cfg; /* Setup clks and regulators */
-- }
-+ if (!cfg)
-+ return -EINVAL;
-
- /* per PHY serdes; usually located at base address */
- usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0);
-@@ -6337,7 +1713,7 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
- static struct platform_driver qcom_qmp_phy_driver = {
- .probe = qcom_qmp_phy_probe,
- .driver = {
-- .name = "qcom-qmp-phy",
-+ .name = "qcom-qmp-msm8996-pcie-phy",
- .pm = &qcom_qmp_phy_pm_ops,
- .of_match_table = qcom_qmp_phy_of_match_table,
- },
-@@ -6346,5 +1722,5 @@ static struct platform_driver qcom_qmp_phy_driver = {
- module_platform_driver(qcom_qmp_phy_driver);
-
- MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
--MODULE_DESCRIPTION("Qualcomm QMP PHY driver");
-+MODULE_DESCRIPTION("Qualcomm QMP MSM8996 PCIe PHY driver");
- MODULE_LICENSE("GPL v2");
---
-2.35.1
-
+++ /dev/null
-From a417a6ed8d18b2f57eb322f8470fc9268b3cf36e Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Wed, 8 Jun 2022 00:31:49 +0300
-Subject: phy: qcom-qmp-pcie-msm8996: drop support for non-PCIe PHY types
-
-From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-
-[ Upstream commit f575ac2d64e7cedb2d70acd5baa359da216cf718 ]
-
-Drop remaining support for PHY types other than PCIe.
-
-Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> # UFS, PCIe and USB on SC8180X
-Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Link: https://lore.kernel.org/r/20220607213203.2819885-17-dmitry.baryshkov@linaro.org
-Signed-off-by: Vinod Koul <vkoul@kernel.org>
-Stable-dep-of: 1f69ededf8e8 ("phy: qcom-qmp-pcie-msm8996: fix memleak on probe deferral")
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- .../phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 532 ++----------------
- 1 file changed, 43 insertions(+), 489 deletions(-)
-
-diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
-index 1741a5675f9a..02e5ae7fa213 100644
---- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
-+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
-@@ -510,7 +510,6 @@ static int qcom_qmp_phy_pcie_msm8996_serdes_init(struct qmp_phy *qphy)
- struct qcom_qmp *qmp = qphy->qmp;
- const struct qmp_phy_cfg *cfg = qphy->cfg;
- void __iomem *serdes = qphy->serdes;
-- const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
- const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
- int serdes_tbl_num = cfg->serdes_tbl_num;
- int ret;
-@@ -520,35 +519,6 @@ static int qcom_qmp_phy_pcie_msm8996_serdes_init(struct qmp_phy *qphy)
- qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
- cfg->serdes_tbl_num_sec);
-
-- if (cfg->type == PHY_TYPE_DP) {
-- switch (dp_opts->link_rate) {
-- case 1620:
-- qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs,
-- cfg->serdes_tbl_rbr,
-- cfg->serdes_tbl_rbr_num);
-- break;
-- case 2700:
-- qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs,
-- cfg->serdes_tbl_hbr,
-- cfg->serdes_tbl_hbr_num);
-- break;
-- case 5400:
-- qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs,
-- cfg->serdes_tbl_hbr2,
-- cfg->serdes_tbl_hbr2_num);
-- break;
-- case 8100:
-- qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs,
-- cfg->serdes_tbl_hbr3,
-- cfg->serdes_tbl_hbr3_num);
-- break;
-- default:
-- /* Other link rates aren't supported */
-- return -EINVAL;
-- }
-- }
--
--
- if (cfg->has_phy_com_ctrl) {
- void __iomem *status;
- unsigned int mask, val;
-@@ -572,36 +542,6 @@ static int qcom_qmp_phy_pcie_msm8996_serdes_init(struct qmp_phy *qphy)
- return 0;
- }
-
--/*
-- * We need to calibrate the aux setting here as many times
-- * as the caller tries
-- */
--static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
--{
-- const struct phy_configure_opts_dp *dp_opts = &opts->dp;
-- struct qmp_phy *qphy = phy_get_drvdata(phy);
-- const struct qmp_phy_cfg *cfg = qphy->cfg;
--
-- memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts));
-- if (qphy->dp_opts.set_voltages) {
-- cfg->configure_dp_tx(qphy);
-- qphy->dp_opts.set_voltages = 0;
-- }
--
-- return 0;
--}
--
--static int qcom_qmp_dp_phy_calibrate(struct phy *phy)
--{
-- struct qmp_phy *qphy = phy_get_drvdata(phy);
-- const struct qmp_phy_cfg *cfg = qphy->cfg;
--
-- if (cfg->calibrate_dp_phy)
-- return cfg->calibrate_dp_phy(qphy);
--
-- return 0;
--}
--
- static int qcom_qmp_phy_pcie_msm8996_com_init(struct qmp_phy *qphy)
- {
- struct qcom_qmp *qmp = qphy->qmp;
-@@ -771,9 +711,6 @@ static int qcom_qmp_phy_pcie_msm8996_init(struct phy *phy)
- if (ret)
- return ret;
-
-- if (cfg->type == PHY_TYPE_DP)
-- cfg->dp_aux_init(qphy);
--
- return 0;
- }
-
-@@ -824,10 +761,6 @@ static int qcom_qmp_phy_pcie_msm8996_power_on(struct phy *phy)
- cfg->tx_tbl_num_sec, 2);
- }
-
-- /* Configure special DP tx tunings */
-- if (cfg->type == PHY_TYPE_DP)
-- cfg->configure_dp_tx(qphy);
--
- qcom_qmp_phy_pcie_msm8996_configure_lane(rx, cfg->regs,
- cfg->rx_tbl, cfg->rx_tbl_num, 1);
- if (cfg->rx_tbl_sec)
-@@ -843,15 +776,10 @@ static int qcom_qmp_phy_pcie_msm8996_power_on(struct phy *phy)
- cfg->rx_tbl_num_sec, 2);
- }
-
-- /* Configure link rate, swing, etc. */
-- if (cfg->type == PHY_TYPE_DP) {
-- cfg->configure_dp_phy(qphy);
-- } else {
-- qcom_qmp_phy_pcie_msm8996_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
-- if (cfg->pcs_tbl_sec)
-- qcom_qmp_phy_pcie_msm8996_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
-- cfg->pcs_tbl_num_sec);
-- }
-+ qcom_qmp_phy_pcie_msm8996_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
-+ if (cfg->pcs_tbl_sec)
-+ qcom_qmp_phy_pcie_msm8996_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
-+ cfg->pcs_tbl_num_sec);
-
- ret = reset_control_deassert(qmp->ufs_reset);
- if (ret)
-@@ -867,36 +795,28 @@ static int qcom_qmp_phy_pcie_msm8996_power_on(struct phy *phy)
- * Pull out PHY from POWER DOWN state.
- * This is active low enable signal to power-down PHY.
- */
-- if(cfg->type == PHY_TYPE_PCIE)
-- qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
-+ qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
-
- if (cfg->has_pwrdn_delay)
- usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
-
-- if (cfg->type != PHY_TYPE_DP) {
-- /* Pull PHY out of reset state */
-- if (!cfg->no_pcs_sw_reset)
-- qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
-- /* start SerDes and Phy-Coding-Sublayer */
-- qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
--
-- if (cfg->type == PHY_TYPE_UFS) {
-- status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
-- mask = PCS_READY;
-- ready = PCS_READY;
-- } else {
-- status = pcs + cfg->regs[QPHY_PCS_STATUS];
-- mask = cfg->phy_status;
-- ready = 0;
-- }
-+ /* Pull PHY out of reset state */
-+ if (!cfg->no_pcs_sw_reset)
-+ qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
-+ /* start SerDes and Phy-Coding-Sublayer */
-+ qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
-
-- ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
-- PHY_INIT_COMPLETE_TIMEOUT);
-- if (ret) {
-- dev_err(qmp->dev, "phy initialization timed-out\n");
-- goto err_disable_pipe_clk;
-- }
-+ status = pcs + cfg->regs[QPHY_PCS_STATUS];
-+ mask = cfg->phy_status;
-+ ready = 0;
-+
-+ ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
-+ PHY_INIT_COMPLETE_TIMEOUT);
-+ if (ret) {
-+ dev_err(qmp->dev, "phy initialization timed-out\n");
-+ goto err_disable_pipe_clk;
- }
-+
- return 0;
-
- err_disable_pipe_clk:
-@@ -915,25 +835,20 @@ static int qcom_qmp_phy_pcie_msm8996_power_off(struct phy *phy)
-
- clk_disable_unprepare(qphy->pipe_clk);
-
-- if (cfg->type == PHY_TYPE_DP) {
-- /* Assert DP PHY power down */
-- writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-- } else {
-- /* PHY reset */
-- if (!cfg->no_pcs_sw_reset)
-- qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
-+ /* PHY reset */
-+ if (!cfg->no_pcs_sw_reset)
-+ qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
-
-- /* stop SerDes and Phy-Coding-Sublayer */
-- qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
-+ /* stop SerDes and Phy-Coding-Sublayer */
-+ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
-
-- /* Put PHY into POWER DOWN state: active low */
-- if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
-- qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
-- cfg->pwrdn_ctrl);
-- } else {
-- qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
-- cfg->pwrdn_ctrl);
-- }
-+ /* Put PHY into POWER DOWN state: active low */
-+ if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
-+ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
-+ cfg->pwrdn_ctrl);
-+ } else {
-+ qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
-+ cfg->pwrdn_ctrl);
- }
-
- return 0;
-@@ -987,112 +902,6 @@ static int qcom_qmp_phy_pcie_msm8996_set_mode(struct phy *phy,
- return 0;
- }
-
--static void qcom_qmp_phy_pcie_msm8996_enable_autonomous_mode(struct qmp_phy *qphy)
--{
-- const struct qmp_phy_cfg *cfg = qphy->cfg;
-- void __iomem *pcs = qphy->pcs;
-- void __iomem *pcs_misc = qphy->pcs_misc;
-- u32 intr_mask;
--
-- if (qphy->mode == PHY_MODE_USB_HOST_SS ||
-- qphy->mode == PHY_MODE_USB_DEVICE_SS)
-- intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
-- else
-- intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
--
-- /* Clear any pending interrupts status */
-- qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
-- /* Writing 1 followed by 0 clears the interrupt */
-- qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
--
-- qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
-- ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
--
-- /* Enable required PHY autonomous mode interrupts */
-- qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
--
-- /* Enable i/o clamp_n for autonomous mode */
-- if (pcs_misc)
-- qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
--}
--
--static void qcom_qmp_phy_pcie_msm8996_disable_autonomous_mode(struct qmp_phy *qphy)
--{
-- const struct qmp_phy_cfg *cfg = qphy->cfg;
-- void __iomem *pcs = qphy->pcs;
-- void __iomem *pcs_misc = qphy->pcs_misc;
--
-- /* Disable i/o clamp_n on resume for normal mode */
-- if (pcs_misc)
-- qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
--
-- qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
-- ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
--
-- qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
-- /* Writing 1 followed by 0 clears the interrupt */
-- qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
--}
--
--static int __maybe_unused qcom_qmp_phy_pcie_msm8996_runtime_suspend(struct device *dev)
--{
-- struct qcom_qmp *qmp = dev_get_drvdata(dev);
-- struct qmp_phy *qphy = qmp->phys[0];
-- const struct qmp_phy_cfg *cfg = qphy->cfg;
--
-- dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode);
--
-- /* Supported only for USB3 PHY and luckily USB3 is the first phy */
-- if (cfg->type != PHY_TYPE_USB3)
-- return 0;
--
-- if (!qmp->init_count) {
-- dev_vdbg(dev, "PHY not initialized, bailing out\n");
-- return 0;
-- }
--
-- qcom_qmp_phy_pcie_msm8996_enable_autonomous_mode(qphy);
--
-- clk_disable_unprepare(qphy->pipe_clk);
-- clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
--
-- return 0;
--}
--
--static int __maybe_unused qcom_qmp_phy_pcie_msm8996_runtime_resume(struct device *dev)
--{
-- struct qcom_qmp *qmp = dev_get_drvdata(dev);
-- struct qmp_phy *qphy = qmp->phys[0];
-- const struct qmp_phy_cfg *cfg = qphy->cfg;
-- int ret = 0;
--
-- dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode);
--
-- /* Supported only for USB3 PHY and luckily USB3 is the first phy */
-- if (cfg->type != PHY_TYPE_USB3)
-- return 0;
--
-- if (!qmp->init_count) {
-- dev_vdbg(dev, "PHY not initialized, bailing out\n");
-- return 0;
-- }
--
-- ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
-- if (ret)
-- return ret;
--
-- ret = clk_prepare_enable(qphy->pipe_clk);
-- if (ret) {
-- dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
-- clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
-- return ret;
-- }
--
-- qcom_qmp_phy_pcie_msm8996_disable_autonomous_mode(qphy);
--
-- return 0;
--}
--
- static int qcom_qmp_phy_pcie_msm8996_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
- {
- struct qcom_qmp *qmp = dev_get_drvdata(dev);
-@@ -1210,223 +1019,13 @@ static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
- return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
- }
-
--/*
-- * Display Port PLL driver block diagram for branch clocks
-- *
-- * +------------------------------+
-- * | DP_VCO_CLK |
-- * | |
-- * | +-------------------+ |
-- * | | (DP PLL/VCO) | |
-- * | +---------+---------+ |
-- * | v |
-- * | +----------+-----------+ |
-- * | | hsclk_divsel_clk_src | |
-- * | +----------+-----------+ |
-- * +------------------------------+
-- * |
-- * +---------<---------v------------>----------+
-- * | |
-- * +--------v----------------+ |
-- * | dp_phy_pll_link_clk | |
-- * | link_clk | |
-- * +--------+----------------+ |
-- * | |
-- * | |
-- * v v
-- * Input to DISPCC block |
-- * for link clk, crypto clk |
-- * and interface clock |
-- * |
-- * |
-- * +--------<------------+-----------------+---<---+
-- * | | |
-- * +----v---------+ +--------v-----+ +--------v------+
-- * | vco_divided | | vco_divided | | vco_divided |
-- * | _clk_src | | _clk_src | | _clk_src |
-- * | | | | | |
-- * |divsel_six | | divsel_two | | divsel_four |
-- * +-------+------+ +-----+--------+ +--------+------+
-- * | | |
-- * v---->----------v-------------<------v
-- * |
-- * +----------+-----------------+
-- * | dp_phy_pll_vco_div_clk |
-- * +---------+------------------+
-- * |
-- * v
-- * Input to DISPCC block
-- * for DP pixel clock
-- *
-- */
--static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw,
-- struct clk_rate_request *req)
--{
-- switch (req->rate) {
-- case 1620000000UL / 2:
-- case 2700000000UL / 2:
-- /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */
-- return 0;
-- default:
-- return -EINVAL;
-- }
--}
--
--static unsigned long
--qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
--{
-- const struct qmp_phy_dp_clks *dp_clks;
-- const struct qmp_phy *qphy;
-- const struct phy_configure_opts_dp *dp_opts;
--
-- dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw);
-- qphy = dp_clks->qphy;
-- dp_opts = &qphy->dp_opts;
--
-- switch (dp_opts->link_rate) {
-- case 1620:
-- return 1620000000UL / 2;
-- case 2700:
-- return 2700000000UL / 2;
-- case 5400:
-- return 5400000000UL / 4;
-- case 8100:
-- return 8100000000UL / 6;
-- default:
-- return 0;
-- }
--}
--
--static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = {
-- .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate,
-- .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate,
--};
--
--static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw,
-- struct clk_rate_request *req)
--{
-- switch (req->rate) {
-- case 162000000:
-- case 270000000:
-- case 540000000:
-- case 810000000:
-- return 0;
-- default:
-- return -EINVAL;
-- }
--}
--
--static unsigned long
--qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
--{
-- const struct qmp_phy_dp_clks *dp_clks;
-- const struct qmp_phy *qphy;
-- const struct phy_configure_opts_dp *dp_opts;
--
-- dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw);
-- qphy = dp_clks->qphy;
-- dp_opts = &qphy->dp_opts;
--
-- switch (dp_opts->link_rate) {
-- case 1620:
-- case 2700:
-- case 5400:
-- case 8100:
-- return dp_opts->link_rate * 100000;
-- default:
-- return 0;
-- }
--}
--
--static const struct clk_ops qcom_qmp_dp_link_clk_ops = {
-- .determine_rate = qcom_qmp_dp_link_clk_determine_rate,
-- .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate,
--};
--
--static struct clk_hw *
--qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data)
--{
-- struct qmp_phy_dp_clks *dp_clks = data;
-- unsigned int idx = clkspec->args[0];
--
-- if (idx >= 2) {
-- pr_err("%s: invalid index %u\n", __func__, idx);
-- return ERR_PTR(-EINVAL);
-- }
--
-- if (idx == 0)
-- return &dp_clks->dp_link_hw;
--
-- return &dp_clks->dp_pixel_hw;
--}
--
--static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy,
-- struct device_node *np)
--{
-- struct clk_init_data init = { };
-- struct qmp_phy_dp_clks *dp_clks;
-- char name[64];
-- int ret;
--
-- dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL);
-- if (!dp_clks)
-- return -ENOMEM;
--
-- dp_clks->qphy = qphy;
-- qphy->dp_clks = dp_clks;
--
-- snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev));
-- init.ops = &qcom_qmp_dp_link_clk_ops;
-- init.name = name;
-- dp_clks->dp_link_hw.init = &init;
-- ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw);
-- if (ret)
-- return ret;
--
-- snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev));
-- init.ops = &qcom_qmp_dp_pixel_clk_ops;
-- init.name = name;
-- dp_clks->dp_pixel_hw.init = &init;
-- ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw);
-- if (ret)
-- return ret;
--
-- ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks);
-- if (ret)
-- return ret;
--
-- /*
-- * Roll a devm action because the clock provider is the child node, but
-- * the child node is not actually a device.
-- */
-- return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
--}
--
--static const struct phy_ops qcom_qmp_phy_pcie_msm8996_gen_ops = {
-+static const struct phy_ops qcom_qmp_phy_pcie_msm8996_ops = {
- .init = qcom_qmp_phy_pcie_msm8996_enable,
- .exit = qcom_qmp_phy_pcie_msm8996_disable,
- .set_mode = qcom_qmp_phy_pcie_msm8996_set_mode,
- .owner = THIS_MODULE,
- };
-
--static const struct phy_ops qcom_qmp_phy_pcie_msm8996_dp_ops = {
-- .init = qcom_qmp_phy_pcie_msm8996_init,
-- .configure = qcom_qmp_dp_phy_configure,
-- .power_on = qcom_qmp_phy_pcie_msm8996_power_on,
-- .calibrate = qcom_qmp_dp_phy_calibrate,
-- .power_off = qcom_qmp_phy_pcie_msm8996_power_off,
-- .exit = qcom_qmp_phy_pcie_msm8996_exit,
-- .set_mode = qcom_qmp_phy_pcie_msm8996_set_mode,
-- .owner = THIS_MODULE,
--};
--
--static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
-- .power_on = qcom_qmp_phy_pcie_msm8996_enable,
-- .power_off = qcom_qmp_phy_pcie_msm8996_disable,
-- .set_mode = qcom_qmp_phy_pcie_msm8996_set_mode,
-- .owner = THIS_MODULE,
--};
--
- static void qcom_qmp_reset_control_put(void *data)
- {
- reset_control_put(data);
-@@ -1439,7 +1038,6 @@ int qcom_qmp_phy_pcie_msm8996_create(struct device *dev, struct device_node *np,
- struct qcom_qmp *qmp = dev_get_drvdata(dev);
- struct phy *generic_phy;
- struct qmp_phy *qphy;
-- const struct phy_ops *ops;
- char prop_name[MAX_PROP_NAME];
- int ret;
-
-@@ -1532,14 +1130,7 @@ int qcom_qmp_phy_pcie_msm8996_create(struct device *dev, struct device_node *np,
- return ret;
- }
-
-- if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE)
-- ops = &qcom_qmp_pcie_ufs_ops;
-- else if (cfg->type == PHY_TYPE_DP)
-- ops = &qcom_qmp_phy_pcie_msm8996_dp_ops;
-- else
-- ops = &qcom_qmp_phy_pcie_msm8996_gen_ops;
--
-- generic_phy = devm_phy_create(dev, np, ops);
-+ generic_phy = devm_phy_create(dev, np, &qcom_qmp_phy_pcie_msm8996_ops);
- if (IS_ERR(generic_phy)) {
- ret = PTR_ERR(generic_phy);
- dev_err(dev, "failed to create qphy %d\n", ret);
-@@ -1564,11 +1155,6 @@ static const struct of_device_id qcom_qmp_phy_pcie_msm8996_of_match_table[] = {
- };
- MODULE_DEVICE_TABLE(of, qcom_qmp_phy_pcie_msm8996_of_match_table);
-
--static const struct dev_pm_ops qcom_qmp_phy_pcie_msm8996_pm_ops = {
-- SET_RUNTIME_PM_OPS(qcom_qmp_phy_pcie_msm8996_runtime_suspend,
-- qcom_qmp_phy_pcie_msm8996_runtime_resume, NULL)
--};
--
- static int qcom_qmp_phy_pcie_msm8996_probe(struct platform_device *pdev)
- {
- struct qcom_qmp *qmp;
-@@ -1576,12 +1162,7 @@ static int qcom_qmp_phy_pcie_msm8996_probe(struct platform_device *pdev)
- struct device_node *child;
- struct phy_provider *phy_provider;
- void __iomem *serdes;
-- void __iomem *usb_serdes;
-- void __iomem *dp_serdes = NULL;
-- const struct qmp_phy_combo_cfg *combo_cfg = NULL;
- const struct qmp_phy_cfg *cfg = NULL;
-- const struct qmp_phy_cfg *usb_cfg = NULL;
-- const struct qmp_phy_cfg *dp_cfg = NULL;
- int num, id, expected_phys;
- int ret;
-
-@@ -1598,28 +1179,18 @@ static int qcom_qmp_phy_pcie_msm8996_probe(struct platform_device *pdev)
- return -EINVAL;
-
- /* per PHY serdes; usually located at base address */
-- usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0);
-+ serdes = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(serdes))
- return PTR_ERR(serdes);
-
- /* per PHY dp_com; if PHY has dp_com control block */
-- if (combo_cfg || cfg->has_phy_dp_com_ctrl) {
-+ if (cfg->has_phy_dp_com_ctrl) {
- qmp->dp_com = devm_platform_ioremap_resource(pdev, 1);
- if (IS_ERR(qmp->dp_com))
- return PTR_ERR(qmp->dp_com);
- }
-
-- if (combo_cfg) {
-- /* Only two serdes for combo PHY */
-- dp_serdes = devm_platform_ioremap_resource(pdev, 2);
-- if (IS_ERR(dp_serdes))
-- return PTR_ERR(dp_serdes);
--
-- dp_cfg = combo_cfg->dp_cfg;
-- expected_phys = 2;
-- } else {
-- expected_phys = cfg->nlanes;
-- }
-+ expected_phys = cfg->nlanes;
-
- mutex_init(&qmp->phy_mutex);
-
-@@ -1658,14 +1229,6 @@ static int qcom_qmp_phy_pcie_msm8996_probe(struct platform_device *pdev)
-
- id = 0;
- for_each_available_child_of_node(dev->of_node, child) {
-- if (of_node_name_eq(child, "dp-phy")) {
-- cfg = dp_cfg;
-- serdes = dp_serdes;
-- } else if (of_node_name_eq(child, "usb3-phy")) {
-- cfg = usb_cfg;
-- serdes = usb_serdes;
-- }
--
- /* Create per-lane phy */
- ret = qcom_qmp_phy_pcie_msm8996_create(dev, child, id, serdes, cfg);
- if (ret) {
-@@ -1678,21 +1241,13 @@ static int qcom_qmp_phy_pcie_msm8996_probe(struct platform_device *pdev)
- * Register the pipe clock provided by phy.
- * See function description to see details of this pipe clock.
- */
-- if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) {
-- ret = phy_pipe_clk_register(qmp, child);
-- if (ret) {
-- dev_err(qmp->dev,
-- "failed to register pipe clock source\n");
-- goto err_node_put;
-- }
-- } else if (cfg->type == PHY_TYPE_DP) {
-- ret = phy_dp_clks_register(qmp, qmp->phys[id], child);
-- if (ret) {
-- dev_err(qmp->dev,
-- "failed to register DP clock source\n");
-- goto err_node_put;
-- }
-+ ret = phy_pipe_clk_register(qmp, child);
-+ if (ret) {
-+ dev_err(qmp->dev,
-+ "failed to register pipe clock source\n");
-+ goto err_node_put;
- }
-+
- id++;
- }
-
-@@ -1714,7 +1269,6 @@ static struct platform_driver qcom_qmp_phy_pcie_msm8996_driver = {
- .probe = qcom_qmp_phy_pcie_msm8996_probe,
- .driver = {
- .name = "qcom-qmp-msm8996-pcie-phy",
-- .pm = &qcom_qmp_phy_pcie_msm8996_pm_ops,
- .of_match_table = qcom_qmp_phy_pcie_msm8996_of_match_table,
- },
- };
---
-2.35.1
-
+++ /dev/null
-From 75a813b667769bc3b67572376483a5d1a4c5f6f3 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Wed, 8 Jun 2022 00:31:44 +0300
-Subject: phy: qcom-qmp-usb: change symbol prefix to qcom_qmp_phy_usb
-
-From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-
-[ Upstream commit 09b492a379402395f646c6db2e16cdac1fc2229d ]
-
-Change all symbol names to start with qcom_qmp_phy_usb_ rather than old
-qcom_qmp_phy_
-
-Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> # UFS, PCIe and USB on SC8180X
-Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Link: https://lore.kernel.org/r/20220607213203.2819885-12-dmitry.baryshkov@linaro.org
-Signed-off-by: Vinod Koul <vkoul@kernel.org>
-Stable-dep-of: a5d6b1ac56cb ("phy: qcom-qmp-usb: fix memleak on probe deferral")
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 158 ++++++++++++------------
- 1 file changed, 79 insertions(+), 79 deletions(-)
-
-diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
-index e147182afea7..2ae13b4485b6 100644
---- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
-+++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
-@@ -2023,7 +2023,7 @@ static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
- .is_dual_lane_phy = true,
- };
-
--static void qcom_qmp_phy_configure_lane(void __iomem *base,
-+static void qcom_qmp_phy_usb_configure_lane(void __iomem *base,
- const unsigned int *regs,
- const struct qmp_phy_init_tbl tbl[],
- int num,
-@@ -2046,15 +2046,15 @@ static void qcom_qmp_phy_configure_lane(void __iomem *base,
- }
- }
-
--static void qcom_qmp_phy_configure(void __iomem *base,
-+static void qcom_qmp_phy_usb_configure(void __iomem *base,
- const unsigned int *regs,
- const struct qmp_phy_init_tbl tbl[],
- int num)
- {
-- qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff);
-+ qcom_qmp_phy_usb_configure_lane(base, regs, tbl, num, 0xff);
- }
-
--static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
-+static int qcom_qmp_phy_usb_serdes_init(struct qmp_phy *qphy)
- {
- struct qcom_qmp *qmp = qphy->qmp;
- const struct qmp_phy_cfg *cfg = qphy->cfg;
-@@ -2064,30 +2064,30 @@ static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
- int serdes_tbl_num = cfg->serdes_tbl_num;
- int ret;
-
-- qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
-+ qcom_qmp_phy_usb_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
- if (cfg->serdes_tbl_sec)
-- qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
-+ qcom_qmp_phy_usb_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
- cfg->serdes_tbl_num_sec);
-
- if (cfg->type == PHY_TYPE_DP) {
- switch (dp_opts->link_rate) {
- case 1620:
-- qcom_qmp_phy_configure(serdes, cfg->regs,
-+ qcom_qmp_phy_usb_configure(serdes, cfg->regs,
- cfg->serdes_tbl_rbr,
- cfg->serdes_tbl_rbr_num);
- break;
- case 2700:
-- qcom_qmp_phy_configure(serdes, cfg->regs,
-+ qcom_qmp_phy_usb_configure(serdes, cfg->regs,
- cfg->serdes_tbl_hbr,
- cfg->serdes_tbl_hbr_num);
- break;
- case 5400:
-- qcom_qmp_phy_configure(serdes, cfg->regs,
-+ qcom_qmp_phy_usb_configure(serdes, cfg->regs,
- cfg->serdes_tbl_hbr2,
- cfg->serdes_tbl_hbr2_num);
- break;
- case 8100:
-- qcom_qmp_phy_configure(serdes, cfg->regs,
-+ qcom_qmp_phy_usb_configure(serdes, cfg->regs,
- cfg->serdes_tbl_hbr3,
- cfg->serdes_tbl_hbr3_num);
- break;
-@@ -2147,7 +2147,7 @@ static int qcom_qmp_dp_phy_calibrate(struct phy *phy)
- return 0;
- }
-
--static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
-+static int qcom_qmp_phy_usb_com_init(struct qmp_phy *qphy)
- {
- struct qcom_qmp *qmp = qphy->qmp;
- const struct qmp_phy_cfg *cfg = qphy->cfg;
-@@ -2242,7 +2242,7 @@ static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
- return ret;
- }
-
--static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy)
-+static int qcom_qmp_phy_usb_com_exit(struct qmp_phy *qphy)
- {
- struct qcom_qmp *qmp = qphy->qmp;
- const struct qmp_phy_cfg *cfg = qphy->cfg;
-@@ -2277,7 +2277,7 @@ static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy)
- return 0;
- }
-
--static int qcom_qmp_phy_init(struct phy *phy)
-+static int qcom_qmp_phy_usb_init(struct phy *phy)
- {
- struct qmp_phy *qphy = phy_get_drvdata(phy);
- struct qcom_qmp *qmp = qphy->qmp;
-@@ -2312,7 +2312,7 @@ static int qcom_qmp_phy_init(struct phy *phy)
- return ret;
- }
-
-- ret = qcom_qmp_phy_com_init(qphy);
-+ ret = qcom_qmp_phy_usb_com_init(qphy);
- if (ret)
- return ret;
-
-@@ -2322,7 +2322,7 @@ static int qcom_qmp_phy_init(struct phy *phy)
- return 0;
- }
-
--static int qcom_qmp_phy_power_on(struct phy *phy)
-+static int qcom_qmp_phy_usb_power_on(struct phy *phy)
- {
- struct qmp_phy *qphy = phy_get_drvdata(phy);
- struct qcom_qmp *qmp = qphy->qmp;
-@@ -2335,7 +2335,7 @@ static int qcom_qmp_phy_power_on(struct phy *phy)
- unsigned int mask, val, ready;
- int ret;
-
-- qcom_qmp_phy_serdes_init(qphy);
-+ qcom_qmp_phy_usb_serdes_init(qphy);
-
- if (cfg->has_lane_rst) {
- ret = reset_control_deassert(qphy->lane_rst);
-@@ -2353,18 +2353,18 @@ static int qcom_qmp_phy_power_on(struct phy *phy)
- }
-
- /* Tx, Rx, and PCS configurations */
-- qcom_qmp_phy_configure_lane(tx, cfg->regs,
-+ qcom_qmp_phy_usb_configure_lane(tx, cfg->regs,
- cfg->tx_tbl, cfg->tx_tbl_num, 1);
- if (cfg->tx_tbl_sec)
-- qcom_qmp_phy_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
-+ qcom_qmp_phy_usb_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
- cfg->tx_tbl_num_sec, 1);
-
- /* Configuration for other LANE for USB-DP combo PHY */
- if (cfg->is_dual_lane_phy) {
-- qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
-+ qcom_qmp_phy_usb_configure_lane(qphy->tx2, cfg->regs,
- cfg->tx_tbl, cfg->tx_tbl_num, 2);
- if (cfg->tx_tbl_sec)
-- qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
-+ qcom_qmp_phy_usb_configure_lane(qphy->tx2, cfg->regs,
- cfg->tx_tbl_sec,
- cfg->tx_tbl_num_sec, 2);
- }
-@@ -2373,17 +2373,17 @@ static int qcom_qmp_phy_power_on(struct phy *phy)
- if (cfg->type == PHY_TYPE_DP)
- cfg->configure_dp_tx(qphy);
-
-- qcom_qmp_phy_configure_lane(rx, cfg->regs,
-+ qcom_qmp_phy_usb_configure_lane(rx, cfg->regs,
- cfg->rx_tbl, cfg->rx_tbl_num, 1);
- if (cfg->rx_tbl_sec)
-- qcom_qmp_phy_configure_lane(rx, cfg->regs,
-+ qcom_qmp_phy_usb_configure_lane(rx, cfg->regs,
- cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1);
-
- if (cfg->is_dual_lane_phy) {
-- qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
-+ qcom_qmp_phy_usb_configure_lane(qphy->rx2, cfg->regs,
- cfg->rx_tbl, cfg->rx_tbl_num, 2);
- if (cfg->rx_tbl_sec)
-- qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
-+ qcom_qmp_phy_usb_configure_lane(qphy->rx2, cfg->regs,
- cfg->rx_tbl_sec,
- cfg->rx_tbl_num_sec, 2);
- }
-@@ -2392,9 +2392,9 @@ static int qcom_qmp_phy_power_on(struct phy *phy)
- if (cfg->type == PHY_TYPE_DP) {
- cfg->configure_dp_phy(qphy);
- } else {
-- qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
-+ qcom_qmp_phy_usb_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
- if (cfg->pcs_tbl_sec)
-- qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
-+ qcom_qmp_phy_usb_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
- cfg->pcs_tbl_num_sec);
- }
-
-@@ -2402,10 +2402,10 @@ static int qcom_qmp_phy_power_on(struct phy *phy)
- if (ret)
- goto err_disable_pipe_clk;
-
-- qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
-+ qcom_qmp_phy_usb_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
- cfg->pcs_misc_tbl_num);
- if (cfg->pcs_misc_tbl_sec)
-- qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
-+ qcom_qmp_phy_usb_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
- cfg->pcs_misc_tbl_num_sec);
-
- /*
-@@ -2453,7 +2453,7 @@ static int qcom_qmp_phy_power_on(struct phy *phy)
- return ret;
- }
-
--static int qcom_qmp_phy_power_off(struct phy *phy)
-+static int qcom_qmp_phy_usb_power_off(struct phy *phy)
- {
- struct qmp_phy *qphy = phy_get_drvdata(phy);
- const struct qmp_phy_cfg *cfg = qphy->cfg;
-@@ -2484,7 +2484,7 @@ static int qcom_qmp_phy_power_off(struct phy *phy)
- return 0;
- }
-
--static int qcom_qmp_phy_exit(struct phy *phy)
-+static int qcom_qmp_phy_usb_exit(struct phy *phy)
- {
- struct qmp_phy *qphy = phy_get_drvdata(phy);
- const struct qmp_phy_cfg *cfg = qphy->cfg;
-@@ -2492,37 +2492,37 @@ static int qcom_qmp_phy_exit(struct phy *phy)
- if (cfg->has_lane_rst)
- reset_control_assert(qphy->lane_rst);
-
-- qcom_qmp_phy_com_exit(qphy);
-+ qcom_qmp_phy_usb_com_exit(qphy);
-
- return 0;
- }
-
--static int qcom_qmp_phy_enable(struct phy *phy)
-+static int qcom_qmp_phy_usb_enable(struct phy *phy)
- {
- int ret;
-
-- ret = qcom_qmp_phy_init(phy);
-+ ret = qcom_qmp_phy_usb_init(phy);
- if (ret)
- return ret;
-
-- ret = qcom_qmp_phy_power_on(phy);
-+ ret = qcom_qmp_phy_usb_power_on(phy);
- if (ret)
-- qcom_qmp_phy_exit(phy);
-+ qcom_qmp_phy_usb_exit(phy);
-
- return ret;
- }
-
--static int qcom_qmp_phy_disable(struct phy *phy)
-+static int qcom_qmp_phy_usb_disable(struct phy *phy)
- {
- int ret;
-
-- ret = qcom_qmp_phy_power_off(phy);
-+ ret = qcom_qmp_phy_usb_power_off(phy);
- if (ret)
- return ret;
-- return qcom_qmp_phy_exit(phy);
-+ return qcom_qmp_phy_usb_exit(phy);
- }
-
--static int qcom_qmp_phy_set_mode(struct phy *phy,
-+static int qcom_qmp_phy_usb_set_mode(struct phy *phy,
- enum phy_mode mode, int submode)
- {
- struct qmp_phy *qphy = phy_get_drvdata(phy);
-@@ -2532,7 +2532,7 @@ static int qcom_qmp_phy_set_mode(struct phy *phy,
- return 0;
- }
-
--static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
-+static void qcom_qmp_phy_usb_enable_autonomous_mode(struct qmp_phy *qphy)
- {
- const struct qmp_phy_cfg *cfg = qphy->cfg;
- void __iomem *pcs = qphy->pcs;
-@@ -2561,7 +2561,7 @@ static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
- qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
- }
-
--static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
-+static void qcom_qmp_phy_usb_disable_autonomous_mode(struct qmp_phy *qphy)
- {
- const struct qmp_phy_cfg *cfg = qphy->cfg;
- void __iomem *pcs = qphy->pcs;
-@@ -2579,7 +2579,7 @@ static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
- qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
- }
-
--static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
-+static int __maybe_unused qcom_qmp_phy_usb_runtime_suspend(struct device *dev)
- {
- struct qcom_qmp *qmp = dev_get_drvdata(dev);
- struct qmp_phy *qphy = qmp->phys[0];
-@@ -2596,7 +2596,7 @@ static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
- return 0;
- }
-
-- qcom_qmp_phy_enable_autonomous_mode(qphy);
-+ qcom_qmp_phy_usb_enable_autonomous_mode(qphy);
-
- clk_disable_unprepare(qphy->pipe_clk);
- clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
-@@ -2604,7 +2604,7 @@ static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
- return 0;
- }
-
--static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
-+static int __maybe_unused qcom_qmp_phy_usb_runtime_resume(struct device *dev)
- {
- struct qcom_qmp *qmp = dev_get_drvdata(dev);
- struct qmp_phy *qphy = qmp->phys[0];
-@@ -2633,12 +2633,12 @@ static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
- return ret;
- }
-
-- qcom_qmp_phy_disable_autonomous_mode(qphy);
-+ qcom_qmp_phy_usb_disable_autonomous_mode(qphy);
-
- return 0;
- }
-
--static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
-+static int qcom_qmp_phy_usb_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
- {
- struct qcom_qmp *qmp = dev_get_drvdata(dev);
- int num = cfg->num_vregs;
-@@ -2654,7 +2654,7 @@ static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *
- return devm_regulator_bulk_get(dev, num, qmp->vregs);
- }
-
--static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
-+static int qcom_qmp_phy_usb_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
- {
- struct qcom_qmp *qmp = dev_get_drvdata(dev);
- int i;
-@@ -2679,7 +2679,7 @@ static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg
- return 0;
- }
-
--static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
-+static int qcom_qmp_phy_usb_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
- {
- struct qcom_qmp *qmp = dev_get_drvdata(dev);
- int num = cfg->num_clks;
-@@ -2947,28 +2947,28 @@ static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy,
- return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
- }
-
--static const struct phy_ops qcom_qmp_phy_gen_ops = {
-- .init = qcom_qmp_phy_enable,
-- .exit = qcom_qmp_phy_disable,
-- .set_mode = qcom_qmp_phy_set_mode,
-+static const struct phy_ops qcom_qmp_phy_usb_gen_ops = {
-+ .init = qcom_qmp_phy_usb_enable,
-+ .exit = qcom_qmp_phy_usb_disable,
-+ .set_mode = qcom_qmp_phy_usb_set_mode,
- .owner = THIS_MODULE,
- };
-
--static const struct phy_ops qcom_qmp_phy_dp_ops = {
-- .init = qcom_qmp_phy_init,
-+static const struct phy_ops qcom_qmp_phy_usb_dp_ops = {
-+ .init = qcom_qmp_phy_usb_init,
- .configure = qcom_qmp_dp_phy_configure,
-- .power_on = qcom_qmp_phy_power_on,
-+ .power_on = qcom_qmp_phy_usb_power_on,
- .calibrate = qcom_qmp_dp_phy_calibrate,
-- .power_off = qcom_qmp_phy_power_off,
-- .exit = qcom_qmp_phy_exit,
-- .set_mode = qcom_qmp_phy_set_mode,
-+ .power_off = qcom_qmp_phy_usb_power_off,
-+ .exit = qcom_qmp_phy_usb_exit,
-+ .set_mode = qcom_qmp_phy_usb_set_mode,
- .owner = THIS_MODULE,
- };
-
- static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
-- .power_on = qcom_qmp_phy_enable,
-- .power_off = qcom_qmp_phy_disable,
-- .set_mode = qcom_qmp_phy_set_mode,
-+ .power_on = qcom_qmp_phy_usb_enable,
-+ .power_off = qcom_qmp_phy_usb_disable,
-+ .set_mode = qcom_qmp_phy_usb_set_mode,
- .owner = THIS_MODULE,
- };
-
-@@ -2978,7 +2978,7 @@ static void qcom_qmp_reset_control_put(void *data)
- }
-
- static
--int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
-+int qcom_qmp_phy_usb_create(struct device *dev, struct device_node *np, int id,
- void __iomem *serdes, const struct qmp_phy_cfg *cfg)
- {
- struct qcom_qmp *qmp = dev_get_drvdata(dev);
-@@ -3080,9 +3080,9 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
- if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE)
- ops = &qcom_qmp_pcie_ufs_ops;
- else if (cfg->type == PHY_TYPE_DP)
-- ops = &qcom_qmp_phy_dp_ops;
-+ ops = &qcom_qmp_phy_usb_dp_ops;
- else
-- ops = &qcom_qmp_phy_gen_ops;
-+ ops = &qcom_qmp_phy_usb_gen_ops;
-
- generic_phy = devm_phy_create(dev, np, ops);
- if (IS_ERR(generic_phy)) {
-@@ -3100,7 +3100,7 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
- return 0;
- }
-
--static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
-+static const struct of_device_id qcom_qmp_phy_usb_of_match_table[] = {
- {
- .compatible = "qcom,ipq8074-qmp-usb3-phy",
- .data = &ipq8074_usb3phy_cfg,
-@@ -3158,14 +3158,14 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
- },
- { },
- };
--MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
-+MODULE_DEVICE_TABLE(of, qcom_qmp_phy_usb_of_match_table);
-
--static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
-- SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
-- qcom_qmp_phy_runtime_resume, NULL)
-+static const struct dev_pm_ops qcom_qmp_phy_usb_pm_ops = {
-+ SET_RUNTIME_PM_OPS(qcom_qmp_phy_usb_runtime_suspend,
-+ qcom_qmp_phy_usb_runtime_resume, NULL)
- };
-
--static int qcom_qmp_phy_probe(struct platform_device *pdev)
-+static int qcom_qmp_phy_usb_probe(struct platform_device *pdev)
- {
- struct qcom_qmp *qmp;
- struct device *dev = &pdev->dev;
-@@ -3219,15 +3219,15 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
-
- mutex_init(&qmp->phy_mutex);
-
-- ret = qcom_qmp_phy_clk_init(dev, cfg);
-+ ret = qcom_qmp_phy_usb_clk_init(dev, cfg);
- if (ret)
- return ret;
-
-- ret = qcom_qmp_phy_reset_init(dev, cfg);
-+ ret = qcom_qmp_phy_usb_reset_init(dev, cfg);
- if (ret)
- return ret;
-
-- ret = qcom_qmp_phy_vreg_init(dev, cfg);
-+ ret = qcom_qmp_phy_usb_vreg_init(dev, cfg);
- if (ret) {
- if (ret != -EPROBE_DEFER)
- dev_err(dev, "failed to get regulator supplies: %d\n",
-@@ -3265,7 +3265,7 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
- }
-
- /* Create per-lane phy */
-- ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg);
-+ ret = qcom_qmp_phy_usb_create(dev, child, id, serdes, cfg);
- if (ret) {
- dev_err(dev, "failed to create lane%d phy, %d\n",
- id, ret);
-@@ -3305,16 +3305,16 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
- return ret;
- }
-
--static struct platform_driver qcom_qmp_phy_driver = {
-- .probe = qcom_qmp_phy_probe,
-+static struct platform_driver qcom_qmp_phy_usb_driver = {
-+ .probe = qcom_qmp_phy_usb_probe,
- .driver = {
- .name = "qcom-qmp-usb-phy",
-- .pm = &qcom_qmp_phy_pm_ops,
-- .of_match_table = qcom_qmp_phy_of_match_table,
-+ .pm = &qcom_qmp_phy_usb_pm_ops,
-+ .of_match_table = qcom_qmp_phy_usb_of_match_table,
- },
- };
-
--module_platform_driver(qcom_qmp_phy_driver);
-+module_platform_driver(qcom_qmp_phy_usb_driver);
-
- MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
- MODULE_DESCRIPTION("Qualcomm QMP USB PHY driver");
---
-2.35.1
-
+++ /dev/null
-From f0c162b04114d3867eff506ace5c3c27feb1ac9e Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Thu, 23 Jun 2022 13:33:14 +0200
-Subject: phy: qcom-qmp-usb: clean up pipe clock handling
-
-From: Johan Hovold <johan+linaro@kernel.org>
-
-[ Upstream commit 5d5b7d509ff85675779caeafcffa8086d7094339 ]
-
-Clean up the pipe clock handling by using dev_err_probe() to handle
-probe deferral and dropping the obsolete comment that claimed that the
-pipe clock was optional for some other PHY types.
-
-Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
-Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Link: https://lore.kernel.org/r/20220623113314.29761-4-johan+linaro@kernel.org
-Signed-off-by: Vinod Koul <vkoul@kernel.org>
-Stable-dep-of: a5d6b1ac56cb ("phy: qcom-qmp-usb: fix memleak on probe deferral")
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 15 ++-------------
- 1 file changed, 2 insertions(+), 13 deletions(-)
-
-diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
-index 9e752fce638d..687f1a534837 100644
---- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
-+++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
-@@ -2566,22 +2566,11 @@ int qcom_qmp_phy_usb_create(struct device *dev, struct device_node *np, int id,
- if (!qphy->pcs_misc)
- dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
-
-- /*
-- * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3
-- * based phys, so they essentially have pipe clock. So,
-- * we return error in case phy is USB3 or PIPE type.
-- * Otherwise, we initialize pipe clock to NULL for
-- * all phys that don't need this.
-- */
- snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
- qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name);
- if (IS_ERR(qphy->pipe_clk)) {
-- ret = PTR_ERR(qphy->pipe_clk);
-- if (ret != -EPROBE_DEFER)
-- dev_err(dev,
-- "failed to get lane%d pipe_clk, %d\n",
-- id, ret);
-- return ret;
-+ return dev_err_probe(dev, PTR_ERR(qphy->pipe_clk),
-+ "failed to get lane%d pipe clock\n", id);
- }
-
- generic_phy = devm_phy_create(dev, np, &qcom_qmp_phy_usb_ops);
---
-2.35.1
-
+++ /dev/null
-From 6b00b876de5cecb111ab9cc5b29c888ffada6368 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Wed, 8 Jun 2022 00:31:56 +0300
-Subject: phy: qcom-qmp-usb: cleanup the driver
-
-From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-
-[ Upstream commit faf83af5d59498509eb84015453073fd5e85231e ]
-
-Remove the conditionals and options that are not used by any of USB PHY
-devices.
-
-Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> # UFS, PCIe and USB on SC8180X
-Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Link: https://lore.kernel.org/r/20220607213203.2819885-24-dmitry.baryshkov@linaro.org
-Signed-off-by: Vinod Koul <vkoul@kernel.org>
-Stable-dep-of: a5d6b1ac56cb ("phy: qcom-qmp-usb: fix memleak on probe deferral")
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 214 ++----------------------
- 1 file changed, 11 insertions(+), 203 deletions(-)
-
-diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
-index 55785dcd47e0..9e752fce638d 100644
---- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
-+++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
-@@ -1359,40 +1359,12 @@ struct qmp_phy_cfg {
- /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
- const struct qmp_phy_init_tbl *serdes_tbl;
- int serdes_tbl_num;
-- const struct qmp_phy_init_tbl *serdes_tbl_sec;
-- int serdes_tbl_num_sec;
- const struct qmp_phy_init_tbl *tx_tbl;
- int tx_tbl_num;
-- const struct qmp_phy_init_tbl *tx_tbl_sec;
-- int tx_tbl_num_sec;
- const struct qmp_phy_init_tbl *rx_tbl;
- int rx_tbl_num;
-- const struct qmp_phy_init_tbl *rx_tbl_sec;
-- int rx_tbl_num_sec;
- const struct qmp_phy_init_tbl *pcs_tbl;
- int pcs_tbl_num;
-- const struct qmp_phy_init_tbl *pcs_tbl_sec;
-- int pcs_tbl_num_sec;
-- const struct qmp_phy_init_tbl *pcs_misc_tbl;
-- int pcs_misc_tbl_num;
-- const struct qmp_phy_init_tbl *pcs_misc_tbl_sec;
-- int pcs_misc_tbl_num_sec;
--
-- /* Init sequence for DP PHY block link rates */
-- const struct qmp_phy_init_tbl *serdes_tbl_rbr;
-- int serdes_tbl_rbr_num;
-- const struct qmp_phy_init_tbl *serdes_tbl_hbr;
-- int serdes_tbl_hbr_num;
-- const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
-- int serdes_tbl_hbr2_num;
-- const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
-- int serdes_tbl_hbr3_num;
--
-- /* DP PHY callbacks */
-- int (*configure_dp_phy)(struct qmp_phy *qphy);
-- void (*configure_dp_tx)(struct qmp_phy *qphy);
-- int (*calibrate_dp_phy)(struct qmp_phy *qphy);
-- void (*dp_aux_init)(struct qmp_phy *qphy);
-
- /* clock ids to be requested */
- const char * const *clk_list;
-@@ -1409,14 +1381,9 @@ struct qmp_phy_cfg {
-
- unsigned int start_ctrl;
- unsigned int pwrdn_ctrl;
-- unsigned int mask_com_pcs_ready;
- /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
- unsigned int phy_status;
-
-- /* true, if PHY has a separate PHY_COM control block */
-- bool has_phy_com_ctrl;
-- /* true, if PHY has a reset for individual lanes */
-- bool has_lane_rst;
- /* true, if PHY needs delay after POWER_DOWN */
- bool has_pwrdn_delay;
- /* power_down delay in usec */
-@@ -1427,14 +1394,6 @@ struct qmp_phy_cfg {
- bool has_phy_dp_com_ctrl;
- /* true, if PHY has secondary tx/rx lanes to be configured */
- bool is_dual_lane_phy;
--
-- /* true, if PCS block has no separate SW_RESET register */
-- bool no_pcs_sw_reset;
--};
--
--struct qmp_phy_combo_cfg {
-- const struct qmp_phy_cfg *usb_cfg;
-- const struct qmp_phy_cfg *dp_cfg;
- };
-
- /**
-@@ -1452,11 +1411,7 @@ struct qmp_phy_combo_cfg {
- * @pipe_clk: pipe clock
- * @index: lane index
- * @qmp: QMP phy to which this lane belongs
-- * @lane_rst: lane's reset controller
- * @mode: current PHY mode
-- * @dp_aux_cfg: Display port aux config
-- * @dp_opts: Display port optional config
-- * @dp_clks: Display port clocks
- */
- struct qmp_phy {
- struct phy *phy;
-@@ -1471,17 +1426,7 @@ struct qmp_phy {
- struct clk *pipe_clk;
- unsigned int index;
- struct qcom_qmp *qmp;
-- struct reset_control *lane_rst;
- enum phy_mode mode;
-- unsigned int dp_aux_cfg;
-- struct phy_configure_opts_dp dp_opts;
-- struct qmp_phy_dp_clks *dp_clks;
--};
--
--struct qmp_phy_dp_clks {
-- struct qmp_phy *qphy;
-- struct clk_hw dp_link_hw;
-- struct clk_hw dp_pixel_hw;
- };
-
- /**
-@@ -1497,7 +1442,6 @@ struct qmp_phy_dp_clks {
- * @phys: array of per-lane phy descriptors
- * @phy_mutex: mutex lock for PHY common block initialization
- * @init_count: phy common block initialization count
-- * @ufs_reset: optional UFS PHY reset handle
- */
- struct qcom_qmp {
- struct device *dev;
-@@ -1511,8 +1455,6 @@ struct qcom_qmp {
-
- struct mutex phy_mutex;
- int init_count;
--
-- struct reset_control *ufs_reset;
- };
-
- static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
-@@ -2056,37 +1998,12 @@ static void qcom_qmp_phy_usb_configure(void __iomem *base,
-
- static int qcom_qmp_phy_usb_serdes_init(struct qmp_phy *qphy)
- {
-- struct qcom_qmp *qmp = qphy->qmp;
- const struct qmp_phy_cfg *cfg = qphy->cfg;
- void __iomem *serdes = qphy->serdes;
- const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
- int serdes_tbl_num = cfg->serdes_tbl_num;
-- int ret;
-
- qcom_qmp_phy_usb_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
-- if (cfg->serdes_tbl_sec)
-- qcom_qmp_phy_usb_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
-- cfg->serdes_tbl_num_sec);
--
-- if (cfg->has_phy_com_ctrl) {
-- void __iomem *status;
-- unsigned int mask, val;
--
-- qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
-- qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
-- SERDES_START | PCS_START);
--
-- status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
-- mask = cfg->mask_com_pcs_ready;
--
-- ret = readl_poll_timeout(status, val, (val & mask), 10,
-- PHY_INIT_COMPLETE_TIMEOUT);
-- if (ret) {
-- dev_err(qmp->dev,
-- "phy common block init timed-out\n");
-- return ret;
-- }
-- }
-
- return 0;
- }
-@@ -2095,7 +2012,6 @@ static int qcom_qmp_phy_usb_com_init(struct qmp_phy *qphy)
- {
- struct qcom_qmp *qmp = qphy->qmp;
- const struct qmp_phy_cfg *cfg = qphy->cfg;
-- void __iomem *serdes = qphy->serdes;
- void __iomem *pcs = qphy->pcs;
- void __iomem *dp_com = qmp->dp_com;
- int ret, i;
-@@ -2158,18 +2074,13 @@ static int qcom_qmp_phy_usb_com_init(struct qmp_phy *qphy)
- qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
- }
-
-- if (cfg->has_phy_com_ctrl) {
-- qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
-- SW_PWRDN);
-- } else {
-- if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
-- qphy_setbits(pcs,
-- cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
-- cfg->pwrdn_ctrl);
-- else
-- qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
-- cfg->pwrdn_ctrl);
-- }
-+ if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
-+ qphy_setbits(pcs,
-+ cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
-+ cfg->pwrdn_ctrl);
-+ else
-+ qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
-+ cfg->pwrdn_ctrl);
-
- mutex_unlock(&qmp->phy_mutex);
-
-@@ -2190,7 +2101,6 @@ static int qcom_qmp_phy_usb_com_exit(struct qmp_phy *qphy)
- {
- struct qcom_qmp *qmp = qphy->qmp;
- const struct qmp_phy_cfg *cfg = qphy->cfg;
-- void __iomem *serdes = qphy->serdes;
- int i = cfg->num_resets;
-
- mutex_lock(&qmp->phy_mutex);
-@@ -2199,16 +2109,6 @@ static int qcom_qmp_phy_usb_com_exit(struct qmp_phy *qphy)
- return 0;
- }
-
-- reset_control_assert(qmp->ufs_reset);
-- if (cfg->has_phy_com_ctrl) {
-- qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
-- SERDES_START | PCS_START);
-- qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
-- SW_RESET);
-- qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
-- SW_PWRDN);
-- }
--
- while (--i >= 0)
- reset_control_assert(qmp->resets[i]);
-
-@@ -2225,37 +2125,9 @@ static int qcom_qmp_phy_usb_init(struct phy *phy)
- {
- struct qmp_phy *qphy = phy_get_drvdata(phy);
- struct qcom_qmp *qmp = qphy->qmp;
-- const struct qmp_phy_cfg *cfg = qphy->cfg;
- int ret;
- dev_vdbg(qmp->dev, "Initializing QMP phy\n");
-
-- if (cfg->no_pcs_sw_reset) {
-- /*
-- * Get UFS reset, which is delayed until now to avoid a
-- * circular dependency where UFS needs its PHY, but the PHY
-- * needs this UFS reset.
-- */
-- if (!qmp->ufs_reset) {
-- qmp->ufs_reset =
-- devm_reset_control_get_exclusive(qmp->dev,
-- "ufsphy");
--
-- if (IS_ERR(qmp->ufs_reset)) {
-- ret = PTR_ERR(qmp->ufs_reset);
-- dev_err(qmp->dev,
-- "failed to get UFS reset: %d\n",
-- ret);
--
-- qmp->ufs_reset = NULL;
-- return ret;
-- }
-- }
--
-- ret = reset_control_assert(qmp->ufs_reset);
-- if (ret)
-- return ret;
-- }
--
- ret = qcom_qmp_phy_usb_com_init(qphy);
- if (ret)
- return ret;
-@@ -2271,82 +2143,45 @@ static int qcom_qmp_phy_usb_power_on(struct phy *phy)
- void __iomem *tx = qphy->tx;
- void __iomem *rx = qphy->rx;
- void __iomem *pcs = qphy->pcs;
-- void __iomem *pcs_misc = qphy->pcs_misc;
- void __iomem *status;
- unsigned int mask, val, ready;
- int ret;
-
- qcom_qmp_phy_usb_serdes_init(qphy);
-
-- if (cfg->has_lane_rst) {
-- ret = reset_control_deassert(qphy->lane_rst);
-- if (ret) {
-- dev_err(qmp->dev, "lane%d reset deassert failed\n",
-- qphy->index);
-- return ret;
-- }
-- }
--
- ret = clk_prepare_enable(qphy->pipe_clk);
- if (ret) {
- dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
-- goto err_reset_lane;
-+ return ret;
- }
-
- /* Tx, Rx, and PCS configurations */
- qcom_qmp_phy_usb_configure_lane(tx, cfg->regs,
- cfg->tx_tbl, cfg->tx_tbl_num, 1);
-- if (cfg->tx_tbl_sec)
-- qcom_qmp_phy_usb_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
-- cfg->tx_tbl_num_sec, 1);
-
- /* Configuration for other LANE for USB-DP combo PHY */
- if (cfg->is_dual_lane_phy) {
- qcom_qmp_phy_usb_configure_lane(qphy->tx2, cfg->regs,
- cfg->tx_tbl, cfg->tx_tbl_num, 2);
-- if (cfg->tx_tbl_sec)
-- qcom_qmp_phy_usb_configure_lane(qphy->tx2, cfg->regs,
-- cfg->tx_tbl_sec,
-- cfg->tx_tbl_num_sec, 2);
- }
-
- qcom_qmp_phy_usb_configure_lane(rx, cfg->regs,
- cfg->rx_tbl, cfg->rx_tbl_num, 1);
-- if (cfg->rx_tbl_sec)
-- qcom_qmp_phy_usb_configure_lane(rx, cfg->regs,
-- cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1);
-
- if (cfg->is_dual_lane_phy) {
- qcom_qmp_phy_usb_configure_lane(qphy->rx2, cfg->regs,
- cfg->rx_tbl, cfg->rx_tbl_num, 2);
-- if (cfg->rx_tbl_sec)
-- qcom_qmp_phy_usb_configure_lane(qphy->rx2, cfg->regs,
-- cfg->rx_tbl_sec,
-- cfg->rx_tbl_num_sec, 2);
- }
-
- /* Configure link rate, swing, etc. */
- qcom_qmp_phy_usb_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
-- if (cfg->pcs_tbl_sec)
-- qcom_qmp_phy_usb_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
-- cfg->pcs_tbl_num_sec);
--
-- ret = reset_control_deassert(qmp->ufs_reset);
-- if (ret)
-- goto err_disable_pipe_clk;
--
-- qcom_qmp_phy_usb_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
-- cfg->pcs_misc_tbl_num);
-- if (cfg->pcs_misc_tbl_sec)
-- qcom_qmp_phy_usb_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
-- cfg->pcs_misc_tbl_num_sec);
-
- if (cfg->has_pwrdn_delay)
- usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
-
- /* Pull PHY out of reset state */
-- if (!cfg->no_pcs_sw_reset)
-- qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
-+ qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
-+
- /* start SerDes and Phy-Coding-Sublayer */
- qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
-
-@@ -2365,9 +2200,6 @@ static int qcom_qmp_phy_usb_power_on(struct phy *phy)
-
- err_disable_pipe_clk:
- clk_disable_unprepare(qphy->pipe_clk);
--err_reset_lane:
-- if (cfg->has_lane_rst)
-- reset_control_assert(qphy->lane_rst);
-
- return ret;
- }
-@@ -2380,8 +2212,7 @@ static int qcom_qmp_phy_usb_power_off(struct phy *phy)
- clk_disable_unprepare(qphy->pipe_clk);
-
- /* PHY reset */
-- if (!cfg->no_pcs_sw_reset)
-- qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
-+ qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
-
- /* stop SerDes and Phy-Coding-Sublayer */
- qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
-@@ -2401,10 +2232,6 @@ static int qcom_qmp_phy_usb_power_off(struct phy *phy)
- static int qcom_qmp_phy_usb_exit(struct phy *phy)
- {
- struct qmp_phy *qphy = phy_get_drvdata(phy);
-- const struct qmp_phy_cfg *cfg = qphy->cfg;
--
-- if (cfg->has_lane_rst)
-- reset_control_assert(qphy->lane_rst);
-
- qcom_qmp_phy_usb_com_exit(qphy);
-
-@@ -2676,11 +2503,6 @@ static const struct phy_ops qcom_qmp_phy_usb_ops = {
- .owner = THIS_MODULE,
- };
-
--static void qcom_qmp_reset_control_put(void *data)
--{
-- reset_control_put(data);
--}
--
- static
- int qcom_qmp_phy_usb_create(struct device *dev, struct device_node *np, int id,
- void __iomem *serdes, const struct qmp_phy_cfg *cfg)
-@@ -2762,20 +2584,6 @@ int qcom_qmp_phy_usb_create(struct device *dev, struct device_node *np, int id,
- return ret;
- }
-
-- /* Get lane reset, if any */
-- if (cfg->has_lane_rst) {
-- snprintf(prop_name, sizeof(prop_name), "lane%d", id);
-- qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name);
-- if (IS_ERR(qphy->lane_rst)) {
-- dev_err(dev, "failed to get lane%d reset\n", id);
-- return PTR_ERR(qphy->lane_rst);
-- }
-- ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put,
-- qphy->lane_rst);
-- if (ret)
-- return ret;
-- }
--
- generic_phy = devm_phy_create(dev, np, &qcom_qmp_phy_usb_ops);
- if (IS_ERR(generic_phy)) {
- ret = PTR_ERR(generic_phy);
---
-2.35.1
-
+++ /dev/null
-From e054c8a8f4fa42be0dc61fc951088435fe56b64a Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Wed, 7 Sep 2022 13:07:21 +0200
-Subject: phy: qcom-qmp-usb: disable runtime PM on unbind
-
-From: Johan Hovold <johan+linaro@kernel.org>
-
-[ Upstream commit e57655e66806750785f9121c98a962404d02395b ]
-
-Make sure to disable runtime PM also on driver unbind.
-
-Fixes: ac0d239936bd ("phy: qcom-qmp: Add support for runtime PM").
-Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
-Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Link: https://lore.kernel.org/r/20220907110728.19092-10-johan+linaro@kernel.org
-Signed-off-by: Vinod Koul <vkoul@kernel.org>
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 7 +++----
- 1 file changed, 3 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
-index c7309e981bfb..dcf8a8764e17 100644
---- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
-+++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
-@@ -6273,7 +6273,9 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
- return -ENOMEM;
-
- pm_runtime_set_active(dev);
-- pm_runtime_enable(dev);
-+ ret = devm_pm_runtime_enable(dev);
-+ if (ret)
-+ return ret;
- /*
- * Prevent runtime pm from being ON by default. Users can enable
- * it using power/control in sysfs.
-@@ -6323,13 +6325,10 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
- phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
- if (!IS_ERR(phy_provider))
- dev_info(dev, "Registered Qcom-QMP phy\n");
-- else
-- pm_runtime_disable(dev);
-
- return PTR_ERR_OR_ZERO(phy_provider);
-
- err_node_put:
-- pm_runtime_disable(dev);
- of_node_put(child);
- return ret;
- }
---
-2.35.1
-
+++ /dev/null
-From 052d5010c0d652291b70fdaa48dc81ca5203317d Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Wed, 8 Jun 2022 00:31:38 +0300
-Subject: phy: qcom-qmp-usb: drop all non-USB compatibles support
-
-From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-
-[ Upstream commit 8c924330ebe3e5c6f41bad0e5118875848843864 ]
-
-Drop support for all non-USB compatibles from the new qmp-usb driver.
-
-Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> # UFS, PCIe and USB on SC8180X
-Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Link: https://lore.kernel.org/r/20220607213203.2819885-6-dmitry.baryshkov@linaro.org
-Signed-off-by: Vinod Koul <vkoul@kernel.org>
-Stable-dep-of: a5d6b1ac56cb ("phy: qcom-qmp-usb: fix memleak on probe deferral")
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 3108 +----------------------
- 1 file changed, 40 insertions(+), 3068 deletions(-)
-
-diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
-index dcf8a8764e17..e147182afea7 100644
---- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
-+++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
-@@ -141,34 +141,6 @@ enum qphy_reg_layout {
- QPHY_LAYOUT_SIZE
- };
-
--static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-- [QPHY_START_CTRL] = 0x00,
-- [QPHY_PCS_READY_STATUS] = 0x168,
--};
--
--static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = {
-- [QPHY_SW_RESET] = 0x00,
-- [QPHY_START_CTRL] = 0x44,
-- [QPHY_PCS_STATUS] = 0x14,
-- [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
--};
--
--static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
-- [QPHY_COM_SW_RESET] = 0x400,
-- [QPHY_COM_POWER_DOWN_CONTROL] = 0x404,
-- [QPHY_COM_START_CONTROL] = 0x408,
-- [QPHY_COM_PCS_READY_STATUS] = 0x448,
-- [QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8,
-- [QPHY_FLL_CNTRL1] = 0xc4,
-- [QPHY_FLL_CNTRL2] = 0xc8,
-- [QPHY_FLL_CNT_VAL_L] = 0xcc,
-- [QPHY_FLL_CNT_VAL_H_TOL] = 0xd0,
-- [QPHY_FLL_MAN_CODE] = 0xd4,
-- [QPHY_SW_RESET] = 0x00,
-- [QPHY_START_CTRL] = 0x08,
-- [QPHY_PCS_STATUS] = 0x174,
--};
--
- static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
- [QPHY_FLL_CNTRL1] = 0xc0,
- [QPHY_FLL_CNTRL2] = 0xc4,
-@@ -192,18 +164,6 @@ static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
- [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
- };
-
--static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
-- [QPHY_SW_RESET] = 0x00,
-- [QPHY_START_CTRL] = 0x08,
-- [QPHY_PCS_STATUS] = 0x174,
--};
--
--static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
-- [QPHY_SW_RESET] = 0x00,
-- [QPHY_START_CTRL] = 0x08,
-- [QPHY_PCS_STATUS] = 0x2ac,
--};
--
- static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
- [QPHY_SW_RESET] = 0x00,
- [QPHY_START_CTRL] = 0x44,
-@@ -241,29 +201,6 @@ static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
- [QPHY_PCS_MISC_TYPEC_CTRL] = 0x00,
- };
-
--static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-- [QPHY_START_CTRL] = 0x00,
-- [QPHY_PCS_READY_STATUS] = 0x160,
--};
--
--static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-- [QPHY_START_CTRL] = 0x00,
-- [QPHY_PCS_READY_STATUS] = 0x168,
--};
--
--static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = {
-- [QPHY_SW_RESET] = 0x00,
-- [QPHY_START_CTRL] = 0x44,
-- [QPHY_PCS_STATUS] = 0x14,
-- [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
--};
--
--static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-- [QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START,
-- [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS,
-- [QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET,
--};
--
- static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
- QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-@@ -339,235 +276,6 @@ static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
- };
-
--static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
-- QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
-- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
-- QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
--};
--
--static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-- QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
--};
--
--static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19),
--};
--
--static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
-- QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
--
-- QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
--
-- QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
-- QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
-- QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
-- QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
--};
--
--static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
--};
--
--static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
--};
--
--static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
--};
--
--static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
--};
--
--static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
-- QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
-- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
--};
--
--static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-- QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
--};
--
--static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
--};
--
- static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
- QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-@@ -639,414 +347,6 @@ static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
- QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
- };
-
--static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
--};
--
--static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12),
--};
--
--static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x61),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04),
--};
--
--static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01),
-- QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d),
-- QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10),
-- QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa),
-- QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-- QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
-- QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01),
-- QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
-- QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
-- QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-- QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-- QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-- QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-- QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11),
-- QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_PRE, 0x00),
-- QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_POST, 0x58),
--};
--
--static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
-- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
-- QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
-- QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
-- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
-- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
--};
--
--static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-- QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
-- QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
-- QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
-- QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
--};
--
--static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
-- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
-- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
--};
--
--static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
-- QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
-- QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
-- QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
-- QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
-- QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
-- QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
-- QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
-- QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
-- QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
-- QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
-- QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
-- QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
--};
--
--static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
--};
--
--static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
--};
--
--static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
--};
--
--static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
--
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
--
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
--
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
--
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
--};
--
--static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
--};
--
--static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07),
--};
--
--static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
--};
--
--static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = {
--};
--
--static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f),
--};
--
- static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
-@@ -1094,88 +394,6 @@ static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
- };
-
--static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
--};
--
--static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
--};
--
--static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
--};
--
--static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
--};
--
--static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08),
--};
--
--static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
--};
--
- static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-@@ -1346,175 +564,6 @@ static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
- QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
- };
-
--static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
-- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
--
-- /* Rate B */
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),
--};
--
--static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-- QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
--};
--
--static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40),
-- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E),
-- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D),
-- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B),
--};
--
--static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_RX_PWM_GEAR_BAND, 0x15),
-- QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_CTRL2, 0x6d),
-- QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_DRV_LVL, 0x0f),
-- QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_DRV_LVL, 0x02),
-- QMP_PHY_INIT_CFG(QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
-- QMP_PHY_INIT_CFG(QPHY_RX_SYM_RESYNC_CTRL, 0x03),
-- QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
-- QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
-- QMP_PHY_INIT_CFG(QPHY_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
--};
--
--static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
--
-- /* Rate B */
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
--};
--
--static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
--};
--
--static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
--};
--
--static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
--};
--
- static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
-@@ -1624,93 +673,6 @@ static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
- };
-
--static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
--
-- /* Rate B */
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
--};
--
--static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
--};
--
--static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
--
--};
--
--static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
--};
--
- static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
-@@ -2023,374 +985,44 @@ static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
--};
--
--static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
--};
--
--static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
--};
--
--static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
--};
--
--static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
--};
--
--static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
--};
--
--static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
--};
--
--static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20),
--};
--
--static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
--};
--
--static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5),
--};
--
--static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
--};
--
--static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),
--};
--
--static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
--};
--
--static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
--};
--
--static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
--};
--
--static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
--};
--
--static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
--};
--
--static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
--};
--
--static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
--};
--
--static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12),
--};
--
--static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
--};
--
--static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f),
--};
--
--static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
--};
--
--static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
- };
-
--static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f),
--};
--
--static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
-+static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
- };
-
- static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
-@@ -2440,101 +1072,6 @@ static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
- QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
- };
-
--static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22),
--};
--
--static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00),
--};
--
--static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12),
--};
--
--static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77),
-- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01),
-- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16),
-- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02),
--};
--
--static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17),
-- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13),
-- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13),
-- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01),
-- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
-- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
--};
--
- static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = {
- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
-@@ -2579,106 +1116,6 @@ static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = {
- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
- };
-
--static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
--
-- /* Rate B */
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
--};
--
--static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),
--};
--
--static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
--};
--
--static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
--};
--
- static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
-@@ -2910,215 +1347,6 @@ static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
- };
-
--static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
--};
--
--static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04),
--};
--
--static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
--};
--
--static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
--};
--
--static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
--};
--
--static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
--};
--
--static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
--};
--
--static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
--
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05),
--
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
--
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
--
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
--};
--
--/* Register names should be validated, they might be different for this PHY */
--static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99),
--};
--
--static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-- QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
-- QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
-- QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),
-- QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
--};
--
- struct qmp_phy;
-
- /* struct qmp_phy_cfg - per-PHY initialization config */
-@@ -3287,16 +1515,6 @@ struct qcom_qmp {
- struct reset_control *ufs_reset;
- };
-
--static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy);
--static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy);
--static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy);
--static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy);
--
--static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy);
--static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy);
--static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy);
--static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy);
--
- static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
- {
- u32 reg;
-@@ -3326,18 +1544,10 @@ static const char * const msm8996_phy_clk_l[] = {
- "aux", "cfg_ahb", "ref",
- };
-
--static const char * const msm8996_ufs_phy_clk_l[] = {
-- "ref",
--};
--
- static const char * const qmp_v3_phy_clk_l[] = {
- "aux", "cfg_ahb", "ref", "com_aux",
- };
-
--static const char * const sdm845_pciephy_clk_l[] = {
-- "aux", "cfg_ahb", "ref", "refgen",
--};
--
- static const char * const qmp_v4_phy_clk_l[] = {
- "aux", "ref_clk_src", "ref", "com_aux",
- };
-@@ -3347,14 +1557,6 @@ static const char * const qmp_v4_sm8250_usbphy_clk_l[] = {
- "aux", "ref_clk_src", "com_aux"
- };
-
--static const char * const sm8450_ufs_phy_clk_l[] = {
-- "qref", "ref", "ref_aux",
--};
--
--static const char * const sdm845_ufs_phy_clk_l[] = {
-- "ref", "ref_aux",
--};
--
- /* usb3 phy on sdx55 doesn't have com_aux clock */
- static const char * const qmp_v4_sdx55_usbphy_clk_l[] = {
- "aux", "cfg_ahb", "ref"
-@@ -3365,10 +1567,6 @@ static const char * const qcm2290_usb3phy_clk_l[] = {
- };
-
- /* list of resets */
--static const char * const msm8996_pciephy_reset_l[] = {
-- "phy", "common", "cfg",
--};
--
- static const char * const msm8996_usb3phy_reset_l[] = {
- "phy", "common",
- };
-@@ -3381,10 +1579,6 @@ static const char * const qcm2290_usb3phy_reset_l[] = {
- "phy_phy", "phy",
- };
-
--static const char * const sdm845_pciephy_reset_l[] = {
-- "phy",
--};
--
- /* list of regulators */
- static const char * const qmp_phy_vreg_l[] = {
- "vdda-phy", "vdda-pll",
-@@ -3415,64 +1609,6 @@ static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
- .phy_status = PHYSTATUS,
- };
-
--static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
-- .type = PHY_TYPE_PCIE,
-- .nlanes = 3,
--
-- .serdes_tbl = msm8996_pcie_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
-- .tx_tbl = msm8996_pcie_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(msm8996_pcie_tx_tbl),
-- .rx_tbl = msm8996_pcie_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(msm8996_pcie_rx_tbl),
-- .pcs_tbl = msm8996_pcie_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
-- .clk_list = msm8996_phy_clk_l,
-- .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-- .reset_list = msm8996_pciephy_reset_l,
-- .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = pciephy_regs_layout,
--
-- .start_ctrl = PCS_START | PLL_READY_GATE_EN,
-- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-- .mask_com_pcs_ready = PCS_READY,
-- .phy_status = PHYSTATUS,
--
-- .has_phy_com_ctrl = true,
-- .has_lane_rst = true,
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
--};
--
--static const struct qmp_phy_cfg msm8996_ufs_cfg = {
-- .type = PHY_TYPE_UFS,
-- .nlanes = 1,
--
-- .serdes_tbl = msm8996_ufs_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(msm8996_ufs_serdes_tbl),
-- .tx_tbl = msm8996_ufs_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(msm8996_ufs_tx_tbl),
-- .rx_tbl = msm8996_ufs_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(msm8996_ufs_rx_tbl),
--
-- .clk_list = msm8996_ufs_phy_clk_l,
-- .num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
--
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
--
-- .regs = msm8996_ufsphy_regs_layout,
--
-- .start_ctrl = SERDES_START,
-- .pwrdn_ctrl = SW_PWRDN,
-- .phy_status = PHYSTATUS,
--
-- .no_pcs_sw_reset = true,
--};
--
- static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
- .type = PHY_TYPE_USB3,
- .nlanes = 1,
-@@ -3498,214 +1634,6 @@ static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
- .phy_status = PHYSTATUS,
- };
-
--static const char * const ipq8074_pciephy_clk_l[] = {
-- "aux", "cfg_ahb",
--};
--/* list of resets */
--static const char * const ipq8074_pciephy_reset_l[] = {
-- "phy", "common",
--};
--
--static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
-- .type = PHY_TYPE_PCIE,
-- .nlanes = 1,
--
-- .serdes_tbl = ipq8074_pcie_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
-- .tx_tbl = ipq8074_pcie_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
-- .rx_tbl = ipq8074_pcie_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
-- .pcs_tbl = ipq8074_pcie_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
-- .clk_list = ipq8074_pciephy_clk_l,
-- .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
-- .reset_list = ipq8074_pciephy_reset_l,
-- .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
-- .vreg_list = NULL,
-- .num_vregs = 0,
-- .regs = pciephy_regs_layout,
--
-- .start_ctrl = SERDES_START | PCS_START,
-- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-- .phy_status = PHYSTATUS,
--
-- .has_phy_com_ctrl = false,
-- .has_lane_rst = false,
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = 995, /* us */
-- .pwrdn_delay_max = 1005, /* us */
--};
--
--static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
-- .type = PHY_TYPE_PCIE,
-- .nlanes = 1,
--
-- .serdes_tbl = ipq6018_pcie_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl),
-- .tx_tbl = ipq6018_pcie_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl),
-- .rx_tbl = ipq6018_pcie_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
-- .pcs_tbl = ipq6018_pcie_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
-- .clk_list = ipq8074_pciephy_clk_l,
-- .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
-- .reset_list = ipq8074_pciephy_reset_l,
-- .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
-- .vreg_list = NULL,
-- .num_vregs = 0,
-- .regs = ipq_pciephy_gen3_regs_layout,
--
-- .start_ctrl = SERDES_START | PCS_START,
-- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
--
-- .has_phy_com_ctrl = false,
-- .has_lane_rst = false,
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = 995, /* us */
-- .pwrdn_delay_max = 1005, /* us */
--};
--
--static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
-- .type = PHY_TYPE_PCIE,
-- .nlanes = 1,
--
-- .serdes_tbl = sdm845_qmp_pcie_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
-- .tx_tbl = sdm845_qmp_pcie_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),
-- .rx_tbl = sdm845_qmp_pcie_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),
-- .pcs_tbl = sdm845_qmp_pcie_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),
-- .pcs_misc_tbl = sdm845_qmp_pcie_pcs_misc_tbl,
-- .pcs_misc_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
-- .clk_list = sdm845_pciephy_clk_l,
-- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-- .reset_list = sdm845_pciephy_reset_l,
-- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = sdm845_qmp_pciephy_regs_layout,
--
-- .start_ctrl = PCS_START | SERDES_START,
-- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-- .phy_status = PHYSTATUS,
--
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = 995, /* us */
-- .pwrdn_delay_max = 1005, /* us */
--};
--
--static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
-- .type = PHY_TYPE_PCIE,
-- .nlanes = 1,
--
-- .serdes_tbl = sdm845_qhp_pcie_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
-- .tx_tbl = sdm845_qhp_pcie_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
-- .rx_tbl = sdm845_qhp_pcie_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl),
-- .pcs_tbl = sdm845_qhp_pcie_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
-- .clk_list = sdm845_pciephy_clk_l,
-- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-- .reset_list = sdm845_pciephy_reset_l,
-- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = sdm845_qhp_pciephy_regs_layout,
--
-- .start_ctrl = PCS_START | SERDES_START,
-- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-- .phy_status = PHYSTATUS,
--
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = 995, /* us */
-- .pwrdn_delay_max = 1005, /* us */
--};
--
--static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
-- .type = PHY_TYPE_PCIE,
-- .nlanes = 1,
--
-- .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
-- .serdes_tbl_sec = sm8250_qmp_gen3x1_pcie_serdes_tbl,
-- .serdes_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
-- .tx_tbl = sm8250_qmp_pcie_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
-- .rx_tbl = sm8250_qmp_pcie_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
-- .rx_tbl_sec = sm8250_qmp_gen3x1_pcie_rx_tbl,
-- .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),
-- .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
-- .pcs_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_tbl,
-- .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),
-- .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
-- .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
-- .pcs_misc_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,
-- .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),
-- .clk_list = sdm845_pciephy_clk_l,
-- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-- .reset_list = sdm845_pciephy_reset_l,
-- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = sm8250_pcie_regs_layout,
--
-- .start_ctrl = PCS_START | SERDES_START,
-- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-- .phy_status = PHYSTATUS,
--
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = 995, /* us */
-- .pwrdn_delay_max = 1005, /* us */
--};
--
--static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
-- .type = PHY_TYPE_PCIE,
-- .nlanes = 2,
--
-- .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
-- .tx_tbl = sm8250_qmp_pcie_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
-- .tx_tbl_sec = sm8250_qmp_gen3x2_pcie_tx_tbl,
-- .tx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),
-- .rx_tbl = sm8250_qmp_pcie_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
-- .rx_tbl_sec = sm8250_qmp_gen3x2_pcie_rx_tbl,
-- .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl),
-- .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
-- .pcs_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_tbl,
-- .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl),
-- .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
-- .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
-- .pcs_misc_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,
-- .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),
-- .clk_list = sdm845_pciephy_clk_l,
-- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-- .reset_list = sdm845_pciephy_reset_l,
-- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = sm8250_pcie_regs_layout,
--
-- .start_ctrl = PCS_START | SERDES_START,
-- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-- .phy_status = PHYSTATUS,
--
-- .is_dual_lane_phy = true,
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = 995, /* us */
-- .pwrdn_delay_max = 1005, /* us */
--};
--
- static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
- .type = PHY_TYPE_USB3,
- .nlanes = 1,
-@@ -3770,46 +1698,6 @@ static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
- .is_dual_lane_phy = true,
- };
-
--static const struct qmp_phy_cfg sc7180_dpphy_cfg = {
-- .type = PHY_TYPE_DP,
-- .nlanes = 1,
--
-- .serdes_tbl = qmp_v3_dp_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
-- .tx_tbl = qmp_v3_dp_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
--
-- .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr,
-- .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
-- .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr,
-- .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
-- .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2,
-- .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
-- .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3,
-- .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
--
-- .clk_list = qmp_v3_phy_clk_l,
-- .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-- .reset_list = sc7180_usb3phy_reset_l,
-- .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = qmp_v3_usb3phy_regs_layout,
--
-- .has_phy_dp_com_ctrl = true,
-- .is_dual_lane_phy = true,
--
-- .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init,
-- .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx,
-- .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy,
-- .calibrate_dp_phy = qcom_qmp_v3_dp_phy_calibrate,
--};
--
--static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = {
-- .usb_cfg = &sc7180_usb3phy_cfg,
-- .dp_cfg = &sc7180_dpphy_cfg,
--};
--
- static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
- .type = PHY_TYPE_USB3,
- .nlanes = 1,
-@@ -3839,82 +1727,6 @@ static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
- };
-
--static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
-- .type = PHY_TYPE_UFS,
-- .nlanes = 2,
--
-- .serdes_tbl = sdm845_ufsphy_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
-- .tx_tbl = sdm845_ufsphy_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
-- .rx_tbl = sdm845_ufsphy_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
-- .pcs_tbl = sdm845_ufsphy_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
-- .clk_list = sdm845_ufs_phy_clk_l,
-- .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = sdm845_ufsphy_regs_layout,
--
-- .start_ctrl = SERDES_START,
-- .pwrdn_ctrl = SW_PWRDN,
-- .phy_status = PHYSTATUS,
--
-- .is_dual_lane_phy = true,
-- .no_pcs_sw_reset = true,
--};
--
--static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
-- .type = PHY_TYPE_UFS,
-- .nlanes = 1,
--
-- .serdes_tbl = sm6115_ufsphy_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl),
-- .tx_tbl = sm6115_ufsphy_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_tx_tbl),
-- .rx_tbl = sm6115_ufsphy_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_rx_tbl),
-- .pcs_tbl = sm6115_ufsphy_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl),
-- .clk_list = sdm845_ufs_phy_clk_l,
-- .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = sm6115_ufsphy_regs_layout,
--
-- .start_ctrl = SERDES_START,
-- .pwrdn_ctrl = SW_PWRDN,
--
-- .is_dual_lane_phy = false,
-- .no_pcs_sw_reset = true,
--};
--
--static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
-- .type = PHY_TYPE_PCIE,
-- .nlanes = 1,
--
-- .serdes_tbl = msm8998_pcie_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
-- .tx_tbl = msm8998_pcie_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(msm8998_pcie_tx_tbl),
-- .rx_tbl = msm8998_pcie_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(msm8998_pcie_rx_tbl),
-- .pcs_tbl = msm8998_pcie_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
-- .clk_list = msm8996_phy_clk_l,
-- .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-- .reset_list = ipq8074_pciephy_reset_l,
-- .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = pciephy_regs_layout,
--
-- .start_ctrl = SERDES_START | PCS_START,
-- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-- .phy_status = PHYSTATUS,
--};
--
- static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
- .type = PHY_TYPE_USB3,
- .nlanes = 1,
-@@ -3933,38 +1745,13 @@ static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
- .vreg_list = qmp_phy_vreg_l,
- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = qmp_v3_usb3phy_regs_layout,
--
-- .start_ctrl = SERDES_START | PCS_START,
-- .pwrdn_ctrl = SW_PWRDN,
-- .phy_status = PHYSTATUS,
--
-- .is_dual_lane_phy = true,
--};
--
--static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
-- .type = PHY_TYPE_UFS,
-- .nlanes = 2,
--
-- .serdes_tbl = sm8150_ufsphy_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl),
-- .tx_tbl = sm8150_ufsphy_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx_tbl),
-- .rx_tbl = sm8150_ufsphy_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx_tbl),
-- .pcs_tbl = sm8150_ufsphy_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl),
-- .clk_list = sdm845_ufs_phy_clk_l,
-- .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = sm8150_ufsphy_regs_layout,
-+ .regs = qmp_v3_usb3phy_regs_layout,
-
-- .start_ctrl = SERDES_START,
-- .pwrdn_ctrl = SW_PWRDN,
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
- .phy_status = PHYSTATUS,
-
-- .is_dual_lane_phy = true,
-+ .is_dual_lane_phy = true,
- };
-
- static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
-@@ -4000,76 +1787,6 @@ static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
- .is_dual_lane_phy = true,
- };
-
--static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
-- .type = PHY_TYPE_PCIE,
-- .nlanes = 1,
--
-- .serdes_tbl = sc8180x_qmp_pcie_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl),
-- .tx_tbl = sc8180x_qmp_pcie_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl),
-- .rx_tbl = sc8180x_qmp_pcie_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl),
-- .pcs_tbl = sc8180x_qmp_pcie_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl),
-- .pcs_misc_tbl = sc8180x_qmp_pcie_pcs_misc_tbl,
-- .pcs_misc_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl),
-- .clk_list = sdm845_pciephy_clk_l,
-- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-- .reset_list = sdm845_pciephy_reset_l,
-- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = sm8250_pcie_regs_layout,
--
-- .start_ctrl = PCS_START | SERDES_START,
-- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
--
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = 995, /* us */
-- .pwrdn_delay_max = 1005, /* us */
--};
--
--static const struct qmp_phy_cfg sc8180x_dpphy_cfg = {
-- .type = PHY_TYPE_DP,
-- .nlanes = 1,
--
-- .serdes_tbl = qmp_v4_dp_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
-- .tx_tbl = qmp_v4_dp_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
--
-- .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
-- .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
-- .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
-- .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
-- .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
-- .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
-- .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
-- .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
--
-- .clk_list = qmp_v3_phy_clk_l,
-- .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-- .reset_list = sc7180_usb3phy_reset_l,
-- .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = qmp_v3_usb3phy_regs_layout,
--
-- .has_phy_dp_com_ctrl = true,
-- .is_dual_lane_phy = true,
--
-- .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
-- .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
-- .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
-- .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
--};
--
--static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = {
-- .usb_cfg = &sm8150_usb3phy_cfg,
-- .dp_cfg = &sc8180x_dpphy_cfg,
--};
--
- static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
- .type = PHY_TYPE_USB3,
- .nlanes = 1,
-@@ -4160,46 +1877,6 @@ static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
- };
-
--static const struct qmp_phy_cfg sm8250_dpphy_cfg = {
-- .type = PHY_TYPE_DP,
-- .nlanes = 1,
--
-- .serdes_tbl = qmp_v4_dp_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
-- .tx_tbl = qmp_v4_dp_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
--
-- .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
-- .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
-- .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
-- .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
-- .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
-- .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
-- .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
-- .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
--
-- .clk_list = qmp_v4_phy_clk_l,
-- .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-- .reset_list = msm8996_usb3phy_reset_l,
-- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = qmp_v4_usb3phy_regs_layout,
--
-- .has_phy_dp_com_ctrl = true,
-- .is_dual_lane_phy = true,
--
-- .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
-- .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
-- .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
-- .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
--};
--
--static const struct qmp_phy_combo_cfg sm8250_usb3dpphy_cfg = {
-- .usb_cfg = &sm8250_usb3phy_cfg,
-- .dp_cfg = &sm8250_dpphy_cfg,
--};
--
- static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
- .type = PHY_TYPE_USB3,
- .nlanes = 1,
-@@ -4229,38 +1906,6 @@ static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
- };
-
--static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
-- .type = PHY_TYPE_PCIE,
-- .nlanes = 2,
--
-- .serdes_tbl = sdx55_qmp_pcie_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl),
-- .tx_tbl = sdx55_qmp_pcie_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl),
-- .rx_tbl = sdx55_qmp_pcie_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl),
-- .pcs_tbl = sdx55_qmp_pcie_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl),
-- .pcs_misc_tbl = sdx55_qmp_pcie_pcs_misc_tbl,
-- .pcs_misc_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl),
-- .clk_list = sdm845_pciephy_clk_l,
-- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-- .reset_list = sdm845_pciephy_reset_l,
-- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = sm8250_pcie_regs_layout,
--
-- .start_ctrl = PCS_START | SERDES_START,
-- .pwrdn_ctrl = SW_PWRDN,
-- .phy_status = PHYSTATUS_4_20,
--
-- .is_dual_lane_phy = true,
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = 995, /* us */
-- .pwrdn_delay_max = 1005, /* us */
--};
--
- static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
- .type = PHY_TYPE_USB3,
- .nlanes = 1,
-@@ -4290,31 +1935,6 @@ static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
- };
-
--static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
-- .type = PHY_TYPE_UFS,
-- .nlanes = 2,
--
-- .serdes_tbl = sm8350_ufsphy_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
-- .tx_tbl = sm8350_ufsphy_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
-- .rx_tbl = sm8350_ufsphy_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
-- .pcs_tbl = sm8350_ufsphy_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
-- .clk_list = sdm845_ufs_phy_clk_l,
-- .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = sm8150_ufsphy_regs_layout,
--
-- .start_ctrl = SERDES_START,
-- .pwrdn_ctrl = SW_PWRDN,
-- .phy_status = PHYSTATUS,
--
-- .is_dual_lane_phy = true,
--};
--
- static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
- .type = PHY_TYPE_USB3,
- .nlanes = 1,
-@@ -4376,94 +1996,6 @@ static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
- };
-
--static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
-- .type = PHY_TYPE_UFS,
-- .nlanes = 2,
--
-- .serdes_tbl = sm8350_ufsphy_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
-- .tx_tbl = sm8350_ufsphy_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
-- .rx_tbl = sm8350_ufsphy_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
-- .pcs_tbl = sm8350_ufsphy_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
-- .clk_list = sm8450_ufs_phy_clk_l,
-- .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = sm8150_ufsphy_regs_layout,
--
-- .start_ctrl = SERDES_START,
-- .pwrdn_ctrl = SW_PWRDN,
-- .phy_status = PHYSTATUS,
--
-- .is_dual_lane_phy = true,
--};
--
--static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
-- .type = PHY_TYPE_PCIE,
-- .nlanes = 1,
--
-- .serdes_tbl = sm8450_qmp_gen3x1_pcie_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl),
-- .tx_tbl = sm8450_qmp_gen3x1_pcie_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl),
-- .rx_tbl = sm8450_qmp_gen3x1_pcie_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl),
-- .pcs_tbl = sm8450_qmp_gen3x1_pcie_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl),
-- .pcs_misc_tbl = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
-- .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
-- .clk_list = sdm845_pciephy_clk_l,
-- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-- .reset_list = sdm845_pciephy_reset_l,
-- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = sm8250_pcie_regs_layout,
--
-- .start_ctrl = SERDES_START | PCS_START,
-- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-- .phy_status = PHYSTATUS,
--
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = 995, /* us */
-- .pwrdn_delay_max = 1005, /* us */
--};
--
--static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
-- .type = PHY_TYPE_PCIE,
-- .nlanes = 2,
--
-- .serdes_tbl = sm8450_qmp_gen4x2_pcie_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl),
-- .tx_tbl = sm8450_qmp_gen4x2_pcie_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl),
-- .rx_tbl = sm8450_qmp_gen4x2_pcie_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl),
-- .pcs_tbl = sm8450_qmp_gen4x2_pcie_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl),
-- .pcs_misc_tbl = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl,
-- .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl),
-- .clk_list = sdm845_pciephy_clk_l,
-- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-- .reset_list = sdm845_pciephy_reset_l,
-- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = sm8250_pcie_regs_layout,
--
-- .start_ctrl = SERDES_START | PCS_START,
-- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-- .phy_status = PHYSTATUS_4_20,
--
-- .is_dual_lane_phy = true,
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = 995, /* us */
-- .pwrdn_delay_max = 1005, /* us */
--};
--
- static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
- .type = PHY_TYPE_USB3,
- .nlanes = 1,
-@@ -4589,457 +2121,6 @@ static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
- return 0;
- }
-
--static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy)
--{
-- writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
-- DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
-- qphy->pcs + QSERDES_DP_PHY_PD_CTL);
--
-- /* Turn on BIAS current for PHY/PLL */
-- writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
-- QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
-- qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
--
-- writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
--
-- writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
-- DP_PHY_PD_CTL_LANE_0_1_PWRDN |
-- DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
-- DP_PHY_PD_CTL_DP_CLAMP_EN,
-- qphy->pcs + QSERDES_DP_PHY_PD_CTL);
--
-- writel(QSERDES_V3_COM_BIAS_EN |
-- QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
-- QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL |
-- QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
-- qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
--
-- writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
-- writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-- writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
-- writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
-- writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
-- writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
-- writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
-- writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
-- writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
-- writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
-- qphy->dp_aux_cfg = 0;
--
-- writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
-- PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
-- PHY_AUX_REQ_ERR_MASK,
-- qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
--}
--
--static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = {
-- { 0x00, 0x0c, 0x15, 0x1a },
-- { 0x02, 0x0e, 0x16, 0xff },
-- { 0x02, 0x11, 0xff, 0xff },
-- { 0x04, 0xff, 0xff, 0xff }
--};
--
--static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = {
-- { 0x02, 0x12, 0x16, 0x1a },
-- { 0x09, 0x19, 0x1f, 0xff },
-- { 0x10, 0x1f, 0xff, 0xff },
-- { 0x1f, 0xff, 0xff, 0xff }
--};
--
--static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = {
-- { 0x00, 0x0c, 0x14, 0x19 },
-- { 0x00, 0x0b, 0x12, 0xff },
-- { 0x00, 0x0b, 0xff, 0xff },
-- { 0x04, 0xff, 0xff, 0xff }
--};
--
--static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = {
-- { 0x08, 0x0f, 0x16, 0x1f },
-- { 0x11, 0x1e, 0x1f, 0xff },
-- { 0x19, 0x1f, 0xff, 0xff },
-- { 0x1f, 0xff, 0xff, 0xff }
--};
--
--static int qcom_qmp_phy_configure_dp_swing(struct qmp_phy *qphy,
-- unsigned int drv_lvl_reg, unsigned int emp_post_reg)
--{
-- const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-- unsigned int v_level = 0, p_level = 0;
-- u8 voltage_swing_cfg, pre_emphasis_cfg;
-- int i;
--
-- for (i = 0; i < dp_opts->lanes; i++) {
-- v_level = max(v_level, dp_opts->voltage[i]);
-- p_level = max(p_level, dp_opts->pre[i]);
-- }
--
-- if (dp_opts->link_rate <= 2700) {
-- voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level];
-- pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level];
-- } else {
-- voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr3_hbr2[v_level][p_level];
-- pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr3_hbr2[v_level][p_level];
-- }
--
-- /* TODO: Move check to config check */
-- if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF)
-- return -EINVAL;
--
-- /* Enable MUX to use Cursor values from these registers */
-- voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
-- pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
--
-- writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg);
-- writel(pre_emphasis_cfg, qphy->tx + emp_post_reg);
-- writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg);
-- writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg);
--
-- return 0;
--}
--
--static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy)
--{
-- const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-- u32 bias_en, drvr_en;
--
-- if (qcom_qmp_phy_configure_dp_swing(qphy,
-- QSERDES_V3_TX_TX_DRV_LVL,
-- QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0)
-- return;
--
-- if (dp_opts->lanes == 1) {
-- bias_en = 0x3e;
-- drvr_en = 0x13;
-- } else {
-- bias_en = 0x3f;
-- drvr_en = 0x10;
-- }
--
-- writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN);
-- writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
-- writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN);
-- writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
--}
--
--static bool qcom_qmp_phy_configure_dp_mode(struct qmp_phy *qphy)
--{
-- u32 val;
-- bool reverse = false;
--
-- val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
-- DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN;
--
-- /*
-- * TODO: Assume orientation is CC1 for now and two lanes, need to
-- * use type-c connector to understand orientation and lanes.
-- *
-- * Otherwise val changes to be like below if this code understood
-- * the orientation of the type-c cable.
-- *
-- * if (lane_cnt == 4 || orientation == ORIENTATION_CC2)
-- * val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN;
-- * if (lane_cnt == 4 || orientation == ORIENTATION_CC1)
-- * val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
-- * if (orientation == ORIENTATION_CC2)
-- * writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
-- */
-- val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
-- writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
--
-- writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE);
--
-- return reverse;
--}
--
--static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy)
--{
-- const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
-- const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-- u32 phy_vco_div, status;
-- unsigned long pixel_freq;
--
-- qcom_qmp_phy_configure_dp_mode(qphy);
--
-- writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
-- writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
--
-- switch (dp_opts->link_rate) {
-- case 1620:
-- phy_vco_div = 0x1;
-- pixel_freq = 1620000000UL / 2;
-- break;
-- case 2700:
-- phy_vco_div = 0x1;
-- pixel_freq = 2700000000UL / 2;
-- break;
-- case 5400:
-- phy_vco_div = 0x2;
-- pixel_freq = 5400000000UL / 4;
-- break;
-- case 8100:
-- phy_vco_div = 0x0;
-- pixel_freq = 8100000000UL / 6;
-- break;
-- default:
-- /* Other link rates aren't supported */
-- return -EINVAL;
-- }
-- writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV);
--
-- clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
-- clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
--
-- writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
-- writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
-- writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
-- writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
-- writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
--
-- writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL);
--
-- if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS,
-- status,
-- ((status & BIT(0)) > 0),
-- 500,
-- 10000))
-- return -ETIMEDOUT;
--
-- writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
--
-- if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
-- status,
-- ((status & BIT(1)) > 0),
-- 500,
-- 10000))
-- return -ETIMEDOUT;
--
-- writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
-- udelay(2000);
-- writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
--
-- return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
-- status,
-- ((status & BIT(1)) > 0),
-- 500,
-- 10000);
--}
--
--/*
-- * We need to calibrate the aux setting here as many times
-- * as the caller tries
-- */
--static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy)
--{
-- static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d };
-- u8 val;
--
-- qphy->dp_aux_cfg++;
-- qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
-- val = cfg1_settings[qphy->dp_aux_cfg];
--
-- writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
--
-- return 0;
--}
--
--static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy)
--{
-- writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
-- DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
-- qphy->pcs + QSERDES_DP_PHY_PD_CTL);
--
-- /* Turn on BIAS current for PHY/PLL */
-- writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN);
--
-- writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
-- writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-- writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
-- writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
-- writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
-- writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
-- writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
-- writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
-- writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
-- writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
-- qphy->dp_aux_cfg = 0;
--
-- writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
-- PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
-- PHY_AUX_REQ_ERR_MASK,
-- qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
--}
--
--static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy)
--{
-- /* Program default values before writing proper values */
-- writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
-- writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
--
-- writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
-- writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
--
-- qcom_qmp_phy_configure_dp_swing(qphy,
-- QSERDES_V4_TX_TX_DRV_LVL,
-- QSERDES_V4_TX_TX_EMP_POST1_LVL);
--}
--
--static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy)
--{
-- const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
-- const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-- u32 phy_vco_div, status;
-- unsigned long pixel_freq;
-- u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
-- bool reverse;
--
-- writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1);
--
-- reverse = qcom_qmp_phy_configure_dp_mode(qphy);
--
-- writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-- writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
--
-- writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL);
-- writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL);
--
-- switch (dp_opts->link_rate) {
-- case 1620:
-- phy_vco_div = 0x1;
-- pixel_freq = 1620000000UL / 2;
-- break;
-- case 2700:
-- phy_vco_div = 0x1;
-- pixel_freq = 2700000000UL / 2;
-- break;
-- case 5400:
-- phy_vco_div = 0x2;
-- pixel_freq = 5400000000UL / 4;
-- break;
-- case 8100:
-- phy_vco_div = 0x0;
-- pixel_freq = 8100000000UL / 6;
-- break;
-- default:
-- /* Other link rates aren't supported */
-- return -EINVAL;
-- }
-- writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV);
--
-- clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
-- clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
--
-- writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
-- writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
-- writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
-- writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
--
-- writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL);
--
-- if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS,
-- status,
-- ((status & BIT(0)) > 0),
-- 500,
-- 10000))
-- return -ETIMEDOUT;
--
-- if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
-- status,
-- ((status & BIT(0)) > 0),
-- 500,
-- 10000))
-- return -ETIMEDOUT;
--
-- if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
-- status,
-- ((status & BIT(1)) > 0),
-- 500,
-- 10000))
-- return -ETIMEDOUT;
--
-- writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
--
-- if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
-- status,
-- ((status & BIT(0)) > 0),
-- 500,
-- 10000))
-- return -ETIMEDOUT;
--
-- if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
-- status,
-- ((status & BIT(1)) > 0),
-- 500,
-- 10000))
-- return -ETIMEDOUT;
--
-- /*
-- * At least for 7nm DP PHY this has to be done after enabling link
-- * clock.
-- */
--
-- if (dp_opts->lanes == 1) {
-- bias0_en = reverse ? 0x3e : 0x15;
-- bias1_en = reverse ? 0x15 : 0x3e;
-- drvr0_en = reverse ? 0x13 : 0x10;
-- drvr1_en = reverse ? 0x10 : 0x13;
-- } else if (dp_opts->lanes == 2) {
-- bias0_en = reverse ? 0x3f : 0x15;
-- bias1_en = reverse ? 0x15 : 0x3f;
-- drvr0_en = 0x10;
-- drvr1_en = 0x10;
-- } else {
-- bias0_en = 0x3f;
-- bias1_en = 0x3f;
-- drvr0_en = 0x10;
-- drvr1_en = 0x10;
-- }
--
-- writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN);
-- writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
-- writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN);
-- writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
--
-- writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
-- udelay(2000);
-- writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
--
-- if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
-- status,
-- ((status & BIT(1)) > 0),
-- 500,
-- 10000))
-- return -ETIMEDOUT;
--
-- writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV);
-- writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV);
--
-- writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
-- writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
--
-- writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
-- writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
--
-- return 0;
--}
--
--/*
-- * We need to calibrate the aux setting here as many times
-- * as the caller tries
-- */
--static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy)
--{
-- static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d };
-- u8 val;
--
-- qphy->dp_aux_cfg++;
-- qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
-- val = cfg1_settings[qphy->dp_aux_cfg];
--
-- writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
--
-- return 0;
--}
--
- static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
- {
- const struct phy_configure_opts_dp *dp_opts = &opts->dp;
-@@ -6023,81 +3104,27 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
- {
- .compatible = "qcom,ipq8074-qmp-usb3-phy",
- .data = &ipq8074_usb3phy_cfg,
-- }, {
-- .compatible = "qcom,msm8996-qmp-pcie-phy",
-- .data = &msm8996_pciephy_cfg,
-- }, {
-- .compatible = "qcom,msm8996-qmp-ufs-phy",
-- .data = &msm8996_ufs_cfg,
- }, {
- .compatible = "qcom,msm8996-qmp-usb3-phy",
- .data = &msm8996_usb3phy_cfg,
-- }, {
-- .compatible = "qcom,msm8998-qmp-pcie-phy",
-- .data = &msm8998_pciephy_cfg,
-- }, {
-- .compatible = "qcom,msm8998-qmp-ufs-phy",
-- .data = &sdm845_ufsphy_cfg,
-- }, {
-- .compatible = "qcom,ipq8074-qmp-pcie-phy",
-- .data = &ipq8074_pciephy_cfg,
-- }, {
-- .compatible = "qcom,ipq6018-qmp-pcie-phy",
-- .data = &ipq6018_pciephy_cfg,
- }, {
- .compatible = "qcom,ipq6018-qmp-usb3-phy",
- .data = &ipq8074_usb3phy_cfg,
- }, {
- .compatible = "qcom,sc7180-qmp-usb3-phy",
- .data = &sc7180_usb3phy_cfg,
-- }, {
-- .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
-- /* It's a combo phy */
-- }, {
-- .compatible = "qcom,sc8180x-qmp-pcie-phy",
-- .data = &sc8180x_pciephy_cfg,
-- }, {
-- .compatible = "qcom,sc8180x-qmp-ufs-phy",
-- .data = &sm8150_ufsphy_cfg,
-- }, {
-- .compatible = "qcom,sc8280xp-qmp-ufs-phy",
-- .data = &sm8350_ufsphy_cfg,
- }, {
- .compatible = "qcom,sc8180x-qmp-usb3-phy",
- .data = &sm8150_usb3phy_cfg,
-- }, {
-- .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
-- /* It's a combo phy */
-- }, {
-- .compatible = "qcom,sdm845-qhp-pcie-phy",
-- .data = &sdm845_qhp_pciephy_cfg,
-- }, {
-- .compatible = "qcom,sdm845-qmp-pcie-phy",
-- .data = &sdm845_qmp_pciephy_cfg,
- }, {
- .compatible = "qcom,sdm845-qmp-usb3-phy",
- .data = &qmp_v3_usb3phy_cfg,
- }, {
- .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
- .data = &qmp_v3_usb3_uniphy_cfg,
-- }, {
-- .compatible = "qcom,sdm845-qmp-ufs-phy",
-- .data = &sdm845_ufsphy_cfg,
- }, {
- .compatible = "qcom,msm8998-qmp-usb3-phy",
- .data = &msm8998_usb3phy_cfg,
-- }, {
-- .compatible = "qcom,sm6115-qmp-ufs-phy",
-- .data = &sm6115_ufsphy_cfg,
-- }, {
-- .compatible = "qcom,sm6350-qmp-ufs-phy",
-- .data = &sdm845_ufsphy_cfg,
-- }, {
-- .compatible = "qcom,sm8150-qmp-ufs-phy",
-- .data = &sm8150_ufsphy_cfg,
-- }, {
-- .compatible = "qcom,sm8250-qmp-ufs-phy",
-- .data = &sm8150_ufsphy_cfg,
- }, {
- .compatible = "qcom,sm8150-qmp-usb3-phy",
- .data = &sm8150_usb3phy_cfg,
-@@ -6107,27 +3134,9 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
- }, {
- .compatible = "qcom,sm8250-qmp-usb3-phy",
- .data = &sm8250_usb3phy_cfg,
-- }, {
-- .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
-- /* It's a combo phy */
- }, {
- .compatible = "qcom,sm8250-qmp-usb3-uni-phy",
- .data = &sm8250_usb3_uniphy_cfg,
-- }, {
-- .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
-- .data = &sm8250_qmp_gen3x1_pciephy_cfg,
-- }, {
-- .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
-- .data = &sm8250_qmp_gen3x2_pciephy_cfg,
-- }, {
-- .compatible = "qcom,sm8350-qmp-ufs-phy",
-- .data = &sm8350_ufsphy_cfg,
-- }, {
-- .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
-- .data = &sm8250_qmp_gen3x2_pciephy_cfg,
-- }, {
-- .compatible = "qcom,sdx55-qmp-pcie-phy",
-- .data = &sdx55_qmp_pciephy_cfg,
- }, {
- .compatible = "qcom,sdx55-qmp-usb3-uni-phy",
- .data = &sdx55_usb3_uniphy_cfg,
-@@ -6140,15 +3149,6 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
- }, {
- .compatible = "qcom,sm8350-qmp-usb3-uni-phy",
- .data = &sm8350_usb3_uniphy_cfg,
-- }, {
-- .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
-- .data = &sm8450_qmp_gen3x1_pciephy_cfg,
-- }, {
-- .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
-- .data = &sm8450_qmp_gen4x2_pciephy_cfg,
-- }, {
-- .compatible = "qcom,sm8450-qmp-ufs-phy",
-- .data = &sm8450_ufsphy_cfg,
- }, {
- .compatible = "qcom,sm8450-qmp-usb3-phy",
- .data = &sm8350_usb3phy_cfg,
-@@ -6160,22 +3160,6 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
- };
- MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
-
--static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = {
-- {
-- .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
-- .data = &sc7180_usb3dpphy_cfg,
-- },
-- {
-- .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
-- .data = &sm8250_usb3dpphy_cfg,
-- },
-- {
-- .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
-- .data = &sc8180x_usb3dpphy_cfg,
-- },
-- { }
--};
--
- static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
- SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
- qcom_qmp_phy_runtime_resume, NULL)
-@@ -6206,20 +3190,8 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
-
- /* Get the specific init parameters of QMP phy */
- cfg = of_device_get_match_data(dev);
-- if (!cfg) {
-- const struct of_device_id *match;
--
-- match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev);
-- if (!match)
-- return -EINVAL;
--
-- combo_cfg = match->data;
-- if (!combo_cfg)
-- return -EINVAL;
--
-- usb_cfg = combo_cfg->usb_cfg;
-- cfg = usb_cfg; /* Setup clks and regulators */
-- }
-+ if (!cfg)
-+ return -EINVAL;
-
- /* per PHY serdes; usually located at base address */
- usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0);
-@@ -6336,7 +3308,7 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
- static struct platform_driver qcom_qmp_phy_driver = {
- .probe = qcom_qmp_phy_probe,
- .driver = {
-- .name = "qcom-qmp-phy",
-+ .name = "qcom-qmp-usb-phy",
- .pm = &qcom_qmp_phy_pm_ops,
- .of_match_table = qcom_qmp_phy_of_match_table,
- },
-@@ -6345,5 +3317,5 @@ static struct platform_driver qcom_qmp_phy_driver = {
- module_platform_driver(qcom_qmp_phy_driver);
-
- MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
--MODULE_DESCRIPTION("Qualcomm QMP PHY driver");
-+MODULE_DESCRIPTION("Qualcomm QMP USB PHY driver");
- MODULE_LICENSE("GPL v2");
---
-2.35.1
-
+++ /dev/null
-From 8ec1d7a1d7cdbf41bd0641e91b68d1b2b6938792 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Wed, 8 Jun 2022 00:31:51 +0300
-Subject: phy: qcom-qmp-usb: drop support for non-USB PHY types
-
-From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-
-[ Upstream commit 86f5ddddcd9c4755e3d1d1ca4be01df5a4ed5d96 ]
-
-Drop remaining support for PHY types other than USB.
-
-Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> # UFS, PCIe and USB on SC8180X
-Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Link: https://lore.kernel.org/r/20220607213203.2819885-19-dmitry.baryshkov@linaro.org
-Signed-off-by: Vinod Koul <vkoul@kernel.org>
-Stable-dep-of: a5d6b1ac56cb ("phy: qcom-qmp-usb: fix memleak on probe deferral")
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 435 +++---------------------
- 1 file changed, 48 insertions(+), 387 deletions(-)
-
-diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
-index 2ae13b4485b6..55785dcd47e0 100644
---- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
-+++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
-@@ -2059,7 +2059,6 @@ static int qcom_qmp_phy_usb_serdes_init(struct qmp_phy *qphy)
- struct qcom_qmp *qmp = qphy->qmp;
- const struct qmp_phy_cfg *cfg = qphy->cfg;
- void __iomem *serdes = qphy->serdes;
-- const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
- const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
- int serdes_tbl_num = cfg->serdes_tbl_num;
- int ret;
-@@ -2069,35 +2068,6 @@ static int qcom_qmp_phy_usb_serdes_init(struct qmp_phy *qphy)
- qcom_qmp_phy_usb_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
- cfg->serdes_tbl_num_sec);
-
-- if (cfg->type == PHY_TYPE_DP) {
-- switch (dp_opts->link_rate) {
-- case 1620:
-- qcom_qmp_phy_usb_configure(serdes, cfg->regs,
-- cfg->serdes_tbl_rbr,
-- cfg->serdes_tbl_rbr_num);
-- break;
-- case 2700:
-- qcom_qmp_phy_usb_configure(serdes, cfg->regs,
-- cfg->serdes_tbl_hbr,
-- cfg->serdes_tbl_hbr_num);
-- break;
-- case 5400:
-- qcom_qmp_phy_usb_configure(serdes, cfg->regs,
-- cfg->serdes_tbl_hbr2,
-- cfg->serdes_tbl_hbr2_num);
-- break;
-- case 8100:
-- qcom_qmp_phy_usb_configure(serdes, cfg->regs,
-- cfg->serdes_tbl_hbr3,
-- cfg->serdes_tbl_hbr3_num);
-- break;
-- default:
-- /* Other link rates aren't supported */
-- return -EINVAL;
-- }
-- }
--
--
- if (cfg->has_phy_com_ctrl) {
- void __iomem *status;
- unsigned int mask, val;
-@@ -2121,32 +2091,6 @@ static int qcom_qmp_phy_usb_serdes_init(struct qmp_phy *qphy)
- return 0;
- }
-
--static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
--{
-- const struct phy_configure_opts_dp *dp_opts = &opts->dp;
-- struct qmp_phy *qphy = phy_get_drvdata(phy);
-- const struct qmp_phy_cfg *cfg = qphy->cfg;
--
-- memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts));
-- if (qphy->dp_opts.set_voltages) {
-- cfg->configure_dp_tx(qphy);
-- qphy->dp_opts.set_voltages = 0;
-- }
--
-- return 0;
--}
--
--static int qcom_qmp_dp_phy_calibrate(struct phy *phy)
--{
-- struct qmp_phy *qphy = phy_get_drvdata(phy);
-- const struct qmp_phy_cfg *cfg = qphy->cfg;
--
-- if (cfg->calibrate_dp_phy)
-- return cfg->calibrate_dp_phy(qphy);
--
-- return 0;
--}
--
- static int qcom_qmp_phy_usb_com_init(struct qmp_phy *qphy)
- {
- struct qcom_qmp *qmp = qphy->qmp;
-@@ -2316,9 +2260,6 @@ static int qcom_qmp_phy_usb_init(struct phy *phy)
- if (ret)
- return ret;
-
-- if (cfg->type == PHY_TYPE_DP)
-- cfg->dp_aux_init(qphy);
--
- return 0;
- }
-
-@@ -2369,10 +2310,6 @@ static int qcom_qmp_phy_usb_power_on(struct phy *phy)
- cfg->tx_tbl_num_sec, 2);
- }
-
-- /* Configure special DP tx tunings */
-- if (cfg->type == PHY_TYPE_DP)
-- cfg->configure_dp_tx(qphy);
--
- qcom_qmp_phy_usb_configure_lane(rx, cfg->regs,
- cfg->rx_tbl, cfg->rx_tbl_num, 1);
- if (cfg->rx_tbl_sec)
-@@ -2389,14 +2326,10 @@ static int qcom_qmp_phy_usb_power_on(struct phy *phy)
- }
-
- /* Configure link rate, swing, etc. */
-- if (cfg->type == PHY_TYPE_DP) {
-- cfg->configure_dp_phy(qphy);
-- } else {
-- qcom_qmp_phy_usb_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
-- if (cfg->pcs_tbl_sec)
-- qcom_qmp_phy_usb_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
-- cfg->pcs_tbl_num_sec);
-- }
-+ qcom_qmp_phy_usb_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
-+ if (cfg->pcs_tbl_sec)
-+ qcom_qmp_phy_usb_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
-+ cfg->pcs_tbl_num_sec);
-
- ret = reset_control_deassert(qmp->ufs_reset);
- if (ret)
-@@ -2408,40 +2341,26 @@ static int qcom_qmp_phy_usb_power_on(struct phy *phy)
- qcom_qmp_phy_usb_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
- cfg->pcs_misc_tbl_num_sec);
-
-- /*
-- * Pull out PHY from POWER DOWN state.
-- * This is active low enable signal to power-down PHY.
-- */
-- if(cfg->type == PHY_TYPE_PCIE)
-- qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
--
- if (cfg->has_pwrdn_delay)
- usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
-
-- if (cfg->type != PHY_TYPE_DP) {
-- /* Pull PHY out of reset state */
-- if (!cfg->no_pcs_sw_reset)
-- qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
-- /* start SerDes and Phy-Coding-Sublayer */
-- qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
--
-- if (cfg->type == PHY_TYPE_UFS) {
-- status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
-- mask = PCS_READY;
-- ready = PCS_READY;
-- } else {
-- status = pcs + cfg->regs[QPHY_PCS_STATUS];
-- mask = cfg->phy_status;
-- ready = 0;
-- }
-+ /* Pull PHY out of reset state */
-+ if (!cfg->no_pcs_sw_reset)
-+ qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
-+ /* start SerDes and Phy-Coding-Sublayer */
-+ qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
-
-- ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
-- PHY_INIT_COMPLETE_TIMEOUT);
-- if (ret) {
-- dev_err(qmp->dev, "phy initialization timed-out\n");
-- goto err_disable_pipe_clk;
-- }
-+ status = pcs + cfg->regs[QPHY_PCS_STATUS];
-+ mask = cfg->phy_status;
-+ ready = 0;
-+
-+ ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
-+ PHY_INIT_COMPLETE_TIMEOUT);
-+ if (ret) {
-+ dev_err(qmp->dev, "phy initialization timed-out\n");
-+ goto err_disable_pipe_clk;
- }
-+
- return 0;
-
- err_disable_pipe_clk:
-@@ -2460,25 +2379,20 @@ static int qcom_qmp_phy_usb_power_off(struct phy *phy)
-
- clk_disable_unprepare(qphy->pipe_clk);
-
-- if (cfg->type == PHY_TYPE_DP) {
-- /* Assert DP PHY power down */
-- writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-- } else {
-- /* PHY reset */
-- if (!cfg->no_pcs_sw_reset)
-- qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
-+ /* PHY reset */
-+ if (!cfg->no_pcs_sw_reset)
-+ qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
-
-- /* stop SerDes and Phy-Coding-Sublayer */
-- qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
-+ /* stop SerDes and Phy-Coding-Sublayer */
-+ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
-
-- /* Put PHY into POWER DOWN state: active low */
-- if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
-- qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
-- cfg->pwrdn_ctrl);
-- } else {
-- qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
-- cfg->pwrdn_ctrl);
-- }
-+ /* Put PHY into POWER DOWN state: active low */
-+ if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
-+ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
-+ cfg->pwrdn_ctrl);
-+ } else {
-+ qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
-+ cfg->pwrdn_ctrl);
- }
-
- return 0;
-@@ -2755,223 +2669,13 @@ static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
- return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
- }
-
--/*
-- * Display Port PLL driver block diagram for branch clocks
-- *
-- * +------------------------------+
-- * | DP_VCO_CLK |
-- * | |
-- * | +-------------------+ |
-- * | | (DP PLL/VCO) | |
-- * | +---------+---------+ |
-- * | v |
-- * | +----------+-----------+ |
-- * | | hsclk_divsel_clk_src | |
-- * | +----------+-----------+ |
-- * +------------------------------+
-- * |
-- * +---------<---------v------------>----------+
-- * | |
-- * +--------v----------------+ |
-- * | dp_phy_pll_link_clk | |
-- * | link_clk | |
-- * +--------+----------------+ |
-- * | |
-- * | |
-- * v v
-- * Input to DISPCC block |
-- * for link clk, crypto clk |
-- * and interface clock |
-- * |
-- * |
-- * +--------<------------+-----------------+---<---+
-- * | | |
-- * +----v---------+ +--------v-----+ +--------v------+
-- * | vco_divided | | vco_divided | | vco_divided |
-- * | _clk_src | | _clk_src | | _clk_src |
-- * | | | | | |
-- * |divsel_six | | divsel_two | | divsel_four |
-- * +-------+------+ +-----+--------+ +--------+------+
-- * | | |
-- * v---->----------v-------------<------v
-- * |
-- * +----------+-----------------+
-- * | dp_phy_pll_vco_div_clk |
-- * +---------+------------------+
-- * |
-- * v
-- * Input to DISPCC block
-- * for DP pixel clock
-- *
-- */
--static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw,
-- struct clk_rate_request *req)
--{
-- switch (req->rate) {
-- case 1620000000UL / 2:
-- case 2700000000UL / 2:
-- /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */
-- return 0;
-- default:
-- return -EINVAL;
-- }
--}
--
--static unsigned long
--qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
--{
-- const struct qmp_phy_dp_clks *dp_clks;
-- const struct qmp_phy *qphy;
-- const struct phy_configure_opts_dp *dp_opts;
--
-- dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw);
-- qphy = dp_clks->qphy;
-- dp_opts = &qphy->dp_opts;
--
-- switch (dp_opts->link_rate) {
-- case 1620:
-- return 1620000000UL / 2;
-- case 2700:
-- return 2700000000UL / 2;
-- case 5400:
-- return 5400000000UL / 4;
-- case 8100:
-- return 8100000000UL / 6;
-- default:
-- return 0;
-- }
--}
--
--static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = {
-- .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate,
-- .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate,
--};
--
--static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw,
-- struct clk_rate_request *req)
--{
-- switch (req->rate) {
-- case 162000000:
-- case 270000000:
-- case 540000000:
-- case 810000000:
-- return 0;
-- default:
-- return -EINVAL;
-- }
--}
--
--static unsigned long
--qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
--{
-- const struct qmp_phy_dp_clks *dp_clks;
-- const struct qmp_phy *qphy;
-- const struct phy_configure_opts_dp *dp_opts;
--
-- dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw);
-- qphy = dp_clks->qphy;
-- dp_opts = &qphy->dp_opts;
--
-- switch (dp_opts->link_rate) {
-- case 1620:
-- case 2700:
-- case 5400:
-- case 8100:
-- return dp_opts->link_rate * 100000;
-- default:
-- return 0;
-- }
--}
--
--static const struct clk_ops qcom_qmp_dp_link_clk_ops = {
-- .determine_rate = qcom_qmp_dp_link_clk_determine_rate,
-- .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate,
--};
--
--static struct clk_hw *
--qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data)
--{
-- struct qmp_phy_dp_clks *dp_clks = data;
-- unsigned int idx = clkspec->args[0];
--
-- if (idx >= 2) {
-- pr_err("%s: invalid index %u\n", __func__, idx);
-- return ERR_PTR(-EINVAL);
-- }
--
-- if (idx == 0)
-- return &dp_clks->dp_link_hw;
--
-- return &dp_clks->dp_pixel_hw;
--}
--
--static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy,
-- struct device_node *np)
--{
-- struct clk_init_data init = { };
-- struct qmp_phy_dp_clks *dp_clks;
-- char name[64];
-- int ret;
--
-- dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL);
-- if (!dp_clks)
-- return -ENOMEM;
--
-- dp_clks->qphy = qphy;
-- qphy->dp_clks = dp_clks;
--
-- snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev));
-- init.ops = &qcom_qmp_dp_link_clk_ops;
-- init.name = name;
-- dp_clks->dp_link_hw.init = &init;
-- ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw);
-- if (ret)
-- return ret;
--
-- snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev));
-- init.ops = &qcom_qmp_dp_pixel_clk_ops;
-- init.name = name;
-- dp_clks->dp_pixel_hw.init = &init;
-- ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw);
-- if (ret)
-- return ret;
--
-- ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks);
-- if (ret)
-- return ret;
--
-- /*
-- * Roll a devm action because the clock provider is the child node, but
-- * the child node is not actually a device.
-- */
-- return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
--}
--
--static const struct phy_ops qcom_qmp_phy_usb_gen_ops = {
-+static const struct phy_ops qcom_qmp_phy_usb_ops = {
- .init = qcom_qmp_phy_usb_enable,
- .exit = qcom_qmp_phy_usb_disable,
- .set_mode = qcom_qmp_phy_usb_set_mode,
- .owner = THIS_MODULE,
- };
-
--static const struct phy_ops qcom_qmp_phy_usb_dp_ops = {
-- .init = qcom_qmp_phy_usb_init,
-- .configure = qcom_qmp_dp_phy_configure,
-- .power_on = qcom_qmp_phy_usb_power_on,
-- .calibrate = qcom_qmp_dp_phy_calibrate,
-- .power_off = qcom_qmp_phy_usb_power_off,
-- .exit = qcom_qmp_phy_usb_exit,
-- .set_mode = qcom_qmp_phy_usb_set_mode,
-- .owner = THIS_MODULE,
--};
--
--static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
-- .power_on = qcom_qmp_phy_usb_enable,
-- .power_off = qcom_qmp_phy_usb_disable,
-- .set_mode = qcom_qmp_phy_usb_set_mode,
-- .owner = THIS_MODULE,
--};
--
- static void qcom_qmp_reset_control_put(void *data)
- {
- reset_control_put(data);
-@@ -2984,7 +2688,6 @@ int qcom_qmp_phy_usb_create(struct device *dev, struct device_node *np, int id,
- struct qcom_qmp *qmp = dev_get_drvdata(dev);
- struct phy *generic_phy;
- struct qmp_phy *qphy;
-- const struct phy_ops *ops;
- char prop_name[MAX_PROP_NAME];
- int ret;
-
-@@ -3051,16 +2754,12 @@ int qcom_qmp_phy_usb_create(struct device *dev, struct device_node *np, int id,
- snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
- qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name);
- if (IS_ERR(qphy->pipe_clk)) {
-- if (cfg->type == PHY_TYPE_PCIE ||
-- cfg->type == PHY_TYPE_USB3) {
-- ret = PTR_ERR(qphy->pipe_clk);
-- if (ret != -EPROBE_DEFER)
-- dev_err(dev,
-- "failed to get lane%d pipe_clk, %d\n",
-- id, ret);
-- return ret;
-- }
-- qphy->pipe_clk = NULL;
-+ ret = PTR_ERR(qphy->pipe_clk);
-+ if (ret != -EPROBE_DEFER)
-+ dev_err(dev,
-+ "failed to get lane%d pipe_clk, %d\n",
-+ id, ret);
-+ return ret;
- }
-
- /* Get lane reset, if any */
-@@ -3077,14 +2776,7 @@ int qcom_qmp_phy_usb_create(struct device *dev, struct device_node *np, int id,
- return ret;
- }
-
-- if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE)
-- ops = &qcom_qmp_pcie_ufs_ops;
-- else if (cfg->type == PHY_TYPE_DP)
-- ops = &qcom_qmp_phy_usb_dp_ops;
-- else
-- ops = &qcom_qmp_phy_usb_gen_ops;
--
-- generic_phy = devm_phy_create(dev, np, ops);
-+ generic_phy = devm_phy_create(dev, np, &qcom_qmp_phy_usb_ops);
- if (IS_ERR(generic_phy)) {
- ret = PTR_ERR(generic_phy);
- dev_err(dev, "failed to create qphy %d\n", ret);
-@@ -3172,12 +2864,7 @@ static int qcom_qmp_phy_usb_probe(struct platform_device *pdev)
- struct device_node *child;
- struct phy_provider *phy_provider;
- void __iomem *serdes;
-- void __iomem *usb_serdes;
-- void __iomem *dp_serdes = NULL;
-- const struct qmp_phy_combo_cfg *combo_cfg = NULL;
- const struct qmp_phy_cfg *cfg = NULL;
-- const struct qmp_phy_cfg *usb_cfg = NULL;
-- const struct qmp_phy_cfg *dp_cfg = NULL;
- int num, id, expected_phys;
- int ret;
-
-@@ -3194,28 +2881,18 @@ static int qcom_qmp_phy_usb_probe(struct platform_device *pdev)
- return -EINVAL;
-
- /* per PHY serdes; usually located at base address */
-- usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0);
-+ serdes = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(serdes))
- return PTR_ERR(serdes);
-
- /* per PHY dp_com; if PHY has dp_com control block */
-- if (combo_cfg || cfg->has_phy_dp_com_ctrl) {
-+ if (cfg->has_phy_dp_com_ctrl) {
- qmp->dp_com = devm_platform_ioremap_resource(pdev, 1);
- if (IS_ERR(qmp->dp_com))
- return PTR_ERR(qmp->dp_com);
- }
-
-- if (combo_cfg) {
-- /* Only two serdes for combo PHY */
-- dp_serdes = devm_platform_ioremap_resource(pdev, 2);
-- if (IS_ERR(dp_serdes))
-- return PTR_ERR(dp_serdes);
--
-- dp_cfg = combo_cfg->dp_cfg;
-- expected_phys = 2;
-- } else {
-- expected_phys = cfg->nlanes;
-- }
-+ expected_phys = cfg->nlanes;
-
- mutex_init(&qmp->phy_mutex);
-
-@@ -3256,14 +2933,6 @@ static int qcom_qmp_phy_usb_probe(struct platform_device *pdev)
-
- id = 0;
- for_each_available_child_of_node(dev->of_node, child) {
-- if (of_node_name_eq(child, "dp-phy")) {
-- cfg = dp_cfg;
-- serdes = dp_serdes;
-- } else if (of_node_name_eq(child, "usb3-phy")) {
-- cfg = usb_cfg;
-- serdes = usb_serdes;
-- }
--
- /* Create per-lane phy */
- ret = qcom_qmp_phy_usb_create(dev, child, id, serdes, cfg);
- if (ret) {
-@@ -3276,21 +2945,13 @@ static int qcom_qmp_phy_usb_probe(struct platform_device *pdev)
- * Register the pipe clock provided by phy.
- * See function description to see details of this pipe clock.
- */
-- if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) {
-- ret = phy_pipe_clk_register(qmp, child);
-- if (ret) {
-- dev_err(qmp->dev,
-- "failed to register pipe clock source\n");
-- goto err_node_put;
-- }
-- } else if (cfg->type == PHY_TYPE_DP) {
-- ret = phy_dp_clks_register(qmp, qmp->phys[id], child);
-- if (ret) {
-- dev_err(qmp->dev,
-- "failed to register DP clock source\n");
-- goto err_node_put;
-- }
-+ ret = phy_pipe_clk_register(qmp, child);
-+ if (ret) {
-+ dev_err(qmp->dev,
-+ "failed to register pipe clock source\n");
-+ goto err_node_put;
- }
-+
- id++;
- }
-
---
-2.35.1
-
dyndbg-drop-exported-dynamic_debug_exec_queries.patch
sbitmap-avoid-leaving-waitqueue-in-invalid-state-in-.patch
mtd-devices-docg3-check-the-return-value-of-devm_ior.patch
-phy-qcom-qmp-create-copies-of-qmp-phy-driver.patch
-phy-qcom-qmp-usb-disable-runtime-pm-on-unbind.patch
-phy-qcom-qmp-pcie-msm8996-drop-all-compatibles-excep.patch
-phy-qcom-qmp-pcie-change-symbol-prefix-to-qcom_qmp_p.patch
-phy-qcom-qmp-pcie-msm8996-drop-support-for-non-pcie-.patch
-phy-qcom-qmp-pcie-msm8996-cleanup-the-driver.patch
-phy-qcom-qmp-usb-drop-all-non-usb-compatibles-suppor.patch
-phy-qcom-qmp-usb-change-symbol-prefix-to-qcom_qmp_ph.patch
-phy-qcom-qmp-usb-drop-support-for-non-usb-phy-types.patch
-phy-qcom-qmp-usb-cleanup-the-driver.patch
-phy-qcom-qmp-usb-clean-up-pipe-clock-handling.patch
mtd-rawnand-fsl_elbc-fix-none-ecc-mode.patch
rdma-siw-always-consume-all-skbuf-data-in-sk_data_re.patch
rdma-rdmavt-decouple-qp-and-sge-lists-allocations.patch
net-ieee802154-return-einval-for-unknown-addr-type.patch
revert-net-ieee802154-reject-zero-sized-raw_sendmsg.patch
net-ieee802154-don-t-warn-zero-sized-raw_sendmsg.patch
-phy-qcom-qmp-fix-msm8996-pcie-phy-support.patch
clk-fix-pointer-casting-to-prevent-oops-in-devm_clk_release.patch
net-wwan-t7xx-use-gfp_atomic-under-spin-lock-in-t7xx_cldma_gpd_set_next_ptr.patch
revert-drm-amdgpu-move-nbio-sdma_doorbell_range-into-sdma-code-for-vega.patch
+++ /dev/null
-From edca98098cfb0438ee6b6b44d1ec1aa82e966554 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Wed, 8 Jun 2022 00:35:32 +0300
-Subject: phy: qcom-qmp: create copies of QMP PHY driver
-
-From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-
-[ Upstream commit 94a407cc17a445ddb3f7315cee0b0916d35d177c ]
-
-In order to split and cleanup the single monstrous QMP PHY driver,
-create blind copies of the current file. They will be used for:
-- PCIe (and a separate msm8996 PCIe PHY driver)
-- UFS
-- USB
-- Combo DP + USB
-
-Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> # UFS, PCIe and USB on SC8180X
-Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Link: https://lore.kernel.org/r/20220607213203.2819885-2-dmitry.baryshkov@linaro.org
-Signed-off-by: Vinod Koul <vkoul@kernel.org>
-Stable-dep-of: 4382d518d188 ("phy: qcom-qmp-combo: disable runtime PM on unbind")
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 6350 +++++++++++++++++
- .../phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 6350 +++++++++++++++++
- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 6350 +++++++++++++++++
- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 6350 +++++++++++++++++
- drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 6350 +++++++++++++++++
- 5 files changed, 31750 insertions(+)
- create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-combo.c
- create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
- create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
- create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
- create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-usb.c
-
-diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
-new file mode 100644
-index 000000000000..c7309e981bfb
---- /dev/null
-+++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
-@@ -0,0 +1,6350 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/clk-provider.h>
-+#include <linux/delay.h>
-+#include <linux/err.h>
-+#include <linux/io.h>
-+#include <linux/iopoll.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/of_device.h>
-+#include <linux/of_address.h>
-+#include <linux/phy/phy.h>
-+#include <linux/platform_device.h>
-+#include <linux/regulator/consumer.h>
-+#include <linux/reset.h>
-+#include <linux/slab.h>
-+
-+#include <dt-bindings/phy/phy.h>
-+
-+#include "phy-qcom-qmp.h"
-+
-+/* QPHY_SW_RESET bit */
-+#define SW_RESET BIT(0)
-+/* QPHY_POWER_DOWN_CONTROL */
-+#define SW_PWRDN BIT(0)
-+#define REFCLK_DRV_DSBL BIT(1)
-+/* QPHY_START_CONTROL bits */
-+#define SERDES_START BIT(0)
-+#define PCS_START BIT(1)
-+#define PLL_READY_GATE_EN BIT(3)
-+/* QPHY_PCS_STATUS bit */
-+#define PHYSTATUS BIT(6)
-+#define PHYSTATUS_4_20 BIT(7)
-+/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */
-+#define PCS_READY BIT(0)
-+
-+/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
-+/* DP PHY soft reset */
-+#define SW_DPPHY_RESET BIT(0)
-+/* mux to select DP PHY reset control, 0:HW control, 1: software reset */
-+#define SW_DPPHY_RESET_MUX BIT(1)
-+/* USB3 PHY soft reset */
-+#define SW_USB3PHY_RESET BIT(2)
-+/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
-+#define SW_USB3PHY_RESET_MUX BIT(3)
-+
-+/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
-+#define USB3_MODE BIT(0) /* enables USB3 mode */
-+#define DP_MODE BIT(1) /* enables DP mode */
-+
-+/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
-+#define ARCVR_DTCT_EN BIT(0)
-+#define ALFPS_DTCT_EN BIT(1)
-+#define ARCVR_DTCT_EVENT_SEL BIT(4)
-+
-+/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
-+#define IRQ_CLEAR BIT(0)
-+
-+/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
-+#define RCVR_DETECT BIT(0)
-+
-+/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
-+#define CLAMP_EN BIT(0) /* enables i/o clamp_n */
-+
-+#define PHY_INIT_COMPLETE_TIMEOUT 10000
-+#define POWER_DOWN_DELAY_US_MIN 10
-+#define POWER_DOWN_DELAY_US_MAX 11
-+
-+#define MAX_PROP_NAME 32
-+
-+/* Define the assumed distance between lanes for underspecified device trees. */
-+#define QMP_PHY_LEGACY_LANE_STRIDE 0x400
-+
-+struct qmp_phy_init_tbl {
-+ unsigned int offset;
-+ unsigned int val;
-+ /*
-+ * register part of layout ?
-+ * if yes, then offset gives index in the reg-layout
-+ */
-+ bool in_layout;
-+ /*
-+ * mask of lanes for which this register is written
-+ * for cases when second lane needs different values
-+ */
-+ u8 lane_mask;
-+};
-+
-+#define QMP_PHY_INIT_CFG(o, v) \
-+ { \
-+ .offset = o, \
-+ .val = v, \
-+ .lane_mask = 0xff, \
-+ }
-+
-+#define QMP_PHY_INIT_CFG_L(o, v) \
-+ { \
-+ .offset = o, \
-+ .val = v, \
-+ .in_layout = true, \
-+ .lane_mask = 0xff, \
-+ }
-+
-+#define QMP_PHY_INIT_CFG_LANE(o, v, l) \
-+ { \
-+ .offset = o, \
-+ .val = v, \
-+ .lane_mask = l, \
-+ }
-+
-+/* set of registers with offsets different per-PHY */
-+enum qphy_reg_layout {
-+ /* Common block control registers */
-+ QPHY_COM_SW_RESET,
-+ QPHY_COM_POWER_DOWN_CONTROL,
-+ QPHY_COM_START_CONTROL,
-+ QPHY_COM_PCS_READY_STATUS,
-+ /* PCS registers */
-+ QPHY_PLL_LOCK_CHK_DLY_TIME,
-+ QPHY_FLL_CNTRL1,
-+ QPHY_FLL_CNTRL2,
-+ QPHY_FLL_CNT_VAL_L,
-+ QPHY_FLL_CNT_VAL_H_TOL,
-+ QPHY_FLL_MAN_CODE,
-+ QPHY_SW_RESET,
-+ QPHY_START_CTRL,
-+ QPHY_PCS_READY_STATUS,
-+ QPHY_PCS_STATUS,
-+ QPHY_PCS_AUTONOMOUS_MODE_CTRL,
-+ QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
-+ QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
-+ QPHY_PCS_POWER_DOWN_CONTROL,
-+ /* PCS_MISC registers */
-+ QPHY_PCS_MISC_TYPEC_CTRL,
-+ /* Keep last to ensure regs_layout arrays are properly initialized */
-+ QPHY_LAYOUT_SIZE
-+};
-+
-+static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_START_CTRL] = 0x00,
-+ [QPHY_PCS_READY_STATUS] = 0x168,
-+};
-+
-+static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x44,
-+ [QPHY_PCS_STATUS] = 0x14,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
-+};
-+
-+static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_COM_SW_RESET] = 0x400,
-+ [QPHY_COM_POWER_DOWN_CONTROL] = 0x404,
-+ [QPHY_COM_START_CONTROL] = 0x408,
-+ [QPHY_COM_PCS_READY_STATUS] = 0x448,
-+ [QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8,
-+ [QPHY_FLL_CNTRL1] = 0xc4,
-+ [QPHY_FLL_CNTRL2] = 0xc8,
-+ [QPHY_FLL_CNT_VAL_L] = 0xcc,
-+ [QPHY_FLL_CNT_VAL_H_TOL] = 0xd0,
-+ [QPHY_FLL_MAN_CODE] = 0xd4,
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_STATUS] = 0x174,
-+};
-+
-+static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_FLL_CNTRL1] = 0xc0,
-+ [QPHY_FLL_CNTRL2] = 0xc4,
-+ [QPHY_FLL_CNT_VAL_L] = 0xc8,
-+ [QPHY_FLL_CNT_VAL_H_TOL] = 0xcc,
-+ [QPHY_FLL_MAN_CODE] = 0xd0,
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_STATUS] = 0x17c,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
-+};
-+
-+static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_STATUS] = 0x174,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
-+};
-+
-+static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_STATUS] = 0x174,
-+};
-+
-+static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_STATUS] = 0x2ac,
-+};
-+
-+static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x44,
-+ [QPHY_PCS_STATUS] = 0x14,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314,
-+};
-+
-+static const unsigned int qmp_v4_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x44,
-+ [QPHY_PCS_STATUS] = 0x14,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x608,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x614,
-+};
-+
-+static const unsigned int sm8350_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x44,
-+ [QPHY_PCS_STATUS] = 0x14,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x1008,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x1014,
-+};
-+
-+static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0xd8,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc,
-+ [QPHY_PCS_STATUS] = 0x174,
-+ [QPHY_PCS_MISC_TYPEC_CTRL] = 0x00,
-+};
-+
-+static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_START_CTRL] = 0x00,
-+ [QPHY_PCS_READY_STATUS] = 0x160,
-+};
-+
-+static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_START_CTRL] = 0x00,
-+ [QPHY_PCS_READY_STATUS] = 0x168,
-+};
-+
-+static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x44,
-+ [QPHY_PCS_STATUS] = 0x14,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
-+};
-+
-+static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START,
-+ [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS,
-+ [QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET,
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
-+ /* PLL and Loop filter settings */
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-+ /* SSC settings */
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
-+ QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
-+
-+ QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
-+
-+ QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
-+ QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
-+ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
-+ /* PLL and Loop filter settings */
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-+ /* SSC settings */
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
-+ /* FLL settings */
-+ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03),
-+ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02),
-+ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42),
-+ QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
-+
-+ /* Lock Det settings */
-+ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x61),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d),
-+ QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10),
-+ QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_PRE, 0x00),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_POST, 0x58),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
-+ QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
-+ QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
-+ QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
-+ QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
-+ QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
-+ QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
-+ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
-+ QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
-+ QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = {
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
-+ /* FLL settings */
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+
-+ /* Lock Det settings */
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
-+ /* FLL settings */
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+
-+ /* Lock Det settings */
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
-+};
-+
-+static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
-+
-+ /* Rate B */
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),
-+};
-+
-+static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B),
-+};
-+
-+static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_RX_PWM_GEAR_BAND, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_CTRL2, 0x6d),
-+ QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_DRV_LVL, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_DRV_LVL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
-+ QMP_PHY_INIT_CFG(QPHY_RX_SYM_RESYNC_CTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
-+ QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
-+
-+ /* Rate B */
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
-+
-+ /* Rate B */
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
-+
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
-+ /* Lock Det settings */
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20),
-+};
-+
-+static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
-+};
-+
-+static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5),
-+};
-+
-+static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
-+};
-+
-+static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),
-+};
-+
-+static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
-+
-+ /* Rate B */
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+};
-+
-+static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01),
-+};
-+
-+static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
-+
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05),
-+
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
-+
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
-+
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
-+};
-+
-+/* Register names should be validated, they might be different for this PHY */
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
-+};
-+
-+struct qmp_phy;
-+
-+/* struct qmp_phy_cfg - per-PHY initialization config */
-+struct qmp_phy_cfg {
-+ /* phy-type - PCIE/UFS/USB */
-+ unsigned int type;
-+ /* number of lanes provided by phy */
-+ int nlanes;
-+
-+ /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
-+ const struct qmp_phy_init_tbl *serdes_tbl;
-+ int serdes_tbl_num;
-+ const struct qmp_phy_init_tbl *serdes_tbl_sec;
-+ int serdes_tbl_num_sec;
-+ const struct qmp_phy_init_tbl *tx_tbl;
-+ int tx_tbl_num;
-+ const struct qmp_phy_init_tbl *tx_tbl_sec;
-+ int tx_tbl_num_sec;
-+ const struct qmp_phy_init_tbl *rx_tbl;
-+ int rx_tbl_num;
-+ const struct qmp_phy_init_tbl *rx_tbl_sec;
-+ int rx_tbl_num_sec;
-+ const struct qmp_phy_init_tbl *pcs_tbl;
-+ int pcs_tbl_num;
-+ const struct qmp_phy_init_tbl *pcs_tbl_sec;
-+ int pcs_tbl_num_sec;
-+ const struct qmp_phy_init_tbl *pcs_misc_tbl;
-+ int pcs_misc_tbl_num;
-+ const struct qmp_phy_init_tbl *pcs_misc_tbl_sec;
-+ int pcs_misc_tbl_num_sec;
-+
-+ /* Init sequence for DP PHY block link rates */
-+ const struct qmp_phy_init_tbl *serdes_tbl_rbr;
-+ int serdes_tbl_rbr_num;
-+ const struct qmp_phy_init_tbl *serdes_tbl_hbr;
-+ int serdes_tbl_hbr_num;
-+ const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
-+ int serdes_tbl_hbr2_num;
-+ const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
-+ int serdes_tbl_hbr3_num;
-+
-+ /* DP PHY callbacks */
-+ int (*configure_dp_phy)(struct qmp_phy *qphy);
-+ void (*configure_dp_tx)(struct qmp_phy *qphy);
-+ int (*calibrate_dp_phy)(struct qmp_phy *qphy);
-+ void (*dp_aux_init)(struct qmp_phy *qphy);
-+
-+ /* clock ids to be requested */
-+ const char * const *clk_list;
-+ int num_clks;
-+ /* resets to be requested */
-+ const char * const *reset_list;
-+ int num_resets;
-+ /* regulators to be requested */
-+ const char * const *vreg_list;
-+ int num_vregs;
-+
-+ /* array of registers with different offsets */
-+ const unsigned int *regs;
-+
-+ unsigned int start_ctrl;
-+ unsigned int pwrdn_ctrl;
-+ unsigned int mask_com_pcs_ready;
-+ /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
-+ unsigned int phy_status;
-+
-+ /* true, if PHY has a separate PHY_COM control block */
-+ bool has_phy_com_ctrl;
-+ /* true, if PHY has a reset for individual lanes */
-+ bool has_lane_rst;
-+ /* true, if PHY needs delay after POWER_DOWN */
-+ bool has_pwrdn_delay;
-+ /* power_down delay in usec */
-+ int pwrdn_delay_min;
-+ int pwrdn_delay_max;
-+
-+ /* true, if PHY has a separate DP_COM control block */
-+ bool has_phy_dp_com_ctrl;
-+ /* true, if PHY has secondary tx/rx lanes to be configured */
-+ bool is_dual_lane_phy;
-+
-+ /* true, if PCS block has no separate SW_RESET register */
-+ bool no_pcs_sw_reset;
-+};
-+
-+struct qmp_phy_combo_cfg {
-+ const struct qmp_phy_cfg *usb_cfg;
-+ const struct qmp_phy_cfg *dp_cfg;
-+};
-+
-+/**
-+ * struct qmp_phy - per-lane phy descriptor
-+ *
-+ * @phy: generic phy
-+ * @cfg: phy specific configuration
-+ * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
-+ * @tx: iomapped memory space for lane's tx
-+ * @rx: iomapped memory space for lane's rx
-+ * @pcs: iomapped memory space for lane's pcs
-+ * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
-+ * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
-+ * @pcs_misc: iomapped memory space for lane's pcs_misc
-+ * @pipe_clk: pipe clock
-+ * @index: lane index
-+ * @qmp: QMP phy to which this lane belongs
-+ * @lane_rst: lane's reset controller
-+ * @mode: current PHY mode
-+ * @dp_aux_cfg: Display port aux config
-+ * @dp_opts: Display port optional config
-+ * @dp_clks: Display port clocks
-+ */
-+struct qmp_phy {
-+ struct phy *phy;
-+ const struct qmp_phy_cfg *cfg;
-+ void __iomem *serdes;
-+ void __iomem *tx;
-+ void __iomem *rx;
-+ void __iomem *pcs;
-+ void __iomem *tx2;
-+ void __iomem *rx2;
-+ void __iomem *pcs_misc;
-+ struct clk *pipe_clk;
-+ unsigned int index;
-+ struct qcom_qmp *qmp;
-+ struct reset_control *lane_rst;
-+ enum phy_mode mode;
-+ unsigned int dp_aux_cfg;
-+ struct phy_configure_opts_dp dp_opts;
-+ struct qmp_phy_dp_clks *dp_clks;
-+};
-+
-+struct qmp_phy_dp_clks {
-+ struct qmp_phy *qphy;
-+ struct clk_hw dp_link_hw;
-+ struct clk_hw dp_pixel_hw;
-+};
-+
-+/**
-+ * struct qcom_qmp - structure holding QMP phy block attributes
-+ *
-+ * @dev: device
-+ * @dp_com: iomapped memory space for phy's dp_com control block
-+ *
-+ * @clks: array of clocks required by phy
-+ * @resets: array of resets required by phy
-+ * @vregs: regulator supplies bulk data
-+ *
-+ * @phys: array of per-lane phy descriptors
-+ * @phy_mutex: mutex lock for PHY common block initialization
-+ * @init_count: phy common block initialization count
-+ * @ufs_reset: optional UFS PHY reset handle
-+ */
-+struct qcom_qmp {
-+ struct device *dev;
-+ void __iomem *dp_com;
-+
-+ struct clk_bulk_data *clks;
-+ struct reset_control **resets;
-+ struct regulator_bulk_data *vregs;
-+
-+ struct qmp_phy **phys;
-+
-+ struct mutex phy_mutex;
-+ int init_count;
-+
-+ struct reset_control *ufs_reset;
-+};
-+
-+static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy);
-+static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy);
-+static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy);
-+static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy);
-+
-+static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy);
-+static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy);
-+static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy);
-+static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy);
-+
-+static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
-+{
-+ u32 reg;
-+
-+ reg = readl(base + offset);
-+ reg |= val;
-+ writel(reg, base + offset);
-+
-+ /* ensure that above write is through */
-+ readl(base + offset);
-+}
-+
-+static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
-+{
-+ u32 reg;
-+
-+ reg = readl(base + offset);
-+ reg &= ~val;
-+ writel(reg, base + offset);
-+
-+ /* ensure that above write is through */
-+ readl(base + offset);
-+}
-+
-+/* list of clocks required by phy */
-+static const char * const msm8996_phy_clk_l[] = {
-+ "aux", "cfg_ahb", "ref",
-+};
-+
-+static const char * const msm8996_ufs_phy_clk_l[] = {
-+ "ref",
-+};
-+
-+static const char * const qmp_v3_phy_clk_l[] = {
-+ "aux", "cfg_ahb", "ref", "com_aux",
-+};
-+
-+static const char * const sdm845_pciephy_clk_l[] = {
-+ "aux", "cfg_ahb", "ref", "refgen",
-+};
-+
-+static const char * const qmp_v4_phy_clk_l[] = {
-+ "aux", "ref_clk_src", "ref", "com_aux",
-+};
-+
-+/* the primary usb3 phy on sm8250 doesn't have a ref clock */
-+static const char * const qmp_v4_sm8250_usbphy_clk_l[] = {
-+ "aux", "ref_clk_src", "com_aux"
-+};
-+
-+static const char * const sm8450_ufs_phy_clk_l[] = {
-+ "qref", "ref", "ref_aux",
-+};
-+
-+static const char * const sdm845_ufs_phy_clk_l[] = {
-+ "ref", "ref_aux",
-+};
-+
-+/* usb3 phy on sdx55 doesn't have com_aux clock */
-+static const char * const qmp_v4_sdx55_usbphy_clk_l[] = {
-+ "aux", "cfg_ahb", "ref"
-+};
-+
-+static const char * const qcm2290_usb3phy_clk_l[] = {
-+ "cfg_ahb", "ref", "com_aux",
-+};
-+
-+/* list of resets */
-+static const char * const msm8996_pciephy_reset_l[] = {
-+ "phy", "common", "cfg",
-+};
-+
-+static const char * const msm8996_usb3phy_reset_l[] = {
-+ "phy", "common",
-+};
-+
-+static const char * const sc7180_usb3phy_reset_l[] = {
-+ "phy",
-+};
-+
-+static const char * const qcm2290_usb3phy_reset_l[] = {
-+ "phy_phy", "phy",
-+};
-+
-+static const char * const sdm845_pciephy_reset_l[] = {
-+ "phy",
-+};
-+
-+/* list of regulators */
-+static const char * const qmp_phy_vreg_l[] = {
-+ "vdda-phy", "vdda-pll",
-+};
-+
-+static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = ipq8074_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
-+ .tx_tbl = msm8996_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
-+ .rx_tbl = ipq8074_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
-+ .pcs_tbl = ipq8074_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
-+ .clk_list = msm8996_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+};
-+
-+static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 3,
-+
-+ .serdes_tbl = msm8996_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
-+ .tx_tbl = msm8996_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8996_pcie_tx_tbl),
-+ .rx_tbl = msm8996_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(msm8996_pcie_rx_tbl),
-+ .pcs_tbl = msm8996_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
-+ .clk_list = msm8996_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-+ .reset_list = msm8996_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = pciephy_regs_layout,
-+
-+ .start_ctrl = PCS_START | PLL_READY_GATE_EN,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .mask_com_pcs_ready = PCS_READY,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_phy_com_ctrl = true,
-+ .has_lane_rst = true,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg msm8996_ufs_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = msm8996_ufs_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(msm8996_ufs_serdes_tbl),
-+ .tx_tbl = msm8996_ufs_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8996_ufs_tx_tbl),
-+ .rx_tbl = msm8996_ufs_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(msm8996_ufs_rx_tbl),
-+
-+ .clk_list = msm8996_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
-+
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+
-+ .regs = msm8996_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .no_pcs_sw_reset = true,
-+};
-+
-+static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = msm8996_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
-+ .tx_tbl = msm8996_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
-+ .rx_tbl = msm8996_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl),
-+ .pcs_tbl = msm8996_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
-+ .clk_list = msm8996_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+};
-+
-+static const char * const ipq8074_pciephy_clk_l[] = {
-+ "aux", "cfg_ahb",
-+};
-+/* list of resets */
-+static const char * const ipq8074_pciephy_reset_l[] = {
-+ "phy", "common",
-+};
-+
-+static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = ipq8074_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
-+ .tx_tbl = ipq8074_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
-+ .rx_tbl = ipq8074_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
-+ .pcs_tbl = ipq8074_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
-+ .clk_list = ipq8074_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
-+ .reset_list = ipq8074_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
-+ .vreg_list = NULL,
-+ .num_vregs = 0,
-+ .regs = pciephy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_phy_com_ctrl = false,
-+ .has_lane_rst = false,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = ipq6018_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl),
-+ .tx_tbl = ipq6018_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl),
-+ .rx_tbl = ipq6018_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
-+ .pcs_tbl = ipq6018_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
-+ .clk_list = ipq8074_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
-+ .reset_list = ipq8074_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
-+ .vreg_list = NULL,
-+ .num_vregs = 0,
-+ .regs = ipq_pciephy_gen3_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+
-+ .has_phy_com_ctrl = false,
-+ .has_lane_rst = false,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sdm845_qmp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
-+ .tx_tbl = sdm845_qmp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),
-+ .rx_tbl = sdm845_qmp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),
-+ .pcs_tbl = sdm845_qmp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sdm845_qmp_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sdm845_qmp_pciephy_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sdm845_qhp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
-+ .tx_tbl = sdm845_qhp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
-+ .rx_tbl = sdm845_qhp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl),
-+ .pcs_tbl = sdm845_qhp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sdm845_qhp_pciephy_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
-+ .serdes_tbl_sec = sm8250_qmp_gen3x1_pcie_serdes_tbl,
-+ .serdes_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
-+ .tx_tbl = sm8250_qmp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
-+ .rx_tbl = sm8250_qmp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
-+ .rx_tbl_sec = sm8250_qmp_gen3x1_pcie_rx_tbl,
-+ .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),
-+ .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
-+ .pcs_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_tbl,
-+ .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
-+ .pcs_misc_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
-+ .tx_tbl = sm8250_qmp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
-+ .tx_tbl_sec = sm8250_qmp_gen3x2_pcie_tx_tbl,
-+ .tx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),
-+ .rx_tbl = sm8250_qmp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
-+ .rx_tbl_sec = sm8250_qmp_gen3x2_pcie_rx_tbl,
-+ .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl),
-+ .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
-+ .pcs_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_tbl,
-+ .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
-+ .pcs_misc_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v3_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
-+ .tx_tbl = qmp_v3_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
-+ .rx_tbl = qmp_v3_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
-+ .pcs_tbl = qmp_v3_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
-+ .clk_list = qmp_v3_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v3_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
-+ .tx_tbl = qmp_v3_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
-+ .rx_tbl = qmp_v3_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
-+ .pcs_tbl = qmp_v3_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
-+ .clk_list = qmp_v3_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-+ .reset_list = sc7180_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sc7180_dpphy_cfg = {
-+ .type = PHY_TYPE_DP,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v3_dp_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
-+ .tx_tbl = qmp_v3_dp_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
-+
-+ .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr,
-+ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
-+ .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr,
-+ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
-+ .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2,
-+ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
-+ .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3,
-+ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
-+
-+ .clk_list = qmp_v3_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-+ .reset_list = sc7180_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+
-+ .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init,
-+ .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx,
-+ .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy,
-+ .calibrate_dp_phy = qcom_qmp_v3_dp_phy_calibrate,
-+};
-+
-+static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = {
-+ .usb_cfg = &sc7180_usb3phy_cfg,
-+ .dp_cfg = &sc7180_dpphy_cfg,
-+};
-+
-+static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
-+ .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v3_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sdm845_ufsphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
-+ .tx_tbl = sdm845_ufsphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
-+ .rx_tbl = sdm845_ufsphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
-+ .pcs_tbl = sdm845_ufsphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
-+ .clk_list = sdm845_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sdm845_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+ .no_pcs_sw_reset = true,
-+};
-+
-+static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm6115_ufsphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl),
-+ .tx_tbl = sm6115_ufsphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_tx_tbl),
-+ .rx_tbl = sm6115_ufsphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_rx_tbl),
-+ .pcs_tbl = sm6115_ufsphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl),
-+ .clk_list = sdm845_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm6115_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+
-+ .is_dual_lane_phy = false,
-+ .no_pcs_sw_reset = true,
-+};
-+
-+static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = msm8998_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
-+ .tx_tbl = msm8998_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8998_pcie_tx_tbl),
-+ .rx_tbl = msm8998_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(msm8998_pcie_rx_tbl),
-+ .pcs_tbl = msm8998_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
-+ .clk_list = msm8996_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-+ .reset_list = ipq8074_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = pciephy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+};
-+
-+static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = msm8998_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
-+ .tx_tbl = msm8998_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl),
-+ .rx_tbl = msm8998_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl),
-+ .pcs_tbl = msm8998_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
-+ .clk_list = msm8996_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sm8150_ufsphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl),
-+ .tx_tbl = sm8150_ufsphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx_tbl),
-+ .rx_tbl = sm8150_ufsphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx_tbl),
-+ .pcs_tbl = sm8150_ufsphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl),
-+ .clk_list = sdm845_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8150_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
-+ .tx_tbl = sm8150_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl),
-+ .rx_tbl = sm8150_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl),
-+ .pcs_tbl = sm8150_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
-+ .clk_list = qmp_v4_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sc8180x_qmp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl),
-+ .tx_tbl = sc8180x_qmp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl),
-+ .rx_tbl = sc8180x_qmp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl),
-+ .pcs_tbl = sc8180x_qmp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sc8180x_qmp_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sc8180x_dpphy_cfg = {
-+ .type = PHY_TYPE_DP,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v4_dp_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
-+ .tx_tbl = qmp_v4_dp_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
-+
-+ .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
-+ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
-+ .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
-+ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
-+ .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
-+ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
-+ .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
-+ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
-+
-+ .clk_list = qmp_v3_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-+ .reset_list = sc7180_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+
-+ .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
-+ .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
-+ .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
-+ .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
-+};
-+
-+static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = {
-+ .usb_cfg = &sm8150_usb3phy_cfg,
-+ .dp_cfg = &sc8180x_dpphy_cfg,
-+};
-+
-+static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = sm8150_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),
-+ .rx_tbl = sm8150_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = sm8150_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v4_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3_uniphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
-+ .tx_tbl = sm8250_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl),
-+ .rx_tbl = sm8250_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl),
-+ .pcs_tbl = sm8250_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
-+ .clk_list = qmp_v4_sm8250_usbphy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = sm8250_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),
-+ .rx_tbl = sm8250_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v4_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3_uniphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sm8250_dpphy_cfg = {
-+ .type = PHY_TYPE_DP,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v4_dp_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
-+ .tx_tbl = qmp_v4_dp_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
-+
-+ .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
-+ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
-+ .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
-+ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
-+ .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
-+ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
-+ .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
-+ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
-+
-+ .clk_list = qmp_v4_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3phy_regs_layout,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+
-+ .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
-+ .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
-+ .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
-+ .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
-+};
-+
-+static const struct qmp_phy_combo_cfg sm8250_usb3dpphy_cfg = {
-+ .usb_cfg = &sm8250_usb3phy_cfg,
-+ .dp_cfg = &sm8250_dpphy_cfg,
-+};
-+
-+static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = sdx55_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl),
-+ .rx_tbl = sdx55_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v4_sdx55_usbphy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3_uniphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sdx55_qmp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl),
-+ .tx_tbl = sdx55_qmp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl),
-+ .rx_tbl = sdx55_qmp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl),
-+ .pcs_tbl = sdx55_qmp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sdx55_qmp_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS_4_20,
-+
-+ .is_dual_lane_phy = true,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = sdx65_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl),
-+ .rx_tbl = sdx65_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v4_sdx55_usbphy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8350_usb3_uniphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sm8350_ufsphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
-+ .tx_tbl = sm8350_ufsphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
-+ .rx_tbl = sm8350_ufsphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
-+ .pcs_tbl = sm8350_ufsphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
-+ .clk_list = sdm845_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8150_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
-+ .tx_tbl = sm8350_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl),
-+ .rx_tbl = sm8350_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl),
-+ .pcs_tbl = sm8350_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl),
-+ .clk_list = qmp_v4_sm8250_usbphy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = sm8350_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),
-+ .rx_tbl = sm8350_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v4_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8350_usb3_uniphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sm8350_ufsphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
-+ .tx_tbl = sm8350_ufsphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
-+ .rx_tbl = sm8350_ufsphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
-+ .pcs_tbl = sm8350_ufsphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
-+ .clk_list = sm8450_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8150_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8450_qmp_gen3x1_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl),
-+ .tx_tbl = sm8450_qmp_gen3x1_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl),
-+ .rx_tbl = sm8450_qmp_gen3x1_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl),
-+ .pcs_tbl = sm8450_qmp_gen3x1_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sm8450_qmp_gen4x2_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl),
-+ .tx_tbl = sm8450_qmp_gen4x2_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl),
-+ .rx_tbl = sm8450_qmp_gen4x2_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl),
-+ .pcs_tbl = sm8450_qmp_gen4x2_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS_4_20,
-+
-+ .is_dual_lane_phy = true,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qcm2290_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl),
-+ .tx_tbl = qcm2290_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl),
-+ .rx_tbl = qcm2290_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(qcm2290_usb3_rx_tbl),
-+ .pcs_tbl = qcm2290_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl),
-+ .clk_list = qcm2290_usb3phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qcm2290_usb3phy_clk_l),
-+ .reset_list = qcm2290_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qcm2290_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+};
-+
-+static void qcom_qmp_phy_configure_lane(void __iomem *base,
-+ const unsigned int *regs,
-+ const struct qmp_phy_init_tbl tbl[],
-+ int num,
-+ u8 lane_mask)
-+{
-+ int i;
-+ const struct qmp_phy_init_tbl *t = tbl;
-+
-+ if (!t)
-+ return;
-+
-+ for (i = 0; i < num; i++, t++) {
-+ if (!(t->lane_mask & lane_mask))
-+ continue;
-+
-+ if (t->in_layout)
-+ writel(t->val, base + regs[t->offset]);
-+ else
-+ writel(t->val, base + t->offset);
-+ }
-+}
-+
-+static void qcom_qmp_phy_configure(void __iomem *base,
-+ const unsigned int *regs,
-+ const struct qmp_phy_init_tbl tbl[],
-+ int num)
-+{
-+ qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff);
-+}
-+
-+static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
-+{
-+ struct qcom_qmp *qmp = qphy->qmp;
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *serdes = qphy->serdes;
-+ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-+ const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
-+ int serdes_tbl_num = cfg->serdes_tbl_num;
-+ int ret;
-+
-+ qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
-+ if (cfg->serdes_tbl_sec)
-+ qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
-+ cfg->serdes_tbl_num_sec);
-+
-+ if (cfg->type == PHY_TYPE_DP) {
-+ switch (dp_opts->link_rate) {
-+ case 1620:
-+ qcom_qmp_phy_configure(serdes, cfg->regs,
-+ cfg->serdes_tbl_rbr,
-+ cfg->serdes_tbl_rbr_num);
-+ break;
-+ case 2700:
-+ qcom_qmp_phy_configure(serdes, cfg->regs,
-+ cfg->serdes_tbl_hbr,
-+ cfg->serdes_tbl_hbr_num);
-+ break;
-+ case 5400:
-+ qcom_qmp_phy_configure(serdes, cfg->regs,
-+ cfg->serdes_tbl_hbr2,
-+ cfg->serdes_tbl_hbr2_num);
-+ break;
-+ case 8100:
-+ qcom_qmp_phy_configure(serdes, cfg->regs,
-+ cfg->serdes_tbl_hbr3,
-+ cfg->serdes_tbl_hbr3_num);
-+ break;
-+ default:
-+ /* Other link rates aren't supported */
-+ return -EINVAL;
-+ }
-+ }
-+
-+
-+ if (cfg->has_phy_com_ctrl) {
-+ void __iomem *status;
-+ unsigned int mask, val;
-+
-+ qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
-+ qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
-+ SERDES_START | PCS_START);
-+
-+ status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
-+ mask = cfg->mask_com_pcs_ready;
-+
-+ ret = readl_poll_timeout(status, val, (val & mask), 10,
-+ PHY_INIT_COMPLETE_TIMEOUT);
-+ if (ret) {
-+ dev_err(qmp->dev,
-+ "phy common block init timed-out\n");
-+ return ret;
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy)
-+{
-+ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
-+ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
-+ qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+
-+ /* Turn on BIAS current for PHY/PLL */
-+ writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
-+ QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
-+ qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
-+
-+ writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+
-+ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
-+ DP_PHY_PD_CTL_LANE_0_1_PWRDN |
-+ DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
-+ DP_PHY_PD_CTL_DP_CLAMP_EN,
-+ qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+
-+ writel(QSERDES_V3_COM_BIAS_EN |
-+ QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
-+ QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL |
-+ QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
-+ qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
-+
-+ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
-+ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-+ writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
-+ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
-+ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
-+ writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
-+ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
-+ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
-+ writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
-+ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
-+ qphy->dp_aux_cfg = 0;
-+
-+ writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
-+ PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
-+ PHY_AUX_REQ_ERR_MASK,
-+ qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
-+}
-+
-+static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = {
-+ { 0x00, 0x0c, 0x15, 0x1a },
-+ { 0x02, 0x0e, 0x16, 0xff },
-+ { 0x02, 0x11, 0xff, 0xff },
-+ { 0x04, 0xff, 0xff, 0xff }
-+};
-+
-+static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = {
-+ { 0x02, 0x12, 0x16, 0x1a },
-+ { 0x09, 0x19, 0x1f, 0xff },
-+ { 0x10, 0x1f, 0xff, 0xff },
-+ { 0x1f, 0xff, 0xff, 0xff }
-+};
-+
-+static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = {
-+ { 0x00, 0x0c, 0x14, 0x19 },
-+ { 0x00, 0x0b, 0x12, 0xff },
-+ { 0x00, 0x0b, 0xff, 0xff },
-+ { 0x04, 0xff, 0xff, 0xff }
-+};
-+
-+static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = {
-+ { 0x08, 0x0f, 0x16, 0x1f },
-+ { 0x11, 0x1e, 0x1f, 0xff },
-+ { 0x19, 0x1f, 0xff, 0xff },
-+ { 0x1f, 0xff, 0xff, 0xff }
-+};
-+
-+static int qcom_qmp_phy_configure_dp_swing(struct qmp_phy *qphy,
-+ unsigned int drv_lvl_reg, unsigned int emp_post_reg)
-+{
-+ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-+ unsigned int v_level = 0, p_level = 0;
-+ u8 voltage_swing_cfg, pre_emphasis_cfg;
-+ int i;
-+
-+ for (i = 0; i < dp_opts->lanes; i++) {
-+ v_level = max(v_level, dp_opts->voltage[i]);
-+ p_level = max(p_level, dp_opts->pre[i]);
-+ }
-+
-+ if (dp_opts->link_rate <= 2700) {
-+ voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level];
-+ pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level];
-+ } else {
-+ voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr3_hbr2[v_level][p_level];
-+ pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr3_hbr2[v_level][p_level];
-+ }
-+
-+ /* TODO: Move check to config check */
-+ if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF)
-+ return -EINVAL;
-+
-+ /* Enable MUX to use Cursor values from these registers */
-+ voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
-+ pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
-+
-+ writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg);
-+ writel(pre_emphasis_cfg, qphy->tx + emp_post_reg);
-+ writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg);
-+ writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg);
-+
-+ return 0;
-+}
-+
-+static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy)
-+{
-+ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-+ u32 bias_en, drvr_en;
-+
-+ if (qcom_qmp_phy_configure_dp_swing(qphy,
-+ QSERDES_V3_TX_TX_DRV_LVL,
-+ QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0)
-+ return;
-+
-+ if (dp_opts->lanes == 1) {
-+ bias_en = 0x3e;
-+ drvr_en = 0x13;
-+ } else {
-+ bias_en = 0x3f;
-+ drvr_en = 0x10;
-+ }
-+
-+ writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN);
-+ writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
-+ writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN);
-+ writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
-+}
-+
-+static bool qcom_qmp_phy_configure_dp_mode(struct qmp_phy *qphy)
-+{
-+ u32 val;
-+ bool reverse = false;
-+
-+ val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
-+ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN;
-+
-+ /*
-+ * TODO: Assume orientation is CC1 for now and two lanes, need to
-+ * use type-c connector to understand orientation and lanes.
-+ *
-+ * Otherwise val changes to be like below if this code understood
-+ * the orientation of the type-c cable.
-+ *
-+ * if (lane_cnt == 4 || orientation == ORIENTATION_CC2)
-+ * val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN;
-+ * if (lane_cnt == 4 || orientation == ORIENTATION_CC1)
-+ * val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
-+ * if (orientation == ORIENTATION_CC2)
-+ * writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
-+ */
-+ val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
-+ writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+
-+ writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE);
-+
-+ return reverse;
-+}
-+
-+static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy)
-+{
-+ const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
-+ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-+ u32 phy_vco_div, status;
-+ unsigned long pixel_freq;
-+
-+ qcom_qmp_phy_configure_dp_mode(qphy);
-+
-+ writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
-+ writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
-+
-+ switch (dp_opts->link_rate) {
-+ case 1620:
-+ phy_vco_div = 0x1;
-+ pixel_freq = 1620000000UL / 2;
-+ break;
-+ case 2700:
-+ phy_vco_div = 0x1;
-+ pixel_freq = 2700000000UL / 2;
-+ break;
-+ case 5400:
-+ phy_vco_div = 0x2;
-+ pixel_freq = 5400000000UL / 4;
-+ break;
-+ case 8100:
-+ phy_vco_div = 0x0;
-+ pixel_freq = 8100000000UL / 6;
-+ break;
-+ default:
-+ /* Other link rates aren't supported */
-+ return -EINVAL;
-+ }
-+ writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV);
-+
-+ clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
-+ clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
-+
-+ writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
-+ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL);
-+
-+ if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS,
-+ status,
-+ ((status & BIT(0)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
-+ status,
-+ ((status & BIT(1)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ udelay(2000);
-+ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
-+ status,
-+ ((status & BIT(1)) > 0),
-+ 500,
-+ 10000);
-+}
-+
-+/*
-+ * We need to calibrate the aux setting here as many times
-+ * as the caller tries
-+ */
-+static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy)
-+{
-+ static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d };
-+ u8 val;
-+
-+ qphy->dp_aux_cfg++;
-+ qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
-+ val = cfg1_settings[qphy->dp_aux_cfg];
-+
-+ writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-+
-+ return 0;
-+}
-+
-+static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy)
-+{
-+ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
-+ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
-+ qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+
-+ /* Turn on BIAS current for PHY/PLL */
-+ writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN);
-+
-+ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
-+ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-+ writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
-+ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
-+ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
-+ writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
-+ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
-+ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
-+ writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
-+ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
-+ qphy->dp_aux_cfg = 0;
-+
-+ writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
-+ PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
-+ PHY_AUX_REQ_ERR_MASK,
-+ qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
-+}
-+
-+static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy)
-+{
-+ /* Program default values before writing proper values */
-+ writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
-+ writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
-+
-+ writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
-+ writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
-+
-+ qcom_qmp_phy_configure_dp_swing(qphy,
-+ QSERDES_V4_TX_TX_DRV_LVL,
-+ QSERDES_V4_TX_TX_EMP_POST1_LVL);
-+}
-+
-+static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy)
-+{
-+ const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
-+ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-+ u32 phy_vco_div, status;
-+ unsigned long pixel_freq;
-+ u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
-+ bool reverse;
-+
-+ writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1);
-+
-+ reverse = qcom_qmp_phy_configure_dp_mode(qphy);
-+
-+ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-+ writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
-+
-+ writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL);
-+ writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL);
-+
-+ switch (dp_opts->link_rate) {
-+ case 1620:
-+ phy_vco_div = 0x1;
-+ pixel_freq = 1620000000UL / 2;
-+ break;
-+ case 2700:
-+ phy_vco_div = 0x1;
-+ pixel_freq = 2700000000UL / 2;
-+ break;
-+ case 5400:
-+ phy_vco_div = 0x2;
-+ pixel_freq = 5400000000UL / 4;
-+ break;
-+ case 8100:
-+ phy_vco_div = 0x0;
-+ pixel_freq = 8100000000UL / 6;
-+ break;
-+ default:
-+ /* Other link rates aren't supported */
-+ return -EINVAL;
-+ }
-+ writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV);
-+
-+ clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
-+ clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
-+
-+ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL);
-+
-+ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS,
-+ status,
-+ ((status & BIT(0)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
-+ status,
-+ ((status & BIT(0)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
-+ status,
-+ ((status & BIT(1)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
-+ status,
-+ ((status & BIT(0)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
-+ status,
-+ ((status & BIT(1)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ /*
-+ * At least for 7nm DP PHY this has to be done after enabling link
-+ * clock.
-+ */
-+
-+ if (dp_opts->lanes == 1) {
-+ bias0_en = reverse ? 0x3e : 0x15;
-+ bias1_en = reverse ? 0x15 : 0x3e;
-+ drvr0_en = reverse ? 0x13 : 0x10;
-+ drvr1_en = reverse ? 0x10 : 0x13;
-+ } else if (dp_opts->lanes == 2) {
-+ bias0_en = reverse ? 0x3f : 0x15;
-+ bias1_en = reverse ? 0x15 : 0x3f;
-+ drvr0_en = 0x10;
-+ drvr1_en = 0x10;
-+ } else {
-+ bias0_en = 0x3f;
-+ bias1_en = 0x3f;
-+ drvr0_en = 0x10;
-+ drvr1_en = 0x10;
-+ }
-+
-+ writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN);
-+ writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
-+ writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN);
-+ writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
-+
-+ writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ udelay(2000);
-+ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
-+ status,
-+ ((status & BIT(1)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV);
-+ writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV);
-+
-+ writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
-+ writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
-+
-+ writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
-+ writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
-+
-+ return 0;
-+}
-+
-+/*
-+ * We need to calibrate the aux setting here as many times
-+ * as the caller tries
-+ */
-+static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy)
-+{
-+ static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d };
-+ u8 val;
-+
-+ qphy->dp_aux_cfg++;
-+ qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
-+ val = cfg1_settings[qphy->dp_aux_cfg];
-+
-+ writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
-+{
-+ const struct phy_configure_opts_dp *dp_opts = &opts->dp;
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+
-+ memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts));
-+ if (qphy->dp_opts.set_voltages) {
-+ cfg->configure_dp_tx(qphy);
-+ qphy->dp_opts.set_voltages = 0;
-+ }
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_dp_phy_calibrate(struct phy *phy)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+
-+ if (cfg->calibrate_dp_phy)
-+ return cfg->calibrate_dp_phy(qphy);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
-+{
-+ struct qcom_qmp *qmp = qphy->qmp;
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *serdes = qphy->serdes;
-+ void __iomem *pcs = qphy->pcs;
-+ void __iomem *dp_com = qmp->dp_com;
-+ int ret, i;
-+
-+ mutex_lock(&qmp->phy_mutex);
-+ if (qmp->init_count++) {
-+ mutex_unlock(&qmp->phy_mutex);
-+ return 0;
-+ }
-+
-+ /* turn on regulator supplies */
-+ ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
-+ if (ret) {
-+ dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
-+ goto err_unlock;
-+ }
-+
-+ for (i = 0; i < cfg->num_resets; i++) {
-+ ret = reset_control_assert(qmp->resets[i]);
-+ if (ret) {
-+ dev_err(qmp->dev, "%s reset assert failed\n",
-+ cfg->reset_list[i]);
-+ goto err_disable_regulators;
-+ }
-+ }
-+
-+ for (i = cfg->num_resets - 1; i >= 0; i--) {
-+ ret = reset_control_deassert(qmp->resets[i]);
-+ if (ret) {
-+ dev_err(qmp->dev, "%s reset deassert failed\n",
-+ qphy->cfg->reset_list[i]);
-+ goto err_assert_reset;
-+ }
-+ }
-+
-+ ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
-+ if (ret)
-+ goto err_assert_reset;
-+
-+ if (cfg->has_phy_dp_com_ctrl) {
-+ qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
-+ SW_PWRDN);
-+ /* override hardware control for reset of qmp phy */
-+ qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
-+ SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
-+ SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
-+
-+ /* Default type-c orientation, i.e CC1 */
-+ qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02);
-+
-+ qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
-+ USB3_MODE | DP_MODE);
-+
-+ /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
-+ qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
-+ SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
-+ SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
-+
-+ qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
-+ qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
-+ }
-+
-+ if (cfg->has_phy_com_ctrl) {
-+ qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
-+ SW_PWRDN);
-+ } else {
-+ if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
-+ qphy_setbits(pcs,
-+ cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
-+ cfg->pwrdn_ctrl);
-+ else
-+ qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
-+ cfg->pwrdn_ctrl);
-+ }
-+
-+ mutex_unlock(&qmp->phy_mutex);
-+
-+ return 0;
-+
-+err_assert_reset:
-+ while (++i < cfg->num_resets)
-+ reset_control_assert(qmp->resets[i]);
-+err_disable_regulators:
-+ regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
-+err_unlock:
-+ mutex_unlock(&qmp->phy_mutex);
-+
-+ return ret;
-+}
-+
-+static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy)
-+{
-+ struct qcom_qmp *qmp = qphy->qmp;
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *serdes = qphy->serdes;
-+ int i = cfg->num_resets;
-+
-+ mutex_lock(&qmp->phy_mutex);
-+ if (--qmp->init_count) {
-+ mutex_unlock(&qmp->phy_mutex);
-+ return 0;
-+ }
-+
-+ reset_control_assert(qmp->ufs_reset);
-+ if (cfg->has_phy_com_ctrl) {
-+ qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
-+ SERDES_START | PCS_START);
-+ qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
-+ SW_RESET);
-+ qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
-+ SW_PWRDN);
-+ }
-+
-+ while (--i >= 0)
-+ reset_control_assert(qmp->resets[i]);
-+
-+ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
-+
-+ regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
-+
-+ mutex_unlock(&qmp->phy_mutex);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_init(struct phy *phy)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ struct qcom_qmp *qmp = qphy->qmp;
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ int ret;
-+ dev_vdbg(qmp->dev, "Initializing QMP phy\n");
-+
-+ if (cfg->no_pcs_sw_reset) {
-+ /*
-+ * Get UFS reset, which is delayed until now to avoid a
-+ * circular dependency where UFS needs its PHY, but the PHY
-+ * needs this UFS reset.
-+ */
-+ if (!qmp->ufs_reset) {
-+ qmp->ufs_reset =
-+ devm_reset_control_get_exclusive(qmp->dev,
-+ "ufsphy");
-+
-+ if (IS_ERR(qmp->ufs_reset)) {
-+ ret = PTR_ERR(qmp->ufs_reset);
-+ dev_err(qmp->dev,
-+ "failed to get UFS reset: %d\n",
-+ ret);
-+
-+ qmp->ufs_reset = NULL;
-+ return ret;
-+ }
-+ }
-+
-+ ret = reset_control_assert(qmp->ufs_reset);
-+ if (ret)
-+ return ret;
-+ }
-+
-+ ret = qcom_qmp_phy_com_init(qphy);
-+ if (ret)
-+ return ret;
-+
-+ if (cfg->type == PHY_TYPE_DP)
-+ cfg->dp_aux_init(qphy);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_power_on(struct phy *phy)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ struct qcom_qmp *qmp = qphy->qmp;
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *tx = qphy->tx;
-+ void __iomem *rx = qphy->rx;
-+ void __iomem *pcs = qphy->pcs;
-+ void __iomem *pcs_misc = qphy->pcs_misc;
-+ void __iomem *status;
-+ unsigned int mask, val, ready;
-+ int ret;
-+
-+ qcom_qmp_phy_serdes_init(qphy);
-+
-+ if (cfg->has_lane_rst) {
-+ ret = reset_control_deassert(qphy->lane_rst);
-+ if (ret) {
-+ dev_err(qmp->dev, "lane%d reset deassert failed\n",
-+ qphy->index);
-+ return ret;
-+ }
-+ }
-+
-+ ret = clk_prepare_enable(qphy->pipe_clk);
-+ if (ret) {
-+ dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
-+ goto err_reset_lane;
-+ }
-+
-+ /* Tx, Rx, and PCS configurations */
-+ qcom_qmp_phy_configure_lane(tx, cfg->regs,
-+ cfg->tx_tbl, cfg->tx_tbl_num, 1);
-+ if (cfg->tx_tbl_sec)
-+ qcom_qmp_phy_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
-+ cfg->tx_tbl_num_sec, 1);
-+
-+ /* Configuration for other LANE for USB-DP combo PHY */
-+ if (cfg->is_dual_lane_phy) {
-+ qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
-+ cfg->tx_tbl, cfg->tx_tbl_num, 2);
-+ if (cfg->tx_tbl_sec)
-+ qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
-+ cfg->tx_tbl_sec,
-+ cfg->tx_tbl_num_sec, 2);
-+ }
-+
-+ /* Configure special DP tx tunings */
-+ if (cfg->type == PHY_TYPE_DP)
-+ cfg->configure_dp_tx(qphy);
-+
-+ qcom_qmp_phy_configure_lane(rx, cfg->regs,
-+ cfg->rx_tbl, cfg->rx_tbl_num, 1);
-+ if (cfg->rx_tbl_sec)
-+ qcom_qmp_phy_configure_lane(rx, cfg->regs,
-+ cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1);
-+
-+ if (cfg->is_dual_lane_phy) {
-+ qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
-+ cfg->rx_tbl, cfg->rx_tbl_num, 2);
-+ if (cfg->rx_tbl_sec)
-+ qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
-+ cfg->rx_tbl_sec,
-+ cfg->rx_tbl_num_sec, 2);
-+ }
-+
-+ /* Configure link rate, swing, etc. */
-+ if (cfg->type == PHY_TYPE_DP) {
-+ cfg->configure_dp_phy(qphy);
-+ } else {
-+ qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
-+ if (cfg->pcs_tbl_sec)
-+ qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
-+ cfg->pcs_tbl_num_sec);
-+ }
-+
-+ ret = reset_control_deassert(qmp->ufs_reset);
-+ if (ret)
-+ goto err_disable_pipe_clk;
-+
-+ qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
-+ cfg->pcs_misc_tbl_num);
-+ if (cfg->pcs_misc_tbl_sec)
-+ qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
-+ cfg->pcs_misc_tbl_num_sec);
-+
-+ /*
-+ * Pull out PHY from POWER DOWN state.
-+ * This is active low enable signal to power-down PHY.
-+ */
-+ if(cfg->type == PHY_TYPE_PCIE)
-+ qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
-+
-+ if (cfg->has_pwrdn_delay)
-+ usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
-+
-+ if (cfg->type != PHY_TYPE_DP) {
-+ /* Pull PHY out of reset state */
-+ if (!cfg->no_pcs_sw_reset)
-+ qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
-+ /* start SerDes and Phy-Coding-Sublayer */
-+ qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
-+
-+ if (cfg->type == PHY_TYPE_UFS) {
-+ status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
-+ mask = PCS_READY;
-+ ready = PCS_READY;
-+ } else {
-+ status = pcs + cfg->regs[QPHY_PCS_STATUS];
-+ mask = cfg->phy_status;
-+ ready = 0;
-+ }
-+
-+ ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
-+ PHY_INIT_COMPLETE_TIMEOUT);
-+ if (ret) {
-+ dev_err(qmp->dev, "phy initialization timed-out\n");
-+ goto err_disable_pipe_clk;
-+ }
-+ }
-+ return 0;
-+
-+err_disable_pipe_clk:
-+ clk_disable_unprepare(qphy->pipe_clk);
-+err_reset_lane:
-+ if (cfg->has_lane_rst)
-+ reset_control_assert(qphy->lane_rst);
-+
-+ return ret;
-+}
-+
-+static int qcom_qmp_phy_power_off(struct phy *phy)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+
-+ clk_disable_unprepare(qphy->pipe_clk);
-+
-+ if (cfg->type == PHY_TYPE_DP) {
-+ /* Assert DP PHY power down */
-+ writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+ } else {
-+ /* PHY reset */
-+ if (!cfg->no_pcs_sw_reset)
-+ qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
-+
-+ /* stop SerDes and Phy-Coding-Sublayer */
-+ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
-+
-+ /* Put PHY into POWER DOWN state: active low */
-+ if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
-+ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
-+ cfg->pwrdn_ctrl);
-+ } else {
-+ qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
-+ cfg->pwrdn_ctrl);
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_exit(struct phy *phy)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+
-+ if (cfg->has_lane_rst)
-+ reset_control_assert(qphy->lane_rst);
-+
-+ qcom_qmp_phy_com_exit(qphy);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_enable(struct phy *phy)
-+{
-+ int ret;
-+
-+ ret = qcom_qmp_phy_init(phy);
-+ if (ret)
-+ return ret;
-+
-+ ret = qcom_qmp_phy_power_on(phy);
-+ if (ret)
-+ qcom_qmp_phy_exit(phy);
-+
-+ return ret;
-+}
-+
-+static int qcom_qmp_phy_disable(struct phy *phy)
-+{
-+ int ret;
-+
-+ ret = qcom_qmp_phy_power_off(phy);
-+ if (ret)
-+ return ret;
-+ return qcom_qmp_phy_exit(phy);
-+}
-+
-+static int qcom_qmp_phy_set_mode(struct phy *phy,
-+ enum phy_mode mode, int submode)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+
-+ qphy->mode = mode;
-+
-+ return 0;
-+}
-+
-+static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
-+{
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *pcs = qphy->pcs;
-+ void __iomem *pcs_misc = qphy->pcs_misc;
-+ u32 intr_mask;
-+
-+ if (qphy->mode == PHY_MODE_USB_HOST_SS ||
-+ qphy->mode == PHY_MODE_USB_DEVICE_SS)
-+ intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
-+ else
-+ intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
-+
-+ /* Clear any pending interrupts status */
-+ qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
-+ /* Writing 1 followed by 0 clears the interrupt */
-+ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
-+
-+ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
-+ ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
-+
-+ /* Enable required PHY autonomous mode interrupts */
-+ qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
-+
-+ /* Enable i/o clamp_n for autonomous mode */
-+ if (pcs_misc)
-+ qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
-+}
-+
-+static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
-+{
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *pcs = qphy->pcs;
-+ void __iomem *pcs_misc = qphy->pcs_misc;
-+
-+ /* Disable i/o clamp_n on resume for normal mode */
-+ if (pcs_misc)
-+ qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
-+
-+ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
-+ ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
-+
-+ qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
-+ /* Writing 1 followed by 0 clears the interrupt */
-+ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
-+}
-+
-+static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ struct qmp_phy *qphy = qmp->phys[0];
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+
-+ dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode);
-+
-+ /* Supported only for USB3 PHY and luckily USB3 is the first phy */
-+ if (cfg->type != PHY_TYPE_USB3)
-+ return 0;
-+
-+ if (!qmp->init_count) {
-+ dev_vdbg(dev, "PHY not initialized, bailing out\n");
-+ return 0;
-+ }
-+
-+ qcom_qmp_phy_enable_autonomous_mode(qphy);
-+
-+ clk_disable_unprepare(qphy->pipe_clk);
-+ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
-+
-+ return 0;
-+}
-+
-+static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ struct qmp_phy *qphy = qmp->phys[0];
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ int ret = 0;
-+
-+ dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode);
-+
-+ /* Supported only for USB3 PHY and luckily USB3 is the first phy */
-+ if (cfg->type != PHY_TYPE_USB3)
-+ return 0;
-+
-+ if (!qmp->init_count) {
-+ dev_vdbg(dev, "PHY not initialized, bailing out\n");
-+ return 0;
-+ }
-+
-+ ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
-+ if (ret)
-+ return ret;
-+
-+ ret = clk_prepare_enable(qphy->pipe_clk);
-+ if (ret) {
-+ dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
-+ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
-+ return ret;
-+ }
-+
-+ qcom_qmp_phy_disable_autonomous_mode(qphy);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ int num = cfg->num_vregs;
-+ int i;
-+
-+ qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
-+ if (!qmp->vregs)
-+ return -ENOMEM;
-+
-+ for (i = 0; i < num; i++)
-+ qmp->vregs[i].supply = cfg->vreg_list[i];
-+
-+ return devm_regulator_bulk_get(dev, num, qmp->vregs);
-+}
-+
-+static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ int i;
-+
-+ qmp->resets = devm_kcalloc(dev, cfg->num_resets,
-+ sizeof(*qmp->resets), GFP_KERNEL);
-+ if (!qmp->resets)
-+ return -ENOMEM;
-+
-+ for (i = 0; i < cfg->num_resets; i++) {
-+ struct reset_control *rst;
-+ const char *name = cfg->reset_list[i];
-+
-+ rst = devm_reset_control_get_exclusive(dev, name);
-+ if (IS_ERR(rst)) {
-+ dev_err(dev, "failed to get %s reset\n", name);
-+ return PTR_ERR(rst);
-+ }
-+ qmp->resets[i] = rst;
-+ }
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ int num = cfg->num_clks;
-+ int i;
-+
-+ qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
-+ if (!qmp->clks)
-+ return -ENOMEM;
-+
-+ for (i = 0; i < num; i++)
-+ qmp->clks[i].id = cfg->clk_list[i];
-+
-+ return devm_clk_bulk_get(dev, num, qmp->clks);
-+}
-+
-+static void phy_clk_release_provider(void *res)
-+{
-+ of_clk_del_provider(res);
-+}
-+
-+/*
-+ * Register a fixed rate pipe clock.
-+ *
-+ * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
-+ * controls it. The <s>_pipe_clk coming out of the GCC is requested
-+ * by the PHY driver for its operations.
-+ * We register the <s>_pipe_clksrc here. The gcc driver takes care
-+ * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
-+ * Below picture shows this relationship.
-+ *
-+ * +---------------+
-+ * | PHY block |<<---------------------------------------+
-+ * | | |
-+ * | +-------+ | +-----+ |
-+ * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
-+ * clk | +-------+ | +-----+
-+ * +---------------+
-+ */
-+static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
-+{
-+ struct clk_fixed_rate *fixed;
-+ struct clk_init_data init = { };
-+ int ret;
-+
-+ ret = of_property_read_string(np, "clock-output-names", &init.name);
-+ if (ret) {
-+ dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
-+ return ret;
-+ }
-+
-+ fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
-+ if (!fixed)
-+ return -ENOMEM;
-+
-+ init.ops = &clk_fixed_rate_ops;
-+
-+ /* controllers using QMP phys use 125MHz pipe clock interface */
-+ fixed->fixed_rate = 125000000;
-+ fixed->hw.init = &init;
-+
-+ ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
-+ if (ret)
-+ return ret;
-+
-+ ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
-+ if (ret)
-+ return ret;
-+
-+ /*
-+ * Roll a devm action because the clock provider is the child node, but
-+ * the child node is not actually a device.
-+ */
-+ return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
-+}
-+
-+/*
-+ * Display Port PLL driver block diagram for branch clocks
-+ *
-+ * +------------------------------+
-+ * | DP_VCO_CLK |
-+ * | |
-+ * | +-------------------+ |
-+ * | | (DP PLL/VCO) | |
-+ * | +---------+---------+ |
-+ * | v |
-+ * | +----------+-----------+ |
-+ * | | hsclk_divsel_clk_src | |
-+ * | +----------+-----------+ |
-+ * +------------------------------+
-+ * |
-+ * +---------<---------v------------>----------+
-+ * | |
-+ * +--------v----------------+ |
-+ * | dp_phy_pll_link_clk | |
-+ * | link_clk | |
-+ * +--------+----------------+ |
-+ * | |
-+ * | |
-+ * v v
-+ * Input to DISPCC block |
-+ * for link clk, crypto clk |
-+ * and interface clock |
-+ * |
-+ * |
-+ * +--------<------------+-----------------+---<---+
-+ * | | |
-+ * +----v---------+ +--------v-----+ +--------v------+
-+ * | vco_divided | | vco_divided | | vco_divided |
-+ * | _clk_src | | _clk_src | | _clk_src |
-+ * | | | | | |
-+ * |divsel_six | | divsel_two | | divsel_four |
-+ * +-------+------+ +-----+--------+ +--------+------+
-+ * | | |
-+ * v---->----------v-------------<------v
-+ * |
-+ * +----------+-----------------+
-+ * | dp_phy_pll_vco_div_clk |
-+ * +---------+------------------+
-+ * |
-+ * v
-+ * Input to DISPCC block
-+ * for DP pixel clock
-+ *
-+ */
-+static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw,
-+ struct clk_rate_request *req)
-+{
-+ switch (req->rate) {
-+ case 1620000000UL / 2:
-+ case 2700000000UL / 2:
-+ /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */
-+ return 0;
-+ default:
-+ return -EINVAL;
-+ }
-+}
-+
-+static unsigned long
-+qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
-+{
-+ const struct qmp_phy_dp_clks *dp_clks;
-+ const struct qmp_phy *qphy;
-+ const struct phy_configure_opts_dp *dp_opts;
-+
-+ dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw);
-+ qphy = dp_clks->qphy;
-+ dp_opts = &qphy->dp_opts;
-+
-+ switch (dp_opts->link_rate) {
-+ case 1620:
-+ return 1620000000UL / 2;
-+ case 2700:
-+ return 2700000000UL / 2;
-+ case 5400:
-+ return 5400000000UL / 4;
-+ case 8100:
-+ return 8100000000UL / 6;
-+ default:
-+ return 0;
-+ }
-+}
-+
-+static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = {
-+ .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate,
-+ .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate,
-+};
-+
-+static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw,
-+ struct clk_rate_request *req)
-+{
-+ switch (req->rate) {
-+ case 162000000:
-+ case 270000000:
-+ case 540000000:
-+ case 810000000:
-+ return 0;
-+ default:
-+ return -EINVAL;
-+ }
-+}
-+
-+static unsigned long
-+qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
-+{
-+ const struct qmp_phy_dp_clks *dp_clks;
-+ const struct qmp_phy *qphy;
-+ const struct phy_configure_opts_dp *dp_opts;
-+
-+ dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw);
-+ qphy = dp_clks->qphy;
-+ dp_opts = &qphy->dp_opts;
-+
-+ switch (dp_opts->link_rate) {
-+ case 1620:
-+ case 2700:
-+ case 5400:
-+ case 8100:
-+ return dp_opts->link_rate * 100000;
-+ default:
-+ return 0;
-+ }
-+}
-+
-+static const struct clk_ops qcom_qmp_dp_link_clk_ops = {
-+ .determine_rate = qcom_qmp_dp_link_clk_determine_rate,
-+ .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate,
-+};
-+
-+static struct clk_hw *
-+qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data)
-+{
-+ struct qmp_phy_dp_clks *dp_clks = data;
-+ unsigned int idx = clkspec->args[0];
-+
-+ if (idx >= 2) {
-+ pr_err("%s: invalid index %u\n", __func__, idx);
-+ return ERR_PTR(-EINVAL);
-+ }
-+
-+ if (idx == 0)
-+ return &dp_clks->dp_link_hw;
-+
-+ return &dp_clks->dp_pixel_hw;
-+}
-+
-+static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy,
-+ struct device_node *np)
-+{
-+ struct clk_init_data init = { };
-+ struct qmp_phy_dp_clks *dp_clks;
-+ char name[64];
-+ int ret;
-+
-+ dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL);
-+ if (!dp_clks)
-+ return -ENOMEM;
-+
-+ dp_clks->qphy = qphy;
-+ qphy->dp_clks = dp_clks;
-+
-+ snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev));
-+ init.ops = &qcom_qmp_dp_link_clk_ops;
-+ init.name = name;
-+ dp_clks->dp_link_hw.init = &init;
-+ ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw);
-+ if (ret)
-+ return ret;
-+
-+ snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev));
-+ init.ops = &qcom_qmp_dp_pixel_clk_ops;
-+ init.name = name;
-+ dp_clks->dp_pixel_hw.init = &init;
-+ ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw);
-+ if (ret)
-+ return ret;
-+
-+ ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks);
-+ if (ret)
-+ return ret;
-+
-+ /*
-+ * Roll a devm action because the clock provider is the child node, but
-+ * the child node is not actually a device.
-+ */
-+ return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
-+}
-+
-+static const struct phy_ops qcom_qmp_phy_gen_ops = {
-+ .init = qcom_qmp_phy_enable,
-+ .exit = qcom_qmp_phy_disable,
-+ .set_mode = qcom_qmp_phy_set_mode,
-+ .owner = THIS_MODULE,
-+};
-+
-+static const struct phy_ops qcom_qmp_phy_dp_ops = {
-+ .init = qcom_qmp_phy_init,
-+ .configure = qcom_qmp_dp_phy_configure,
-+ .power_on = qcom_qmp_phy_power_on,
-+ .calibrate = qcom_qmp_dp_phy_calibrate,
-+ .power_off = qcom_qmp_phy_power_off,
-+ .exit = qcom_qmp_phy_exit,
-+ .set_mode = qcom_qmp_phy_set_mode,
-+ .owner = THIS_MODULE,
-+};
-+
-+static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
-+ .power_on = qcom_qmp_phy_enable,
-+ .power_off = qcom_qmp_phy_disable,
-+ .set_mode = qcom_qmp_phy_set_mode,
-+ .owner = THIS_MODULE,
-+};
-+
-+static void qcom_qmp_reset_control_put(void *data)
-+{
-+ reset_control_put(data);
-+}
-+
-+static
-+int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
-+ void __iomem *serdes, const struct qmp_phy_cfg *cfg)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ struct phy *generic_phy;
-+ struct qmp_phy *qphy;
-+ const struct phy_ops *ops;
-+ char prop_name[MAX_PROP_NAME];
-+ int ret;
-+
-+ qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
-+ if (!qphy)
-+ return -ENOMEM;
-+
-+ qphy->cfg = cfg;
-+ qphy->serdes = serdes;
-+ /*
-+ * Get memory resources for each phy lane:
-+ * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
-+ * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
-+ * For single lane PHYs: pcs_misc (optional) -> 3.
-+ */
-+ qphy->tx = of_iomap(np, 0);
-+ if (!qphy->tx)
-+ return -ENOMEM;
-+
-+ qphy->rx = of_iomap(np, 1);
-+ if (!qphy->rx)
-+ return -ENOMEM;
-+
-+ qphy->pcs = of_iomap(np, 2);
-+ if (!qphy->pcs)
-+ return -ENOMEM;
-+
-+ /*
-+ * If this is a dual-lane PHY, then there should be registers for the
-+ * second lane. Some old device trees did not specify this, so fall
-+ * back to old legacy behavior of assuming they can be reached at an
-+ * offset from the first lane.
-+ */
-+ if (cfg->is_dual_lane_phy) {
-+ qphy->tx2 = of_iomap(np, 3);
-+ qphy->rx2 = of_iomap(np, 4);
-+ if (!qphy->tx2 || !qphy->rx2) {
-+ dev_warn(dev,
-+ "Underspecified device tree, falling back to legacy register regions\n");
-+
-+ /* In the old version, pcs_misc is at index 3. */
-+ qphy->pcs_misc = qphy->tx2;
-+ qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE;
-+ qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
-+
-+ } else {
-+ qphy->pcs_misc = of_iomap(np, 5);
-+ }
-+
-+ } else {
-+ qphy->pcs_misc = of_iomap(np, 3);
-+ }
-+
-+ if (!qphy->pcs_misc)
-+ dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
-+
-+ /*
-+ * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3
-+ * based phys, so they essentially have pipe clock. So,
-+ * we return error in case phy is USB3 or PIPE type.
-+ * Otherwise, we initialize pipe clock to NULL for
-+ * all phys that don't need this.
-+ */
-+ snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
-+ qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name);
-+ if (IS_ERR(qphy->pipe_clk)) {
-+ if (cfg->type == PHY_TYPE_PCIE ||
-+ cfg->type == PHY_TYPE_USB3) {
-+ ret = PTR_ERR(qphy->pipe_clk);
-+ if (ret != -EPROBE_DEFER)
-+ dev_err(dev,
-+ "failed to get lane%d pipe_clk, %d\n",
-+ id, ret);
-+ return ret;
-+ }
-+ qphy->pipe_clk = NULL;
-+ }
-+
-+ /* Get lane reset, if any */
-+ if (cfg->has_lane_rst) {
-+ snprintf(prop_name, sizeof(prop_name), "lane%d", id);
-+ qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name);
-+ if (IS_ERR(qphy->lane_rst)) {
-+ dev_err(dev, "failed to get lane%d reset\n", id);
-+ return PTR_ERR(qphy->lane_rst);
-+ }
-+ ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put,
-+ qphy->lane_rst);
-+ if (ret)
-+ return ret;
-+ }
-+
-+ if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE)
-+ ops = &qcom_qmp_pcie_ufs_ops;
-+ else if (cfg->type == PHY_TYPE_DP)
-+ ops = &qcom_qmp_phy_dp_ops;
-+ else
-+ ops = &qcom_qmp_phy_gen_ops;
-+
-+ generic_phy = devm_phy_create(dev, np, ops);
-+ if (IS_ERR(generic_phy)) {
-+ ret = PTR_ERR(generic_phy);
-+ dev_err(dev, "failed to create qphy %d\n", ret);
-+ return ret;
-+ }
-+
-+ qphy->phy = generic_phy;
-+ qphy->index = id;
-+ qphy->qmp = qmp;
-+ qmp->phys[id] = qphy;
-+ phy_set_drvdata(generic_phy, qphy);
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
-+ {
-+ .compatible = "qcom,ipq8074-qmp-usb3-phy",
-+ .data = &ipq8074_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,msm8996-qmp-pcie-phy",
-+ .data = &msm8996_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,msm8996-qmp-ufs-phy",
-+ .data = &msm8996_ufs_cfg,
-+ }, {
-+ .compatible = "qcom,msm8996-qmp-usb3-phy",
-+ .data = &msm8996_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,msm8998-qmp-pcie-phy",
-+ .data = &msm8998_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,msm8998-qmp-ufs-phy",
-+ .data = &sdm845_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,ipq8074-qmp-pcie-phy",
-+ .data = &ipq8074_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,ipq6018-qmp-pcie-phy",
-+ .data = &ipq6018_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,ipq6018-qmp-usb3-phy",
-+ .data = &ipq8074_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sc7180-qmp-usb3-phy",
-+ .data = &sc7180_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
-+ /* It's a combo phy */
-+ }, {
-+ .compatible = "qcom,sc8180x-qmp-pcie-phy",
-+ .data = &sc8180x_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sc8180x-qmp-ufs-phy",
-+ .data = &sm8150_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sc8280xp-qmp-ufs-phy",
-+ .data = &sm8350_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sc8180x-qmp-usb3-phy",
-+ .data = &sm8150_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
-+ /* It's a combo phy */
-+ }, {
-+ .compatible = "qcom,sdm845-qhp-pcie-phy",
-+ .data = &sdm845_qhp_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sdm845-qmp-pcie-phy",
-+ .data = &sdm845_qmp_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sdm845-qmp-usb3-phy",
-+ .data = &qmp_v3_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
-+ .data = &qmp_v3_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sdm845-qmp-ufs-phy",
-+ .data = &sdm845_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,msm8998-qmp-usb3-phy",
-+ .data = &msm8998_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sm6115-qmp-ufs-phy",
-+ .data = &sm6115_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm6350-qmp-ufs-phy",
-+ .data = &sdm845_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8150-qmp-ufs-phy",
-+ .data = &sm8150_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-ufs-phy",
-+ .data = &sm8150_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8150-qmp-usb3-phy",
-+ .data = &sm8150_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8150-qmp-usb3-uni-phy",
-+ .data = &sm8150_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-usb3-phy",
-+ .data = &sm8250_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
-+ /* It's a combo phy */
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-usb3-uni-phy",
-+ .data = &sm8250_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
-+ .data = &sm8250_qmp_gen3x1_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
-+ .data = &sm8250_qmp_gen3x2_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8350-qmp-ufs-phy",
-+ .data = &sm8350_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
-+ .data = &sm8250_qmp_gen3x2_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sdx55-qmp-pcie-phy",
-+ .data = &sdx55_qmp_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sdx55-qmp-usb3-uni-phy",
-+ .data = &sdx55_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sdx65-qmp-usb3-uni-phy",
-+ .data = &sdx65_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8350-qmp-usb3-phy",
-+ .data = &sm8350_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8350-qmp-usb3-uni-phy",
-+ .data = &sm8350_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
-+ .data = &sm8450_qmp_gen3x1_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
-+ .data = &sm8450_qmp_gen4x2_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8450-qmp-ufs-phy",
-+ .data = &sm8450_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8450-qmp-usb3-phy",
-+ .data = &sm8350_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,qcm2290-qmp-usb3-phy",
-+ .data = &qcm2290_usb3phy_cfg,
-+ },
-+ { },
-+};
-+MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
-+
-+static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = {
-+ {
-+ .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
-+ .data = &sc7180_usb3dpphy_cfg,
-+ },
-+ {
-+ .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
-+ .data = &sm8250_usb3dpphy_cfg,
-+ },
-+ {
-+ .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
-+ .data = &sc8180x_usb3dpphy_cfg,
-+ },
-+ { }
-+};
-+
-+static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
-+ SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
-+ qcom_qmp_phy_runtime_resume, NULL)
-+};
-+
-+static int qcom_qmp_phy_probe(struct platform_device *pdev)
-+{
-+ struct qcom_qmp *qmp;
-+ struct device *dev = &pdev->dev;
-+ struct device_node *child;
-+ struct phy_provider *phy_provider;
-+ void __iomem *serdes;
-+ void __iomem *usb_serdes;
-+ void __iomem *dp_serdes = NULL;
-+ const struct qmp_phy_combo_cfg *combo_cfg = NULL;
-+ const struct qmp_phy_cfg *cfg = NULL;
-+ const struct qmp_phy_cfg *usb_cfg = NULL;
-+ const struct qmp_phy_cfg *dp_cfg = NULL;
-+ int num, id, expected_phys;
-+ int ret;
-+
-+ qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
-+ if (!qmp)
-+ return -ENOMEM;
-+
-+ qmp->dev = dev;
-+ dev_set_drvdata(dev, qmp);
-+
-+ /* Get the specific init parameters of QMP phy */
-+ cfg = of_device_get_match_data(dev);
-+ if (!cfg) {
-+ const struct of_device_id *match;
-+
-+ match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev);
-+ if (!match)
-+ return -EINVAL;
-+
-+ combo_cfg = match->data;
-+ if (!combo_cfg)
-+ return -EINVAL;
-+
-+ usb_cfg = combo_cfg->usb_cfg;
-+ cfg = usb_cfg; /* Setup clks and regulators */
-+ }
-+
-+ /* per PHY serdes; usually located at base address */
-+ usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0);
-+ if (IS_ERR(serdes))
-+ return PTR_ERR(serdes);
-+
-+ /* per PHY dp_com; if PHY has dp_com control block */
-+ if (combo_cfg || cfg->has_phy_dp_com_ctrl) {
-+ qmp->dp_com = devm_platform_ioremap_resource(pdev, 1);
-+ if (IS_ERR(qmp->dp_com))
-+ return PTR_ERR(qmp->dp_com);
-+ }
-+
-+ if (combo_cfg) {
-+ /* Only two serdes for combo PHY */
-+ dp_serdes = devm_platform_ioremap_resource(pdev, 2);
-+ if (IS_ERR(dp_serdes))
-+ return PTR_ERR(dp_serdes);
-+
-+ dp_cfg = combo_cfg->dp_cfg;
-+ expected_phys = 2;
-+ } else {
-+ expected_phys = cfg->nlanes;
-+ }
-+
-+ mutex_init(&qmp->phy_mutex);
-+
-+ ret = qcom_qmp_phy_clk_init(dev, cfg);
-+ if (ret)
-+ return ret;
-+
-+ ret = qcom_qmp_phy_reset_init(dev, cfg);
-+ if (ret)
-+ return ret;
-+
-+ ret = qcom_qmp_phy_vreg_init(dev, cfg);
-+ if (ret) {
-+ if (ret != -EPROBE_DEFER)
-+ dev_err(dev, "failed to get regulator supplies: %d\n",
-+ ret);
-+ return ret;
-+ }
-+
-+ num = of_get_available_child_count(dev->of_node);
-+ /* do we have a rogue child node ? */
-+ if (num > expected_phys)
-+ return -EINVAL;
-+
-+ qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
-+ if (!qmp->phys)
-+ return -ENOMEM;
-+
-+ pm_runtime_set_active(dev);
-+ pm_runtime_enable(dev);
-+ /*
-+ * Prevent runtime pm from being ON by default. Users can enable
-+ * it using power/control in sysfs.
-+ */
-+ pm_runtime_forbid(dev);
-+
-+ id = 0;
-+ for_each_available_child_of_node(dev->of_node, child) {
-+ if (of_node_name_eq(child, "dp-phy")) {
-+ cfg = dp_cfg;
-+ serdes = dp_serdes;
-+ } else if (of_node_name_eq(child, "usb3-phy")) {
-+ cfg = usb_cfg;
-+ serdes = usb_serdes;
-+ }
-+
-+ /* Create per-lane phy */
-+ ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg);
-+ if (ret) {
-+ dev_err(dev, "failed to create lane%d phy, %d\n",
-+ id, ret);
-+ goto err_node_put;
-+ }
-+
-+ /*
-+ * Register the pipe clock provided by phy.
-+ * See function description to see details of this pipe clock.
-+ */
-+ if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) {
-+ ret = phy_pipe_clk_register(qmp, child);
-+ if (ret) {
-+ dev_err(qmp->dev,
-+ "failed to register pipe clock source\n");
-+ goto err_node_put;
-+ }
-+ } else if (cfg->type == PHY_TYPE_DP) {
-+ ret = phy_dp_clks_register(qmp, qmp->phys[id], child);
-+ if (ret) {
-+ dev_err(qmp->dev,
-+ "failed to register DP clock source\n");
-+ goto err_node_put;
-+ }
-+ }
-+ id++;
-+ }
-+
-+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
-+ if (!IS_ERR(phy_provider))
-+ dev_info(dev, "Registered Qcom-QMP phy\n");
-+ else
-+ pm_runtime_disable(dev);
-+
-+ return PTR_ERR_OR_ZERO(phy_provider);
-+
-+err_node_put:
-+ pm_runtime_disable(dev);
-+ of_node_put(child);
-+ return ret;
-+}
-+
-+static struct platform_driver qcom_qmp_phy_driver = {
-+ .probe = qcom_qmp_phy_probe,
-+ .driver = {
-+ .name = "qcom-qmp-phy",
-+ .pm = &qcom_qmp_phy_pm_ops,
-+ .of_match_table = qcom_qmp_phy_of_match_table,
-+ },
-+};
-+
-+module_platform_driver(qcom_qmp_phy_driver);
-+
-+MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
-+MODULE_DESCRIPTION("Qualcomm QMP PHY driver");
-+MODULE_LICENSE("GPL v2");
-diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
-new file mode 100644
-index 000000000000..c7309e981bfb
---- /dev/null
-+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
-@@ -0,0 +1,6350 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/clk-provider.h>
-+#include <linux/delay.h>
-+#include <linux/err.h>
-+#include <linux/io.h>
-+#include <linux/iopoll.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/of_device.h>
-+#include <linux/of_address.h>
-+#include <linux/phy/phy.h>
-+#include <linux/platform_device.h>
-+#include <linux/regulator/consumer.h>
-+#include <linux/reset.h>
-+#include <linux/slab.h>
-+
-+#include <dt-bindings/phy/phy.h>
-+
-+#include "phy-qcom-qmp.h"
-+
-+/* QPHY_SW_RESET bit */
-+#define SW_RESET BIT(0)
-+/* QPHY_POWER_DOWN_CONTROL */
-+#define SW_PWRDN BIT(0)
-+#define REFCLK_DRV_DSBL BIT(1)
-+/* QPHY_START_CONTROL bits */
-+#define SERDES_START BIT(0)
-+#define PCS_START BIT(1)
-+#define PLL_READY_GATE_EN BIT(3)
-+/* QPHY_PCS_STATUS bit */
-+#define PHYSTATUS BIT(6)
-+#define PHYSTATUS_4_20 BIT(7)
-+/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */
-+#define PCS_READY BIT(0)
-+
-+/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
-+/* DP PHY soft reset */
-+#define SW_DPPHY_RESET BIT(0)
-+/* mux to select DP PHY reset control, 0:HW control, 1: software reset */
-+#define SW_DPPHY_RESET_MUX BIT(1)
-+/* USB3 PHY soft reset */
-+#define SW_USB3PHY_RESET BIT(2)
-+/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
-+#define SW_USB3PHY_RESET_MUX BIT(3)
-+
-+/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
-+#define USB3_MODE BIT(0) /* enables USB3 mode */
-+#define DP_MODE BIT(1) /* enables DP mode */
-+
-+/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
-+#define ARCVR_DTCT_EN BIT(0)
-+#define ALFPS_DTCT_EN BIT(1)
-+#define ARCVR_DTCT_EVENT_SEL BIT(4)
-+
-+/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
-+#define IRQ_CLEAR BIT(0)
-+
-+/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
-+#define RCVR_DETECT BIT(0)
-+
-+/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
-+#define CLAMP_EN BIT(0) /* enables i/o clamp_n */
-+
-+#define PHY_INIT_COMPLETE_TIMEOUT 10000
-+#define POWER_DOWN_DELAY_US_MIN 10
-+#define POWER_DOWN_DELAY_US_MAX 11
-+
-+#define MAX_PROP_NAME 32
-+
-+/* Define the assumed distance between lanes for underspecified device trees. */
-+#define QMP_PHY_LEGACY_LANE_STRIDE 0x400
-+
-+struct qmp_phy_init_tbl {
-+ unsigned int offset;
-+ unsigned int val;
-+ /*
-+ * register part of layout ?
-+ * if yes, then offset gives index in the reg-layout
-+ */
-+ bool in_layout;
-+ /*
-+ * mask of lanes for which this register is written
-+ * for cases when second lane needs different values
-+ */
-+ u8 lane_mask;
-+};
-+
-+#define QMP_PHY_INIT_CFG(o, v) \
-+ { \
-+ .offset = o, \
-+ .val = v, \
-+ .lane_mask = 0xff, \
-+ }
-+
-+#define QMP_PHY_INIT_CFG_L(o, v) \
-+ { \
-+ .offset = o, \
-+ .val = v, \
-+ .in_layout = true, \
-+ .lane_mask = 0xff, \
-+ }
-+
-+#define QMP_PHY_INIT_CFG_LANE(o, v, l) \
-+ { \
-+ .offset = o, \
-+ .val = v, \
-+ .lane_mask = l, \
-+ }
-+
-+/* set of registers with offsets different per-PHY */
-+enum qphy_reg_layout {
-+ /* Common block control registers */
-+ QPHY_COM_SW_RESET,
-+ QPHY_COM_POWER_DOWN_CONTROL,
-+ QPHY_COM_START_CONTROL,
-+ QPHY_COM_PCS_READY_STATUS,
-+ /* PCS registers */
-+ QPHY_PLL_LOCK_CHK_DLY_TIME,
-+ QPHY_FLL_CNTRL1,
-+ QPHY_FLL_CNTRL2,
-+ QPHY_FLL_CNT_VAL_L,
-+ QPHY_FLL_CNT_VAL_H_TOL,
-+ QPHY_FLL_MAN_CODE,
-+ QPHY_SW_RESET,
-+ QPHY_START_CTRL,
-+ QPHY_PCS_READY_STATUS,
-+ QPHY_PCS_STATUS,
-+ QPHY_PCS_AUTONOMOUS_MODE_CTRL,
-+ QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
-+ QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
-+ QPHY_PCS_POWER_DOWN_CONTROL,
-+ /* PCS_MISC registers */
-+ QPHY_PCS_MISC_TYPEC_CTRL,
-+ /* Keep last to ensure regs_layout arrays are properly initialized */
-+ QPHY_LAYOUT_SIZE
-+};
-+
-+static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_START_CTRL] = 0x00,
-+ [QPHY_PCS_READY_STATUS] = 0x168,
-+};
-+
-+static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x44,
-+ [QPHY_PCS_STATUS] = 0x14,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
-+};
-+
-+static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_COM_SW_RESET] = 0x400,
-+ [QPHY_COM_POWER_DOWN_CONTROL] = 0x404,
-+ [QPHY_COM_START_CONTROL] = 0x408,
-+ [QPHY_COM_PCS_READY_STATUS] = 0x448,
-+ [QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8,
-+ [QPHY_FLL_CNTRL1] = 0xc4,
-+ [QPHY_FLL_CNTRL2] = 0xc8,
-+ [QPHY_FLL_CNT_VAL_L] = 0xcc,
-+ [QPHY_FLL_CNT_VAL_H_TOL] = 0xd0,
-+ [QPHY_FLL_MAN_CODE] = 0xd4,
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_STATUS] = 0x174,
-+};
-+
-+static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_FLL_CNTRL1] = 0xc0,
-+ [QPHY_FLL_CNTRL2] = 0xc4,
-+ [QPHY_FLL_CNT_VAL_L] = 0xc8,
-+ [QPHY_FLL_CNT_VAL_H_TOL] = 0xcc,
-+ [QPHY_FLL_MAN_CODE] = 0xd0,
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_STATUS] = 0x17c,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
-+};
-+
-+static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_STATUS] = 0x174,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
-+};
-+
-+static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_STATUS] = 0x174,
-+};
-+
-+static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_STATUS] = 0x2ac,
-+};
-+
-+static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x44,
-+ [QPHY_PCS_STATUS] = 0x14,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314,
-+};
-+
-+static const unsigned int qmp_v4_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x44,
-+ [QPHY_PCS_STATUS] = 0x14,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x608,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x614,
-+};
-+
-+static const unsigned int sm8350_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x44,
-+ [QPHY_PCS_STATUS] = 0x14,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x1008,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x1014,
-+};
-+
-+static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0xd8,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc,
-+ [QPHY_PCS_STATUS] = 0x174,
-+ [QPHY_PCS_MISC_TYPEC_CTRL] = 0x00,
-+};
-+
-+static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_START_CTRL] = 0x00,
-+ [QPHY_PCS_READY_STATUS] = 0x160,
-+};
-+
-+static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_START_CTRL] = 0x00,
-+ [QPHY_PCS_READY_STATUS] = 0x168,
-+};
-+
-+static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x44,
-+ [QPHY_PCS_STATUS] = 0x14,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
-+};
-+
-+static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START,
-+ [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS,
-+ [QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET,
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
-+ /* PLL and Loop filter settings */
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-+ /* SSC settings */
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
-+ QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
-+
-+ QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
-+
-+ QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
-+ QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
-+ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
-+ /* PLL and Loop filter settings */
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-+ /* SSC settings */
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
-+ /* FLL settings */
-+ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03),
-+ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02),
-+ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42),
-+ QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
-+
-+ /* Lock Det settings */
-+ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x61),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d),
-+ QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10),
-+ QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_PRE, 0x00),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_POST, 0x58),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
-+ QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
-+ QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
-+ QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
-+ QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
-+ QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
-+ QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
-+ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
-+ QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
-+ QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = {
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
-+ /* FLL settings */
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+
-+ /* Lock Det settings */
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
-+ /* FLL settings */
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+
-+ /* Lock Det settings */
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
-+};
-+
-+static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
-+
-+ /* Rate B */
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),
-+};
-+
-+static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B),
-+};
-+
-+static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_RX_PWM_GEAR_BAND, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_CTRL2, 0x6d),
-+ QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_DRV_LVL, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_DRV_LVL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
-+ QMP_PHY_INIT_CFG(QPHY_RX_SYM_RESYNC_CTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
-+ QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
-+
-+ /* Rate B */
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
-+
-+ /* Rate B */
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
-+
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
-+ /* Lock Det settings */
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20),
-+};
-+
-+static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
-+};
-+
-+static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5),
-+};
-+
-+static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
-+};
-+
-+static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),
-+};
-+
-+static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
-+
-+ /* Rate B */
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+};
-+
-+static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01),
-+};
-+
-+static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
-+
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05),
-+
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
-+
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
-+
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
-+};
-+
-+/* Register names should be validated, they might be different for this PHY */
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
-+};
-+
-+struct qmp_phy;
-+
-+/* struct qmp_phy_cfg - per-PHY initialization config */
-+struct qmp_phy_cfg {
-+ /* phy-type - PCIE/UFS/USB */
-+ unsigned int type;
-+ /* number of lanes provided by phy */
-+ int nlanes;
-+
-+ /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
-+ const struct qmp_phy_init_tbl *serdes_tbl;
-+ int serdes_tbl_num;
-+ const struct qmp_phy_init_tbl *serdes_tbl_sec;
-+ int serdes_tbl_num_sec;
-+ const struct qmp_phy_init_tbl *tx_tbl;
-+ int tx_tbl_num;
-+ const struct qmp_phy_init_tbl *tx_tbl_sec;
-+ int tx_tbl_num_sec;
-+ const struct qmp_phy_init_tbl *rx_tbl;
-+ int rx_tbl_num;
-+ const struct qmp_phy_init_tbl *rx_tbl_sec;
-+ int rx_tbl_num_sec;
-+ const struct qmp_phy_init_tbl *pcs_tbl;
-+ int pcs_tbl_num;
-+ const struct qmp_phy_init_tbl *pcs_tbl_sec;
-+ int pcs_tbl_num_sec;
-+ const struct qmp_phy_init_tbl *pcs_misc_tbl;
-+ int pcs_misc_tbl_num;
-+ const struct qmp_phy_init_tbl *pcs_misc_tbl_sec;
-+ int pcs_misc_tbl_num_sec;
-+
-+ /* Init sequence for DP PHY block link rates */
-+ const struct qmp_phy_init_tbl *serdes_tbl_rbr;
-+ int serdes_tbl_rbr_num;
-+ const struct qmp_phy_init_tbl *serdes_tbl_hbr;
-+ int serdes_tbl_hbr_num;
-+ const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
-+ int serdes_tbl_hbr2_num;
-+ const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
-+ int serdes_tbl_hbr3_num;
-+
-+ /* DP PHY callbacks */
-+ int (*configure_dp_phy)(struct qmp_phy *qphy);
-+ void (*configure_dp_tx)(struct qmp_phy *qphy);
-+ int (*calibrate_dp_phy)(struct qmp_phy *qphy);
-+ void (*dp_aux_init)(struct qmp_phy *qphy);
-+
-+ /* clock ids to be requested */
-+ const char * const *clk_list;
-+ int num_clks;
-+ /* resets to be requested */
-+ const char * const *reset_list;
-+ int num_resets;
-+ /* regulators to be requested */
-+ const char * const *vreg_list;
-+ int num_vregs;
-+
-+ /* array of registers with different offsets */
-+ const unsigned int *regs;
-+
-+ unsigned int start_ctrl;
-+ unsigned int pwrdn_ctrl;
-+ unsigned int mask_com_pcs_ready;
-+ /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
-+ unsigned int phy_status;
-+
-+ /* true, if PHY has a separate PHY_COM control block */
-+ bool has_phy_com_ctrl;
-+ /* true, if PHY has a reset for individual lanes */
-+ bool has_lane_rst;
-+ /* true, if PHY needs delay after POWER_DOWN */
-+ bool has_pwrdn_delay;
-+ /* power_down delay in usec */
-+ int pwrdn_delay_min;
-+ int pwrdn_delay_max;
-+
-+ /* true, if PHY has a separate DP_COM control block */
-+ bool has_phy_dp_com_ctrl;
-+ /* true, if PHY has secondary tx/rx lanes to be configured */
-+ bool is_dual_lane_phy;
-+
-+ /* true, if PCS block has no separate SW_RESET register */
-+ bool no_pcs_sw_reset;
-+};
-+
-+struct qmp_phy_combo_cfg {
-+ const struct qmp_phy_cfg *usb_cfg;
-+ const struct qmp_phy_cfg *dp_cfg;
-+};
-+
-+/**
-+ * struct qmp_phy - per-lane phy descriptor
-+ *
-+ * @phy: generic phy
-+ * @cfg: phy specific configuration
-+ * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
-+ * @tx: iomapped memory space for lane's tx
-+ * @rx: iomapped memory space for lane's rx
-+ * @pcs: iomapped memory space for lane's pcs
-+ * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
-+ * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
-+ * @pcs_misc: iomapped memory space for lane's pcs_misc
-+ * @pipe_clk: pipe clock
-+ * @index: lane index
-+ * @qmp: QMP phy to which this lane belongs
-+ * @lane_rst: lane's reset controller
-+ * @mode: current PHY mode
-+ * @dp_aux_cfg: Display port aux config
-+ * @dp_opts: Display port optional config
-+ * @dp_clks: Display port clocks
-+ */
-+struct qmp_phy {
-+ struct phy *phy;
-+ const struct qmp_phy_cfg *cfg;
-+ void __iomem *serdes;
-+ void __iomem *tx;
-+ void __iomem *rx;
-+ void __iomem *pcs;
-+ void __iomem *tx2;
-+ void __iomem *rx2;
-+ void __iomem *pcs_misc;
-+ struct clk *pipe_clk;
-+ unsigned int index;
-+ struct qcom_qmp *qmp;
-+ struct reset_control *lane_rst;
-+ enum phy_mode mode;
-+ unsigned int dp_aux_cfg;
-+ struct phy_configure_opts_dp dp_opts;
-+ struct qmp_phy_dp_clks *dp_clks;
-+};
-+
-+struct qmp_phy_dp_clks {
-+ struct qmp_phy *qphy;
-+ struct clk_hw dp_link_hw;
-+ struct clk_hw dp_pixel_hw;
-+};
-+
-+/**
-+ * struct qcom_qmp - structure holding QMP phy block attributes
-+ *
-+ * @dev: device
-+ * @dp_com: iomapped memory space for phy's dp_com control block
-+ *
-+ * @clks: array of clocks required by phy
-+ * @resets: array of resets required by phy
-+ * @vregs: regulator supplies bulk data
-+ *
-+ * @phys: array of per-lane phy descriptors
-+ * @phy_mutex: mutex lock for PHY common block initialization
-+ * @init_count: phy common block initialization count
-+ * @ufs_reset: optional UFS PHY reset handle
-+ */
-+struct qcom_qmp {
-+ struct device *dev;
-+ void __iomem *dp_com;
-+
-+ struct clk_bulk_data *clks;
-+ struct reset_control **resets;
-+ struct regulator_bulk_data *vregs;
-+
-+ struct qmp_phy **phys;
-+
-+ struct mutex phy_mutex;
-+ int init_count;
-+
-+ struct reset_control *ufs_reset;
-+};
-+
-+static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy);
-+static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy);
-+static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy);
-+static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy);
-+
-+static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy);
-+static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy);
-+static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy);
-+static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy);
-+
-+static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
-+{
-+ u32 reg;
-+
-+ reg = readl(base + offset);
-+ reg |= val;
-+ writel(reg, base + offset);
-+
-+ /* ensure that above write is through */
-+ readl(base + offset);
-+}
-+
-+static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
-+{
-+ u32 reg;
-+
-+ reg = readl(base + offset);
-+ reg &= ~val;
-+ writel(reg, base + offset);
-+
-+ /* ensure that above write is through */
-+ readl(base + offset);
-+}
-+
-+/* list of clocks required by phy */
-+static const char * const msm8996_phy_clk_l[] = {
-+ "aux", "cfg_ahb", "ref",
-+};
-+
-+static const char * const msm8996_ufs_phy_clk_l[] = {
-+ "ref",
-+};
-+
-+static const char * const qmp_v3_phy_clk_l[] = {
-+ "aux", "cfg_ahb", "ref", "com_aux",
-+};
-+
-+static const char * const sdm845_pciephy_clk_l[] = {
-+ "aux", "cfg_ahb", "ref", "refgen",
-+};
-+
-+static const char * const qmp_v4_phy_clk_l[] = {
-+ "aux", "ref_clk_src", "ref", "com_aux",
-+};
-+
-+/* the primary usb3 phy on sm8250 doesn't have a ref clock */
-+static const char * const qmp_v4_sm8250_usbphy_clk_l[] = {
-+ "aux", "ref_clk_src", "com_aux"
-+};
-+
-+static const char * const sm8450_ufs_phy_clk_l[] = {
-+ "qref", "ref", "ref_aux",
-+};
-+
-+static const char * const sdm845_ufs_phy_clk_l[] = {
-+ "ref", "ref_aux",
-+};
-+
-+/* usb3 phy on sdx55 doesn't have com_aux clock */
-+static const char * const qmp_v4_sdx55_usbphy_clk_l[] = {
-+ "aux", "cfg_ahb", "ref"
-+};
-+
-+static const char * const qcm2290_usb3phy_clk_l[] = {
-+ "cfg_ahb", "ref", "com_aux",
-+};
-+
-+/* list of resets */
-+static const char * const msm8996_pciephy_reset_l[] = {
-+ "phy", "common", "cfg",
-+};
-+
-+static const char * const msm8996_usb3phy_reset_l[] = {
-+ "phy", "common",
-+};
-+
-+static const char * const sc7180_usb3phy_reset_l[] = {
-+ "phy",
-+};
-+
-+static const char * const qcm2290_usb3phy_reset_l[] = {
-+ "phy_phy", "phy",
-+};
-+
-+static const char * const sdm845_pciephy_reset_l[] = {
-+ "phy",
-+};
-+
-+/* list of regulators */
-+static const char * const qmp_phy_vreg_l[] = {
-+ "vdda-phy", "vdda-pll",
-+};
-+
-+static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = ipq8074_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
-+ .tx_tbl = msm8996_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
-+ .rx_tbl = ipq8074_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
-+ .pcs_tbl = ipq8074_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
-+ .clk_list = msm8996_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+};
-+
-+static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 3,
-+
-+ .serdes_tbl = msm8996_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
-+ .tx_tbl = msm8996_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8996_pcie_tx_tbl),
-+ .rx_tbl = msm8996_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(msm8996_pcie_rx_tbl),
-+ .pcs_tbl = msm8996_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
-+ .clk_list = msm8996_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-+ .reset_list = msm8996_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = pciephy_regs_layout,
-+
-+ .start_ctrl = PCS_START | PLL_READY_GATE_EN,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .mask_com_pcs_ready = PCS_READY,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_phy_com_ctrl = true,
-+ .has_lane_rst = true,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg msm8996_ufs_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = msm8996_ufs_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(msm8996_ufs_serdes_tbl),
-+ .tx_tbl = msm8996_ufs_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8996_ufs_tx_tbl),
-+ .rx_tbl = msm8996_ufs_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(msm8996_ufs_rx_tbl),
-+
-+ .clk_list = msm8996_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
-+
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+
-+ .regs = msm8996_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .no_pcs_sw_reset = true,
-+};
-+
-+static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = msm8996_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
-+ .tx_tbl = msm8996_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
-+ .rx_tbl = msm8996_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl),
-+ .pcs_tbl = msm8996_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
-+ .clk_list = msm8996_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+};
-+
-+static const char * const ipq8074_pciephy_clk_l[] = {
-+ "aux", "cfg_ahb",
-+};
-+/* list of resets */
-+static const char * const ipq8074_pciephy_reset_l[] = {
-+ "phy", "common",
-+};
-+
-+static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = ipq8074_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
-+ .tx_tbl = ipq8074_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
-+ .rx_tbl = ipq8074_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
-+ .pcs_tbl = ipq8074_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
-+ .clk_list = ipq8074_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
-+ .reset_list = ipq8074_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
-+ .vreg_list = NULL,
-+ .num_vregs = 0,
-+ .regs = pciephy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_phy_com_ctrl = false,
-+ .has_lane_rst = false,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = ipq6018_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl),
-+ .tx_tbl = ipq6018_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl),
-+ .rx_tbl = ipq6018_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
-+ .pcs_tbl = ipq6018_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
-+ .clk_list = ipq8074_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
-+ .reset_list = ipq8074_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
-+ .vreg_list = NULL,
-+ .num_vregs = 0,
-+ .regs = ipq_pciephy_gen3_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+
-+ .has_phy_com_ctrl = false,
-+ .has_lane_rst = false,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sdm845_qmp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
-+ .tx_tbl = sdm845_qmp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),
-+ .rx_tbl = sdm845_qmp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),
-+ .pcs_tbl = sdm845_qmp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sdm845_qmp_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sdm845_qmp_pciephy_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sdm845_qhp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
-+ .tx_tbl = sdm845_qhp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
-+ .rx_tbl = sdm845_qhp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl),
-+ .pcs_tbl = sdm845_qhp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sdm845_qhp_pciephy_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
-+ .serdes_tbl_sec = sm8250_qmp_gen3x1_pcie_serdes_tbl,
-+ .serdes_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
-+ .tx_tbl = sm8250_qmp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
-+ .rx_tbl = sm8250_qmp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
-+ .rx_tbl_sec = sm8250_qmp_gen3x1_pcie_rx_tbl,
-+ .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),
-+ .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
-+ .pcs_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_tbl,
-+ .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
-+ .pcs_misc_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
-+ .tx_tbl = sm8250_qmp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
-+ .tx_tbl_sec = sm8250_qmp_gen3x2_pcie_tx_tbl,
-+ .tx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),
-+ .rx_tbl = sm8250_qmp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
-+ .rx_tbl_sec = sm8250_qmp_gen3x2_pcie_rx_tbl,
-+ .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl),
-+ .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
-+ .pcs_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_tbl,
-+ .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
-+ .pcs_misc_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v3_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
-+ .tx_tbl = qmp_v3_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
-+ .rx_tbl = qmp_v3_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
-+ .pcs_tbl = qmp_v3_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
-+ .clk_list = qmp_v3_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v3_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
-+ .tx_tbl = qmp_v3_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
-+ .rx_tbl = qmp_v3_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
-+ .pcs_tbl = qmp_v3_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
-+ .clk_list = qmp_v3_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-+ .reset_list = sc7180_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sc7180_dpphy_cfg = {
-+ .type = PHY_TYPE_DP,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v3_dp_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
-+ .tx_tbl = qmp_v3_dp_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
-+
-+ .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr,
-+ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
-+ .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr,
-+ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
-+ .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2,
-+ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
-+ .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3,
-+ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
-+
-+ .clk_list = qmp_v3_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-+ .reset_list = sc7180_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+
-+ .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init,
-+ .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx,
-+ .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy,
-+ .calibrate_dp_phy = qcom_qmp_v3_dp_phy_calibrate,
-+};
-+
-+static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = {
-+ .usb_cfg = &sc7180_usb3phy_cfg,
-+ .dp_cfg = &sc7180_dpphy_cfg,
-+};
-+
-+static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
-+ .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v3_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sdm845_ufsphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
-+ .tx_tbl = sdm845_ufsphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
-+ .rx_tbl = sdm845_ufsphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
-+ .pcs_tbl = sdm845_ufsphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
-+ .clk_list = sdm845_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sdm845_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+ .no_pcs_sw_reset = true,
-+};
-+
-+static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm6115_ufsphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl),
-+ .tx_tbl = sm6115_ufsphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_tx_tbl),
-+ .rx_tbl = sm6115_ufsphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_rx_tbl),
-+ .pcs_tbl = sm6115_ufsphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl),
-+ .clk_list = sdm845_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm6115_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+
-+ .is_dual_lane_phy = false,
-+ .no_pcs_sw_reset = true,
-+};
-+
-+static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = msm8998_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
-+ .tx_tbl = msm8998_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8998_pcie_tx_tbl),
-+ .rx_tbl = msm8998_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(msm8998_pcie_rx_tbl),
-+ .pcs_tbl = msm8998_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
-+ .clk_list = msm8996_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-+ .reset_list = ipq8074_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = pciephy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+};
-+
-+static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = msm8998_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
-+ .tx_tbl = msm8998_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl),
-+ .rx_tbl = msm8998_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl),
-+ .pcs_tbl = msm8998_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
-+ .clk_list = msm8996_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sm8150_ufsphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl),
-+ .tx_tbl = sm8150_ufsphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx_tbl),
-+ .rx_tbl = sm8150_ufsphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx_tbl),
-+ .pcs_tbl = sm8150_ufsphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl),
-+ .clk_list = sdm845_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8150_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
-+ .tx_tbl = sm8150_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl),
-+ .rx_tbl = sm8150_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl),
-+ .pcs_tbl = sm8150_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
-+ .clk_list = qmp_v4_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sc8180x_qmp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl),
-+ .tx_tbl = sc8180x_qmp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl),
-+ .rx_tbl = sc8180x_qmp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl),
-+ .pcs_tbl = sc8180x_qmp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sc8180x_qmp_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sc8180x_dpphy_cfg = {
-+ .type = PHY_TYPE_DP,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v4_dp_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
-+ .tx_tbl = qmp_v4_dp_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
-+
-+ .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
-+ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
-+ .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
-+ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
-+ .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
-+ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
-+ .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
-+ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
-+
-+ .clk_list = qmp_v3_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-+ .reset_list = sc7180_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+
-+ .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
-+ .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
-+ .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
-+ .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
-+};
-+
-+static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = {
-+ .usb_cfg = &sm8150_usb3phy_cfg,
-+ .dp_cfg = &sc8180x_dpphy_cfg,
-+};
-+
-+static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = sm8150_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),
-+ .rx_tbl = sm8150_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = sm8150_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v4_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3_uniphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
-+ .tx_tbl = sm8250_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl),
-+ .rx_tbl = sm8250_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl),
-+ .pcs_tbl = sm8250_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
-+ .clk_list = qmp_v4_sm8250_usbphy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = sm8250_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),
-+ .rx_tbl = sm8250_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v4_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3_uniphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sm8250_dpphy_cfg = {
-+ .type = PHY_TYPE_DP,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v4_dp_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
-+ .tx_tbl = qmp_v4_dp_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
-+
-+ .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
-+ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
-+ .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
-+ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
-+ .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
-+ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
-+ .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
-+ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
-+
-+ .clk_list = qmp_v4_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3phy_regs_layout,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+
-+ .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
-+ .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
-+ .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
-+ .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
-+};
-+
-+static const struct qmp_phy_combo_cfg sm8250_usb3dpphy_cfg = {
-+ .usb_cfg = &sm8250_usb3phy_cfg,
-+ .dp_cfg = &sm8250_dpphy_cfg,
-+};
-+
-+static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = sdx55_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl),
-+ .rx_tbl = sdx55_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v4_sdx55_usbphy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3_uniphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sdx55_qmp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl),
-+ .tx_tbl = sdx55_qmp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl),
-+ .rx_tbl = sdx55_qmp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl),
-+ .pcs_tbl = sdx55_qmp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sdx55_qmp_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS_4_20,
-+
-+ .is_dual_lane_phy = true,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = sdx65_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl),
-+ .rx_tbl = sdx65_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v4_sdx55_usbphy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8350_usb3_uniphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sm8350_ufsphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
-+ .tx_tbl = sm8350_ufsphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
-+ .rx_tbl = sm8350_ufsphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
-+ .pcs_tbl = sm8350_ufsphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
-+ .clk_list = sdm845_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8150_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
-+ .tx_tbl = sm8350_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl),
-+ .rx_tbl = sm8350_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl),
-+ .pcs_tbl = sm8350_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl),
-+ .clk_list = qmp_v4_sm8250_usbphy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = sm8350_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),
-+ .rx_tbl = sm8350_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v4_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8350_usb3_uniphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sm8350_ufsphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
-+ .tx_tbl = sm8350_ufsphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
-+ .rx_tbl = sm8350_ufsphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
-+ .pcs_tbl = sm8350_ufsphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
-+ .clk_list = sm8450_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8150_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8450_qmp_gen3x1_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl),
-+ .tx_tbl = sm8450_qmp_gen3x1_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl),
-+ .rx_tbl = sm8450_qmp_gen3x1_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl),
-+ .pcs_tbl = sm8450_qmp_gen3x1_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sm8450_qmp_gen4x2_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl),
-+ .tx_tbl = sm8450_qmp_gen4x2_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl),
-+ .rx_tbl = sm8450_qmp_gen4x2_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl),
-+ .pcs_tbl = sm8450_qmp_gen4x2_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS_4_20,
-+
-+ .is_dual_lane_phy = true,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qcm2290_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl),
-+ .tx_tbl = qcm2290_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl),
-+ .rx_tbl = qcm2290_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(qcm2290_usb3_rx_tbl),
-+ .pcs_tbl = qcm2290_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl),
-+ .clk_list = qcm2290_usb3phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qcm2290_usb3phy_clk_l),
-+ .reset_list = qcm2290_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qcm2290_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+};
-+
-+static void qcom_qmp_phy_configure_lane(void __iomem *base,
-+ const unsigned int *regs,
-+ const struct qmp_phy_init_tbl tbl[],
-+ int num,
-+ u8 lane_mask)
-+{
-+ int i;
-+ const struct qmp_phy_init_tbl *t = tbl;
-+
-+ if (!t)
-+ return;
-+
-+ for (i = 0; i < num; i++, t++) {
-+ if (!(t->lane_mask & lane_mask))
-+ continue;
-+
-+ if (t->in_layout)
-+ writel(t->val, base + regs[t->offset]);
-+ else
-+ writel(t->val, base + t->offset);
-+ }
-+}
-+
-+static void qcom_qmp_phy_configure(void __iomem *base,
-+ const unsigned int *regs,
-+ const struct qmp_phy_init_tbl tbl[],
-+ int num)
-+{
-+ qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff);
-+}
-+
-+static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
-+{
-+ struct qcom_qmp *qmp = qphy->qmp;
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *serdes = qphy->serdes;
-+ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-+ const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
-+ int serdes_tbl_num = cfg->serdes_tbl_num;
-+ int ret;
-+
-+ qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
-+ if (cfg->serdes_tbl_sec)
-+ qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
-+ cfg->serdes_tbl_num_sec);
-+
-+ if (cfg->type == PHY_TYPE_DP) {
-+ switch (dp_opts->link_rate) {
-+ case 1620:
-+ qcom_qmp_phy_configure(serdes, cfg->regs,
-+ cfg->serdes_tbl_rbr,
-+ cfg->serdes_tbl_rbr_num);
-+ break;
-+ case 2700:
-+ qcom_qmp_phy_configure(serdes, cfg->regs,
-+ cfg->serdes_tbl_hbr,
-+ cfg->serdes_tbl_hbr_num);
-+ break;
-+ case 5400:
-+ qcom_qmp_phy_configure(serdes, cfg->regs,
-+ cfg->serdes_tbl_hbr2,
-+ cfg->serdes_tbl_hbr2_num);
-+ break;
-+ case 8100:
-+ qcom_qmp_phy_configure(serdes, cfg->regs,
-+ cfg->serdes_tbl_hbr3,
-+ cfg->serdes_tbl_hbr3_num);
-+ break;
-+ default:
-+ /* Other link rates aren't supported */
-+ return -EINVAL;
-+ }
-+ }
-+
-+
-+ if (cfg->has_phy_com_ctrl) {
-+ void __iomem *status;
-+ unsigned int mask, val;
-+
-+ qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
-+ qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
-+ SERDES_START | PCS_START);
-+
-+ status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
-+ mask = cfg->mask_com_pcs_ready;
-+
-+ ret = readl_poll_timeout(status, val, (val & mask), 10,
-+ PHY_INIT_COMPLETE_TIMEOUT);
-+ if (ret) {
-+ dev_err(qmp->dev,
-+ "phy common block init timed-out\n");
-+ return ret;
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy)
-+{
-+ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
-+ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
-+ qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+
-+ /* Turn on BIAS current for PHY/PLL */
-+ writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
-+ QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
-+ qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
-+
-+ writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+
-+ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
-+ DP_PHY_PD_CTL_LANE_0_1_PWRDN |
-+ DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
-+ DP_PHY_PD_CTL_DP_CLAMP_EN,
-+ qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+
-+ writel(QSERDES_V3_COM_BIAS_EN |
-+ QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
-+ QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL |
-+ QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
-+ qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
-+
-+ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
-+ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-+ writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
-+ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
-+ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
-+ writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
-+ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
-+ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
-+ writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
-+ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
-+ qphy->dp_aux_cfg = 0;
-+
-+ writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
-+ PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
-+ PHY_AUX_REQ_ERR_MASK,
-+ qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
-+}
-+
-+static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = {
-+ { 0x00, 0x0c, 0x15, 0x1a },
-+ { 0x02, 0x0e, 0x16, 0xff },
-+ { 0x02, 0x11, 0xff, 0xff },
-+ { 0x04, 0xff, 0xff, 0xff }
-+};
-+
-+static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = {
-+ { 0x02, 0x12, 0x16, 0x1a },
-+ { 0x09, 0x19, 0x1f, 0xff },
-+ { 0x10, 0x1f, 0xff, 0xff },
-+ { 0x1f, 0xff, 0xff, 0xff }
-+};
-+
-+static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = {
-+ { 0x00, 0x0c, 0x14, 0x19 },
-+ { 0x00, 0x0b, 0x12, 0xff },
-+ { 0x00, 0x0b, 0xff, 0xff },
-+ { 0x04, 0xff, 0xff, 0xff }
-+};
-+
-+static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = {
-+ { 0x08, 0x0f, 0x16, 0x1f },
-+ { 0x11, 0x1e, 0x1f, 0xff },
-+ { 0x19, 0x1f, 0xff, 0xff },
-+ { 0x1f, 0xff, 0xff, 0xff }
-+};
-+
-+static int qcom_qmp_phy_configure_dp_swing(struct qmp_phy *qphy,
-+ unsigned int drv_lvl_reg, unsigned int emp_post_reg)
-+{
-+ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-+ unsigned int v_level = 0, p_level = 0;
-+ u8 voltage_swing_cfg, pre_emphasis_cfg;
-+ int i;
-+
-+ for (i = 0; i < dp_opts->lanes; i++) {
-+ v_level = max(v_level, dp_opts->voltage[i]);
-+ p_level = max(p_level, dp_opts->pre[i]);
-+ }
-+
-+ if (dp_opts->link_rate <= 2700) {
-+ voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level];
-+ pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level];
-+ } else {
-+ voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr3_hbr2[v_level][p_level];
-+ pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr3_hbr2[v_level][p_level];
-+ }
-+
-+ /* TODO: Move check to config check */
-+ if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF)
-+ return -EINVAL;
-+
-+ /* Enable MUX to use Cursor values from these registers */
-+ voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
-+ pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
-+
-+ writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg);
-+ writel(pre_emphasis_cfg, qphy->tx + emp_post_reg);
-+ writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg);
-+ writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg);
-+
-+ return 0;
-+}
-+
-+static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy)
-+{
-+ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-+ u32 bias_en, drvr_en;
-+
-+ if (qcom_qmp_phy_configure_dp_swing(qphy,
-+ QSERDES_V3_TX_TX_DRV_LVL,
-+ QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0)
-+ return;
-+
-+ if (dp_opts->lanes == 1) {
-+ bias_en = 0x3e;
-+ drvr_en = 0x13;
-+ } else {
-+ bias_en = 0x3f;
-+ drvr_en = 0x10;
-+ }
-+
-+ writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN);
-+ writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
-+ writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN);
-+ writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
-+}
-+
-+static bool qcom_qmp_phy_configure_dp_mode(struct qmp_phy *qphy)
-+{
-+ u32 val;
-+ bool reverse = false;
-+
-+ val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
-+ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN;
-+
-+ /*
-+ * TODO: Assume orientation is CC1 for now and two lanes, need to
-+ * use type-c connector to understand orientation and lanes.
-+ *
-+ * Otherwise val changes to be like below if this code understood
-+ * the orientation of the type-c cable.
-+ *
-+ * if (lane_cnt == 4 || orientation == ORIENTATION_CC2)
-+ * val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN;
-+ * if (lane_cnt == 4 || orientation == ORIENTATION_CC1)
-+ * val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
-+ * if (orientation == ORIENTATION_CC2)
-+ * writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
-+ */
-+ val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
-+ writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+
-+ writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE);
-+
-+ return reverse;
-+}
-+
-+static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy)
-+{
-+ const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
-+ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-+ u32 phy_vco_div, status;
-+ unsigned long pixel_freq;
-+
-+ qcom_qmp_phy_configure_dp_mode(qphy);
-+
-+ writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
-+ writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
-+
-+ switch (dp_opts->link_rate) {
-+ case 1620:
-+ phy_vco_div = 0x1;
-+ pixel_freq = 1620000000UL / 2;
-+ break;
-+ case 2700:
-+ phy_vco_div = 0x1;
-+ pixel_freq = 2700000000UL / 2;
-+ break;
-+ case 5400:
-+ phy_vco_div = 0x2;
-+ pixel_freq = 5400000000UL / 4;
-+ break;
-+ case 8100:
-+ phy_vco_div = 0x0;
-+ pixel_freq = 8100000000UL / 6;
-+ break;
-+ default:
-+ /* Other link rates aren't supported */
-+ return -EINVAL;
-+ }
-+ writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV);
-+
-+ clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
-+ clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
-+
-+ writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
-+ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL);
-+
-+ if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS,
-+ status,
-+ ((status & BIT(0)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
-+ status,
-+ ((status & BIT(1)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ udelay(2000);
-+ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
-+ status,
-+ ((status & BIT(1)) > 0),
-+ 500,
-+ 10000);
-+}
-+
-+/*
-+ * We need to calibrate the aux setting here as many times
-+ * as the caller tries
-+ */
-+static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy)
-+{
-+ static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d };
-+ u8 val;
-+
-+ qphy->dp_aux_cfg++;
-+ qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
-+ val = cfg1_settings[qphy->dp_aux_cfg];
-+
-+ writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-+
-+ return 0;
-+}
-+
-+static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy)
-+{
-+ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
-+ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
-+ qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+
-+ /* Turn on BIAS current for PHY/PLL */
-+ writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN);
-+
-+ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
-+ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-+ writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
-+ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
-+ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
-+ writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
-+ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
-+ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
-+ writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
-+ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
-+ qphy->dp_aux_cfg = 0;
-+
-+ writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
-+ PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
-+ PHY_AUX_REQ_ERR_MASK,
-+ qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
-+}
-+
-+static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy)
-+{
-+ /* Program default values before writing proper values */
-+ writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
-+ writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
-+
-+ writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
-+ writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
-+
-+ qcom_qmp_phy_configure_dp_swing(qphy,
-+ QSERDES_V4_TX_TX_DRV_LVL,
-+ QSERDES_V4_TX_TX_EMP_POST1_LVL);
-+}
-+
-+static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy)
-+{
-+ const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
-+ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-+ u32 phy_vco_div, status;
-+ unsigned long pixel_freq;
-+ u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
-+ bool reverse;
-+
-+ writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1);
-+
-+ reverse = qcom_qmp_phy_configure_dp_mode(qphy);
-+
-+ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-+ writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
-+
-+ writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL);
-+ writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL);
-+
-+ switch (dp_opts->link_rate) {
-+ case 1620:
-+ phy_vco_div = 0x1;
-+ pixel_freq = 1620000000UL / 2;
-+ break;
-+ case 2700:
-+ phy_vco_div = 0x1;
-+ pixel_freq = 2700000000UL / 2;
-+ break;
-+ case 5400:
-+ phy_vco_div = 0x2;
-+ pixel_freq = 5400000000UL / 4;
-+ break;
-+ case 8100:
-+ phy_vco_div = 0x0;
-+ pixel_freq = 8100000000UL / 6;
-+ break;
-+ default:
-+ /* Other link rates aren't supported */
-+ return -EINVAL;
-+ }
-+ writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV);
-+
-+ clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
-+ clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
-+
-+ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL);
-+
-+ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS,
-+ status,
-+ ((status & BIT(0)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
-+ status,
-+ ((status & BIT(0)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
-+ status,
-+ ((status & BIT(1)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
-+ status,
-+ ((status & BIT(0)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
-+ status,
-+ ((status & BIT(1)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ /*
-+ * At least for 7nm DP PHY this has to be done after enabling link
-+ * clock.
-+ */
-+
-+ if (dp_opts->lanes == 1) {
-+ bias0_en = reverse ? 0x3e : 0x15;
-+ bias1_en = reverse ? 0x15 : 0x3e;
-+ drvr0_en = reverse ? 0x13 : 0x10;
-+ drvr1_en = reverse ? 0x10 : 0x13;
-+ } else if (dp_opts->lanes == 2) {
-+ bias0_en = reverse ? 0x3f : 0x15;
-+ bias1_en = reverse ? 0x15 : 0x3f;
-+ drvr0_en = 0x10;
-+ drvr1_en = 0x10;
-+ } else {
-+ bias0_en = 0x3f;
-+ bias1_en = 0x3f;
-+ drvr0_en = 0x10;
-+ drvr1_en = 0x10;
-+ }
-+
-+ writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN);
-+ writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
-+ writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN);
-+ writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
-+
-+ writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ udelay(2000);
-+ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
-+ status,
-+ ((status & BIT(1)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV);
-+ writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV);
-+
-+ writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
-+ writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
-+
-+ writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
-+ writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
-+
-+ return 0;
-+}
-+
-+/*
-+ * We need to calibrate the aux setting here as many times
-+ * as the caller tries
-+ */
-+static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy)
-+{
-+ static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d };
-+ u8 val;
-+
-+ qphy->dp_aux_cfg++;
-+ qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
-+ val = cfg1_settings[qphy->dp_aux_cfg];
-+
-+ writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
-+{
-+ const struct phy_configure_opts_dp *dp_opts = &opts->dp;
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+
-+ memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts));
-+ if (qphy->dp_opts.set_voltages) {
-+ cfg->configure_dp_tx(qphy);
-+ qphy->dp_opts.set_voltages = 0;
-+ }
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_dp_phy_calibrate(struct phy *phy)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+
-+ if (cfg->calibrate_dp_phy)
-+ return cfg->calibrate_dp_phy(qphy);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
-+{
-+ struct qcom_qmp *qmp = qphy->qmp;
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *serdes = qphy->serdes;
-+ void __iomem *pcs = qphy->pcs;
-+ void __iomem *dp_com = qmp->dp_com;
-+ int ret, i;
-+
-+ mutex_lock(&qmp->phy_mutex);
-+ if (qmp->init_count++) {
-+ mutex_unlock(&qmp->phy_mutex);
-+ return 0;
-+ }
-+
-+ /* turn on regulator supplies */
-+ ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
-+ if (ret) {
-+ dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
-+ goto err_unlock;
-+ }
-+
-+ for (i = 0; i < cfg->num_resets; i++) {
-+ ret = reset_control_assert(qmp->resets[i]);
-+ if (ret) {
-+ dev_err(qmp->dev, "%s reset assert failed\n",
-+ cfg->reset_list[i]);
-+ goto err_disable_regulators;
-+ }
-+ }
-+
-+ for (i = cfg->num_resets - 1; i >= 0; i--) {
-+ ret = reset_control_deassert(qmp->resets[i]);
-+ if (ret) {
-+ dev_err(qmp->dev, "%s reset deassert failed\n",
-+ qphy->cfg->reset_list[i]);
-+ goto err_assert_reset;
-+ }
-+ }
-+
-+ ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
-+ if (ret)
-+ goto err_assert_reset;
-+
-+ if (cfg->has_phy_dp_com_ctrl) {
-+ qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
-+ SW_PWRDN);
-+ /* override hardware control for reset of qmp phy */
-+ qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
-+ SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
-+ SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
-+
-+ /* Default type-c orientation, i.e CC1 */
-+ qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02);
-+
-+ qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
-+ USB3_MODE | DP_MODE);
-+
-+ /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
-+ qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
-+ SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
-+ SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
-+
-+ qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
-+ qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
-+ }
-+
-+ if (cfg->has_phy_com_ctrl) {
-+ qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
-+ SW_PWRDN);
-+ } else {
-+ if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
-+ qphy_setbits(pcs,
-+ cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
-+ cfg->pwrdn_ctrl);
-+ else
-+ qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
-+ cfg->pwrdn_ctrl);
-+ }
-+
-+ mutex_unlock(&qmp->phy_mutex);
-+
-+ return 0;
-+
-+err_assert_reset:
-+ while (++i < cfg->num_resets)
-+ reset_control_assert(qmp->resets[i]);
-+err_disable_regulators:
-+ regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
-+err_unlock:
-+ mutex_unlock(&qmp->phy_mutex);
-+
-+ return ret;
-+}
-+
-+static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy)
-+{
-+ struct qcom_qmp *qmp = qphy->qmp;
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *serdes = qphy->serdes;
-+ int i = cfg->num_resets;
-+
-+ mutex_lock(&qmp->phy_mutex);
-+ if (--qmp->init_count) {
-+ mutex_unlock(&qmp->phy_mutex);
-+ return 0;
-+ }
-+
-+ reset_control_assert(qmp->ufs_reset);
-+ if (cfg->has_phy_com_ctrl) {
-+ qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
-+ SERDES_START | PCS_START);
-+ qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
-+ SW_RESET);
-+ qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
-+ SW_PWRDN);
-+ }
-+
-+ while (--i >= 0)
-+ reset_control_assert(qmp->resets[i]);
-+
-+ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
-+
-+ regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
-+
-+ mutex_unlock(&qmp->phy_mutex);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_init(struct phy *phy)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ struct qcom_qmp *qmp = qphy->qmp;
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ int ret;
-+ dev_vdbg(qmp->dev, "Initializing QMP phy\n");
-+
-+ if (cfg->no_pcs_sw_reset) {
-+ /*
-+ * Get UFS reset, which is delayed until now to avoid a
-+ * circular dependency where UFS needs its PHY, but the PHY
-+ * needs this UFS reset.
-+ */
-+ if (!qmp->ufs_reset) {
-+ qmp->ufs_reset =
-+ devm_reset_control_get_exclusive(qmp->dev,
-+ "ufsphy");
-+
-+ if (IS_ERR(qmp->ufs_reset)) {
-+ ret = PTR_ERR(qmp->ufs_reset);
-+ dev_err(qmp->dev,
-+ "failed to get UFS reset: %d\n",
-+ ret);
-+
-+ qmp->ufs_reset = NULL;
-+ return ret;
-+ }
-+ }
-+
-+ ret = reset_control_assert(qmp->ufs_reset);
-+ if (ret)
-+ return ret;
-+ }
-+
-+ ret = qcom_qmp_phy_com_init(qphy);
-+ if (ret)
-+ return ret;
-+
-+ if (cfg->type == PHY_TYPE_DP)
-+ cfg->dp_aux_init(qphy);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_power_on(struct phy *phy)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ struct qcom_qmp *qmp = qphy->qmp;
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *tx = qphy->tx;
-+ void __iomem *rx = qphy->rx;
-+ void __iomem *pcs = qphy->pcs;
-+ void __iomem *pcs_misc = qphy->pcs_misc;
-+ void __iomem *status;
-+ unsigned int mask, val, ready;
-+ int ret;
-+
-+ qcom_qmp_phy_serdes_init(qphy);
-+
-+ if (cfg->has_lane_rst) {
-+ ret = reset_control_deassert(qphy->lane_rst);
-+ if (ret) {
-+ dev_err(qmp->dev, "lane%d reset deassert failed\n",
-+ qphy->index);
-+ return ret;
-+ }
-+ }
-+
-+ ret = clk_prepare_enable(qphy->pipe_clk);
-+ if (ret) {
-+ dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
-+ goto err_reset_lane;
-+ }
-+
-+ /* Tx, Rx, and PCS configurations */
-+ qcom_qmp_phy_configure_lane(tx, cfg->regs,
-+ cfg->tx_tbl, cfg->tx_tbl_num, 1);
-+ if (cfg->tx_tbl_sec)
-+ qcom_qmp_phy_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
-+ cfg->tx_tbl_num_sec, 1);
-+
-+ /* Configuration for other LANE for USB-DP combo PHY */
-+ if (cfg->is_dual_lane_phy) {
-+ qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
-+ cfg->tx_tbl, cfg->tx_tbl_num, 2);
-+ if (cfg->tx_tbl_sec)
-+ qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
-+ cfg->tx_tbl_sec,
-+ cfg->tx_tbl_num_sec, 2);
-+ }
-+
-+ /* Configure special DP tx tunings */
-+ if (cfg->type == PHY_TYPE_DP)
-+ cfg->configure_dp_tx(qphy);
-+
-+ qcom_qmp_phy_configure_lane(rx, cfg->regs,
-+ cfg->rx_tbl, cfg->rx_tbl_num, 1);
-+ if (cfg->rx_tbl_sec)
-+ qcom_qmp_phy_configure_lane(rx, cfg->regs,
-+ cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1);
-+
-+ if (cfg->is_dual_lane_phy) {
-+ qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
-+ cfg->rx_tbl, cfg->rx_tbl_num, 2);
-+ if (cfg->rx_tbl_sec)
-+ qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
-+ cfg->rx_tbl_sec,
-+ cfg->rx_tbl_num_sec, 2);
-+ }
-+
-+ /* Configure link rate, swing, etc. */
-+ if (cfg->type == PHY_TYPE_DP) {
-+ cfg->configure_dp_phy(qphy);
-+ } else {
-+ qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
-+ if (cfg->pcs_tbl_sec)
-+ qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
-+ cfg->pcs_tbl_num_sec);
-+ }
-+
-+ ret = reset_control_deassert(qmp->ufs_reset);
-+ if (ret)
-+ goto err_disable_pipe_clk;
-+
-+ qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
-+ cfg->pcs_misc_tbl_num);
-+ if (cfg->pcs_misc_tbl_sec)
-+ qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
-+ cfg->pcs_misc_tbl_num_sec);
-+
-+ /*
-+ * Pull out PHY from POWER DOWN state.
-+ * This is active low enable signal to power-down PHY.
-+ */
-+ if(cfg->type == PHY_TYPE_PCIE)
-+ qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
-+
-+ if (cfg->has_pwrdn_delay)
-+ usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
-+
-+ if (cfg->type != PHY_TYPE_DP) {
-+ /* Pull PHY out of reset state */
-+ if (!cfg->no_pcs_sw_reset)
-+ qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
-+ /* start SerDes and Phy-Coding-Sublayer */
-+ qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
-+
-+ if (cfg->type == PHY_TYPE_UFS) {
-+ status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
-+ mask = PCS_READY;
-+ ready = PCS_READY;
-+ } else {
-+ status = pcs + cfg->regs[QPHY_PCS_STATUS];
-+ mask = cfg->phy_status;
-+ ready = 0;
-+ }
-+
-+ ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
-+ PHY_INIT_COMPLETE_TIMEOUT);
-+ if (ret) {
-+ dev_err(qmp->dev, "phy initialization timed-out\n");
-+ goto err_disable_pipe_clk;
-+ }
-+ }
-+ return 0;
-+
-+err_disable_pipe_clk:
-+ clk_disable_unprepare(qphy->pipe_clk);
-+err_reset_lane:
-+ if (cfg->has_lane_rst)
-+ reset_control_assert(qphy->lane_rst);
-+
-+ return ret;
-+}
-+
-+static int qcom_qmp_phy_power_off(struct phy *phy)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+
-+ clk_disable_unprepare(qphy->pipe_clk);
-+
-+ if (cfg->type == PHY_TYPE_DP) {
-+ /* Assert DP PHY power down */
-+ writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+ } else {
-+ /* PHY reset */
-+ if (!cfg->no_pcs_sw_reset)
-+ qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
-+
-+ /* stop SerDes and Phy-Coding-Sublayer */
-+ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
-+
-+ /* Put PHY into POWER DOWN state: active low */
-+ if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
-+ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
-+ cfg->pwrdn_ctrl);
-+ } else {
-+ qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
-+ cfg->pwrdn_ctrl);
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_exit(struct phy *phy)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+
-+ if (cfg->has_lane_rst)
-+ reset_control_assert(qphy->lane_rst);
-+
-+ qcom_qmp_phy_com_exit(qphy);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_enable(struct phy *phy)
-+{
-+ int ret;
-+
-+ ret = qcom_qmp_phy_init(phy);
-+ if (ret)
-+ return ret;
-+
-+ ret = qcom_qmp_phy_power_on(phy);
-+ if (ret)
-+ qcom_qmp_phy_exit(phy);
-+
-+ return ret;
-+}
-+
-+static int qcom_qmp_phy_disable(struct phy *phy)
-+{
-+ int ret;
-+
-+ ret = qcom_qmp_phy_power_off(phy);
-+ if (ret)
-+ return ret;
-+ return qcom_qmp_phy_exit(phy);
-+}
-+
-+static int qcom_qmp_phy_set_mode(struct phy *phy,
-+ enum phy_mode mode, int submode)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+
-+ qphy->mode = mode;
-+
-+ return 0;
-+}
-+
-+static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
-+{
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *pcs = qphy->pcs;
-+ void __iomem *pcs_misc = qphy->pcs_misc;
-+ u32 intr_mask;
-+
-+ if (qphy->mode == PHY_MODE_USB_HOST_SS ||
-+ qphy->mode == PHY_MODE_USB_DEVICE_SS)
-+ intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
-+ else
-+ intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
-+
-+ /* Clear any pending interrupts status */
-+ qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
-+ /* Writing 1 followed by 0 clears the interrupt */
-+ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
-+
-+ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
-+ ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
-+
-+ /* Enable required PHY autonomous mode interrupts */
-+ qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
-+
-+ /* Enable i/o clamp_n for autonomous mode */
-+ if (pcs_misc)
-+ qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
-+}
-+
-+static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
-+{
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *pcs = qphy->pcs;
-+ void __iomem *pcs_misc = qphy->pcs_misc;
-+
-+ /* Disable i/o clamp_n on resume for normal mode */
-+ if (pcs_misc)
-+ qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
-+
-+ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
-+ ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
-+
-+ qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
-+ /* Writing 1 followed by 0 clears the interrupt */
-+ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
-+}
-+
-+static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ struct qmp_phy *qphy = qmp->phys[0];
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+
-+ dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode);
-+
-+ /* Supported only for USB3 PHY and luckily USB3 is the first phy */
-+ if (cfg->type != PHY_TYPE_USB3)
-+ return 0;
-+
-+ if (!qmp->init_count) {
-+ dev_vdbg(dev, "PHY not initialized, bailing out\n");
-+ return 0;
-+ }
-+
-+ qcom_qmp_phy_enable_autonomous_mode(qphy);
-+
-+ clk_disable_unprepare(qphy->pipe_clk);
-+ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
-+
-+ return 0;
-+}
-+
-+static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ struct qmp_phy *qphy = qmp->phys[0];
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ int ret = 0;
-+
-+ dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode);
-+
-+ /* Supported only for USB3 PHY and luckily USB3 is the first phy */
-+ if (cfg->type != PHY_TYPE_USB3)
-+ return 0;
-+
-+ if (!qmp->init_count) {
-+ dev_vdbg(dev, "PHY not initialized, bailing out\n");
-+ return 0;
-+ }
-+
-+ ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
-+ if (ret)
-+ return ret;
-+
-+ ret = clk_prepare_enable(qphy->pipe_clk);
-+ if (ret) {
-+ dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
-+ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
-+ return ret;
-+ }
-+
-+ qcom_qmp_phy_disable_autonomous_mode(qphy);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ int num = cfg->num_vregs;
-+ int i;
-+
-+ qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
-+ if (!qmp->vregs)
-+ return -ENOMEM;
-+
-+ for (i = 0; i < num; i++)
-+ qmp->vregs[i].supply = cfg->vreg_list[i];
-+
-+ return devm_regulator_bulk_get(dev, num, qmp->vregs);
-+}
-+
-+static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ int i;
-+
-+ qmp->resets = devm_kcalloc(dev, cfg->num_resets,
-+ sizeof(*qmp->resets), GFP_KERNEL);
-+ if (!qmp->resets)
-+ return -ENOMEM;
-+
-+ for (i = 0; i < cfg->num_resets; i++) {
-+ struct reset_control *rst;
-+ const char *name = cfg->reset_list[i];
-+
-+ rst = devm_reset_control_get_exclusive(dev, name);
-+ if (IS_ERR(rst)) {
-+ dev_err(dev, "failed to get %s reset\n", name);
-+ return PTR_ERR(rst);
-+ }
-+ qmp->resets[i] = rst;
-+ }
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ int num = cfg->num_clks;
-+ int i;
-+
-+ qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
-+ if (!qmp->clks)
-+ return -ENOMEM;
-+
-+ for (i = 0; i < num; i++)
-+ qmp->clks[i].id = cfg->clk_list[i];
-+
-+ return devm_clk_bulk_get(dev, num, qmp->clks);
-+}
-+
-+static void phy_clk_release_provider(void *res)
-+{
-+ of_clk_del_provider(res);
-+}
-+
-+/*
-+ * Register a fixed rate pipe clock.
-+ *
-+ * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
-+ * controls it. The <s>_pipe_clk coming out of the GCC is requested
-+ * by the PHY driver for its operations.
-+ * We register the <s>_pipe_clksrc here. The gcc driver takes care
-+ * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
-+ * Below picture shows this relationship.
-+ *
-+ * +---------------+
-+ * | PHY block |<<---------------------------------------+
-+ * | | |
-+ * | +-------+ | +-----+ |
-+ * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
-+ * clk | +-------+ | +-----+
-+ * +---------------+
-+ */
-+static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
-+{
-+ struct clk_fixed_rate *fixed;
-+ struct clk_init_data init = { };
-+ int ret;
-+
-+ ret = of_property_read_string(np, "clock-output-names", &init.name);
-+ if (ret) {
-+ dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
-+ return ret;
-+ }
-+
-+ fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
-+ if (!fixed)
-+ return -ENOMEM;
-+
-+ init.ops = &clk_fixed_rate_ops;
-+
-+ /* controllers using QMP phys use 125MHz pipe clock interface */
-+ fixed->fixed_rate = 125000000;
-+ fixed->hw.init = &init;
-+
-+ ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
-+ if (ret)
-+ return ret;
-+
-+ ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
-+ if (ret)
-+ return ret;
-+
-+ /*
-+ * Roll a devm action because the clock provider is the child node, but
-+ * the child node is not actually a device.
-+ */
-+ return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
-+}
-+
-+/*
-+ * Display Port PLL driver block diagram for branch clocks
-+ *
-+ * +------------------------------+
-+ * | DP_VCO_CLK |
-+ * | |
-+ * | +-------------------+ |
-+ * | | (DP PLL/VCO) | |
-+ * | +---------+---------+ |
-+ * | v |
-+ * | +----------+-----------+ |
-+ * | | hsclk_divsel_clk_src | |
-+ * | +----------+-----------+ |
-+ * +------------------------------+
-+ * |
-+ * +---------<---------v------------>----------+
-+ * | |
-+ * +--------v----------------+ |
-+ * | dp_phy_pll_link_clk | |
-+ * | link_clk | |
-+ * +--------+----------------+ |
-+ * | |
-+ * | |
-+ * v v
-+ * Input to DISPCC block |
-+ * for link clk, crypto clk |
-+ * and interface clock |
-+ * |
-+ * |
-+ * +--------<------------+-----------------+---<---+
-+ * | | |
-+ * +----v---------+ +--------v-----+ +--------v------+
-+ * | vco_divided | | vco_divided | | vco_divided |
-+ * | _clk_src | | _clk_src | | _clk_src |
-+ * | | | | | |
-+ * |divsel_six | | divsel_two | | divsel_four |
-+ * +-------+------+ +-----+--------+ +--------+------+
-+ * | | |
-+ * v---->----------v-------------<------v
-+ * |
-+ * +----------+-----------------+
-+ * | dp_phy_pll_vco_div_clk |
-+ * +---------+------------------+
-+ * |
-+ * v
-+ * Input to DISPCC block
-+ * for DP pixel clock
-+ *
-+ */
-+static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw,
-+ struct clk_rate_request *req)
-+{
-+ switch (req->rate) {
-+ case 1620000000UL / 2:
-+ case 2700000000UL / 2:
-+ /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */
-+ return 0;
-+ default:
-+ return -EINVAL;
-+ }
-+}
-+
-+static unsigned long
-+qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
-+{
-+ const struct qmp_phy_dp_clks *dp_clks;
-+ const struct qmp_phy *qphy;
-+ const struct phy_configure_opts_dp *dp_opts;
-+
-+ dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw);
-+ qphy = dp_clks->qphy;
-+ dp_opts = &qphy->dp_opts;
-+
-+ switch (dp_opts->link_rate) {
-+ case 1620:
-+ return 1620000000UL / 2;
-+ case 2700:
-+ return 2700000000UL / 2;
-+ case 5400:
-+ return 5400000000UL / 4;
-+ case 8100:
-+ return 8100000000UL / 6;
-+ default:
-+ return 0;
-+ }
-+}
-+
-+static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = {
-+ .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate,
-+ .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate,
-+};
-+
-+static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw,
-+ struct clk_rate_request *req)
-+{
-+ switch (req->rate) {
-+ case 162000000:
-+ case 270000000:
-+ case 540000000:
-+ case 810000000:
-+ return 0;
-+ default:
-+ return -EINVAL;
-+ }
-+}
-+
-+static unsigned long
-+qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
-+{
-+ const struct qmp_phy_dp_clks *dp_clks;
-+ const struct qmp_phy *qphy;
-+ const struct phy_configure_opts_dp *dp_opts;
-+
-+ dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw);
-+ qphy = dp_clks->qphy;
-+ dp_opts = &qphy->dp_opts;
-+
-+ switch (dp_opts->link_rate) {
-+ case 1620:
-+ case 2700:
-+ case 5400:
-+ case 8100:
-+ return dp_opts->link_rate * 100000;
-+ default:
-+ return 0;
-+ }
-+}
-+
-+static const struct clk_ops qcom_qmp_dp_link_clk_ops = {
-+ .determine_rate = qcom_qmp_dp_link_clk_determine_rate,
-+ .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate,
-+};
-+
-+static struct clk_hw *
-+qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data)
-+{
-+ struct qmp_phy_dp_clks *dp_clks = data;
-+ unsigned int idx = clkspec->args[0];
-+
-+ if (idx >= 2) {
-+ pr_err("%s: invalid index %u\n", __func__, idx);
-+ return ERR_PTR(-EINVAL);
-+ }
-+
-+ if (idx == 0)
-+ return &dp_clks->dp_link_hw;
-+
-+ return &dp_clks->dp_pixel_hw;
-+}
-+
-+static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy,
-+ struct device_node *np)
-+{
-+ struct clk_init_data init = { };
-+ struct qmp_phy_dp_clks *dp_clks;
-+ char name[64];
-+ int ret;
-+
-+ dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL);
-+ if (!dp_clks)
-+ return -ENOMEM;
-+
-+ dp_clks->qphy = qphy;
-+ qphy->dp_clks = dp_clks;
-+
-+ snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev));
-+ init.ops = &qcom_qmp_dp_link_clk_ops;
-+ init.name = name;
-+ dp_clks->dp_link_hw.init = &init;
-+ ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw);
-+ if (ret)
-+ return ret;
-+
-+ snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev));
-+ init.ops = &qcom_qmp_dp_pixel_clk_ops;
-+ init.name = name;
-+ dp_clks->dp_pixel_hw.init = &init;
-+ ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw);
-+ if (ret)
-+ return ret;
-+
-+ ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks);
-+ if (ret)
-+ return ret;
-+
-+ /*
-+ * Roll a devm action because the clock provider is the child node, but
-+ * the child node is not actually a device.
-+ */
-+ return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
-+}
-+
-+static const struct phy_ops qcom_qmp_phy_gen_ops = {
-+ .init = qcom_qmp_phy_enable,
-+ .exit = qcom_qmp_phy_disable,
-+ .set_mode = qcom_qmp_phy_set_mode,
-+ .owner = THIS_MODULE,
-+};
-+
-+static const struct phy_ops qcom_qmp_phy_dp_ops = {
-+ .init = qcom_qmp_phy_init,
-+ .configure = qcom_qmp_dp_phy_configure,
-+ .power_on = qcom_qmp_phy_power_on,
-+ .calibrate = qcom_qmp_dp_phy_calibrate,
-+ .power_off = qcom_qmp_phy_power_off,
-+ .exit = qcom_qmp_phy_exit,
-+ .set_mode = qcom_qmp_phy_set_mode,
-+ .owner = THIS_MODULE,
-+};
-+
-+static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
-+ .power_on = qcom_qmp_phy_enable,
-+ .power_off = qcom_qmp_phy_disable,
-+ .set_mode = qcom_qmp_phy_set_mode,
-+ .owner = THIS_MODULE,
-+};
-+
-+static void qcom_qmp_reset_control_put(void *data)
-+{
-+ reset_control_put(data);
-+}
-+
-+static
-+int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
-+ void __iomem *serdes, const struct qmp_phy_cfg *cfg)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ struct phy *generic_phy;
-+ struct qmp_phy *qphy;
-+ const struct phy_ops *ops;
-+ char prop_name[MAX_PROP_NAME];
-+ int ret;
-+
-+ qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
-+ if (!qphy)
-+ return -ENOMEM;
-+
-+ qphy->cfg = cfg;
-+ qphy->serdes = serdes;
-+ /*
-+ * Get memory resources for each phy lane:
-+ * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
-+ * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
-+ * For single lane PHYs: pcs_misc (optional) -> 3.
-+ */
-+ qphy->tx = of_iomap(np, 0);
-+ if (!qphy->tx)
-+ return -ENOMEM;
-+
-+ qphy->rx = of_iomap(np, 1);
-+ if (!qphy->rx)
-+ return -ENOMEM;
-+
-+ qphy->pcs = of_iomap(np, 2);
-+ if (!qphy->pcs)
-+ return -ENOMEM;
-+
-+ /*
-+ * If this is a dual-lane PHY, then there should be registers for the
-+ * second lane. Some old device trees did not specify this, so fall
-+ * back to old legacy behavior of assuming they can be reached at an
-+ * offset from the first lane.
-+ */
-+ if (cfg->is_dual_lane_phy) {
-+ qphy->tx2 = of_iomap(np, 3);
-+ qphy->rx2 = of_iomap(np, 4);
-+ if (!qphy->tx2 || !qphy->rx2) {
-+ dev_warn(dev,
-+ "Underspecified device tree, falling back to legacy register regions\n");
-+
-+ /* In the old version, pcs_misc is at index 3. */
-+ qphy->pcs_misc = qphy->tx2;
-+ qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE;
-+ qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
-+
-+ } else {
-+ qphy->pcs_misc = of_iomap(np, 5);
-+ }
-+
-+ } else {
-+ qphy->pcs_misc = of_iomap(np, 3);
-+ }
-+
-+ if (!qphy->pcs_misc)
-+ dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
-+
-+ /*
-+ * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3
-+ * based phys, so they essentially have pipe clock. So,
-+ * we return error in case phy is USB3 or PIPE type.
-+ * Otherwise, we initialize pipe clock to NULL for
-+ * all phys that don't need this.
-+ */
-+ snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
-+ qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name);
-+ if (IS_ERR(qphy->pipe_clk)) {
-+ if (cfg->type == PHY_TYPE_PCIE ||
-+ cfg->type == PHY_TYPE_USB3) {
-+ ret = PTR_ERR(qphy->pipe_clk);
-+ if (ret != -EPROBE_DEFER)
-+ dev_err(dev,
-+ "failed to get lane%d pipe_clk, %d\n",
-+ id, ret);
-+ return ret;
-+ }
-+ qphy->pipe_clk = NULL;
-+ }
-+
-+ /* Get lane reset, if any */
-+ if (cfg->has_lane_rst) {
-+ snprintf(prop_name, sizeof(prop_name), "lane%d", id);
-+ qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name);
-+ if (IS_ERR(qphy->lane_rst)) {
-+ dev_err(dev, "failed to get lane%d reset\n", id);
-+ return PTR_ERR(qphy->lane_rst);
-+ }
-+ ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put,
-+ qphy->lane_rst);
-+ if (ret)
-+ return ret;
-+ }
-+
-+ if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE)
-+ ops = &qcom_qmp_pcie_ufs_ops;
-+ else if (cfg->type == PHY_TYPE_DP)
-+ ops = &qcom_qmp_phy_dp_ops;
-+ else
-+ ops = &qcom_qmp_phy_gen_ops;
-+
-+ generic_phy = devm_phy_create(dev, np, ops);
-+ if (IS_ERR(generic_phy)) {
-+ ret = PTR_ERR(generic_phy);
-+ dev_err(dev, "failed to create qphy %d\n", ret);
-+ return ret;
-+ }
-+
-+ qphy->phy = generic_phy;
-+ qphy->index = id;
-+ qphy->qmp = qmp;
-+ qmp->phys[id] = qphy;
-+ phy_set_drvdata(generic_phy, qphy);
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
-+ {
-+ .compatible = "qcom,ipq8074-qmp-usb3-phy",
-+ .data = &ipq8074_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,msm8996-qmp-pcie-phy",
-+ .data = &msm8996_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,msm8996-qmp-ufs-phy",
-+ .data = &msm8996_ufs_cfg,
-+ }, {
-+ .compatible = "qcom,msm8996-qmp-usb3-phy",
-+ .data = &msm8996_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,msm8998-qmp-pcie-phy",
-+ .data = &msm8998_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,msm8998-qmp-ufs-phy",
-+ .data = &sdm845_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,ipq8074-qmp-pcie-phy",
-+ .data = &ipq8074_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,ipq6018-qmp-pcie-phy",
-+ .data = &ipq6018_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,ipq6018-qmp-usb3-phy",
-+ .data = &ipq8074_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sc7180-qmp-usb3-phy",
-+ .data = &sc7180_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
-+ /* It's a combo phy */
-+ }, {
-+ .compatible = "qcom,sc8180x-qmp-pcie-phy",
-+ .data = &sc8180x_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sc8180x-qmp-ufs-phy",
-+ .data = &sm8150_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sc8280xp-qmp-ufs-phy",
-+ .data = &sm8350_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sc8180x-qmp-usb3-phy",
-+ .data = &sm8150_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
-+ /* It's a combo phy */
-+ }, {
-+ .compatible = "qcom,sdm845-qhp-pcie-phy",
-+ .data = &sdm845_qhp_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sdm845-qmp-pcie-phy",
-+ .data = &sdm845_qmp_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sdm845-qmp-usb3-phy",
-+ .data = &qmp_v3_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
-+ .data = &qmp_v3_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sdm845-qmp-ufs-phy",
-+ .data = &sdm845_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,msm8998-qmp-usb3-phy",
-+ .data = &msm8998_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sm6115-qmp-ufs-phy",
-+ .data = &sm6115_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm6350-qmp-ufs-phy",
-+ .data = &sdm845_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8150-qmp-ufs-phy",
-+ .data = &sm8150_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-ufs-phy",
-+ .data = &sm8150_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8150-qmp-usb3-phy",
-+ .data = &sm8150_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8150-qmp-usb3-uni-phy",
-+ .data = &sm8150_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-usb3-phy",
-+ .data = &sm8250_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
-+ /* It's a combo phy */
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-usb3-uni-phy",
-+ .data = &sm8250_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
-+ .data = &sm8250_qmp_gen3x1_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
-+ .data = &sm8250_qmp_gen3x2_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8350-qmp-ufs-phy",
-+ .data = &sm8350_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
-+ .data = &sm8250_qmp_gen3x2_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sdx55-qmp-pcie-phy",
-+ .data = &sdx55_qmp_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sdx55-qmp-usb3-uni-phy",
-+ .data = &sdx55_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sdx65-qmp-usb3-uni-phy",
-+ .data = &sdx65_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8350-qmp-usb3-phy",
-+ .data = &sm8350_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8350-qmp-usb3-uni-phy",
-+ .data = &sm8350_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
-+ .data = &sm8450_qmp_gen3x1_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
-+ .data = &sm8450_qmp_gen4x2_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8450-qmp-ufs-phy",
-+ .data = &sm8450_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8450-qmp-usb3-phy",
-+ .data = &sm8350_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,qcm2290-qmp-usb3-phy",
-+ .data = &qcm2290_usb3phy_cfg,
-+ },
-+ { },
-+};
-+MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
-+
-+static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = {
-+ {
-+ .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
-+ .data = &sc7180_usb3dpphy_cfg,
-+ },
-+ {
-+ .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
-+ .data = &sm8250_usb3dpphy_cfg,
-+ },
-+ {
-+ .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
-+ .data = &sc8180x_usb3dpphy_cfg,
-+ },
-+ { }
-+};
-+
-+static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
-+ SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
-+ qcom_qmp_phy_runtime_resume, NULL)
-+};
-+
-+static int qcom_qmp_phy_probe(struct platform_device *pdev)
-+{
-+ struct qcom_qmp *qmp;
-+ struct device *dev = &pdev->dev;
-+ struct device_node *child;
-+ struct phy_provider *phy_provider;
-+ void __iomem *serdes;
-+ void __iomem *usb_serdes;
-+ void __iomem *dp_serdes = NULL;
-+ const struct qmp_phy_combo_cfg *combo_cfg = NULL;
-+ const struct qmp_phy_cfg *cfg = NULL;
-+ const struct qmp_phy_cfg *usb_cfg = NULL;
-+ const struct qmp_phy_cfg *dp_cfg = NULL;
-+ int num, id, expected_phys;
-+ int ret;
-+
-+ qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
-+ if (!qmp)
-+ return -ENOMEM;
-+
-+ qmp->dev = dev;
-+ dev_set_drvdata(dev, qmp);
-+
-+ /* Get the specific init parameters of QMP phy */
-+ cfg = of_device_get_match_data(dev);
-+ if (!cfg) {
-+ const struct of_device_id *match;
-+
-+ match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev);
-+ if (!match)
-+ return -EINVAL;
-+
-+ combo_cfg = match->data;
-+ if (!combo_cfg)
-+ return -EINVAL;
-+
-+ usb_cfg = combo_cfg->usb_cfg;
-+ cfg = usb_cfg; /* Setup clks and regulators */
-+ }
-+
-+ /* per PHY serdes; usually located at base address */
-+ usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0);
-+ if (IS_ERR(serdes))
-+ return PTR_ERR(serdes);
-+
-+ /* per PHY dp_com; if PHY has dp_com control block */
-+ if (combo_cfg || cfg->has_phy_dp_com_ctrl) {
-+ qmp->dp_com = devm_platform_ioremap_resource(pdev, 1);
-+ if (IS_ERR(qmp->dp_com))
-+ return PTR_ERR(qmp->dp_com);
-+ }
-+
-+ if (combo_cfg) {
-+ /* Only two serdes for combo PHY */
-+ dp_serdes = devm_platform_ioremap_resource(pdev, 2);
-+ if (IS_ERR(dp_serdes))
-+ return PTR_ERR(dp_serdes);
-+
-+ dp_cfg = combo_cfg->dp_cfg;
-+ expected_phys = 2;
-+ } else {
-+ expected_phys = cfg->nlanes;
-+ }
-+
-+ mutex_init(&qmp->phy_mutex);
-+
-+ ret = qcom_qmp_phy_clk_init(dev, cfg);
-+ if (ret)
-+ return ret;
-+
-+ ret = qcom_qmp_phy_reset_init(dev, cfg);
-+ if (ret)
-+ return ret;
-+
-+ ret = qcom_qmp_phy_vreg_init(dev, cfg);
-+ if (ret) {
-+ if (ret != -EPROBE_DEFER)
-+ dev_err(dev, "failed to get regulator supplies: %d\n",
-+ ret);
-+ return ret;
-+ }
-+
-+ num = of_get_available_child_count(dev->of_node);
-+ /* do we have a rogue child node ? */
-+ if (num > expected_phys)
-+ return -EINVAL;
-+
-+ qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
-+ if (!qmp->phys)
-+ return -ENOMEM;
-+
-+ pm_runtime_set_active(dev);
-+ pm_runtime_enable(dev);
-+ /*
-+ * Prevent runtime pm from being ON by default. Users can enable
-+ * it using power/control in sysfs.
-+ */
-+ pm_runtime_forbid(dev);
-+
-+ id = 0;
-+ for_each_available_child_of_node(dev->of_node, child) {
-+ if (of_node_name_eq(child, "dp-phy")) {
-+ cfg = dp_cfg;
-+ serdes = dp_serdes;
-+ } else if (of_node_name_eq(child, "usb3-phy")) {
-+ cfg = usb_cfg;
-+ serdes = usb_serdes;
-+ }
-+
-+ /* Create per-lane phy */
-+ ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg);
-+ if (ret) {
-+ dev_err(dev, "failed to create lane%d phy, %d\n",
-+ id, ret);
-+ goto err_node_put;
-+ }
-+
-+ /*
-+ * Register the pipe clock provided by phy.
-+ * See function description to see details of this pipe clock.
-+ */
-+ if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) {
-+ ret = phy_pipe_clk_register(qmp, child);
-+ if (ret) {
-+ dev_err(qmp->dev,
-+ "failed to register pipe clock source\n");
-+ goto err_node_put;
-+ }
-+ } else if (cfg->type == PHY_TYPE_DP) {
-+ ret = phy_dp_clks_register(qmp, qmp->phys[id], child);
-+ if (ret) {
-+ dev_err(qmp->dev,
-+ "failed to register DP clock source\n");
-+ goto err_node_put;
-+ }
-+ }
-+ id++;
-+ }
-+
-+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
-+ if (!IS_ERR(phy_provider))
-+ dev_info(dev, "Registered Qcom-QMP phy\n");
-+ else
-+ pm_runtime_disable(dev);
-+
-+ return PTR_ERR_OR_ZERO(phy_provider);
-+
-+err_node_put:
-+ pm_runtime_disable(dev);
-+ of_node_put(child);
-+ return ret;
-+}
-+
-+static struct platform_driver qcom_qmp_phy_driver = {
-+ .probe = qcom_qmp_phy_probe,
-+ .driver = {
-+ .name = "qcom-qmp-phy",
-+ .pm = &qcom_qmp_phy_pm_ops,
-+ .of_match_table = qcom_qmp_phy_of_match_table,
-+ },
-+};
-+
-+module_platform_driver(qcom_qmp_phy_driver);
-+
-+MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
-+MODULE_DESCRIPTION("Qualcomm QMP PHY driver");
-+MODULE_LICENSE("GPL v2");
-diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
-new file mode 100644
-index 000000000000..c7309e981bfb
---- /dev/null
-+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
-@@ -0,0 +1,6350 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/clk-provider.h>
-+#include <linux/delay.h>
-+#include <linux/err.h>
-+#include <linux/io.h>
-+#include <linux/iopoll.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/of_device.h>
-+#include <linux/of_address.h>
-+#include <linux/phy/phy.h>
-+#include <linux/platform_device.h>
-+#include <linux/regulator/consumer.h>
-+#include <linux/reset.h>
-+#include <linux/slab.h>
-+
-+#include <dt-bindings/phy/phy.h>
-+
-+#include "phy-qcom-qmp.h"
-+
-+/* QPHY_SW_RESET bit */
-+#define SW_RESET BIT(0)
-+/* QPHY_POWER_DOWN_CONTROL */
-+#define SW_PWRDN BIT(0)
-+#define REFCLK_DRV_DSBL BIT(1)
-+/* QPHY_START_CONTROL bits */
-+#define SERDES_START BIT(0)
-+#define PCS_START BIT(1)
-+#define PLL_READY_GATE_EN BIT(3)
-+/* QPHY_PCS_STATUS bit */
-+#define PHYSTATUS BIT(6)
-+#define PHYSTATUS_4_20 BIT(7)
-+/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */
-+#define PCS_READY BIT(0)
-+
-+/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
-+/* DP PHY soft reset */
-+#define SW_DPPHY_RESET BIT(0)
-+/* mux to select DP PHY reset control, 0:HW control, 1: software reset */
-+#define SW_DPPHY_RESET_MUX BIT(1)
-+/* USB3 PHY soft reset */
-+#define SW_USB3PHY_RESET BIT(2)
-+/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
-+#define SW_USB3PHY_RESET_MUX BIT(3)
-+
-+/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
-+#define USB3_MODE BIT(0) /* enables USB3 mode */
-+#define DP_MODE BIT(1) /* enables DP mode */
-+
-+/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
-+#define ARCVR_DTCT_EN BIT(0)
-+#define ALFPS_DTCT_EN BIT(1)
-+#define ARCVR_DTCT_EVENT_SEL BIT(4)
-+
-+/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
-+#define IRQ_CLEAR BIT(0)
-+
-+/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
-+#define RCVR_DETECT BIT(0)
-+
-+/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
-+#define CLAMP_EN BIT(0) /* enables i/o clamp_n */
-+
-+#define PHY_INIT_COMPLETE_TIMEOUT 10000
-+#define POWER_DOWN_DELAY_US_MIN 10
-+#define POWER_DOWN_DELAY_US_MAX 11
-+
-+#define MAX_PROP_NAME 32
-+
-+/* Define the assumed distance between lanes for underspecified device trees. */
-+#define QMP_PHY_LEGACY_LANE_STRIDE 0x400
-+
-+struct qmp_phy_init_tbl {
-+ unsigned int offset;
-+ unsigned int val;
-+ /*
-+ * register part of layout ?
-+ * if yes, then offset gives index in the reg-layout
-+ */
-+ bool in_layout;
-+ /*
-+ * mask of lanes for which this register is written
-+ * for cases when second lane needs different values
-+ */
-+ u8 lane_mask;
-+};
-+
-+#define QMP_PHY_INIT_CFG(o, v) \
-+ { \
-+ .offset = o, \
-+ .val = v, \
-+ .lane_mask = 0xff, \
-+ }
-+
-+#define QMP_PHY_INIT_CFG_L(o, v) \
-+ { \
-+ .offset = o, \
-+ .val = v, \
-+ .in_layout = true, \
-+ .lane_mask = 0xff, \
-+ }
-+
-+#define QMP_PHY_INIT_CFG_LANE(o, v, l) \
-+ { \
-+ .offset = o, \
-+ .val = v, \
-+ .lane_mask = l, \
-+ }
-+
-+/* set of registers with offsets different per-PHY */
-+enum qphy_reg_layout {
-+ /* Common block control registers */
-+ QPHY_COM_SW_RESET,
-+ QPHY_COM_POWER_DOWN_CONTROL,
-+ QPHY_COM_START_CONTROL,
-+ QPHY_COM_PCS_READY_STATUS,
-+ /* PCS registers */
-+ QPHY_PLL_LOCK_CHK_DLY_TIME,
-+ QPHY_FLL_CNTRL1,
-+ QPHY_FLL_CNTRL2,
-+ QPHY_FLL_CNT_VAL_L,
-+ QPHY_FLL_CNT_VAL_H_TOL,
-+ QPHY_FLL_MAN_CODE,
-+ QPHY_SW_RESET,
-+ QPHY_START_CTRL,
-+ QPHY_PCS_READY_STATUS,
-+ QPHY_PCS_STATUS,
-+ QPHY_PCS_AUTONOMOUS_MODE_CTRL,
-+ QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
-+ QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
-+ QPHY_PCS_POWER_DOWN_CONTROL,
-+ /* PCS_MISC registers */
-+ QPHY_PCS_MISC_TYPEC_CTRL,
-+ /* Keep last to ensure regs_layout arrays are properly initialized */
-+ QPHY_LAYOUT_SIZE
-+};
-+
-+static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_START_CTRL] = 0x00,
-+ [QPHY_PCS_READY_STATUS] = 0x168,
-+};
-+
-+static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x44,
-+ [QPHY_PCS_STATUS] = 0x14,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
-+};
-+
-+static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_COM_SW_RESET] = 0x400,
-+ [QPHY_COM_POWER_DOWN_CONTROL] = 0x404,
-+ [QPHY_COM_START_CONTROL] = 0x408,
-+ [QPHY_COM_PCS_READY_STATUS] = 0x448,
-+ [QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8,
-+ [QPHY_FLL_CNTRL1] = 0xc4,
-+ [QPHY_FLL_CNTRL2] = 0xc8,
-+ [QPHY_FLL_CNT_VAL_L] = 0xcc,
-+ [QPHY_FLL_CNT_VAL_H_TOL] = 0xd0,
-+ [QPHY_FLL_MAN_CODE] = 0xd4,
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_STATUS] = 0x174,
-+};
-+
-+static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_FLL_CNTRL1] = 0xc0,
-+ [QPHY_FLL_CNTRL2] = 0xc4,
-+ [QPHY_FLL_CNT_VAL_L] = 0xc8,
-+ [QPHY_FLL_CNT_VAL_H_TOL] = 0xcc,
-+ [QPHY_FLL_MAN_CODE] = 0xd0,
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_STATUS] = 0x17c,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
-+};
-+
-+static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_STATUS] = 0x174,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
-+};
-+
-+static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_STATUS] = 0x174,
-+};
-+
-+static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_STATUS] = 0x2ac,
-+};
-+
-+static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x44,
-+ [QPHY_PCS_STATUS] = 0x14,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314,
-+};
-+
-+static const unsigned int qmp_v4_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x44,
-+ [QPHY_PCS_STATUS] = 0x14,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x608,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x614,
-+};
-+
-+static const unsigned int sm8350_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x44,
-+ [QPHY_PCS_STATUS] = 0x14,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x1008,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x1014,
-+};
-+
-+static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0xd8,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc,
-+ [QPHY_PCS_STATUS] = 0x174,
-+ [QPHY_PCS_MISC_TYPEC_CTRL] = 0x00,
-+};
-+
-+static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_START_CTRL] = 0x00,
-+ [QPHY_PCS_READY_STATUS] = 0x160,
-+};
-+
-+static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_START_CTRL] = 0x00,
-+ [QPHY_PCS_READY_STATUS] = 0x168,
-+};
-+
-+static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x44,
-+ [QPHY_PCS_STATUS] = 0x14,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
-+};
-+
-+static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START,
-+ [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS,
-+ [QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET,
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
-+ /* PLL and Loop filter settings */
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-+ /* SSC settings */
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
-+ QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
-+
-+ QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
-+
-+ QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
-+ QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
-+ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
-+ /* PLL and Loop filter settings */
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-+ /* SSC settings */
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
-+ /* FLL settings */
-+ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03),
-+ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02),
-+ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42),
-+ QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
-+
-+ /* Lock Det settings */
-+ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x61),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d),
-+ QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10),
-+ QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_PRE, 0x00),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_POST, 0x58),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
-+ QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
-+ QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
-+ QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
-+ QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
-+ QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
-+ QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
-+ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
-+ QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
-+ QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = {
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
-+ /* FLL settings */
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+
-+ /* Lock Det settings */
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
-+ /* FLL settings */
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+
-+ /* Lock Det settings */
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
-+};
-+
-+static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
-+
-+ /* Rate B */
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),
-+};
-+
-+static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B),
-+};
-+
-+static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_RX_PWM_GEAR_BAND, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_CTRL2, 0x6d),
-+ QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_DRV_LVL, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_DRV_LVL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
-+ QMP_PHY_INIT_CFG(QPHY_RX_SYM_RESYNC_CTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
-+ QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
-+
-+ /* Rate B */
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
-+
-+ /* Rate B */
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
-+
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
-+ /* Lock Det settings */
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20),
-+};
-+
-+static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
-+};
-+
-+static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5),
-+};
-+
-+static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
-+};
-+
-+static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),
-+};
-+
-+static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
-+
-+ /* Rate B */
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+};
-+
-+static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01),
-+};
-+
-+static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
-+
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05),
-+
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
-+
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
-+
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
-+};
-+
-+/* Register names should be validated, they might be different for this PHY */
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
-+};
-+
-+struct qmp_phy;
-+
-+/* struct qmp_phy_cfg - per-PHY initialization config */
-+struct qmp_phy_cfg {
-+ /* phy-type - PCIE/UFS/USB */
-+ unsigned int type;
-+ /* number of lanes provided by phy */
-+ int nlanes;
-+
-+ /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
-+ const struct qmp_phy_init_tbl *serdes_tbl;
-+ int serdes_tbl_num;
-+ const struct qmp_phy_init_tbl *serdes_tbl_sec;
-+ int serdes_tbl_num_sec;
-+ const struct qmp_phy_init_tbl *tx_tbl;
-+ int tx_tbl_num;
-+ const struct qmp_phy_init_tbl *tx_tbl_sec;
-+ int tx_tbl_num_sec;
-+ const struct qmp_phy_init_tbl *rx_tbl;
-+ int rx_tbl_num;
-+ const struct qmp_phy_init_tbl *rx_tbl_sec;
-+ int rx_tbl_num_sec;
-+ const struct qmp_phy_init_tbl *pcs_tbl;
-+ int pcs_tbl_num;
-+ const struct qmp_phy_init_tbl *pcs_tbl_sec;
-+ int pcs_tbl_num_sec;
-+ const struct qmp_phy_init_tbl *pcs_misc_tbl;
-+ int pcs_misc_tbl_num;
-+ const struct qmp_phy_init_tbl *pcs_misc_tbl_sec;
-+ int pcs_misc_tbl_num_sec;
-+
-+ /* Init sequence for DP PHY block link rates */
-+ const struct qmp_phy_init_tbl *serdes_tbl_rbr;
-+ int serdes_tbl_rbr_num;
-+ const struct qmp_phy_init_tbl *serdes_tbl_hbr;
-+ int serdes_tbl_hbr_num;
-+ const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
-+ int serdes_tbl_hbr2_num;
-+ const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
-+ int serdes_tbl_hbr3_num;
-+
-+ /* DP PHY callbacks */
-+ int (*configure_dp_phy)(struct qmp_phy *qphy);
-+ void (*configure_dp_tx)(struct qmp_phy *qphy);
-+ int (*calibrate_dp_phy)(struct qmp_phy *qphy);
-+ void (*dp_aux_init)(struct qmp_phy *qphy);
-+
-+ /* clock ids to be requested */
-+ const char * const *clk_list;
-+ int num_clks;
-+ /* resets to be requested */
-+ const char * const *reset_list;
-+ int num_resets;
-+ /* regulators to be requested */
-+ const char * const *vreg_list;
-+ int num_vregs;
-+
-+ /* array of registers with different offsets */
-+ const unsigned int *regs;
-+
-+ unsigned int start_ctrl;
-+ unsigned int pwrdn_ctrl;
-+ unsigned int mask_com_pcs_ready;
-+ /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
-+ unsigned int phy_status;
-+
-+ /* true, if PHY has a separate PHY_COM control block */
-+ bool has_phy_com_ctrl;
-+ /* true, if PHY has a reset for individual lanes */
-+ bool has_lane_rst;
-+ /* true, if PHY needs delay after POWER_DOWN */
-+ bool has_pwrdn_delay;
-+ /* power_down delay in usec */
-+ int pwrdn_delay_min;
-+ int pwrdn_delay_max;
-+
-+ /* true, if PHY has a separate DP_COM control block */
-+ bool has_phy_dp_com_ctrl;
-+ /* true, if PHY has secondary tx/rx lanes to be configured */
-+ bool is_dual_lane_phy;
-+
-+ /* true, if PCS block has no separate SW_RESET register */
-+ bool no_pcs_sw_reset;
-+};
-+
-+struct qmp_phy_combo_cfg {
-+ const struct qmp_phy_cfg *usb_cfg;
-+ const struct qmp_phy_cfg *dp_cfg;
-+};
-+
-+/**
-+ * struct qmp_phy - per-lane phy descriptor
-+ *
-+ * @phy: generic phy
-+ * @cfg: phy specific configuration
-+ * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
-+ * @tx: iomapped memory space for lane's tx
-+ * @rx: iomapped memory space for lane's rx
-+ * @pcs: iomapped memory space for lane's pcs
-+ * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
-+ * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
-+ * @pcs_misc: iomapped memory space for lane's pcs_misc
-+ * @pipe_clk: pipe clock
-+ * @index: lane index
-+ * @qmp: QMP phy to which this lane belongs
-+ * @lane_rst: lane's reset controller
-+ * @mode: current PHY mode
-+ * @dp_aux_cfg: Display port aux config
-+ * @dp_opts: Display port optional config
-+ * @dp_clks: Display port clocks
-+ */
-+struct qmp_phy {
-+ struct phy *phy;
-+ const struct qmp_phy_cfg *cfg;
-+ void __iomem *serdes;
-+ void __iomem *tx;
-+ void __iomem *rx;
-+ void __iomem *pcs;
-+ void __iomem *tx2;
-+ void __iomem *rx2;
-+ void __iomem *pcs_misc;
-+ struct clk *pipe_clk;
-+ unsigned int index;
-+ struct qcom_qmp *qmp;
-+ struct reset_control *lane_rst;
-+ enum phy_mode mode;
-+ unsigned int dp_aux_cfg;
-+ struct phy_configure_opts_dp dp_opts;
-+ struct qmp_phy_dp_clks *dp_clks;
-+};
-+
-+struct qmp_phy_dp_clks {
-+ struct qmp_phy *qphy;
-+ struct clk_hw dp_link_hw;
-+ struct clk_hw dp_pixel_hw;
-+};
-+
-+/**
-+ * struct qcom_qmp - structure holding QMP phy block attributes
-+ *
-+ * @dev: device
-+ * @dp_com: iomapped memory space for phy's dp_com control block
-+ *
-+ * @clks: array of clocks required by phy
-+ * @resets: array of resets required by phy
-+ * @vregs: regulator supplies bulk data
-+ *
-+ * @phys: array of per-lane phy descriptors
-+ * @phy_mutex: mutex lock for PHY common block initialization
-+ * @init_count: phy common block initialization count
-+ * @ufs_reset: optional UFS PHY reset handle
-+ */
-+struct qcom_qmp {
-+ struct device *dev;
-+ void __iomem *dp_com;
-+
-+ struct clk_bulk_data *clks;
-+ struct reset_control **resets;
-+ struct regulator_bulk_data *vregs;
-+
-+ struct qmp_phy **phys;
-+
-+ struct mutex phy_mutex;
-+ int init_count;
-+
-+ struct reset_control *ufs_reset;
-+};
-+
-+static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy);
-+static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy);
-+static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy);
-+static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy);
-+
-+static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy);
-+static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy);
-+static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy);
-+static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy);
-+
-+static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
-+{
-+ u32 reg;
-+
-+ reg = readl(base + offset);
-+ reg |= val;
-+ writel(reg, base + offset);
-+
-+ /* ensure that above write is through */
-+ readl(base + offset);
-+}
-+
-+static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
-+{
-+ u32 reg;
-+
-+ reg = readl(base + offset);
-+ reg &= ~val;
-+ writel(reg, base + offset);
-+
-+ /* ensure that above write is through */
-+ readl(base + offset);
-+}
-+
-+/* list of clocks required by phy */
-+static const char * const msm8996_phy_clk_l[] = {
-+ "aux", "cfg_ahb", "ref",
-+};
-+
-+static const char * const msm8996_ufs_phy_clk_l[] = {
-+ "ref",
-+};
-+
-+static const char * const qmp_v3_phy_clk_l[] = {
-+ "aux", "cfg_ahb", "ref", "com_aux",
-+};
-+
-+static const char * const sdm845_pciephy_clk_l[] = {
-+ "aux", "cfg_ahb", "ref", "refgen",
-+};
-+
-+static const char * const qmp_v4_phy_clk_l[] = {
-+ "aux", "ref_clk_src", "ref", "com_aux",
-+};
-+
-+/* the primary usb3 phy on sm8250 doesn't have a ref clock */
-+static const char * const qmp_v4_sm8250_usbphy_clk_l[] = {
-+ "aux", "ref_clk_src", "com_aux"
-+};
-+
-+static const char * const sm8450_ufs_phy_clk_l[] = {
-+ "qref", "ref", "ref_aux",
-+};
-+
-+static const char * const sdm845_ufs_phy_clk_l[] = {
-+ "ref", "ref_aux",
-+};
-+
-+/* usb3 phy on sdx55 doesn't have com_aux clock */
-+static const char * const qmp_v4_sdx55_usbphy_clk_l[] = {
-+ "aux", "cfg_ahb", "ref"
-+};
-+
-+static const char * const qcm2290_usb3phy_clk_l[] = {
-+ "cfg_ahb", "ref", "com_aux",
-+};
-+
-+/* list of resets */
-+static const char * const msm8996_pciephy_reset_l[] = {
-+ "phy", "common", "cfg",
-+};
-+
-+static const char * const msm8996_usb3phy_reset_l[] = {
-+ "phy", "common",
-+};
-+
-+static const char * const sc7180_usb3phy_reset_l[] = {
-+ "phy",
-+};
-+
-+static const char * const qcm2290_usb3phy_reset_l[] = {
-+ "phy_phy", "phy",
-+};
-+
-+static const char * const sdm845_pciephy_reset_l[] = {
-+ "phy",
-+};
-+
-+/* list of regulators */
-+static const char * const qmp_phy_vreg_l[] = {
-+ "vdda-phy", "vdda-pll",
-+};
-+
-+static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = ipq8074_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
-+ .tx_tbl = msm8996_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
-+ .rx_tbl = ipq8074_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
-+ .pcs_tbl = ipq8074_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
-+ .clk_list = msm8996_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+};
-+
-+static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 3,
-+
-+ .serdes_tbl = msm8996_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
-+ .tx_tbl = msm8996_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8996_pcie_tx_tbl),
-+ .rx_tbl = msm8996_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(msm8996_pcie_rx_tbl),
-+ .pcs_tbl = msm8996_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
-+ .clk_list = msm8996_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-+ .reset_list = msm8996_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = pciephy_regs_layout,
-+
-+ .start_ctrl = PCS_START | PLL_READY_GATE_EN,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .mask_com_pcs_ready = PCS_READY,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_phy_com_ctrl = true,
-+ .has_lane_rst = true,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg msm8996_ufs_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = msm8996_ufs_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(msm8996_ufs_serdes_tbl),
-+ .tx_tbl = msm8996_ufs_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8996_ufs_tx_tbl),
-+ .rx_tbl = msm8996_ufs_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(msm8996_ufs_rx_tbl),
-+
-+ .clk_list = msm8996_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
-+
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+
-+ .regs = msm8996_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .no_pcs_sw_reset = true,
-+};
-+
-+static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = msm8996_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
-+ .tx_tbl = msm8996_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
-+ .rx_tbl = msm8996_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl),
-+ .pcs_tbl = msm8996_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
-+ .clk_list = msm8996_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+};
-+
-+static const char * const ipq8074_pciephy_clk_l[] = {
-+ "aux", "cfg_ahb",
-+};
-+/* list of resets */
-+static const char * const ipq8074_pciephy_reset_l[] = {
-+ "phy", "common",
-+};
-+
-+static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = ipq8074_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
-+ .tx_tbl = ipq8074_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
-+ .rx_tbl = ipq8074_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
-+ .pcs_tbl = ipq8074_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
-+ .clk_list = ipq8074_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
-+ .reset_list = ipq8074_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
-+ .vreg_list = NULL,
-+ .num_vregs = 0,
-+ .regs = pciephy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_phy_com_ctrl = false,
-+ .has_lane_rst = false,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = ipq6018_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl),
-+ .tx_tbl = ipq6018_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl),
-+ .rx_tbl = ipq6018_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
-+ .pcs_tbl = ipq6018_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
-+ .clk_list = ipq8074_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
-+ .reset_list = ipq8074_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
-+ .vreg_list = NULL,
-+ .num_vregs = 0,
-+ .regs = ipq_pciephy_gen3_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+
-+ .has_phy_com_ctrl = false,
-+ .has_lane_rst = false,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sdm845_qmp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
-+ .tx_tbl = sdm845_qmp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),
-+ .rx_tbl = sdm845_qmp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),
-+ .pcs_tbl = sdm845_qmp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sdm845_qmp_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sdm845_qmp_pciephy_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sdm845_qhp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
-+ .tx_tbl = sdm845_qhp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
-+ .rx_tbl = sdm845_qhp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl),
-+ .pcs_tbl = sdm845_qhp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sdm845_qhp_pciephy_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
-+ .serdes_tbl_sec = sm8250_qmp_gen3x1_pcie_serdes_tbl,
-+ .serdes_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
-+ .tx_tbl = sm8250_qmp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
-+ .rx_tbl = sm8250_qmp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
-+ .rx_tbl_sec = sm8250_qmp_gen3x1_pcie_rx_tbl,
-+ .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),
-+ .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
-+ .pcs_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_tbl,
-+ .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
-+ .pcs_misc_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
-+ .tx_tbl = sm8250_qmp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
-+ .tx_tbl_sec = sm8250_qmp_gen3x2_pcie_tx_tbl,
-+ .tx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),
-+ .rx_tbl = sm8250_qmp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
-+ .rx_tbl_sec = sm8250_qmp_gen3x2_pcie_rx_tbl,
-+ .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl),
-+ .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
-+ .pcs_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_tbl,
-+ .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
-+ .pcs_misc_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v3_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
-+ .tx_tbl = qmp_v3_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
-+ .rx_tbl = qmp_v3_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
-+ .pcs_tbl = qmp_v3_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
-+ .clk_list = qmp_v3_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v3_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
-+ .tx_tbl = qmp_v3_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
-+ .rx_tbl = qmp_v3_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
-+ .pcs_tbl = qmp_v3_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
-+ .clk_list = qmp_v3_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-+ .reset_list = sc7180_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sc7180_dpphy_cfg = {
-+ .type = PHY_TYPE_DP,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v3_dp_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
-+ .tx_tbl = qmp_v3_dp_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
-+
-+ .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr,
-+ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
-+ .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr,
-+ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
-+ .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2,
-+ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
-+ .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3,
-+ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
-+
-+ .clk_list = qmp_v3_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-+ .reset_list = sc7180_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+
-+ .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init,
-+ .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx,
-+ .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy,
-+ .calibrate_dp_phy = qcom_qmp_v3_dp_phy_calibrate,
-+};
-+
-+static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = {
-+ .usb_cfg = &sc7180_usb3phy_cfg,
-+ .dp_cfg = &sc7180_dpphy_cfg,
-+};
-+
-+static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
-+ .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v3_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sdm845_ufsphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
-+ .tx_tbl = sdm845_ufsphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
-+ .rx_tbl = sdm845_ufsphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
-+ .pcs_tbl = sdm845_ufsphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
-+ .clk_list = sdm845_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sdm845_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+ .no_pcs_sw_reset = true,
-+};
-+
-+static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm6115_ufsphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl),
-+ .tx_tbl = sm6115_ufsphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_tx_tbl),
-+ .rx_tbl = sm6115_ufsphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_rx_tbl),
-+ .pcs_tbl = sm6115_ufsphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl),
-+ .clk_list = sdm845_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm6115_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+
-+ .is_dual_lane_phy = false,
-+ .no_pcs_sw_reset = true,
-+};
-+
-+static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = msm8998_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
-+ .tx_tbl = msm8998_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8998_pcie_tx_tbl),
-+ .rx_tbl = msm8998_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(msm8998_pcie_rx_tbl),
-+ .pcs_tbl = msm8998_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
-+ .clk_list = msm8996_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-+ .reset_list = ipq8074_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = pciephy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+};
-+
-+static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = msm8998_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
-+ .tx_tbl = msm8998_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl),
-+ .rx_tbl = msm8998_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl),
-+ .pcs_tbl = msm8998_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
-+ .clk_list = msm8996_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sm8150_ufsphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl),
-+ .tx_tbl = sm8150_ufsphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx_tbl),
-+ .rx_tbl = sm8150_ufsphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx_tbl),
-+ .pcs_tbl = sm8150_ufsphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl),
-+ .clk_list = sdm845_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8150_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
-+ .tx_tbl = sm8150_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl),
-+ .rx_tbl = sm8150_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl),
-+ .pcs_tbl = sm8150_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
-+ .clk_list = qmp_v4_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sc8180x_qmp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl),
-+ .tx_tbl = sc8180x_qmp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl),
-+ .rx_tbl = sc8180x_qmp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl),
-+ .pcs_tbl = sc8180x_qmp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sc8180x_qmp_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sc8180x_dpphy_cfg = {
-+ .type = PHY_TYPE_DP,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v4_dp_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
-+ .tx_tbl = qmp_v4_dp_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
-+
-+ .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
-+ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
-+ .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
-+ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
-+ .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
-+ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
-+ .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
-+ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
-+
-+ .clk_list = qmp_v3_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-+ .reset_list = sc7180_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+
-+ .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
-+ .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
-+ .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
-+ .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
-+};
-+
-+static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = {
-+ .usb_cfg = &sm8150_usb3phy_cfg,
-+ .dp_cfg = &sc8180x_dpphy_cfg,
-+};
-+
-+static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = sm8150_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),
-+ .rx_tbl = sm8150_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = sm8150_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v4_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3_uniphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
-+ .tx_tbl = sm8250_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl),
-+ .rx_tbl = sm8250_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl),
-+ .pcs_tbl = sm8250_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
-+ .clk_list = qmp_v4_sm8250_usbphy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = sm8250_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),
-+ .rx_tbl = sm8250_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v4_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3_uniphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sm8250_dpphy_cfg = {
-+ .type = PHY_TYPE_DP,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v4_dp_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
-+ .tx_tbl = qmp_v4_dp_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
-+
-+ .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
-+ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
-+ .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
-+ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
-+ .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
-+ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
-+ .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
-+ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
-+
-+ .clk_list = qmp_v4_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3phy_regs_layout,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+
-+ .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
-+ .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
-+ .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
-+ .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
-+};
-+
-+static const struct qmp_phy_combo_cfg sm8250_usb3dpphy_cfg = {
-+ .usb_cfg = &sm8250_usb3phy_cfg,
-+ .dp_cfg = &sm8250_dpphy_cfg,
-+};
-+
-+static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = sdx55_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl),
-+ .rx_tbl = sdx55_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v4_sdx55_usbphy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3_uniphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sdx55_qmp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl),
-+ .tx_tbl = sdx55_qmp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl),
-+ .rx_tbl = sdx55_qmp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl),
-+ .pcs_tbl = sdx55_qmp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sdx55_qmp_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS_4_20,
-+
-+ .is_dual_lane_phy = true,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = sdx65_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl),
-+ .rx_tbl = sdx65_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v4_sdx55_usbphy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8350_usb3_uniphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sm8350_ufsphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
-+ .tx_tbl = sm8350_ufsphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
-+ .rx_tbl = sm8350_ufsphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
-+ .pcs_tbl = sm8350_ufsphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
-+ .clk_list = sdm845_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8150_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
-+ .tx_tbl = sm8350_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl),
-+ .rx_tbl = sm8350_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl),
-+ .pcs_tbl = sm8350_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl),
-+ .clk_list = qmp_v4_sm8250_usbphy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = sm8350_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),
-+ .rx_tbl = sm8350_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v4_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8350_usb3_uniphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sm8350_ufsphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
-+ .tx_tbl = sm8350_ufsphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
-+ .rx_tbl = sm8350_ufsphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
-+ .pcs_tbl = sm8350_ufsphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
-+ .clk_list = sm8450_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8150_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8450_qmp_gen3x1_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl),
-+ .tx_tbl = sm8450_qmp_gen3x1_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl),
-+ .rx_tbl = sm8450_qmp_gen3x1_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl),
-+ .pcs_tbl = sm8450_qmp_gen3x1_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sm8450_qmp_gen4x2_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl),
-+ .tx_tbl = sm8450_qmp_gen4x2_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl),
-+ .rx_tbl = sm8450_qmp_gen4x2_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl),
-+ .pcs_tbl = sm8450_qmp_gen4x2_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS_4_20,
-+
-+ .is_dual_lane_phy = true,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qcm2290_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl),
-+ .tx_tbl = qcm2290_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl),
-+ .rx_tbl = qcm2290_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(qcm2290_usb3_rx_tbl),
-+ .pcs_tbl = qcm2290_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl),
-+ .clk_list = qcm2290_usb3phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qcm2290_usb3phy_clk_l),
-+ .reset_list = qcm2290_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qcm2290_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+};
-+
-+static void qcom_qmp_phy_configure_lane(void __iomem *base,
-+ const unsigned int *regs,
-+ const struct qmp_phy_init_tbl tbl[],
-+ int num,
-+ u8 lane_mask)
-+{
-+ int i;
-+ const struct qmp_phy_init_tbl *t = tbl;
-+
-+ if (!t)
-+ return;
-+
-+ for (i = 0; i < num; i++, t++) {
-+ if (!(t->lane_mask & lane_mask))
-+ continue;
-+
-+ if (t->in_layout)
-+ writel(t->val, base + regs[t->offset]);
-+ else
-+ writel(t->val, base + t->offset);
-+ }
-+}
-+
-+static void qcom_qmp_phy_configure(void __iomem *base,
-+ const unsigned int *regs,
-+ const struct qmp_phy_init_tbl tbl[],
-+ int num)
-+{
-+ qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff);
-+}
-+
-+static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
-+{
-+ struct qcom_qmp *qmp = qphy->qmp;
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *serdes = qphy->serdes;
-+ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-+ const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
-+ int serdes_tbl_num = cfg->serdes_tbl_num;
-+ int ret;
-+
-+ qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
-+ if (cfg->serdes_tbl_sec)
-+ qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
-+ cfg->serdes_tbl_num_sec);
-+
-+ if (cfg->type == PHY_TYPE_DP) {
-+ switch (dp_opts->link_rate) {
-+ case 1620:
-+ qcom_qmp_phy_configure(serdes, cfg->regs,
-+ cfg->serdes_tbl_rbr,
-+ cfg->serdes_tbl_rbr_num);
-+ break;
-+ case 2700:
-+ qcom_qmp_phy_configure(serdes, cfg->regs,
-+ cfg->serdes_tbl_hbr,
-+ cfg->serdes_tbl_hbr_num);
-+ break;
-+ case 5400:
-+ qcom_qmp_phy_configure(serdes, cfg->regs,
-+ cfg->serdes_tbl_hbr2,
-+ cfg->serdes_tbl_hbr2_num);
-+ break;
-+ case 8100:
-+ qcom_qmp_phy_configure(serdes, cfg->regs,
-+ cfg->serdes_tbl_hbr3,
-+ cfg->serdes_tbl_hbr3_num);
-+ break;
-+ default:
-+ /* Other link rates aren't supported */
-+ return -EINVAL;
-+ }
-+ }
-+
-+
-+ if (cfg->has_phy_com_ctrl) {
-+ void __iomem *status;
-+ unsigned int mask, val;
-+
-+ qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
-+ qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
-+ SERDES_START | PCS_START);
-+
-+ status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
-+ mask = cfg->mask_com_pcs_ready;
-+
-+ ret = readl_poll_timeout(status, val, (val & mask), 10,
-+ PHY_INIT_COMPLETE_TIMEOUT);
-+ if (ret) {
-+ dev_err(qmp->dev,
-+ "phy common block init timed-out\n");
-+ return ret;
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy)
-+{
-+ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
-+ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
-+ qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+
-+ /* Turn on BIAS current for PHY/PLL */
-+ writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
-+ QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
-+ qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
-+
-+ writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+
-+ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
-+ DP_PHY_PD_CTL_LANE_0_1_PWRDN |
-+ DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
-+ DP_PHY_PD_CTL_DP_CLAMP_EN,
-+ qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+
-+ writel(QSERDES_V3_COM_BIAS_EN |
-+ QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
-+ QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL |
-+ QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
-+ qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
-+
-+ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
-+ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-+ writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
-+ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
-+ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
-+ writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
-+ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
-+ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
-+ writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
-+ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
-+ qphy->dp_aux_cfg = 0;
-+
-+ writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
-+ PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
-+ PHY_AUX_REQ_ERR_MASK,
-+ qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
-+}
-+
-+static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = {
-+ { 0x00, 0x0c, 0x15, 0x1a },
-+ { 0x02, 0x0e, 0x16, 0xff },
-+ { 0x02, 0x11, 0xff, 0xff },
-+ { 0x04, 0xff, 0xff, 0xff }
-+};
-+
-+static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = {
-+ { 0x02, 0x12, 0x16, 0x1a },
-+ { 0x09, 0x19, 0x1f, 0xff },
-+ { 0x10, 0x1f, 0xff, 0xff },
-+ { 0x1f, 0xff, 0xff, 0xff }
-+};
-+
-+static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = {
-+ { 0x00, 0x0c, 0x14, 0x19 },
-+ { 0x00, 0x0b, 0x12, 0xff },
-+ { 0x00, 0x0b, 0xff, 0xff },
-+ { 0x04, 0xff, 0xff, 0xff }
-+};
-+
-+static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = {
-+ { 0x08, 0x0f, 0x16, 0x1f },
-+ { 0x11, 0x1e, 0x1f, 0xff },
-+ { 0x19, 0x1f, 0xff, 0xff },
-+ { 0x1f, 0xff, 0xff, 0xff }
-+};
-+
-+static int qcom_qmp_phy_configure_dp_swing(struct qmp_phy *qphy,
-+ unsigned int drv_lvl_reg, unsigned int emp_post_reg)
-+{
-+ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-+ unsigned int v_level = 0, p_level = 0;
-+ u8 voltage_swing_cfg, pre_emphasis_cfg;
-+ int i;
-+
-+ for (i = 0; i < dp_opts->lanes; i++) {
-+ v_level = max(v_level, dp_opts->voltage[i]);
-+ p_level = max(p_level, dp_opts->pre[i]);
-+ }
-+
-+ if (dp_opts->link_rate <= 2700) {
-+ voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level];
-+ pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level];
-+ } else {
-+ voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr3_hbr2[v_level][p_level];
-+ pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr3_hbr2[v_level][p_level];
-+ }
-+
-+ /* TODO: Move check to config check */
-+ if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF)
-+ return -EINVAL;
-+
-+ /* Enable MUX to use Cursor values from these registers */
-+ voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
-+ pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
-+
-+ writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg);
-+ writel(pre_emphasis_cfg, qphy->tx + emp_post_reg);
-+ writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg);
-+ writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg);
-+
-+ return 0;
-+}
-+
-+static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy)
-+{
-+ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-+ u32 bias_en, drvr_en;
-+
-+ if (qcom_qmp_phy_configure_dp_swing(qphy,
-+ QSERDES_V3_TX_TX_DRV_LVL,
-+ QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0)
-+ return;
-+
-+ if (dp_opts->lanes == 1) {
-+ bias_en = 0x3e;
-+ drvr_en = 0x13;
-+ } else {
-+ bias_en = 0x3f;
-+ drvr_en = 0x10;
-+ }
-+
-+ writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN);
-+ writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
-+ writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN);
-+ writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
-+}
-+
-+static bool qcom_qmp_phy_configure_dp_mode(struct qmp_phy *qphy)
-+{
-+ u32 val;
-+ bool reverse = false;
-+
-+ val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
-+ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN;
-+
-+ /*
-+ * TODO: Assume orientation is CC1 for now and two lanes, need to
-+ * use type-c connector to understand orientation and lanes.
-+ *
-+ * Otherwise val changes to be like below if this code understood
-+ * the orientation of the type-c cable.
-+ *
-+ * if (lane_cnt == 4 || orientation == ORIENTATION_CC2)
-+ * val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN;
-+ * if (lane_cnt == 4 || orientation == ORIENTATION_CC1)
-+ * val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
-+ * if (orientation == ORIENTATION_CC2)
-+ * writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
-+ */
-+ val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
-+ writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+
-+ writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE);
-+
-+ return reverse;
-+}
-+
-+static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy)
-+{
-+ const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
-+ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-+ u32 phy_vco_div, status;
-+ unsigned long pixel_freq;
-+
-+ qcom_qmp_phy_configure_dp_mode(qphy);
-+
-+ writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
-+ writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
-+
-+ switch (dp_opts->link_rate) {
-+ case 1620:
-+ phy_vco_div = 0x1;
-+ pixel_freq = 1620000000UL / 2;
-+ break;
-+ case 2700:
-+ phy_vco_div = 0x1;
-+ pixel_freq = 2700000000UL / 2;
-+ break;
-+ case 5400:
-+ phy_vco_div = 0x2;
-+ pixel_freq = 5400000000UL / 4;
-+ break;
-+ case 8100:
-+ phy_vco_div = 0x0;
-+ pixel_freq = 8100000000UL / 6;
-+ break;
-+ default:
-+ /* Other link rates aren't supported */
-+ return -EINVAL;
-+ }
-+ writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV);
-+
-+ clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
-+ clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
-+
-+ writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
-+ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL);
-+
-+ if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS,
-+ status,
-+ ((status & BIT(0)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
-+ status,
-+ ((status & BIT(1)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ udelay(2000);
-+ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
-+ status,
-+ ((status & BIT(1)) > 0),
-+ 500,
-+ 10000);
-+}
-+
-+/*
-+ * We need to calibrate the aux setting here as many times
-+ * as the caller tries
-+ */
-+static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy)
-+{
-+ static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d };
-+ u8 val;
-+
-+ qphy->dp_aux_cfg++;
-+ qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
-+ val = cfg1_settings[qphy->dp_aux_cfg];
-+
-+ writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-+
-+ return 0;
-+}
-+
-+static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy)
-+{
-+ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
-+ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
-+ qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+
-+ /* Turn on BIAS current for PHY/PLL */
-+ writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN);
-+
-+ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
-+ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-+ writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
-+ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
-+ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
-+ writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
-+ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
-+ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
-+ writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
-+ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
-+ qphy->dp_aux_cfg = 0;
-+
-+ writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
-+ PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
-+ PHY_AUX_REQ_ERR_MASK,
-+ qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
-+}
-+
-+static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy)
-+{
-+ /* Program default values before writing proper values */
-+ writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
-+ writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
-+
-+ writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
-+ writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
-+
-+ qcom_qmp_phy_configure_dp_swing(qphy,
-+ QSERDES_V4_TX_TX_DRV_LVL,
-+ QSERDES_V4_TX_TX_EMP_POST1_LVL);
-+}
-+
-+static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy)
-+{
-+ const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
-+ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-+ u32 phy_vco_div, status;
-+ unsigned long pixel_freq;
-+ u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
-+ bool reverse;
-+
-+ writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1);
-+
-+ reverse = qcom_qmp_phy_configure_dp_mode(qphy);
-+
-+ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-+ writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
-+
-+ writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL);
-+ writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL);
-+
-+ switch (dp_opts->link_rate) {
-+ case 1620:
-+ phy_vco_div = 0x1;
-+ pixel_freq = 1620000000UL / 2;
-+ break;
-+ case 2700:
-+ phy_vco_div = 0x1;
-+ pixel_freq = 2700000000UL / 2;
-+ break;
-+ case 5400:
-+ phy_vco_div = 0x2;
-+ pixel_freq = 5400000000UL / 4;
-+ break;
-+ case 8100:
-+ phy_vco_div = 0x0;
-+ pixel_freq = 8100000000UL / 6;
-+ break;
-+ default:
-+ /* Other link rates aren't supported */
-+ return -EINVAL;
-+ }
-+ writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV);
-+
-+ clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
-+ clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
-+
-+ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL);
-+
-+ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS,
-+ status,
-+ ((status & BIT(0)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
-+ status,
-+ ((status & BIT(0)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
-+ status,
-+ ((status & BIT(1)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
-+ status,
-+ ((status & BIT(0)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
-+ status,
-+ ((status & BIT(1)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ /*
-+ * At least for 7nm DP PHY this has to be done after enabling link
-+ * clock.
-+ */
-+
-+ if (dp_opts->lanes == 1) {
-+ bias0_en = reverse ? 0x3e : 0x15;
-+ bias1_en = reverse ? 0x15 : 0x3e;
-+ drvr0_en = reverse ? 0x13 : 0x10;
-+ drvr1_en = reverse ? 0x10 : 0x13;
-+ } else if (dp_opts->lanes == 2) {
-+ bias0_en = reverse ? 0x3f : 0x15;
-+ bias1_en = reverse ? 0x15 : 0x3f;
-+ drvr0_en = 0x10;
-+ drvr1_en = 0x10;
-+ } else {
-+ bias0_en = 0x3f;
-+ bias1_en = 0x3f;
-+ drvr0_en = 0x10;
-+ drvr1_en = 0x10;
-+ }
-+
-+ writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN);
-+ writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
-+ writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN);
-+ writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
-+
-+ writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ udelay(2000);
-+ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
-+ status,
-+ ((status & BIT(1)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV);
-+ writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV);
-+
-+ writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
-+ writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
-+
-+ writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
-+ writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
-+
-+ return 0;
-+}
-+
-+/*
-+ * We need to calibrate the aux setting here as many times
-+ * as the caller tries
-+ */
-+static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy)
-+{
-+ static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d };
-+ u8 val;
-+
-+ qphy->dp_aux_cfg++;
-+ qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
-+ val = cfg1_settings[qphy->dp_aux_cfg];
-+
-+ writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
-+{
-+ const struct phy_configure_opts_dp *dp_opts = &opts->dp;
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+
-+ memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts));
-+ if (qphy->dp_opts.set_voltages) {
-+ cfg->configure_dp_tx(qphy);
-+ qphy->dp_opts.set_voltages = 0;
-+ }
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_dp_phy_calibrate(struct phy *phy)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+
-+ if (cfg->calibrate_dp_phy)
-+ return cfg->calibrate_dp_phy(qphy);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
-+{
-+ struct qcom_qmp *qmp = qphy->qmp;
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *serdes = qphy->serdes;
-+ void __iomem *pcs = qphy->pcs;
-+ void __iomem *dp_com = qmp->dp_com;
-+ int ret, i;
-+
-+ mutex_lock(&qmp->phy_mutex);
-+ if (qmp->init_count++) {
-+ mutex_unlock(&qmp->phy_mutex);
-+ return 0;
-+ }
-+
-+ /* turn on regulator supplies */
-+ ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
-+ if (ret) {
-+ dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
-+ goto err_unlock;
-+ }
-+
-+ for (i = 0; i < cfg->num_resets; i++) {
-+ ret = reset_control_assert(qmp->resets[i]);
-+ if (ret) {
-+ dev_err(qmp->dev, "%s reset assert failed\n",
-+ cfg->reset_list[i]);
-+ goto err_disable_regulators;
-+ }
-+ }
-+
-+ for (i = cfg->num_resets - 1; i >= 0; i--) {
-+ ret = reset_control_deassert(qmp->resets[i]);
-+ if (ret) {
-+ dev_err(qmp->dev, "%s reset deassert failed\n",
-+ qphy->cfg->reset_list[i]);
-+ goto err_assert_reset;
-+ }
-+ }
-+
-+ ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
-+ if (ret)
-+ goto err_assert_reset;
-+
-+ if (cfg->has_phy_dp_com_ctrl) {
-+ qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
-+ SW_PWRDN);
-+ /* override hardware control for reset of qmp phy */
-+ qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
-+ SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
-+ SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
-+
-+ /* Default type-c orientation, i.e CC1 */
-+ qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02);
-+
-+ qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
-+ USB3_MODE | DP_MODE);
-+
-+ /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
-+ qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
-+ SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
-+ SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
-+
-+ qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
-+ qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
-+ }
-+
-+ if (cfg->has_phy_com_ctrl) {
-+ qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
-+ SW_PWRDN);
-+ } else {
-+ if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
-+ qphy_setbits(pcs,
-+ cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
-+ cfg->pwrdn_ctrl);
-+ else
-+ qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
-+ cfg->pwrdn_ctrl);
-+ }
-+
-+ mutex_unlock(&qmp->phy_mutex);
-+
-+ return 0;
-+
-+err_assert_reset:
-+ while (++i < cfg->num_resets)
-+ reset_control_assert(qmp->resets[i]);
-+err_disable_regulators:
-+ regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
-+err_unlock:
-+ mutex_unlock(&qmp->phy_mutex);
-+
-+ return ret;
-+}
-+
-+static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy)
-+{
-+ struct qcom_qmp *qmp = qphy->qmp;
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *serdes = qphy->serdes;
-+ int i = cfg->num_resets;
-+
-+ mutex_lock(&qmp->phy_mutex);
-+ if (--qmp->init_count) {
-+ mutex_unlock(&qmp->phy_mutex);
-+ return 0;
-+ }
-+
-+ reset_control_assert(qmp->ufs_reset);
-+ if (cfg->has_phy_com_ctrl) {
-+ qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
-+ SERDES_START | PCS_START);
-+ qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
-+ SW_RESET);
-+ qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
-+ SW_PWRDN);
-+ }
-+
-+ while (--i >= 0)
-+ reset_control_assert(qmp->resets[i]);
-+
-+ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
-+
-+ regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
-+
-+ mutex_unlock(&qmp->phy_mutex);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_init(struct phy *phy)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ struct qcom_qmp *qmp = qphy->qmp;
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ int ret;
-+ dev_vdbg(qmp->dev, "Initializing QMP phy\n");
-+
-+ if (cfg->no_pcs_sw_reset) {
-+ /*
-+ * Get UFS reset, which is delayed until now to avoid a
-+ * circular dependency where UFS needs its PHY, but the PHY
-+ * needs this UFS reset.
-+ */
-+ if (!qmp->ufs_reset) {
-+ qmp->ufs_reset =
-+ devm_reset_control_get_exclusive(qmp->dev,
-+ "ufsphy");
-+
-+ if (IS_ERR(qmp->ufs_reset)) {
-+ ret = PTR_ERR(qmp->ufs_reset);
-+ dev_err(qmp->dev,
-+ "failed to get UFS reset: %d\n",
-+ ret);
-+
-+ qmp->ufs_reset = NULL;
-+ return ret;
-+ }
-+ }
-+
-+ ret = reset_control_assert(qmp->ufs_reset);
-+ if (ret)
-+ return ret;
-+ }
-+
-+ ret = qcom_qmp_phy_com_init(qphy);
-+ if (ret)
-+ return ret;
-+
-+ if (cfg->type == PHY_TYPE_DP)
-+ cfg->dp_aux_init(qphy);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_power_on(struct phy *phy)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ struct qcom_qmp *qmp = qphy->qmp;
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *tx = qphy->tx;
-+ void __iomem *rx = qphy->rx;
-+ void __iomem *pcs = qphy->pcs;
-+ void __iomem *pcs_misc = qphy->pcs_misc;
-+ void __iomem *status;
-+ unsigned int mask, val, ready;
-+ int ret;
-+
-+ qcom_qmp_phy_serdes_init(qphy);
-+
-+ if (cfg->has_lane_rst) {
-+ ret = reset_control_deassert(qphy->lane_rst);
-+ if (ret) {
-+ dev_err(qmp->dev, "lane%d reset deassert failed\n",
-+ qphy->index);
-+ return ret;
-+ }
-+ }
-+
-+ ret = clk_prepare_enable(qphy->pipe_clk);
-+ if (ret) {
-+ dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
-+ goto err_reset_lane;
-+ }
-+
-+ /* Tx, Rx, and PCS configurations */
-+ qcom_qmp_phy_configure_lane(tx, cfg->regs,
-+ cfg->tx_tbl, cfg->tx_tbl_num, 1);
-+ if (cfg->tx_tbl_sec)
-+ qcom_qmp_phy_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
-+ cfg->tx_tbl_num_sec, 1);
-+
-+ /* Configuration for other LANE for USB-DP combo PHY */
-+ if (cfg->is_dual_lane_phy) {
-+ qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
-+ cfg->tx_tbl, cfg->tx_tbl_num, 2);
-+ if (cfg->tx_tbl_sec)
-+ qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
-+ cfg->tx_tbl_sec,
-+ cfg->tx_tbl_num_sec, 2);
-+ }
-+
-+ /* Configure special DP tx tunings */
-+ if (cfg->type == PHY_TYPE_DP)
-+ cfg->configure_dp_tx(qphy);
-+
-+ qcom_qmp_phy_configure_lane(rx, cfg->regs,
-+ cfg->rx_tbl, cfg->rx_tbl_num, 1);
-+ if (cfg->rx_tbl_sec)
-+ qcom_qmp_phy_configure_lane(rx, cfg->regs,
-+ cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1);
-+
-+ if (cfg->is_dual_lane_phy) {
-+ qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
-+ cfg->rx_tbl, cfg->rx_tbl_num, 2);
-+ if (cfg->rx_tbl_sec)
-+ qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
-+ cfg->rx_tbl_sec,
-+ cfg->rx_tbl_num_sec, 2);
-+ }
-+
-+ /* Configure link rate, swing, etc. */
-+ if (cfg->type == PHY_TYPE_DP) {
-+ cfg->configure_dp_phy(qphy);
-+ } else {
-+ qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
-+ if (cfg->pcs_tbl_sec)
-+ qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
-+ cfg->pcs_tbl_num_sec);
-+ }
-+
-+ ret = reset_control_deassert(qmp->ufs_reset);
-+ if (ret)
-+ goto err_disable_pipe_clk;
-+
-+ qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
-+ cfg->pcs_misc_tbl_num);
-+ if (cfg->pcs_misc_tbl_sec)
-+ qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
-+ cfg->pcs_misc_tbl_num_sec);
-+
-+ /*
-+ * Pull out PHY from POWER DOWN state.
-+ * This is active low enable signal to power-down PHY.
-+ */
-+ if(cfg->type == PHY_TYPE_PCIE)
-+ qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
-+
-+ if (cfg->has_pwrdn_delay)
-+ usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
-+
-+ if (cfg->type != PHY_TYPE_DP) {
-+ /* Pull PHY out of reset state */
-+ if (!cfg->no_pcs_sw_reset)
-+ qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
-+ /* start SerDes and Phy-Coding-Sublayer */
-+ qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
-+
-+ if (cfg->type == PHY_TYPE_UFS) {
-+ status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
-+ mask = PCS_READY;
-+ ready = PCS_READY;
-+ } else {
-+ status = pcs + cfg->regs[QPHY_PCS_STATUS];
-+ mask = cfg->phy_status;
-+ ready = 0;
-+ }
-+
-+ ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
-+ PHY_INIT_COMPLETE_TIMEOUT);
-+ if (ret) {
-+ dev_err(qmp->dev, "phy initialization timed-out\n");
-+ goto err_disable_pipe_clk;
-+ }
-+ }
-+ return 0;
-+
-+err_disable_pipe_clk:
-+ clk_disable_unprepare(qphy->pipe_clk);
-+err_reset_lane:
-+ if (cfg->has_lane_rst)
-+ reset_control_assert(qphy->lane_rst);
-+
-+ return ret;
-+}
-+
-+static int qcom_qmp_phy_power_off(struct phy *phy)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+
-+ clk_disable_unprepare(qphy->pipe_clk);
-+
-+ if (cfg->type == PHY_TYPE_DP) {
-+ /* Assert DP PHY power down */
-+ writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+ } else {
-+ /* PHY reset */
-+ if (!cfg->no_pcs_sw_reset)
-+ qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
-+
-+ /* stop SerDes and Phy-Coding-Sublayer */
-+ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
-+
-+ /* Put PHY into POWER DOWN state: active low */
-+ if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
-+ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
-+ cfg->pwrdn_ctrl);
-+ } else {
-+ qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
-+ cfg->pwrdn_ctrl);
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_exit(struct phy *phy)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+
-+ if (cfg->has_lane_rst)
-+ reset_control_assert(qphy->lane_rst);
-+
-+ qcom_qmp_phy_com_exit(qphy);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_enable(struct phy *phy)
-+{
-+ int ret;
-+
-+ ret = qcom_qmp_phy_init(phy);
-+ if (ret)
-+ return ret;
-+
-+ ret = qcom_qmp_phy_power_on(phy);
-+ if (ret)
-+ qcom_qmp_phy_exit(phy);
-+
-+ return ret;
-+}
-+
-+static int qcom_qmp_phy_disable(struct phy *phy)
-+{
-+ int ret;
-+
-+ ret = qcom_qmp_phy_power_off(phy);
-+ if (ret)
-+ return ret;
-+ return qcom_qmp_phy_exit(phy);
-+}
-+
-+static int qcom_qmp_phy_set_mode(struct phy *phy,
-+ enum phy_mode mode, int submode)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+
-+ qphy->mode = mode;
-+
-+ return 0;
-+}
-+
-+static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
-+{
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *pcs = qphy->pcs;
-+ void __iomem *pcs_misc = qphy->pcs_misc;
-+ u32 intr_mask;
-+
-+ if (qphy->mode == PHY_MODE_USB_HOST_SS ||
-+ qphy->mode == PHY_MODE_USB_DEVICE_SS)
-+ intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
-+ else
-+ intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
-+
-+ /* Clear any pending interrupts status */
-+ qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
-+ /* Writing 1 followed by 0 clears the interrupt */
-+ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
-+
-+ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
-+ ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
-+
-+ /* Enable required PHY autonomous mode interrupts */
-+ qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
-+
-+ /* Enable i/o clamp_n for autonomous mode */
-+ if (pcs_misc)
-+ qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
-+}
-+
-+static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
-+{
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *pcs = qphy->pcs;
-+ void __iomem *pcs_misc = qphy->pcs_misc;
-+
-+ /* Disable i/o clamp_n on resume for normal mode */
-+ if (pcs_misc)
-+ qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
-+
-+ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
-+ ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
-+
-+ qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
-+ /* Writing 1 followed by 0 clears the interrupt */
-+ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
-+}
-+
-+static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ struct qmp_phy *qphy = qmp->phys[0];
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+
-+ dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode);
-+
-+ /* Supported only for USB3 PHY and luckily USB3 is the first phy */
-+ if (cfg->type != PHY_TYPE_USB3)
-+ return 0;
-+
-+ if (!qmp->init_count) {
-+ dev_vdbg(dev, "PHY not initialized, bailing out\n");
-+ return 0;
-+ }
-+
-+ qcom_qmp_phy_enable_autonomous_mode(qphy);
-+
-+ clk_disable_unprepare(qphy->pipe_clk);
-+ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
-+
-+ return 0;
-+}
-+
-+static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ struct qmp_phy *qphy = qmp->phys[0];
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ int ret = 0;
-+
-+ dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode);
-+
-+ /* Supported only for USB3 PHY and luckily USB3 is the first phy */
-+ if (cfg->type != PHY_TYPE_USB3)
-+ return 0;
-+
-+ if (!qmp->init_count) {
-+ dev_vdbg(dev, "PHY not initialized, bailing out\n");
-+ return 0;
-+ }
-+
-+ ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
-+ if (ret)
-+ return ret;
-+
-+ ret = clk_prepare_enable(qphy->pipe_clk);
-+ if (ret) {
-+ dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
-+ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
-+ return ret;
-+ }
-+
-+ qcom_qmp_phy_disable_autonomous_mode(qphy);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ int num = cfg->num_vregs;
-+ int i;
-+
-+ qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
-+ if (!qmp->vregs)
-+ return -ENOMEM;
-+
-+ for (i = 0; i < num; i++)
-+ qmp->vregs[i].supply = cfg->vreg_list[i];
-+
-+ return devm_regulator_bulk_get(dev, num, qmp->vregs);
-+}
-+
-+static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ int i;
-+
-+ qmp->resets = devm_kcalloc(dev, cfg->num_resets,
-+ sizeof(*qmp->resets), GFP_KERNEL);
-+ if (!qmp->resets)
-+ return -ENOMEM;
-+
-+ for (i = 0; i < cfg->num_resets; i++) {
-+ struct reset_control *rst;
-+ const char *name = cfg->reset_list[i];
-+
-+ rst = devm_reset_control_get_exclusive(dev, name);
-+ if (IS_ERR(rst)) {
-+ dev_err(dev, "failed to get %s reset\n", name);
-+ return PTR_ERR(rst);
-+ }
-+ qmp->resets[i] = rst;
-+ }
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ int num = cfg->num_clks;
-+ int i;
-+
-+ qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
-+ if (!qmp->clks)
-+ return -ENOMEM;
-+
-+ for (i = 0; i < num; i++)
-+ qmp->clks[i].id = cfg->clk_list[i];
-+
-+ return devm_clk_bulk_get(dev, num, qmp->clks);
-+}
-+
-+static void phy_clk_release_provider(void *res)
-+{
-+ of_clk_del_provider(res);
-+}
-+
-+/*
-+ * Register a fixed rate pipe clock.
-+ *
-+ * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
-+ * controls it. The <s>_pipe_clk coming out of the GCC is requested
-+ * by the PHY driver for its operations.
-+ * We register the <s>_pipe_clksrc here. The gcc driver takes care
-+ * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
-+ * Below picture shows this relationship.
-+ *
-+ * +---------------+
-+ * | PHY block |<<---------------------------------------+
-+ * | | |
-+ * | +-------+ | +-----+ |
-+ * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
-+ * clk | +-------+ | +-----+
-+ * +---------------+
-+ */
-+static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
-+{
-+ struct clk_fixed_rate *fixed;
-+ struct clk_init_data init = { };
-+ int ret;
-+
-+ ret = of_property_read_string(np, "clock-output-names", &init.name);
-+ if (ret) {
-+ dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
-+ return ret;
-+ }
-+
-+ fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
-+ if (!fixed)
-+ return -ENOMEM;
-+
-+ init.ops = &clk_fixed_rate_ops;
-+
-+ /* controllers using QMP phys use 125MHz pipe clock interface */
-+ fixed->fixed_rate = 125000000;
-+ fixed->hw.init = &init;
-+
-+ ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
-+ if (ret)
-+ return ret;
-+
-+ ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
-+ if (ret)
-+ return ret;
-+
-+ /*
-+ * Roll a devm action because the clock provider is the child node, but
-+ * the child node is not actually a device.
-+ */
-+ return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
-+}
-+
-+/*
-+ * Display Port PLL driver block diagram for branch clocks
-+ *
-+ * +------------------------------+
-+ * | DP_VCO_CLK |
-+ * | |
-+ * | +-------------------+ |
-+ * | | (DP PLL/VCO) | |
-+ * | +---------+---------+ |
-+ * | v |
-+ * | +----------+-----------+ |
-+ * | | hsclk_divsel_clk_src | |
-+ * | +----------+-----------+ |
-+ * +------------------------------+
-+ * |
-+ * +---------<---------v------------>----------+
-+ * | |
-+ * +--------v----------------+ |
-+ * | dp_phy_pll_link_clk | |
-+ * | link_clk | |
-+ * +--------+----------------+ |
-+ * | |
-+ * | |
-+ * v v
-+ * Input to DISPCC block |
-+ * for link clk, crypto clk |
-+ * and interface clock |
-+ * |
-+ * |
-+ * +--------<------------+-----------------+---<---+
-+ * | | |
-+ * +----v---------+ +--------v-----+ +--------v------+
-+ * | vco_divided | | vco_divided | | vco_divided |
-+ * | _clk_src | | _clk_src | | _clk_src |
-+ * | | | | | |
-+ * |divsel_six | | divsel_two | | divsel_four |
-+ * +-------+------+ +-----+--------+ +--------+------+
-+ * | | |
-+ * v---->----------v-------------<------v
-+ * |
-+ * +----------+-----------------+
-+ * | dp_phy_pll_vco_div_clk |
-+ * +---------+------------------+
-+ * |
-+ * v
-+ * Input to DISPCC block
-+ * for DP pixel clock
-+ *
-+ */
-+static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw,
-+ struct clk_rate_request *req)
-+{
-+ switch (req->rate) {
-+ case 1620000000UL / 2:
-+ case 2700000000UL / 2:
-+ /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */
-+ return 0;
-+ default:
-+ return -EINVAL;
-+ }
-+}
-+
-+static unsigned long
-+qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
-+{
-+ const struct qmp_phy_dp_clks *dp_clks;
-+ const struct qmp_phy *qphy;
-+ const struct phy_configure_opts_dp *dp_opts;
-+
-+ dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw);
-+ qphy = dp_clks->qphy;
-+ dp_opts = &qphy->dp_opts;
-+
-+ switch (dp_opts->link_rate) {
-+ case 1620:
-+ return 1620000000UL / 2;
-+ case 2700:
-+ return 2700000000UL / 2;
-+ case 5400:
-+ return 5400000000UL / 4;
-+ case 8100:
-+ return 8100000000UL / 6;
-+ default:
-+ return 0;
-+ }
-+}
-+
-+static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = {
-+ .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate,
-+ .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate,
-+};
-+
-+static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw,
-+ struct clk_rate_request *req)
-+{
-+ switch (req->rate) {
-+ case 162000000:
-+ case 270000000:
-+ case 540000000:
-+ case 810000000:
-+ return 0;
-+ default:
-+ return -EINVAL;
-+ }
-+}
-+
-+static unsigned long
-+qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
-+{
-+ const struct qmp_phy_dp_clks *dp_clks;
-+ const struct qmp_phy *qphy;
-+ const struct phy_configure_opts_dp *dp_opts;
-+
-+ dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw);
-+ qphy = dp_clks->qphy;
-+ dp_opts = &qphy->dp_opts;
-+
-+ switch (dp_opts->link_rate) {
-+ case 1620:
-+ case 2700:
-+ case 5400:
-+ case 8100:
-+ return dp_opts->link_rate * 100000;
-+ default:
-+ return 0;
-+ }
-+}
-+
-+static const struct clk_ops qcom_qmp_dp_link_clk_ops = {
-+ .determine_rate = qcom_qmp_dp_link_clk_determine_rate,
-+ .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate,
-+};
-+
-+static struct clk_hw *
-+qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data)
-+{
-+ struct qmp_phy_dp_clks *dp_clks = data;
-+ unsigned int idx = clkspec->args[0];
-+
-+ if (idx >= 2) {
-+ pr_err("%s: invalid index %u\n", __func__, idx);
-+ return ERR_PTR(-EINVAL);
-+ }
-+
-+ if (idx == 0)
-+ return &dp_clks->dp_link_hw;
-+
-+ return &dp_clks->dp_pixel_hw;
-+}
-+
-+static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy,
-+ struct device_node *np)
-+{
-+ struct clk_init_data init = { };
-+ struct qmp_phy_dp_clks *dp_clks;
-+ char name[64];
-+ int ret;
-+
-+ dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL);
-+ if (!dp_clks)
-+ return -ENOMEM;
-+
-+ dp_clks->qphy = qphy;
-+ qphy->dp_clks = dp_clks;
-+
-+ snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev));
-+ init.ops = &qcom_qmp_dp_link_clk_ops;
-+ init.name = name;
-+ dp_clks->dp_link_hw.init = &init;
-+ ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw);
-+ if (ret)
-+ return ret;
-+
-+ snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev));
-+ init.ops = &qcom_qmp_dp_pixel_clk_ops;
-+ init.name = name;
-+ dp_clks->dp_pixel_hw.init = &init;
-+ ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw);
-+ if (ret)
-+ return ret;
-+
-+ ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks);
-+ if (ret)
-+ return ret;
-+
-+ /*
-+ * Roll a devm action because the clock provider is the child node, but
-+ * the child node is not actually a device.
-+ */
-+ return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
-+}
-+
-+static const struct phy_ops qcom_qmp_phy_gen_ops = {
-+ .init = qcom_qmp_phy_enable,
-+ .exit = qcom_qmp_phy_disable,
-+ .set_mode = qcom_qmp_phy_set_mode,
-+ .owner = THIS_MODULE,
-+};
-+
-+static const struct phy_ops qcom_qmp_phy_dp_ops = {
-+ .init = qcom_qmp_phy_init,
-+ .configure = qcom_qmp_dp_phy_configure,
-+ .power_on = qcom_qmp_phy_power_on,
-+ .calibrate = qcom_qmp_dp_phy_calibrate,
-+ .power_off = qcom_qmp_phy_power_off,
-+ .exit = qcom_qmp_phy_exit,
-+ .set_mode = qcom_qmp_phy_set_mode,
-+ .owner = THIS_MODULE,
-+};
-+
-+static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
-+ .power_on = qcom_qmp_phy_enable,
-+ .power_off = qcom_qmp_phy_disable,
-+ .set_mode = qcom_qmp_phy_set_mode,
-+ .owner = THIS_MODULE,
-+};
-+
-+static void qcom_qmp_reset_control_put(void *data)
-+{
-+ reset_control_put(data);
-+}
-+
-+static
-+int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
-+ void __iomem *serdes, const struct qmp_phy_cfg *cfg)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ struct phy *generic_phy;
-+ struct qmp_phy *qphy;
-+ const struct phy_ops *ops;
-+ char prop_name[MAX_PROP_NAME];
-+ int ret;
-+
-+ qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
-+ if (!qphy)
-+ return -ENOMEM;
-+
-+ qphy->cfg = cfg;
-+ qphy->serdes = serdes;
-+ /*
-+ * Get memory resources for each phy lane:
-+ * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
-+ * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
-+ * For single lane PHYs: pcs_misc (optional) -> 3.
-+ */
-+ qphy->tx = of_iomap(np, 0);
-+ if (!qphy->tx)
-+ return -ENOMEM;
-+
-+ qphy->rx = of_iomap(np, 1);
-+ if (!qphy->rx)
-+ return -ENOMEM;
-+
-+ qphy->pcs = of_iomap(np, 2);
-+ if (!qphy->pcs)
-+ return -ENOMEM;
-+
-+ /*
-+ * If this is a dual-lane PHY, then there should be registers for the
-+ * second lane. Some old device trees did not specify this, so fall
-+ * back to old legacy behavior of assuming they can be reached at an
-+ * offset from the first lane.
-+ */
-+ if (cfg->is_dual_lane_phy) {
-+ qphy->tx2 = of_iomap(np, 3);
-+ qphy->rx2 = of_iomap(np, 4);
-+ if (!qphy->tx2 || !qphy->rx2) {
-+ dev_warn(dev,
-+ "Underspecified device tree, falling back to legacy register regions\n");
-+
-+ /* In the old version, pcs_misc is at index 3. */
-+ qphy->pcs_misc = qphy->tx2;
-+ qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE;
-+ qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
-+
-+ } else {
-+ qphy->pcs_misc = of_iomap(np, 5);
-+ }
-+
-+ } else {
-+ qphy->pcs_misc = of_iomap(np, 3);
-+ }
-+
-+ if (!qphy->pcs_misc)
-+ dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
-+
-+ /*
-+ * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3
-+ * based phys, so they essentially have pipe clock. So,
-+ * we return error in case phy is USB3 or PIPE type.
-+ * Otherwise, we initialize pipe clock to NULL for
-+ * all phys that don't need this.
-+ */
-+ snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
-+ qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name);
-+ if (IS_ERR(qphy->pipe_clk)) {
-+ if (cfg->type == PHY_TYPE_PCIE ||
-+ cfg->type == PHY_TYPE_USB3) {
-+ ret = PTR_ERR(qphy->pipe_clk);
-+ if (ret != -EPROBE_DEFER)
-+ dev_err(dev,
-+ "failed to get lane%d pipe_clk, %d\n",
-+ id, ret);
-+ return ret;
-+ }
-+ qphy->pipe_clk = NULL;
-+ }
-+
-+ /* Get lane reset, if any */
-+ if (cfg->has_lane_rst) {
-+ snprintf(prop_name, sizeof(prop_name), "lane%d", id);
-+ qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name);
-+ if (IS_ERR(qphy->lane_rst)) {
-+ dev_err(dev, "failed to get lane%d reset\n", id);
-+ return PTR_ERR(qphy->lane_rst);
-+ }
-+ ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put,
-+ qphy->lane_rst);
-+ if (ret)
-+ return ret;
-+ }
-+
-+ if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE)
-+ ops = &qcom_qmp_pcie_ufs_ops;
-+ else if (cfg->type == PHY_TYPE_DP)
-+ ops = &qcom_qmp_phy_dp_ops;
-+ else
-+ ops = &qcom_qmp_phy_gen_ops;
-+
-+ generic_phy = devm_phy_create(dev, np, ops);
-+ if (IS_ERR(generic_phy)) {
-+ ret = PTR_ERR(generic_phy);
-+ dev_err(dev, "failed to create qphy %d\n", ret);
-+ return ret;
-+ }
-+
-+ qphy->phy = generic_phy;
-+ qphy->index = id;
-+ qphy->qmp = qmp;
-+ qmp->phys[id] = qphy;
-+ phy_set_drvdata(generic_phy, qphy);
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
-+ {
-+ .compatible = "qcom,ipq8074-qmp-usb3-phy",
-+ .data = &ipq8074_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,msm8996-qmp-pcie-phy",
-+ .data = &msm8996_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,msm8996-qmp-ufs-phy",
-+ .data = &msm8996_ufs_cfg,
-+ }, {
-+ .compatible = "qcom,msm8996-qmp-usb3-phy",
-+ .data = &msm8996_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,msm8998-qmp-pcie-phy",
-+ .data = &msm8998_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,msm8998-qmp-ufs-phy",
-+ .data = &sdm845_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,ipq8074-qmp-pcie-phy",
-+ .data = &ipq8074_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,ipq6018-qmp-pcie-phy",
-+ .data = &ipq6018_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,ipq6018-qmp-usb3-phy",
-+ .data = &ipq8074_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sc7180-qmp-usb3-phy",
-+ .data = &sc7180_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
-+ /* It's a combo phy */
-+ }, {
-+ .compatible = "qcom,sc8180x-qmp-pcie-phy",
-+ .data = &sc8180x_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sc8180x-qmp-ufs-phy",
-+ .data = &sm8150_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sc8280xp-qmp-ufs-phy",
-+ .data = &sm8350_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sc8180x-qmp-usb3-phy",
-+ .data = &sm8150_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
-+ /* It's a combo phy */
-+ }, {
-+ .compatible = "qcom,sdm845-qhp-pcie-phy",
-+ .data = &sdm845_qhp_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sdm845-qmp-pcie-phy",
-+ .data = &sdm845_qmp_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sdm845-qmp-usb3-phy",
-+ .data = &qmp_v3_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
-+ .data = &qmp_v3_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sdm845-qmp-ufs-phy",
-+ .data = &sdm845_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,msm8998-qmp-usb3-phy",
-+ .data = &msm8998_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sm6115-qmp-ufs-phy",
-+ .data = &sm6115_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm6350-qmp-ufs-phy",
-+ .data = &sdm845_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8150-qmp-ufs-phy",
-+ .data = &sm8150_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-ufs-phy",
-+ .data = &sm8150_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8150-qmp-usb3-phy",
-+ .data = &sm8150_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8150-qmp-usb3-uni-phy",
-+ .data = &sm8150_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-usb3-phy",
-+ .data = &sm8250_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
-+ /* It's a combo phy */
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-usb3-uni-phy",
-+ .data = &sm8250_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
-+ .data = &sm8250_qmp_gen3x1_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
-+ .data = &sm8250_qmp_gen3x2_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8350-qmp-ufs-phy",
-+ .data = &sm8350_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
-+ .data = &sm8250_qmp_gen3x2_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sdx55-qmp-pcie-phy",
-+ .data = &sdx55_qmp_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sdx55-qmp-usb3-uni-phy",
-+ .data = &sdx55_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sdx65-qmp-usb3-uni-phy",
-+ .data = &sdx65_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8350-qmp-usb3-phy",
-+ .data = &sm8350_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8350-qmp-usb3-uni-phy",
-+ .data = &sm8350_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
-+ .data = &sm8450_qmp_gen3x1_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
-+ .data = &sm8450_qmp_gen4x2_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8450-qmp-ufs-phy",
-+ .data = &sm8450_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8450-qmp-usb3-phy",
-+ .data = &sm8350_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,qcm2290-qmp-usb3-phy",
-+ .data = &qcm2290_usb3phy_cfg,
-+ },
-+ { },
-+};
-+MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
-+
-+static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = {
-+ {
-+ .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
-+ .data = &sc7180_usb3dpphy_cfg,
-+ },
-+ {
-+ .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
-+ .data = &sm8250_usb3dpphy_cfg,
-+ },
-+ {
-+ .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
-+ .data = &sc8180x_usb3dpphy_cfg,
-+ },
-+ { }
-+};
-+
-+static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
-+ SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
-+ qcom_qmp_phy_runtime_resume, NULL)
-+};
-+
-+static int qcom_qmp_phy_probe(struct platform_device *pdev)
-+{
-+ struct qcom_qmp *qmp;
-+ struct device *dev = &pdev->dev;
-+ struct device_node *child;
-+ struct phy_provider *phy_provider;
-+ void __iomem *serdes;
-+ void __iomem *usb_serdes;
-+ void __iomem *dp_serdes = NULL;
-+ const struct qmp_phy_combo_cfg *combo_cfg = NULL;
-+ const struct qmp_phy_cfg *cfg = NULL;
-+ const struct qmp_phy_cfg *usb_cfg = NULL;
-+ const struct qmp_phy_cfg *dp_cfg = NULL;
-+ int num, id, expected_phys;
-+ int ret;
-+
-+ qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
-+ if (!qmp)
-+ return -ENOMEM;
-+
-+ qmp->dev = dev;
-+ dev_set_drvdata(dev, qmp);
-+
-+ /* Get the specific init parameters of QMP phy */
-+ cfg = of_device_get_match_data(dev);
-+ if (!cfg) {
-+ const struct of_device_id *match;
-+
-+ match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev);
-+ if (!match)
-+ return -EINVAL;
-+
-+ combo_cfg = match->data;
-+ if (!combo_cfg)
-+ return -EINVAL;
-+
-+ usb_cfg = combo_cfg->usb_cfg;
-+ cfg = usb_cfg; /* Setup clks and regulators */
-+ }
-+
-+ /* per PHY serdes; usually located at base address */
-+ usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0);
-+ if (IS_ERR(serdes))
-+ return PTR_ERR(serdes);
-+
-+ /* per PHY dp_com; if PHY has dp_com control block */
-+ if (combo_cfg || cfg->has_phy_dp_com_ctrl) {
-+ qmp->dp_com = devm_platform_ioremap_resource(pdev, 1);
-+ if (IS_ERR(qmp->dp_com))
-+ return PTR_ERR(qmp->dp_com);
-+ }
-+
-+ if (combo_cfg) {
-+ /* Only two serdes for combo PHY */
-+ dp_serdes = devm_platform_ioremap_resource(pdev, 2);
-+ if (IS_ERR(dp_serdes))
-+ return PTR_ERR(dp_serdes);
-+
-+ dp_cfg = combo_cfg->dp_cfg;
-+ expected_phys = 2;
-+ } else {
-+ expected_phys = cfg->nlanes;
-+ }
-+
-+ mutex_init(&qmp->phy_mutex);
-+
-+ ret = qcom_qmp_phy_clk_init(dev, cfg);
-+ if (ret)
-+ return ret;
-+
-+ ret = qcom_qmp_phy_reset_init(dev, cfg);
-+ if (ret)
-+ return ret;
-+
-+ ret = qcom_qmp_phy_vreg_init(dev, cfg);
-+ if (ret) {
-+ if (ret != -EPROBE_DEFER)
-+ dev_err(dev, "failed to get regulator supplies: %d\n",
-+ ret);
-+ return ret;
-+ }
-+
-+ num = of_get_available_child_count(dev->of_node);
-+ /* do we have a rogue child node ? */
-+ if (num > expected_phys)
-+ return -EINVAL;
-+
-+ qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
-+ if (!qmp->phys)
-+ return -ENOMEM;
-+
-+ pm_runtime_set_active(dev);
-+ pm_runtime_enable(dev);
-+ /*
-+ * Prevent runtime pm from being ON by default. Users can enable
-+ * it using power/control in sysfs.
-+ */
-+ pm_runtime_forbid(dev);
-+
-+ id = 0;
-+ for_each_available_child_of_node(dev->of_node, child) {
-+ if (of_node_name_eq(child, "dp-phy")) {
-+ cfg = dp_cfg;
-+ serdes = dp_serdes;
-+ } else if (of_node_name_eq(child, "usb3-phy")) {
-+ cfg = usb_cfg;
-+ serdes = usb_serdes;
-+ }
-+
-+ /* Create per-lane phy */
-+ ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg);
-+ if (ret) {
-+ dev_err(dev, "failed to create lane%d phy, %d\n",
-+ id, ret);
-+ goto err_node_put;
-+ }
-+
-+ /*
-+ * Register the pipe clock provided by phy.
-+ * See function description to see details of this pipe clock.
-+ */
-+ if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) {
-+ ret = phy_pipe_clk_register(qmp, child);
-+ if (ret) {
-+ dev_err(qmp->dev,
-+ "failed to register pipe clock source\n");
-+ goto err_node_put;
-+ }
-+ } else if (cfg->type == PHY_TYPE_DP) {
-+ ret = phy_dp_clks_register(qmp, qmp->phys[id], child);
-+ if (ret) {
-+ dev_err(qmp->dev,
-+ "failed to register DP clock source\n");
-+ goto err_node_put;
-+ }
-+ }
-+ id++;
-+ }
-+
-+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
-+ if (!IS_ERR(phy_provider))
-+ dev_info(dev, "Registered Qcom-QMP phy\n");
-+ else
-+ pm_runtime_disable(dev);
-+
-+ return PTR_ERR_OR_ZERO(phy_provider);
-+
-+err_node_put:
-+ pm_runtime_disable(dev);
-+ of_node_put(child);
-+ return ret;
-+}
-+
-+static struct platform_driver qcom_qmp_phy_driver = {
-+ .probe = qcom_qmp_phy_probe,
-+ .driver = {
-+ .name = "qcom-qmp-phy",
-+ .pm = &qcom_qmp_phy_pm_ops,
-+ .of_match_table = qcom_qmp_phy_of_match_table,
-+ },
-+};
-+
-+module_platform_driver(qcom_qmp_phy_driver);
-+
-+MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
-+MODULE_DESCRIPTION("Qualcomm QMP PHY driver");
-+MODULE_LICENSE("GPL v2");
-diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
-new file mode 100644
-index 000000000000..c7309e981bfb
---- /dev/null
-+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
-@@ -0,0 +1,6350 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/clk-provider.h>
-+#include <linux/delay.h>
-+#include <linux/err.h>
-+#include <linux/io.h>
-+#include <linux/iopoll.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/of_device.h>
-+#include <linux/of_address.h>
-+#include <linux/phy/phy.h>
-+#include <linux/platform_device.h>
-+#include <linux/regulator/consumer.h>
-+#include <linux/reset.h>
-+#include <linux/slab.h>
-+
-+#include <dt-bindings/phy/phy.h>
-+
-+#include "phy-qcom-qmp.h"
-+
-+/* QPHY_SW_RESET bit */
-+#define SW_RESET BIT(0)
-+/* QPHY_POWER_DOWN_CONTROL */
-+#define SW_PWRDN BIT(0)
-+#define REFCLK_DRV_DSBL BIT(1)
-+/* QPHY_START_CONTROL bits */
-+#define SERDES_START BIT(0)
-+#define PCS_START BIT(1)
-+#define PLL_READY_GATE_EN BIT(3)
-+/* QPHY_PCS_STATUS bit */
-+#define PHYSTATUS BIT(6)
-+#define PHYSTATUS_4_20 BIT(7)
-+/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */
-+#define PCS_READY BIT(0)
-+
-+/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
-+/* DP PHY soft reset */
-+#define SW_DPPHY_RESET BIT(0)
-+/* mux to select DP PHY reset control, 0:HW control, 1: software reset */
-+#define SW_DPPHY_RESET_MUX BIT(1)
-+/* USB3 PHY soft reset */
-+#define SW_USB3PHY_RESET BIT(2)
-+/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
-+#define SW_USB3PHY_RESET_MUX BIT(3)
-+
-+/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
-+#define USB3_MODE BIT(0) /* enables USB3 mode */
-+#define DP_MODE BIT(1) /* enables DP mode */
-+
-+/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
-+#define ARCVR_DTCT_EN BIT(0)
-+#define ALFPS_DTCT_EN BIT(1)
-+#define ARCVR_DTCT_EVENT_SEL BIT(4)
-+
-+/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
-+#define IRQ_CLEAR BIT(0)
-+
-+/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
-+#define RCVR_DETECT BIT(0)
-+
-+/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
-+#define CLAMP_EN BIT(0) /* enables i/o clamp_n */
-+
-+#define PHY_INIT_COMPLETE_TIMEOUT 10000
-+#define POWER_DOWN_DELAY_US_MIN 10
-+#define POWER_DOWN_DELAY_US_MAX 11
-+
-+#define MAX_PROP_NAME 32
-+
-+/* Define the assumed distance between lanes for underspecified device trees. */
-+#define QMP_PHY_LEGACY_LANE_STRIDE 0x400
-+
-+struct qmp_phy_init_tbl {
-+ unsigned int offset;
-+ unsigned int val;
-+ /*
-+ * register part of layout ?
-+ * if yes, then offset gives index in the reg-layout
-+ */
-+ bool in_layout;
-+ /*
-+ * mask of lanes for which this register is written
-+ * for cases when second lane needs different values
-+ */
-+ u8 lane_mask;
-+};
-+
-+#define QMP_PHY_INIT_CFG(o, v) \
-+ { \
-+ .offset = o, \
-+ .val = v, \
-+ .lane_mask = 0xff, \
-+ }
-+
-+#define QMP_PHY_INIT_CFG_L(o, v) \
-+ { \
-+ .offset = o, \
-+ .val = v, \
-+ .in_layout = true, \
-+ .lane_mask = 0xff, \
-+ }
-+
-+#define QMP_PHY_INIT_CFG_LANE(o, v, l) \
-+ { \
-+ .offset = o, \
-+ .val = v, \
-+ .lane_mask = l, \
-+ }
-+
-+/* set of registers with offsets different per-PHY */
-+enum qphy_reg_layout {
-+ /* Common block control registers */
-+ QPHY_COM_SW_RESET,
-+ QPHY_COM_POWER_DOWN_CONTROL,
-+ QPHY_COM_START_CONTROL,
-+ QPHY_COM_PCS_READY_STATUS,
-+ /* PCS registers */
-+ QPHY_PLL_LOCK_CHK_DLY_TIME,
-+ QPHY_FLL_CNTRL1,
-+ QPHY_FLL_CNTRL2,
-+ QPHY_FLL_CNT_VAL_L,
-+ QPHY_FLL_CNT_VAL_H_TOL,
-+ QPHY_FLL_MAN_CODE,
-+ QPHY_SW_RESET,
-+ QPHY_START_CTRL,
-+ QPHY_PCS_READY_STATUS,
-+ QPHY_PCS_STATUS,
-+ QPHY_PCS_AUTONOMOUS_MODE_CTRL,
-+ QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
-+ QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
-+ QPHY_PCS_POWER_DOWN_CONTROL,
-+ /* PCS_MISC registers */
-+ QPHY_PCS_MISC_TYPEC_CTRL,
-+ /* Keep last to ensure regs_layout arrays are properly initialized */
-+ QPHY_LAYOUT_SIZE
-+};
-+
-+static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_START_CTRL] = 0x00,
-+ [QPHY_PCS_READY_STATUS] = 0x168,
-+};
-+
-+static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x44,
-+ [QPHY_PCS_STATUS] = 0x14,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
-+};
-+
-+static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_COM_SW_RESET] = 0x400,
-+ [QPHY_COM_POWER_DOWN_CONTROL] = 0x404,
-+ [QPHY_COM_START_CONTROL] = 0x408,
-+ [QPHY_COM_PCS_READY_STATUS] = 0x448,
-+ [QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8,
-+ [QPHY_FLL_CNTRL1] = 0xc4,
-+ [QPHY_FLL_CNTRL2] = 0xc8,
-+ [QPHY_FLL_CNT_VAL_L] = 0xcc,
-+ [QPHY_FLL_CNT_VAL_H_TOL] = 0xd0,
-+ [QPHY_FLL_MAN_CODE] = 0xd4,
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_STATUS] = 0x174,
-+};
-+
-+static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_FLL_CNTRL1] = 0xc0,
-+ [QPHY_FLL_CNTRL2] = 0xc4,
-+ [QPHY_FLL_CNT_VAL_L] = 0xc8,
-+ [QPHY_FLL_CNT_VAL_H_TOL] = 0xcc,
-+ [QPHY_FLL_MAN_CODE] = 0xd0,
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_STATUS] = 0x17c,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
-+};
-+
-+static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_STATUS] = 0x174,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
-+};
-+
-+static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_STATUS] = 0x174,
-+};
-+
-+static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_STATUS] = 0x2ac,
-+};
-+
-+static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x44,
-+ [QPHY_PCS_STATUS] = 0x14,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314,
-+};
-+
-+static const unsigned int qmp_v4_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x44,
-+ [QPHY_PCS_STATUS] = 0x14,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x608,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x614,
-+};
-+
-+static const unsigned int sm8350_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x44,
-+ [QPHY_PCS_STATUS] = 0x14,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x1008,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x1014,
-+};
-+
-+static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0xd8,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc,
-+ [QPHY_PCS_STATUS] = 0x174,
-+ [QPHY_PCS_MISC_TYPEC_CTRL] = 0x00,
-+};
-+
-+static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_START_CTRL] = 0x00,
-+ [QPHY_PCS_READY_STATUS] = 0x160,
-+};
-+
-+static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_START_CTRL] = 0x00,
-+ [QPHY_PCS_READY_STATUS] = 0x168,
-+};
-+
-+static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x44,
-+ [QPHY_PCS_STATUS] = 0x14,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
-+};
-+
-+static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START,
-+ [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS,
-+ [QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET,
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
-+ /* PLL and Loop filter settings */
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-+ /* SSC settings */
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
-+ QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
-+
-+ QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
-+
-+ QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
-+ QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
-+ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
-+ /* PLL and Loop filter settings */
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-+ /* SSC settings */
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
-+ /* FLL settings */
-+ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03),
-+ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02),
-+ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42),
-+ QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
-+
-+ /* Lock Det settings */
-+ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x61),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d),
-+ QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10),
-+ QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_PRE, 0x00),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_POST, 0x58),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
-+ QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
-+ QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
-+ QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
-+ QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
-+ QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
-+ QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
-+ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
-+ QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
-+ QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = {
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
-+ /* FLL settings */
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+
-+ /* Lock Det settings */
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
-+ /* FLL settings */
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+
-+ /* Lock Det settings */
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
-+};
-+
-+static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
-+
-+ /* Rate B */
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),
-+};
-+
-+static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B),
-+};
-+
-+static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_RX_PWM_GEAR_BAND, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_CTRL2, 0x6d),
-+ QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_DRV_LVL, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_DRV_LVL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
-+ QMP_PHY_INIT_CFG(QPHY_RX_SYM_RESYNC_CTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
-+ QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
-+
-+ /* Rate B */
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
-+
-+ /* Rate B */
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
-+
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
-+ /* Lock Det settings */
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20),
-+};
-+
-+static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
-+};
-+
-+static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5),
-+};
-+
-+static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
-+};
-+
-+static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),
-+};
-+
-+static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
-+
-+ /* Rate B */
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+};
-+
-+static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01),
-+};
-+
-+static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
-+
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05),
-+
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
-+
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
-+
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
-+};
-+
-+/* Register names should be validated, they might be different for this PHY */
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
-+};
-+
-+struct qmp_phy;
-+
-+/* struct qmp_phy_cfg - per-PHY initialization config */
-+struct qmp_phy_cfg {
-+ /* phy-type - PCIE/UFS/USB */
-+ unsigned int type;
-+ /* number of lanes provided by phy */
-+ int nlanes;
-+
-+ /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
-+ const struct qmp_phy_init_tbl *serdes_tbl;
-+ int serdes_tbl_num;
-+ const struct qmp_phy_init_tbl *serdes_tbl_sec;
-+ int serdes_tbl_num_sec;
-+ const struct qmp_phy_init_tbl *tx_tbl;
-+ int tx_tbl_num;
-+ const struct qmp_phy_init_tbl *tx_tbl_sec;
-+ int tx_tbl_num_sec;
-+ const struct qmp_phy_init_tbl *rx_tbl;
-+ int rx_tbl_num;
-+ const struct qmp_phy_init_tbl *rx_tbl_sec;
-+ int rx_tbl_num_sec;
-+ const struct qmp_phy_init_tbl *pcs_tbl;
-+ int pcs_tbl_num;
-+ const struct qmp_phy_init_tbl *pcs_tbl_sec;
-+ int pcs_tbl_num_sec;
-+ const struct qmp_phy_init_tbl *pcs_misc_tbl;
-+ int pcs_misc_tbl_num;
-+ const struct qmp_phy_init_tbl *pcs_misc_tbl_sec;
-+ int pcs_misc_tbl_num_sec;
-+
-+ /* Init sequence for DP PHY block link rates */
-+ const struct qmp_phy_init_tbl *serdes_tbl_rbr;
-+ int serdes_tbl_rbr_num;
-+ const struct qmp_phy_init_tbl *serdes_tbl_hbr;
-+ int serdes_tbl_hbr_num;
-+ const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
-+ int serdes_tbl_hbr2_num;
-+ const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
-+ int serdes_tbl_hbr3_num;
-+
-+ /* DP PHY callbacks */
-+ int (*configure_dp_phy)(struct qmp_phy *qphy);
-+ void (*configure_dp_tx)(struct qmp_phy *qphy);
-+ int (*calibrate_dp_phy)(struct qmp_phy *qphy);
-+ void (*dp_aux_init)(struct qmp_phy *qphy);
-+
-+ /* clock ids to be requested */
-+ const char * const *clk_list;
-+ int num_clks;
-+ /* resets to be requested */
-+ const char * const *reset_list;
-+ int num_resets;
-+ /* regulators to be requested */
-+ const char * const *vreg_list;
-+ int num_vregs;
-+
-+ /* array of registers with different offsets */
-+ const unsigned int *regs;
-+
-+ unsigned int start_ctrl;
-+ unsigned int pwrdn_ctrl;
-+ unsigned int mask_com_pcs_ready;
-+ /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
-+ unsigned int phy_status;
-+
-+ /* true, if PHY has a separate PHY_COM control block */
-+ bool has_phy_com_ctrl;
-+ /* true, if PHY has a reset for individual lanes */
-+ bool has_lane_rst;
-+ /* true, if PHY needs delay after POWER_DOWN */
-+ bool has_pwrdn_delay;
-+ /* power_down delay in usec */
-+ int pwrdn_delay_min;
-+ int pwrdn_delay_max;
-+
-+ /* true, if PHY has a separate DP_COM control block */
-+ bool has_phy_dp_com_ctrl;
-+ /* true, if PHY has secondary tx/rx lanes to be configured */
-+ bool is_dual_lane_phy;
-+
-+ /* true, if PCS block has no separate SW_RESET register */
-+ bool no_pcs_sw_reset;
-+};
-+
-+struct qmp_phy_combo_cfg {
-+ const struct qmp_phy_cfg *usb_cfg;
-+ const struct qmp_phy_cfg *dp_cfg;
-+};
-+
-+/**
-+ * struct qmp_phy - per-lane phy descriptor
-+ *
-+ * @phy: generic phy
-+ * @cfg: phy specific configuration
-+ * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
-+ * @tx: iomapped memory space for lane's tx
-+ * @rx: iomapped memory space for lane's rx
-+ * @pcs: iomapped memory space for lane's pcs
-+ * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
-+ * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
-+ * @pcs_misc: iomapped memory space for lane's pcs_misc
-+ * @pipe_clk: pipe clock
-+ * @index: lane index
-+ * @qmp: QMP phy to which this lane belongs
-+ * @lane_rst: lane's reset controller
-+ * @mode: current PHY mode
-+ * @dp_aux_cfg: Display port aux config
-+ * @dp_opts: Display port optional config
-+ * @dp_clks: Display port clocks
-+ */
-+struct qmp_phy {
-+ struct phy *phy;
-+ const struct qmp_phy_cfg *cfg;
-+ void __iomem *serdes;
-+ void __iomem *tx;
-+ void __iomem *rx;
-+ void __iomem *pcs;
-+ void __iomem *tx2;
-+ void __iomem *rx2;
-+ void __iomem *pcs_misc;
-+ struct clk *pipe_clk;
-+ unsigned int index;
-+ struct qcom_qmp *qmp;
-+ struct reset_control *lane_rst;
-+ enum phy_mode mode;
-+ unsigned int dp_aux_cfg;
-+ struct phy_configure_opts_dp dp_opts;
-+ struct qmp_phy_dp_clks *dp_clks;
-+};
-+
-+struct qmp_phy_dp_clks {
-+ struct qmp_phy *qphy;
-+ struct clk_hw dp_link_hw;
-+ struct clk_hw dp_pixel_hw;
-+};
-+
-+/**
-+ * struct qcom_qmp - structure holding QMP phy block attributes
-+ *
-+ * @dev: device
-+ * @dp_com: iomapped memory space for phy's dp_com control block
-+ *
-+ * @clks: array of clocks required by phy
-+ * @resets: array of resets required by phy
-+ * @vregs: regulator supplies bulk data
-+ *
-+ * @phys: array of per-lane phy descriptors
-+ * @phy_mutex: mutex lock for PHY common block initialization
-+ * @init_count: phy common block initialization count
-+ * @ufs_reset: optional UFS PHY reset handle
-+ */
-+struct qcom_qmp {
-+ struct device *dev;
-+ void __iomem *dp_com;
-+
-+ struct clk_bulk_data *clks;
-+ struct reset_control **resets;
-+ struct regulator_bulk_data *vregs;
-+
-+ struct qmp_phy **phys;
-+
-+ struct mutex phy_mutex;
-+ int init_count;
-+
-+ struct reset_control *ufs_reset;
-+};
-+
-+static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy);
-+static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy);
-+static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy);
-+static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy);
-+
-+static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy);
-+static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy);
-+static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy);
-+static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy);
-+
-+static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
-+{
-+ u32 reg;
-+
-+ reg = readl(base + offset);
-+ reg |= val;
-+ writel(reg, base + offset);
-+
-+ /* ensure that above write is through */
-+ readl(base + offset);
-+}
-+
-+static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
-+{
-+ u32 reg;
-+
-+ reg = readl(base + offset);
-+ reg &= ~val;
-+ writel(reg, base + offset);
-+
-+ /* ensure that above write is through */
-+ readl(base + offset);
-+}
-+
-+/* list of clocks required by phy */
-+static const char * const msm8996_phy_clk_l[] = {
-+ "aux", "cfg_ahb", "ref",
-+};
-+
-+static const char * const msm8996_ufs_phy_clk_l[] = {
-+ "ref",
-+};
-+
-+static const char * const qmp_v3_phy_clk_l[] = {
-+ "aux", "cfg_ahb", "ref", "com_aux",
-+};
-+
-+static const char * const sdm845_pciephy_clk_l[] = {
-+ "aux", "cfg_ahb", "ref", "refgen",
-+};
-+
-+static const char * const qmp_v4_phy_clk_l[] = {
-+ "aux", "ref_clk_src", "ref", "com_aux",
-+};
-+
-+/* the primary usb3 phy on sm8250 doesn't have a ref clock */
-+static const char * const qmp_v4_sm8250_usbphy_clk_l[] = {
-+ "aux", "ref_clk_src", "com_aux"
-+};
-+
-+static const char * const sm8450_ufs_phy_clk_l[] = {
-+ "qref", "ref", "ref_aux",
-+};
-+
-+static const char * const sdm845_ufs_phy_clk_l[] = {
-+ "ref", "ref_aux",
-+};
-+
-+/* usb3 phy on sdx55 doesn't have com_aux clock */
-+static const char * const qmp_v4_sdx55_usbphy_clk_l[] = {
-+ "aux", "cfg_ahb", "ref"
-+};
-+
-+static const char * const qcm2290_usb3phy_clk_l[] = {
-+ "cfg_ahb", "ref", "com_aux",
-+};
-+
-+/* list of resets */
-+static const char * const msm8996_pciephy_reset_l[] = {
-+ "phy", "common", "cfg",
-+};
-+
-+static const char * const msm8996_usb3phy_reset_l[] = {
-+ "phy", "common",
-+};
-+
-+static const char * const sc7180_usb3phy_reset_l[] = {
-+ "phy",
-+};
-+
-+static const char * const qcm2290_usb3phy_reset_l[] = {
-+ "phy_phy", "phy",
-+};
-+
-+static const char * const sdm845_pciephy_reset_l[] = {
-+ "phy",
-+};
-+
-+/* list of regulators */
-+static const char * const qmp_phy_vreg_l[] = {
-+ "vdda-phy", "vdda-pll",
-+};
-+
-+static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = ipq8074_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
-+ .tx_tbl = msm8996_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
-+ .rx_tbl = ipq8074_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
-+ .pcs_tbl = ipq8074_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
-+ .clk_list = msm8996_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+};
-+
-+static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 3,
-+
-+ .serdes_tbl = msm8996_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
-+ .tx_tbl = msm8996_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8996_pcie_tx_tbl),
-+ .rx_tbl = msm8996_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(msm8996_pcie_rx_tbl),
-+ .pcs_tbl = msm8996_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
-+ .clk_list = msm8996_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-+ .reset_list = msm8996_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = pciephy_regs_layout,
-+
-+ .start_ctrl = PCS_START | PLL_READY_GATE_EN,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .mask_com_pcs_ready = PCS_READY,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_phy_com_ctrl = true,
-+ .has_lane_rst = true,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg msm8996_ufs_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = msm8996_ufs_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(msm8996_ufs_serdes_tbl),
-+ .tx_tbl = msm8996_ufs_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8996_ufs_tx_tbl),
-+ .rx_tbl = msm8996_ufs_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(msm8996_ufs_rx_tbl),
-+
-+ .clk_list = msm8996_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
-+
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+
-+ .regs = msm8996_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .no_pcs_sw_reset = true,
-+};
-+
-+static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = msm8996_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
-+ .tx_tbl = msm8996_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
-+ .rx_tbl = msm8996_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl),
-+ .pcs_tbl = msm8996_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
-+ .clk_list = msm8996_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+};
-+
-+static const char * const ipq8074_pciephy_clk_l[] = {
-+ "aux", "cfg_ahb",
-+};
-+/* list of resets */
-+static const char * const ipq8074_pciephy_reset_l[] = {
-+ "phy", "common",
-+};
-+
-+static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = ipq8074_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
-+ .tx_tbl = ipq8074_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
-+ .rx_tbl = ipq8074_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
-+ .pcs_tbl = ipq8074_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
-+ .clk_list = ipq8074_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
-+ .reset_list = ipq8074_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
-+ .vreg_list = NULL,
-+ .num_vregs = 0,
-+ .regs = pciephy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_phy_com_ctrl = false,
-+ .has_lane_rst = false,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = ipq6018_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl),
-+ .tx_tbl = ipq6018_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl),
-+ .rx_tbl = ipq6018_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
-+ .pcs_tbl = ipq6018_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
-+ .clk_list = ipq8074_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
-+ .reset_list = ipq8074_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
-+ .vreg_list = NULL,
-+ .num_vregs = 0,
-+ .regs = ipq_pciephy_gen3_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+
-+ .has_phy_com_ctrl = false,
-+ .has_lane_rst = false,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sdm845_qmp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
-+ .tx_tbl = sdm845_qmp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),
-+ .rx_tbl = sdm845_qmp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),
-+ .pcs_tbl = sdm845_qmp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sdm845_qmp_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sdm845_qmp_pciephy_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sdm845_qhp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
-+ .tx_tbl = sdm845_qhp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
-+ .rx_tbl = sdm845_qhp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl),
-+ .pcs_tbl = sdm845_qhp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sdm845_qhp_pciephy_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
-+ .serdes_tbl_sec = sm8250_qmp_gen3x1_pcie_serdes_tbl,
-+ .serdes_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
-+ .tx_tbl = sm8250_qmp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
-+ .rx_tbl = sm8250_qmp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
-+ .rx_tbl_sec = sm8250_qmp_gen3x1_pcie_rx_tbl,
-+ .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),
-+ .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
-+ .pcs_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_tbl,
-+ .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
-+ .pcs_misc_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
-+ .tx_tbl = sm8250_qmp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
-+ .tx_tbl_sec = sm8250_qmp_gen3x2_pcie_tx_tbl,
-+ .tx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),
-+ .rx_tbl = sm8250_qmp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
-+ .rx_tbl_sec = sm8250_qmp_gen3x2_pcie_rx_tbl,
-+ .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl),
-+ .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
-+ .pcs_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_tbl,
-+ .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
-+ .pcs_misc_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v3_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
-+ .tx_tbl = qmp_v3_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
-+ .rx_tbl = qmp_v3_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
-+ .pcs_tbl = qmp_v3_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
-+ .clk_list = qmp_v3_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v3_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
-+ .tx_tbl = qmp_v3_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
-+ .rx_tbl = qmp_v3_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
-+ .pcs_tbl = qmp_v3_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
-+ .clk_list = qmp_v3_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-+ .reset_list = sc7180_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sc7180_dpphy_cfg = {
-+ .type = PHY_TYPE_DP,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v3_dp_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
-+ .tx_tbl = qmp_v3_dp_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
-+
-+ .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr,
-+ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
-+ .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr,
-+ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
-+ .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2,
-+ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
-+ .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3,
-+ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
-+
-+ .clk_list = qmp_v3_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-+ .reset_list = sc7180_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+
-+ .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init,
-+ .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx,
-+ .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy,
-+ .calibrate_dp_phy = qcom_qmp_v3_dp_phy_calibrate,
-+};
-+
-+static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = {
-+ .usb_cfg = &sc7180_usb3phy_cfg,
-+ .dp_cfg = &sc7180_dpphy_cfg,
-+};
-+
-+static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
-+ .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v3_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sdm845_ufsphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
-+ .tx_tbl = sdm845_ufsphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
-+ .rx_tbl = sdm845_ufsphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
-+ .pcs_tbl = sdm845_ufsphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
-+ .clk_list = sdm845_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sdm845_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+ .no_pcs_sw_reset = true,
-+};
-+
-+static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm6115_ufsphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl),
-+ .tx_tbl = sm6115_ufsphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_tx_tbl),
-+ .rx_tbl = sm6115_ufsphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_rx_tbl),
-+ .pcs_tbl = sm6115_ufsphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl),
-+ .clk_list = sdm845_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm6115_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+
-+ .is_dual_lane_phy = false,
-+ .no_pcs_sw_reset = true,
-+};
-+
-+static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = msm8998_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
-+ .tx_tbl = msm8998_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8998_pcie_tx_tbl),
-+ .rx_tbl = msm8998_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(msm8998_pcie_rx_tbl),
-+ .pcs_tbl = msm8998_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
-+ .clk_list = msm8996_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-+ .reset_list = ipq8074_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = pciephy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+};
-+
-+static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = msm8998_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
-+ .tx_tbl = msm8998_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl),
-+ .rx_tbl = msm8998_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl),
-+ .pcs_tbl = msm8998_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
-+ .clk_list = msm8996_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sm8150_ufsphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl),
-+ .tx_tbl = sm8150_ufsphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx_tbl),
-+ .rx_tbl = sm8150_ufsphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx_tbl),
-+ .pcs_tbl = sm8150_ufsphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl),
-+ .clk_list = sdm845_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8150_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
-+ .tx_tbl = sm8150_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl),
-+ .rx_tbl = sm8150_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl),
-+ .pcs_tbl = sm8150_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
-+ .clk_list = qmp_v4_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sc8180x_qmp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl),
-+ .tx_tbl = sc8180x_qmp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl),
-+ .rx_tbl = sc8180x_qmp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl),
-+ .pcs_tbl = sc8180x_qmp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sc8180x_qmp_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sc8180x_dpphy_cfg = {
-+ .type = PHY_TYPE_DP,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v4_dp_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
-+ .tx_tbl = qmp_v4_dp_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
-+
-+ .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
-+ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
-+ .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
-+ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
-+ .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
-+ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
-+ .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
-+ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
-+
-+ .clk_list = qmp_v3_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-+ .reset_list = sc7180_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+
-+ .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
-+ .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
-+ .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
-+ .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
-+};
-+
-+static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = {
-+ .usb_cfg = &sm8150_usb3phy_cfg,
-+ .dp_cfg = &sc8180x_dpphy_cfg,
-+};
-+
-+static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = sm8150_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),
-+ .rx_tbl = sm8150_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = sm8150_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v4_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3_uniphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
-+ .tx_tbl = sm8250_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl),
-+ .rx_tbl = sm8250_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl),
-+ .pcs_tbl = sm8250_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
-+ .clk_list = qmp_v4_sm8250_usbphy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = sm8250_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),
-+ .rx_tbl = sm8250_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v4_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3_uniphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sm8250_dpphy_cfg = {
-+ .type = PHY_TYPE_DP,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v4_dp_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
-+ .tx_tbl = qmp_v4_dp_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
-+
-+ .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
-+ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
-+ .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
-+ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
-+ .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
-+ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
-+ .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
-+ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
-+
-+ .clk_list = qmp_v4_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3phy_regs_layout,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+
-+ .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
-+ .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
-+ .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
-+ .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
-+};
-+
-+static const struct qmp_phy_combo_cfg sm8250_usb3dpphy_cfg = {
-+ .usb_cfg = &sm8250_usb3phy_cfg,
-+ .dp_cfg = &sm8250_dpphy_cfg,
-+};
-+
-+static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = sdx55_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl),
-+ .rx_tbl = sdx55_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v4_sdx55_usbphy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3_uniphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sdx55_qmp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl),
-+ .tx_tbl = sdx55_qmp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl),
-+ .rx_tbl = sdx55_qmp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl),
-+ .pcs_tbl = sdx55_qmp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sdx55_qmp_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS_4_20,
-+
-+ .is_dual_lane_phy = true,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = sdx65_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl),
-+ .rx_tbl = sdx65_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v4_sdx55_usbphy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8350_usb3_uniphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sm8350_ufsphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
-+ .tx_tbl = sm8350_ufsphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
-+ .rx_tbl = sm8350_ufsphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
-+ .pcs_tbl = sm8350_ufsphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
-+ .clk_list = sdm845_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8150_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
-+ .tx_tbl = sm8350_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl),
-+ .rx_tbl = sm8350_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl),
-+ .pcs_tbl = sm8350_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl),
-+ .clk_list = qmp_v4_sm8250_usbphy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = sm8350_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),
-+ .rx_tbl = sm8350_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v4_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8350_usb3_uniphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sm8350_ufsphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
-+ .tx_tbl = sm8350_ufsphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
-+ .rx_tbl = sm8350_ufsphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
-+ .pcs_tbl = sm8350_ufsphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
-+ .clk_list = sm8450_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8150_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8450_qmp_gen3x1_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl),
-+ .tx_tbl = sm8450_qmp_gen3x1_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl),
-+ .rx_tbl = sm8450_qmp_gen3x1_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl),
-+ .pcs_tbl = sm8450_qmp_gen3x1_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sm8450_qmp_gen4x2_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl),
-+ .tx_tbl = sm8450_qmp_gen4x2_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl),
-+ .rx_tbl = sm8450_qmp_gen4x2_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl),
-+ .pcs_tbl = sm8450_qmp_gen4x2_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS_4_20,
-+
-+ .is_dual_lane_phy = true,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qcm2290_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl),
-+ .tx_tbl = qcm2290_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl),
-+ .rx_tbl = qcm2290_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(qcm2290_usb3_rx_tbl),
-+ .pcs_tbl = qcm2290_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl),
-+ .clk_list = qcm2290_usb3phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qcm2290_usb3phy_clk_l),
-+ .reset_list = qcm2290_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qcm2290_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+};
-+
-+static void qcom_qmp_phy_configure_lane(void __iomem *base,
-+ const unsigned int *regs,
-+ const struct qmp_phy_init_tbl tbl[],
-+ int num,
-+ u8 lane_mask)
-+{
-+ int i;
-+ const struct qmp_phy_init_tbl *t = tbl;
-+
-+ if (!t)
-+ return;
-+
-+ for (i = 0; i < num; i++, t++) {
-+ if (!(t->lane_mask & lane_mask))
-+ continue;
-+
-+ if (t->in_layout)
-+ writel(t->val, base + regs[t->offset]);
-+ else
-+ writel(t->val, base + t->offset);
-+ }
-+}
-+
-+static void qcom_qmp_phy_configure(void __iomem *base,
-+ const unsigned int *regs,
-+ const struct qmp_phy_init_tbl tbl[],
-+ int num)
-+{
-+ qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff);
-+}
-+
-+static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
-+{
-+ struct qcom_qmp *qmp = qphy->qmp;
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *serdes = qphy->serdes;
-+ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-+ const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
-+ int serdes_tbl_num = cfg->serdes_tbl_num;
-+ int ret;
-+
-+ qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
-+ if (cfg->serdes_tbl_sec)
-+ qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
-+ cfg->serdes_tbl_num_sec);
-+
-+ if (cfg->type == PHY_TYPE_DP) {
-+ switch (dp_opts->link_rate) {
-+ case 1620:
-+ qcom_qmp_phy_configure(serdes, cfg->regs,
-+ cfg->serdes_tbl_rbr,
-+ cfg->serdes_tbl_rbr_num);
-+ break;
-+ case 2700:
-+ qcom_qmp_phy_configure(serdes, cfg->regs,
-+ cfg->serdes_tbl_hbr,
-+ cfg->serdes_tbl_hbr_num);
-+ break;
-+ case 5400:
-+ qcom_qmp_phy_configure(serdes, cfg->regs,
-+ cfg->serdes_tbl_hbr2,
-+ cfg->serdes_tbl_hbr2_num);
-+ break;
-+ case 8100:
-+ qcom_qmp_phy_configure(serdes, cfg->regs,
-+ cfg->serdes_tbl_hbr3,
-+ cfg->serdes_tbl_hbr3_num);
-+ break;
-+ default:
-+ /* Other link rates aren't supported */
-+ return -EINVAL;
-+ }
-+ }
-+
-+
-+ if (cfg->has_phy_com_ctrl) {
-+ void __iomem *status;
-+ unsigned int mask, val;
-+
-+ qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
-+ qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
-+ SERDES_START | PCS_START);
-+
-+ status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
-+ mask = cfg->mask_com_pcs_ready;
-+
-+ ret = readl_poll_timeout(status, val, (val & mask), 10,
-+ PHY_INIT_COMPLETE_TIMEOUT);
-+ if (ret) {
-+ dev_err(qmp->dev,
-+ "phy common block init timed-out\n");
-+ return ret;
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy)
-+{
-+ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
-+ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
-+ qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+
-+ /* Turn on BIAS current for PHY/PLL */
-+ writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
-+ QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
-+ qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
-+
-+ writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+
-+ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
-+ DP_PHY_PD_CTL_LANE_0_1_PWRDN |
-+ DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
-+ DP_PHY_PD_CTL_DP_CLAMP_EN,
-+ qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+
-+ writel(QSERDES_V3_COM_BIAS_EN |
-+ QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
-+ QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL |
-+ QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
-+ qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
-+
-+ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
-+ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-+ writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
-+ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
-+ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
-+ writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
-+ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
-+ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
-+ writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
-+ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
-+ qphy->dp_aux_cfg = 0;
-+
-+ writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
-+ PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
-+ PHY_AUX_REQ_ERR_MASK,
-+ qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
-+}
-+
-+static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = {
-+ { 0x00, 0x0c, 0x15, 0x1a },
-+ { 0x02, 0x0e, 0x16, 0xff },
-+ { 0x02, 0x11, 0xff, 0xff },
-+ { 0x04, 0xff, 0xff, 0xff }
-+};
-+
-+static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = {
-+ { 0x02, 0x12, 0x16, 0x1a },
-+ { 0x09, 0x19, 0x1f, 0xff },
-+ { 0x10, 0x1f, 0xff, 0xff },
-+ { 0x1f, 0xff, 0xff, 0xff }
-+};
-+
-+static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = {
-+ { 0x00, 0x0c, 0x14, 0x19 },
-+ { 0x00, 0x0b, 0x12, 0xff },
-+ { 0x00, 0x0b, 0xff, 0xff },
-+ { 0x04, 0xff, 0xff, 0xff }
-+};
-+
-+static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = {
-+ { 0x08, 0x0f, 0x16, 0x1f },
-+ { 0x11, 0x1e, 0x1f, 0xff },
-+ { 0x19, 0x1f, 0xff, 0xff },
-+ { 0x1f, 0xff, 0xff, 0xff }
-+};
-+
-+static int qcom_qmp_phy_configure_dp_swing(struct qmp_phy *qphy,
-+ unsigned int drv_lvl_reg, unsigned int emp_post_reg)
-+{
-+ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-+ unsigned int v_level = 0, p_level = 0;
-+ u8 voltage_swing_cfg, pre_emphasis_cfg;
-+ int i;
-+
-+ for (i = 0; i < dp_opts->lanes; i++) {
-+ v_level = max(v_level, dp_opts->voltage[i]);
-+ p_level = max(p_level, dp_opts->pre[i]);
-+ }
-+
-+ if (dp_opts->link_rate <= 2700) {
-+ voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level];
-+ pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level];
-+ } else {
-+ voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr3_hbr2[v_level][p_level];
-+ pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr3_hbr2[v_level][p_level];
-+ }
-+
-+ /* TODO: Move check to config check */
-+ if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF)
-+ return -EINVAL;
-+
-+ /* Enable MUX to use Cursor values from these registers */
-+ voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
-+ pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
-+
-+ writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg);
-+ writel(pre_emphasis_cfg, qphy->tx + emp_post_reg);
-+ writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg);
-+ writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg);
-+
-+ return 0;
-+}
-+
-+static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy)
-+{
-+ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-+ u32 bias_en, drvr_en;
-+
-+ if (qcom_qmp_phy_configure_dp_swing(qphy,
-+ QSERDES_V3_TX_TX_DRV_LVL,
-+ QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0)
-+ return;
-+
-+ if (dp_opts->lanes == 1) {
-+ bias_en = 0x3e;
-+ drvr_en = 0x13;
-+ } else {
-+ bias_en = 0x3f;
-+ drvr_en = 0x10;
-+ }
-+
-+ writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN);
-+ writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
-+ writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN);
-+ writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
-+}
-+
-+static bool qcom_qmp_phy_configure_dp_mode(struct qmp_phy *qphy)
-+{
-+ u32 val;
-+ bool reverse = false;
-+
-+ val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
-+ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN;
-+
-+ /*
-+ * TODO: Assume orientation is CC1 for now and two lanes, need to
-+ * use type-c connector to understand orientation and lanes.
-+ *
-+ * Otherwise val changes to be like below if this code understood
-+ * the orientation of the type-c cable.
-+ *
-+ * if (lane_cnt == 4 || orientation == ORIENTATION_CC2)
-+ * val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN;
-+ * if (lane_cnt == 4 || orientation == ORIENTATION_CC1)
-+ * val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
-+ * if (orientation == ORIENTATION_CC2)
-+ * writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
-+ */
-+ val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
-+ writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+
-+ writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE);
-+
-+ return reverse;
-+}
-+
-+static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy)
-+{
-+ const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
-+ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-+ u32 phy_vco_div, status;
-+ unsigned long pixel_freq;
-+
-+ qcom_qmp_phy_configure_dp_mode(qphy);
-+
-+ writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
-+ writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
-+
-+ switch (dp_opts->link_rate) {
-+ case 1620:
-+ phy_vco_div = 0x1;
-+ pixel_freq = 1620000000UL / 2;
-+ break;
-+ case 2700:
-+ phy_vco_div = 0x1;
-+ pixel_freq = 2700000000UL / 2;
-+ break;
-+ case 5400:
-+ phy_vco_div = 0x2;
-+ pixel_freq = 5400000000UL / 4;
-+ break;
-+ case 8100:
-+ phy_vco_div = 0x0;
-+ pixel_freq = 8100000000UL / 6;
-+ break;
-+ default:
-+ /* Other link rates aren't supported */
-+ return -EINVAL;
-+ }
-+ writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV);
-+
-+ clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
-+ clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
-+
-+ writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
-+ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL);
-+
-+ if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS,
-+ status,
-+ ((status & BIT(0)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
-+ status,
-+ ((status & BIT(1)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ udelay(2000);
-+ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
-+ status,
-+ ((status & BIT(1)) > 0),
-+ 500,
-+ 10000);
-+}
-+
-+/*
-+ * We need to calibrate the aux setting here as many times
-+ * as the caller tries
-+ */
-+static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy)
-+{
-+ static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d };
-+ u8 val;
-+
-+ qphy->dp_aux_cfg++;
-+ qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
-+ val = cfg1_settings[qphy->dp_aux_cfg];
-+
-+ writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-+
-+ return 0;
-+}
-+
-+static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy)
-+{
-+ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
-+ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
-+ qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+
-+ /* Turn on BIAS current for PHY/PLL */
-+ writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN);
-+
-+ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
-+ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-+ writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
-+ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
-+ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
-+ writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
-+ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
-+ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
-+ writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
-+ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
-+ qphy->dp_aux_cfg = 0;
-+
-+ writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
-+ PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
-+ PHY_AUX_REQ_ERR_MASK,
-+ qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
-+}
-+
-+static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy)
-+{
-+ /* Program default values before writing proper values */
-+ writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
-+ writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
-+
-+ writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
-+ writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
-+
-+ qcom_qmp_phy_configure_dp_swing(qphy,
-+ QSERDES_V4_TX_TX_DRV_LVL,
-+ QSERDES_V4_TX_TX_EMP_POST1_LVL);
-+}
-+
-+static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy)
-+{
-+ const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
-+ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-+ u32 phy_vco_div, status;
-+ unsigned long pixel_freq;
-+ u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
-+ bool reverse;
-+
-+ writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1);
-+
-+ reverse = qcom_qmp_phy_configure_dp_mode(qphy);
-+
-+ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-+ writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
-+
-+ writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL);
-+ writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL);
-+
-+ switch (dp_opts->link_rate) {
-+ case 1620:
-+ phy_vco_div = 0x1;
-+ pixel_freq = 1620000000UL / 2;
-+ break;
-+ case 2700:
-+ phy_vco_div = 0x1;
-+ pixel_freq = 2700000000UL / 2;
-+ break;
-+ case 5400:
-+ phy_vco_div = 0x2;
-+ pixel_freq = 5400000000UL / 4;
-+ break;
-+ case 8100:
-+ phy_vco_div = 0x0;
-+ pixel_freq = 8100000000UL / 6;
-+ break;
-+ default:
-+ /* Other link rates aren't supported */
-+ return -EINVAL;
-+ }
-+ writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV);
-+
-+ clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
-+ clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
-+
-+ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL);
-+
-+ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS,
-+ status,
-+ ((status & BIT(0)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
-+ status,
-+ ((status & BIT(0)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
-+ status,
-+ ((status & BIT(1)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
-+ status,
-+ ((status & BIT(0)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
-+ status,
-+ ((status & BIT(1)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ /*
-+ * At least for 7nm DP PHY this has to be done after enabling link
-+ * clock.
-+ */
-+
-+ if (dp_opts->lanes == 1) {
-+ bias0_en = reverse ? 0x3e : 0x15;
-+ bias1_en = reverse ? 0x15 : 0x3e;
-+ drvr0_en = reverse ? 0x13 : 0x10;
-+ drvr1_en = reverse ? 0x10 : 0x13;
-+ } else if (dp_opts->lanes == 2) {
-+ bias0_en = reverse ? 0x3f : 0x15;
-+ bias1_en = reverse ? 0x15 : 0x3f;
-+ drvr0_en = 0x10;
-+ drvr1_en = 0x10;
-+ } else {
-+ bias0_en = 0x3f;
-+ bias1_en = 0x3f;
-+ drvr0_en = 0x10;
-+ drvr1_en = 0x10;
-+ }
-+
-+ writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN);
-+ writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
-+ writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN);
-+ writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
-+
-+ writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ udelay(2000);
-+ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
-+ status,
-+ ((status & BIT(1)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV);
-+ writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV);
-+
-+ writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
-+ writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
-+
-+ writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
-+ writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
-+
-+ return 0;
-+}
-+
-+/*
-+ * We need to calibrate the aux setting here as many times
-+ * as the caller tries
-+ */
-+static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy)
-+{
-+ static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d };
-+ u8 val;
-+
-+ qphy->dp_aux_cfg++;
-+ qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
-+ val = cfg1_settings[qphy->dp_aux_cfg];
-+
-+ writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
-+{
-+ const struct phy_configure_opts_dp *dp_opts = &opts->dp;
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+
-+ memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts));
-+ if (qphy->dp_opts.set_voltages) {
-+ cfg->configure_dp_tx(qphy);
-+ qphy->dp_opts.set_voltages = 0;
-+ }
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_dp_phy_calibrate(struct phy *phy)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+
-+ if (cfg->calibrate_dp_phy)
-+ return cfg->calibrate_dp_phy(qphy);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
-+{
-+ struct qcom_qmp *qmp = qphy->qmp;
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *serdes = qphy->serdes;
-+ void __iomem *pcs = qphy->pcs;
-+ void __iomem *dp_com = qmp->dp_com;
-+ int ret, i;
-+
-+ mutex_lock(&qmp->phy_mutex);
-+ if (qmp->init_count++) {
-+ mutex_unlock(&qmp->phy_mutex);
-+ return 0;
-+ }
-+
-+ /* turn on regulator supplies */
-+ ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
-+ if (ret) {
-+ dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
-+ goto err_unlock;
-+ }
-+
-+ for (i = 0; i < cfg->num_resets; i++) {
-+ ret = reset_control_assert(qmp->resets[i]);
-+ if (ret) {
-+ dev_err(qmp->dev, "%s reset assert failed\n",
-+ cfg->reset_list[i]);
-+ goto err_disable_regulators;
-+ }
-+ }
-+
-+ for (i = cfg->num_resets - 1; i >= 0; i--) {
-+ ret = reset_control_deassert(qmp->resets[i]);
-+ if (ret) {
-+ dev_err(qmp->dev, "%s reset deassert failed\n",
-+ qphy->cfg->reset_list[i]);
-+ goto err_assert_reset;
-+ }
-+ }
-+
-+ ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
-+ if (ret)
-+ goto err_assert_reset;
-+
-+ if (cfg->has_phy_dp_com_ctrl) {
-+ qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
-+ SW_PWRDN);
-+ /* override hardware control for reset of qmp phy */
-+ qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
-+ SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
-+ SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
-+
-+ /* Default type-c orientation, i.e CC1 */
-+ qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02);
-+
-+ qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
-+ USB3_MODE | DP_MODE);
-+
-+ /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
-+ qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
-+ SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
-+ SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
-+
-+ qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
-+ qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
-+ }
-+
-+ if (cfg->has_phy_com_ctrl) {
-+ qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
-+ SW_PWRDN);
-+ } else {
-+ if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
-+ qphy_setbits(pcs,
-+ cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
-+ cfg->pwrdn_ctrl);
-+ else
-+ qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
-+ cfg->pwrdn_ctrl);
-+ }
-+
-+ mutex_unlock(&qmp->phy_mutex);
-+
-+ return 0;
-+
-+err_assert_reset:
-+ while (++i < cfg->num_resets)
-+ reset_control_assert(qmp->resets[i]);
-+err_disable_regulators:
-+ regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
-+err_unlock:
-+ mutex_unlock(&qmp->phy_mutex);
-+
-+ return ret;
-+}
-+
-+static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy)
-+{
-+ struct qcom_qmp *qmp = qphy->qmp;
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *serdes = qphy->serdes;
-+ int i = cfg->num_resets;
-+
-+ mutex_lock(&qmp->phy_mutex);
-+ if (--qmp->init_count) {
-+ mutex_unlock(&qmp->phy_mutex);
-+ return 0;
-+ }
-+
-+ reset_control_assert(qmp->ufs_reset);
-+ if (cfg->has_phy_com_ctrl) {
-+ qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
-+ SERDES_START | PCS_START);
-+ qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
-+ SW_RESET);
-+ qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
-+ SW_PWRDN);
-+ }
-+
-+ while (--i >= 0)
-+ reset_control_assert(qmp->resets[i]);
-+
-+ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
-+
-+ regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
-+
-+ mutex_unlock(&qmp->phy_mutex);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_init(struct phy *phy)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ struct qcom_qmp *qmp = qphy->qmp;
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ int ret;
-+ dev_vdbg(qmp->dev, "Initializing QMP phy\n");
-+
-+ if (cfg->no_pcs_sw_reset) {
-+ /*
-+ * Get UFS reset, which is delayed until now to avoid a
-+ * circular dependency where UFS needs its PHY, but the PHY
-+ * needs this UFS reset.
-+ */
-+ if (!qmp->ufs_reset) {
-+ qmp->ufs_reset =
-+ devm_reset_control_get_exclusive(qmp->dev,
-+ "ufsphy");
-+
-+ if (IS_ERR(qmp->ufs_reset)) {
-+ ret = PTR_ERR(qmp->ufs_reset);
-+ dev_err(qmp->dev,
-+ "failed to get UFS reset: %d\n",
-+ ret);
-+
-+ qmp->ufs_reset = NULL;
-+ return ret;
-+ }
-+ }
-+
-+ ret = reset_control_assert(qmp->ufs_reset);
-+ if (ret)
-+ return ret;
-+ }
-+
-+ ret = qcom_qmp_phy_com_init(qphy);
-+ if (ret)
-+ return ret;
-+
-+ if (cfg->type == PHY_TYPE_DP)
-+ cfg->dp_aux_init(qphy);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_power_on(struct phy *phy)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ struct qcom_qmp *qmp = qphy->qmp;
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *tx = qphy->tx;
-+ void __iomem *rx = qphy->rx;
-+ void __iomem *pcs = qphy->pcs;
-+ void __iomem *pcs_misc = qphy->pcs_misc;
-+ void __iomem *status;
-+ unsigned int mask, val, ready;
-+ int ret;
-+
-+ qcom_qmp_phy_serdes_init(qphy);
-+
-+ if (cfg->has_lane_rst) {
-+ ret = reset_control_deassert(qphy->lane_rst);
-+ if (ret) {
-+ dev_err(qmp->dev, "lane%d reset deassert failed\n",
-+ qphy->index);
-+ return ret;
-+ }
-+ }
-+
-+ ret = clk_prepare_enable(qphy->pipe_clk);
-+ if (ret) {
-+ dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
-+ goto err_reset_lane;
-+ }
-+
-+ /* Tx, Rx, and PCS configurations */
-+ qcom_qmp_phy_configure_lane(tx, cfg->regs,
-+ cfg->tx_tbl, cfg->tx_tbl_num, 1);
-+ if (cfg->tx_tbl_sec)
-+ qcom_qmp_phy_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
-+ cfg->tx_tbl_num_sec, 1);
-+
-+ /* Configuration for other LANE for USB-DP combo PHY */
-+ if (cfg->is_dual_lane_phy) {
-+ qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
-+ cfg->tx_tbl, cfg->tx_tbl_num, 2);
-+ if (cfg->tx_tbl_sec)
-+ qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
-+ cfg->tx_tbl_sec,
-+ cfg->tx_tbl_num_sec, 2);
-+ }
-+
-+ /* Configure special DP tx tunings */
-+ if (cfg->type == PHY_TYPE_DP)
-+ cfg->configure_dp_tx(qphy);
-+
-+ qcom_qmp_phy_configure_lane(rx, cfg->regs,
-+ cfg->rx_tbl, cfg->rx_tbl_num, 1);
-+ if (cfg->rx_tbl_sec)
-+ qcom_qmp_phy_configure_lane(rx, cfg->regs,
-+ cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1);
-+
-+ if (cfg->is_dual_lane_phy) {
-+ qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
-+ cfg->rx_tbl, cfg->rx_tbl_num, 2);
-+ if (cfg->rx_tbl_sec)
-+ qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
-+ cfg->rx_tbl_sec,
-+ cfg->rx_tbl_num_sec, 2);
-+ }
-+
-+ /* Configure link rate, swing, etc. */
-+ if (cfg->type == PHY_TYPE_DP) {
-+ cfg->configure_dp_phy(qphy);
-+ } else {
-+ qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
-+ if (cfg->pcs_tbl_sec)
-+ qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
-+ cfg->pcs_tbl_num_sec);
-+ }
-+
-+ ret = reset_control_deassert(qmp->ufs_reset);
-+ if (ret)
-+ goto err_disable_pipe_clk;
-+
-+ qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
-+ cfg->pcs_misc_tbl_num);
-+ if (cfg->pcs_misc_tbl_sec)
-+ qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
-+ cfg->pcs_misc_tbl_num_sec);
-+
-+ /*
-+ * Pull out PHY from POWER DOWN state.
-+ * This is active low enable signal to power-down PHY.
-+ */
-+ if(cfg->type == PHY_TYPE_PCIE)
-+ qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
-+
-+ if (cfg->has_pwrdn_delay)
-+ usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
-+
-+ if (cfg->type != PHY_TYPE_DP) {
-+ /* Pull PHY out of reset state */
-+ if (!cfg->no_pcs_sw_reset)
-+ qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
-+ /* start SerDes and Phy-Coding-Sublayer */
-+ qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
-+
-+ if (cfg->type == PHY_TYPE_UFS) {
-+ status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
-+ mask = PCS_READY;
-+ ready = PCS_READY;
-+ } else {
-+ status = pcs + cfg->regs[QPHY_PCS_STATUS];
-+ mask = cfg->phy_status;
-+ ready = 0;
-+ }
-+
-+ ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
-+ PHY_INIT_COMPLETE_TIMEOUT);
-+ if (ret) {
-+ dev_err(qmp->dev, "phy initialization timed-out\n");
-+ goto err_disable_pipe_clk;
-+ }
-+ }
-+ return 0;
-+
-+err_disable_pipe_clk:
-+ clk_disable_unprepare(qphy->pipe_clk);
-+err_reset_lane:
-+ if (cfg->has_lane_rst)
-+ reset_control_assert(qphy->lane_rst);
-+
-+ return ret;
-+}
-+
-+static int qcom_qmp_phy_power_off(struct phy *phy)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+
-+ clk_disable_unprepare(qphy->pipe_clk);
-+
-+ if (cfg->type == PHY_TYPE_DP) {
-+ /* Assert DP PHY power down */
-+ writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+ } else {
-+ /* PHY reset */
-+ if (!cfg->no_pcs_sw_reset)
-+ qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
-+
-+ /* stop SerDes and Phy-Coding-Sublayer */
-+ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
-+
-+ /* Put PHY into POWER DOWN state: active low */
-+ if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
-+ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
-+ cfg->pwrdn_ctrl);
-+ } else {
-+ qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
-+ cfg->pwrdn_ctrl);
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_exit(struct phy *phy)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+
-+ if (cfg->has_lane_rst)
-+ reset_control_assert(qphy->lane_rst);
-+
-+ qcom_qmp_phy_com_exit(qphy);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_enable(struct phy *phy)
-+{
-+ int ret;
-+
-+ ret = qcom_qmp_phy_init(phy);
-+ if (ret)
-+ return ret;
-+
-+ ret = qcom_qmp_phy_power_on(phy);
-+ if (ret)
-+ qcom_qmp_phy_exit(phy);
-+
-+ return ret;
-+}
-+
-+static int qcom_qmp_phy_disable(struct phy *phy)
-+{
-+ int ret;
-+
-+ ret = qcom_qmp_phy_power_off(phy);
-+ if (ret)
-+ return ret;
-+ return qcom_qmp_phy_exit(phy);
-+}
-+
-+static int qcom_qmp_phy_set_mode(struct phy *phy,
-+ enum phy_mode mode, int submode)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+
-+ qphy->mode = mode;
-+
-+ return 0;
-+}
-+
-+static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
-+{
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *pcs = qphy->pcs;
-+ void __iomem *pcs_misc = qphy->pcs_misc;
-+ u32 intr_mask;
-+
-+ if (qphy->mode == PHY_MODE_USB_HOST_SS ||
-+ qphy->mode == PHY_MODE_USB_DEVICE_SS)
-+ intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
-+ else
-+ intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
-+
-+ /* Clear any pending interrupts status */
-+ qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
-+ /* Writing 1 followed by 0 clears the interrupt */
-+ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
-+
-+ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
-+ ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
-+
-+ /* Enable required PHY autonomous mode interrupts */
-+ qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
-+
-+ /* Enable i/o clamp_n for autonomous mode */
-+ if (pcs_misc)
-+ qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
-+}
-+
-+static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
-+{
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *pcs = qphy->pcs;
-+ void __iomem *pcs_misc = qphy->pcs_misc;
-+
-+ /* Disable i/o clamp_n on resume for normal mode */
-+ if (pcs_misc)
-+ qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
-+
-+ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
-+ ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
-+
-+ qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
-+ /* Writing 1 followed by 0 clears the interrupt */
-+ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
-+}
-+
-+static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ struct qmp_phy *qphy = qmp->phys[0];
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+
-+ dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode);
-+
-+ /* Supported only for USB3 PHY and luckily USB3 is the first phy */
-+ if (cfg->type != PHY_TYPE_USB3)
-+ return 0;
-+
-+ if (!qmp->init_count) {
-+ dev_vdbg(dev, "PHY not initialized, bailing out\n");
-+ return 0;
-+ }
-+
-+ qcom_qmp_phy_enable_autonomous_mode(qphy);
-+
-+ clk_disable_unprepare(qphy->pipe_clk);
-+ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
-+
-+ return 0;
-+}
-+
-+static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ struct qmp_phy *qphy = qmp->phys[0];
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ int ret = 0;
-+
-+ dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode);
-+
-+ /* Supported only for USB3 PHY and luckily USB3 is the first phy */
-+ if (cfg->type != PHY_TYPE_USB3)
-+ return 0;
-+
-+ if (!qmp->init_count) {
-+ dev_vdbg(dev, "PHY not initialized, bailing out\n");
-+ return 0;
-+ }
-+
-+ ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
-+ if (ret)
-+ return ret;
-+
-+ ret = clk_prepare_enable(qphy->pipe_clk);
-+ if (ret) {
-+ dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
-+ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
-+ return ret;
-+ }
-+
-+ qcom_qmp_phy_disable_autonomous_mode(qphy);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ int num = cfg->num_vregs;
-+ int i;
-+
-+ qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
-+ if (!qmp->vregs)
-+ return -ENOMEM;
-+
-+ for (i = 0; i < num; i++)
-+ qmp->vregs[i].supply = cfg->vreg_list[i];
-+
-+ return devm_regulator_bulk_get(dev, num, qmp->vregs);
-+}
-+
-+static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ int i;
-+
-+ qmp->resets = devm_kcalloc(dev, cfg->num_resets,
-+ sizeof(*qmp->resets), GFP_KERNEL);
-+ if (!qmp->resets)
-+ return -ENOMEM;
-+
-+ for (i = 0; i < cfg->num_resets; i++) {
-+ struct reset_control *rst;
-+ const char *name = cfg->reset_list[i];
-+
-+ rst = devm_reset_control_get_exclusive(dev, name);
-+ if (IS_ERR(rst)) {
-+ dev_err(dev, "failed to get %s reset\n", name);
-+ return PTR_ERR(rst);
-+ }
-+ qmp->resets[i] = rst;
-+ }
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ int num = cfg->num_clks;
-+ int i;
-+
-+ qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
-+ if (!qmp->clks)
-+ return -ENOMEM;
-+
-+ for (i = 0; i < num; i++)
-+ qmp->clks[i].id = cfg->clk_list[i];
-+
-+ return devm_clk_bulk_get(dev, num, qmp->clks);
-+}
-+
-+static void phy_clk_release_provider(void *res)
-+{
-+ of_clk_del_provider(res);
-+}
-+
-+/*
-+ * Register a fixed rate pipe clock.
-+ *
-+ * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
-+ * controls it. The <s>_pipe_clk coming out of the GCC is requested
-+ * by the PHY driver for its operations.
-+ * We register the <s>_pipe_clksrc here. The gcc driver takes care
-+ * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
-+ * Below picture shows this relationship.
-+ *
-+ * +---------------+
-+ * | PHY block |<<---------------------------------------+
-+ * | | |
-+ * | +-------+ | +-----+ |
-+ * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
-+ * clk | +-------+ | +-----+
-+ * +---------------+
-+ */
-+static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
-+{
-+ struct clk_fixed_rate *fixed;
-+ struct clk_init_data init = { };
-+ int ret;
-+
-+ ret = of_property_read_string(np, "clock-output-names", &init.name);
-+ if (ret) {
-+ dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
-+ return ret;
-+ }
-+
-+ fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
-+ if (!fixed)
-+ return -ENOMEM;
-+
-+ init.ops = &clk_fixed_rate_ops;
-+
-+ /* controllers using QMP phys use 125MHz pipe clock interface */
-+ fixed->fixed_rate = 125000000;
-+ fixed->hw.init = &init;
-+
-+ ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
-+ if (ret)
-+ return ret;
-+
-+ ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
-+ if (ret)
-+ return ret;
-+
-+ /*
-+ * Roll a devm action because the clock provider is the child node, but
-+ * the child node is not actually a device.
-+ */
-+ return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
-+}
-+
-+/*
-+ * Display Port PLL driver block diagram for branch clocks
-+ *
-+ * +------------------------------+
-+ * | DP_VCO_CLK |
-+ * | |
-+ * | +-------------------+ |
-+ * | | (DP PLL/VCO) | |
-+ * | +---------+---------+ |
-+ * | v |
-+ * | +----------+-----------+ |
-+ * | | hsclk_divsel_clk_src | |
-+ * | +----------+-----------+ |
-+ * +------------------------------+
-+ * |
-+ * +---------<---------v------------>----------+
-+ * | |
-+ * +--------v----------------+ |
-+ * | dp_phy_pll_link_clk | |
-+ * | link_clk | |
-+ * +--------+----------------+ |
-+ * | |
-+ * | |
-+ * v v
-+ * Input to DISPCC block |
-+ * for link clk, crypto clk |
-+ * and interface clock |
-+ * |
-+ * |
-+ * +--------<------------+-----------------+---<---+
-+ * | | |
-+ * +----v---------+ +--------v-----+ +--------v------+
-+ * | vco_divided | | vco_divided | | vco_divided |
-+ * | _clk_src | | _clk_src | | _clk_src |
-+ * | | | | | |
-+ * |divsel_six | | divsel_two | | divsel_four |
-+ * +-------+------+ +-----+--------+ +--------+------+
-+ * | | |
-+ * v---->----------v-------------<------v
-+ * |
-+ * +----------+-----------------+
-+ * | dp_phy_pll_vco_div_clk |
-+ * +---------+------------------+
-+ * |
-+ * v
-+ * Input to DISPCC block
-+ * for DP pixel clock
-+ *
-+ */
-+static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw,
-+ struct clk_rate_request *req)
-+{
-+ switch (req->rate) {
-+ case 1620000000UL / 2:
-+ case 2700000000UL / 2:
-+ /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */
-+ return 0;
-+ default:
-+ return -EINVAL;
-+ }
-+}
-+
-+static unsigned long
-+qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
-+{
-+ const struct qmp_phy_dp_clks *dp_clks;
-+ const struct qmp_phy *qphy;
-+ const struct phy_configure_opts_dp *dp_opts;
-+
-+ dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw);
-+ qphy = dp_clks->qphy;
-+ dp_opts = &qphy->dp_opts;
-+
-+ switch (dp_opts->link_rate) {
-+ case 1620:
-+ return 1620000000UL / 2;
-+ case 2700:
-+ return 2700000000UL / 2;
-+ case 5400:
-+ return 5400000000UL / 4;
-+ case 8100:
-+ return 8100000000UL / 6;
-+ default:
-+ return 0;
-+ }
-+}
-+
-+static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = {
-+ .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate,
-+ .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate,
-+};
-+
-+static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw,
-+ struct clk_rate_request *req)
-+{
-+ switch (req->rate) {
-+ case 162000000:
-+ case 270000000:
-+ case 540000000:
-+ case 810000000:
-+ return 0;
-+ default:
-+ return -EINVAL;
-+ }
-+}
-+
-+static unsigned long
-+qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
-+{
-+ const struct qmp_phy_dp_clks *dp_clks;
-+ const struct qmp_phy *qphy;
-+ const struct phy_configure_opts_dp *dp_opts;
-+
-+ dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw);
-+ qphy = dp_clks->qphy;
-+ dp_opts = &qphy->dp_opts;
-+
-+ switch (dp_opts->link_rate) {
-+ case 1620:
-+ case 2700:
-+ case 5400:
-+ case 8100:
-+ return dp_opts->link_rate * 100000;
-+ default:
-+ return 0;
-+ }
-+}
-+
-+static const struct clk_ops qcom_qmp_dp_link_clk_ops = {
-+ .determine_rate = qcom_qmp_dp_link_clk_determine_rate,
-+ .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate,
-+};
-+
-+static struct clk_hw *
-+qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data)
-+{
-+ struct qmp_phy_dp_clks *dp_clks = data;
-+ unsigned int idx = clkspec->args[0];
-+
-+ if (idx >= 2) {
-+ pr_err("%s: invalid index %u\n", __func__, idx);
-+ return ERR_PTR(-EINVAL);
-+ }
-+
-+ if (idx == 0)
-+ return &dp_clks->dp_link_hw;
-+
-+ return &dp_clks->dp_pixel_hw;
-+}
-+
-+static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy,
-+ struct device_node *np)
-+{
-+ struct clk_init_data init = { };
-+ struct qmp_phy_dp_clks *dp_clks;
-+ char name[64];
-+ int ret;
-+
-+ dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL);
-+ if (!dp_clks)
-+ return -ENOMEM;
-+
-+ dp_clks->qphy = qphy;
-+ qphy->dp_clks = dp_clks;
-+
-+ snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev));
-+ init.ops = &qcom_qmp_dp_link_clk_ops;
-+ init.name = name;
-+ dp_clks->dp_link_hw.init = &init;
-+ ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw);
-+ if (ret)
-+ return ret;
-+
-+ snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev));
-+ init.ops = &qcom_qmp_dp_pixel_clk_ops;
-+ init.name = name;
-+ dp_clks->dp_pixel_hw.init = &init;
-+ ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw);
-+ if (ret)
-+ return ret;
-+
-+ ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks);
-+ if (ret)
-+ return ret;
-+
-+ /*
-+ * Roll a devm action because the clock provider is the child node, but
-+ * the child node is not actually a device.
-+ */
-+ return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
-+}
-+
-+static const struct phy_ops qcom_qmp_phy_gen_ops = {
-+ .init = qcom_qmp_phy_enable,
-+ .exit = qcom_qmp_phy_disable,
-+ .set_mode = qcom_qmp_phy_set_mode,
-+ .owner = THIS_MODULE,
-+};
-+
-+static const struct phy_ops qcom_qmp_phy_dp_ops = {
-+ .init = qcom_qmp_phy_init,
-+ .configure = qcom_qmp_dp_phy_configure,
-+ .power_on = qcom_qmp_phy_power_on,
-+ .calibrate = qcom_qmp_dp_phy_calibrate,
-+ .power_off = qcom_qmp_phy_power_off,
-+ .exit = qcom_qmp_phy_exit,
-+ .set_mode = qcom_qmp_phy_set_mode,
-+ .owner = THIS_MODULE,
-+};
-+
-+static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
-+ .power_on = qcom_qmp_phy_enable,
-+ .power_off = qcom_qmp_phy_disable,
-+ .set_mode = qcom_qmp_phy_set_mode,
-+ .owner = THIS_MODULE,
-+};
-+
-+static void qcom_qmp_reset_control_put(void *data)
-+{
-+ reset_control_put(data);
-+}
-+
-+static
-+int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
-+ void __iomem *serdes, const struct qmp_phy_cfg *cfg)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ struct phy *generic_phy;
-+ struct qmp_phy *qphy;
-+ const struct phy_ops *ops;
-+ char prop_name[MAX_PROP_NAME];
-+ int ret;
-+
-+ qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
-+ if (!qphy)
-+ return -ENOMEM;
-+
-+ qphy->cfg = cfg;
-+ qphy->serdes = serdes;
-+ /*
-+ * Get memory resources for each phy lane:
-+ * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
-+ * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
-+ * For single lane PHYs: pcs_misc (optional) -> 3.
-+ */
-+ qphy->tx = of_iomap(np, 0);
-+ if (!qphy->tx)
-+ return -ENOMEM;
-+
-+ qphy->rx = of_iomap(np, 1);
-+ if (!qphy->rx)
-+ return -ENOMEM;
-+
-+ qphy->pcs = of_iomap(np, 2);
-+ if (!qphy->pcs)
-+ return -ENOMEM;
-+
-+ /*
-+ * If this is a dual-lane PHY, then there should be registers for the
-+ * second lane. Some old device trees did not specify this, so fall
-+ * back to old legacy behavior of assuming they can be reached at an
-+ * offset from the first lane.
-+ */
-+ if (cfg->is_dual_lane_phy) {
-+ qphy->tx2 = of_iomap(np, 3);
-+ qphy->rx2 = of_iomap(np, 4);
-+ if (!qphy->tx2 || !qphy->rx2) {
-+ dev_warn(dev,
-+ "Underspecified device tree, falling back to legacy register regions\n");
-+
-+ /* In the old version, pcs_misc is at index 3. */
-+ qphy->pcs_misc = qphy->tx2;
-+ qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE;
-+ qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
-+
-+ } else {
-+ qphy->pcs_misc = of_iomap(np, 5);
-+ }
-+
-+ } else {
-+ qphy->pcs_misc = of_iomap(np, 3);
-+ }
-+
-+ if (!qphy->pcs_misc)
-+ dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
-+
-+ /*
-+ * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3
-+ * based phys, so they essentially have pipe clock. So,
-+ * we return error in case phy is USB3 or PIPE type.
-+ * Otherwise, we initialize pipe clock to NULL for
-+ * all phys that don't need this.
-+ */
-+ snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
-+ qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name);
-+ if (IS_ERR(qphy->pipe_clk)) {
-+ if (cfg->type == PHY_TYPE_PCIE ||
-+ cfg->type == PHY_TYPE_USB3) {
-+ ret = PTR_ERR(qphy->pipe_clk);
-+ if (ret != -EPROBE_DEFER)
-+ dev_err(dev,
-+ "failed to get lane%d pipe_clk, %d\n",
-+ id, ret);
-+ return ret;
-+ }
-+ qphy->pipe_clk = NULL;
-+ }
-+
-+ /* Get lane reset, if any */
-+ if (cfg->has_lane_rst) {
-+ snprintf(prop_name, sizeof(prop_name), "lane%d", id);
-+ qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name);
-+ if (IS_ERR(qphy->lane_rst)) {
-+ dev_err(dev, "failed to get lane%d reset\n", id);
-+ return PTR_ERR(qphy->lane_rst);
-+ }
-+ ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put,
-+ qphy->lane_rst);
-+ if (ret)
-+ return ret;
-+ }
-+
-+ if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE)
-+ ops = &qcom_qmp_pcie_ufs_ops;
-+ else if (cfg->type == PHY_TYPE_DP)
-+ ops = &qcom_qmp_phy_dp_ops;
-+ else
-+ ops = &qcom_qmp_phy_gen_ops;
-+
-+ generic_phy = devm_phy_create(dev, np, ops);
-+ if (IS_ERR(generic_phy)) {
-+ ret = PTR_ERR(generic_phy);
-+ dev_err(dev, "failed to create qphy %d\n", ret);
-+ return ret;
-+ }
-+
-+ qphy->phy = generic_phy;
-+ qphy->index = id;
-+ qphy->qmp = qmp;
-+ qmp->phys[id] = qphy;
-+ phy_set_drvdata(generic_phy, qphy);
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
-+ {
-+ .compatible = "qcom,ipq8074-qmp-usb3-phy",
-+ .data = &ipq8074_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,msm8996-qmp-pcie-phy",
-+ .data = &msm8996_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,msm8996-qmp-ufs-phy",
-+ .data = &msm8996_ufs_cfg,
-+ }, {
-+ .compatible = "qcom,msm8996-qmp-usb3-phy",
-+ .data = &msm8996_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,msm8998-qmp-pcie-phy",
-+ .data = &msm8998_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,msm8998-qmp-ufs-phy",
-+ .data = &sdm845_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,ipq8074-qmp-pcie-phy",
-+ .data = &ipq8074_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,ipq6018-qmp-pcie-phy",
-+ .data = &ipq6018_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,ipq6018-qmp-usb3-phy",
-+ .data = &ipq8074_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sc7180-qmp-usb3-phy",
-+ .data = &sc7180_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
-+ /* It's a combo phy */
-+ }, {
-+ .compatible = "qcom,sc8180x-qmp-pcie-phy",
-+ .data = &sc8180x_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sc8180x-qmp-ufs-phy",
-+ .data = &sm8150_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sc8280xp-qmp-ufs-phy",
-+ .data = &sm8350_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sc8180x-qmp-usb3-phy",
-+ .data = &sm8150_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
-+ /* It's a combo phy */
-+ }, {
-+ .compatible = "qcom,sdm845-qhp-pcie-phy",
-+ .data = &sdm845_qhp_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sdm845-qmp-pcie-phy",
-+ .data = &sdm845_qmp_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sdm845-qmp-usb3-phy",
-+ .data = &qmp_v3_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
-+ .data = &qmp_v3_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sdm845-qmp-ufs-phy",
-+ .data = &sdm845_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,msm8998-qmp-usb3-phy",
-+ .data = &msm8998_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sm6115-qmp-ufs-phy",
-+ .data = &sm6115_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm6350-qmp-ufs-phy",
-+ .data = &sdm845_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8150-qmp-ufs-phy",
-+ .data = &sm8150_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-ufs-phy",
-+ .data = &sm8150_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8150-qmp-usb3-phy",
-+ .data = &sm8150_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8150-qmp-usb3-uni-phy",
-+ .data = &sm8150_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-usb3-phy",
-+ .data = &sm8250_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
-+ /* It's a combo phy */
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-usb3-uni-phy",
-+ .data = &sm8250_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
-+ .data = &sm8250_qmp_gen3x1_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
-+ .data = &sm8250_qmp_gen3x2_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8350-qmp-ufs-phy",
-+ .data = &sm8350_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
-+ .data = &sm8250_qmp_gen3x2_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sdx55-qmp-pcie-phy",
-+ .data = &sdx55_qmp_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sdx55-qmp-usb3-uni-phy",
-+ .data = &sdx55_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sdx65-qmp-usb3-uni-phy",
-+ .data = &sdx65_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8350-qmp-usb3-phy",
-+ .data = &sm8350_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8350-qmp-usb3-uni-phy",
-+ .data = &sm8350_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
-+ .data = &sm8450_qmp_gen3x1_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
-+ .data = &sm8450_qmp_gen4x2_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8450-qmp-ufs-phy",
-+ .data = &sm8450_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8450-qmp-usb3-phy",
-+ .data = &sm8350_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,qcm2290-qmp-usb3-phy",
-+ .data = &qcm2290_usb3phy_cfg,
-+ },
-+ { },
-+};
-+MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
-+
-+static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = {
-+ {
-+ .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
-+ .data = &sc7180_usb3dpphy_cfg,
-+ },
-+ {
-+ .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
-+ .data = &sm8250_usb3dpphy_cfg,
-+ },
-+ {
-+ .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
-+ .data = &sc8180x_usb3dpphy_cfg,
-+ },
-+ { }
-+};
-+
-+static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
-+ SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
-+ qcom_qmp_phy_runtime_resume, NULL)
-+};
-+
-+static int qcom_qmp_phy_probe(struct platform_device *pdev)
-+{
-+ struct qcom_qmp *qmp;
-+ struct device *dev = &pdev->dev;
-+ struct device_node *child;
-+ struct phy_provider *phy_provider;
-+ void __iomem *serdes;
-+ void __iomem *usb_serdes;
-+ void __iomem *dp_serdes = NULL;
-+ const struct qmp_phy_combo_cfg *combo_cfg = NULL;
-+ const struct qmp_phy_cfg *cfg = NULL;
-+ const struct qmp_phy_cfg *usb_cfg = NULL;
-+ const struct qmp_phy_cfg *dp_cfg = NULL;
-+ int num, id, expected_phys;
-+ int ret;
-+
-+ qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
-+ if (!qmp)
-+ return -ENOMEM;
-+
-+ qmp->dev = dev;
-+ dev_set_drvdata(dev, qmp);
-+
-+ /* Get the specific init parameters of QMP phy */
-+ cfg = of_device_get_match_data(dev);
-+ if (!cfg) {
-+ const struct of_device_id *match;
-+
-+ match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev);
-+ if (!match)
-+ return -EINVAL;
-+
-+ combo_cfg = match->data;
-+ if (!combo_cfg)
-+ return -EINVAL;
-+
-+ usb_cfg = combo_cfg->usb_cfg;
-+ cfg = usb_cfg; /* Setup clks and regulators */
-+ }
-+
-+ /* per PHY serdes; usually located at base address */
-+ usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0);
-+ if (IS_ERR(serdes))
-+ return PTR_ERR(serdes);
-+
-+ /* per PHY dp_com; if PHY has dp_com control block */
-+ if (combo_cfg || cfg->has_phy_dp_com_ctrl) {
-+ qmp->dp_com = devm_platform_ioremap_resource(pdev, 1);
-+ if (IS_ERR(qmp->dp_com))
-+ return PTR_ERR(qmp->dp_com);
-+ }
-+
-+ if (combo_cfg) {
-+ /* Only two serdes for combo PHY */
-+ dp_serdes = devm_platform_ioremap_resource(pdev, 2);
-+ if (IS_ERR(dp_serdes))
-+ return PTR_ERR(dp_serdes);
-+
-+ dp_cfg = combo_cfg->dp_cfg;
-+ expected_phys = 2;
-+ } else {
-+ expected_phys = cfg->nlanes;
-+ }
-+
-+ mutex_init(&qmp->phy_mutex);
-+
-+ ret = qcom_qmp_phy_clk_init(dev, cfg);
-+ if (ret)
-+ return ret;
-+
-+ ret = qcom_qmp_phy_reset_init(dev, cfg);
-+ if (ret)
-+ return ret;
-+
-+ ret = qcom_qmp_phy_vreg_init(dev, cfg);
-+ if (ret) {
-+ if (ret != -EPROBE_DEFER)
-+ dev_err(dev, "failed to get regulator supplies: %d\n",
-+ ret);
-+ return ret;
-+ }
-+
-+ num = of_get_available_child_count(dev->of_node);
-+ /* do we have a rogue child node ? */
-+ if (num > expected_phys)
-+ return -EINVAL;
-+
-+ qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
-+ if (!qmp->phys)
-+ return -ENOMEM;
-+
-+ pm_runtime_set_active(dev);
-+ pm_runtime_enable(dev);
-+ /*
-+ * Prevent runtime pm from being ON by default. Users can enable
-+ * it using power/control in sysfs.
-+ */
-+ pm_runtime_forbid(dev);
-+
-+ id = 0;
-+ for_each_available_child_of_node(dev->of_node, child) {
-+ if (of_node_name_eq(child, "dp-phy")) {
-+ cfg = dp_cfg;
-+ serdes = dp_serdes;
-+ } else if (of_node_name_eq(child, "usb3-phy")) {
-+ cfg = usb_cfg;
-+ serdes = usb_serdes;
-+ }
-+
-+ /* Create per-lane phy */
-+ ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg);
-+ if (ret) {
-+ dev_err(dev, "failed to create lane%d phy, %d\n",
-+ id, ret);
-+ goto err_node_put;
-+ }
-+
-+ /*
-+ * Register the pipe clock provided by phy.
-+ * See function description to see details of this pipe clock.
-+ */
-+ if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) {
-+ ret = phy_pipe_clk_register(qmp, child);
-+ if (ret) {
-+ dev_err(qmp->dev,
-+ "failed to register pipe clock source\n");
-+ goto err_node_put;
-+ }
-+ } else if (cfg->type == PHY_TYPE_DP) {
-+ ret = phy_dp_clks_register(qmp, qmp->phys[id], child);
-+ if (ret) {
-+ dev_err(qmp->dev,
-+ "failed to register DP clock source\n");
-+ goto err_node_put;
-+ }
-+ }
-+ id++;
-+ }
-+
-+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
-+ if (!IS_ERR(phy_provider))
-+ dev_info(dev, "Registered Qcom-QMP phy\n");
-+ else
-+ pm_runtime_disable(dev);
-+
-+ return PTR_ERR_OR_ZERO(phy_provider);
-+
-+err_node_put:
-+ pm_runtime_disable(dev);
-+ of_node_put(child);
-+ return ret;
-+}
-+
-+static struct platform_driver qcom_qmp_phy_driver = {
-+ .probe = qcom_qmp_phy_probe,
-+ .driver = {
-+ .name = "qcom-qmp-phy",
-+ .pm = &qcom_qmp_phy_pm_ops,
-+ .of_match_table = qcom_qmp_phy_of_match_table,
-+ },
-+};
-+
-+module_platform_driver(qcom_qmp_phy_driver);
-+
-+MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
-+MODULE_DESCRIPTION("Qualcomm QMP PHY driver");
-+MODULE_LICENSE("GPL v2");
-diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
-new file mode 100644
-index 000000000000..c7309e981bfb
---- /dev/null
-+++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
-@@ -0,0 +1,6350 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/clk-provider.h>
-+#include <linux/delay.h>
-+#include <linux/err.h>
-+#include <linux/io.h>
-+#include <linux/iopoll.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/of_device.h>
-+#include <linux/of_address.h>
-+#include <linux/phy/phy.h>
-+#include <linux/platform_device.h>
-+#include <linux/regulator/consumer.h>
-+#include <linux/reset.h>
-+#include <linux/slab.h>
-+
-+#include <dt-bindings/phy/phy.h>
-+
-+#include "phy-qcom-qmp.h"
-+
-+/* QPHY_SW_RESET bit */
-+#define SW_RESET BIT(0)
-+/* QPHY_POWER_DOWN_CONTROL */
-+#define SW_PWRDN BIT(0)
-+#define REFCLK_DRV_DSBL BIT(1)
-+/* QPHY_START_CONTROL bits */
-+#define SERDES_START BIT(0)
-+#define PCS_START BIT(1)
-+#define PLL_READY_GATE_EN BIT(3)
-+/* QPHY_PCS_STATUS bit */
-+#define PHYSTATUS BIT(6)
-+#define PHYSTATUS_4_20 BIT(7)
-+/* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */
-+#define PCS_READY BIT(0)
-+
-+/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
-+/* DP PHY soft reset */
-+#define SW_DPPHY_RESET BIT(0)
-+/* mux to select DP PHY reset control, 0:HW control, 1: software reset */
-+#define SW_DPPHY_RESET_MUX BIT(1)
-+/* USB3 PHY soft reset */
-+#define SW_USB3PHY_RESET BIT(2)
-+/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
-+#define SW_USB3PHY_RESET_MUX BIT(3)
-+
-+/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
-+#define USB3_MODE BIT(0) /* enables USB3 mode */
-+#define DP_MODE BIT(1) /* enables DP mode */
-+
-+/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
-+#define ARCVR_DTCT_EN BIT(0)
-+#define ALFPS_DTCT_EN BIT(1)
-+#define ARCVR_DTCT_EVENT_SEL BIT(4)
-+
-+/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
-+#define IRQ_CLEAR BIT(0)
-+
-+/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
-+#define RCVR_DETECT BIT(0)
-+
-+/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
-+#define CLAMP_EN BIT(0) /* enables i/o clamp_n */
-+
-+#define PHY_INIT_COMPLETE_TIMEOUT 10000
-+#define POWER_DOWN_DELAY_US_MIN 10
-+#define POWER_DOWN_DELAY_US_MAX 11
-+
-+#define MAX_PROP_NAME 32
-+
-+/* Define the assumed distance between lanes for underspecified device trees. */
-+#define QMP_PHY_LEGACY_LANE_STRIDE 0x400
-+
-+struct qmp_phy_init_tbl {
-+ unsigned int offset;
-+ unsigned int val;
-+ /*
-+ * register part of layout ?
-+ * if yes, then offset gives index in the reg-layout
-+ */
-+ bool in_layout;
-+ /*
-+ * mask of lanes for which this register is written
-+ * for cases when second lane needs different values
-+ */
-+ u8 lane_mask;
-+};
-+
-+#define QMP_PHY_INIT_CFG(o, v) \
-+ { \
-+ .offset = o, \
-+ .val = v, \
-+ .lane_mask = 0xff, \
-+ }
-+
-+#define QMP_PHY_INIT_CFG_L(o, v) \
-+ { \
-+ .offset = o, \
-+ .val = v, \
-+ .in_layout = true, \
-+ .lane_mask = 0xff, \
-+ }
-+
-+#define QMP_PHY_INIT_CFG_LANE(o, v, l) \
-+ { \
-+ .offset = o, \
-+ .val = v, \
-+ .lane_mask = l, \
-+ }
-+
-+/* set of registers with offsets different per-PHY */
-+enum qphy_reg_layout {
-+ /* Common block control registers */
-+ QPHY_COM_SW_RESET,
-+ QPHY_COM_POWER_DOWN_CONTROL,
-+ QPHY_COM_START_CONTROL,
-+ QPHY_COM_PCS_READY_STATUS,
-+ /* PCS registers */
-+ QPHY_PLL_LOCK_CHK_DLY_TIME,
-+ QPHY_FLL_CNTRL1,
-+ QPHY_FLL_CNTRL2,
-+ QPHY_FLL_CNT_VAL_L,
-+ QPHY_FLL_CNT_VAL_H_TOL,
-+ QPHY_FLL_MAN_CODE,
-+ QPHY_SW_RESET,
-+ QPHY_START_CTRL,
-+ QPHY_PCS_READY_STATUS,
-+ QPHY_PCS_STATUS,
-+ QPHY_PCS_AUTONOMOUS_MODE_CTRL,
-+ QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
-+ QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
-+ QPHY_PCS_POWER_DOWN_CONTROL,
-+ /* PCS_MISC registers */
-+ QPHY_PCS_MISC_TYPEC_CTRL,
-+ /* Keep last to ensure regs_layout arrays are properly initialized */
-+ QPHY_LAYOUT_SIZE
-+};
-+
-+static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_START_CTRL] = 0x00,
-+ [QPHY_PCS_READY_STATUS] = 0x168,
-+};
-+
-+static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x44,
-+ [QPHY_PCS_STATUS] = 0x14,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
-+};
-+
-+static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_COM_SW_RESET] = 0x400,
-+ [QPHY_COM_POWER_DOWN_CONTROL] = 0x404,
-+ [QPHY_COM_START_CONTROL] = 0x408,
-+ [QPHY_COM_PCS_READY_STATUS] = 0x448,
-+ [QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8,
-+ [QPHY_FLL_CNTRL1] = 0xc4,
-+ [QPHY_FLL_CNTRL2] = 0xc8,
-+ [QPHY_FLL_CNT_VAL_L] = 0xcc,
-+ [QPHY_FLL_CNT_VAL_H_TOL] = 0xd0,
-+ [QPHY_FLL_MAN_CODE] = 0xd4,
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_STATUS] = 0x174,
-+};
-+
-+static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_FLL_CNTRL1] = 0xc0,
-+ [QPHY_FLL_CNTRL2] = 0xc4,
-+ [QPHY_FLL_CNT_VAL_L] = 0xc8,
-+ [QPHY_FLL_CNT_VAL_H_TOL] = 0xcc,
-+ [QPHY_FLL_MAN_CODE] = 0xd0,
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_STATUS] = 0x17c,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
-+};
-+
-+static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_STATUS] = 0x174,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
-+};
-+
-+static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_STATUS] = 0x174,
-+};
-+
-+static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_STATUS] = 0x2ac,
-+};
-+
-+static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x44,
-+ [QPHY_PCS_STATUS] = 0x14,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314,
-+};
-+
-+static const unsigned int qmp_v4_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x44,
-+ [QPHY_PCS_STATUS] = 0x14,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x608,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x614,
-+};
-+
-+static const unsigned int sm8350_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x44,
-+ [QPHY_PCS_STATUS] = 0x14,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x1008,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x1014,
-+};
-+
-+static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
-+ [QPHY_START_CTRL] = 0x08,
-+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0xd8,
-+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc,
-+ [QPHY_PCS_STATUS] = 0x174,
-+ [QPHY_PCS_MISC_TYPEC_CTRL] = 0x00,
-+};
-+
-+static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_START_CTRL] = 0x00,
-+ [QPHY_PCS_READY_STATUS] = 0x160,
-+};
-+
-+static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_START_CTRL] = 0x00,
-+ [QPHY_PCS_READY_STATUS] = 0x168,
-+};
-+
-+static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_SW_RESET] = 0x00,
-+ [QPHY_START_CTRL] = 0x44,
-+ [QPHY_PCS_STATUS] = 0x14,
-+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
-+};
-+
-+static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-+ [QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START,
-+ [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS,
-+ [QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET,
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
-+ /* PLL and Loop filter settings */
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-+ /* SSC settings */
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
-+ QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
-+
-+ QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
-+
-+ QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
-+ QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
-+ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
-+ /* PLL and Loop filter settings */
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-+ /* SSC settings */
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
-+ /* FLL settings */
-+ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03),
-+ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02),
-+ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42),
-+ QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
-+
-+ /* Lock Det settings */
-+ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x61),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d),
-+ QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10),
-+ QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_PRE, 0x00),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_POST, 0x58),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
-+ QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
-+ QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
-+ QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
-+ QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
-+ QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
-+ QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
-+ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
-+ QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
-+ QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = {
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09),
-+ QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
-+ /* FLL settings */
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+
-+ /* Lock Det settings */
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
-+ /* FLL settings */
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+
-+ /* Lock Det settings */
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
-+};
-+
-+static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
-+
-+ /* Rate B */
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),
-+};
-+
-+static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-+ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B),
-+};
-+
-+static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_RX_PWM_GEAR_BAND, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_CTRL2, 0x6d),
-+ QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_DRV_LVL, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_DRV_LVL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
-+ QMP_PHY_INIT_CFG(QPHY_RX_SYM_RESYNC_CTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
-+ QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
-+
-+ /* Rate B */
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
-+};
-+
-+static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
-+};
-+
-+static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
-+
-+ /* Rate B */
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
-+
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
-+ /* Lock Det settings */
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20),
-+};
-+
-+static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
-+};
-+
-+static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5),
-+};
-+
-+static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
-+};
-+
-+static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),
-+};
-+
-+static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b),
-+};
-+
-+static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
-+
-+ /* Rate B */
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1),
-+ QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-+};
-+
-+static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01),
-+};
-+
-+static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00),
-+};
-+
-+static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
-+
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05),
-+
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
-+
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
-+
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
-+};
-+
-+/* Register names should be validated, they might be different for this PHY */
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e),
-+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99),
-+};
-+
-+static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),
-+ QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
-+};
-+
-+struct qmp_phy;
-+
-+/* struct qmp_phy_cfg - per-PHY initialization config */
-+struct qmp_phy_cfg {
-+ /* phy-type - PCIE/UFS/USB */
-+ unsigned int type;
-+ /* number of lanes provided by phy */
-+ int nlanes;
-+
-+ /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
-+ const struct qmp_phy_init_tbl *serdes_tbl;
-+ int serdes_tbl_num;
-+ const struct qmp_phy_init_tbl *serdes_tbl_sec;
-+ int serdes_tbl_num_sec;
-+ const struct qmp_phy_init_tbl *tx_tbl;
-+ int tx_tbl_num;
-+ const struct qmp_phy_init_tbl *tx_tbl_sec;
-+ int tx_tbl_num_sec;
-+ const struct qmp_phy_init_tbl *rx_tbl;
-+ int rx_tbl_num;
-+ const struct qmp_phy_init_tbl *rx_tbl_sec;
-+ int rx_tbl_num_sec;
-+ const struct qmp_phy_init_tbl *pcs_tbl;
-+ int pcs_tbl_num;
-+ const struct qmp_phy_init_tbl *pcs_tbl_sec;
-+ int pcs_tbl_num_sec;
-+ const struct qmp_phy_init_tbl *pcs_misc_tbl;
-+ int pcs_misc_tbl_num;
-+ const struct qmp_phy_init_tbl *pcs_misc_tbl_sec;
-+ int pcs_misc_tbl_num_sec;
-+
-+ /* Init sequence for DP PHY block link rates */
-+ const struct qmp_phy_init_tbl *serdes_tbl_rbr;
-+ int serdes_tbl_rbr_num;
-+ const struct qmp_phy_init_tbl *serdes_tbl_hbr;
-+ int serdes_tbl_hbr_num;
-+ const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
-+ int serdes_tbl_hbr2_num;
-+ const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
-+ int serdes_tbl_hbr3_num;
-+
-+ /* DP PHY callbacks */
-+ int (*configure_dp_phy)(struct qmp_phy *qphy);
-+ void (*configure_dp_tx)(struct qmp_phy *qphy);
-+ int (*calibrate_dp_phy)(struct qmp_phy *qphy);
-+ void (*dp_aux_init)(struct qmp_phy *qphy);
-+
-+ /* clock ids to be requested */
-+ const char * const *clk_list;
-+ int num_clks;
-+ /* resets to be requested */
-+ const char * const *reset_list;
-+ int num_resets;
-+ /* regulators to be requested */
-+ const char * const *vreg_list;
-+ int num_vregs;
-+
-+ /* array of registers with different offsets */
-+ const unsigned int *regs;
-+
-+ unsigned int start_ctrl;
-+ unsigned int pwrdn_ctrl;
-+ unsigned int mask_com_pcs_ready;
-+ /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
-+ unsigned int phy_status;
-+
-+ /* true, if PHY has a separate PHY_COM control block */
-+ bool has_phy_com_ctrl;
-+ /* true, if PHY has a reset for individual lanes */
-+ bool has_lane_rst;
-+ /* true, if PHY needs delay after POWER_DOWN */
-+ bool has_pwrdn_delay;
-+ /* power_down delay in usec */
-+ int pwrdn_delay_min;
-+ int pwrdn_delay_max;
-+
-+ /* true, if PHY has a separate DP_COM control block */
-+ bool has_phy_dp_com_ctrl;
-+ /* true, if PHY has secondary tx/rx lanes to be configured */
-+ bool is_dual_lane_phy;
-+
-+ /* true, if PCS block has no separate SW_RESET register */
-+ bool no_pcs_sw_reset;
-+};
-+
-+struct qmp_phy_combo_cfg {
-+ const struct qmp_phy_cfg *usb_cfg;
-+ const struct qmp_phy_cfg *dp_cfg;
-+};
-+
-+/**
-+ * struct qmp_phy - per-lane phy descriptor
-+ *
-+ * @phy: generic phy
-+ * @cfg: phy specific configuration
-+ * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
-+ * @tx: iomapped memory space for lane's tx
-+ * @rx: iomapped memory space for lane's rx
-+ * @pcs: iomapped memory space for lane's pcs
-+ * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
-+ * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
-+ * @pcs_misc: iomapped memory space for lane's pcs_misc
-+ * @pipe_clk: pipe clock
-+ * @index: lane index
-+ * @qmp: QMP phy to which this lane belongs
-+ * @lane_rst: lane's reset controller
-+ * @mode: current PHY mode
-+ * @dp_aux_cfg: Display port aux config
-+ * @dp_opts: Display port optional config
-+ * @dp_clks: Display port clocks
-+ */
-+struct qmp_phy {
-+ struct phy *phy;
-+ const struct qmp_phy_cfg *cfg;
-+ void __iomem *serdes;
-+ void __iomem *tx;
-+ void __iomem *rx;
-+ void __iomem *pcs;
-+ void __iomem *tx2;
-+ void __iomem *rx2;
-+ void __iomem *pcs_misc;
-+ struct clk *pipe_clk;
-+ unsigned int index;
-+ struct qcom_qmp *qmp;
-+ struct reset_control *lane_rst;
-+ enum phy_mode mode;
-+ unsigned int dp_aux_cfg;
-+ struct phy_configure_opts_dp dp_opts;
-+ struct qmp_phy_dp_clks *dp_clks;
-+};
-+
-+struct qmp_phy_dp_clks {
-+ struct qmp_phy *qphy;
-+ struct clk_hw dp_link_hw;
-+ struct clk_hw dp_pixel_hw;
-+};
-+
-+/**
-+ * struct qcom_qmp - structure holding QMP phy block attributes
-+ *
-+ * @dev: device
-+ * @dp_com: iomapped memory space for phy's dp_com control block
-+ *
-+ * @clks: array of clocks required by phy
-+ * @resets: array of resets required by phy
-+ * @vregs: regulator supplies bulk data
-+ *
-+ * @phys: array of per-lane phy descriptors
-+ * @phy_mutex: mutex lock for PHY common block initialization
-+ * @init_count: phy common block initialization count
-+ * @ufs_reset: optional UFS PHY reset handle
-+ */
-+struct qcom_qmp {
-+ struct device *dev;
-+ void __iomem *dp_com;
-+
-+ struct clk_bulk_data *clks;
-+ struct reset_control **resets;
-+ struct regulator_bulk_data *vregs;
-+
-+ struct qmp_phy **phys;
-+
-+ struct mutex phy_mutex;
-+ int init_count;
-+
-+ struct reset_control *ufs_reset;
-+};
-+
-+static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy);
-+static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy);
-+static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy);
-+static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy);
-+
-+static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy);
-+static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy);
-+static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy);
-+static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy);
-+
-+static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
-+{
-+ u32 reg;
-+
-+ reg = readl(base + offset);
-+ reg |= val;
-+ writel(reg, base + offset);
-+
-+ /* ensure that above write is through */
-+ readl(base + offset);
-+}
-+
-+static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
-+{
-+ u32 reg;
-+
-+ reg = readl(base + offset);
-+ reg &= ~val;
-+ writel(reg, base + offset);
-+
-+ /* ensure that above write is through */
-+ readl(base + offset);
-+}
-+
-+/* list of clocks required by phy */
-+static const char * const msm8996_phy_clk_l[] = {
-+ "aux", "cfg_ahb", "ref",
-+};
-+
-+static const char * const msm8996_ufs_phy_clk_l[] = {
-+ "ref",
-+};
-+
-+static const char * const qmp_v3_phy_clk_l[] = {
-+ "aux", "cfg_ahb", "ref", "com_aux",
-+};
-+
-+static const char * const sdm845_pciephy_clk_l[] = {
-+ "aux", "cfg_ahb", "ref", "refgen",
-+};
-+
-+static const char * const qmp_v4_phy_clk_l[] = {
-+ "aux", "ref_clk_src", "ref", "com_aux",
-+};
-+
-+/* the primary usb3 phy on sm8250 doesn't have a ref clock */
-+static const char * const qmp_v4_sm8250_usbphy_clk_l[] = {
-+ "aux", "ref_clk_src", "com_aux"
-+};
-+
-+static const char * const sm8450_ufs_phy_clk_l[] = {
-+ "qref", "ref", "ref_aux",
-+};
-+
-+static const char * const sdm845_ufs_phy_clk_l[] = {
-+ "ref", "ref_aux",
-+};
-+
-+/* usb3 phy on sdx55 doesn't have com_aux clock */
-+static const char * const qmp_v4_sdx55_usbphy_clk_l[] = {
-+ "aux", "cfg_ahb", "ref"
-+};
-+
-+static const char * const qcm2290_usb3phy_clk_l[] = {
-+ "cfg_ahb", "ref", "com_aux",
-+};
-+
-+/* list of resets */
-+static const char * const msm8996_pciephy_reset_l[] = {
-+ "phy", "common", "cfg",
-+};
-+
-+static const char * const msm8996_usb3phy_reset_l[] = {
-+ "phy", "common",
-+};
-+
-+static const char * const sc7180_usb3phy_reset_l[] = {
-+ "phy",
-+};
-+
-+static const char * const qcm2290_usb3phy_reset_l[] = {
-+ "phy_phy", "phy",
-+};
-+
-+static const char * const sdm845_pciephy_reset_l[] = {
-+ "phy",
-+};
-+
-+/* list of regulators */
-+static const char * const qmp_phy_vreg_l[] = {
-+ "vdda-phy", "vdda-pll",
-+};
-+
-+static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = ipq8074_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
-+ .tx_tbl = msm8996_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
-+ .rx_tbl = ipq8074_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
-+ .pcs_tbl = ipq8074_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
-+ .clk_list = msm8996_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+};
-+
-+static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 3,
-+
-+ .serdes_tbl = msm8996_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
-+ .tx_tbl = msm8996_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8996_pcie_tx_tbl),
-+ .rx_tbl = msm8996_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(msm8996_pcie_rx_tbl),
-+ .pcs_tbl = msm8996_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
-+ .clk_list = msm8996_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-+ .reset_list = msm8996_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = pciephy_regs_layout,
-+
-+ .start_ctrl = PCS_START | PLL_READY_GATE_EN,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .mask_com_pcs_ready = PCS_READY,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_phy_com_ctrl = true,
-+ .has_lane_rst = true,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg msm8996_ufs_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = msm8996_ufs_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(msm8996_ufs_serdes_tbl),
-+ .tx_tbl = msm8996_ufs_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8996_ufs_tx_tbl),
-+ .rx_tbl = msm8996_ufs_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(msm8996_ufs_rx_tbl),
-+
-+ .clk_list = msm8996_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
-+
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+
-+ .regs = msm8996_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .no_pcs_sw_reset = true,
-+};
-+
-+static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = msm8996_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
-+ .tx_tbl = msm8996_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
-+ .rx_tbl = msm8996_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl),
-+ .pcs_tbl = msm8996_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
-+ .clk_list = msm8996_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+};
-+
-+static const char * const ipq8074_pciephy_clk_l[] = {
-+ "aux", "cfg_ahb",
-+};
-+/* list of resets */
-+static const char * const ipq8074_pciephy_reset_l[] = {
-+ "phy", "common",
-+};
-+
-+static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = ipq8074_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
-+ .tx_tbl = ipq8074_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
-+ .rx_tbl = ipq8074_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
-+ .pcs_tbl = ipq8074_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
-+ .clk_list = ipq8074_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
-+ .reset_list = ipq8074_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
-+ .vreg_list = NULL,
-+ .num_vregs = 0,
-+ .regs = pciephy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_phy_com_ctrl = false,
-+ .has_lane_rst = false,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = ipq6018_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl),
-+ .tx_tbl = ipq6018_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl),
-+ .rx_tbl = ipq6018_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
-+ .pcs_tbl = ipq6018_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
-+ .clk_list = ipq8074_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
-+ .reset_list = ipq8074_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
-+ .vreg_list = NULL,
-+ .num_vregs = 0,
-+ .regs = ipq_pciephy_gen3_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+
-+ .has_phy_com_ctrl = false,
-+ .has_lane_rst = false,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sdm845_qmp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
-+ .tx_tbl = sdm845_qmp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),
-+ .rx_tbl = sdm845_qmp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),
-+ .pcs_tbl = sdm845_qmp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sdm845_qmp_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sdm845_qmp_pciephy_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sdm845_qhp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
-+ .tx_tbl = sdm845_qhp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
-+ .rx_tbl = sdm845_qhp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl),
-+ .pcs_tbl = sdm845_qhp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sdm845_qhp_pciephy_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
-+ .serdes_tbl_sec = sm8250_qmp_gen3x1_pcie_serdes_tbl,
-+ .serdes_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
-+ .tx_tbl = sm8250_qmp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
-+ .rx_tbl = sm8250_qmp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
-+ .rx_tbl_sec = sm8250_qmp_gen3x1_pcie_rx_tbl,
-+ .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),
-+ .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
-+ .pcs_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_tbl,
-+ .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
-+ .pcs_misc_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
-+ .tx_tbl = sm8250_qmp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
-+ .tx_tbl_sec = sm8250_qmp_gen3x2_pcie_tx_tbl,
-+ .tx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),
-+ .rx_tbl = sm8250_qmp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
-+ .rx_tbl_sec = sm8250_qmp_gen3x2_pcie_rx_tbl,
-+ .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl),
-+ .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
-+ .pcs_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_tbl,
-+ .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
-+ .pcs_misc_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v3_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
-+ .tx_tbl = qmp_v3_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
-+ .rx_tbl = qmp_v3_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
-+ .pcs_tbl = qmp_v3_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
-+ .clk_list = qmp_v3_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v3_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
-+ .tx_tbl = qmp_v3_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
-+ .rx_tbl = qmp_v3_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
-+ .pcs_tbl = qmp_v3_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
-+ .clk_list = qmp_v3_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-+ .reset_list = sc7180_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sc7180_dpphy_cfg = {
-+ .type = PHY_TYPE_DP,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v3_dp_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
-+ .tx_tbl = qmp_v3_dp_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
-+
-+ .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr,
-+ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
-+ .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr,
-+ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
-+ .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2,
-+ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
-+ .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3,
-+ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
-+
-+ .clk_list = qmp_v3_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-+ .reset_list = sc7180_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+
-+ .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init,
-+ .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx,
-+ .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy,
-+ .calibrate_dp_phy = qcom_qmp_v3_dp_phy_calibrate,
-+};
-+
-+static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = {
-+ .usb_cfg = &sc7180_usb3phy_cfg,
-+ .dp_cfg = &sc7180_dpphy_cfg,
-+};
-+
-+static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
-+ .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v3_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sdm845_ufsphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
-+ .tx_tbl = sdm845_ufsphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
-+ .rx_tbl = sdm845_ufsphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
-+ .pcs_tbl = sdm845_ufsphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
-+ .clk_list = sdm845_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sdm845_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+ .no_pcs_sw_reset = true,
-+};
-+
-+static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm6115_ufsphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl),
-+ .tx_tbl = sm6115_ufsphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_tx_tbl),
-+ .rx_tbl = sm6115_ufsphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_rx_tbl),
-+ .pcs_tbl = sm6115_ufsphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl),
-+ .clk_list = sdm845_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm6115_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+
-+ .is_dual_lane_phy = false,
-+ .no_pcs_sw_reset = true,
-+};
-+
-+static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = msm8998_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
-+ .tx_tbl = msm8998_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8998_pcie_tx_tbl),
-+ .rx_tbl = msm8998_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(msm8998_pcie_rx_tbl),
-+ .pcs_tbl = msm8998_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
-+ .clk_list = msm8996_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-+ .reset_list = ipq8074_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = pciephy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+};
-+
-+static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = msm8998_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
-+ .tx_tbl = msm8998_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl),
-+ .rx_tbl = msm8998_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl),
-+ .pcs_tbl = msm8998_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
-+ .clk_list = msm8996_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sm8150_ufsphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl),
-+ .tx_tbl = sm8150_ufsphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx_tbl),
-+ .rx_tbl = sm8150_ufsphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx_tbl),
-+ .pcs_tbl = sm8150_ufsphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl),
-+ .clk_list = sdm845_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8150_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
-+ .tx_tbl = sm8150_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl),
-+ .rx_tbl = sm8150_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl),
-+ .pcs_tbl = sm8150_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
-+ .clk_list = qmp_v4_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sc8180x_qmp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl),
-+ .tx_tbl = sc8180x_qmp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl),
-+ .rx_tbl = sc8180x_qmp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl),
-+ .pcs_tbl = sc8180x_qmp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sc8180x_qmp_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sc8180x_dpphy_cfg = {
-+ .type = PHY_TYPE_DP,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v4_dp_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
-+ .tx_tbl = qmp_v4_dp_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
-+
-+ .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
-+ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
-+ .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
-+ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
-+ .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
-+ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
-+ .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
-+ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
-+
-+ .clk_list = qmp_v3_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-+ .reset_list = sc7180_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v3_usb3phy_regs_layout,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+
-+ .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
-+ .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
-+ .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
-+ .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
-+};
-+
-+static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = {
-+ .usb_cfg = &sm8150_usb3phy_cfg,
-+ .dp_cfg = &sc8180x_dpphy_cfg,
-+};
-+
-+static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = sm8150_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),
-+ .rx_tbl = sm8150_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = sm8150_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v4_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3_uniphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
-+ .tx_tbl = sm8250_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl),
-+ .rx_tbl = sm8250_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl),
-+ .pcs_tbl = sm8250_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
-+ .clk_list = qmp_v4_sm8250_usbphy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = sm8250_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),
-+ .rx_tbl = sm8250_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v4_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3_uniphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sm8250_dpphy_cfg = {
-+ .type = PHY_TYPE_DP,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qmp_v4_dp_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
-+ .tx_tbl = qmp_v4_dp_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
-+
-+ .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
-+ .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
-+ .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
-+ .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
-+ .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
-+ .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
-+ .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
-+ .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
-+
-+ .clk_list = qmp_v4_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3phy_regs_layout,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+
-+ .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
-+ .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
-+ .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
-+ .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
-+};
-+
-+static const struct qmp_phy_combo_cfg sm8250_usb3dpphy_cfg = {
-+ .usb_cfg = &sm8250_usb3phy_cfg,
-+ .dp_cfg = &sm8250_dpphy_cfg,
-+};
-+
-+static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = sdx55_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl),
-+ .rx_tbl = sdx55_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v4_sdx55_usbphy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3_uniphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sdx55_qmp_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl),
-+ .tx_tbl = sdx55_qmp_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl),
-+ .rx_tbl = sdx55_qmp_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl),
-+ .pcs_tbl = sdx55_qmp_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sdx55_qmp_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = PCS_START | SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS_4_20,
-+
-+ .is_dual_lane_phy = true,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = sdx65_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl),
-+ .rx_tbl = sdx65_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v4_sdx55_usbphy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8350_usb3_uniphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sm8350_ufsphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
-+ .tx_tbl = sm8350_ufsphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
-+ .rx_tbl = sm8350_ufsphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
-+ .pcs_tbl = sm8350_ufsphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
-+ .clk_list = sdm845_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8150_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
-+ .tx_tbl = sm8350_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl),
-+ .rx_tbl = sm8350_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl),
-+ .pcs_tbl = sm8350_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl),
-+ .clk_list = qmp_v4_sm8250_usbphy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qmp_v4_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+
-+ .has_phy_dp_com_ctrl = true,
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-+ .tx_tbl = sm8350_usb3_uniphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),
-+ .rx_tbl = sm8350_usb3_uniphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),
-+ .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
-+ .clk_list = qmp_v4_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-+ .reset_list = msm8996_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8350_usb3_uniphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+};
-+
-+static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
-+ .type = PHY_TYPE_UFS,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sm8350_ufsphy_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
-+ .tx_tbl = sm8350_ufsphy_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
-+ .rx_tbl = sm8350_ufsphy_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
-+ .pcs_tbl = sm8350_ufsphy_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
-+ .clk_list = sm8450_ufs_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8150_ufsphy_regs_layout,
-+
-+ .start_ctrl = SERDES_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+};
-+
-+static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = sm8450_qmp_gen3x1_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl),
-+ .tx_tbl = sm8450_qmp_gen3x1_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl),
-+ .rx_tbl = sm8450_qmp_gen3x1_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl),
-+ .pcs_tbl = sm8450_qmp_gen3x1_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 2,
-+
-+ .serdes_tbl = sm8450_qmp_gen4x2_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl),
-+ .tx_tbl = sm8450_qmp_gen4x2_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl),
-+ .rx_tbl = sm8450_qmp_gen4x2_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl),
-+ .pcs_tbl = sm8450_qmp_gen4x2_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl),
-+ .pcs_misc_tbl = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl),
-+ .clk_list = sdm845_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-+ .reset_list = sdm845_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = sm8250_pcie_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .phy_status = PHYSTATUS_4_20,
-+
-+ .is_dual_lane_phy = true,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+};
-+
-+static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
-+ .type = PHY_TYPE_USB3,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = qcm2290_usb3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl),
-+ .tx_tbl = qcm2290_usb3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl),
-+ .rx_tbl = qcm2290_usb3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(qcm2290_usb3_rx_tbl),
-+ .pcs_tbl = qcm2290_usb3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl),
-+ .clk_list = qcm2290_usb3phy_clk_l,
-+ .num_clks = ARRAY_SIZE(qcm2290_usb3phy_clk_l),
-+ .reset_list = qcm2290_usb3phy_reset_l,
-+ .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
-+ .vreg_list = qmp_phy_vreg_l,
-+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-+ .regs = qcm2290_usb3phy_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
-+ .phy_status = PHYSTATUS,
-+
-+ .is_dual_lane_phy = true,
-+};
-+
-+static void qcom_qmp_phy_configure_lane(void __iomem *base,
-+ const unsigned int *regs,
-+ const struct qmp_phy_init_tbl tbl[],
-+ int num,
-+ u8 lane_mask)
-+{
-+ int i;
-+ const struct qmp_phy_init_tbl *t = tbl;
-+
-+ if (!t)
-+ return;
-+
-+ for (i = 0; i < num; i++, t++) {
-+ if (!(t->lane_mask & lane_mask))
-+ continue;
-+
-+ if (t->in_layout)
-+ writel(t->val, base + regs[t->offset]);
-+ else
-+ writel(t->val, base + t->offset);
-+ }
-+}
-+
-+static void qcom_qmp_phy_configure(void __iomem *base,
-+ const unsigned int *regs,
-+ const struct qmp_phy_init_tbl tbl[],
-+ int num)
-+{
-+ qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff);
-+}
-+
-+static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
-+{
-+ struct qcom_qmp *qmp = qphy->qmp;
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *serdes = qphy->serdes;
-+ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-+ const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
-+ int serdes_tbl_num = cfg->serdes_tbl_num;
-+ int ret;
-+
-+ qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
-+ if (cfg->serdes_tbl_sec)
-+ qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
-+ cfg->serdes_tbl_num_sec);
-+
-+ if (cfg->type == PHY_TYPE_DP) {
-+ switch (dp_opts->link_rate) {
-+ case 1620:
-+ qcom_qmp_phy_configure(serdes, cfg->regs,
-+ cfg->serdes_tbl_rbr,
-+ cfg->serdes_tbl_rbr_num);
-+ break;
-+ case 2700:
-+ qcom_qmp_phy_configure(serdes, cfg->regs,
-+ cfg->serdes_tbl_hbr,
-+ cfg->serdes_tbl_hbr_num);
-+ break;
-+ case 5400:
-+ qcom_qmp_phy_configure(serdes, cfg->regs,
-+ cfg->serdes_tbl_hbr2,
-+ cfg->serdes_tbl_hbr2_num);
-+ break;
-+ case 8100:
-+ qcom_qmp_phy_configure(serdes, cfg->regs,
-+ cfg->serdes_tbl_hbr3,
-+ cfg->serdes_tbl_hbr3_num);
-+ break;
-+ default:
-+ /* Other link rates aren't supported */
-+ return -EINVAL;
-+ }
-+ }
-+
-+
-+ if (cfg->has_phy_com_ctrl) {
-+ void __iomem *status;
-+ unsigned int mask, val;
-+
-+ qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
-+ qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
-+ SERDES_START | PCS_START);
-+
-+ status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
-+ mask = cfg->mask_com_pcs_ready;
-+
-+ ret = readl_poll_timeout(status, val, (val & mask), 10,
-+ PHY_INIT_COMPLETE_TIMEOUT);
-+ if (ret) {
-+ dev_err(qmp->dev,
-+ "phy common block init timed-out\n");
-+ return ret;
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy)
-+{
-+ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
-+ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
-+ qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+
-+ /* Turn on BIAS current for PHY/PLL */
-+ writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
-+ QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
-+ qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
-+
-+ writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+
-+ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
-+ DP_PHY_PD_CTL_LANE_0_1_PWRDN |
-+ DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
-+ DP_PHY_PD_CTL_DP_CLAMP_EN,
-+ qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+
-+ writel(QSERDES_V3_COM_BIAS_EN |
-+ QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
-+ QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL |
-+ QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
-+ qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
-+
-+ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
-+ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-+ writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
-+ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
-+ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
-+ writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
-+ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
-+ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
-+ writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
-+ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
-+ qphy->dp_aux_cfg = 0;
-+
-+ writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
-+ PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
-+ PHY_AUX_REQ_ERR_MASK,
-+ qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
-+}
-+
-+static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = {
-+ { 0x00, 0x0c, 0x15, 0x1a },
-+ { 0x02, 0x0e, 0x16, 0xff },
-+ { 0x02, 0x11, 0xff, 0xff },
-+ { 0x04, 0xff, 0xff, 0xff }
-+};
-+
-+static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = {
-+ { 0x02, 0x12, 0x16, 0x1a },
-+ { 0x09, 0x19, 0x1f, 0xff },
-+ { 0x10, 0x1f, 0xff, 0xff },
-+ { 0x1f, 0xff, 0xff, 0xff }
-+};
-+
-+static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = {
-+ { 0x00, 0x0c, 0x14, 0x19 },
-+ { 0x00, 0x0b, 0x12, 0xff },
-+ { 0x00, 0x0b, 0xff, 0xff },
-+ { 0x04, 0xff, 0xff, 0xff }
-+};
-+
-+static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = {
-+ { 0x08, 0x0f, 0x16, 0x1f },
-+ { 0x11, 0x1e, 0x1f, 0xff },
-+ { 0x19, 0x1f, 0xff, 0xff },
-+ { 0x1f, 0xff, 0xff, 0xff }
-+};
-+
-+static int qcom_qmp_phy_configure_dp_swing(struct qmp_phy *qphy,
-+ unsigned int drv_lvl_reg, unsigned int emp_post_reg)
-+{
-+ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-+ unsigned int v_level = 0, p_level = 0;
-+ u8 voltage_swing_cfg, pre_emphasis_cfg;
-+ int i;
-+
-+ for (i = 0; i < dp_opts->lanes; i++) {
-+ v_level = max(v_level, dp_opts->voltage[i]);
-+ p_level = max(p_level, dp_opts->pre[i]);
-+ }
-+
-+ if (dp_opts->link_rate <= 2700) {
-+ voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level];
-+ pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level];
-+ } else {
-+ voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr3_hbr2[v_level][p_level];
-+ pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr3_hbr2[v_level][p_level];
-+ }
-+
-+ /* TODO: Move check to config check */
-+ if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF)
-+ return -EINVAL;
-+
-+ /* Enable MUX to use Cursor values from these registers */
-+ voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
-+ pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
-+
-+ writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg);
-+ writel(pre_emphasis_cfg, qphy->tx + emp_post_reg);
-+ writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg);
-+ writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg);
-+
-+ return 0;
-+}
-+
-+static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy)
-+{
-+ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-+ u32 bias_en, drvr_en;
-+
-+ if (qcom_qmp_phy_configure_dp_swing(qphy,
-+ QSERDES_V3_TX_TX_DRV_LVL,
-+ QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0)
-+ return;
-+
-+ if (dp_opts->lanes == 1) {
-+ bias_en = 0x3e;
-+ drvr_en = 0x13;
-+ } else {
-+ bias_en = 0x3f;
-+ drvr_en = 0x10;
-+ }
-+
-+ writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN);
-+ writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
-+ writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN);
-+ writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
-+}
-+
-+static bool qcom_qmp_phy_configure_dp_mode(struct qmp_phy *qphy)
-+{
-+ u32 val;
-+ bool reverse = false;
-+
-+ val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
-+ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN;
-+
-+ /*
-+ * TODO: Assume orientation is CC1 for now and two lanes, need to
-+ * use type-c connector to understand orientation and lanes.
-+ *
-+ * Otherwise val changes to be like below if this code understood
-+ * the orientation of the type-c cable.
-+ *
-+ * if (lane_cnt == 4 || orientation == ORIENTATION_CC2)
-+ * val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN;
-+ * if (lane_cnt == 4 || orientation == ORIENTATION_CC1)
-+ * val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
-+ * if (orientation == ORIENTATION_CC2)
-+ * writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
-+ */
-+ val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
-+ writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+
-+ writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE);
-+
-+ return reverse;
-+}
-+
-+static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy)
-+{
-+ const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
-+ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-+ u32 phy_vco_div, status;
-+ unsigned long pixel_freq;
-+
-+ qcom_qmp_phy_configure_dp_mode(qphy);
-+
-+ writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
-+ writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
-+
-+ switch (dp_opts->link_rate) {
-+ case 1620:
-+ phy_vco_div = 0x1;
-+ pixel_freq = 1620000000UL / 2;
-+ break;
-+ case 2700:
-+ phy_vco_div = 0x1;
-+ pixel_freq = 2700000000UL / 2;
-+ break;
-+ case 5400:
-+ phy_vco_div = 0x2;
-+ pixel_freq = 5400000000UL / 4;
-+ break;
-+ case 8100:
-+ phy_vco_div = 0x0;
-+ pixel_freq = 8100000000UL / 6;
-+ break;
-+ default:
-+ /* Other link rates aren't supported */
-+ return -EINVAL;
-+ }
-+ writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV);
-+
-+ clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
-+ clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
-+
-+ writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
-+ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL);
-+
-+ if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS,
-+ status,
-+ ((status & BIT(0)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
-+ status,
-+ ((status & BIT(1)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ udelay(2000);
-+ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
-+ status,
-+ ((status & BIT(1)) > 0),
-+ 500,
-+ 10000);
-+}
-+
-+/*
-+ * We need to calibrate the aux setting here as many times
-+ * as the caller tries
-+ */
-+static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy)
-+{
-+ static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d };
-+ u8 val;
-+
-+ qphy->dp_aux_cfg++;
-+ qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
-+ val = cfg1_settings[qphy->dp_aux_cfg];
-+
-+ writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-+
-+ return 0;
-+}
-+
-+static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy)
-+{
-+ writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
-+ DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
-+ qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+
-+ /* Turn on BIAS current for PHY/PLL */
-+ writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN);
-+
-+ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
-+ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-+ writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
-+ writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
-+ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
-+ writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
-+ writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
-+ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
-+ writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
-+ writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
-+ qphy->dp_aux_cfg = 0;
-+
-+ writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
-+ PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
-+ PHY_AUX_REQ_ERR_MASK,
-+ qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
-+}
-+
-+static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy)
-+{
-+ /* Program default values before writing proper values */
-+ writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
-+ writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
-+
-+ writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
-+ writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
-+
-+ qcom_qmp_phy_configure_dp_swing(qphy,
-+ QSERDES_V4_TX_TX_DRV_LVL,
-+ QSERDES_V4_TX_TX_EMP_POST1_LVL);
-+}
-+
-+static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy)
-+{
-+ const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
-+ const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-+ u32 phy_vco_div, status;
-+ unsigned long pixel_freq;
-+ u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
-+ bool reverse;
-+
-+ writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1);
-+
-+ reverse = qcom_qmp_phy_configure_dp_mode(qphy);
-+
-+ writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-+ writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
-+
-+ writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL);
-+ writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL);
-+
-+ switch (dp_opts->link_rate) {
-+ case 1620:
-+ phy_vco_div = 0x1;
-+ pixel_freq = 1620000000UL / 2;
-+ break;
-+ case 2700:
-+ phy_vco_div = 0x1;
-+ pixel_freq = 2700000000UL / 2;
-+ break;
-+ case 5400:
-+ phy_vco_div = 0x2;
-+ pixel_freq = 5400000000UL / 4;
-+ break;
-+ case 8100:
-+ phy_vco_div = 0x0;
-+ pixel_freq = 8100000000UL / 6;
-+ break;
-+ default:
-+ /* Other link rates aren't supported */
-+ return -EINVAL;
-+ }
-+ writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV);
-+
-+ clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
-+ clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
-+
-+ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL);
-+
-+ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS,
-+ status,
-+ ((status & BIT(0)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
-+ status,
-+ ((status & BIT(0)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
-+ status,
-+ ((status & BIT(1)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
-+ status,
-+ ((status & BIT(0)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
-+ status,
-+ ((status & BIT(1)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ /*
-+ * At least for 7nm DP PHY this has to be done after enabling link
-+ * clock.
-+ */
-+
-+ if (dp_opts->lanes == 1) {
-+ bias0_en = reverse ? 0x3e : 0x15;
-+ bias1_en = reverse ? 0x15 : 0x3e;
-+ drvr0_en = reverse ? 0x13 : 0x10;
-+ drvr1_en = reverse ? 0x10 : 0x13;
-+ } else if (dp_opts->lanes == 2) {
-+ bias0_en = reverse ? 0x3f : 0x15;
-+ bias1_en = reverse ? 0x15 : 0x3f;
-+ drvr0_en = 0x10;
-+ drvr1_en = 0x10;
-+ } else {
-+ bias0_en = 0x3f;
-+ bias1_en = 0x3f;
-+ drvr0_en = 0x10;
-+ drvr1_en = 0x10;
-+ }
-+
-+ writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN);
-+ writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
-+ writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN);
-+ writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
-+
-+ writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
-+ udelay(2000);
-+ writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
-+
-+ if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
-+ status,
-+ ((status & BIT(1)) > 0),
-+ 500,
-+ 10000))
-+ return -ETIMEDOUT;
-+
-+ writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV);
-+ writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV);
-+
-+ writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
-+ writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
-+
-+ writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
-+ writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
-+
-+ return 0;
-+}
-+
-+/*
-+ * We need to calibrate the aux setting here as many times
-+ * as the caller tries
-+ */
-+static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy)
-+{
-+ static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d };
-+ u8 val;
-+
-+ qphy->dp_aux_cfg++;
-+ qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
-+ val = cfg1_settings[qphy->dp_aux_cfg];
-+
-+ writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
-+{
-+ const struct phy_configure_opts_dp *dp_opts = &opts->dp;
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+
-+ memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts));
-+ if (qphy->dp_opts.set_voltages) {
-+ cfg->configure_dp_tx(qphy);
-+ qphy->dp_opts.set_voltages = 0;
-+ }
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_dp_phy_calibrate(struct phy *phy)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+
-+ if (cfg->calibrate_dp_phy)
-+ return cfg->calibrate_dp_phy(qphy);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
-+{
-+ struct qcom_qmp *qmp = qphy->qmp;
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *serdes = qphy->serdes;
-+ void __iomem *pcs = qphy->pcs;
-+ void __iomem *dp_com = qmp->dp_com;
-+ int ret, i;
-+
-+ mutex_lock(&qmp->phy_mutex);
-+ if (qmp->init_count++) {
-+ mutex_unlock(&qmp->phy_mutex);
-+ return 0;
-+ }
-+
-+ /* turn on regulator supplies */
-+ ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
-+ if (ret) {
-+ dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
-+ goto err_unlock;
-+ }
-+
-+ for (i = 0; i < cfg->num_resets; i++) {
-+ ret = reset_control_assert(qmp->resets[i]);
-+ if (ret) {
-+ dev_err(qmp->dev, "%s reset assert failed\n",
-+ cfg->reset_list[i]);
-+ goto err_disable_regulators;
-+ }
-+ }
-+
-+ for (i = cfg->num_resets - 1; i >= 0; i--) {
-+ ret = reset_control_deassert(qmp->resets[i]);
-+ if (ret) {
-+ dev_err(qmp->dev, "%s reset deassert failed\n",
-+ qphy->cfg->reset_list[i]);
-+ goto err_assert_reset;
-+ }
-+ }
-+
-+ ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
-+ if (ret)
-+ goto err_assert_reset;
-+
-+ if (cfg->has_phy_dp_com_ctrl) {
-+ qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
-+ SW_PWRDN);
-+ /* override hardware control for reset of qmp phy */
-+ qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
-+ SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
-+ SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
-+
-+ /* Default type-c orientation, i.e CC1 */
-+ qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02);
-+
-+ qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
-+ USB3_MODE | DP_MODE);
-+
-+ /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
-+ qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
-+ SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
-+ SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
-+
-+ qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
-+ qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
-+ }
-+
-+ if (cfg->has_phy_com_ctrl) {
-+ qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
-+ SW_PWRDN);
-+ } else {
-+ if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
-+ qphy_setbits(pcs,
-+ cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
-+ cfg->pwrdn_ctrl);
-+ else
-+ qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
-+ cfg->pwrdn_ctrl);
-+ }
-+
-+ mutex_unlock(&qmp->phy_mutex);
-+
-+ return 0;
-+
-+err_assert_reset:
-+ while (++i < cfg->num_resets)
-+ reset_control_assert(qmp->resets[i]);
-+err_disable_regulators:
-+ regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
-+err_unlock:
-+ mutex_unlock(&qmp->phy_mutex);
-+
-+ return ret;
-+}
-+
-+static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy)
-+{
-+ struct qcom_qmp *qmp = qphy->qmp;
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *serdes = qphy->serdes;
-+ int i = cfg->num_resets;
-+
-+ mutex_lock(&qmp->phy_mutex);
-+ if (--qmp->init_count) {
-+ mutex_unlock(&qmp->phy_mutex);
-+ return 0;
-+ }
-+
-+ reset_control_assert(qmp->ufs_reset);
-+ if (cfg->has_phy_com_ctrl) {
-+ qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
-+ SERDES_START | PCS_START);
-+ qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
-+ SW_RESET);
-+ qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
-+ SW_PWRDN);
-+ }
-+
-+ while (--i >= 0)
-+ reset_control_assert(qmp->resets[i]);
-+
-+ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
-+
-+ regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
-+
-+ mutex_unlock(&qmp->phy_mutex);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_init(struct phy *phy)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ struct qcom_qmp *qmp = qphy->qmp;
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ int ret;
-+ dev_vdbg(qmp->dev, "Initializing QMP phy\n");
-+
-+ if (cfg->no_pcs_sw_reset) {
-+ /*
-+ * Get UFS reset, which is delayed until now to avoid a
-+ * circular dependency where UFS needs its PHY, but the PHY
-+ * needs this UFS reset.
-+ */
-+ if (!qmp->ufs_reset) {
-+ qmp->ufs_reset =
-+ devm_reset_control_get_exclusive(qmp->dev,
-+ "ufsphy");
-+
-+ if (IS_ERR(qmp->ufs_reset)) {
-+ ret = PTR_ERR(qmp->ufs_reset);
-+ dev_err(qmp->dev,
-+ "failed to get UFS reset: %d\n",
-+ ret);
-+
-+ qmp->ufs_reset = NULL;
-+ return ret;
-+ }
-+ }
-+
-+ ret = reset_control_assert(qmp->ufs_reset);
-+ if (ret)
-+ return ret;
-+ }
-+
-+ ret = qcom_qmp_phy_com_init(qphy);
-+ if (ret)
-+ return ret;
-+
-+ if (cfg->type == PHY_TYPE_DP)
-+ cfg->dp_aux_init(qphy);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_power_on(struct phy *phy)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ struct qcom_qmp *qmp = qphy->qmp;
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *tx = qphy->tx;
-+ void __iomem *rx = qphy->rx;
-+ void __iomem *pcs = qphy->pcs;
-+ void __iomem *pcs_misc = qphy->pcs_misc;
-+ void __iomem *status;
-+ unsigned int mask, val, ready;
-+ int ret;
-+
-+ qcom_qmp_phy_serdes_init(qphy);
-+
-+ if (cfg->has_lane_rst) {
-+ ret = reset_control_deassert(qphy->lane_rst);
-+ if (ret) {
-+ dev_err(qmp->dev, "lane%d reset deassert failed\n",
-+ qphy->index);
-+ return ret;
-+ }
-+ }
-+
-+ ret = clk_prepare_enable(qphy->pipe_clk);
-+ if (ret) {
-+ dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
-+ goto err_reset_lane;
-+ }
-+
-+ /* Tx, Rx, and PCS configurations */
-+ qcom_qmp_phy_configure_lane(tx, cfg->regs,
-+ cfg->tx_tbl, cfg->tx_tbl_num, 1);
-+ if (cfg->tx_tbl_sec)
-+ qcom_qmp_phy_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
-+ cfg->tx_tbl_num_sec, 1);
-+
-+ /* Configuration for other LANE for USB-DP combo PHY */
-+ if (cfg->is_dual_lane_phy) {
-+ qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
-+ cfg->tx_tbl, cfg->tx_tbl_num, 2);
-+ if (cfg->tx_tbl_sec)
-+ qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
-+ cfg->tx_tbl_sec,
-+ cfg->tx_tbl_num_sec, 2);
-+ }
-+
-+ /* Configure special DP tx tunings */
-+ if (cfg->type == PHY_TYPE_DP)
-+ cfg->configure_dp_tx(qphy);
-+
-+ qcom_qmp_phy_configure_lane(rx, cfg->regs,
-+ cfg->rx_tbl, cfg->rx_tbl_num, 1);
-+ if (cfg->rx_tbl_sec)
-+ qcom_qmp_phy_configure_lane(rx, cfg->regs,
-+ cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1);
-+
-+ if (cfg->is_dual_lane_phy) {
-+ qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
-+ cfg->rx_tbl, cfg->rx_tbl_num, 2);
-+ if (cfg->rx_tbl_sec)
-+ qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
-+ cfg->rx_tbl_sec,
-+ cfg->rx_tbl_num_sec, 2);
-+ }
-+
-+ /* Configure link rate, swing, etc. */
-+ if (cfg->type == PHY_TYPE_DP) {
-+ cfg->configure_dp_phy(qphy);
-+ } else {
-+ qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
-+ if (cfg->pcs_tbl_sec)
-+ qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
-+ cfg->pcs_tbl_num_sec);
-+ }
-+
-+ ret = reset_control_deassert(qmp->ufs_reset);
-+ if (ret)
-+ goto err_disable_pipe_clk;
-+
-+ qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
-+ cfg->pcs_misc_tbl_num);
-+ if (cfg->pcs_misc_tbl_sec)
-+ qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
-+ cfg->pcs_misc_tbl_num_sec);
-+
-+ /*
-+ * Pull out PHY from POWER DOWN state.
-+ * This is active low enable signal to power-down PHY.
-+ */
-+ if(cfg->type == PHY_TYPE_PCIE)
-+ qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
-+
-+ if (cfg->has_pwrdn_delay)
-+ usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
-+
-+ if (cfg->type != PHY_TYPE_DP) {
-+ /* Pull PHY out of reset state */
-+ if (!cfg->no_pcs_sw_reset)
-+ qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
-+ /* start SerDes and Phy-Coding-Sublayer */
-+ qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
-+
-+ if (cfg->type == PHY_TYPE_UFS) {
-+ status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
-+ mask = PCS_READY;
-+ ready = PCS_READY;
-+ } else {
-+ status = pcs + cfg->regs[QPHY_PCS_STATUS];
-+ mask = cfg->phy_status;
-+ ready = 0;
-+ }
-+
-+ ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
-+ PHY_INIT_COMPLETE_TIMEOUT);
-+ if (ret) {
-+ dev_err(qmp->dev, "phy initialization timed-out\n");
-+ goto err_disable_pipe_clk;
-+ }
-+ }
-+ return 0;
-+
-+err_disable_pipe_clk:
-+ clk_disable_unprepare(qphy->pipe_clk);
-+err_reset_lane:
-+ if (cfg->has_lane_rst)
-+ reset_control_assert(qphy->lane_rst);
-+
-+ return ret;
-+}
-+
-+static int qcom_qmp_phy_power_off(struct phy *phy)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+
-+ clk_disable_unprepare(qphy->pipe_clk);
-+
-+ if (cfg->type == PHY_TYPE_DP) {
-+ /* Assert DP PHY power down */
-+ writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-+ } else {
-+ /* PHY reset */
-+ if (!cfg->no_pcs_sw_reset)
-+ qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
-+
-+ /* stop SerDes and Phy-Coding-Sublayer */
-+ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
-+
-+ /* Put PHY into POWER DOWN state: active low */
-+ if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
-+ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
-+ cfg->pwrdn_ctrl);
-+ } else {
-+ qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
-+ cfg->pwrdn_ctrl);
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_exit(struct phy *phy)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+
-+ if (cfg->has_lane_rst)
-+ reset_control_assert(qphy->lane_rst);
-+
-+ qcom_qmp_phy_com_exit(qphy);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_enable(struct phy *phy)
-+{
-+ int ret;
-+
-+ ret = qcom_qmp_phy_init(phy);
-+ if (ret)
-+ return ret;
-+
-+ ret = qcom_qmp_phy_power_on(phy);
-+ if (ret)
-+ qcom_qmp_phy_exit(phy);
-+
-+ return ret;
-+}
-+
-+static int qcom_qmp_phy_disable(struct phy *phy)
-+{
-+ int ret;
-+
-+ ret = qcom_qmp_phy_power_off(phy);
-+ if (ret)
-+ return ret;
-+ return qcom_qmp_phy_exit(phy);
-+}
-+
-+static int qcom_qmp_phy_set_mode(struct phy *phy,
-+ enum phy_mode mode, int submode)
-+{
-+ struct qmp_phy *qphy = phy_get_drvdata(phy);
-+
-+ qphy->mode = mode;
-+
-+ return 0;
-+}
-+
-+static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
-+{
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *pcs = qphy->pcs;
-+ void __iomem *pcs_misc = qphy->pcs_misc;
-+ u32 intr_mask;
-+
-+ if (qphy->mode == PHY_MODE_USB_HOST_SS ||
-+ qphy->mode == PHY_MODE_USB_DEVICE_SS)
-+ intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
-+ else
-+ intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
-+
-+ /* Clear any pending interrupts status */
-+ qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
-+ /* Writing 1 followed by 0 clears the interrupt */
-+ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
-+
-+ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
-+ ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
-+
-+ /* Enable required PHY autonomous mode interrupts */
-+ qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
-+
-+ /* Enable i/o clamp_n for autonomous mode */
-+ if (pcs_misc)
-+ qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
-+}
-+
-+static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
-+{
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ void __iomem *pcs = qphy->pcs;
-+ void __iomem *pcs_misc = qphy->pcs_misc;
-+
-+ /* Disable i/o clamp_n on resume for normal mode */
-+ if (pcs_misc)
-+ qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
-+
-+ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
-+ ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
-+
-+ qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
-+ /* Writing 1 followed by 0 clears the interrupt */
-+ qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
-+}
-+
-+static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ struct qmp_phy *qphy = qmp->phys[0];
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+
-+ dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode);
-+
-+ /* Supported only for USB3 PHY and luckily USB3 is the first phy */
-+ if (cfg->type != PHY_TYPE_USB3)
-+ return 0;
-+
-+ if (!qmp->init_count) {
-+ dev_vdbg(dev, "PHY not initialized, bailing out\n");
-+ return 0;
-+ }
-+
-+ qcom_qmp_phy_enable_autonomous_mode(qphy);
-+
-+ clk_disable_unprepare(qphy->pipe_clk);
-+ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
-+
-+ return 0;
-+}
-+
-+static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ struct qmp_phy *qphy = qmp->phys[0];
-+ const struct qmp_phy_cfg *cfg = qphy->cfg;
-+ int ret = 0;
-+
-+ dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode);
-+
-+ /* Supported only for USB3 PHY and luckily USB3 is the first phy */
-+ if (cfg->type != PHY_TYPE_USB3)
-+ return 0;
-+
-+ if (!qmp->init_count) {
-+ dev_vdbg(dev, "PHY not initialized, bailing out\n");
-+ return 0;
-+ }
-+
-+ ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
-+ if (ret)
-+ return ret;
-+
-+ ret = clk_prepare_enable(qphy->pipe_clk);
-+ if (ret) {
-+ dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
-+ clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
-+ return ret;
-+ }
-+
-+ qcom_qmp_phy_disable_autonomous_mode(qphy);
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ int num = cfg->num_vregs;
-+ int i;
-+
-+ qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
-+ if (!qmp->vregs)
-+ return -ENOMEM;
-+
-+ for (i = 0; i < num; i++)
-+ qmp->vregs[i].supply = cfg->vreg_list[i];
-+
-+ return devm_regulator_bulk_get(dev, num, qmp->vregs);
-+}
-+
-+static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ int i;
-+
-+ qmp->resets = devm_kcalloc(dev, cfg->num_resets,
-+ sizeof(*qmp->resets), GFP_KERNEL);
-+ if (!qmp->resets)
-+ return -ENOMEM;
-+
-+ for (i = 0; i < cfg->num_resets; i++) {
-+ struct reset_control *rst;
-+ const char *name = cfg->reset_list[i];
-+
-+ rst = devm_reset_control_get_exclusive(dev, name);
-+ if (IS_ERR(rst)) {
-+ dev_err(dev, "failed to get %s reset\n", name);
-+ return PTR_ERR(rst);
-+ }
-+ qmp->resets[i] = rst;
-+ }
-+
-+ return 0;
-+}
-+
-+static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ int num = cfg->num_clks;
-+ int i;
-+
-+ qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
-+ if (!qmp->clks)
-+ return -ENOMEM;
-+
-+ for (i = 0; i < num; i++)
-+ qmp->clks[i].id = cfg->clk_list[i];
-+
-+ return devm_clk_bulk_get(dev, num, qmp->clks);
-+}
-+
-+static void phy_clk_release_provider(void *res)
-+{
-+ of_clk_del_provider(res);
-+}
-+
-+/*
-+ * Register a fixed rate pipe clock.
-+ *
-+ * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
-+ * controls it. The <s>_pipe_clk coming out of the GCC is requested
-+ * by the PHY driver for its operations.
-+ * We register the <s>_pipe_clksrc here. The gcc driver takes care
-+ * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
-+ * Below picture shows this relationship.
-+ *
-+ * +---------------+
-+ * | PHY block |<<---------------------------------------+
-+ * | | |
-+ * | +-------+ | +-----+ |
-+ * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
-+ * clk | +-------+ | +-----+
-+ * +---------------+
-+ */
-+static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
-+{
-+ struct clk_fixed_rate *fixed;
-+ struct clk_init_data init = { };
-+ int ret;
-+
-+ ret = of_property_read_string(np, "clock-output-names", &init.name);
-+ if (ret) {
-+ dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
-+ return ret;
-+ }
-+
-+ fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
-+ if (!fixed)
-+ return -ENOMEM;
-+
-+ init.ops = &clk_fixed_rate_ops;
-+
-+ /* controllers using QMP phys use 125MHz pipe clock interface */
-+ fixed->fixed_rate = 125000000;
-+ fixed->hw.init = &init;
-+
-+ ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
-+ if (ret)
-+ return ret;
-+
-+ ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
-+ if (ret)
-+ return ret;
-+
-+ /*
-+ * Roll a devm action because the clock provider is the child node, but
-+ * the child node is not actually a device.
-+ */
-+ return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
-+}
-+
-+/*
-+ * Display Port PLL driver block diagram for branch clocks
-+ *
-+ * +------------------------------+
-+ * | DP_VCO_CLK |
-+ * | |
-+ * | +-------------------+ |
-+ * | | (DP PLL/VCO) | |
-+ * | +---------+---------+ |
-+ * | v |
-+ * | +----------+-----------+ |
-+ * | | hsclk_divsel_clk_src | |
-+ * | +----------+-----------+ |
-+ * +------------------------------+
-+ * |
-+ * +---------<---------v------------>----------+
-+ * | |
-+ * +--------v----------------+ |
-+ * | dp_phy_pll_link_clk | |
-+ * | link_clk | |
-+ * +--------+----------------+ |
-+ * | |
-+ * | |
-+ * v v
-+ * Input to DISPCC block |
-+ * for link clk, crypto clk |
-+ * and interface clock |
-+ * |
-+ * |
-+ * +--------<------------+-----------------+---<---+
-+ * | | |
-+ * +----v---------+ +--------v-----+ +--------v------+
-+ * | vco_divided | | vco_divided | | vco_divided |
-+ * | _clk_src | | _clk_src | | _clk_src |
-+ * | | | | | |
-+ * |divsel_six | | divsel_two | | divsel_four |
-+ * +-------+------+ +-----+--------+ +--------+------+
-+ * | | |
-+ * v---->----------v-------------<------v
-+ * |
-+ * +----------+-----------------+
-+ * | dp_phy_pll_vco_div_clk |
-+ * +---------+------------------+
-+ * |
-+ * v
-+ * Input to DISPCC block
-+ * for DP pixel clock
-+ *
-+ */
-+static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw,
-+ struct clk_rate_request *req)
-+{
-+ switch (req->rate) {
-+ case 1620000000UL / 2:
-+ case 2700000000UL / 2:
-+ /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */
-+ return 0;
-+ default:
-+ return -EINVAL;
-+ }
-+}
-+
-+static unsigned long
-+qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
-+{
-+ const struct qmp_phy_dp_clks *dp_clks;
-+ const struct qmp_phy *qphy;
-+ const struct phy_configure_opts_dp *dp_opts;
-+
-+ dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw);
-+ qphy = dp_clks->qphy;
-+ dp_opts = &qphy->dp_opts;
-+
-+ switch (dp_opts->link_rate) {
-+ case 1620:
-+ return 1620000000UL / 2;
-+ case 2700:
-+ return 2700000000UL / 2;
-+ case 5400:
-+ return 5400000000UL / 4;
-+ case 8100:
-+ return 8100000000UL / 6;
-+ default:
-+ return 0;
-+ }
-+}
-+
-+static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = {
-+ .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate,
-+ .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate,
-+};
-+
-+static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw,
-+ struct clk_rate_request *req)
-+{
-+ switch (req->rate) {
-+ case 162000000:
-+ case 270000000:
-+ case 540000000:
-+ case 810000000:
-+ return 0;
-+ default:
-+ return -EINVAL;
-+ }
-+}
-+
-+static unsigned long
-+qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
-+{
-+ const struct qmp_phy_dp_clks *dp_clks;
-+ const struct qmp_phy *qphy;
-+ const struct phy_configure_opts_dp *dp_opts;
-+
-+ dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw);
-+ qphy = dp_clks->qphy;
-+ dp_opts = &qphy->dp_opts;
-+
-+ switch (dp_opts->link_rate) {
-+ case 1620:
-+ case 2700:
-+ case 5400:
-+ case 8100:
-+ return dp_opts->link_rate * 100000;
-+ default:
-+ return 0;
-+ }
-+}
-+
-+static const struct clk_ops qcom_qmp_dp_link_clk_ops = {
-+ .determine_rate = qcom_qmp_dp_link_clk_determine_rate,
-+ .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate,
-+};
-+
-+static struct clk_hw *
-+qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data)
-+{
-+ struct qmp_phy_dp_clks *dp_clks = data;
-+ unsigned int idx = clkspec->args[0];
-+
-+ if (idx >= 2) {
-+ pr_err("%s: invalid index %u\n", __func__, idx);
-+ return ERR_PTR(-EINVAL);
-+ }
-+
-+ if (idx == 0)
-+ return &dp_clks->dp_link_hw;
-+
-+ return &dp_clks->dp_pixel_hw;
-+}
-+
-+static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy,
-+ struct device_node *np)
-+{
-+ struct clk_init_data init = { };
-+ struct qmp_phy_dp_clks *dp_clks;
-+ char name[64];
-+ int ret;
-+
-+ dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL);
-+ if (!dp_clks)
-+ return -ENOMEM;
-+
-+ dp_clks->qphy = qphy;
-+ qphy->dp_clks = dp_clks;
-+
-+ snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev));
-+ init.ops = &qcom_qmp_dp_link_clk_ops;
-+ init.name = name;
-+ dp_clks->dp_link_hw.init = &init;
-+ ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw);
-+ if (ret)
-+ return ret;
-+
-+ snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev));
-+ init.ops = &qcom_qmp_dp_pixel_clk_ops;
-+ init.name = name;
-+ dp_clks->dp_pixel_hw.init = &init;
-+ ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw);
-+ if (ret)
-+ return ret;
-+
-+ ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks);
-+ if (ret)
-+ return ret;
-+
-+ /*
-+ * Roll a devm action because the clock provider is the child node, but
-+ * the child node is not actually a device.
-+ */
-+ return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
-+}
-+
-+static const struct phy_ops qcom_qmp_phy_gen_ops = {
-+ .init = qcom_qmp_phy_enable,
-+ .exit = qcom_qmp_phy_disable,
-+ .set_mode = qcom_qmp_phy_set_mode,
-+ .owner = THIS_MODULE,
-+};
-+
-+static const struct phy_ops qcom_qmp_phy_dp_ops = {
-+ .init = qcom_qmp_phy_init,
-+ .configure = qcom_qmp_dp_phy_configure,
-+ .power_on = qcom_qmp_phy_power_on,
-+ .calibrate = qcom_qmp_dp_phy_calibrate,
-+ .power_off = qcom_qmp_phy_power_off,
-+ .exit = qcom_qmp_phy_exit,
-+ .set_mode = qcom_qmp_phy_set_mode,
-+ .owner = THIS_MODULE,
-+};
-+
-+static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
-+ .power_on = qcom_qmp_phy_enable,
-+ .power_off = qcom_qmp_phy_disable,
-+ .set_mode = qcom_qmp_phy_set_mode,
-+ .owner = THIS_MODULE,
-+};
-+
-+static void qcom_qmp_reset_control_put(void *data)
-+{
-+ reset_control_put(data);
-+}
-+
-+static
-+int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
-+ void __iomem *serdes, const struct qmp_phy_cfg *cfg)
-+{
-+ struct qcom_qmp *qmp = dev_get_drvdata(dev);
-+ struct phy *generic_phy;
-+ struct qmp_phy *qphy;
-+ const struct phy_ops *ops;
-+ char prop_name[MAX_PROP_NAME];
-+ int ret;
-+
-+ qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
-+ if (!qphy)
-+ return -ENOMEM;
-+
-+ qphy->cfg = cfg;
-+ qphy->serdes = serdes;
-+ /*
-+ * Get memory resources for each phy lane:
-+ * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
-+ * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
-+ * For single lane PHYs: pcs_misc (optional) -> 3.
-+ */
-+ qphy->tx = of_iomap(np, 0);
-+ if (!qphy->tx)
-+ return -ENOMEM;
-+
-+ qphy->rx = of_iomap(np, 1);
-+ if (!qphy->rx)
-+ return -ENOMEM;
-+
-+ qphy->pcs = of_iomap(np, 2);
-+ if (!qphy->pcs)
-+ return -ENOMEM;
-+
-+ /*
-+ * If this is a dual-lane PHY, then there should be registers for the
-+ * second lane. Some old device trees did not specify this, so fall
-+ * back to old legacy behavior of assuming they can be reached at an
-+ * offset from the first lane.
-+ */
-+ if (cfg->is_dual_lane_phy) {
-+ qphy->tx2 = of_iomap(np, 3);
-+ qphy->rx2 = of_iomap(np, 4);
-+ if (!qphy->tx2 || !qphy->rx2) {
-+ dev_warn(dev,
-+ "Underspecified device tree, falling back to legacy register regions\n");
-+
-+ /* In the old version, pcs_misc is at index 3. */
-+ qphy->pcs_misc = qphy->tx2;
-+ qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE;
-+ qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
-+
-+ } else {
-+ qphy->pcs_misc = of_iomap(np, 5);
-+ }
-+
-+ } else {
-+ qphy->pcs_misc = of_iomap(np, 3);
-+ }
-+
-+ if (!qphy->pcs_misc)
-+ dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
-+
-+ /*
-+ * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3
-+ * based phys, so they essentially have pipe clock. So,
-+ * we return error in case phy is USB3 or PIPE type.
-+ * Otherwise, we initialize pipe clock to NULL for
-+ * all phys that don't need this.
-+ */
-+ snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
-+ qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name);
-+ if (IS_ERR(qphy->pipe_clk)) {
-+ if (cfg->type == PHY_TYPE_PCIE ||
-+ cfg->type == PHY_TYPE_USB3) {
-+ ret = PTR_ERR(qphy->pipe_clk);
-+ if (ret != -EPROBE_DEFER)
-+ dev_err(dev,
-+ "failed to get lane%d pipe_clk, %d\n",
-+ id, ret);
-+ return ret;
-+ }
-+ qphy->pipe_clk = NULL;
-+ }
-+
-+ /* Get lane reset, if any */
-+ if (cfg->has_lane_rst) {
-+ snprintf(prop_name, sizeof(prop_name), "lane%d", id);
-+ qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name);
-+ if (IS_ERR(qphy->lane_rst)) {
-+ dev_err(dev, "failed to get lane%d reset\n", id);
-+ return PTR_ERR(qphy->lane_rst);
-+ }
-+ ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put,
-+ qphy->lane_rst);
-+ if (ret)
-+ return ret;
-+ }
-+
-+ if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE)
-+ ops = &qcom_qmp_pcie_ufs_ops;
-+ else if (cfg->type == PHY_TYPE_DP)
-+ ops = &qcom_qmp_phy_dp_ops;
-+ else
-+ ops = &qcom_qmp_phy_gen_ops;
-+
-+ generic_phy = devm_phy_create(dev, np, ops);
-+ if (IS_ERR(generic_phy)) {
-+ ret = PTR_ERR(generic_phy);
-+ dev_err(dev, "failed to create qphy %d\n", ret);
-+ return ret;
-+ }
-+
-+ qphy->phy = generic_phy;
-+ qphy->index = id;
-+ qphy->qmp = qmp;
-+ qmp->phys[id] = qphy;
-+ phy_set_drvdata(generic_phy, qphy);
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
-+ {
-+ .compatible = "qcom,ipq8074-qmp-usb3-phy",
-+ .data = &ipq8074_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,msm8996-qmp-pcie-phy",
-+ .data = &msm8996_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,msm8996-qmp-ufs-phy",
-+ .data = &msm8996_ufs_cfg,
-+ }, {
-+ .compatible = "qcom,msm8996-qmp-usb3-phy",
-+ .data = &msm8996_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,msm8998-qmp-pcie-phy",
-+ .data = &msm8998_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,msm8998-qmp-ufs-phy",
-+ .data = &sdm845_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,ipq8074-qmp-pcie-phy",
-+ .data = &ipq8074_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,ipq6018-qmp-pcie-phy",
-+ .data = &ipq6018_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,ipq6018-qmp-usb3-phy",
-+ .data = &ipq8074_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sc7180-qmp-usb3-phy",
-+ .data = &sc7180_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
-+ /* It's a combo phy */
-+ }, {
-+ .compatible = "qcom,sc8180x-qmp-pcie-phy",
-+ .data = &sc8180x_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sc8180x-qmp-ufs-phy",
-+ .data = &sm8150_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sc8280xp-qmp-ufs-phy",
-+ .data = &sm8350_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sc8180x-qmp-usb3-phy",
-+ .data = &sm8150_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
-+ /* It's a combo phy */
-+ }, {
-+ .compatible = "qcom,sdm845-qhp-pcie-phy",
-+ .data = &sdm845_qhp_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sdm845-qmp-pcie-phy",
-+ .data = &sdm845_qmp_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sdm845-qmp-usb3-phy",
-+ .data = &qmp_v3_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
-+ .data = &qmp_v3_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sdm845-qmp-ufs-phy",
-+ .data = &sdm845_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,msm8998-qmp-usb3-phy",
-+ .data = &msm8998_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sm6115-qmp-ufs-phy",
-+ .data = &sm6115_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm6350-qmp-ufs-phy",
-+ .data = &sdm845_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8150-qmp-ufs-phy",
-+ .data = &sm8150_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-ufs-phy",
-+ .data = &sm8150_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8150-qmp-usb3-phy",
-+ .data = &sm8150_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8150-qmp-usb3-uni-phy",
-+ .data = &sm8150_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-usb3-phy",
-+ .data = &sm8250_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
-+ /* It's a combo phy */
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-usb3-uni-phy",
-+ .data = &sm8250_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
-+ .data = &sm8250_qmp_gen3x1_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
-+ .data = &sm8250_qmp_gen3x2_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8350-qmp-ufs-phy",
-+ .data = &sm8350_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
-+ .data = &sm8250_qmp_gen3x2_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sdx55-qmp-pcie-phy",
-+ .data = &sdx55_qmp_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sdx55-qmp-usb3-uni-phy",
-+ .data = &sdx55_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sdx65-qmp-usb3-uni-phy",
-+ .data = &sdx65_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8350-qmp-usb3-phy",
-+ .data = &sm8350_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8350-qmp-usb3-uni-phy",
-+ .data = &sm8350_usb3_uniphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
-+ .data = &sm8450_qmp_gen3x1_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
-+ .data = &sm8450_qmp_gen4x2_pciephy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8450-qmp-ufs-phy",
-+ .data = &sm8450_ufsphy_cfg,
-+ }, {
-+ .compatible = "qcom,sm8450-qmp-usb3-phy",
-+ .data = &sm8350_usb3phy_cfg,
-+ }, {
-+ .compatible = "qcom,qcm2290-qmp-usb3-phy",
-+ .data = &qcm2290_usb3phy_cfg,
-+ },
-+ { },
-+};
-+MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
-+
-+static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = {
-+ {
-+ .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
-+ .data = &sc7180_usb3dpphy_cfg,
-+ },
-+ {
-+ .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
-+ .data = &sm8250_usb3dpphy_cfg,
-+ },
-+ {
-+ .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
-+ .data = &sc8180x_usb3dpphy_cfg,
-+ },
-+ { }
-+};
-+
-+static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
-+ SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
-+ qcom_qmp_phy_runtime_resume, NULL)
-+};
-+
-+static int qcom_qmp_phy_probe(struct platform_device *pdev)
-+{
-+ struct qcom_qmp *qmp;
-+ struct device *dev = &pdev->dev;
-+ struct device_node *child;
-+ struct phy_provider *phy_provider;
-+ void __iomem *serdes;
-+ void __iomem *usb_serdes;
-+ void __iomem *dp_serdes = NULL;
-+ const struct qmp_phy_combo_cfg *combo_cfg = NULL;
-+ const struct qmp_phy_cfg *cfg = NULL;
-+ const struct qmp_phy_cfg *usb_cfg = NULL;
-+ const struct qmp_phy_cfg *dp_cfg = NULL;
-+ int num, id, expected_phys;
-+ int ret;
-+
-+ qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
-+ if (!qmp)
-+ return -ENOMEM;
-+
-+ qmp->dev = dev;
-+ dev_set_drvdata(dev, qmp);
-+
-+ /* Get the specific init parameters of QMP phy */
-+ cfg = of_device_get_match_data(dev);
-+ if (!cfg) {
-+ const struct of_device_id *match;
-+
-+ match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev);
-+ if (!match)
-+ return -EINVAL;
-+
-+ combo_cfg = match->data;
-+ if (!combo_cfg)
-+ return -EINVAL;
-+
-+ usb_cfg = combo_cfg->usb_cfg;
-+ cfg = usb_cfg; /* Setup clks and regulators */
-+ }
-+
-+ /* per PHY serdes; usually located at base address */
-+ usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0);
-+ if (IS_ERR(serdes))
-+ return PTR_ERR(serdes);
-+
-+ /* per PHY dp_com; if PHY has dp_com control block */
-+ if (combo_cfg || cfg->has_phy_dp_com_ctrl) {
-+ qmp->dp_com = devm_platform_ioremap_resource(pdev, 1);
-+ if (IS_ERR(qmp->dp_com))
-+ return PTR_ERR(qmp->dp_com);
-+ }
-+
-+ if (combo_cfg) {
-+ /* Only two serdes for combo PHY */
-+ dp_serdes = devm_platform_ioremap_resource(pdev, 2);
-+ if (IS_ERR(dp_serdes))
-+ return PTR_ERR(dp_serdes);
-+
-+ dp_cfg = combo_cfg->dp_cfg;
-+ expected_phys = 2;
-+ } else {
-+ expected_phys = cfg->nlanes;
-+ }
-+
-+ mutex_init(&qmp->phy_mutex);
-+
-+ ret = qcom_qmp_phy_clk_init(dev, cfg);
-+ if (ret)
-+ return ret;
-+
-+ ret = qcom_qmp_phy_reset_init(dev, cfg);
-+ if (ret)
-+ return ret;
-+
-+ ret = qcom_qmp_phy_vreg_init(dev, cfg);
-+ if (ret) {
-+ if (ret != -EPROBE_DEFER)
-+ dev_err(dev, "failed to get regulator supplies: %d\n",
-+ ret);
-+ return ret;
-+ }
-+
-+ num = of_get_available_child_count(dev->of_node);
-+ /* do we have a rogue child node ? */
-+ if (num > expected_phys)
-+ return -EINVAL;
-+
-+ qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
-+ if (!qmp->phys)
-+ return -ENOMEM;
-+
-+ pm_runtime_set_active(dev);
-+ pm_runtime_enable(dev);
-+ /*
-+ * Prevent runtime pm from being ON by default. Users can enable
-+ * it using power/control in sysfs.
-+ */
-+ pm_runtime_forbid(dev);
-+
-+ id = 0;
-+ for_each_available_child_of_node(dev->of_node, child) {
-+ if (of_node_name_eq(child, "dp-phy")) {
-+ cfg = dp_cfg;
-+ serdes = dp_serdes;
-+ } else if (of_node_name_eq(child, "usb3-phy")) {
-+ cfg = usb_cfg;
-+ serdes = usb_serdes;
-+ }
-+
-+ /* Create per-lane phy */
-+ ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg);
-+ if (ret) {
-+ dev_err(dev, "failed to create lane%d phy, %d\n",
-+ id, ret);
-+ goto err_node_put;
-+ }
-+
-+ /*
-+ * Register the pipe clock provided by phy.
-+ * See function description to see details of this pipe clock.
-+ */
-+ if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) {
-+ ret = phy_pipe_clk_register(qmp, child);
-+ if (ret) {
-+ dev_err(qmp->dev,
-+ "failed to register pipe clock source\n");
-+ goto err_node_put;
-+ }
-+ } else if (cfg->type == PHY_TYPE_DP) {
-+ ret = phy_dp_clks_register(qmp, qmp->phys[id], child);
-+ if (ret) {
-+ dev_err(qmp->dev,
-+ "failed to register DP clock source\n");
-+ goto err_node_put;
-+ }
-+ }
-+ id++;
-+ }
-+
-+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
-+ if (!IS_ERR(phy_provider))
-+ dev_info(dev, "Registered Qcom-QMP phy\n");
-+ else
-+ pm_runtime_disable(dev);
-+
-+ return PTR_ERR_OR_ZERO(phy_provider);
-+
-+err_node_put:
-+ pm_runtime_disable(dev);
-+ of_node_put(child);
-+ return ret;
-+}
-+
-+static struct platform_driver qcom_qmp_phy_driver = {
-+ .probe = qcom_qmp_phy_probe,
-+ .driver = {
-+ .name = "qcom-qmp-phy",
-+ .pm = &qcom_qmp_phy_pm_ops,
-+ .of_match_table = qcom_qmp_phy_of_match_table,
-+ },
-+};
-+
-+module_platform_driver(qcom_qmp_phy_driver);
-+
-+MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
-+MODULE_DESCRIPTION("Qualcomm QMP PHY driver");
-+MODULE_LICENSE("GPL v2");
---
-2.35.1
-
+++ /dev/null
-From fbbf71f3740939c44dfb5411e2daf3bf0d8e8f41 Mon Sep 17 00:00:00 2001
-From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Date: Fri, 10 Jun 2022 21:55:41 +0300
-Subject: phy: qcom-qmp: fix msm8996 PCIe PHY support
-
-From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-
-commit fbbf71f3740939c44dfb5411e2daf3bf0d8e8f41 upstream.
-
-Replace init/exit ops with power_on/power_off which should be used for
-the PCIe PHYs to fix PHY initialization.
-
-Fixes: f575ac2d64e7 ("phy: qcom-qmp-pcie-msm8996: drop support for non-PCIe PHY types")
-Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Link: https://lore.kernel.org/r/20220610185542.3662484-2-dmitry.baryshkov@linaro.org
-Signed-off-by: Vinod Koul <vkoul@kernel.org>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
-+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
-@@ -867,8 +867,8 @@ static int phy_pipe_clk_register(struct
- }
-
- static const struct phy_ops qcom_qmp_phy_pcie_msm8996_ops = {
-- .init = qcom_qmp_phy_pcie_msm8996_enable,
-- .exit = qcom_qmp_phy_pcie_msm8996_disable,
-+ .power_on = qcom_qmp_phy_pcie_msm8996_enable,
-+ .power_off = qcom_qmp_phy_pcie_msm8996_disable,
- .set_mode = qcom_qmp_phy_pcie_msm8996_set_mode,
- .owner = THIS_MODULE,
- };
+++ /dev/null
-From 439ba35ff86af2152e588957e923ac3c29e45c92 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Wed, 8 Jun 2022 00:31:42 +0300
-Subject: phy: qcom-qmp-pcie: change symbol prefix to qcom_qmp_phy_pcie_msm8996
-
-From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-
-[ Upstream commit 2abf0c8e61a900a77f2262f54596973db572cabb ]
-
-Change all symbol names to start with qcom_qmp_phy_pcie_msm8996_ rather
-than old qcom_qmp_phy_.
-
-Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> # UFS, PCIe and USB on SC8180X
-Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Link: https://lore.kernel.org/r/20220607213203.2819885-10-dmitry.baryshkov@linaro.org
-Signed-off-by: Vinod Koul <vkoul@kernel.org>
-Stable-dep-of: 1f69ededf8e8 ("phy: qcom-qmp-pcie-msm8996: fix memleak on probe deferral")
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- .../phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 158 +++++++++---------
- 1 file changed, 79 insertions(+), 79 deletions(-)
-
-diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
-index 260e534b5607..1741a5675f9a 100644
---- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
-+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
-@@ -474,7 +474,7 @@ static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
- };
-
--static void qcom_qmp_phy_configure_lane(void __iomem *base,
-+static void qcom_qmp_phy_pcie_msm8996_configure_lane(void __iomem *base,
- const unsigned int *regs,
- const struct qmp_phy_init_tbl tbl[],
- int num,
-@@ -497,15 +497,15 @@ static void qcom_qmp_phy_configure_lane(void __iomem *base,
- }
- }
-
--static void qcom_qmp_phy_configure(void __iomem *base,
-+static void qcom_qmp_phy_pcie_msm8996_configure(void __iomem *base,
- const unsigned int *regs,
- const struct qmp_phy_init_tbl tbl[],
- int num)
- {
-- qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff);
-+ qcom_qmp_phy_pcie_msm8996_configure_lane(base, regs, tbl, num, 0xff);
- }
-
--static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
-+static int qcom_qmp_phy_pcie_msm8996_serdes_init(struct qmp_phy *qphy)
- {
- struct qcom_qmp *qmp = qphy->qmp;
- const struct qmp_phy_cfg *cfg = qphy->cfg;
-@@ -515,30 +515,30 @@ static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
- int serdes_tbl_num = cfg->serdes_tbl_num;
- int ret;
-
-- qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
-+ qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
- if (cfg->serdes_tbl_sec)
-- qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
-+ qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
- cfg->serdes_tbl_num_sec);
-
- if (cfg->type == PHY_TYPE_DP) {
- switch (dp_opts->link_rate) {
- case 1620:
-- qcom_qmp_phy_configure(serdes, cfg->regs,
-+ qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs,
- cfg->serdes_tbl_rbr,
- cfg->serdes_tbl_rbr_num);
- break;
- case 2700:
-- qcom_qmp_phy_configure(serdes, cfg->regs,
-+ qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs,
- cfg->serdes_tbl_hbr,
- cfg->serdes_tbl_hbr_num);
- break;
- case 5400:
-- qcom_qmp_phy_configure(serdes, cfg->regs,
-+ qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs,
- cfg->serdes_tbl_hbr2,
- cfg->serdes_tbl_hbr2_num);
- break;
- case 8100:
-- qcom_qmp_phy_configure(serdes, cfg->regs,
-+ qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs,
- cfg->serdes_tbl_hbr3,
- cfg->serdes_tbl_hbr3_num);
- break;
-@@ -602,7 +602,7 @@ static int qcom_qmp_dp_phy_calibrate(struct phy *phy)
- return 0;
- }
-
--static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
-+static int qcom_qmp_phy_pcie_msm8996_com_init(struct qmp_phy *qphy)
- {
- struct qcom_qmp *qmp = qphy->qmp;
- const struct qmp_phy_cfg *cfg = qphy->cfg;
-@@ -697,7 +697,7 @@ static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
- return ret;
- }
-
--static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy)
-+static int qcom_qmp_phy_pcie_msm8996_com_exit(struct qmp_phy *qphy)
- {
- struct qcom_qmp *qmp = qphy->qmp;
- const struct qmp_phy_cfg *cfg = qphy->cfg;
-@@ -732,7 +732,7 @@ static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy)
- return 0;
- }
-
--static int qcom_qmp_phy_init(struct phy *phy)
-+static int qcom_qmp_phy_pcie_msm8996_init(struct phy *phy)
- {
- struct qmp_phy *qphy = phy_get_drvdata(phy);
- struct qcom_qmp *qmp = qphy->qmp;
-@@ -767,7 +767,7 @@ static int qcom_qmp_phy_init(struct phy *phy)
- return ret;
- }
-
-- ret = qcom_qmp_phy_com_init(qphy);
-+ ret = qcom_qmp_phy_pcie_msm8996_com_init(qphy);
- if (ret)
- return ret;
-
-@@ -777,7 +777,7 @@ static int qcom_qmp_phy_init(struct phy *phy)
- return 0;
- }
-
--static int qcom_qmp_phy_power_on(struct phy *phy)
-+static int qcom_qmp_phy_pcie_msm8996_power_on(struct phy *phy)
- {
- struct qmp_phy *qphy = phy_get_drvdata(phy);
- struct qcom_qmp *qmp = qphy->qmp;
-@@ -790,7 +790,7 @@ static int qcom_qmp_phy_power_on(struct phy *phy)
- unsigned int mask, val, ready;
- int ret;
-
-- qcom_qmp_phy_serdes_init(qphy);
-+ qcom_qmp_phy_pcie_msm8996_serdes_init(qphy);
-
- if (cfg->has_lane_rst) {
- ret = reset_control_deassert(qphy->lane_rst);
-@@ -808,18 +808,18 @@ static int qcom_qmp_phy_power_on(struct phy *phy)
- }
-
- /* Tx, Rx, and PCS configurations */
-- qcom_qmp_phy_configure_lane(tx, cfg->regs,
-+ qcom_qmp_phy_pcie_msm8996_configure_lane(tx, cfg->regs,
- cfg->tx_tbl, cfg->tx_tbl_num, 1);
- if (cfg->tx_tbl_sec)
-- qcom_qmp_phy_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
-+ qcom_qmp_phy_pcie_msm8996_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
- cfg->tx_tbl_num_sec, 1);
-
- /* Configuration for other LANE for USB-DP combo PHY */
- if (cfg->is_dual_lane_phy) {
-- qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
-+ qcom_qmp_phy_pcie_msm8996_configure_lane(qphy->tx2, cfg->regs,
- cfg->tx_tbl, cfg->tx_tbl_num, 2);
- if (cfg->tx_tbl_sec)
-- qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
-+ qcom_qmp_phy_pcie_msm8996_configure_lane(qphy->tx2, cfg->regs,
- cfg->tx_tbl_sec,
- cfg->tx_tbl_num_sec, 2);
- }
-@@ -828,17 +828,17 @@ static int qcom_qmp_phy_power_on(struct phy *phy)
- if (cfg->type == PHY_TYPE_DP)
- cfg->configure_dp_tx(qphy);
-
-- qcom_qmp_phy_configure_lane(rx, cfg->regs,
-+ qcom_qmp_phy_pcie_msm8996_configure_lane(rx, cfg->regs,
- cfg->rx_tbl, cfg->rx_tbl_num, 1);
- if (cfg->rx_tbl_sec)
-- qcom_qmp_phy_configure_lane(rx, cfg->regs,
-+ qcom_qmp_phy_pcie_msm8996_configure_lane(rx, cfg->regs,
- cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1);
-
- if (cfg->is_dual_lane_phy) {
-- qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
-+ qcom_qmp_phy_pcie_msm8996_configure_lane(qphy->rx2, cfg->regs,
- cfg->rx_tbl, cfg->rx_tbl_num, 2);
- if (cfg->rx_tbl_sec)
-- qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
-+ qcom_qmp_phy_pcie_msm8996_configure_lane(qphy->rx2, cfg->regs,
- cfg->rx_tbl_sec,
- cfg->rx_tbl_num_sec, 2);
- }
-@@ -847,9 +847,9 @@ static int qcom_qmp_phy_power_on(struct phy *phy)
- if (cfg->type == PHY_TYPE_DP) {
- cfg->configure_dp_phy(qphy);
- } else {
-- qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
-+ qcom_qmp_phy_pcie_msm8996_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
- if (cfg->pcs_tbl_sec)
-- qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
-+ qcom_qmp_phy_pcie_msm8996_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
- cfg->pcs_tbl_num_sec);
- }
-
-@@ -857,10 +857,10 @@ static int qcom_qmp_phy_power_on(struct phy *phy)
- if (ret)
- goto err_disable_pipe_clk;
-
-- qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
-+ qcom_qmp_phy_pcie_msm8996_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
- cfg->pcs_misc_tbl_num);
- if (cfg->pcs_misc_tbl_sec)
-- qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
-+ qcom_qmp_phy_pcie_msm8996_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
- cfg->pcs_misc_tbl_num_sec);
-
- /*
-@@ -908,7 +908,7 @@ static int qcom_qmp_phy_power_on(struct phy *phy)
- return ret;
- }
-
--static int qcom_qmp_phy_power_off(struct phy *phy)
-+static int qcom_qmp_phy_pcie_msm8996_power_off(struct phy *phy)
- {
- struct qmp_phy *qphy = phy_get_drvdata(phy);
- const struct qmp_phy_cfg *cfg = qphy->cfg;
-@@ -939,7 +939,7 @@ static int qcom_qmp_phy_power_off(struct phy *phy)
- return 0;
- }
-
--static int qcom_qmp_phy_exit(struct phy *phy)
-+static int qcom_qmp_phy_pcie_msm8996_exit(struct phy *phy)
- {
- struct qmp_phy *qphy = phy_get_drvdata(phy);
- const struct qmp_phy_cfg *cfg = qphy->cfg;
-@@ -947,37 +947,37 @@ static int qcom_qmp_phy_exit(struct phy *phy)
- if (cfg->has_lane_rst)
- reset_control_assert(qphy->lane_rst);
-
-- qcom_qmp_phy_com_exit(qphy);
-+ qcom_qmp_phy_pcie_msm8996_com_exit(qphy);
-
- return 0;
- }
-
--static int qcom_qmp_phy_enable(struct phy *phy)
-+static int qcom_qmp_phy_pcie_msm8996_enable(struct phy *phy)
- {
- int ret;
-
-- ret = qcom_qmp_phy_init(phy);
-+ ret = qcom_qmp_phy_pcie_msm8996_init(phy);
- if (ret)
- return ret;
-
-- ret = qcom_qmp_phy_power_on(phy);
-+ ret = qcom_qmp_phy_pcie_msm8996_power_on(phy);
- if (ret)
-- qcom_qmp_phy_exit(phy);
-+ qcom_qmp_phy_pcie_msm8996_exit(phy);
-
- return ret;
- }
-
--static int qcom_qmp_phy_disable(struct phy *phy)
-+static int qcom_qmp_phy_pcie_msm8996_disable(struct phy *phy)
- {
- int ret;
-
-- ret = qcom_qmp_phy_power_off(phy);
-+ ret = qcom_qmp_phy_pcie_msm8996_power_off(phy);
- if (ret)
- return ret;
-- return qcom_qmp_phy_exit(phy);
-+ return qcom_qmp_phy_pcie_msm8996_exit(phy);
- }
-
--static int qcom_qmp_phy_set_mode(struct phy *phy,
-+static int qcom_qmp_phy_pcie_msm8996_set_mode(struct phy *phy,
- enum phy_mode mode, int submode)
- {
- struct qmp_phy *qphy = phy_get_drvdata(phy);
-@@ -987,7 +987,7 @@ static int qcom_qmp_phy_set_mode(struct phy *phy,
- return 0;
- }
-
--static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
-+static void qcom_qmp_phy_pcie_msm8996_enable_autonomous_mode(struct qmp_phy *qphy)
- {
- const struct qmp_phy_cfg *cfg = qphy->cfg;
- void __iomem *pcs = qphy->pcs;
-@@ -1016,7 +1016,7 @@ static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
- qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
- }
-
--static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
-+static void qcom_qmp_phy_pcie_msm8996_disable_autonomous_mode(struct qmp_phy *qphy)
- {
- const struct qmp_phy_cfg *cfg = qphy->cfg;
- void __iomem *pcs = qphy->pcs;
-@@ -1034,7 +1034,7 @@ static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
- qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
- }
-
--static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
-+static int __maybe_unused qcom_qmp_phy_pcie_msm8996_runtime_suspend(struct device *dev)
- {
- struct qcom_qmp *qmp = dev_get_drvdata(dev);
- struct qmp_phy *qphy = qmp->phys[0];
-@@ -1051,7 +1051,7 @@ static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
- return 0;
- }
-
-- qcom_qmp_phy_enable_autonomous_mode(qphy);
-+ qcom_qmp_phy_pcie_msm8996_enable_autonomous_mode(qphy);
-
- clk_disable_unprepare(qphy->pipe_clk);
- clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
-@@ -1059,7 +1059,7 @@ static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
- return 0;
- }
-
--static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
-+static int __maybe_unused qcom_qmp_phy_pcie_msm8996_runtime_resume(struct device *dev)
- {
- struct qcom_qmp *qmp = dev_get_drvdata(dev);
- struct qmp_phy *qphy = qmp->phys[0];
-@@ -1088,12 +1088,12 @@ static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
- return ret;
- }
-
-- qcom_qmp_phy_disable_autonomous_mode(qphy);
-+ qcom_qmp_phy_pcie_msm8996_disable_autonomous_mode(qphy);
-
- return 0;
- }
-
--static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
-+static int qcom_qmp_phy_pcie_msm8996_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
- {
- struct qcom_qmp *qmp = dev_get_drvdata(dev);
- int num = cfg->num_vregs;
-@@ -1109,7 +1109,7 @@ static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *
- return devm_regulator_bulk_get(dev, num, qmp->vregs);
- }
-
--static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
-+static int qcom_qmp_phy_pcie_msm8996_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
- {
- struct qcom_qmp *qmp = dev_get_drvdata(dev);
- int i;
-@@ -1134,7 +1134,7 @@ static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg
- return 0;
- }
-
--static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
-+static int qcom_qmp_phy_pcie_msm8996_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
- {
- struct qcom_qmp *qmp = dev_get_drvdata(dev);
- int num = cfg->num_clks;
-@@ -1402,28 +1402,28 @@ static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy,
- return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
- }
-
--static const struct phy_ops qcom_qmp_phy_gen_ops = {
-- .init = qcom_qmp_phy_enable,
-- .exit = qcom_qmp_phy_disable,
-- .set_mode = qcom_qmp_phy_set_mode,
-+static const struct phy_ops qcom_qmp_phy_pcie_msm8996_gen_ops = {
-+ .init = qcom_qmp_phy_pcie_msm8996_enable,
-+ .exit = qcom_qmp_phy_pcie_msm8996_disable,
-+ .set_mode = qcom_qmp_phy_pcie_msm8996_set_mode,
- .owner = THIS_MODULE,
- };
-
--static const struct phy_ops qcom_qmp_phy_dp_ops = {
-- .init = qcom_qmp_phy_init,
-+static const struct phy_ops qcom_qmp_phy_pcie_msm8996_dp_ops = {
-+ .init = qcom_qmp_phy_pcie_msm8996_init,
- .configure = qcom_qmp_dp_phy_configure,
-- .power_on = qcom_qmp_phy_power_on,
-+ .power_on = qcom_qmp_phy_pcie_msm8996_power_on,
- .calibrate = qcom_qmp_dp_phy_calibrate,
-- .power_off = qcom_qmp_phy_power_off,
-- .exit = qcom_qmp_phy_exit,
-- .set_mode = qcom_qmp_phy_set_mode,
-+ .power_off = qcom_qmp_phy_pcie_msm8996_power_off,
-+ .exit = qcom_qmp_phy_pcie_msm8996_exit,
-+ .set_mode = qcom_qmp_phy_pcie_msm8996_set_mode,
- .owner = THIS_MODULE,
- };
-
- static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
-- .power_on = qcom_qmp_phy_enable,
-- .power_off = qcom_qmp_phy_disable,
-- .set_mode = qcom_qmp_phy_set_mode,
-+ .power_on = qcom_qmp_phy_pcie_msm8996_enable,
-+ .power_off = qcom_qmp_phy_pcie_msm8996_disable,
-+ .set_mode = qcom_qmp_phy_pcie_msm8996_set_mode,
- .owner = THIS_MODULE,
- };
-
-@@ -1433,7 +1433,7 @@ static void qcom_qmp_reset_control_put(void *data)
- }
-
- static
--int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
-+int qcom_qmp_phy_pcie_msm8996_create(struct device *dev, struct device_node *np, int id,
- void __iomem *serdes, const struct qmp_phy_cfg *cfg)
- {
- struct qcom_qmp *qmp = dev_get_drvdata(dev);
-@@ -1535,9 +1535,9 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
- if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE)
- ops = &qcom_qmp_pcie_ufs_ops;
- else if (cfg->type == PHY_TYPE_DP)
-- ops = &qcom_qmp_phy_dp_ops;
-+ ops = &qcom_qmp_phy_pcie_msm8996_dp_ops;
- else
-- ops = &qcom_qmp_phy_gen_ops;
-+ ops = &qcom_qmp_phy_pcie_msm8996_gen_ops;
-
- generic_phy = devm_phy_create(dev, np, ops);
- if (IS_ERR(generic_phy)) {
-@@ -1555,21 +1555,21 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
- return 0;
- }
-
--static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
-+static const struct of_device_id qcom_qmp_phy_pcie_msm8996_of_match_table[] = {
- {
- .compatible = "qcom,msm8996-qmp-pcie-phy",
- .data = &msm8996_pciephy_cfg,
- },
- { },
- };
--MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
-+MODULE_DEVICE_TABLE(of, qcom_qmp_phy_pcie_msm8996_of_match_table);
-
--static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
-- SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
-- qcom_qmp_phy_runtime_resume, NULL)
-+static const struct dev_pm_ops qcom_qmp_phy_pcie_msm8996_pm_ops = {
-+ SET_RUNTIME_PM_OPS(qcom_qmp_phy_pcie_msm8996_runtime_suspend,
-+ qcom_qmp_phy_pcie_msm8996_runtime_resume, NULL)
- };
-
--static int qcom_qmp_phy_probe(struct platform_device *pdev)
-+static int qcom_qmp_phy_pcie_msm8996_probe(struct platform_device *pdev)
- {
- struct qcom_qmp *qmp;
- struct device *dev = &pdev->dev;
-@@ -1623,15 +1623,15 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
-
- mutex_init(&qmp->phy_mutex);
-
-- ret = qcom_qmp_phy_clk_init(dev, cfg);
-+ ret = qcom_qmp_phy_pcie_msm8996_clk_init(dev, cfg);
- if (ret)
- return ret;
-
-- ret = qcom_qmp_phy_reset_init(dev, cfg);
-+ ret = qcom_qmp_phy_pcie_msm8996_reset_init(dev, cfg);
- if (ret)
- return ret;
-
-- ret = qcom_qmp_phy_vreg_init(dev, cfg);
-+ ret = qcom_qmp_phy_pcie_msm8996_vreg_init(dev, cfg);
- if (ret) {
- if (ret != -EPROBE_DEFER)
- dev_err(dev, "failed to get regulator supplies: %d\n",
-@@ -1667,7 +1667,7 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
- }
-
- /* Create per-lane phy */
-- ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg);
-+ ret = qcom_qmp_phy_pcie_msm8996_create(dev, child, id, serdes, cfg);
- if (ret) {
- dev_err(dev, "failed to create lane%d phy, %d\n",
- id, ret);
-@@ -1710,16 +1710,16 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
- return ret;
- }
-
--static struct platform_driver qcom_qmp_phy_driver = {
-- .probe = qcom_qmp_phy_probe,
-+static struct platform_driver qcom_qmp_phy_pcie_msm8996_driver = {
-+ .probe = qcom_qmp_phy_pcie_msm8996_probe,
- .driver = {
- .name = "qcom-qmp-msm8996-pcie-phy",
-- .pm = &qcom_qmp_phy_pm_ops,
-- .of_match_table = qcom_qmp_phy_of_match_table,
-+ .pm = &qcom_qmp_phy_pcie_msm8996_pm_ops,
-+ .of_match_table = qcom_qmp_phy_pcie_msm8996_of_match_table,
- },
- };
-
--module_platform_driver(qcom_qmp_phy_driver);
-+module_platform_driver(qcom_qmp_phy_pcie_msm8996_driver);
-
- MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
- MODULE_DESCRIPTION("Qualcomm QMP MSM8996 PCIe PHY driver");
---
-2.35.1
-
+++ /dev/null
-From 2279b83eab0c0afe89c96f1609ddcfa54d5295e2 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Wed, 8 Jun 2022 00:31:54 +0300
-Subject: phy: qcom-qmp-pcie-msm8996: cleanup the driver
-
-From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-
-[ Upstream commit 4856865b0dec88570edfbdf3e9c3b551923c0768 ]
-
-Remove the conditionals and options that are not used by the MSM8996
-PCIe PHY device. Hardcode has_lane_rst and has_phy_com_ctrl as this is
-the case for this PHY.
-
-Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> # UFS, PCIe and USB on SC8180X
-Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Link: https://lore.kernel.org/r/20220607213203.2819885-22-dmitry.baryshkov@linaro.org
-Signed-off-by: Vinod Koul <vkoul@kernel.org>
-Stable-dep-of: 1f69ededf8e8 ("phy: qcom-qmp-pcie-msm8996: fix memleak on probe deferral")
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- .../phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 268 +++---------------
- 1 file changed, 41 insertions(+), 227 deletions(-)
-
-diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
-index 02e5ae7fa213..51da3a3a199e 100644
---- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
-+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
-@@ -266,22 +266,6 @@ struct qmp_phy_cfg {
- const struct qmp_phy_init_tbl *pcs_misc_tbl_sec;
- int pcs_misc_tbl_num_sec;
-
-- /* Init sequence for DP PHY block link rates */
-- const struct qmp_phy_init_tbl *serdes_tbl_rbr;
-- int serdes_tbl_rbr_num;
-- const struct qmp_phy_init_tbl *serdes_tbl_hbr;
-- int serdes_tbl_hbr_num;
-- const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
-- int serdes_tbl_hbr2_num;
-- const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
-- int serdes_tbl_hbr3_num;
--
-- /* DP PHY callbacks */
-- int (*configure_dp_phy)(struct qmp_phy *qphy);
-- void (*configure_dp_tx)(struct qmp_phy *qphy);
-- int (*calibrate_dp_phy)(struct qmp_phy *qphy);
-- void (*dp_aux_init)(struct qmp_phy *qphy);
--
- /* clock ids to be requested */
- const char * const *clk_list;
- int num_clks;
-@@ -301,28 +285,11 @@ struct qmp_phy_cfg {
- /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
- unsigned int phy_status;
-
-- /* true, if PHY has a separate PHY_COM control block */
-- bool has_phy_com_ctrl;
-- /* true, if PHY has a reset for individual lanes */
-- bool has_lane_rst;
- /* true, if PHY needs delay after POWER_DOWN */
- bool has_pwrdn_delay;
- /* power_down delay in usec */
- int pwrdn_delay_min;
- int pwrdn_delay_max;
--
-- /* true, if PHY has a separate DP_COM control block */
-- bool has_phy_dp_com_ctrl;
-- /* true, if PHY has secondary tx/rx lanes to be configured */
-- bool is_dual_lane_phy;
--
-- /* true, if PCS block has no separate SW_RESET register */
-- bool no_pcs_sw_reset;
--};
--
--struct qmp_phy_combo_cfg {
-- const struct qmp_phy_cfg *usb_cfg;
-- const struct qmp_phy_cfg *dp_cfg;
- };
-
- /**
-@@ -334,17 +301,12 @@ struct qmp_phy_combo_cfg {
- * @tx: iomapped memory space for lane's tx
- * @rx: iomapped memory space for lane's rx
- * @pcs: iomapped memory space for lane's pcs
-- * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
-- * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
- * @pcs_misc: iomapped memory space for lane's pcs_misc
- * @pipe_clk: pipe clock
- * @index: lane index
- * @qmp: QMP phy to which this lane belongs
- * @lane_rst: lane's reset controller
- * @mode: current PHY mode
-- * @dp_aux_cfg: Display port aux config
-- * @dp_opts: Display port optional config
-- * @dp_clks: Display port clocks
- */
- struct qmp_phy {
- struct phy *phy;
-@@ -353,30 +315,18 @@ struct qmp_phy {
- void __iomem *tx;
- void __iomem *rx;
- void __iomem *pcs;
-- void __iomem *tx2;
-- void __iomem *rx2;
- void __iomem *pcs_misc;
- struct clk *pipe_clk;
- unsigned int index;
- struct qcom_qmp *qmp;
- struct reset_control *lane_rst;
- enum phy_mode mode;
-- unsigned int dp_aux_cfg;
-- struct phy_configure_opts_dp dp_opts;
-- struct qmp_phy_dp_clks *dp_clks;
--};
--
--struct qmp_phy_dp_clks {
-- struct qmp_phy *qphy;
-- struct clk_hw dp_link_hw;
-- struct clk_hw dp_pixel_hw;
- };
-
- /**
- * struct qcom_qmp - structure holding QMP phy block attributes
- *
- * @dev: device
-- * @dp_com: iomapped memory space for phy's dp_com control block
- *
- * @clks: array of clocks required by phy
- * @resets: array of resets required by phy
-@@ -385,11 +335,9 @@ struct qmp_phy_dp_clks {
- * @phys: array of per-lane phy descriptors
- * @phy_mutex: mutex lock for PHY common block initialization
- * @init_count: phy common block initialization count
-- * @ufs_reset: optional UFS PHY reset handle
- */
- struct qcom_qmp {
- struct device *dev;
-- void __iomem *dp_com;
-
- struct clk_bulk_data *clks;
- struct reset_control **resets;
-@@ -399,8 +347,6 @@ struct qcom_qmp {
-
- struct mutex phy_mutex;
- int init_count;
--
-- struct reset_control *ufs_reset;
- };
-
- static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
-@@ -467,8 +413,6 @@ static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
- .mask_com_pcs_ready = PCS_READY,
- .phy_status = PHYSTATUS,
-
-- .has_phy_com_ctrl = true,
-- .has_lane_rst = true,
- .has_pwrdn_delay = true,
- .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-@@ -512,6 +456,8 @@ static int qcom_qmp_phy_pcie_msm8996_serdes_init(struct qmp_phy *qphy)
- void __iomem *serdes = qphy->serdes;
- const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
- int serdes_tbl_num = cfg->serdes_tbl_num;
-+ void __iomem *status;
-+ unsigned int mask, val;
- int ret;
-
- qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
-@@ -519,24 +465,20 @@ static int qcom_qmp_phy_pcie_msm8996_serdes_init(struct qmp_phy *qphy)
- qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
- cfg->serdes_tbl_num_sec);
-
-- if (cfg->has_phy_com_ctrl) {
-- void __iomem *status;
-- unsigned int mask, val;
-
-- qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
-- qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
-- SERDES_START | PCS_START);
-+ qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
-+ qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
-+ SERDES_START | PCS_START);
-
-- status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
-- mask = cfg->mask_com_pcs_ready;
-+ status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
-+ mask = cfg->mask_com_pcs_ready;
-
-- ret = readl_poll_timeout(status, val, (val & mask), 10,
-- PHY_INIT_COMPLETE_TIMEOUT);
-- if (ret) {
-- dev_err(qmp->dev,
-- "phy common block init timed-out\n");
-- return ret;
-- }
-+ ret = readl_poll_timeout(status, val, (val & mask), 10,
-+ PHY_INIT_COMPLETE_TIMEOUT);
-+ if (ret) {
-+ dev_err(qmp->dev,
-+ "phy common block init timed-out\n");
-+ return ret;
- }
-
- return 0;
-@@ -547,8 +489,6 @@ static int qcom_qmp_phy_pcie_msm8996_com_init(struct qmp_phy *qphy)
- struct qcom_qmp *qmp = qphy->qmp;
- const struct qmp_phy_cfg *cfg = qphy->cfg;
- void __iomem *serdes = qphy->serdes;
-- void __iomem *pcs = qphy->pcs;
-- void __iomem *dp_com = qmp->dp_com;
- int ret, i;
-
- mutex_lock(&qmp->phy_mutex);
-@@ -586,41 +526,8 @@ static int qcom_qmp_phy_pcie_msm8996_com_init(struct qmp_phy *qphy)
- if (ret)
- goto err_assert_reset;
-
-- if (cfg->has_phy_dp_com_ctrl) {
-- qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
-- SW_PWRDN);
-- /* override hardware control for reset of qmp phy */
-- qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
-- SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
-- SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
--
-- /* Default type-c orientation, i.e CC1 */
-- qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02);
--
-- qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
-- USB3_MODE | DP_MODE);
--
-- /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
-- qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
-- SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
-- SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
--
-- qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
-- qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
-- }
--
-- if (cfg->has_phy_com_ctrl) {
-- qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
-- SW_PWRDN);
-- } else {
-- if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
-- qphy_setbits(pcs,
-- cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
-- cfg->pwrdn_ctrl);
-- else
-- qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
-- cfg->pwrdn_ctrl);
-- }
-+ qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
-+ SW_PWRDN);
-
- mutex_unlock(&qmp->phy_mutex);
-
-@@ -650,15 +557,12 @@ static int qcom_qmp_phy_pcie_msm8996_com_exit(struct qmp_phy *qphy)
- return 0;
- }
-
-- reset_control_assert(qmp->ufs_reset);
-- if (cfg->has_phy_com_ctrl) {
-- qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
-- SERDES_START | PCS_START);
-- qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
-- SW_RESET);
-- qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
-- SW_PWRDN);
-- }
-+ qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
-+ SERDES_START | PCS_START);
-+ qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
-+ SW_RESET);
-+ qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
-+ SW_PWRDN);
-
- while (--i >= 0)
- reset_control_assert(qmp->resets[i]);
-@@ -676,37 +580,9 @@ static int qcom_qmp_phy_pcie_msm8996_init(struct phy *phy)
- {
- struct qmp_phy *qphy = phy_get_drvdata(phy);
- struct qcom_qmp *qmp = qphy->qmp;
-- const struct qmp_phy_cfg *cfg = qphy->cfg;
- int ret;
- dev_vdbg(qmp->dev, "Initializing QMP phy\n");
-
-- if (cfg->no_pcs_sw_reset) {
-- /*
-- * Get UFS reset, which is delayed until now to avoid a
-- * circular dependency where UFS needs its PHY, but the PHY
-- * needs this UFS reset.
-- */
-- if (!qmp->ufs_reset) {
-- qmp->ufs_reset =
-- devm_reset_control_get_exclusive(qmp->dev,
-- "ufsphy");
--
-- if (IS_ERR(qmp->ufs_reset)) {
-- ret = PTR_ERR(qmp->ufs_reset);
-- dev_err(qmp->dev,
-- "failed to get UFS reset: %d\n",
-- ret);
--
-- qmp->ufs_reset = NULL;
-- return ret;
-- }
-- }
--
-- ret = reset_control_assert(qmp->ufs_reset);
-- if (ret)
-- return ret;
-- }
--
- ret = qcom_qmp_phy_pcie_msm8996_com_init(qphy);
- if (ret)
- return ret;
-@@ -729,13 +605,11 @@ static int qcom_qmp_phy_pcie_msm8996_power_on(struct phy *phy)
-
- qcom_qmp_phy_pcie_msm8996_serdes_init(qphy);
-
-- if (cfg->has_lane_rst) {
-- ret = reset_control_deassert(qphy->lane_rst);
-- if (ret) {
-- dev_err(qmp->dev, "lane%d reset deassert failed\n",
-- qphy->index);
-- return ret;
-- }
-+ ret = reset_control_deassert(qphy->lane_rst);
-+ if (ret) {
-+ dev_err(qmp->dev, "lane%d reset deassert failed\n",
-+ qphy->index);
-+ return ret;
- }
-
- ret = clk_prepare_enable(qphy->pipe_clk);
-@@ -751,40 +625,17 @@ static int qcom_qmp_phy_pcie_msm8996_power_on(struct phy *phy)
- qcom_qmp_phy_pcie_msm8996_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
- cfg->tx_tbl_num_sec, 1);
-
-- /* Configuration for other LANE for USB-DP combo PHY */
-- if (cfg->is_dual_lane_phy) {
-- qcom_qmp_phy_pcie_msm8996_configure_lane(qphy->tx2, cfg->regs,
-- cfg->tx_tbl, cfg->tx_tbl_num, 2);
-- if (cfg->tx_tbl_sec)
-- qcom_qmp_phy_pcie_msm8996_configure_lane(qphy->tx2, cfg->regs,
-- cfg->tx_tbl_sec,
-- cfg->tx_tbl_num_sec, 2);
-- }
--
- qcom_qmp_phy_pcie_msm8996_configure_lane(rx, cfg->regs,
- cfg->rx_tbl, cfg->rx_tbl_num, 1);
- if (cfg->rx_tbl_sec)
- qcom_qmp_phy_pcie_msm8996_configure_lane(rx, cfg->regs,
- cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1);
-
-- if (cfg->is_dual_lane_phy) {
-- qcom_qmp_phy_pcie_msm8996_configure_lane(qphy->rx2, cfg->regs,
-- cfg->rx_tbl, cfg->rx_tbl_num, 2);
-- if (cfg->rx_tbl_sec)
-- qcom_qmp_phy_pcie_msm8996_configure_lane(qphy->rx2, cfg->regs,
-- cfg->rx_tbl_sec,
-- cfg->rx_tbl_num_sec, 2);
-- }
--
- qcom_qmp_phy_pcie_msm8996_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
- if (cfg->pcs_tbl_sec)
- qcom_qmp_phy_pcie_msm8996_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
- cfg->pcs_tbl_num_sec);
-
-- ret = reset_control_deassert(qmp->ufs_reset);
-- if (ret)
-- goto err_disable_pipe_clk;
--
- qcom_qmp_phy_pcie_msm8996_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
- cfg->pcs_misc_tbl_num);
- if (cfg->pcs_misc_tbl_sec)
-@@ -801,8 +652,8 @@ static int qcom_qmp_phy_pcie_msm8996_power_on(struct phy *phy)
- usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
-
- /* Pull PHY out of reset state */
-- if (!cfg->no_pcs_sw_reset)
-- qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
-+ qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
-+
- /* start SerDes and Phy-Coding-Sublayer */
- qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
-
-@@ -822,8 +673,7 @@ static int qcom_qmp_phy_pcie_msm8996_power_on(struct phy *phy)
- err_disable_pipe_clk:
- clk_disable_unprepare(qphy->pipe_clk);
- err_reset_lane:
-- if (cfg->has_lane_rst)
-- reset_control_assert(qphy->lane_rst);
-+ reset_control_assert(qphy->lane_rst);
-
- return ret;
- }
-@@ -836,8 +686,7 @@ static int qcom_qmp_phy_pcie_msm8996_power_off(struct phy *phy)
- clk_disable_unprepare(qphy->pipe_clk);
-
- /* PHY reset */
-- if (!cfg->no_pcs_sw_reset)
-- qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
-+ qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
-
- /* stop SerDes and Phy-Coding-Sublayer */
- qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
-@@ -857,10 +706,8 @@ static int qcom_qmp_phy_pcie_msm8996_power_off(struct phy *phy)
- static int qcom_qmp_phy_pcie_msm8996_exit(struct phy *phy)
- {
- struct qmp_phy *qphy = phy_get_drvdata(phy);
-- const struct qmp_phy_cfg *cfg = qphy->cfg;
-
-- if (cfg->has_lane_rst)
-- reset_control_assert(qphy->lane_rst);
-+ reset_control_assert(qphy->lane_rst);
-
- qcom_qmp_phy_pcie_msm8996_com_exit(qphy);
-
-@@ -1065,31 +912,7 @@ int qcom_qmp_phy_pcie_msm8996_create(struct device *dev, struct device_node *np,
- if (!qphy->pcs)
- return -ENOMEM;
-
-- /*
-- * If this is a dual-lane PHY, then there should be registers for the
-- * second lane. Some old device trees did not specify this, so fall
-- * back to old legacy behavior of assuming they can be reached at an
-- * offset from the first lane.
-- */
-- if (cfg->is_dual_lane_phy) {
-- qphy->tx2 = of_iomap(np, 3);
-- qphy->rx2 = of_iomap(np, 4);
-- if (!qphy->tx2 || !qphy->rx2) {
-- dev_warn(dev,
-- "Underspecified device tree, falling back to legacy register regions\n");
--
-- /* In the old version, pcs_misc is at index 3. */
-- qphy->pcs_misc = qphy->tx2;
-- qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE;
-- qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
--
-- } else {
-- qphy->pcs_misc = of_iomap(np, 5);
-- }
--
-- } else {
-- qphy->pcs_misc = of_iomap(np, 3);
-- }
-+ qphy->pcs_misc = of_iomap(np, 3);
-
- if (!qphy->pcs_misc)
- dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
-@@ -1117,18 +940,16 @@ int qcom_qmp_phy_pcie_msm8996_create(struct device *dev, struct device_node *np,
- }
-
- /* Get lane reset, if any */
-- if (cfg->has_lane_rst) {
-- snprintf(prop_name, sizeof(prop_name), "lane%d", id);
-- qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name);
-- if (IS_ERR(qphy->lane_rst)) {
-- dev_err(dev, "failed to get lane%d reset\n", id);
-- return PTR_ERR(qphy->lane_rst);
-- }
-- ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put,
-- qphy->lane_rst);
-- if (ret)
-- return ret;
-+ snprintf(prop_name, sizeof(prop_name), "lane%d", id);
-+ qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name);
-+ if (IS_ERR(qphy->lane_rst)) {
-+ dev_err(dev, "failed to get lane%d reset\n", id);
-+ return PTR_ERR(qphy->lane_rst);
- }
-+ ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put,
-+ qphy->lane_rst);
-+ if (ret)
-+ return ret;
-
- generic_phy = devm_phy_create(dev, np, &qcom_qmp_phy_pcie_msm8996_ops);
- if (IS_ERR(generic_phy)) {
-@@ -1183,13 +1004,6 @@ static int qcom_qmp_phy_pcie_msm8996_probe(struct platform_device *pdev)
- if (IS_ERR(serdes))
- return PTR_ERR(serdes);
-
-- /* per PHY dp_com; if PHY has dp_com control block */
-- if (cfg->has_phy_dp_com_ctrl) {
-- qmp->dp_com = devm_platform_ioremap_resource(pdev, 1);
-- if (IS_ERR(qmp->dp_com))
-- return PTR_ERR(qmp->dp_com);
-- }
--
- expected_phys = cfg->nlanes;
-
- mutex_init(&qmp->phy_mutex);
---
-2.35.1
-
+++ /dev/null
-From 98d520bf8babb35032781cb6a3b1096c53ea857f Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Wed, 8 Jun 2022 00:31:36 +0300
-Subject: phy: qcom-qmp-pcie-msm8996: drop all compatibles except
- msm8996-pcie-phy
-
-From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-
-[ Upstream commit 9fc8fa59ef1038714a9b86259f515373a7380169 ]
-
-Drop support for all compatibles from the new qmp-pcie driver except the
-qcom,msm8996-qmp-pcie-phy. This PHY differs from the rest of PCIe PHYs,
-so it warrants a separate device driver.
-
-Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> # UFS, PCIe and USB on SC8180X
-Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Link: https://lore.kernel.org/r/20220607213203.2819885-4-dmitry.baryshkov@linaro.org
-Signed-off-by: Vinod Koul <vkoul@kernel.org>
-Stable-dep-of: 1f69ededf8e8 ("phy: qcom-qmp-pcie-msm8996: fix memleak on probe deferral")
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- .../phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 5024 +----------------
- 1 file changed, 200 insertions(+), 4824 deletions(-)
-
-diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
-index c7309e981bfb..260e534b5607 100644
---- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
-+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
-@@ -141,18 +141,6 @@ enum qphy_reg_layout {
- QPHY_LAYOUT_SIZE
- };
-
--static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-- [QPHY_START_CTRL] = 0x00,
-- [QPHY_PCS_READY_STATUS] = 0x168,
--};
--
--static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = {
-- [QPHY_SW_RESET] = 0x00,
-- [QPHY_START_CTRL] = 0x44,
-- [QPHY_PCS_STATUS] = 0x14,
-- [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
--};
--
- static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
- [QPHY_COM_SW_RESET] = 0x400,
- [QPHY_COM_POWER_DOWN_CONTROL] = 0x404,
-@@ -169,176 +157,6 @@ static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
- [QPHY_PCS_STATUS] = 0x174,
- };
-
--static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
-- [QPHY_FLL_CNTRL1] = 0xc0,
-- [QPHY_FLL_CNTRL2] = 0xc4,
-- [QPHY_FLL_CNT_VAL_L] = 0xc8,
-- [QPHY_FLL_CNT_VAL_H_TOL] = 0xcc,
-- [QPHY_FLL_MAN_CODE] = 0xd0,
-- [QPHY_SW_RESET] = 0x00,
-- [QPHY_START_CTRL] = 0x08,
-- [QPHY_PCS_STATUS] = 0x17c,
-- [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
-- [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8,
-- [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
--};
--
--static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
-- [QPHY_SW_RESET] = 0x00,
-- [QPHY_START_CTRL] = 0x08,
-- [QPHY_PCS_STATUS] = 0x174,
-- [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
-- [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc,
-- [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
--};
--
--static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
-- [QPHY_SW_RESET] = 0x00,
-- [QPHY_START_CTRL] = 0x08,
-- [QPHY_PCS_STATUS] = 0x174,
--};
--
--static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
-- [QPHY_SW_RESET] = 0x00,
-- [QPHY_START_CTRL] = 0x08,
-- [QPHY_PCS_STATUS] = 0x2ac,
--};
--
--static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
-- [QPHY_SW_RESET] = 0x00,
-- [QPHY_START_CTRL] = 0x44,
-- [QPHY_PCS_STATUS] = 0x14,
-- [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
-- [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308,
-- [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314,
--};
--
--static const unsigned int qmp_v4_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-- [QPHY_SW_RESET] = 0x00,
-- [QPHY_START_CTRL] = 0x44,
-- [QPHY_PCS_STATUS] = 0x14,
-- [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
-- [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x608,
-- [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x614,
--};
--
--static const unsigned int sm8350_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-- [QPHY_SW_RESET] = 0x00,
-- [QPHY_START_CTRL] = 0x44,
-- [QPHY_PCS_STATUS] = 0x14,
-- [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
-- [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x1008,
-- [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x1014,
--};
--
--static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
-- [QPHY_SW_RESET] = 0x00,
-- [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
-- [QPHY_START_CTRL] = 0x08,
-- [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0xd8,
-- [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc,
-- [QPHY_PCS_STATUS] = 0x174,
-- [QPHY_PCS_MISC_TYPEC_CTRL] = 0x00,
--};
--
--static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-- [QPHY_START_CTRL] = 0x00,
-- [QPHY_PCS_READY_STATUS] = 0x160,
--};
--
--static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-- [QPHY_START_CTRL] = 0x00,
-- [QPHY_PCS_READY_STATUS] = 0x168,
--};
--
--static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = {
-- [QPHY_SW_RESET] = 0x00,
-- [QPHY_START_CTRL] = 0x44,
-- [QPHY_PCS_STATUS] = 0x14,
-- [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
--};
--
--static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-- [QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START,
-- [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS,
-- [QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET,
--};
--
--static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
-- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
-- /* PLL and Loop filter settings */
-- QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-- /* SSC settings */
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
--};
--
--static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
--};
--
--static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
--};
--
- static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
-@@ -417,4078 +235,243 @@ static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
- QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
- };
-
--static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
--};
--
--static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
--};
--
--static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
--};
--
--static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
--};
--
--static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
-- QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
-- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
--};
--
--static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-- QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
--};
--
--static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
--};
--
--static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
-- /* PLL and Loop filter settings */
-- QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-- /* SSC settings */
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
--};
--
--static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-- QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
-- QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
--};
--
--static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
--};
--
--static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
-- /* FLL settings */
-- QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03),
-- QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02),
-- QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09),
-- QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42),
-- QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
--
-- /* Lock Det settings */
-- QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
-- QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
-- QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
-- QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
--};
--
--static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
--};
--
--static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12),
--};
--
--static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x61),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04),
--};
--
--static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01),
-- QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d),
-- QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10),
-- QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa),
-- QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-- QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
-- QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01),
-- QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
-- QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
-- QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-- QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-- QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-- QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-- QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11),
-- QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_PRE, 0x00),
-- QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_POST, 0x58),
--};
--
--static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
-- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
-- QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
-- QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
-- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
-- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
--};
--
--static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-- QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
-- QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
-- QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
-- QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
--};
--
--static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
-- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
-- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
--};
--
--static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
-- QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
-- QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
-- QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
-- QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
-- QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
-- QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
-- QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
-- QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
-- QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
-- QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
-- QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
-- QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
--};
--
--static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
--};
--
--static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
--};
--
--static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
--};
--
--static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
--
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
--
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
-+struct qmp_phy;
-
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
-+/* struct qmp_phy_cfg - per-PHY initialization config */
-+struct qmp_phy_cfg {
-+ /* phy-type - PCIE/UFS/USB */
-+ unsigned int type;
-+ /* number of lanes provided by phy */
-+ int nlanes;
-
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
--};
-+ /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
-+ const struct qmp_phy_init_tbl *serdes_tbl;
-+ int serdes_tbl_num;
-+ const struct qmp_phy_init_tbl *serdes_tbl_sec;
-+ int serdes_tbl_num_sec;
-+ const struct qmp_phy_init_tbl *tx_tbl;
-+ int tx_tbl_num;
-+ const struct qmp_phy_init_tbl *tx_tbl_sec;
-+ int tx_tbl_num_sec;
-+ const struct qmp_phy_init_tbl *rx_tbl;
-+ int rx_tbl_num;
-+ const struct qmp_phy_init_tbl *rx_tbl_sec;
-+ int rx_tbl_num_sec;
-+ const struct qmp_phy_init_tbl *pcs_tbl;
-+ int pcs_tbl_num;
-+ const struct qmp_phy_init_tbl *pcs_tbl_sec;
-+ int pcs_tbl_num_sec;
-+ const struct qmp_phy_init_tbl *pcs_misc_tbl;
-+ int pcs_misc_tbl_num;
-+ const struct qmp_phy_init_tbl *pcs_misc_tbl_sec;
-+ int pcs_misc_tbl_num_sec;
-
--static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
--};
-+ /* Init sequence for DP PHY block link rates */
-+ const struct qmp_phy_init_tbl *serdes_tbl_rbr;
-+ int serdes_tbl_rbr_num;
-+ const struct qmp_phy_init_tbl *serdes_tbl_hbr;
-+ int serdes_tbl_hbr_num;
-+ const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
-+ int serdes_tbl_hbr2_num;
-+ const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
-+ int serdes_tbl_hbr3_num;
-
--static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07),
--};
-+ /* DP PHY callbacks */
-+ int (*configure_dp_phy)(struct qmp_phy *qphy);
-+ void (*configure_dp_tx)(struct qmp_phy *qphy);
-+ int (*calibrate_dp_phy)(struct qmp_phy *qphy);
-+ void (*dp_aux_init)(struct qmp_phy *qphy);
-
--static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
--};
-+ /* clock ids to be requested */
-+ const char * const *clk_list;
-+ int num_clks;
-+ /* resets to be requested */
-+ const char * const *reset_list;
-+ int num_resets;
-+ /* regulators to be requested */
-+ const char * const *vreg_list;
-+ int num_vregs;
-
--static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = {
--};
-+ /* array of registers with different offsets */
-+ const unsigned int *regs;
-
--static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f),
--};
-+ unsigned int start_ctrl;
-+ unsigned int pwrdn_ctrl;
-+ unsigned int mask_com_pcs_ready;
-+ /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
-+ unsigned int phy_status;
-
--static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
--};
-+ /* true, if PHY has a separate PHY_COM control block */
-+ bool has_phy_com_ctrl;
-+ /* true, if PHY has a reset for individual lanes */
-+ bool has_lane_rst;
-+ /* true, if PHY needs delay after POWER_DOWN */
-+ bool has_pwrdn_delay;
-+ /* power_down delay in usec */
-+ int pwrdn_delay_min;
-+ int pwrdn_delay_max;
-
--static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
--};
-+ /* true, if PHY has a separate DP_COM control block */
-+ bool has_phy_dp_com_ctrl;
-+ /* true, if PHY has secondary tx/rx lanes to be configured */
-+ bool is_dual_lane_phy;
-
--static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-+ /* true, if PCS block has no separate SW_RESET register */
-+ bool no_pcs_sw_reset;
- };
-
--static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
-+struct qmp_phy_combo_cfg {
-+ const struct qmp_phy_cfg *usb_cfg;
-+ const struct qmp_phy_cfg *dp_cfg;
- };
-
--static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
--};
--
--static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
--};
--
--static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08),
--};
--
--static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
--};
--
--static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
--};
--
--static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
-- /* FLL settings */
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
--
-- /* Lock Det settings */
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
--
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
--
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
--};
--
--static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
--};
--
--static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
--};
--
--static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
--};
--
--static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
-- /* FLL settings */
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
--
-- /* Lock Det settings */
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
--
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
--
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
--
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
--};
--
--static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
-- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
--
-- /* Rate B */
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),
--};
--
--static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-- QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
--};
--
--static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40),
-- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E),
-- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D),
-- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B),
--};
--
--static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_RX_PWM_GEAR_BAND, 0x15),
-- QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_CTRL2, 0x6d),
-- QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_DRV_LVL, 0x0f),
-- QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_DRV_LVL, 0x02),
-- QMP_PHY_INIT_CFG(QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
-- QMP_PHY_INIT_CFG(QPHY_RX_SYM_RESYNC_CTRL, 0x03),
-- QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
-- QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
-- QMP_PHY_INIT_CFG(QPHY_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
--};
--
--static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
--
-- /* Rate B */
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
--};
--
--static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
--};
--
--static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
--};
--
--static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
--};
--
--static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
--};
--
--static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
--};
--
--static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
--};
--
--static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
--};
--
--static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
--
-- /* Rate B */
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
--};
--
--static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
--};
--
--static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
--
--};
--
--static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
--};
--
--static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
--};
--
--static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
--};
--
--static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
--};
--
--static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
-- /* Lock Det settings */
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
--
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
--};
--
--static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
--};
--
--static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),
--};
--
--static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
--};
--
--static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
--};
--
--static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-- QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1),
-- QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2),
--};
--
--static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-- QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1),
-- QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2),
-- QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1),
-- QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
--};
--
--static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
--};
--
--static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
--};
--
--static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
--};
--
--static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
--};
--
--static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
--};
--
--static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
--};
--
--static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
--};
--
--static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
--};
--
--static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
--};
--
--static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20),
--};
--
--static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
--};
--
--static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5),
--};
--
--static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
--};
--
--static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),
--};
--
--static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
--};
--
--static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
--};
--
--static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
--};
--
--static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
--};
--
--static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
--};
--
--static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
--};
--
--static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
--};
--
--static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12),
--};
--
--static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
--};
--
--static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f),
--};
--
--static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
--};
--
--static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
--};
--
--static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f),
--};
--
--static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
--};
--
--static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08),
--};
--
--static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
--};
--
--static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22),
--};
--
--static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00),
--};
--
--static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12),
--};
--
--static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77),
-- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01),
-- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16),
-- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02),
--};
--
--static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17),
-- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13),
-- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13),
-- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01),
-- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
-- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
--};
--
--static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b),
--};
--
--static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
--};
--
--static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
--
-- /* Rate B */
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
--};
--
--static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),
--};
--
--static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
--};
--
--static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
--};
--
--static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
--};
--
--static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb),
-- QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1),
-- QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10),
--};
--
--static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
--};
--
--static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
--};
--
--static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
--};
--
--static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
--};
--
--static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01),
--};
--
--static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00),
--};
--
--static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00),
--};
--
--static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
--};
--
--static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
--};
--
--static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04),
--};
--
--static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
--};
--
--static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
--};
--
--static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
--};
--
--static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
--};
--
--static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
--};
--
--static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
--
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05),
--
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
--
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
--
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
--};
--
--/* Register names should be validated, they might be different for this PHY */
--static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99),
--};
--
--static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-- QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
-- QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
-- QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),
-- QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
--};
--
--struct qmp_phy;
--
--/* struct qmp_phy_cfg - per-PHY initialization config */
--struct qmp_phy_cfg {
-- /* phy-type - PCIE/UFS/USB */
-- unsigned int type;
-- /* number of lanes provided by phy */
-- int nlanes;
--
-- /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
-- const struct qmp_phy_init_tbl *serdes_tbl;
-- int serdes_tbl_num;
-- const struct qmp_phy_init_tbl *serdes_tbl_sec;
-- int serdes_tbl_num_sec;
-- const struct qmp_phy_init_tbl *tx_tbl;
-- int tx_tbl_num;
-- const struct qmp_phy_init_tbl *tx_tbl_sec;
-- int tx_tbl_num_sec;
-- const struct qmp_phy_init_tbl *rx_tbl;
-- int rx_tbl_num;
-- const struct qmp_phy_init_tbl *rx_tbl_sec;
-- int rx_tbl_num_sec;
-- const struct qmp_phy_init_tbl *pcs_tbl;
-- int pcs_tbl_num;
-- const struct qmp_phy_init_tbl *pcs_tbl_sec;
-- int pcs_tbl_num_sec;
-- const struct qmp_phy_init_tbl *pcs_misc_tbl;
-- int pcs_misc_tbl_num;
-- const struct qmp_phy_init_tbl *pcs_misc_tbl_sec;
-- int pcs_misc_tbl_num_sec;
--
-- /* Init sequence for DP PHY block link rates */
-- const struct qmp_phy_init_tbl *serdes_tbl_rbr;
-- int serdes_tbl_rbr_num;
-- const struct qmp_phy_init_tbl *serdes_tbl_hbr;
-- int serdes_tbl_hbr_num;
-- const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
-- int serdes_tbl_hbr2_num;
-- const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
-- int serdes_tbl_hbr3_num;
--
-- /* DP PHY callbacks */
-- int (*configure_dp_phy)(struct qmp_phy *qphy);
-- void (*configure_dp_tx)(struct qmp_phy *qphy);
-- int (*calibrate_dp_phy)(struct qmp_phy *qphy);
-- void (*dp_aux_init)(struct qmp_phy *qphy);
--
-- /* clock ids to be requested */
-- const char * const *clk_list;
-- int num_clks;
-- /* resets to be requested */
-- const char * const *reset_list;
-- int num_resets;
-- /* regulators to be requested */
-- const char * const *vreg_list;
-- int num_vregs;
--
-- /* array of registers with different offsets */
-- const unsigned int *regs;
--
-- unsigned int start_ctrl;
-- unsigned int pwrdn_ctrl;
-- unsigned int mask_com_pcs_ready;
-- /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
-- unsigned int phy_status;
--
-- /* true, if PHY has a separate PHY_COM control block */
-- bool has_phy_com_ctrl;
-- /* true, if PHY has a reset for individual lanes */
-- bool has_lane_rst;
-- /* true, if PHY needs delay after POWER_DOWN */
-- bool has_pwrdn_delay;
-- /* power_down delay in usec */
-- int pwrdn_delay_min;
-- int pwrdn_delay_max;
--
-- /* true, if PHY has a separate DP_COM control block */
-- bool has_phy_dp_com_ctrl;
-- /* true, if PHY has secondary tx/rx lanes to be configured */
-- bool is_dual_lane_phy;
--
-- /* true, if PCS block has no separate SW_RESET register */
-- bool no_pcs_sw_reset;
--};
--
--struct qmp_phy_combo_cfg {
-- const struct qmp_phy_cfg *usb_cfg;
-- const struct qmp_phy_cfg *dp_cfg;
--};
--
--/**
-- * struct qmp_phy - per-lane phy descriptor
-- *
-- * @phy: generic phy
-- * @cfg: phy specific configuration
-- * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
-- * @tx: iomapped memory space for lane's tx
-- * @rx: iomapped memory space for lane's rx
-- * @pcs: iomapped memory space for lane's pcs
-- * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
-- * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
-- * @pcs_misc: iomapped memory space for lane's pcs_misc
-- * @pipe_clk: pipe clock
-- * @index: lane index
-- * @qmp: QMP phy to which this lane belongs
-- * @lane_rst: lane's reset controller
-- * @mode: current PHY mode
-- * @dp_aux_cfg: Display port aux config
-- * @dp_opts: Display port optional config
-- * @dp_clks: Display port clocks
-- */
--struct qmp_phy {
-- struct phy *phy;
-- const struct qmp_phy_cfg *cfg;
-- void __iomem *serdes;
-- void __iomem *tx;
-- void __iomem *rx;
-- void __iomem *pcs;
-- void __iomem *tx2;
-- void __iomem *rx2;
-- void __iomem *pcs_misc;
-- struct clk *pipe_clk;
-- unsigned int index;
-- struct qcom_qmp *qmp;
-- struct reset_control *lane_rst;
-- enum phy_mode mode;
-- unsigned int dp_aux_cfg;
-- struct phy_configure_opts_dp dp_opts;
-- struct qmp_phy_dp_clks *dp_clks;
--};
--
--struct qmp_phy_dp_clks {
-- struct qmp_phy *qphy;
-- struct clk_hw dp_link_hw;
-- struct clk_hw dp_pixel_hw;
--};
--
--/**
-- * struct qcom_qmp - structure holding QMP phy block attributes
-- *
-- * @dev: device
-- * @dp_com: iomapped memory space for phy's dp_com control block
-- *
-- * @clks: array of clocks required by phy
-- * @resets: array of resets required by phy
-- * @vregs: regulator supplies bulk data
-- *
-- * @phys: array of per-lane phy descriptors
-- * @phy_mutex: mutex lock for PHY common block initialization
-- * @init_count: phy common block initialization count
-- * @ufs_reset: optional UFS PHY reset handle
-- */
--struct qcom_qmp {
-- struct device *dev;
-- void __iomem *dp_com;
--
-- struct clk_bulk_data *clks;
-- struct reset_control **resets;
-- struct regulator_bulk_data *vregs;
--
-- struct qmp_phy **phys;
--
-- struct mutex phy_mutex;
-- int init_count;
--
-- struct reset_control *ufs_reset;
--};
--
--static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy);
--static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy);
--static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy);
--static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy);
--
--static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy);
--static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy);
--static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy);
--static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy);
--
--static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
--{
-- u32 reg;
--
-- reg = readl(base + offset);
-- reg |= val;
-- writel(reg, base + offset);
--
-- /* ensure that above write is through */
-- readl(base + offset);
--}
--
--static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
--{
-- u32 reg;
--
-- reg = readl(base + offset);
-- reg &= ~val;
-- writel(reg, base + offset);
--
-- /* ensure that above write is through */
-- readl(base + offset);
--}
--
--/* list of clocks required by phy */
--static const char * const msm8996_phy_clk_l[] = {
-- "aux", "cfg_ahb", "ref",
--};
--
--static const char * const msm8996_ufs_phy_clk_l[] = {
-- "ref",
--};
--
--static const char * const qmp_v3_phy_clk_l[] = {
-- "aux", "cfg_ahb", "ref", "com_aux",
--};
--
--static const char * const sdm845_pciephy_clk_l[] = {
-- "aux", "cfg_ahb", "ref", "refgen",
--};
--
--static const char * const qmp_v4_phy_clk_l[] = {
-- "aux", "ref_clk_src", "ref", "com_aux",
--};
--
--/* the primary usb3 phy on sm8250 doesn't have a ref clock */
--static const char * const qmp_v4_sm8250_usbphy_clk_l[] = {
-- "aux", "ref_clk_src", "com_aux"
--};
--
--static const char * const sm8450_ufs_phy_clk_l[] = {
-- "qref", "ref", "ref_aux",
--};
--
--static const char * const sdm845_ufs_phy_clk_l[] = {
-- "ref", "ref_aux",
--};
--
--/* usb3 phy on sdx55 doesn't have com_aux clock */
--static const char * const qmp_v4_sdx55_usbphy_clk_l[] = {
-- "aux", "cfg_ahb", "ref"
--};
--
--static const char * const qcm2290_usb3phy_clk_l[] = {
-- "cfg_ahb", "ref", "com_aux",
--};
--
--/* list of resets */
--static const char * const msm8996_pciephy_reset_l[] = {
-- "phy", "common", "cfg",
--};
--
--static const char * const msm8996_usb3phy_reset_l[] = {
-- "phy", "common",
--};
--
--static const char * const sc7180_usb3phy_reset_l[] = {
-- "phy",
--};
--
--static const char * const qcm2290_usb3phy_reset_l[] = {
-- "phy_phy", "phy",
--};
--
--static const char * const sdm845_pciephy_reset_l[] = {
-- "phy",
--};
--
--/* list of regulators */
--static const char * const qmp_phy_vreg_l[] = {
-- "vdda-phy", "vdda-pll",
--};
--
--static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
-- .type = PHY_TYPE_USB3,
-- .nlanes = 1,
--
-- .serdes_tbl = ipq8074_usb3_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
-- .tx_tbl = msm8996_usb3_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
-- .rx_tbl = ipq8074_usb3_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
-- .pcs_tbl = ipq8074_usb3_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
-- .clk_list = msm8996_phy_clk_l,
-- .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-- .reset_list = msm8996_usb3phy_reset_l,
-- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = usb3phy_regs_layout,
--
-- .start_ctrl = SERDES_START | PCS_START,
-- .pwrdn_ctrl = SW_PWRDN,
-- .phy_status = PHYSTATUS,
--};
--
--static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
-- .type = PHY_TYPE_PCIE,
-- .nlanes = 3,
--
-- .serdes_tbl = msm8996_pcie_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
-- .tx_tbl = msm8996_pcie_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(msm8996_pcie_tx_tbl),
-- .rx_tbl = msm8996_pcie_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(msm8996_pcie_rx_tbl),
-- .pcs_tbl = msm8996_pcie_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
-- .clk_list = msm8996_phy_clk_l,
-- .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-- .reset_list = msm8996_pciephy_reset_l,
-- .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = pciephy_regs_layout,
--
-- .start_ctrl = PCS_START | PLL_READY_GATE_EN,
-- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-- .mask_com_pcs_ready = PCS_READY,
-- .phy_status = PHYSTATUS,
--
-- .has_phy_com_ctrl = true,
-- .has_lane_rst = true,
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
--};
--
--static const struct qmp_phy_cfg msm8996_ufs_cfg = {
-- .type = PHY_TYPE_UFS,
-- .nlanes = 1,
--
-- .serdes_tbl = msm8996_ufs_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(msm8996_ufs_serdes_tbl),
-- .tx_tbl = msm8996_ufs_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(msm8996_ufs_tx_tbl),
-- .rx_tbl = msm8996_ufs_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(msm8996_ufs_rx_tbl),
--
-- .clk_list = msm8996_ufs_phy_clk_l,
-- .num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
--
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
--
-- .regs = msm8996_ufsphy_regs_layout,
--
-- .start_ctrl = SERDES_START,
-- .pwrdn_ctrl = SW_PWRDN,
-- .phy_status = PHYSTATUS,
--
-- .no_pcs_sw_reset = true,
--};
--
--static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
-- .type = PHY_TYPE_USB3,
-- .nlanes = 1,
--
-- .serdes_tbl = msm8996_usb3_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
-- .tx_tbl = msm8996_usb3_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
-- .rx_tbl = msm8996_usb3_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl),
-- .pcs_tbl = msm8996_usb3_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
-- .clk_list = msm8996_phy_clk_l,
-- .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-- .reset_list = msm8996_usb3phy_reset_l,
-- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = usb3phy_regs_layout,
--
-- .start_ctrl = SERDES_START | PCS_START,
-- .pwrdn_ctrl = SW_PWRDN,
-- .phy_status = PHYSTATUS,
--};
--
--static const char * const ipq8074_pciephy_clk_l[] = {
-- "aux", "cfg_ahb",
--};
--/* list of resets */
--static const char * const ipq8074_pciephy_reset_l[] = {
-- "phy", "common",
--};
--
--static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
-- .type = PHY_TYPE_PCIE,
-- .nlanes = 1,
--
-- .serdes_tbl = ipq8074_pcie_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
-- .tx_tbl = ipq8074_pcie_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
-- .rx_tbl = ipq8074_pcie_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
-- .pcs_tbl = ipq8074_pcie_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
-- .clk_list = ipq8074_pciephy_clk_l,
-- .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
-- .reset_list = ipq8074_pciephy_reset_l,
-- .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
-- .vreg_list = NULL,
-- .num_vregs = 0,
-- .regs = pciephy_regs_layout,
--
-- .start_ctrl = SERDES_START | PCS_START,
-- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-- .phy_status = PHYSTATUS,
--
-- .has_phy_com_ctrl = false,
-- .has_lane_rst = false,
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = 995, /* us */
-- .pwrdn_delay_max = 1005, /* us */
--};
--
--static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
-- .type = PHY_TYPE_PCIE,
-- .nlanes = 1,
--
-- .serdes_tbl = ipq6018_pcie_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl),
-- .tx_tbl = ipq6018_pcie_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl),
-- .rx_tbl = ipq6018_pcie_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
-- .pcs_tbl = ipq6018_pcie_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
-- .clk_list = ipq8074_pciephy_clk_l,
-- .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
-- .reset_list = ipq8074_pciephy_reset_l,
-- .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
-- .vreg_list = NULL,
-- .num_vregs = 0,
-- .regs = ipq_pciephy_gen3_regs_layout,
--
-- .start_ctrl = SERDES_START | PCS_START,
-- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
--
-- .has_phy_com_ctrl = false,
-- .has_lane_rst = false,
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = 995, /* us */
-- .pwrdn_delay_max = 1005, /* us */
--};
--
--static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
-- .type = PHY_TYPE_PCIE,
-- .nlanes = 1,
--
-- .serdes_tbl = sdm845_qmp_pcie_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
-- .tx_tbl = sdm845_qmp_pcie_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),
-- .rx_tbl = sdm845_qmp_pcie_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),
-- .pcs_tbl = sdm845_qmp_pcie_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),
-- .pcs_misc_tbl = sdm845_qmp_pcie_pcs_misc_tbl,
-- .pcs_misc_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
-- .clk_list = sdm845_pciephy_clk_l,
-- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-- .reset_list = sdm845_pciephy_reset_l,
-- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = sdm845_qmp_pciephy_regs_layout,
--
-- .start_ctrl = PCS_START | SERDES_START,
-- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-- .phy_status = PHYSTATUS,
--
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = 995, /* us */
-- .pwrdn_delay_max = 1005, /* us */
--};
--
--static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
-- .type = PHY_TYPE_PCIE,
-- .nlanes = 1,
--
-- .serdes_tbl = sdm845_qhp_pcie_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
-- .tx_tbl = sdm845_qhp_pcie_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
-- .rx_tbl = sdm845_qhp_pcie_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl),
-- .pcs_tbl = sdm845_qhp_pcie_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
-- .clk_list = sdm845_pciephy_clk_l,
-- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-- .reset_list = sdm845_pciephy_reset_l,
-- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = sdm845_qhp_pciephy_regs_layout,
--
-- .start_ctrl = PCS_START | SERDES_START,
-- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-- .phy_status = PHYSTATUS,
--
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = 995, /* us */
-- .pwrdn_delay_max = 1005, /* us */
--};
--
--static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
-- .type = PHY_TYPE_PCIE,
-- .nlanes = 1,
--
-- .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
-- .serdes_tbl_sec = sm8250_qmp_gen3x1_pcie_serdes_tbl,
-- .serdes_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
-- .tx_tbl = sm8250_qmp_pcie_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
-- .rx_tbl = sm8250_qmp_pcie_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
-- .rx_tbl_sec = sm8250_qmp_gen3x1_pcie_rx_tbl,
-- .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),
-- .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
-- .pcs_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_tbl,
-- .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),
-- .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
-- .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
-- .pcs_misc_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,
-- .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),
-- .clk_list = sdm845_pciephy_clk_l,
-- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-- .reset_list = sdm845_pciephy_reset_l,
-- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = sm8250_pcie_regs_layout,
--
-- .start_ctrl = PCS_START | SERDES_START,
-- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-- .phy_status = PHYSTATUS,
--
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = 995, /* us */
-- .pwrdn_delay_max = 1005, /* us */
--};
--
--static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
-- .type = PHY_TYPE_PCIE,
-- .nlanes = 2,
--
-- .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
-- .tx_tbl = sm8250_qmp_pcie_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
-- .tx_tbl_sec = sm8250_qmp_gen3x2_pcie_tx_tbl,
-- .tx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),
-- .rx_tbl = sm8250_qmp_pcie_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
-- .rx_tbl_sec = sm8250_qmp_gen3x2_pcie_rx_tbl,
-- .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl),
-- .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
-- .pcs_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_tbl,
-- .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl),
-- .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
-- .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
-- .pcs_misc_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,
-- .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),
-- .clk_list = sdm845_pciephy_clk_l,
-- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-- .reset_list = sdm845_pciephy_reset_l,
-- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = sm8250_pcie_regs_layout,
--
-- .start_ctrl = PCS_START | SERDES_START,
-- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-- .phy_status = PHYSTATUS,
--
-- .is_dual_lane_phy = true,
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = 995, /* us */
-- .pwrdn_delay_max = 1005, /* us */
--};
--
--static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
-- .type = PHY_TYPE_USB3,
-- .nlanes = 1,
--
-- .serdes_tbl = qmp_v3_usb3_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
-- .tx_tbl = qmp_v3_usb3_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
-- .rx_tbl = qmp_v3_usb3_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
-- .pcs_tbl = qmp_v3_usb3_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
-- .clk_list = qmp_v3_phy_clk_l,
-- .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-- .reset_list = msm8996_usb3phy_reset_l,
-- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = qmp_v3_usb3phy_regs_layout,
--
-- .start_ctrl = SERDES_START | PCS_START,
-- .pwrdn_ctrl = SW_PWRDN,
-- .phy_status = PHYSTATUS,
--
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
--
-- .has_phy_dp_com_ctrl = true,
-- .is_dual_lane_phy = true,
--};
--
--static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
-- .type = PHY_TYPE_USB3,
-- .nlanes = 1,
--
-- .serdes_tbl = qmp_v3_usb3_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
-- .tx_tbl = qmp_v3_usb3_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
-- .rx_tbl = qmp_v3_usb3_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
-- .pcs_tbl = qmp_v3_usb3_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
-- .clk_list = qmp_v3_phy_clk_l,
-- .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-- .reset_list = sc7180_usb3phy_reset_l,
-- .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = qmp_v3_usb3phy_regs_layout,
--
-- .start_ctrl = SERDES_START | PCS_START,
-- .pwrdn_ctrl = SW_PWRDN,
-- .phy_status = PHYSTATUS,
--
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
--
-- .has_phy_dp_com_ctrl = true,
-- .is_dual_lane_phy = true,
--};
--
--static const struct qmp_phy_cfg sc7180_dpphy_cfg = {
-- .type = PHY_TYPE_DP,
-- .nlanes = 1,
--
-- .serdes_tbl = qmp_v3_dp_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
-- .tx_tbl = qmp_v3_dp_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
--
-- .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr,
-- .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
-- .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr,
-- .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
-- .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2,
-- .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
-- .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3,
-- .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
--
-- .clk_list = qmp_v3_phy_clk_l,
-- .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-- .reset_list = sc7180_usb3phy_reset_l,
-- .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = qmp_v3_usb3phy_regs_layout,
--
-- .has_phy_dp_com_ctrl = true,
-- .is_dual_lane_phy = true,
--
-- .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init,
-- .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx,
-- .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy,
-- .calibrate_dp_phy = qcom_qmp_v3_dp_phy_calibrate,
--};
--
--static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = {
-- .usb_cfg = &sc7180_usb3phy_cfg,
-- .dp_cfg = &sc7180_dpphy_cfg,
--};
--
--static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
-- .type = PHY_TYPE_USB3,
-- .nlanes = 1,
--
-- .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
-- .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
-- .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
-- .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
-- .clk_list = qmp_v3_phy_clk_l,
-- .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-- .reset_list = msm8996_usb3phy_reset_l,
-- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = qmp_v3_usb3phy_regs_layout,
--
-- .start_ctrl = SERDES_START | PCS_START,
-- .pwrdn_ctrl = SW_PWRDN,
-- .phy_status = PHYSTATUS,
--
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
--};
--
--static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
-- .type = PHY_TYPE_UFS,
-- .nlanes = 2,
--
-- .serdes_tbl = sdm845_ufsphy_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
-- .tx_tbl = sdm845_ufsphy_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
-- .rx_tbl = sdm845_ufsphy_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
-- .pcs_tbl = sdm845_ufsphy_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
-- .clk_list = sdm845_ufs_phy_clk_l,
-- .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = sdm845_ufsphy_regs_layout,
--
-- .start_ctrl = SERDES_START,
-- .pwrdn_ctrl = SW_PWRDN,
-- .phy_status = PHYSTATUS,
--
-- .is_dual_lane_phy = true,
-- .no_pcs_sw_reset = true,
--};
--
--static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
-- .type = PHY_TYPE_UFS,
-- .nlanes = 1,
--
-- .serdes_tbl = sm6115_ufsphy_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl),
-- .tx_tbl = sm6115_ufsphy_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_tx_tbl),
-- .rx_tbl = sm6115_ufsphy_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_rx_tbl),
-- .pcs_tbl = sm6115_ufsphy_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl),
-- .clk_list = sdm845_ufs_phy_clk_l,
-- .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = sm6115_ufsphy_regs_layout,
--
-- .start_ctrl = SERDES_START,
-- .pwrdn_ctrl = SW_PWRDN,
--
-- .is_dual_lane_phy = false,
-- .no_pcs_sw_reset = true,
--};
--
--static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
-- .type = PHY_TYPE_PCIE,
-- .nlanes = 1,
--
-- .serdes_tbl = msm8998_pcie_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
-- .tx_tbl = msm8998_pcie_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(msm8998_pcie_tx_tbl),
-- .rx_tbl = msm8998_pcie_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(msm8998_pcie_rx_tbl),
-- .pcs_tbl = msm8998_pcie_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
-- .clk_list = msm8996_phy_clk_l,
-- .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-- .reset_list = ipq8074_pciephy_reset_l,
-- .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = pciephy_regs_layout,
--
-- .start_ctrl = SERDES_START | PCS_START,
-- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-- .phy_status = PHYSTATUS,
--};
--
--static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
-- .type = PHY_TYPE_USB3,
-- .nlanes = 1,
--
-- .serdes_tbl = msm8998_usb3_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
-- .tx_tbl = msm8998_usb3_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl),
-- .rx_tbl = msm8998_usb3_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl),
-- .pcs_tbl = msm8998_usb3_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
-- .clk_list = msm8996_phy_clk_l,
-- .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-- .reset_list = msm8996_usb3phy_reset_l,
-- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = qmp_v3_usb3phy_regs_layout,
--
-- .start_ctrl = SERDES_START | PCS_START,
-- .pwrdn_ctrl = SW_PWRDN,
-- .phy_status = PHYSTATUS,
--
-- .is_dual_lane_phy = true,
--};
--
--static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
-- .type = PHY_TYPE_UFS,
-- .nlanes = 2,
--
-- .serdes_tbl = sm8150_ufsphy_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl),
-- .tx_tbl = sm8150_ufsphy_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx_tbl),
-- .rx_tbl = sm8150_ufsphy_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx_tbl),
-- .pcs_tbl = sm8150_ufsphy_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl),
-- .clk_list = sdm845_ufs_phy_clk_l,
-- .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = sm8150_ufsphy_regs_layout,
--
-- .start_ctrl = SERDES_START,
-- .pwrdn_ctrl = SW_PWRDN,
-- .phy_status = PHYSTATUS,
--
-- .is_dual_lane_phy = true,
--};
--
--static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
-- .type = PHY_TYPE_USB3,
-- .nlanes = 1,
--
-- .serdes_tbl = sm8150_usb3_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
-- .tx_tbl = sm8150_usb3_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl),
-- .rx_tbl = sm8150_usb3_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl),
-- .pcs_tbl = sm8150_usb3_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
-- .clk_list = qmp_v4_phy_clk_l,
-- .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-- .reset_list = msm8996_usb3phy_reset_l,
-- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = qmp_v4_usb3phy_regs_layout,
--
-- .start_ctrl = SERDES_START | PCS_START,
-- .pwrdn_ctrl = SW_PWRDN,
-- .phy_status = PHYSTATUS,
--
--
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
--
-- .has_phy_dp_com_ctrl = true,
-- .is_dual_lane_phy = true,
--};
--
--static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
-- .type = PHY_TYPE_PCIE,
-- .nlanes = 1,
--
-- .serdes_tbl = sc8180x_qmp_pcie_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl),
-- .tx_tbl = sc8180x_qmp_pcie_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl),
-- .rx_tbl = sc8180x_qmp_pcie_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl),
-- .pcs_tbl = sc8180x_qmp_pcie_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl),
-- .pcs_misc_tbl = sc8180x_qmp_pcie_pcs_misc_tbl,
-- .pcs_misc_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl),
-- .clk_list = sdm845_pciephy_clk_l,
-- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-- .reset_list = sdm845_pciephy_reset_l,
-- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = sm8250_pcie_regs_layout,
--
-- .start_ctrl = PCS_START | SERDES_START,
-- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
--
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = 995, /* us */
-- .pwrdn_delay_max = 1005, /* us */
--};
--
--static const struct qmp_phy_cfg sc8180x_dpphy_cfg = {
-- .type = PHY_TYPE_DP,
-- .nlanes = 1,
--
-- .serdes_tbl = qmp_v4_dp_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
-- .tx_tbl = qmp_v4_dp_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
--
-- .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
-- .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
-- .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
-- .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
-- .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
-- .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
-- .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
-- .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
--
-- .clk_list = qmp_v3_phy_clk_l,
-- .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-- .reset_list = sc7180_usb3phy_reset_l,
-- .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = qmp_v3_usb3phy_regs_layout,
--
-- .has_phy_dp_com_ctrl = true,
-- .is_dual_lane_phy = true,
--
-- .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
-- .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
-- .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
-- .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
--};
--
--static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = {
-- .usb_cfg = &sm8150_usb3phy_cfg,
-- .dp_cfg = &sc8180x_dpphy_cfg,
--};
--
--static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
-- .type = PHY_TYPE_USB3,
-- .nlanes = 1,
--
-- .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-- .tx_tbl = sm8150_usb3_uniphy_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),
-- .rx_tbl = sm8150_usb3_uniphy_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
-- .pcs_tbl = sm8150_usb3_uniphy_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
-- .clk_list = qmp_v4_phy_clk_l,
-- .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-- .reset_list = msm8996_usb3phy_reset_l,
-- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = qmp_v4_usb3_uniphy_regs_layout,
--
-- .start_ctrl = SERDES_START | PCS_START,
-- .pwrdn_ctrl = SW_PWRDN,
-- .phy_status = PHYSTATUS,
--
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
--};
--
--static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
-- .type = PHY_TYPE_USB3,
-- .nlanes = 1,
--
-- .serdes_tbl = sm8150_usb3_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
-- .tx_tbl = sm8250_usb3_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl),
-- .rx_tbl = sm8250_usb3_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl),
-- .pcs_tbl = sm8250_usb3_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
-- .clk_list = qmp_v4_sm8250_usbphy_clk_l,
-- .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
-- .reset_list = msm8996_usb3phy_reset_l,
-- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = qmp_v4_usb3phy_regs_layout,
--
-- .start_ctrl = SERDES_START | PCS_START,
-- .pwrdn_ctrl = SW_PWRDN,
-- .phy_status = PHYSTATUS,
--
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
--
-- .has_phy_dp_com_ctrl = true,
-- .is_dual_lane_phy = true,
--};
--
--static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
-- .type = PHY_TYPE_USB3,
-- .nlanes = 1,
--
-- .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-- .tx_tbl = sm8250_usb3_uniphy_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),
-- .rx_tbl = sm8250_usb3_uniphy_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
-- .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
-- .clk_list = qmp_v4_phy_clk_l,
-- .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-- .reset_list = msm8996_usb3phy_reset_l,
-- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = qmp_v4_usb3_uniphy_regs_layout,
--
-- .start_ctrl = SERDES_START | PCS_START,
-- .pwrdn_ctrl = SW_PWRDN,
-- .phy_status = PHYSTATUS,
--
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
--};
--
--static const struct qmp_phy_cfg sm8250_dpphy_cfg = {
-- .type = PHY_TYPE_DP,
-- .nlanes = 1,
--
-- .serdes_tbl = qmp_v4_dp_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
-- .tx_tbl = qmp_v4_dp_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
--
-- .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
-- .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
-- .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
-- .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
-- .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
-- .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
-- .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
-- .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
--
-- .clk_list = qmp_v4_phy_clk_l,
-- .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-- .reset_list = msm8996_usb3phy_reset_l,
-- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = qmp_v4_usb3phy_regs_layout,
--
-- .has_phy_dp_com_ctrl = true,
-- .is_dual_lane_phy = true,
--
-- .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
-- .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
-- .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
-- .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
--};
--
--static const struct qmp_phy_combo_cfg sm8250_usb3dpphy_cfg = {
-- .usb_cfg = &sm8250_usb3phy_cfg,
-- .dp_cfg = &sm8250_dpphy_cfg,
--};
--
--static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
-- .type = PHY_TYPE_USB3,
-- .nlanes = 1,
--
-- .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-- .tx_tbl = sdx55_usb3_uniphy_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl),
-- .rx_tbl = sdx55_usb3_uniphy_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),
-- .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
-- .clk_list = qmp_v4_sdx55_usbphy_clk_l,
-- .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
-- .reset_list = msm8996_usb3phy_reset_l,
-- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = qmp_v4_usb3_uniphy_regs_layout,
--
-- .start_ctrl = SERDES_START | PCS_START,
-- .pwrdn_ctrl = SW_PWRDN,
-- .phy_status = PHYSTATUS,
--
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
--};
--
--static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
-- .type = PHY_TYPE_PCIE,
-- .nlanes = 2,
--
-- .serdes_tbl = sdx55_qmp_pcie_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl),
-- .tx_tbl = sdx55_qmp_pcie_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl),
-- .rx_tbl = sdx55_qmp_pcie_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl),
-- .pcs_tbl = sdx55_qmp_pcie_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl),
-- .pcs_misc_tbl = sdx55_qmp_pcie_pcs_misc_tbl,
-- .pcs_misc_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl),
-- .clk_list = sdm845_pciephy_clk_l,
-- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-- .reset_list = sdm845_pciephy_reset_l,
-- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = sm8250_pcie_regs_layout,
--
-- .start_ctrl = PCS_START | SERDES_START,
-- .pwrdn_ctrl = SW_PWRDN,
-- .phy_status = PHYSTATUS_4_20,
--
-- .is_dual_lane_phy = true,
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = 995, /* us */
-- .pwrdn_delay_max = 1005, /* us */
-+/**
-+ * struct qmp_phy - per-lane phy descriptor
-+ *
-+ * @phy: generic phy
-+ * @cfg: phy specific configuration
-+ * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
-+ * @tx: iomapped memory space for lane's tx
-+ * @rx: iomapped memory space for lane's rx
-+ * @pcs: iomapped memory space for lane's pcs
-+ * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
-+ * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
-+ * @pcs_misc: iomapped memory space for lane's pcs_misc
-+ * @pipe_clk: pipe clock
-+ * @index: lane index
-+ * @qmp: QMP phy to which this lane belongs
-+ * @lane_rst: lane's reset controller
-+ * @mode: current PHY mode
-+ * @dp_aux_cfg: Display port aux config
-+ * @dp_opts: Display port optional config
-+ * @dp_clks: Display port clocks
-+ */
-+struct qmp_phy {
-+ struct phy *phy;
-+ const struct qmp_phy_cfg *cfg;
-+ void __iomem *serdes;
-+ void __iomem *tx;
-+ void __iomem *rx;
-+ void __iomem *pcs;
-+ void __iomem *tx2;
-+ void __iomem *rx2;
-+ void __iomem *pcs_misc;
-+ struct clk *pipe_clk;
-+ unsigned int index;
-+ struct qcom_qmp *qmp;
-+ struct reset_control *lane_rst;
-+ enum phy_mode mode;
-+ unsigned int dp_aux_cfg;
-+ struct phy_configure_opts_dp dp_opts;
-+ struct qmp_phy_dp_clks *dp_clks;
- };
-
--static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
-- .type = PHY_TYPE_USB3,
-- .nlanes = 1,
--
-- .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-- .tx_tbl = sdx65_usb3_uniphy_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl),
-- .rx_tbl = sdx65_usb3_uniphy_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl),
-- .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
-- .clk_list = qmp_v4_sdx55_usbphy_clk_l,
-- .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
-- .reset_list = msm8996_usb3phy_reset_l,
-- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = sm8350_usb3_uniphy_regs_layout,
-+struct qmp_phy_dp_clks {
-+ struct qmp_phy *qphy;
-+ struct clk_hw dp_link_hw;
-+ struct clk_hw dp_pixel_hw;
-+};
-
-- .start_ctrl = SERDES_START | PCS_START,
-- .pwrdn_ctrl = SW_PWRDN,
-- .phy_status = PHYSTATUS,
-+/**
-+ * struct qcom_qmp - structure holding QMP phy block attributes
-+ *
-+ * @dev: device
-+ * @dp_com: iomapped memory space for phy's dp_com control block
-+ *
-+ * @clks: array of clocks required by phy
-+ * @resets: array of resets required by phy
-+ * @vregs: regulator supplies bulk data
-+ *
-+ * @phys: array of per-lane phy descriptors
-+ * @phy_mutex: mutex lock for PHY common block initialization
-+ * @init_count: phy common block initialization count
-+ * @ufs_reset: optional UFS PHY reset handle
-+ */
-+struct qcom_qmp {
-+ struct device *dev;
-+ void __iomem *dp_com;
-
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
--};
-+ struct clk_bulk_data *clks;
-+ struct reset_control **resets;
-+ struct regulator_bulk_data *vregs;
-
--static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
-- .type = PHY_TYPE_UFS,
-- .nlanes = 2,
--
-- .serdes_tbl = sm8350_ufsphy_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
-- .tx_tbl = sm8350_ufsphy_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
-- .rx_tbl = sm8350_ufsphy_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
-- .pcs_tbl = sm8350_ufsphy_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
-- .clk_list = sdm845_ufs_phy_clk_l,
-- .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = sm8150_ufsphy_regs_layout,
-+ struct qmp_phy **phys;
-
-- .start_ctrl = SERDES_START,
-- .pwrdn_ctrl = SW_PWRDN,
-- .phy_status = PHYSTATUS,
-+ struct mutex phy_mutex;
-+ int init_count;
-
-- .is_dual_lane_phy = true,
-+ struct reset_control *ufs_reset;
- };
-
--static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
-- .type = PHY_TYPE_USB3,
-- .nlanes = 1,
--
-- .serdes_tbl = sm8150_usb3_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
-- .tx_tbl = sm8350_usb3_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl),
-- .rx_tbl = sm8350_usb3_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl),
-- .pcs_tbl = sm8350_usb3_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl),
-- .clk_list = qmp_v4_sm8250_usbphy_clk_l,
-- .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
-- .reset_list = msm8996_usb3phy_reset_l,
-- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = qmp_v4_usb3phy_regs_layout,
-+static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
-+{
-+ u32 reg;
-
-- .start_ctrl = SERDES_START | PCS_START,
-- .pwrdn_ctrl = SW_PWRDN,
-- .phy_status = PHYSTATUS,
-+ reg = readl(base + offset);
-+ reg |= val;
-+ writel(reg, base + offset);
-
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+ /* ensure that above write is through */
-+ readl(base + offset);
-+}
-
-- .has_phy_dp_com_ctrl = true,
-- .is_dual_lane_phy = true,
--};
-+static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
-+{
-+ u32 reg;
-
--static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
-- .type = PHY_TYPE_USB3,
-- .nlanes = 1,
--
-- .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
-- .tx_tbl = sm8350_usb3_uniphy_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),
-- .rx_tbl = sm8350_usb3_uniphy_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),
-- .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
-- .clk_list = qmp_v4_phy_clk_l,
-- .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-- .reset_list = msm8996_usb3phy_reset_l,
-- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = sm8350_usb3_uniphy_regs_layout,
-+ reg = readl(base + offset);
-+ reg &= ~val;
-+ writel(reg, base + offset);
-
-- .start_ctrl = SERDES_START | PCS_START,
-- .pwrdn_ctrl = SW_PWRDN,
-- .phy_status = PHYSTATUS,
-+ /* ensure that above write is through */
-+ readl(base + offset);
-+}
-
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
-+/* list of clocks required by phy */
-+static const char * const msm8996_phy_clk_l[] = {
-+ "aux", "cfg_ahb", "ref",
- };
-
--static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
-- .type = PHY_TYPE_UFS,
-- .nlanes = 2,
--
-- .serdes_tbl = sm8350_ufsphy_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
-- .tx_tbl = sm8350_ufsphy_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
-- .rx_tbl = sm8350_ufsphy_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
-- .pcs_tbl = sm8350_ufsphy_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
-- .clk_list = sm8450_ufs_phy_clk_l,
-- .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = sm8150_ufsphy_regs_layout,
--
-- .start_ctrl = SERDES_START,
-- .pwrdn_ctrl = SW_PWRDN,
-- .phy_status = PHYSTATUS,
--
-- .is_dual_lane_phy = true,
-+/* list of resets */
-+static const char * const msm8996_pciephy_reset_l[] = {
-+ "phy", "common", "cfg",
- };
-
--static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
-- .type = PHY_TYPE_PCIE,
-- .nlanes = 1,
--
-- .serdes_tbl = sm8450_qmp_gen3x1_pcie_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl),
-- .tx_tbl = sm8450_qmp_gen3x1_pcie_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl),
-- .rx_tbl = sm8450_qmp_gen3x1_pcie_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl),
-- .pcs_tbl = sm8450_qmp_gen3x1_pcie_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl),
-- .pcs_misc_tbl = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
-- .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
-- .clk_list = sdm845_pciephy_clk_l,
-- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-- .reset_list = sdm845_pciephy_reset_l,
-- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = sm8250_pcie_regs_layout,
--
-- .start_ctrl = SERDES_START | PCS_START,
-- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-- .phy_status = PHYSTATUS,
--
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = 995, /* us */
-- .pwrdn_delay_max = 1005, /* us */
-+/* list of regulators */
-+static const char * const qmp_phy_vreg_l[] = {
-+ "vdda-phy", "vdda-pll",
- };
-
--static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
-- .type = PHY_TYPE_PCIE,
-- .nlanes = 2,
--
-- .serdes_tbl = sm8450_qmp_gen4x2_pcie_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl),
-- .tx_tbl = sm8450_qmp_gen4x2_pcie_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl),
-- .rx_tbl = sm8450_qmp_gen4x2_pcie_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl),
-- .pcs_tbl = sm8450_qmp_gen4x2_pcie_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl),
-- .pcs_misc_tbl = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl,
-- .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl),
-- .clk_list = sdm845_pciephy_clk_l,
-- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-- .reset_list = sdm845_pciephy_reset_l,
-- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = sm8250_pcie_regs_layout,
--
-- .start_ctrl = SERDES_START | PCS_START,
-- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-- .phy_status = PHYSTATUS_4_20,
--
-- .is_dual_lane_phy = true,
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = 995, /* us */
-- .pwrdn_delay_max = 1005, /* us */
--};
-+static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 3,
-
--static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
-- .type = PHY_TYPE_USB3,
-- .nlanes = 1,
--
-- .serdes_tbl = qcm2290_usb3_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl),
-- .tx_tbl = qcm2290_usb3_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl),
-- .rx_tbl = qcm2290_usb3_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(qcm2290_usb3_rx_tbl),
-- .pcs_tbl = qcm2290_usb3_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl),
-- .clk_list = qcm2290_usb3phy_clk_l,
-- .num_clks = ARRAY_SIZE(qcm2290_usb3phy_clk_l),
-- .reset_list = qcm2290_usb3phy_reset_l,
-- .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
-+ .serdes_tbl = msm8996_pcie_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
-+ .tx_tbl = msm8996_pcie_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(msm8996_pcie_tx_tbl),
-+ .rx_tbl = msm8996_pcie_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(msm8996_pcie_rx_tbl),
-+ .pcs_tbl = msm8996_pcie_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
-+ .clk_list = msm8996_phy_clk_l,
-+ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-+ .reset_list = msm8996_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l),
- .vreg_list = qmp_phy_vreg_l,
- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = qcm2290_usb3phy_regs_layout,
-+ .regs = pciephy_regs_layout,
-
-- .start_ctrl = SERDES_START | PCS_START,
-- .pwrdn_ctrl = SW_PWRDN,
-+ .start_ctrl = PCS_START | PLL_READY_GATE_EN,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+ .mask_com_pcs_ready = PCS_READY,
- .phy_status = PHYSTATUS,
-
-- .is_dual_lane_phy = true,
-+ .has_phy_com_ctrl = true,
-+ .has_lane_rst = true,
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
- };
-
- static void qcom_qmp_phy_configure_lane(void __iomem *base,
-@@ -4589,457 +572,10 @@ static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
- return 0;
- }
-
--static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy)
--{
-- writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
-- DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
-- qphy->pcs + QSERDES_DP_PHY_PD_CTL);
--
-- /* Turn on BIAS current for PHY/PLL */
-- writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
-- QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
-- qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
--
-- writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
--
-- writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
-- DP_PHY_PD_CTL_LANE_0_1_PWRDN |
-- DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
-- DP_PHY_PD_CTL_DP_CLAMP_EN,
-- qphy->pcs + QSERDES_DP_PHY_PD_CTL);
--
-- writel(QSERDES_V3_COM_BIAS_EN |
-- QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
-- QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL |
-- QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
-- qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
--
-- writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
-- writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-- writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
-- writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
-- writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
-- writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
-- writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
-- writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
-- writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
-- writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
-- qphy->dp_aux_cfg = 0;
--
-- writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
-- PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
-- PHY_AUX_REQ_ERR_MASK,
-- qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
--}
--
--static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = {
-- { 0x00, 0x0c, 0x15, 0x1a },
-- { 0x02, 0x0e, 0x16, 0xff },
-- { 0x02, 0x11, 0xff, 0xff },
-- { 0x04, 0xff, 0xff, 0xff }
--};
--
--static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = {
-- { 0x02, 0x12, 0x16, 0x1a },
-- { 0x09, 0x19, 0x1f, 0xff },
-- { 0x10, 0x1f, 0xff, 0xff },
-- { 0x1f, 0xff, 0xff, 0xff }
--};
--
--static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = {
-- { 0x00, 0x0c, 0x14, 0x19 },
-- { 0x00, 0x0b, 0x12, 0xff },
-- { 0x00, 0x0b, 0xff, 0xff },
-- { 0x04, 0xff, 0xff, 0xff }
--};
--
--static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = {
-- { 0x08, 0x0f, 0x16, 0x1f },
-- { 0x11, 0x1e, 0x1f, 0xff },
-- { 0x19, 0x1f, 0xff, 0xff },
-- { 0x1f, 0xff, 0xff, 0xff }
--};
--
--static int qcom_qmp_phy_configure_dp_swing(struct qmp_phy *qphy,
-- unsigned int drv_lvl_reg, unsigned int emp_post_reg)
--{
-- const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-- unsigned int v_level = 0, p_level = 0;
-- u8 voltage_swing_cfg, pre_emphasis_cfg;
-- int i;
--
-- for (i = 0; i < dp_opts->lanes; i++) {
-- v_level = max(v_level, dp_opts->voltage[i]);
-- p_level = max(p_level, dp_opts->pre[i]);
-- }
--
-- if (dp_opts->link_rate <= 2700) {
-- voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level];
-- pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level];
-- } else {
-- voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr3_hbr2[v_level][p_level];
-- pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr3_hbr2[v_level][p_level];
-- }
--
-- /* TODO: Move check to config check */
-- if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF)
-- return -EINVAL;
--
-- /* Enable MUX to use Cursor values from these registers */
-- voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
-- pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
--
-- writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg);
-- writel(pre_emphasis_cfg, qphy->tx + emp_post_reg);
-- writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg);
-- writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg);
--
-- return 0;
--}
--
--static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy)
--{
-- const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-- u32 bias_en, drvr_en;
--
-- if (qcom_qmp_phy_configure_dp_swing(qphy,
-- QSERDES_V3_TX_TX_DRV_LVL,
-- QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0)
-- return;
--
-- if (dp_opts->lanes == 1) {
-- bias_en = 0x3e;
-- drvr_en = 0x13;
-- } else {
-- bias_en = 0x3f;
-- drvr_en = 0x10;
-- }
--
-- writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN);
-- writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
-- writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN);
-- writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
--}
--
--static bool qcom_qmp_phy_configure_dp_mode(struct qmp_phy *qphy)
--{
-- u32 val;
-- bool reverse = false;
--
-- val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
-- DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN;
--
-- /*
-- * TODO: Assume orientation is CC1 for now and two lanes, need to
-- * use type-c connector to understand orientation and lanes.
-- *
-- * Otherwise val changes to be like below if this code understood
-- * the orientation of the type-c cable.
-- *
-- * if (lane_cnt == 4 || orientation == ORIENTATION_CC2)
-- * val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN;
-- * if (lane_cnt == 4 || orientation == ORIENTATION_CC1)
-- * val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
-- * if (orientation == ORIENTATION_CC2)
-- * writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
-- */
-- val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
-- writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
--
-- writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE);
--
-- return reverse;
--}
--
--static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy)
--{
-- const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
-- const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-- u32 phy_vco_div, status;
-- unsigned long pixel_freq;
--
-- qcom_qmp_phy_configure_dp_mode(qphy);
--
-- writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
-- writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
--
-- switch (dp_opts->link_rate) {
-- case 1620:
-- phy_vco_div = 0x1;
-- pixel_freq = 1620000000UL / 2;
-- break;
-- case 2700:
-- phy_vco_div = 0x1;
-- pixel_freq = 2700000000UL / 2;
-- break;
-- case 5400:
-- phy_vco_div = 0x2;
-- pixel_freq = 5400000000UL / 4;
-- break;
-- case 8100:
-- phy_vco_div = 0x0;
-- pixel_freq = 8100000000UL / 6;
-- break;
-- default:
-- /* Other link rates aren't supported */
-- return -EINVAL;
-- }
-- writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV);
--
-- clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
-- clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
--
-- writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
-- writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
-- writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
-- writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
-- writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
--
-- writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL);
--
-- if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS,
-- status,
-- ((status & BIT(0)) > 0),
-- 500,
-- 10000))
-- return -ETIMEDOUT;
--
-- writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
--
-- if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
-- status,
-- ((status & BIT(1)) > 0),
-- 500,
-- 10000))
-- return -ETIMEDOUT;
--
-- writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
-- udelay(2000);
-- writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
--
-- return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
-- status,
-- ((status & BIT(1)) > 0),
-- 500,
-- 10000);
--}
--
--/*
-- * We need to calibrate the aux setting here as many times
-- * as the caller tries
-- */
--static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy)
--{
-- static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d };
-- u8 val;
--
-- qphy->dp_aux_cfg++;
-- qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
-- val = cfg1_settings[qphy->dp_aux_cfg];
--
-- writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
--
-- return 0;
--}
--
--static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy)
--{
-- writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
-- DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
-- qphy->pcs + QSERDES_DP_PHY_PD_CTL);
--
-- /* Turn on BIAS current for PHY/PLL */
-- writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN);
--
-- writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
-- writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-- writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
-- writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
-- writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
-- writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
-- writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
-- writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
-- writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
-- writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
-- qphy->dp_aux_cfg = 0;
--
-- writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
-- PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
-- PHY_AUX_REQ_ERR_MASK,
-- qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
--}
--
--static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy)
--{
-- /* Program default values before writing proper values */
-- writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
-- writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
--
-- writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
-- writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
--
-- qcom_qmp_phy_configure_dp_swing(qphy,
-- QSERDES_V4_TX_TX_DRV_LVL,
-- QSERDES_V4_TX_TX_EMP_POST1_LVL);
--}
--
--static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy)
--{
-- const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
-- const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-- u32 phy_vco_div, status;
-- unsigned long pixel_freq;
-- u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
-- bool reverse;
--
-- writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1);
--
-- reverse = qcom_qmp_phy_configure_dp_mode(qphy);
--
-- writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-- writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
--
-- writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL);
-- writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL);
--
-- switch (dp_opts->link_rate) {
-- case 1620:
-- phy_vco_div = 0x1;
-- pixel_freq = 1620000000UL / 2;
-- break;
-- case 2700:
-- phy_vco_div = 0x1;
-- pixel_freq = 2700000000UL / 2;
-- break;
-- case 5400:
-- phy_vco_div = 0x2;
-- pixel_freq = 5400000000UL / 4;
-- break;
-- case 8100:
-- phy_vco_div = 0x0;
-- pixel_freq = 8100000000UL / 6;
-- break;
-- default:
-- /* Other link rates aren't supported */
-- return -EINVAL;
-- }
-- writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV);
--
-- clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
-- clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
--
-- writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
-- writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
-- writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
-- writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
--
-- writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL);
--
-- if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS,
-- status,
-- ((status & BIT(0)) > 0),
-- 500,
-- 10000))
-- return -ETIMEDOUT;
--
-- if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
-- status,
-- ((status & BIT(0)) > 0),
-- 500,
-- 10000))
-- return -ETIMEDOUT;
--
-- if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
-- status,
-- ((status & BIT(1)) > 0),
-- 500,
-- 10000))
-- return -ETIMEDOUT;
--
-- writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
--
-- if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
-- status,
-- ((status & BIT(0)) > 0),
-- 500,
-- 10000))
-- return -ETIMEDOUT;
--
-- if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
-- status,
-- ((status & BIT(1)) > 0),
-- 500,
-- 10000))
-- return -ETIMEDOUT;
--
-- /*
-- * At least for 7nm DP PHY this has to be done after enabling link
-- * clock.
-- */
--
-- if (dp_opts->lanes == 1) {
-- bias0_en = reverse ? 0x3e : 0x15;
-- bias1_en = reverse ? 0x15 : 0x3e;
-- drvr0_en = reverse ? 0x13 : 0x10;
-- drvr1_en = reverse ? 0x10 : 0x13;
-- } else if (dp_opts->lanes == 2) {
-- bias0_en = reverse ? 0x3f : 0x15;
-- bias1_en = reverse ? 0x15 : 0x3f;
-- drvr0_en = 0x10;
-- drvr1_en = 0x10;
-- } else {
-- bias0_en = 0x3f;
-- bias1_en = 0x3f;
-- drvr0_en = 0x10;
-- drvr1_en = 0x10;
-- }
--
-- writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN);
-- writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
-- writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN);
-- writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
--
-- writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
-- udelay(2000);
-- writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
--
-- if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
-- status,
-- ((status & BIT(1)) > 0),
-- 500,
-- 10000))
-- return -ETIMEDOUT;
--
-- writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV);
-- writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV);
--
-- writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
-- writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
--
-- writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
-- writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
--
-- return 0;
--}
--
- /*
- * We need to calibrate the aux setting here as many times
- * as the caller tries
- */
--static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy)
--{
-- static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d };
-- u8 val;
--
-- qphy->dp_aux_cfg++;
-- qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
-- val = cfg1_settings[qphy->dp_aux_cfg];
--
-- writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
--
-- return 0;
--}
--
- static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
- {
- const struct phy_configure_opts_dp *dp_opts = &opts->dp;
-@@ -6021,161 +1557,13 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
-
- static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
- {
-- .compatible = "qcom,ipq8074-qmp-usb3-phy",
-- .data = &ipq8074_usb3phy_cfg,
-- }, {
- .compatible = "qcom,msm8996-qmp-pcie-phy",
- .data = &msm8996_pciephy_cfg,
-- }, {
-- .compatible = "qcom,msm8996-qmp-ufs-phy",
-- .data = &msm8996_ufs_cfg,
-- }, {
-- .compatible = "qcom,msm8996-qmp-usb3-phy",
-- .data = &msm8996_usb3phy_cfg,
-- }, {
-- .compatible = "qcom,msm8998-qmp-pcie-phy",
-- .data = &msm8998_pciephy_cfg,
-- }, {
-- .compatible = "qcom,msm8998-qmp-ufs-phy",
-- .data = &sdm845_ufsphy_cfg,
-- }, {
-- .compatible = "qcom,ipq8074-qmp-pcie-phy",
-- .data = &ipq8074_pciephy_cfg,
-- }, {
-- .compatible = "qcom,ipq6018-qmp-pcie-phy",
-- .data = &ipq6018_pciephy_cfg,
-- }, {
-- .compatible = "qcom,ipq6018-qmp-usb3-phy",
-- .data = &ipq8074_usb3phy_cfg,
-- }, {
-- .compatible = "qcom,sc7180-qmp-usb3-phy",
-- .data = &sc7180_usb3phy_cfg,
-- }, {
-- .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
-- /* It's a combo phy */
-- }, {
-- .compatible = "qcom,sc8180x-qmp-pcie-phy",
-- .data = &sc8180x_pciephy_cfg,
-- }, {
-- .compatible = "qcom,sc8180x-qmp-ufs-phy",
-- .data = &sm8150_ufsphy_cfg,
-- }, {
-- .compatible = "qcom,sc8280xp-qmp-ufs-phy",
-- .data = &sm8350_ufsphy_cfg,
-- }, {
-- .compatible = "qcom,sc8180x-qmp-usb3-phy",
-- .data = &sm8150_usb3phy_cfg,
-- }, {
-- .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
-- /* It's a combo phy */
-- }, {
-- .compatible = "qcom,sdm845-qhp-pcie-phy",
-- .data = &sdm845_qhp_pciephy_cfg,
-- }, {
-- .compatible = "qcom,sdm845-qmp-pcie-phy",
-- .data = &sdm845_qmp_pciephy_cfg,
-- }, {
-- .compatible = "qcom,sdm845-qmp-usb3-phy",
-- .data = &qmp_v3_usb3phy_cfg,
-- }, {
-- .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
-- .data = &qmp_v3_usb3_uniphy_cfg,
-- }, {
-- .compatible = "qcom,sdm845-qmp-ufs-phy",
-- .data = &sdm845_ufsphy_cfg,
-- }, {
-- .compatible = "qcom,msm8998-qmp-usb3-phy",
-- .data = &msm8998_usb3phy_cfg,
-- }, {
-- .compatible = "qcom,sm6115-qmp-ufs-phy",
-- .data = &sm6115_ufsphy_cfg,
-- }, {
-- .compatible = "qcom,sm6350-qmp-ufs-phy",
-- .data = &sdm845_ufsphy_cfg,
-- }, {
-- .compatible = "qcom,sm8150-qmp-ufs-phy",
-- .data = &sm8150_ufsphy_cfg,
-- }, {
-- .compatible = "qcom,sm8250-qmp-ufs-phy",
-- .data = &sm8150_ufsphy_cfg,
-- }, {
-- .compatible = "qcom,sm8150-qmp-usb3-phy",
-- .data = &sm8150_usb3phy_cfg,
-- }, {
-- .compatible = "qcom,sm8150-qmp-usb3-uni-phy",
-- .data = &sm8150_usb3_uniphy_cfg,
-- }, {
-- .compatible = "qcom,sm8250-qmp-usb3-phy",
-- .data = &sm8250_usb3phy_cfg,
-- }, {
-- .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
-- /* It's a combo phy */
-- }, {
-- .compatible = "qcom,sm8250-qmp-usb3-uni-phy",
-- .data = &sm8250_usb3_uniphy_cfg,
-- }, {
-- .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
-- .data = &sm8250_qmp_gen3x1_pciephy_cfg,
-- }, {
-- .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
-- .data = &sm8250_qmp_gen3x2_pciephy_cfg,
-- }, {
-- .compatible = "qcom,sm8350-qmp-ufs-phy",
-- .data = &sm8350_ufsphy_cfg,
-- }, {
-- .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
-- .data = &sm8250_qmp_gen3x2_pciephy_cfg,
-- }, {
-- .compatible = "qcom,sdx55-qmp-pcie-phy",
-- .data = &sdx55_qmp_pciephy_cfg,
-- }, {
-- .compatible = "qcom,sdx55-qmp-usb3-uni-phy",
-- .data = &sdx55_usb3_uniphy_cfg,
-- }, {
-- .compatible = "qcom,sdx65-qmp-usb3-uni-phy",
-- .data = &sdx65_usb3_uniphy_cfg,
-- }, {
-- .compatible = "qcom,sm8350-qmp-usb3-phy",
-- .data = &sm8350_usb3phy_cfg,
-- }, {
-- .compatible = "qcom,sm8350-qmp-usb3-uni-phy",
-- .data = &sm8350_usb3_uniphy_cfg,
-- }, {
-- .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
-- .data = &sm8450_qmp_gen3x1_pciephy_cfg,
-- }, {
-- .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
-- .data = &sm8450_qmp_gen4x2_pciephy_cfg,
-- }, {
-- .compatible = "qcom,sm8450-qmp-ufs-phy",
-- .data = &sm8450_ufsphy_cfg,
-- }, {
-- .compatible = "qcom,sm8450-qmp-usb3-phy",
-- .data = &sm8350_usb3phy_cfg,
-- }, {
-- .compatible = "qcom,qcm2290-qmp-usb3-phy",
-- .data = &qcm2290_usb3phy_cfg,
- },
- { },
- };
- MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
-
--static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = {
-- {
-- .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
-- .data = &sc7180_usb3dpphy_cfg,
-- },
-- {
-- .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
-- .data = &sm8250_usb3dpphy_cfg,
-- },
-- {
-- .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
-- .data = &sc8180x_usb3dpphy_cfg,
-- },
-- { }
--};
--
- static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
- SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
- qcom_qmp_phy_runtime_resume, NULL)
-@@ -6206,20 +1594,8 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
-
- /* Get the specific init parameters of QMP phy */
- cfg = of_device_get_match_data(dev);
-- if (!cfg) {
-- const struct of_device_id *match;
--
-- match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev);
-- if (!match)
-- return -EINVAL;
--
-- combo_cfg = match->data;
-- if (!combo_cfg)
-- return -EINVAL;
--
-- usb_cfg = combo_cfg->usb_cfg;
-- cfg = usb_cfg; /* Setup clks and regulators */
-- }
-+ if (!cfg)
-+ return -EINVAL;
-
- /* per PHY serdes; usually located at base address */
- usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0);
-@@ -6337,7 +1713,7 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
- static struct platform_driver qcom_qmp_phy_driver = {
- .probe = qcom_qmp_phy_probe,
- .driver = {
-- .name = "qcom-qmp-phy",
-+ .name = "qcom-qmp-msm8996-pcie-phy",
- .pm = &qcom_qmp_phy_pm_ops,
- .of_match_table = qcom_qmp_phy_of_match_table,
- },
-@@ -6346,5 +1722,5 @@ static struct platform_driver qcom_qmp_phy_driver = {
- module_platform_driver(qcom_qmp_phy_driver);
-
- MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
--MODULE_DESCRIPTION("Qualcomm QMP PHY driver");
-+MODULE_DESCRIPTION("Qualcomm QMP MSM8996 PCIe PHY driver");
- MODULE_LICENSE("GPL v2");
---
-2.35.1
-
+++ /dev/null
-From 92b851087d73968358ef5624044c5747b5e01730 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Wed, 8 Jun 2022 00:31:49 +0300
-Subject: phy: qcom-qmp-pcie-msm8996: drop support for non-PCIe PHY types
-
-From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-
-[ Upstream commit f575ac2d64e7cedb2d70acd5baa359da216cf718 ]
-
-Drop remaining support for PHY types other than PCIe.
-
-Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> # UFS, PCIe and USB on SC8180X
-Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Link: https://lore.kernel.org/r/20220607213203.2819885-17-dmitry.baryshkov@linaro.org
-Signed-off-by: Vinod Koul <vkoul@kernel.org>
-Stable-dep-of: 1f69ededf8e8 ("phy: qcom-qmp-pcie-msm8996: fix memleak on probe deferral")
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- .../phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 532 ++----------------
- 1 file changed, 43 insertions(+), 489 deletions(-)
-
-diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
-index 1741a5675f9a..02e5ae7fa213 100644
---- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
-+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
-@@ -510,7 +510,6 @@ static int qcom_qmp_phy_pcie_msm8996_serdes_init(struct qmp_phy *qphy)
- struct qcom_qmp *qmp = qphy->qmp;
- const struct qmp_phy_cfg *cfg = qphy->cfg;
- void __iomem *serdes = qphy->serdes;
-- const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
- const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
- int serdes_tbl_num = cfg->serdes_tbl_num;
- int ret;
-@@ -520,35 +519,6 @@ static int qcom_qmp_phy_pcie_msm8996_serdes_init(struct qmp_phy *qphy)
- qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
- cfg->serdes_tbl_num_sec);
-
-- if (cfg->type == PHY_TYPE_DP) {
-- switch (dp_opts->link_rate) {
-- case 1620:
-- qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs,
-- cfg->serdes_tbl_rbr,
-- cfg->serdes_tbl_rbr_num);
-- break;
-- case 2700:
-- qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs,
-- cfg->serdes_tbl_hbr,
-- cfg->serdes_tbl_hbr_num);
-- break;
-- case 5400:
-- qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs,
-- cfg->serdes_tbl_hbr2,
-- cfg->serdes_tbl_hbr2_num);
-- break;
-- case 8100:
-- qcom_qmp_phy_pcie_msm8996_configure(serdes, cfg->regs,
-- cfg->serdes_tbl_hbr3,
-- cfg->serdes_tbl_hbr3_num);
-- break;
-- default:
-- /* Other link rates aren't supported */
-- return -EINVAL;
-- }
-- }
--
--
- if (cfg->has_phy_com_ctrl) {
- void __iomem *status;
- unsigned int mask, val;
-@@ -572,36 +542,6 @@ static int qcom_qmp_phy_pcie_msm8996_serdes_init(struct qmp_phy *qphy)
- return 0;
- }
-
--/*
-- * We need to calibrate the aux setting here as many times
-- * as the caller tries
-- */
--static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
--{
-- const struct phy_configure_opts_dp *dp_opts = &opts->dp;
-- struct qmp_phy *qphy = phy_get_drvdata(phy);
-- const struct qmp_phy_cfg *cfg = qphy->cfg;
--
-- memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts));
-- if (qphy->dp_opts.set_voltages) {
-- cfg->configure_dp_tx(qphy);
-- qphy->dp_opts.set_voltages = 0;
-- }
--
-- return 0;
--}
--
--static int qcom_qmp_dp_phy_calibrate(struct phy *phy)
--{
-- struct qmp_phy *qphy = phy_get_drvdata(phy);
-- const struct qmp_phy_cfg *cfg = qphy->cfg;
--
-- if (cfg->calibrate_dp_phy)
-- return cfg->calibrate_dp_phy(qphy);
--
-- return 0;
--}
--
- static int qcom_qmp_phy_pcie_msm8996_com_init(struct qmp_phy *qphy)
- {
- struct qcom_qmp *qmp = qphy->qmp;
-@@ -771,9 +711,6 @@ static int qcom_qmp_phy_pcie_msm8996_init(struct phy *phy)
- if (ret)
- return ret;
-
-- if (cfg->type == PHY_TYPE_DP)
-- cfg->dp_aux_init(qphy);
--
- return 0;
- }
-
-@@ -824,10 +761,6 @@ static int qcom_qmp_phy_pcie_msm8996_power_on(struct phy *phy)
- cfg->tx_tbl_num_sec, 2);
- }
-
-- /* Configure special DP tx tunings */
-- if (cfg->type == PHY_TYPE_DP)
-- cfg->configure_dp_tx(qphy);
--
- qcom_qmp_phy_pcie_msm8996_configure_lane(rx, cfg->regs,
- cfg->rx_tbl, cfg->rx_tbl_num, 1);
- if (cfg->rx_tbl_sec)
-@@ -843,15 +776,10 @@ static int qcom_qmp_phy_pcie_msm8996_power_on(struct phy *phy)
- cfg->rx_tbl_num_sec, 2);
- }
-
-- /* Configure link rate, swing, etc. */
-- if (cfg->type == PHY_TYPE_DP) {
-- cfg->configure_dp_phy(qphy);
-- } else {
-- qcom_qmp_phy_pcie_msm8996_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
-- if (cfg->pcs_tbl_sec)
-- qcom_qmp_phy_pcie_msm8996_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
-- cfg->pcs_tbl_num_sec);
-- }
-+ qcom_qmp_phy_pcie_msm8996_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
-+ if (cfg->pcs_tbl_sec)
-+ qcom_qmp_phy_pcie_msm8996_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
-+ cfg->pcs_tbl_num_sec);
-
- ret = reset_control_deassert(qmp->ufs_reset);
- if (ret)
-@@ -867,36 +795,28 @@ static int qcom_qmp_phy_pcie_msm8996_power_on(struct phy *phy)
- * Pull out PHY from POWER DOWN state.
- * This is active low enable signal to power-down PHY.
- */
-- if(cfg->type == PHY_TYPE_PCIE)
-- qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
-+ qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
-
- if (cfg->has_pwrdn_delay)
- usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
-
-- if (cfg->type != PHY_TYPE_DP) {
-- /* Pull PHY out of reset state */
-- if (!cfg->no_pcs_sw_reset)
-- qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
-- /* start SerDes and Phy-Coding-Sublayer */
-- qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
--
-- if (cfg->type == PHY_TYPE_UFS) {
-- status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
-- mask = PCS_READY;
-- ready = PCS_READY;
-- } else {
-- status = pcs + cfg->regs[QPHY_PCS_STATUS];
-- mask = cfg->phy_status;
-- ready = 0;
-- }
-+ /* Pull PHY out of reset state */
-+ if (!cfg->no_pcs_sw_reset)
-+ qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
-+ /* start SerDes and Phy-Coding-Sublayer */
-+ qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
-
-- ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
-- PHY_INIT_COMPLETE_TIMEOUT);
-- if (ret) {
-- dev_err(qmp->dev, "phy initialization timed-out\n");
-- goto err_disable_pipe_clk;
-- }
-+ status = pcs + cfg->regs[QPHY_PCS_STATUS];
-+ mask = cfg->phy_status;
-+ ready = 0;
-+
-+ ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
-+ PHY_INIT_COMPLETE_TIMEOUT);
-+ if (ret) {
-+ dev_err(qmp->dev, "phy initialization timed-out\n");
-+ goto err_disable_pipe_clk;
- }
-+
- return 0;
-
- err_disable_pipe_clk:
-@@ -915,25 +835,20 @@ static int qcom_qmp_phy_pcie_msm8996_power_off(struct phy *phy)
-
- clk_disable_unprepare(qphy->pipe_clk);
-
-- if (cfg->type == PHY_TYPE_DP) {
-- /* Assert DP PHY power down */
-- writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-- } else {
-- /* PHY reset */
-- if (!cfg->no_pcs_sw_reset)
-- qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
-+ /* PHY reset */
-+ if (!cfg->no_pcs_sw_reset)
-+ qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
-
-- /* stop SerDes and Phy-Coding-Sublayer */
-- qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
-+ /* stop SerDes and Phy-Coding-Sublayer */
-+ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
-
-- /* Put PHY into POWER DOWN state: active low */
-- if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
-- qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
-- cfg->pwrdn_ctrl);
-- } else {
-- qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
-- cfg->pwrdn_ctrl);
-- }
-+ /* Put PHY into POWER DOWN state: active low */
-+ if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
-+ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
-+ cfg->pwrdn_ctrl);
-+ } else {
-+ qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
-+ cfg->pwrdn_ctrl);
- }
-
- return 0;
-@@ -987,112 +902,6 @@ static int qcom_qmp_phy_pcie_msm8996_set_mode(struct phy *phy,
- return 0;
- }
-
--static void qcom_qmp_phy_pcie_msm8996_enable_autonomous_mode(struct qmp_phy *qphy)
--{
-- const struct qmp_phy_cfg *cfg = qphy->cfg;
-- void __iomem *pcs = qphy->pcs;
-- void __iomem *pcs_misc = qphy->pcs_misc;
-- u32 intr_mask;
--
-- if (qphy->mode == PHY_MODE_USB_HOST_SS ||
-- qphy->mode == PHY_MODE_USB_DEVICE_SS)
-- intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
-- else
-- intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
--
-- /* Clear any pending interrupts status */
-- qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
-- /* Writing 1 followed by 0 clears the interrupt */
-- qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
--
-- qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
-- ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
--
-- /* Enable required PHY autonomous mode interrupts */
-- qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
--
-- /* Enable i/o clamp_n for autonomous mode */
-- if (pcs_misc)
-- qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
--}
--
--static void qcom_qmp_phy_pcie_msm8996_disable_autonomous_mode(struct qmp_phy *qphy)
--{
-- const struct qmp_phy_cfg *cfg = qphy->cfg;
-- void __iomem *pcs = qphy->pcs;
-- void __iomem *pcs_misc = qphy->pcs_misc;
--
-- /* Disable i/o clamp_n on resume for normal mode */
-- if (pcs_misc)
-- qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
--
-- qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
-- ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
--
-- qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
-- /* Writing 1 followed by 0 clears the interrupt */
-- qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
--}
--
--static int __maybe_unused qcom_qmp_phy_pcie_msm8996_runtime_suspend(struct device *dev)
--{
-- struct qcom_qmp *qmp = dev_get_drvdata(dev);
-- struct qmp_phy *qphy = qmp->phys[0];
-- const struct qmp_phy_cfg *cfg = qphy->cfg;
--
-- dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode);
--
-- /* Supported only for USB3 PHY and luckily USB3 is the first phy */
-- if (cfg->type != PHY_TYPE_USB3)
-- return 0;
--
-- if (!qmp->init_count) {
-- dev_vdbg(dev, "PHY not initialized, bailing out\n");
-- return 0;
-- }
--
-- qcom_qmp_phy_pcie_msm8996_enable_autonomous_mode(qphy);
--
-- clk_disable_unprepare(qphy->pipe_clk);
-- clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
--
-- return 0;
--}
--
--static int __maybe_unused qcom_qmp_phy_pcie_msm8996_runtime_resume(struct device *dev)
--{
-- struct qcom_qmp *qmp = dev_get_drvdata(dev);
-- struct qmp_phy *qphy = qmp->phys[0];
-- const struct qmp_phy_cfg *cfg = qphy->cfg;
-- int ret = 0;
--
-- dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode);
--
-- /* Supported only for USB3 PHY and luckily USB3 is the first phy */
-- if (cfg->type != PHY_TYPE_USB3)
-- return 0;
--
-- if (!qmp->init_count) {
-- dev_vdbg(dev, "PHY not initialized, bailing out\n");
-- return 0;
-- }
--
-- ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
-- if (ret)
-- return ret;
--
-- ret = clk_prepare_enable(qphy->pipe_clk);
-- if (ret) {
-- dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
-- clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
-- return ret;
-- }
--
-- qcom_qmp_phy_pcie_msm8996_disable_autonomous_mode(qphy);
--
-- return 0;
--}
--
- static int qcom_qmp_phy_pcie_msm8996_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
- {
- struct qcom_qmp *qmp = dev_get_drvdata(dev);
-@@ -1210,223 +1019,13 @@ static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
- return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
- }
-
--/*
-- * Display Port PLL driver block diagram for branch clocks
-- *
-- * +------------------------------+
-- * | DP_VCO_CLK |
-- * | |
-- * | +-------------------+ |
-- * | | (DP PLL/VCO) | |
-- * | +---------+---------+ |
-- * | v |
-- * | +----------+-----------+ |
-- * | | hsclk_divsel_clk_src | |
-- * | +----------+-----------+ |
-- * +------------------------------+
-- * |
-- * +---------<---------v------------>----------+
-- * | |
-- * +--------v----------------+ |
-- * | dp_phy_pll_link_clk | |
-- * | link_clk | |
-- * +--------+----------------+ |
-- * | |
-- * | |
-- * v v
-- * Input to DISPCC block |
-- * for link clk, crypto clk |
-- * and interface clock |
-- * |
-- * |
-- * +--------<------------+-----------------+---<---+
-- * | | |
-- * +----v---------+ +--------v-----+ +--------v------+
-- * | vco_divided | | vco_divided | | vco_divided |
-- * | _clk_src | | _clk_src | | _clk_src |
-- * | | | | | |
-- * |divsel_six | | divsel_two | | divsel_four |
-- * +-------+------+ +-----+--------+ +--------+------+
-- * | | |
-- * v---->----------v-------------<------v
-- * |
-- * +----------+-----------------+
-- * | dp_phy_pll_vco_div_clk |
-- * +---------+------------------+
-- * |
-- * v
-- * Input to DISPCC block
-- * for DP pixel clock
-- *
-- */
--static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw,
-- struct clk_rate_request *req)
--{
-- switch (req->rate) {
-- case 1620000000UL / 2:
-- case 2700000000UL / 2:
-- /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */
-- return 0;
-- default:
-- return -EINVAL;
-- }
--}
--
--static unsigned long
--qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
--{
-- const struct qmp_phy_dp_clks *dp_clks;
-- const struct qmp_phy *qphy;
-- const struct phy_configure_opts_dp *dp_opts;
--
-- dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw);
-- qphy = dp_clks->qphy;
-- dp_opts = &qphy->dp_opts;
--
-- switch (dp_opts->link_rate) {
-- case 1620:
-- return 1620000000UL / 2;
-- case 2700:
-- return 2700000000UL / 2;
-- case 5400:
-- return 5400000000UL / 4;
-- case 8100:
-- return 8100000000UL / 6;
-- default:
-- return 0;
-- }
--}
--
--static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = {
-- .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate,
-- .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate,
--};
--
--static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw,
-- struct clk_rate_request *req)
--{
-- switch (req->rate) {
-- case 162000000:
-- case 270000000:
-- case 540000000:
-- case 810000000:
-- return 0;
-- default:
-- return -EINVAL;
-- }
--}
--
--static unsigned long
--qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
--{
-- const struct qmp_phy_dp_clks *dp_clks;
-- const struct qmp_phy *qphy;
-- const struct phy_configure_opts_dp *dp_opts;
--
-- dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw);
-- qphy = dp_clks->qphy;
-- dp_opts = &qphy->dp_opts;
--
-- switch (dp_opts->link_rate) {
-- case 1620:
-- case 2700:
-- case 5400:
-- case 8100:
-- return dp_opts->link_rate * 100000;
-- default:
-- return 0;
-- }
--}
--
--static const struct clk_ops qcom_qmp_dp_link_clk_ops = {
-- .determine_rate = qcom_qmp_dp_link_clk_determine_rate,
-- .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate,
--};
--
--static struct clk_hw *
--qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data)
--{
-- struct qmp_phy_dp_clks *dp_clks = data;
-- unsigned int idx = clkspec->args[0];
--
-- if (idx >= 2) {
-- pr_err("%s: invalid index %u\n", __func__, idx);
-- return ERR_PTR(-EINVAL);
-- }
--
-- if (idx == 0)
-- return &dp_clks->dp_link_hw;
--
-- return &dp_clks->dp_pixel_hw;
--}
--
--static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy,
-- struct device_node *np)
--{
-- struct clk_init_data init = { };
-- struct qmp_phy_dp_clks *dp_clks;
-- char name[64];
-- int ret;
--
-- dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL);
-- if (!dp_clks)
-- return -ENOMEM;
--
-- dp_clks->qphy = qphy;
-- qphy->dp_clks = dp_clks;
--
-- snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev));
-- init.ops = &qcom_qmp_dp_link_clk_ops;
-- init.name = name;
-- dp_clks->dp_link_hw.init = &init;
-- ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw);
-- if (ret)
-- return ret;
--
-- snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev));
-- init.ops = &qcom_qmp_dp_pixel_clk_ops;
-- init.name = name;
-- dp_clks->dp_pixel_hw.init = &init;
-- ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw);
-- if (ret)
-- return ret;
--
-- ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks);
-- if (ret)
-- return ret;
--
-- /*
-- * Roll a devm action because the clock provider is the child node, but
-- * the child node is not actually a device.
-- */
-- return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
--}
--
--static const struct phy_ops qcom_qmp_phy_pcie_msm8996_gen_ops = {
-+static const struct phy_ops qcom_qmp_phy_pcie_msm8996_ops = {
- .init = qcom_qmp_phy_pcie_msm8996_enable,
- .exit = qcom_qmp_phy_pcie_msm8996_disable,
- .set_mode = qcom_qmp_phy_pcie_msm8996_set_mode,
- .owner = THIS_MODULE,
- };
-
--static const struct phy_ops qcom_qmp_phy_pcie_msm8996_dp_ops = {
-- .init = qcom_qmp_phy_pcie_msm8996_init,
-- .configure = qcom_qmp_dp_phy_configure,
-- .power_on = qcom_qmp_phy_pcie_msm8996_power_on,
-- .calibrate = qcom_qmp_dp_phy_calibrate,
-- .power_off = qcom_qmp_phy_pcie_msm8996_power_off,
-- .exit = qcom_qmp_phy_pcie_msm8996_exit,
-- .set_mode = qcom_qmp_phy_pcie_msm8996_set_mode,
-- .owner = THIS_MODULE,
--};
--
--static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
-- .power_on = qcom_qmp_phy_pcie_msm8996_enable,
-- .power_off = qcom_qmp_phy_pcie_msm8996_disable,
-- .set_mode = qcom_qmp_phy_pcie_msm8996_set_mode,
-- .owner = THIS_MODULE,
--};
--
- static void qcom_qmp_reset_control_put(void *data)
- {
- reset_control_put(data);
-@@ -1439,7 +1038,6 @@ int qcom_qmp_phy_pcie_msm8996_create(struct device *dev, struct device_node *np,
- struct qcom_qmp *qmp = dev_get_drvdata(dev);
- struct phy *generic_phy;
- struct qmp_phy *qphy;
-- const struct phy_ops *ops;
- char prop_name[MAX_PROP_NAME];
- int ret;
-
-@@ -1532,14 +1130,7 @@ int qcom_qmp_phy_pcie_msm8996_create(struct device *dev, struct device_node *np,
- return ret;
- }
-
-- if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE)
-- ops = &qcom_qmp_pcie_ufs_ops;
-- else if (cfg->type == PHY_TYPE_DP)
-- ops = &qcom_qmp_phy_pcie_msm8996_dp_ops;
-- else
-- ops = &qcom_qmp_phy_pcie_msm8996_gen_ops;
--
-- generic_phy = devm_phy_create(dev, np, ops);
-+ generic_phy = devm_phy_create(dev, np, &qcom_qmp_phy_pcie_msm8996_ops);
- if (IS_ERR(generic_phy)) {
- ret = PTR_ERR(generic_phy);
- dev_err(dev, "failed to create qphy %d\n", ret);
-@@ -1564,11 +1155,6 @@ static const struct of_device_id qcom_qmp_phy_pcie_msm8996_of_match_table[] = {
- };
- MODULE_DEVICE_TABLE(of, qcom_qmp_phy_pcie_msm8996_of_match_table);
-
--static const struct dev_pm_ops qcom_qmp_phy_pcie_msm8996_pm_ops = {
-- SET_RUNTIME_PM_OPS(qcom_qmp_phy_pcie_msm8996_runtime_suspend,
-- qcom_qmp_phy_pcie_msm8996_runtime_resume, NULL)
--};
--
- static int qcom_qmp_phy_pcie_msm8996_probe(struct platform_device *pdev)
- {
- struct qcom_qmp *qmp;
-@@ -1576,12 +1162,7 @@ static int qcom_qmp_phy_pcie_msm8996_probe(struct platform_device *pdev)
- struct device_node *child;
- struct phy_provider *phy_provider;
- void __iomem *serdes;
-- void __iomem *usb_serdes;
-- void __iomem *dp_serdes = NULL;
-- const struct qmp_phy_combo_cfg *combo_cfg = NULL;
- const struct qmp_phy_cfg *cfg = NULL;
-- const struct qmp_phy_cfg *usb_cfg = NULL;
-- const struct qmp_phy_cfg *dp_cfg = NULL;
- int num, id, expected_phys;
- int ret;
-
-@@ -1598,28 +1179,18 @@ static int qcom_qmp_phy_pcie_msm8996_probe(struct platform_device *pdev)
- return -EINVAL;
-
- /* per PHY serdes; usually located at base address */
-- usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0);
-+ serdes = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(serdes))
- return PTR_ERR(serdes);
-
- /* per PHY dp_com; if PHY has dp_com control block */
-- if (combo_cfg || cfg->has_phy_dp_com_ctrl) {
-+ if (cfg->has_phy_dp_com_ctrl) {
- qmp->dp_com = devm_platform_ioremap_resource(pdev, 1);
- if (IS_ERR(qmp->dp_com))
- return PTR_ERR(qmp->dp_com);
- }
-
-- if (combo_cfg) {
-- /* Only two serdes for combo PHY */
-- dp_serdes = devm_platform_ioremap_resource(pdev, 2);
-- if (IS_ERR(dp_serdes))
-- return PTR_ERR(dp_serdes);
--
-- dp_cfg = combo_cfg->dp_cfg;
-- expected_phys = 2;
-- } else {
-- expected_phys = cfg->nlanes;
-- }
-+ expected_phys = cfg->nlanes;
-
- mutex_init(&qmp->phy_mutex);
-
-@@ -1658,14 +1229,6 @@ static int qcom_qmp_phy_pcie_msm8996_probe(struct platform_device *pdev)
-
- id = 0;
- for_each_available_child_of_node(dev->of_node, child) {
-- if (of_node_name_eq(child, "dp-phy")) {
-- cfg = dp_cfg;
-- serdes = dp_serdes;
-- } else if (of_node_name_eq(child, "usb3-phy")) {
-- cfg = usb_cfg;
-- serdes = usb_serdes;
-- }
--
- /* Create per-lane phy */
- ret = qcom_qmp_phy_pcie_msm8996_create(dev, child, id, serdes, cfg);
- if (ret) {
-@@ -1678,21 +1241,13 @@ static int qcom_qmp_phy_pcie_msm8996_probe(struct platform_device *pdev)
- * Register the pipe clock provided by phy.
- * See function description to see details of this pipe clock.
- */
-- if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) {
-- ret = phy_pipe_clk_register(qmp, child);
-- if (ret) {
-- dev_err(qmp->dev,
-- "failed to register pipe clock source\n");
-- goto err_node_put;
-- }
-- } else if (cfg->type == PHY_TYPE_DP) {
-- ret = phy_dp_clks_register(qmp, qmp->phys[id], child);
-- if (ret) {
-- dev_err(qmp->dev,
-- "failed to register DP clock source\n");
-- goto err_node_put;
-- }
-+ ret = phy_pipe_clk_register(qmp, child);
-+ if (ret) {
-+ dev_err(qmp->dev,
-+ "failed to register pipe clock source\n");
-+ goto err_node_put;
- }
-+
- id++;
- }
-
-@@ -1714,7 +1269,6 @@ static struct platform_driver qcom_qmp_phy_pcie_msm8996_driver = {
- .probe = qcom_qmp_phy_pcie_msm8996_probe,
- .driver = {
- .name = "qcom-qmp-msm8996-pcie-phy",
-- .pm = &qcom_qmp_phy_pcie_msm8996_pm_ops,
- .of_match_table = qcom_qmp_phy_pcie_msm8996_of_match_table,
- },
- };
---
-2.35.1
-
+++ /dev/null
-From a521c6e7b712ecf3803d903ccc91dbbc0d26fffa Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Tue, 5 Jul 2022 12:42:56 +0300
-Subject: phy: qcom-qmp-pcie: split pcs_misc region for ipq6018 pcie gen3
-
-From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-
-[ Upstream commit af6643242d3ac9c90674c5ba8dbddb01ffc37f29 ]
-
-Follow the example of other PCIe PHYs and use separate pcs_misc region
-to access PCS_PCIE_* resources.
-
-Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Link: https://lore.kernel.org/r/20220705094320.1313312-5-dmitry.baryshkov@linaro.org
-Signed-off-by: Vinod Koul <vkoul@kernel.org>
-Stable-dep-of: ecd5507e72ea ("phy: qcom-qmp-pcie: add pcs_misc sanity check")
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 9 +++++++
- drivers/phy/qualcomm/phy-qcom-qmp.h | 32 ++++++++++++------------
- 2 files changed, 25 insertions(+), 16 deletions(-)
-
-diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
-index c7309e981bfb..38fd0c5c3797 100644
---- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
-+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
-@@ -735,6 +735,9 @@ static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
- QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
- QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
- QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_misc_tbl[] = {
- QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
- QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
- QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-@@ -3549,6 +3552,8 @@ static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
- .rx_tbl_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
- .pcs_tbl = ipq6018_pcie_pcs_tbl,
- .pcs_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
-+ .pcs_misc_tbl = ipq6018_pcie_pcs_misc_tbl,
-+ .pcs_misc_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_misc_tbl),
- .clk_list = ipq8074_pciephy_clk_l,
- .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
- .reset_list = ipq8074_pciephy_reset_l,
-@@ -5957,6 +5962,10 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
- qphy->pcs_misc = of_iomap(np, 3);
- }
-
-+ if (!qphy->pcs_misc &&
-+ of_device_is_compatible(dev->of_node, "qcom,ipq6018-qmp-pcie-phy"))
-+ qphy->pcs_misc = qphy->pcs + 0x400;
-+
- if (!qphy->pcs_misc)
- dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
-
-diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
-index bebeac2c091c..9f05966cb60d 100644
---- a/drivers/phy/qualcomm/phy-qcom-qmp.h
-+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
-@@ -121,22 +121,22 @@
-
- /* QMP V2 PHY for PCIE gen3 ports - PCS Misc registers */
-
--#define PCS_PCIE_POWER_STATE_CONFIG2 0x40c
--#define PCS_PCIE_POWER_STATE_CONFIG4 0x414
--#define PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x41c
--#define PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x440
--#define PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H 0x444
--#define PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x448
--#define PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H 0x44c
--#define PCS_PCIE_OSC_DTCT_CONFIG2 0x45c
--#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG2 0x478
--#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG4 0x480
--#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x484
--#define PCS_PCIE_OSC_DTCT_ACTIONS 0x490
--#define PCS_PCIE_EQ_CONFIG1 0x4a0
--#define PCS_PCIE_EQ_CONFIG2 0x4a4
--#define PCS_PCIE_PRESET_P10_PRE 0x4bc
--#define PCS_PCIE_PRESET_P10_POST 0x4e0
-+#define PCS_PCIE_POWER_STATE_CONFIG2 0x00c
-+#define PCS_PCIE_POWER_STATE_CONFIG4 0x014
-+#define PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c
-+#define PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x040
-+#define PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H 0x044
-+#define PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x048
-+#define PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H 0x04c
-+#define PCS_PCIE_OSC_DTCT_CONFIG2 0x05c
-+#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG2 0x078
-+#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG4 0x080
-+#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x084
-+#define PCS_PCIE_OSC_DTCT_ACTIONS 0x090
-+#define PCS_PCIE_EQ_CONFIG1 0x0a0
-+#define PCS_PCIE_EQ_CONFIG2 0x0a4
-+#define PCS_PCIE_PRESET_P10_PRE 0x0bc
-+#define PCS_PCIE_PRESET_P10_POST 0x0e0
-
- /* Only for QMP V2 PHY - QSERDES COM registers */
- #define QSERDES_COM_BG_TIMER 0x00c
---
-2.35.1
-
+++ /dev/null
-From 99370fdab6d7d8784fa5e4d5eea748204da5e45f Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Wed, 8 Jun 2022 00:31:44 +0300
-Subject: phy: qcom-qmp-usb: change symbol prefix to qcom_qmp_phy_usb
-
-From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-
-[ Upstream commit 09b492a379402395f646c6db2e16cdac1fc2229d ]
-
-Change all symbol names to start with qcom_qmp_phy_usb_ rather than old
-qcom_qmp_phy_
-
-Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> # UFS, PCIe and USB on SC8180X
-Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Link: https://lore.kernel.org/r/20220607213203.2819885-12-dmitry.baryshkov@linaro.org
-Signed-off-by: Vinod Koul <vkoul@kernel.org>
-Stable-dep-of: a5d6b1ac56cb ("phy: qcom-qmp-usb: fix memleak on probe deferral")
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 158 ++++++++++++------------
- 1 file changed, 79 insertions(+), 79 deletions(-)
-
-diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
-index e147182afea7..2ae13b4485b6 100644
---- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
-+++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
-@@ -2023,7 +2023,7 @@ static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
- .is_dual_lane_phy = true,
- };
-
--static void qcom_qmp_phy_configure_lane(void __iomem *base,
-+static void qcom_qmp_phy_usb_configure_lane(void __iomem *base,
- const unsigned int *regs,
- const struct qmp_phy_init_tbl tbl[],
- int num,
-@@ -2046,15 +2046,15 @@ static void qcom_qmp_phy_configure_lane(void __iomem *base,
- }
- }
-
--static void qcom_qmp_phy_configure(void __iomem *base,
-+static void qcom_qmp_phy_usb_configure(void __iomem *base,
- const unsigned int *regs,
- const struct qmp_phy_init_tbl tbl[],
- int num)
- {
-- qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff);
-+ qcom_qmp_phy_usb_configure_lane(base, regs, tbl, num, 0xff);
- }
-
--static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
-+static int qcom_qmp_phy_usb_serdes_init(struct qmp_phy *qphy)
- {
- struct qcom_qmp *qmp = qphy->qmp;
- const struct qmp_phy_cfg *cfg = qphy->cfg;
-@@ -2064,30 +2064,30 @@ static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
- int serdes_tbl_num = cfg->serdes_tbl_num;
- int ret;
-
-- qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
-+ qcom_qmp_phy_usb_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
- if (cfg->serdes_tbl_sec)
-- qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
-+ qcom_qmp_phy_usb_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
- cfg->serdes_tbl_num_sec);
-
- if (cfg->type == PHY_TYPE_DP) {
- switch (dp_opts->link_rate) {
- case 1620:
-- qcom_qmp_phy_configure(serdes, cfg->regs,
-+ qcom_qmp_phy_usb_configure(serdes, cfg->regs,
- cfg->serdes_tbl_rbr,
- cfg->serdes_tbl_rbr_num);
- break;
- case 2700:
-- qcom_qmp_phy_configure(serdes, cfg->regs,
-+ qcom_qmp_phy_usb_configure(serdes, cfg->regs,
- cfg->serdes_tbl_hbr,
- cfg->serdes_tbl_hbr_num);
- break;
- case 5400:
-- qcom_qmp_phy_configure(serdes, cfg->regs,
-+ qcom_qmp_phy_usb_configure(serdes, cfg->regs,
- cfg->serdes_tbl_hbr2,
- cfg->serdes_tbl_hbr2_num);
- break;
- case 8100:
-- qcom_qmp_phy_configure(serdes, cfg->regs,
-+ qcom_qmp_phy_usb_configure(serdes, cfg->regs,
- cfg->serdes_tbl_hbr3,
- cfg->serdes_tbl_hbr3_num);
- break;
-@@ -2147,7 +2147,7 @@ static int qcom_qmp_dp_phy_calibrate(struct phy *phy)
- return 0;
- }
-
--static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
-+static int qcom_qmp_phy_usb_com_init(struct qmp_phy *qphy)
- {
- struct qcom_qmp *qmp = qphy->qmp;
- const struct qmp_phy_cfg *cfg = qphy->cfg;
-@@ -2242,7 +2242,7 @@ static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
- return ret;
- }
-
--static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy)
-+static int qcom_qmp_phy_usb_com_exit(struct qmp_phy *qphy)
- {
- struct qcom_qmp *qmp = qphy->qmp;
- const struct qmp_phy_cfg *cfg = qphy->cfg;
-@@ -2277,7 +2277,7 @@ static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy)
- return 0;
- }
-
--static int qcom_qmp_phy_init(struct phy *phy)
-+static int qcom_qmp_phy_usb_init(struct phy *phy)
- {
- struct qmp_phy *qphy = phy_get_drvdata(phy);
- struct qcom_qmp *qmp = qphy->qmp;
-@@ -2312,7 +2312,7 @@ static int qcom_qmp_phy_init(struct phy *phy)
- return ret;
- }
-
-- ret = qcom_qmp_phy_com_init(qphy);
-+ ret = qcom_qmp_phy_usb_com_init(qphy);
- if (ret)
- return ret;
-
-@@ -2322,7 +2322,7 @@ static int qcom_qmp_phy_init(struct phy *phy)
- return 0;
- }
-
--static int qcom_qmp_phy_power_on(struct phy *phy)
-+static int qcom_qmp_phy_usb_power_on(struct phy *phy)
- {
- struct qmp_phy *qphy = phy_get_drvdata(phy);
- struct qcom_qmp *qmp = qphy->qmp;
-@@ -2335,7 +2335,7 @@ static int qcom_qmp_phy_power_on(struct phy *phy)
- unsigned int mask, val, ready;
- int ret;
-
-- qcom_qmp_phy_serdes_init(qphy);
-+ qcom_qmp_phy_usb_serdes_init(qphy);
-
- if (cfg->has_lane_rst) {
- ret = reset_control_deassert(qphy->lane_rst);
-@@ -2353,18 +2353,18 @@ static int qcom_qmp_phy_power_on(struct phy *phy)
- }
-
- /* Tx, Rx, and PCS configurations */
-- qcom_qmp_phy_configure_lane(tx, cfg->regs,
-+ qcom_qmp_phy_usb_configure_lane(tx, cfg->regs,
- cfg->tx_tbl, cfg->tx_tbl_num, 1);
- if (cfg->tx_tbl_sec)
-- qcom_qmp_phy_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
-+ qcom_qmp_phy_usb_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
- cfg->tx_tbl_num_sec, 1);
-
- /* Configuration for other LANE for USB-DP combo PHY */
- if (cfg->is_dual_lane_phy) {
-- qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
-+ qcom_qmp_phy_usb_configure_lane(qphy->tx2, cfg->regs,
- cfg->tx_tbl, cfg->tx_tbl_num, 2);
- if (cfg->tx_tbl_sec)
-- qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
-+ qcom_qmp_phy_usb_configure_lane(qphy->tx2, cfg->regs,
- cfg->tx_tbl_sec,
- cfg->tx_tbl_num_sec, 2);
- }
-@@ -2373,17 +2373,17 @@ static int qcom_qmp_phy_power_on(struct phy *phy)
- if (cfg->type == PHY_TYPE_DP)
- cfg->configure_dp_tx(qphy);
-
-- qcom_qmp_phy_configure_lane(rx, cfg->regs,
-+ qcom_qmp_phy_usb_configure_lane(rx, cfg->regs,
- cfg->rx_tbl, cfg->rx_tbl_num, 1);
- if (cfg->rx_tbl_sec)
-- qcom_qmp_phy_configure_lane(rx, cfg->regs,
-+ qcom_qmp_phy_usb_configure_lane(rx, cfg->regs,
- cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1);
-
- if (cfg->is_dual_lane_phy) {
-- qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
-+ qcom_qmp_phy_usb_configure_lane(qphy->rx2, cfg->regs,
- cfg->rx_tbl, cfg->rx_tbl_num, 2);
- if (cfg->rx_tbl_sec)
-- qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
-+ qcom_qmp_phy_usb_configure_lane(qphy->rx2, cfg->regs,
- cfg->rx_tbl_sec,
- cfg->rx_tbl_num_sec, 2);
- }
-@@ -2392,9 +2392,9 @@ static int qcom_qmp_phy_power_on(struct phy *phy)
- if (cfg->type == PHY_TYPE_DP) {
- cfg->configure_dp_phy(qphy);
- } else {
-- qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
-+ qcom_qmp_phy_usb_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
- if (cfg->pcs_tbl_sec)
-- qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
-+ qcom_qmp_phy_usb_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
- cfg->pcs_tbl_num_sec);
- }
-
-@@ -2402,10 +2402,10 @@ static int qcom_qmp_phy_power_on(struct phy *phy)
- if (ret)
- goto err_disable_pipe_clk;
-
-- qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
-+ qcom_qmp_phy_usb_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
- cfg->pcs_misc_tbl_num);
- if (cfg->pcs_misc_tbl_sec)
-- qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
-+ qcom_qmp_phy_usb_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
- cfg->pcs_misc_tbl_num_sec);
-
- /*
-@@ -2453,7 +2453,7 @@ static int qcom_qmp_phy_power_on(struct phy *phy)
- return ret;
- }
-
--static int qcom_qmp_phy_power_off(struct phy *phy)
-+static int qcom_qmp_phy_usb_power_off(struct phy *phy)
- {
- struct qmp_phy *qphy = phy_get_drvdata(phy);
- const struct qmp_phy_cfg *cfg = qphy->cfg;
-@@ -2484,7 +2484,7 @@ static int qcom_qmp_phy_power_off(struct phy *phy)
- return 0;
- }
-
--static int qcom_qmp_phy_exit(struct phy *phy)
-+static int qcom_qmp_phy_usb_exit(struct phy *phy)
- {
- struct qmp_phy *qphy = phy_get_drvdata(phy);
- const struct qmp_phy_cfg *cfg = qphy->cfg;
-@@ -2492,37 +2492,37 @@ static int qcom_qmp_phy_exit(struct phy *phy)
- if (cfg->has_lane_rst)
- reset_control_assert(qphy->lane_rst);
-
-- qcom_qmp_phy_com_exit(qphy);
-+ qcom_qmp_phy_usb_com_exit(qphy);
-
- return 0;
- }
-
--static int qcom_qmp_phy_enable(struct phy *phy)
-+static int qcom_qmp_phy_usb_enable(struct phy *phy)
- {
- int ret;
-
-- ret = qcom_qmp_phy_init(phy);
-+ ret = qcom_qmp_phy_usb_init(phy);
- if (ret)
- return ret;
-
-- ret = qcom_qmp_phy_power_on(phy);
-+ ret = qcom_qmp_phy_usb_power_on(phy);
- if (ret)
-- qcom_qmp_phy_exit(phy);
-+ qcom_qmp_phy_usb_exit(phy);
-
- return ret;
- }
-
--static int qcom_qmp_phy_disable(struct phy *phy)
-+static int qcom_qmp_phy_usb_disable(struct phy *phy)
- {
- int ret;
-
-- ret = qcom_qmp_phy_power_off(phy);
-+ ret = qcom_qmp_phy_usb_power_off(phy);
- if (ret)
- return ret;
-- return qcom_qmp_phy_exit(phy);
-+ return qcom_qmp_phy_usb_exit(phy);
- }
-
--static int qcom_qmp_phy_set_mode(struct phy *phy,
-+static int qcom_qmp_phy_usb_set_mode(struct phy *phy,
- enum phy_mode mode, int submode)
- {
- struct qmp_phy *qphy = phy_get_drvdata(phy);
-@@ -2532,7 +2532,7 @@ static int qcom_qmp_phy_set_mode(struct phy *phy,
- return 0;
- }
-
--static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
-+static void qcom_qmp_phy_usb_enable_autonomous_mode(struct qmp_phy *qphy)
- {
- const struct qmp_phy_cfg *cfg = qphy->cfg;
- void __iomem *pcs = qphy->pcs;
-@@ -2561,7 +2561,7 @@ static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
- qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
- }
-
--static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
-+static void qcom_qmp_phy_usb_disable_autonomous_mode(struct qmp_phy *qphy)
- {
- const struct qmp_phy_cfg *cfg = qphy->cfg;
- void __iomem *pcs = qphy->pcs;
-@@ -2579,7 +2579,7 @@ static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
- qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
- }
-
--static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
-+static int __maybe_unused qcom_qmp_phy_usb_runtime_suspend(struct device *dev)
- {
- struct qcom_qmp *qmp = dev_get_drvdata(dev);
- struct qmp_phy *qphy = qmp->phys[0];
-@@ -2596,7 +2596,7 @@ static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
- return 0;
- }
-
-- qcom_qmp_phy_enable_autonomous_mode(qphy);
-+ qcom_qmp_phy_usb_enable_autonomous_mode(qphy);
-
- clk_disable_unprepare(qphy->pipe_clk);
- clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
-@@ -2604,7 +2604,7 @@ static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
- return 0;
- }
-
--static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
-+static int __maybe_unused qcom_qmp_phy_usb_runtime_resume(struct device *dev)
- {
- struct qcom_qmp *qmp = dev_get_drvdata(dev);
- struct qmp_phy *qphy = qmp->phys[0];
-@@ -2633,12 +2633,12 @@ static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
- return ret;
- }
-
-- qcom_qmp_phy_disable_autonomous_mode(qphy);
-+ qcom_qmp_phy_usb_disable_autonomous_mode(qphy);
-
- return 0;
- }
-
--static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
-+static int qcom_qmp_phy_usb_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
- {
- struct qcom_qmp *qmp = dev_get_drvdata(dev);
- int num = cfg->num_vregs;
-@@ -2654,7 +2654,7 @@ static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *
- return devm_regulator_bulk_get(dev, num, qmp->vregs);
- }
-
--static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
-+static int qcom_qmp_phy_usb_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
- {
- struct qcom_qmp *qmp = dev_get_drvdata(dev);
- int i;
-@@ -2679,7 +2679,7 @@ static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg
- return 0;
- }
-
--static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
-+static int qcom_qmp_phy_usb_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
- {
- struct qcom_qmp *qmp = dev_get_drvdata(dev);
- int num = cfg->num_clks;
-@@ -2947,28 +2947,28 @@ static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy,
- return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
- }
-
--static const struct phy_ops qcom_qmp_phy_gen_ops = {
-- .init = qcom_qmp_phy_enable,
-- .exit = qcom_qmp_phy_disable,
-- .set_mode = qcom_qmp_phy_set_mode,
-+static const struct phy_ops qcom_qmp_phy_usb_gen_ops = {
-+ .init = qcom_qmp_phy_usb_enable,
-+ .exit = qcom_qmp_phy_usb_disable,
-+ .set_mode = qcom_qmp_phy_usb_set_mode,
- .owner = THIS_MODULE,
- };
-
--static const struct phy_ops qcom_qmp_phy_dp_ops = {
-- .init = qcom_qmp_phy_init,
-+static const struct phy_ops qcom_qmp_phy_usb_dp_ops = {
-+ .init = qcom_qmp_phy_usb_init,
- .configure = qcom_qmp_dp_phy_configure,
-- .power_on = qcom_qmp_phy_power_on,
-+ .power_on = qcom_qmp_phy_usb_power_on,
- .calibrate = qcom_qmp_dp_phy_calibrate,
-- .power_off = qcom_qmp_phy_power_off,
-- .exit = qcom_qmp_phy_exit,
-- .set_mode = qcom_qmp_phy_set_mode,
-+ .power_off = qcom_qmp_phy_usb_power_off,
-+ .exit = qcom_qmp_phy_usb_exit,
-+ .set_mode = qcom_qmp_phy_usb_set_mode,
- .owner = THIS_MODULE,
- };
-
- static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
-- .power_on = qcom_qmp_phy_enable,
-- .power_off = qcom_qmp_phy_disable,
-- .set_mode = qcom_qmp_phy_set_mode,
-+ .power_on = qcom_qmp_phy_usb_enable,
-+ .power_off = qcom_qmp_phy_usb_disable,
-+ .set_mode = qcom_qmp_phy_usb_set_mode,
- .owner = THIS_MODULE,
- };
-
-@@ -2978,7 +2978,7 @@ static void qcom_qmp_reset_control_put(void *data)
- }
-
- static
--int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
-+int qcom_qmp_phy_usb_create(struct device *dev, struct device_node *np, int id,
- void __iomem *serdes, const struct qmp_phy_cfg *cfg)
- {
- struct qcom_qmp *qmp = dev_get_drvdata(dev);
-@@ -3080,9 +3080,9 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
- if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE)
- ops = &qcom_qmp_pcie_ufs_ops;
- else if (cfg->type == PHY_TYPE_DP)
-- ops = &qcom_qmp_phy_dp_ops;
-+ ops = &qcom_qmp_phy_usb_dp_ops;
- else
-- ops = &qcom_qmp_phy_gen_ops;
-+ ops = &qcom_qmp_phy_usb_gen_ops;
-
- generic_phy = devm_phy_create(dev, np, ops);
- if (IS_ERR(generic_phy)) {
-@@ -3100,7 +3100,7 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
- return 0;
- }
-
--static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
-+static const struct of_device_id qcom_qmp_phy_usb_of_match_table[] = {
- {
- .compatible = "qcom,ipq8074-qmp-usb3-phy",
- .data = &ipq8074_usb3phy_cfg,
-@@ -3158,14 +3158,14 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
- },
- { },
- };
--MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
-+MODULE_DEVICE_TABLE(of, qcom_qmp_phy_usb_of_match_table);
-
--static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
-- SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
-- qcom_qmp_phy_runtime_resume, NULL)
-+static const struct dev_pm_ops qcom_qmp_phy_usb_pm_ops = {
-+ SET_RUNTIME_PM_OPS(qcom_qmp_phy_usb_runtime_suspend,
-+ qcom_qmp_phy_usb_runtime_resume, NULL)
- };
-
--static int qcom_qmp_phy_probe(struct platform_device *pdev)
-+static int qcom_qmp_phy_usb_probe(struct platform_device *pdev)
- {
- struct qcom_qmp *qmp;
- struct device *dev = &pdev->dev;
-@@ -3219,15 +3219,15 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
-
- mutex_init(&qmp->phy_mutex);
-
-- ret = qcom_qmp_phy_clk_init(dev, cfg);
-+ ret = qcom_qmp_phy_usb_clk_init(dev, cfg);
- if (ret)
- return ret;
-
-- ret = qcom_qmp_phy_reset_init(dev, cfg);
-+ ret = qcom_qmp_phy_usb_reset_init(dev, cfg);
- if (ret)
- return ret;
-
-- ret = qcom_qmp_phy_vreg_init(dev, cfg);
-+ ret = qcom_qmp_phy_usb_vreg_init(dev, cfg);
- if (ret) {
- if (ret != -EPROBE_DEFER)
- dev_err(dev, "failed to get regulator supplies: %d\n",
-@@ -3265,7 +3265,7 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
- }
-
- /* Create per-lane phy */
-- ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg);
-+ ret = qcom_qmp_phy_usb_create(dev, child, id, serdes, cfg);
- if (ret) {
- dev_err(dev, "failed to create lane%d phy, %d\n",
- id, ret);
-@@ -3305,16 +3305,16 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
- return ret;
- }
-
--static struct platform_driver qcom_qmp_phy_driver = {
-- .probe = qcom_qmp_phy_probe,
-+static struct platform_driver qcom_qmp_phy_usb_driver = {
-+ .probe = qcom_qmp_phy_usb_probe,
- .driver = {
- .name = "qcom-qmp-usb-phy",
-- .pm = &qcom_qmp_phy_pm_ops,
-- .of_match_table = qcom_qmp_phy_of_match_table,
-+ .pm = &qcom_qmp_phy_usb_pm_ops,
-+ .of_match_table = qcom_qmp_phy_usb_of_match_table,
- },
- };
-
--module_platform_driver(qcom_qmp_phy_driver);
-+module_platform_driver(qcom_qmp_phy_usb_driver);
-
- MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
- MODULE_DESCRIPTION("Qualcomm QMP USB PHY driver");
---
-2.35.1
-
+++ /dev/null
-From f7e0a5e72ca54215471d23384650e3ce19b4a70d Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Thu, 23 Jun 2022 13:33:14 +0200
-Subject: phy: qcom-qmp-usb: clean up pipe clock handling
-
-From: Johan Hovold <johan+linaro@kernel.org>
-
-[ Upstream commit 5d5b7d509ff85675779caeafcffa8086d7094339 ]
-
-Clean up the pipe clock handling by using dev_err_probe() to handle
-probe deferral and dropping the obsolete comment that claimed that the
-pipe clock was optional for some other PHY types.
-
-Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
-Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Link: https://lore.kernel.org/r/20220623113314.29761-4-johan+linaro@kernel.org
-Signed-off-by: Vinod Koul <vkoul@kernel.org>
-Stable-dep-of: a5d6b1ac56cb ("phy: qcom-qmp-usb: fix memleak on probe deferral")
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 15 ++-------------
- 1 file changed, 2 insertions(+), 13 deletions(-)
-
-diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
-index 9e752fce638d..687f1a534837 100644
---- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
-+++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
-@@ -2566,22 +2566,11 @@ int qcom_qmp_phy_usb_create(struct device *dev, struct device_node *np, int id,
- if (!qphy->pcs_misc)
- dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
-
-- /*
-- * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3
-- * based phys, so they essentially have pipe clock. So,
-- * we return error in case phy is USB3 or PIPE type.
-- * Otherwise, we initialize pipe clock to NULL for
-- * all phys that don't need this.
-- */
- snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
- qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name);
- if (IS_ERR(qphy->pipe_clk)) {
-- ret = PTR_ERR(qphy->pipe_clk);
-- if (ret != -EPROBE_DEFER)
-- dev_err(dev,
-- "failed to get lane%d pipe_clk, %d\n",
-- id, ret);
-- return ret;
-+ return dev_err_probe(dev, PTR_ERR(qphy->pipe_clk),
-+ "failed to get lane%d pipe clock\n", id);
- }
-
- generic_phy = devm_phy_create(dev, np, &qcom_qmp_phy_usb_ops);
---
-2.35.1
-
+++ /dev/null
-From 00b19fe255215980b0b97d8d64bde9c4b82e870f Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Wed, 8 Jun 2022 00:31:56 +0300
-Subject: phy: qcom-qmp-usb: cleanup the driver
-
-From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-
-[ Upstream commit faf83af5d59498509eb84015453073fd5e85231e ]
-
-Remove the conditionals and options that are not used by any of USB PHY
-devices.
-
-Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> # UFS, PCIe and USB on SC8180X
-Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Link: https://lore.kernel.org/r/20220607213203.2819885-24-dmitry.baryshkov@linaro.org
-Signed-off-by: Vinod Koul <vkoul@kernel.org>
-Stable-dep-of: a5d6b1ac56cb ("phy: qcom-qmp-usb: fix memleak on probe deferral")
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 214 ++----------------------
- 1 file changed, 11 insertions(+), 203 deletions(-)
-
-diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
-index 55785dcd47e0..9e752fce638d 100644
---- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
-+++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
-@@ -1359,40 +1359,12 @@ struct qmp_phy_cfg {
- /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
- const struct qmp_phy_init_tbl *serdes_tbl;
- int serdes_tbl_num;
-- const struct qmp_phy_init_tbl *serdes_tbl_sec;
-- int serdes_tbl_num_sec;
- const struct qmp_phy_init_tbl *tx_tbl;
- int tx_tbl_num;
-- const struct qmp_phy_init_tbl *tx_tbl_sec;
-- int tx_tbl_num_sec;
- const struct qmp_phy_init_tbl *rx_tbl;
- int rx_tbl_num;
-- const struct qmp_phy_init_tbl *rx_tbl_sec;
-- int rx_tbl_num_sec;
- const struct qmp_phy_init_tbl *pcs_tbl;
- int pcs_tbl_num;
-- const struct qmp_phy_init_tbl *pcs_tbl_sec;
-- int pcs_tbl_num_sec;
-- const struct qmp_phy_init_tbl *pcs_misc_tbl;
-- int pcs_misc_tbl_num;
-- const struct qmp_phy_init_tbl *pcs_misc_tbl_sec;
-- int pcs_misc_tbl_num_sec;
--
-- /* Init sequence for DP PHY block link rates */
-- const struct qmp_phy_init_tbl *serdes_tbl_rbr;
-- int serdes_tbl_rbr_num;
-- const struct qmp_phy_init_tbl *serdes_tbl_hbr;
-- int serdes_tbl_hbr_num;
-- const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
-- int serdes_tbl_hbr2_num;
-- const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
-- int serdes_tbl_hbr3_num;
--
-- /* DP PHY callbacks */
-- int (*configure_dp_phy)(struct qmp_phy *qphy);
-- void (*configure_dp_tx)(struct qmp_phy *qphy);
-- int (*calibrate_dp_phy)(struct qmp_phy *qphy);
-- void (*dp_aux_init)(struct qmp_phy *qphy);
-
- /* clock ids to be requested */
- const char * const *clk_list;
-@@ -1409,14 +1381,9 @@ struct qmp_phy_cfg {
-
- unsigned int start_ctrl;
- unsigned int pwrdn_ctrl;
-- unsigned int mask_com_pcs_ready;
- /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
- unsigned int phy_status;
-
-- /* true, if PHY has a separate PHY_COM control block */
-- bool has_phy_com_ctrl;
-- /* true, if PHY has a reset for individual lanes */
-- bool has_lane_rst;
- /* true, if PHY needs delay after POWER_DOWN */
- bool has_pwrdn_delay;
- /* power_down delay in usec */
-@@ -1427,14 +1394,6 @@ struct qmp_phy_cfg {
- bool has_phy_dp_com_ctrl;
- /* true, if PHY has secondary tx/rx lanes to be configured */
- bool is_dual_lane_phy;
--
-- /* true, if PCS block has no separate SW_RESET register */
-- bool no_pcs_sw_reset;
--};
--
--struct qmp_phy_combo_cfg {
-- const struct qmp_phy_cfg *usb_cfg;
-- const struct qmp_phy_cfg *dp_cfg;
- };
-
- /**
-@@ -1452,11 +1411,7 @@ struct qmp_phy_combo_cfg {
- * @pipe_clk: pipe clock
- * @index: lane index
- * @qmp: QMP phy to which this lane belongs
-- * @lane_rst: lane's reset controller
- * @mode: current PHY mode
-- * @dp_aux_cfg: Display port aux config
-- * @dp_opts: Display port optional config
-- * @dp_clks: Display port clocks
- */
- struct qmp_phy {
- struct phy *phy;
-@@ -1471,17 +1426,7 @@ struct qmp_phy {
- struct clk *pipe_clk;
- unsigned int index;
- struct qcom_qmp *qmp;
-- struct reset_control *lane_rst;
- enum phy_mode mode;
-- unsigned int dp_aux_cfg;
-- struct phy_configure_opts_dp dp_opts;
-- struct qmp_phy_dp_clks *dp_clks;
--};
--
--struct qmp_phy_dp_clks {
-- struct qmp_phy *qphy;
-- struct clk_hw dp_link_hw;
-- struct clk_hw dp_pixel_hw;
- };
-
- /**
-@@ -1497,7 +1442,6 @@ struct qmp_phy_dp_clks {
- * @phys: array of per-lane phy descriptors
- * @phy_mutex: mutex lock for PHY common block initialization
- * @init_count: phy common block initialization count
-- * @ufs_reset: optional UFS PHY reset handle
- */
- struct qcom_qmp {
- struct device *dev;
-@@ -1511,8 +1455,6 @@ struct qcom_qmp {
-
- struct mutex phy_mutex;
- int init_count;
--
-- struct reset_control *ufs_reset;
- };
-
- static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
-@@ -2056,37 +1998,12 @@ static void qcom_qmp_phy_usb_configure(void __iomem *base,
-
- static int qcom_qmp_phy_usb_serdes_init(struct qmp_phy *qphy)
- {
-- struct qcom_qmp *qmp = qphy->qmp;
- const struct qmp_phy_cfg *cfg = qphy->cfg;
- void __iomem *serdes = qphy->serdes;
- const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
- int serdes_tbl_num = cfg->serdes_tbl_num;
-- int ret;
-
- qcom_qmp_phy_usb_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
-- if (cfg->serdes_tbl_sec)
-- qcom_qmp_phy_usb_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
-- cfg->serdes_tbl_num_sec);
--
-- if (cfg->has_phy_com_ctrl) {
-- void __iomem *status;
-- unsigned int mask, val;
--
-- qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
-- qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
-- SERDES_START | PCS_START);
--
-- status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
-- mask = cfg->mask_com_pcs_ready;
--
-- ret = readl_poll_timeout(status, val, (val & mask), 10,
-- PHY_INIT_COMPLETE_TIMEOUT);
-- if (ret) {
-- dev_err(qmp->dev,
-- "phy common block init timed-out\n");
-- return ret;
-- }
-- }
-
- return 0;
- }
-@@ -2095,7 +2012,6 @@ static int qcom_qmp_phy_usb_com_init(struct qmp_phy *qphy)
- {
- struct qcom_qmp *qmp = qphy->qmp;
- const struct qmp_phy_cfg *cfg = qphy->cfg;
-- void __iomem *serdes = qphy->serdes;
- void __iomem *pcs = qphy->pcs;
- void __iomem *dp_com = qmp->dp_com;
- int ret, i;
-@@ -2158,18 +2074,13 @@ static int qcom_qmp_phy_usb_com_init(struct qmp_phy *qphy)
- qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
- }
-
-- if (cfg->has_phy_com_ctrl) {
-- qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
-- SW_PWRDN);
-- } else {
-- if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
-- qphy_setbits(pcs,
-- cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
-- cfg->pwrdn_ctrl);
-- else
-- qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
-- cfg->pwrdn_ctrl);
-- }
-+ if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
-+ qphy_setbits(pcs,
-+ cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
-+ cfg->pwrdn_ctrl);
-+ else
-+ qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
-+ cfg->pwrdn_ctrl);
-
- mutex_unlock(&qmp->phy_mutex);
-
-@@ -2190,7 +2101,6 @@ static int qcom_qmp_phy_usb_com_exit(struct qmp_phy *qphy)
- {
- struct qcom_qmp *qmp = qphy->qmp;
- const struct qmp_phy_cfg *cfg = qphy->cfg;
-- void __iomem *serdes = qphy->serdes;
- int i = cfg->num_resets;
-
- mutex_lock(&qmp->phy_mutex);
-@@ -2199,16 +2109,6 @@ static int qcom_qmp_phy_usb_com_exit(struct qmp_phy *qphy)
- return 0;
- }
-
-- reset_control_assert(qmp->ufs_reset);
-- if (cfg->has_phy_com_ctrl) {
-- qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
-- SERDES_START | PCS_START);
-- qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
-- SW_RESET);
-- qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
-- SW_PWRDN);
-- }
--
- while (--i >= 0)
- reset_control_assert(qmp->resets[i]);
-
-@@ -2225,37 +2125,9 @@ static int qcom_qmp_phy_usb_init(struct phy *phy)
- {
- struct qmp_phy *qphy = phy_get_drvdata(phy);
- struct qcom_qmp *qmp = qphy->qmp;
-- const struct qmp_phy_cfg *cfg = qphy->cfg;
- int ret;
- dev_vdbg(qmp->dev, "Initializing QMP phy\n");
-
-- if (cfg->no_pcs_sw_reset) {
-- /*
-- * Get UFS reset, which is delayed until now to avoid a
-- * circular dependency where UFS needs its PHY, but the PHY
-- * needs this UFS reset.
-- */
-- if (!qmp->ufs_reset) {
-- qmp->ufs_reset =
-- devm_reset_control_get_exclusive(qmp->dev,
-- "ufsphy");
--
-- if (IS_ERR(qmp->ufs_reset)) {
-- ret = PTR_ERR(qmp->ufs_reset);
-- dev_err(qmp->dev,
-- "failed to get UFS reset: %d\n",
-- ret);
--
-- qmp->ufs_reset = NULL;
-- return ret;
-- }
-- }
--
-- ret = reset_control_assert(qmp->ufs_reset);
-- if (ret)
-- return ret;
-- }
--
- ret = qcom_qmp_phy_usb_com_init(qphy);
- if (ret)
- return ret;
-@@ -2271,82 +2143,45 @@ static int qcom_qmp_phy_usb_power_on(struct phy *phy)
- void __iomem *tx = qphy->tx;
- void __iomem *rx = qphy->rx;
- void __iomem *pcs = qphy->pcs;
-- void __iomem *pcs_misc = qphy->pcs_misc;
- void __iomem *status;
- unsigned int mask, val, ready;
- int ret;
-
- qcom_qmp_phy_usb_serdes_init(qphy);
-
-- if (cfg->has_lane_rst) {
-- ret = reset_control_deassert(qphy->lane_rst);
-- if (ret) {
-- dev_err(qmp->dev, "lane%d reset deassert failed\n",
-- qphy->index);
-- return ret;
-- }
-- }
--
- ret = clk_prepare_enable(qphy->pipe_clk);
- if (ret) {
- dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
-- goto err_reset_lane;
-+ return ret;
- }
-
- /* Tx, Rx, and PCS configurations */
- qcom_qmp_phy_usb_configure_lane(tx, cfg->regs,
- cfg->tx_tbl, cfg->tx_tbl_num, 1);
-- if (cfg->tx_tbl_sec)
-- qcom_qmp_phy_usb_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
-- cfg->tx_tbl_num_sec, 1);
-
- /* Configuration for other LANE for USB-DP combo PHY */
- if (cfg->is_dual_lane_phy) {
- qcom_qmp_phy_usb_configure_lane(qphy->tx2, cfg->regs,
- cfg->tx_tbl, cfg->tx_tbl_num, 2);
-- if (cfg->tx_tbl_sec)
-- qcom_qmp_phy_usb_configure_lane(qphy->tx2, cfg->regs,
-- cfg->tx_tbl_sec,
-- cfg->tx_tbl_num_sec, 2);
- }
-
- qcom_qmp_phy_usb_configure_lane(rx, cfg->regs,
- cfg->rx_tbl, cfg->rx_tbl_num, 1);
-- if (cfg->rx_tbl_sec)
-- qcom_qmp_phy_usb_configure_lane(rx, cfg->regs,
-- cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1);
-
- if (cfg->is_dual_lane_phy) {
- qcom_qmp_phy_usb_configure_lane(qphy->rx2, cfg->regs,
- cfg->rx_tbl, cfg->rx_tbl_num, 2);
-- if (cfg->rx_tbl_sec)
-- qcom_qmp_phy_usb_configure_lane(qphy->rx2, cfg->regs,
-- cfg->rx_tbl_sec,
-- cfg->rx_tbl_num_sec, 2);
- }
-
- /* Configure link rate, swing, etc. */
- qcom_qmp_phy_usb_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
-- if (cfg->pcs_tbl_sec)
-- qcom_qmp_phy_usb_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
-- cfg->pcs_tbl_num_sec);
--
-- ret = reset_control_deassert(qmp->ufs_reset);
-- if (ret)
-- goto err_disable_pipe_clk;
--
-- qcom_qmp_phy_usb_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
-- cfg->pcs_misc_tbl_num);
-- if (cfg->pcs_misc_tbl_sec)
-- qcom_qmp_phy_usb_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
-- cfg->pcs_misc_tbl_num_sec);
-
- if (cfg->has_pwrdn_delay)
- usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
-
- /* Pull PHY out of reset state */
-- if (!cfg->no_pcs_sw_reset)
-- qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
-+ qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
-+
- /* start SerDes and Phy-Coding-Sublayer */
- qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
-
-@@ -2365,9 +2200,6 @@ static int qcom_qmp_phy_usb_power_on(struct phy *phy)
-
- err_disable_pipe_clk:
- clk_disable_unprepare(qphy->pipe_clk);
--err_reset_lane:
-- if (cfg->has_lane_rst)
-- reset_control_assert(qphy->lane_rst);
-
- return ret;
- }
-@@ -2380,8 +2212,7 @@ static int qcom_qmp_phy_usb_power_off(struct phy *phy)
- clk_disable_unprepare(qphy->pipe_clk);
-
- /* PHY reset */
-- if (!cfg->no_pcs_sw_reset)
-- qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
-+ qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
-
- /* stop SerDes and Phy-Coding-Sublayer */
- qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
-@@ -2401,10 +2232,6 @@ static int qcom_qmp_phy_usb_power_off(struct phy *phy)
- static int qcom_qmp_phy_usb_exit(struct phy *phy)
- {
- struct qmp_phy *qphy = phy_get_drvdata(phy);
-- const struct qmp_phy_cfg *cfg = qphy->cfg;
--
-- if (cfg->has_lane_rst)
-- reset_control_assert(qphy->lane_rst);
-
- qcom_qmp_phy_usb_com_exit(qphy);
-
-@@ -2676,11 +2503,6 @@ static const struct phy_ops qcom_qmp_phy_usb_ops = {
- .owner = THIS_MODULE,
- };
-
--static void qcom_qmp_reset_control_put(void *data)
--{
-- reset_control_put(data);
--}
--
- static
- int qcom_qmp_phy_usb_create(struct device *dev, struct device_node *np, int id,
- void __iomem *serdes, const struct qmp_phy_cfg *cfg)
-@@ -2762,20 +2584,6 @@ int qcom_qmp_phy_usb_create(struct device *dev, struct device_node *np, int id,
- return ret;
- }
-
-- /* Get lane reset, if any */
-- if (cfg->has_lane_rst) {
-- snprintf(prop_name, sizeof(prop_name), "lane%d", id);
-- qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name);
-- if (IS_ERR(qphy->lane_rst)) {
-- dev_err(dev, "failed to get lane%d reset\n", id);
-- return PTR_ERR(qphy->lane_rst);
-- }
-- ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put,
-- qphy->lane_rst);
-- if (ret)
-- return ret;
-- }
--
- generic_phy = devm_phy_create(dev, np, &qcom_qmp_phy_usb_ops);
- if (IS_ERR(generic_phy)) {
- ret = PTR_ERR(generic_phy);
---
-2.35.1
-
+++ /dev/null
-From 7b9b153c67dfed5063ad8ba797b28c742aa05aca Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Wed, 7 Sep 2022 13:07:21 +0200
-Subject: phy: qcom-qmp-usb: disable runtime PM on unbind
-
-From: Johan Hovold <johan+linaro@kernel.org>
-
-[ Upstream commit e57655e66806750785f9121c98a962404d02395b ]
-
-Make sure to disable runtime PM also on driver unbind.
-
-Fixes: ac0d239936bd ("phy: qcom-qmp: Add support for runtime PM").
-Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
-Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Link: https://lore.kernel.org/r/20220907110728.19092-10-johan+linaro@kernel.org
-Signed-off-by: Vinod Koul <vkoul@kernel.org>
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 7 +++----
- 1 file changed, 3 insertions(+), 4 deletions(-)
-
-diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
-index c7309e981bfb..dcf8a8764e17 100644
---- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
-+++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
-@@ -6273,7 +6273,9 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
- return -ENOMEM;
-
- pm_runtime_set_active(dev);
-- pm_runtime_enable(dev);
-+ ret = devm_pm_runtime_enable(dev);
-+ if (ret)
-+ return ret;
- /*
- * Prevent runtime pm from being ON by default. Users can enable
- * it using power/control in sysfs.
-@@ -6323,13 +6325,10 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
- phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
- if (!IS_ERR(phy_provider))
- dev_info(dev, "Registered Qcom-QMP phy\n");
-- else
-- pm_runtime_disable(dev);
-
- return PTR_ERR_OR_ZERO(phy_provider);
-
- err_node_put:
-- pm_runtime_disable(dev);
- of_node_put(child);
- return ret;
- }
---
-2.35.1
-
+++ /dev/null
-From fc6a1be1ee217d1ec1f986400c741ce00bcd87d3 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Wed, 8 Jun 2022 00:31:38 +0300
-Subject: phy: qcom-qmp-usb: drop all non-USB compatibles support
-
-From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-
-[ Upstream commit 8c924330ebe3e5c6f41bad0e5118875848843864 ]
-
-Drop support for all non-USB compatibles from the new qmp-usb driver.
-
-Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> # UFS, PCIe and USB on SC8180X
-Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Link: https://lore.kernel.org/r/20220607213203.2819885-6-dmitry.baryshkov@linaro.org
-Signed-off-by: Vinod Koul <vkoul@kernel.org>
-Stable-dep-of: a5d6b1ac56cb ("phy: qcom-qmp-usb: fix memleak on probe deferral")
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 3108 +----------------------
- 1 file changed, 40 insertions(+), 3068 deletions(-)
-
-diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
-index dcf8a8764e17..e147182afea7 100644
---- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
-+++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
-@@ -141,34 +141,6 @@ enum qphy_reg_layout {
- QPHY_LAYOUT_SIZE
- };
-
--static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-- [QPHY_START_CTRL] = 0x00,
-- [QPHY_PCS_READY_STATUS] = 0x168,
--};
--
--static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = {
-- [QPHY_SW_RESET] = 0x00,
-- [QPHY_START_CTRL] = 0x44,
-- [QPHY_PCS_STATUS] = 0x14,
-- [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
--};
--
--static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
-- [QPHY_COM_SW_RESET] = 0x400,
-- [QPHY_COM_POWER_DOWN_CONTROL] = 0x404,
-- [QPHY_COM_START_CONTROL] = 0x408,
-- [QPHY_COM_PCS_READY_STATUS] = 0x448,
-- [QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8,
-- [QPHY_FLL_CNTRL1] = 0xc4,
-- [QPHY_FLL_CNTRL2] = 0xc8,
-- [QPHY_FLL_CNT_VAL_L] = 0xcc,
-- [QPHY_FLL_CNT_VAL_H_TOL] = 0xd0,
-- [QPHY_FLL_MAN_CODE] = 0xd4,
-- [QPHY_SW_RESET] = 0x00,
-- [QPHY_START_CTRL] = 0x08,
-- [QPHY_PCS_STATUS] = 0x174,
--};
--
- static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
- [QPHY_FLL_CNTRL1] = 0xc0,
- [QPHY_FLL_CNTRL2] = 0xc4,
-@@ -192,18 +164,6 @@ static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
- [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
- };
-
--static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
-- [QPHY_SW_RESET] = 0x00,
-- [QPHY_START_CTRL] = 0x08,
-- [QPHY_PCS_STATUS] = 0x174,
--};
--
--static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
-- [QPHY_SW_RESET] = 0x00,
-- [QPHY_START_CTRL] = 0x08,
-- [QPHY_PCS_STATUS] = 0x2ac,
--};
--
- static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
- [QPHY_SW_RESET] = 0x00,
- [QPHY_START_CTRL] = 0x44,
-@@ -241,29 +201,6 @@ static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
- [QPHY_PCS_MISC_TYPEC_CTRL] = 0x00,
- };
-
--static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-- [QPHY_START_CTRL] = 0x00,
-- [QPHY_PCS_READY_STATUS] = 0x160,
--};
--
--static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-- [QPHY_START_CTRL] = 0x00,
-- [QPHY_PCS_READY_STATUS] = 0x168,
--};
--
--static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = {
-- [QPHY_SW_RESET] = 0x00,
-- [QPHY_START_CTRL] = 0x44,
-- [QPHY_PCS_STATUS] = 0x14,
-- [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
--};
--
--static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
-- [QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START,
-- [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS,
-- [QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET,
--};
--
- static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
- QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-@@ -339,235 +276,6 @@ static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
- };
-
--static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
-- QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
-- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
-- QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
--};
--
--static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-- QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
--};
--
--static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19),
--};
--
--static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
-- QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
--
-- QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
--
-- QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
-- QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
-- QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
-- QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
--};
--
--static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
--};
--
--static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
--};
--
--static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
--};
--
--static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
--};
--
--static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
-- QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
-- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
--};
--
--static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-- QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
--};
--
--static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
--};
--
- static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
- QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-@@ -639,414 +347,6 @@ static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
- QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
- };
-
--static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
--};
--
--static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12),
--};
--
--static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x61),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1),
-- QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04),
--};
--
--static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01),
-- QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d),
-- QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10),
-- QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa),
-- QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-- QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
-- QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01),
-- QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
-- QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
-- QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-- QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-- QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-- QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-- QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11),
-- QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_PRE, 0x00),
-- QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_POST, 0x58),
--};
--
--static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
-- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
-- QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
-- QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
-- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
-- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
--};
--
--static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-- QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
-- QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
-- QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
-- QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
--};
--
--static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
-- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
-- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
--};
--
--static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
-- QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
-- QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
-- QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
-- QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
-- QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
-- QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
-- QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
-- QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
-- QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
-- QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
-- QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
-- QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
--};
--
--static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
--};
--
--static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
--};
--
--static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
--};
--
--static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
--
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
--
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
--
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
--
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
--};
--
--static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
--};
--
--static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07),
--};
--
--static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
--};
--
--static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = {
--};
--
--static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09),
-- QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f),
--};
--
- static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
-@@ -1094,88 +394,6 @@ static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
- };
-
--static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
--};
--
--static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
--};
--
--static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
--};
--
--static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
--};
--
--static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08),
--};
--
--static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
--};
--
- static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-@@ -1346,175 +564,6 @@ static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
- QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
- };
-
--static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
-- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
-- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
--
-- /* Rate B */
-- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),
--};
--
--static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
-- QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
--};
--
--static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40),
-- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E),
-- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F),
-- QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D),
-- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B),
--};
--
--static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_RX_PWM_GEAR_BAND, 0x15),
-- QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_CTRL2, 0x6d),
-- QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_DRV_LVL, 0x0f),
-- QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_DRV_LVL, 0x02),
-- QMP_PHY_INIT_CFG(QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
-- QMP_PHY_INIT_CFG(QPHY_RX_SYM_RESYNC_CTRL, 0x03),
-- QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
-- QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
-- QMP_PHY_INIT_CFG(QPHY_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
--};
--
--static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
--
-- /* Rate B */
-- QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
--};
--
--static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
--};
--
--static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
--};
--
--static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
-- QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
--};
--
- static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
-@@ -1624,93 +673,6 @@ static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
- };
-
--static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
--
-- /* Rate B */
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
--};
--
--static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
--};
--
--static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
--
--};
--
--static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
--};
--
- static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
-@@ -2023,374 +985,44 @@ static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
--};
--
--static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
--};
--
--static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
--};
--
--static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
--};
--
--static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
--};
--
--static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
--};
--
--static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
--};
--
--static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20),
--};
--
--static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
--};
--
--static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5),
--};
--
--static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
--};
--
--static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),
--};
--
--static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
--};
--
--static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
--};
--
--static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
--};
--
--static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
--};
--
--static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
--};
--
--static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
--};
--
--static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
--};
--
--static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12),
--};
--
--static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
--};
--
--static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f),
--};
--
--static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
--};
--
--static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
-- QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
- QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
- };
-
--static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f),
--};
--
--static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
-- QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
-+static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
-+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
- };
-
- static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
-@@ -2440,101 +1072,6 @@ static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
- QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
- };
-
--static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22),
--};
--
--static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00),
--};
--
--static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-- QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12),
--};
--
--static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77),
-- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01),
-- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16),
-- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02),
--};
--
--static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17),
-- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13),
-- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13),
-- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01),
-- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
-- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
--};
--
- static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = {
- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
-@@ -2579,106 +1116,6 @@ static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = {
- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
- };
-
--static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
--
-- /* Rate B */
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
--};
--
--static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),
--};
--
--static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
--};
--
--static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
--};
--
- static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
-@@ -2910,215 +1347,6 @@ static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
- QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
- };
-
--static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
--};
--
--static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04),
--};
--
--static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09),
-- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
--};
--
--static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
--};
--
--static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
--};
--
--static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
-- QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
--};
--
--static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
--};
--
--static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = {
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
--
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05),
--
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
--
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
--
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
-- QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
--};
--
--/* Register names should be validated, they might be different for this PHY */
--static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e),
-- QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99),
--};
--
--static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
-- QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-- QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
-- QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
-- QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
-- QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),
-- QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
--};
--
- struct qmp_phy;
-
- /* struct qmp_phy_cfg - per-PHY initialization config */
-@@ -3287,16 +1515,6 @@ struct qcom_qmp {
- struct reset_control *ufs_reset;
- };
-
--static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy);
--static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy);
--static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy);
--static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy);
--
--static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy);
--static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy);
--static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy);
--static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy);
--
- static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
- {
- u32 reg;
-@@ -3326,18 +1544,10 @@ static const char * const msm8996_phy_clk_l[] = {
- "aux", "cfg_ahb", "ref",
- };
-
--static const char * const msm8996_ufs_phy_clk_l[] = {
-- "ref",
--};
--
- static const char * const qmp_v3_phy_clk_l[] = {
- "aux", "cfg_ahb", "ref", "com_aux",
- };
-
--static const char * const sdm845_pciephy_clk_l[] = {
-- "aux", "cfg_ahb", "ref", "refgen",
--};
--
- static const char * const qmp_v4_phy_clk_l[] = {
- "aux", "ref_clk_src", "ref", "com_aux",
- };
-@@ -3347,14 +1557,6 @@ static const char * const qmp_v4_sm8250_usbphy_clk_l[] = {
- "aux", "ref_clk_src", "com_aux"
- };
-
--static const char * const sm8450_ufs_phy_clk_l[] = {
-- "qref", "ref", "ref_aux",
--};
--
--static const char * const sdm845_ufs_phy_clk_l[] = {
-- "ref", "ref_aux",
--};
--
- /* usb3 phy on sdx55 doesn't have com_aux clock */
- static const char * const qmp_v4_sdx55_usbphy_clk_l[] = {
- "aux", "cfg_ahb", "ref"
-@@ -3365,10 +1567,6 @@ static const char * const qcm2290_usb3phy_clk_l[] = {
- };
-
- /* list of resets */
--static const char * const msm8996_pciephy_reset_l[] = {
-- "phy", "common", "cfg",
--};
--
- static const char * const msm8996_usb3phy_reset_l[] = {
- "phy", "common",
- };
-@@ -3381,10 +1579,6 @@ static const char * const qcm2290_usb3phy_reset_l[] = {
- "phy_phy", "phy",
- };
-
--static const char * const sdm845_pciephy_reset_l[] = {
-- "phy",
--};
--
- /* list of regulators */
- static const char * const qmp_phy_vreg_l[] = {
- "vdda-phy", "vdda-pll",
-@@ -3415,64 +1609,6 @@ static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
- .phy_status = PHYSTATUS,
- };
-
--static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
-- .type = PHY_TYPE_PCIE,
-- .nlanes = 3,
--
-- .serdes_tbl = msm8996_pcie_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
-- .tx_tbl = msm8996_pcie_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(msm8996_pcie_tx_tbl),
-- .rx_tbl = msm8996_pcie_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(msm8996_pcie_rx_tbl),
-- .pcs_tbl = msm8996_pcie_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
-- .clk_list = msm8996_phy_clk_l,
-- .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-- .reset_list = msm8996_pciephy_reset_l,
-- .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = pciephy_regs_layout,
--
-- .start_ctrl = PCS_START | PLL_READY_GATE_EN,
-- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-- .mask_com_pcs_ready = PCS_READY,
-- .phy_status = PHYSTATUS,
--
-- .has_phy_com_ctrl = true,
-- .has_lane_rst = true,
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
-- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
--};
--
--static const struct qmp_phy_cfg msm8996_ufs_cfg = {
-- .type = PHY_TYPE_UFS,
-- .nlanes = 1,
--
-- .serdes_tbl = msm8996_ufs_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(msm8996_ufs_serdes_tbl),
-- .tx_tbl = msm8996_ufs_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(msm8996_ufs_tx_tbl),
-- .rx_tbl = msm8996_ufs_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(msm8996_ufs_rx_tbl),
--
-- .clk_list = msm8996_ufs_phy_clk_l,
-- .num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
--
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
--
-- .regs = msm8996_ufsphy_regs_layout,
--
-- .start_ctrl = SERDES_START,
-- .pwrdn_ctrl = SW_PWRDN,
-- .phy_status = PHYSTATUS,
--
-- .no_pcs_sw_reset = true,
--};
--
- static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
- .type = PHY_TYPE_USB3,
- .nlanes = 1,
-@@ -3498,214 +1634,6 @@ static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
- .phy_status = PHYSTATUS,
- };
-
--static const char * const ipq8074_pciephy_clk_l[] = {
-- "aux", "cfg_ahb",
--};
--/* list of resets */
--static const char * const ipq8074_pciephy_reset_l[] = {
-- "phy", "common",
--};
--
--static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
-- .type = PHY_TYPE_PCIE,
-- .nlanes = 1,
--
-- .serdes_tbl = ipq8074_pcie_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
-- .tx_tbl = ipq8074_pcie_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
-- .rx_tbl = ipq8074_pcie_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
-- .pcs_tbl = ipq8074_pcie_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
-- .clk_list = ipq8074_pciephy_clk_l,
-- .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
-- .reset_list = ipq8074_pciephy_reset_l,
-- .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
-- .vreg_list = NULL,
-- .num_vregs = 0,
-- .regs = pciephy_regs_layout,
--
-- .start_ctrl = SERDES_START | PCS_START,
-- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-- .phy_status = PHYSTATUS,
--
-- .has_phy_com_ctrl = false,
-- .has_lane_rst = false,
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = 995, /* us */
-- .pwrdn_delay_max = 1005, /* us */
--};
--
--static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
-- .type = PHY_TYPE_PCIE,
-- .nlanes = 1,
--
-- .serdes_tbl = ipq6018_pcie_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl),
-- .tx_tbl = ipq6018_pcie_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl),
-- .rx_tbl = ipq6018_pcie_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
-- .pcs_tbl = ipq6018_pcie_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
-- .clk_list = ipq8074_pciephy_clk_l,
-- .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
-- .reset_list = ipq8074_pciephy_reset_l,
-- .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
-- .vreg_list = NULL,
-- .num_vregs = 0,
-- .regs = ipq_pciephy_gen3_regs_layout,
--
-- .start_ctrl = SERDES_START | PCS_START,
-- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
--
-- .has_phy_com_ctrl = false,
-- .has_lane_rst = false,
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = 995, /* us */
-- .pwrdn_delay_max = 1005, /* us */
--};
--
--static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
-- .type = PHY_TYPE_PCIE,
-- .nlanes = 1,
--
-- .serdes_tbl = sdm845_qmp_pcie_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
-- .tx_tbl = sdm845_qmp_pcie_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),
-- .rx_tbl = sdm845_qmp_pcie_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),
-- .pcs_tbl = sdm845_qmp_pcie_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),
-- .pcs_misc_tbl = sdm845_qmp_pcie_pcs_misc_tbl,
-- .pcs_misc_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
-- .clk_list = sdm845_pciephy_clk_l,
-- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-- .reset_list = sdm845_pciephy_reset_l,
-- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = sdm845_qmp_pciephy_regs_layout,
--
-- .start_ctrl = PCS_START | SERDES_START,
-- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-- .phy_status = PHYSTATUS,
--
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = 995, /* us */
-- .pwrdn_delay_max = 1005, /* us */
--};
--
--static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
-- .type = PHY_TYPE_PCIE,
-- .nlanes = 1,
--
-- .serdes_tbl = sdm845_qhp_pcie_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
-- .tx_tbl = sdm845_qhp_pcie_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
-- .rx_tbl = sdm845_qhp_pcie_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl),
-- .pcs_tbl = sdm845_qhp_pcie_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
-- .clk_list = sdm845_pciephy_clk_l,
-- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-- .reset_list = sdm845_pciephy_reset_l,
-- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = sdm845_qhp_pciephy_regs_layout,
--
-- .start_ctrl = PCS_START | SERDES_START,
-- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-- .phy_status = PHYSTATUS,
--
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = 995, /* us */
-- .pwrdn_delay_max = 1005, /* us */
--};
--
--static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
-- .type = PHY_TYPE_PCIE,
-- .nlanes = 1,
--
-- .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
-- .serdes_tbl_sec = sm8250_qmp_gen3x1_pcie_serdes_tbl,
-- .serdes_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
-- .tx_tbl = sm8250_qmp_pcie_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
-- .rx_tbl = sm8250_qmp_pcie_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
-- .rx_tbl_sec = sm8250_qmp_gen3x1_pcie_rx_tbl,
-- .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),
-- .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
-- .pcs_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_tbl,
-- .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),
-- .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
-- .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
-- .pcs_misc_tbl_sec = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,
-- .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),
-- .clk_list = sdm845_pciephy_clk_l,
-- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-- .reset_list = sdm845_pciephy_reset_l,
-- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = sm8250_pcie_regs_layout,
--
-- .start_ctrl = PCS_START | SERDES_START,
-- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-- .phy_status = PHYSTATUS,
--
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = 995, /* us */
-- .pwrdn_delay_max = 1005, /* us */
--};
--
--static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
-- .type = PHY_TYPE_PCIE,
-- .nlanes = 2,
--
-- .serdes_tbl = sm8250_qmp_pcie_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
-- .tx_tbl = sm8250_qmp_pcie_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
-- .tx_tbl_sec = sm8250_qmp_gen3x2_pcie_tx_tbl,
-- .tx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),
-- .rx_tbl = sm8250_qmp_pcie_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
-- .rx_tbl_sec = sm8250_qmp_gen3x2_pcie_rx_tbl,
-- .rx_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl),
-- .pcs_tbl = sm8250_qmp_pcie_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
-- .pcs_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_tbl,
-- .pcs_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl),
-- .pcs_misc_tbl = sm8250_qmp_pcie_pcs_misc_tbl,
-- .pcs_misc_tbl_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
-- .pcs_misc_tbl_sec = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,
-- .pcs_misc_tbl_num_sec = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),
-- .clk_list = sdm845_pciephy_clk_l,
-- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-- .reset_list = sdm845_pciephy_reset_l,
-- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = sm8250_pcie_regs_layout,
--
-- .start_ctrl = PCS_START | SERDES_START,
-- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-- .phy_status = PHYSTATUS,
--
-- .is_dual_lane_phy = true,
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = 995, /* us */
-- .pwrdn_delay_max = 1005, /* us */
--};
--
- static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
- .type = PHY_TYPE_USB3,
- .nlanes = 1,
-@@ -3770,46 +1698,6 @@ static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
- .is_dual_lane_phy = true,
- };
-
--static const struct qmp_phy_cfg sc7180_dpphy_cfg = {
-- .type = PHY_TYPE_DP,
-- .nlanes = 1,
--
-- .serdes_tbl = qmp_v3_dp_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
-- .tx_tbl = qmp_v3_dp_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
--
-- .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr,
-- .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
-- .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr,
-- .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
-- .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2,
-- .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
-- .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3,
-- .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
--
-- .clk_list = qmp_v3_phy_clk_l,
-- .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-- .reset_list = sc7180_usb3phy_reset_l,
-- .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = qmp_v3_usb3phy_regs_layout,
--
-- .has_phy_dp_com_ctrl = true,
-- .is_dual_lane_phy = true,
--
-- .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init,
-- .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx,
-- .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy,
-- .calibrate_dp_phy = qcom_qmp_v3_dp_phy_calibrate,
--};
--
--static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = {
-- .usb_cfg = &sc7180_usb3phy_cfg,
-- .dp_cfg = &sc7180_dpphy_cfg,
--};
--
- static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
- .type = PHY_TYPE_USB3,
- .nlanes = 1,
-@@ -3839,82 +1727,6 @@ static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
- };
-
--static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
-- .type = PHY_TYPE_UFS,
-- .nlanes = 2,
--
-- .serdes_tbl = sdm845_ufsphy_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
-- .tx_tbl = sdm845_ufsphy_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
-- .rx_tbl = sdm845_ufsphy_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
-- .pcs_tbl = sdm845_ufsphy_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
-- .clk_list = sdm845_ufs_phy_clk_l,
-- .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = sdm845_ufsphy_regs_layout,
--
-- .start_ctrl = SERDES_START,
-- .pwrdn_ctrl = SW_PWRDN,
-- .phy_status = PHYSTATUS,
--
-- .is_dual_lane_phy = true,
-- .no_pcs_sw_reset = true,
--};
--
--static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
-- .type = PHY_TYPE_UFS,
-- .nlanes = 1,
--
-- .serdes_tbl = sm6115_ufsphy_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl),
-- .tx_tbl = sm6115_ufsphy_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_tx_tbl),
-- .rx_tbl = sm6115_ufsphy_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_rx_tbl),
-- .pcs_tbl = sm6115_ufsphy_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl),
-- .clk_list = sdm845_ufs_phy_clk_l,
-- .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = sm6115_ufsphy_regs_layout,
--
-- .start_ctrl = SERDES_START,
-- .pwrdn_ctrl = SW_PWRDN,
--
-- .is_dual_lane_phy = false,
-- .no_pcs_sw_reset = true,
--};
--
--static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
-- .type = PHY_TYPE_PCIE,
-- .nlanes = 1,
--
-- .serdes_tbl = msm8998_pcie_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
-- .tx_tbl = msm8998_pcie_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(msm8998_pcie_tx_tbl),
-- .rx_tbl = msm8998_pcie_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(msm8998_pcie_rx_tbl),
-- .pcs_tbl = msm8998_pcie_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
-- .clk_list = msm8996_phy_clk_l,
-- .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
-- .reset_list = ipq8074_pciephy_reset_l,
-- .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = pciephy_regs_layout,
--
-- .start_ctrl = SERDES_START | PCS_START,
-- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-- .phy_status = PHYSTATUS,
--};
--
- static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
- .type = PHY_TYPE_USB3,
- .nlanes = 1,
-@@ -3933,38 +1745,13 @@ static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
- .vreg_list = qmp_phy_vreg_l,
- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = qmp_v3_usb3phy_regs_layout,
--
-- .start_ctrl = SERDES_START | PCS_START,
-- .pwrdn_ctrl = SW_PWRDN,
-- .phy_status = PHYSTATUS,
--
-- .is_dual_lane_phy = true,
--};
--
--static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
-- .type = PHY_TYPE_UFS,
-- .nlanes = 2,
--
-- .serdes_tbl = sm8150_ufsphy_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl),
-- .tx_tbl = sm8150_ufsphy_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx_tbl),
-- .rx_tbl = sm8150_ufsphy_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx_tbl),
-- .pcs_tbl = sm8150_ufsphy_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl),
-- .clk_list = sdm845_ufs_phy_clk_l,
-- .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = sm8150_ufsphy_regs_layout,
-+ .regs = qmp_v3_usb3phy_regs_layout,
-
-- .start_ctrl = SERDES_START,
-- .pwrdn_ctrl = SW_PWRDN,
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN,
- .phy_status = PHYSTATUS,
-
-- .is_dual_lane_phy = true,
-+ .is_dual_lane_phy = true,
- };
-
- static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
-@@ -4000,76 +1787,6 @@ static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
- .is_dual_lane_phy = true,
- };
-
--static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
-- .type = PHY_TYPE_PCIE,
-- .nlanes = 1,
--
-- .serdes_tbl = sc8180x_qmp_pcie_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl),
-- .tx_tbl = sc8180x_qmp_pcie_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl),
-- .rx_tbl = sc8180x_qmp_pcie_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl),
-- .pcs_tbl = sc8180x_qmp_pcie_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl),
-- .pcs_misc_tbl = sc8180x_qmp_pcie_pcs_misc_tbl,
-- .pcs_misc_tbl_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl),
-- .clk_list = sdm845_pciephy_clk_l,
-- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-- .reset_list = sdm845_pciephy_reset_l,
-- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = sm8250_pcie_regs_layout,
--
-- .start_ctrl = PCS_START | SERDES_START,
-- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
--
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = 995, /* us */
-- .pwrdn_delay_max = 1005, /* us */
--};
--
--static const struct qmp_phy_cfg sc8180x_dpphy_cfg = {
-- .type = PHY_TYPE_DP,
-- .nlanes = 1,
--
-- .serdes_tbl = qmp_v4_dp_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
-- .tx_tbl = qmp_v4_dp_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
--
-- .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
-- .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
-- .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
-- .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
-- .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
-- .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
-- .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
-- .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
--
-- .clk_list = qmp_v3_phy_clk_l,
-- .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
-- .reset_list = sc7180_usb3phy_reset_l,
-- .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = qmp_v3_usb3phy_regs_layout,
--
-- .has_phy_dp_com_ctrl = true,
-- .is_dual_lane_phy = true,
--
-- .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
-- .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
-- .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
-- .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
--};
--
--static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = {
-- .usb_cfg = &sm8150_usb3phy_cfg,
-- .dp_cfg = &sc8180x_dpphy_cfg,
--};
--
- static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
- .type = PHY_TYPE_USB3,
- .nlanes = 1,
-@@ -4160,46 +1877,6 @@ static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
- };
-
--static const struct qmp_phy_cfg sm8250_dpphy_cfg = {
-- .type = PHY_TYPE_DP,
-- .nlanes = 1,
--
-- .serdes_tbl = qmp_v4_dp_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
-- .tx_tbl = qmp_v4_dp_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
--
-- .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
-- .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
-- .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
-- .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
-- .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
-- .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
-- .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
-- .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
--
-- .clk_list = qmp_v4_phy_clk_l,
-- .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
-- .reset_list = msm8996_usb3phy_reset_l,
-- .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = qmp_v4_usb3phy_regs_layout,
--
-- .has_phy_dp_com_ctrl = true,
-- .is_dual_lane_phy = true,
--
-- .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
-- .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
-- .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
-- .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
--};
--
--static const struct qmp_phy_combo_cfg sm8250_usb3dpphy_cfg = {
-- .usb_cfg = &sm8250_usb3phy_cfg,
-- .dp_cfg = &sm8250_dpphy_cfg,
--};
--
- static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
- .type = PHY_TYPE_USB3,
- .nlanes = 1,
-@@ -4229,38 +1906,6 @@ static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
- };
-
--static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
-- .type = PHY_TYPE_PCIE,
-- .nlanes = 2,
--
-- .serdes_tbl = sdx55_qmp_pcie_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl),
-- .tx_tbl = sdx55_qmp_pcie_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl),
-- .rx_tbl = sdx55_qmp_pcie_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl),
-- .pcs_tbl = sdx55_qmp_pcie_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl),
-- .pcs_misc_tbl = sdx55_qmp_pcie_pcs_misc_tbl,
-- .pcs_misc_tbl_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl),
-- .clk_list = sdm845_pciephy_clk_l,
-- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-- .reset_list = sdm845_pciephy_reset_l,
-- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = sm8250_pcie_regs_layout,
--
-- .start_ctrl = PCS_START | SERDES_START,
-- .pwrdn_ctrl = SW_PWRDN,
-- .phy_status = PHYSTATUS_4_20,
--
-- .is_dual_lane_phy = true,
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = 995, /* us */
-- .pwrdn_delay_max = 1005, /* us */
--};
--
- static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
- .type = PHY_TYPE_USB3,
- .nlanes = 1,
-@@ -4290,31 +1935,6 @@ static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
- };
-
--static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
-- .type = PHY_TYPE_UFS,
-- .nlanes = 2,
--
-- .serdes_tbl = sm8350_ufsphy_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
-- .tx_tbl = sm8350_ufsphy_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
-- .rx_tbl = sm8350_ufsphy_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
-- .pcs_tbl = sm8350_ufsphy_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
-- .clk_list = sdm845_ufs_phy_clk_l,
-- .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = sm8150_ufsphy_regs_layout,
--
-- .start_ctrl = SERDES_START,
-- .pwrdn_ctrl = SW_PWRDN,
-- .phy_status = PHYSTATUS,
--
-- .is_dual_lane_phy = true,
--};
--
- static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
- .type = PHY_TYPE_USB3,
- .nlanes = 1,
-@@ -4376,94 +1996,6 @@ static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
- .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
- };
-
--static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
-- .type = PHY_TYPE_UFS,
-- .nlanes = 2,
--
-- .serdes_tbl = sm8350_ufsphy_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
-- .tx_tbl = sm8350_ufsphy_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
-- .rx_tbl = sm8350_ufsphy_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
-- .pcs_tbl = sm8350_ufsphy_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
-- .clk_list = sm8450_ufs_phy_clk_l,
-- .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = sm8150_ufsphy_regs_layout,
--
-- .start_ctrl = SERDES_START,
-- .pwrdn_ctrl = SW_PWRDN,
-- .phy_status = PHYSTATUS,
--
-- .is_dual_lane_phy = true,
--};
--
--static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
-- .type = PHY_TYPE_PCIE,
-- .nlanes = 1,
--
-- .serdes_tbl = sm8450_qmp_gen3x1_pcie_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl),
-- .tx_tbl = sm8450_qmp_gen3x1_pcie_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl),
-- .rx_tbl = sm8450_qmp_gen3x1_pcie_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl),
-- .pcs_tbl = sm8450_qmp_gen3x1_pcie_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl),
-- .pcs_misc_tbl = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
-- .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
-- .clk_list = sdm845_pciephy_clk_l,
-- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-- .reset_list = sdm845_pciephy_reset_l,
-- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = sm8250_pcie_regs_layout,
--
-- .start_ctrl = SERDES_START | PCS_START,
-- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-- .phy_status = PHYSTATUS,
--
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = 995, /* us */
-- .pwrdn_delay_max = 1005, /* us */
--};
--
--static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
-- .type = PHY_TYPE_PCIE,
-- .nlanes = 2,
--
-- .serdes_tbl = sm8450_qmp_gen4x2_pcie_serdes_tbl,
-- .serdes_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl),
-- .tx_tbl = sm8450_qmp_gen4x2_pcie_tx_tbl,
-- .tx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl),
-- .rx_tbl = sm8450_qmp_gen4x2_pcie_rx_tbl,
-- .rx_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl),
-- .pcs_tbl = sm8450_qmp_gen4x2_pcie_pcs_tbl,
-- .pcs_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl),
-- .pcs_misc_tbl = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl,
-- .pcs_misc_tbl_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl),
-- .clk_list = sdm845_pciephy_clk_l,
-- .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
-- .reset_list = sdm845_pciephy_reset_l,
-- .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
-- .vreg_list = qmp_phy_vreg_l,
-- .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
-- .regs = sm8250_pcie_regs_layout,
--
-- .start_ctrl = SERDES_START | PCS_START,
-- .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-- .phy_status = PHYSTATUS_4_20,
--
-- .is_dual_lane_phy = true,
-- .has_pwrdn_delay = true,
-- .pwrdn_delay_min = 995, /* us */
-- .pwrdn_delay_max = 1005, /* us */
--};
--
- static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
- .type = PHY_TYPE_USB3,
- .nlanes = 1,
-@@ -4589,457 +2121,6 @@ static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
- return 0;
- }
-
--static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy)
--{
-- writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
-- DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
-- qphy->pcs + QSERDES_DP_PHY_PD_CTL);
--
-- /* Turn on BIAS current for PHY/PLL */
-- writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
-- QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
-- qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
--
-- writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
--
-- writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
-- DP_PHY_PD_CTL_LANE_0_1_PWRDN |
-- DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
-- DP_PHY_PD_CTL_DP_CLAMP_EN,
-- qphy->pcs + QSERDES_DP_PHY_PD_CTL);
--
-- writel(QSERDES_V3_COM_BIAS_EN |
-- QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
-- QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL |
-- QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
-- qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
--
-- writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
-- writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-- writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
-- writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
-- writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
-- writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
-- writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
-- writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
-- writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
-- writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
-- qphy->dp_aux_cfg = 0;
--
-- writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
-- PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
-- PHY_AUX_REQ_ERR_MASK,
-- qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
--}
--
--static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = {
-- { 0x00, 0x0c, 0x15, 0x1a },
-- { 0x02, 0x0e, 0x16, 0xff },
-- { 0x02, 0x11, 0xff, 0xff },
-- { 0x04, 0xff, 0xff, 0xff }
--};
--
--static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = {
-- { 0x02, 0x12, 0x16, 0x1a },
-- { 0x09, 0x19, 0x1f, 0xff },
-- { 0x10, 0x1f, 0xff, 0xff },
-- { 0x1f, 0xff, 0xff, 0xff }
--};
--
--static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = {
-- { 0x00, 0x0c, 0x14, 0x19 },
-- { 0x00, 0x0b, 0x12, 0xff },
-- { 0x00, 0x0b, 0xff, 0xff },
-- { 0x04, 0xff, 0xff, 0xff }
--};
--
--static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = {
-- { 0x08, 0x0f, 0x16, 0x1f },
-- { 0x11, 0x1e, 0x1f, 0xff },
-- { 0x19, 0x1f, 0xff, 0xff },
-- { 0x1f, 0xff, 0xff, 0xff }
--};
--
--static int qcom_qmp_phy_configure_dp_swing(struct qmp_phy *qphy,
-- unsigned int drv_lvl_reg, unsigned int emp_post_reg)
--{
-- const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-- unsigned int v_level = 0, p_level = 0;
-- u8 voltage_swing_cfg, pre_emphasis_cfg;
-- int i;
--
-- for (i = 0; i < dp_opts->lanes; i++) {
-- v_level = max(v_level, dp_opts->voltage[i]);
-- p_level = max(p_level, dp_opts->pre[i]);
-- }
--
-- if (dp_opts->link_rate <= 2700) {
-- voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level];
-- pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level];
-- } else {
-- voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr3_hbr2[v_level][p_level];
-- pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr3_hbr2[v_level][p_level];
-- }
--
-- /* TODO: Move check to config check */
-- if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF)
-- return -EINVAL;
--
-- /* Enable MUX to use Cursor values from these registers */
-- voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
-- pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
--
-- writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg);
-- writel(pre_emphasis_cfg, qphy->tx + emp_post_reg);
-- writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg);
-- writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg);
--
-- return 0;
--}
--
--static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy)
--{
-- const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-- u32 bias_en, drvr_en;
--
-- if (qcom_qmp_phy_configure_dp_swing(qphy,
-- QSERDES_V3_TX_TX_DRV_LVL,
-- QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0)
-- return;
--
-- if (dp_opts->lanes == 1) {
-- bias_en = 0x3e;
-- drvr_en = 0x13;
-- } else {
-- bias_en = 0x3f;
-- drvr_en = 0x10;
-- }
--
-- writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN);
-- writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
-- writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN);
-- writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
--}
--
--static bool qcom_qmp_phy_configure_dp_mode(struct qmp_phy *qphy)
--{
-- u32 val;
-- bool reverse = false;
--
-- val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
-- DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN;
--
-- /*
-- * TODO: Assume orientation is CC1 for now and two lanes, need to
-- * use type-c connector to understand orientation and lanes.
-- *
-- * Otherwise val changes to be like below if this code understood
-- * the orientation of the type-c cable.
-- *
-- * if (lane_cnt == 4 || orientation == ORIENTATION_CC2)
-- * val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN;
-- * if (lane_cnt == 4 || orientation == ORIENTATION_CC1)
-- * val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
-- * if (orientation == ORIENTATION_CC2)
-- * writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
-- */
-- val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
-- writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
--
-- writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE);
--
-- return reverse;
--}
--
--static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy)
--{
-- const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
-- const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-- u32 phy_vco_div, status;
-- unsigned long pixel_freq;
--
-- qcom_qmp_phy_configure_dp_mode(qphy);
--
-- writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
-- writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
--
-- switch (dp_opts->link_rate) {
-- case 1620:
-- phy_vco_div = 0x1;
-- pixel_freq = 1620000000UL / 2;
-- break;
-- case 2700:
-- phy_vco_div = 0x1;
-- pixel_freq = 2700000000UL / 2;
-- break;
-- case 5400:
-- phy_vco_div = 0x2;
-- pixel_freq = 5400000000UL / 4;
-- break;
-- case 8100:
-- phy_vco_div = 0x0;
-- pixel_freq = 8100000000UL / 6;
-- break;
-- default:
-- /* Other link rates aren't supported */
-- return -EINVAL;
-- }
-- writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV);
--
-- clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
-- clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
--
-- writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
-- writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
-- writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
-- writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
-- writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
--
-- writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL);
--
-- if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS,
-- status,
-- ((status & BIT(0)) > 0),
-- 500,
-- 10000))
-- return -ETIMEDOUT;
--
-- writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
--
-- if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
-- status,
-- ((status & BIT(1)) > 0),
-- 500,
-- 10000))
-- return -ETIMEDOUT;
--
-- writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
-- udelay(2000);
-- writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
--
-- return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
-- status,
-- ((status & BIT(1)) > 0),
-- 500,
-- 10000);
--}
--
--/*
-- * We need to calibrate the aux setting here as many times
-- * as the caller tries
-- */
--static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy)
--{
-- static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d };
-- u8 val;
--
-- qphy->dp_aux_cfg++;
-- qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
-- val = cfg1_settings[qphy->dp_aux_cfg];
--
-- writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
--
-- return 0;
--}
--
--static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy)
--{
-- writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
-- DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
-- qphy->pcs + QSERDES_DP_PHY_PD_CTL);
--
-- /* Turn on BIAS current for PHY/PLL */
-- writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN);
--
-- writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
-- writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-- writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
-- writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
-- writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
-- writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
-- writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
-- writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
-- writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
-- writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
-- qphy->dp_aux_cfg = 0;
--
-- writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
-- PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
-- PHY_AUX_REQ_ERR_MASK,
-- qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
--}
--
--static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy)
--{
-- /* Program default values before writing proper values */
-- writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
-- writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
--
-- writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
-- writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
--
-- qcom_qmp_phy_configure_dp_swing(qphy,
-- QSERDES_V4_TX_TX_DRV_LVL,
-- QSERDES_V4_TX_TX_EMP_POST1_LVL);
--}
--
--static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy)
--{
-- const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
-- const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
-- u32 phy_vco_div, status;
-- unsigned long pixel_freq;
-- u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
-- bool reverse;
--
-- writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1);
--
-- reverse = qcom_qmp_phy_configure_dp_mode(qphy);
--
-- writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
-- writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
--
-- writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL);
-- writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL);
--
-- switch (dp_opts->link_rate) {
-- case 1620:
-- phy_vco_div = 0x1;
-- pixel_freq = 1620000000UL / 2;
-- break;
-- case 2700:
-- phy_vco_div = 0x1;
-- pixel_freq = 2700000000UL / 2;
-- break;
-- case 5400:
-- phy_vco_div = 0x2;
-- pixel_freq = 5400000000UL / 4;
-- break;
-- case 8100:
-- phy_vco_div = 0x0;
-- pixel_freq = 8100000000UL / 6;
-- break;
-- default:
-- /* Other link rates aren't supported */
-- return -EINVAL;
-- }
-- writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV);
--
-- clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
-- clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
--
-- writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
-- writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
-- writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
-- writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
--
-- writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL);
--
-- if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS,
-- status,
-- ((status & BIT(0)) > 0),
-- 500,
-- 10000))
-- return -ETIMEDOUT;
--
-- if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
-- status,
-- ((status & BIT(0)) > 0),
-- 500,
-- 10000))
-- return -ETIMEDOUT;
--
-- if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
-- status,
-- ((status & BIT(1)) > 0),
-- 500,
-- 10000))
-- return -ETIMEDOUT;
--
-- writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
--
-- if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
-- status,
-- ((status & BIT(0)) > 0),
-- 500,
-- 10000))
-- return -ETIMEDOUT;
--
-- if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
-- status,
-- ((status & BIT(1)) > 0),
-- 500,
-- 10000))
-- return -ETIMEDOUT;
--
-- /*
-- * At least for 7nm DP PHY this has to be done after enabling link
-- * clock.
-- */
--
-- if (dp_opts->lanes == 1) {
-- bias0_en = reverse ? 0x3e : 0x15;
-- bias1_en = reverse ? 0x15 : 0x3e;
-- drvr0_en = reverse ? 0x13 : 0x10;
-- drvr1_en = reverse ? 0x10 : 0x13;
-- } else if (dp_opts->lanes == 2) {
-- bias0_en = reverse ? 0x3f : 0x15;
-- bias1_en = reverse ? 0x15 : 0x3f;
-- drvr0_en = 0x10;
-- drvr1_en = 0x10;
-- } else {
-- bias0_en = 0x3f;
-- bias1_en = 0x3f;
-- drvr0_en = 0x10;
-- drvr1_en = 0x10;
-- }
--
-- writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN);
-- writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
-- writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN);
-- writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
--
-- writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
-- udelay(2000);
-- writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
--
-- if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
-- status,
-- ((status & BIT(1)) > 0),
-- 500,
-- 10000))
-- return -ETIMEDOUT;
--
-- writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV);
-- writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV);
--
-- writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
-- writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
--
-- writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
-- writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
--
-- return 0;
--}
--
--/*
-- * We need to calibrate the aux setting here as many times
-- * as the caller tries
-- */
--static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy)
--{
-- static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d };
-- u8 val;
--
-- qphy->dp_aux_cfg++;
-- qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
-- val = cfg1_settings[qphy->dp_aux_cfg];
--
-- writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
--
-- return 0;
--}
--
- static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
- {
- const struct phy_configure_opts_dp *dp_opts = &opts->dp;
-@@ -6023,81 +3104,27 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
- {
- .compatible = "qcom,ipq8074-qmp-usb3-phy",
- .data = &ipq8074_usb3phy_cfg,
-- }, {
-- .compatible = "qcom,msm8996-qmp-pcie-phy",
-- .data = &msm8996_pciephy_cfg,
-- }, {
-- .compatible = "qcom,msm8996-qmp-ufs-phy",
-- .data = &msm8996_ufs_cfg,
- }, {
- .compatible = "qcom,msm8996-qmp-usb3-phy",
- .data = &msm8996_usb3phy_cfg,
-- }, {
-- .compatible = "qcom,msm8998-qmp-pcie-phy",
-- .data = &msm8998_pciephy_cfg,
-- }, {
-- .compatible = "qcom,msm8998-qmp-ufs-phy",
-- .data = &sdm845_ufsphy_cfg,
-- }, {
-- .compatible = "qcom,ipq8074-qmp-pcie-phy",
-- .data = &ipq8074_pciephy_cfg,
-- }, {
-- .compatible = "qcom,ipq6018-qmp-pcie-phy",
-- .data = &ipq6018_pciephy_cfg,
- }, {
- .compatible = "qcom,ipq6018-qmp-usb3-phy",
- .data = &ipq8074_usb3phy_cfg,
- }, {
- .compatible = "qcom,sc7180-qmp-usb3-phy",
- .data = &sc7180_usb3phy_cfg,
-- }, {
-- .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
-- /* It's a combo phy */
-- }, {
-- .compatible = "qcom,sc8180x-qmp-pcie-phy",
-- .data = &sc8180x_pciephy_cfg,
-- }, {
-- .compatible = "qcom,sc8180x-qmp-ufs-phy",
-- .data = &sm8150_ufsphy_cfg,
-- }, {
-- .compatible = "qcom,sc8280xp-qmp-ufs-phy",
-- .data = &sm8350_ufsphy_cfg,
- }, {
- .compatible = "qcom,sc8180x-qmp-usb3-phy",
- .data = &sm8150_usb3phy_cfg,
-- }, {
-- .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
-- /* It's a combo phy */
-- }, {
-- .compatible = "qcom,sdm845-qhp-pcie-phy",
-- .data = &sdm845_qhp_pciephy_cfg,
-- }, {
-- .compatible = "qcom,sdm845-qmp-pcie-phy",
-- .data = &sdm845_qmp_pciephy_cfg,
- }, {
- .compatible = "qcom,sdm845-qmp-usb3-phy",
- .data = &qmp_v3_usb3phy_cfg,
- }, {
- .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
- .data = &qmp_v3_usb3_uniphy_cfg,
-- }, {
-- .compatible = "qcom,sdm845-qmp-ufs-phy",
-- .data = &sdm845_ufsphy_cfg,
- }, {
- .compatible = "qcom,msm8998-qmp-usb3-phy",
- .data = &msm8998_usb3phy_cfg,
-- }, {
-- .compatible = "qcom,sm6115-qmp-ufs-phy",
-- .data = &sm6115_ufsphy_cfg,
-- }, {
-- .compatible = "qcom,sm6350-qmp-ufs-phy",
-- .data = &sdm845_ufsphy_cfg,
-- }, {
-- .compatible = "qcom,sm8150-qmp-ufs-phy",
-- .data = &sm8150_ufsphy_cfg,
-- }, {
-- .compatible = "qcom,sm8250-qmp-ufs-phy",
-- .data = &sm8150_ufsphy_cfg,
- }, {
- .compatible = "qcom,sm8150-qmp-usb3-phy",
- .data = &sm8150_usb3phy_cfg,
-@@ -6107,27 +3134,9 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
- }, {
- .compatible = "qcom,sm8250-qmp-usb3-phy",
- .data = &sm8250_usb3phy_cfg,
-- }, {
-- .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
-- /* It's a combo phy */
- }, {
- .compatible = "qcom,sm8250-qmp-usb3-uni-phy",
- .data = &sm8250_usb3_uniphy_cfg,
-- }, {
-- .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
-- .data = &sm8250_qmp_gen3x1_pciephy_cfg,
-- }, {
-- .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
-- .data = &sm8250_qmp_gen3x2_pciephy_cfg,
-- }, {
-- .compatible = "qcom,sm8350-qmp-ufs-phy",
-- .data = &sm8350_ufsphy_cfg,
-- }, {
-- .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
-- .data = &sm8250_qmp_gen3x2_pciephy_cfg,
-- }, {
-- .compatible = "qcom,sdx55-qmp-pcie-phy",
-- .data = &sdx55_qmp_pciephy_cfg,
- }, {
- .compatible = "qcom,sdx55-qmp-usb3-uni-phy",
- .data = &sdx55_usb3_uniphy_cfg,
-@@ -6140,15 +3149,6 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
- }, {
- .compatible = "qcom,sm8350-qmp-usb3-uni-phy",
- .data = &sm8350_usb3_uniphy_cfg,
-- }, {
-- .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
-- .data = &sm8450_qmp_gen3x1_pciephy_cfg,
-- }, {
-- .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
-- .data = &sm8450_qmp_gen4x2_pciephy_cfg,
-- }, {
-- .compatible = "qcom,sm8450-qmp-ufs-phy",
-- .data = &sm8450_ufsphy_cfg,
- }, {
- .compatible = "qcom,sm8450-qmp-usb3-phy",
- .data = &sm8350_usb3phy_cfg,
-@@ -6160,22 +3160,6 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
- };
- MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
-
--static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = {
-- {
-- .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
-- .data = &sc7180_usb3dpphy_cfg,
-- },
-- {
-- .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
-- .data = &sm8250_usb3dpphy_cfg,
-- },
-- {
-- .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
-- .data = &sc8180x_usb3dpphy_cfg,
-- },
-- { }
--};
--
- static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
- SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
- qcom_qmp_phy_runtime_resume, NULL)
-@@ -6206,20 +3190,8 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
-
- /* Get the specific init parameters of QMP phy */
- cfg = of_device_get_match_data(dev);
-- if (!cfg) {
-- const struct of_device_id *match;
--
-- match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev);
-- if (!match)
-- return -EINVAL;
--
-- combo_cfg = match->data;
-- if (!combo_cfg)
-- return -EINVAL;
--
-- usb_cfg = combo_cfg->usb_cfg;
-- cfg = usb_cfg; /* Setup clks and regulators */
-- }
-+ if (!cfg)
-+ return -EINVAL;
-
- /* per PHY serdes; usually located at base address */
- usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0);
-@@ -6336,7 +3308,7 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev)
- static struct platform_driver qcom_qmp_phy_driver = {
- .probe = qcom_qmp_phy_probe,
- .driver = {
-- .name = "qcom-qmp-phy",
-+ .name = "qcom-qmp-usb-phy",
- .pm = &qcom_qmp_phy_pm_ops,
- .of_match_table = qcom_qmp_phy_of_match_table,
- },
-@@ -6345,5 +3317,5 @@ static struct platform_driver qcom_qmp_phy_driver = {
- module_platform_driver(qcom_qmp_phy_driver);
-
- MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
--MODULE_DESCRIPTION("Qualcomm QMP PHY driver");
-+MODULE_DESCRIPTION("Qualcomm QMP USB PHY driver");
- MODULE_LICENSE("GPL v2");
---
-2.35.1
-
+++ /dev/null
-From a27bf0d085843b2d538221bdbd250c82aa7eeb1f Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Wed, 8 Jun 2022 00:31:51 +0300
-Subject: phy: qcom-qmp-usb: drop support for non-USB PHY types
-
-From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-
-[ Upstream commit 86f5ddddcd9c4755e3d1d1ca4be01df5a4ed5d96 ]
-
-Drop remaining support for PHY types other than USB.
-
-Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> # UFS, PCIe and USB on SC8180X
-Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Link: https://lore.kernel.org/r/20220607213203.2819885-19-dmitry.baryshkov@linaro.org
-Signed-off-by: Vinod Koul <vkoul@kernel.org>
-Stable-dep-of: a5d6b1ac56cb ("phy: qcom-qmp-usb: fix memleak on probe deferral")
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 435 +++---------------------
- 1 file changed, 48 insertions(+), 387 deletions(-)
-
-diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
-index 2ae13b4485b6..55785dcd47e0 100644
---- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
-+++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
-@@ -2059,7 +2059,6 @@ static int qcom_qmp_phy_usb_serdes_init(struct qmp_phy *qphy)
- struct qcom_qmp *qmp = qphy->qmp;
- const struct qmp_phy_cfg *cfg = qphy->cfg;
- void __iomem *serdes = qphy->serdes;
-- const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
- const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
- int serdes_tbl_num = cfg->serdes_tbl_num;
- int ret;
-@@ -2069,35 +2068,6 @@ static int qcom_qmp_phy_usb_serdes_init(struct qmp_phy *qphy)
- qcom_qmp_phy_usb_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
- cfg->serdes_tbl_num_sec);
-
-- if (cfg->type == PHY_TYPE_DP) {
-- switch (dp_opts->link_rate) {
-- case 1620:
-- qcom_qmp_phy_usb_configure(serdes, cfg->regs,
-- cfg->serdes_tbl_rbr,
-- cfg->serdes_tbl_rbr_num);
-- break;
-- case 2700:
-- qcom_qmp_phy_usb_configure(serdes, cfg->regs,
-- cfg->serdes_tbl_hbr,
-- cfg->serdes_tbl_hbr_num);
-- break;
-- case 5400:
-- qcom_qmp_phy_usb_configure(serdes, cfg->regs,
-- cfg->serdes_tbl_hbr2,
-- cfg->serdes_tbl_hbr2_num);
-- break;
-- case 8100:
-- qcom_qmp_phy_usb_configure(serdes, cfg->regs,
-- cfg->serdes_tbl_hbr3,
-- cfg->serdes_tbl_hbr3_num);
-- break;
-- default:
-- /* Other link rates aren't supported */
-- return -EINVAL;
-- }
-- }
--
--
- if (cfg->has_phy_com_ctrl) {
- void __iomem *status;
- unsigned int mask, val;
-@@ -2121,32 +2091,6 @@ static int qcom_qmp_phy_usb_serdes_init(struct qmp_phy *qphy)
- return 0;
- }
-
--static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
--{
-- const struct phy_configure_opts_dp *dp_opts = &opts->dp;
-- struct qmp_phy *qphy = phy_get_drvdata(phy);
-- const struct qmp_phy_cfg *cfg = qphy->cfg;
--
-- memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts));
-- if (qphy->dp_opts.set_voltages) {
-- cfg->configure_dp_tx(qphy);
-- qphy->dp_opts.set_voltages = 0;
-- }
--
-- return 0;
--}
--
--static int qcom_qmp_dp_phy_calibrate(struct phy *phy)
--{
-- struct qmp_phy *qphy = phy_get_drvdata(phy);
-- const struct qmp_phy_cfg *cfg = qphy->cfg;
--
-- if (cfg->calibrate_dp_phy)
-- return cfg->calibrate_dp_phy(qphy);
--
-- return 0;
--}
--
- static int qcom_qmp_phy_usb_com_init(struct qmp_phy *qphy)
- {
- struct qcom_qmp *qmp = qphy->qmp;
-@@ -2316,9 +2260,6 @@ static int qcom_qmp_phy_usb_init(struct phy *phy)
- if (ret)
- return ret;
-
-- if (cfg->type == PHY_TYPE_DP)
-- cfg->dp_aux_init(qphy);
--
- return 0;
- }
-
-@@ -2369,10 +2310,6 @@ static int qcom_qmp_phy_usb_power_on(struct phy *phy)
- cfg->tx_tbl_num_sec, 2);
- }
-
-- /* Configure special DP tx tunings */
-- if (cfg->type == PHY_TYPE_DP)
-- cfg->configure_dp_tx(qphy);
--
- qcom_qmp_phy_usb_configure_lane(rx, cfg->regs,
- cfg->rx_tbl, cfg->rx_tbl_num, 1);
- if (cfg->rx_tbl_sec)
-@@ -2389,14 +2326,10 @@ static int qcom_qmp_phy_usb_power_on(struct phy *phy)
- }
-
- /* Configure link rate, swing, etc. */
-- if (cfg->type == PHY_TYPE_DP) {
-- cfg->configure_dp_phy(qphy);
-- } else {
-- qcom_qmp_phy_usb_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
-- if (cfg->pcs_tbl_sec)
-- qcom_qmp_phy_usb_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
-- cfg->pcs_tbl_num_sec);
-- }
-+ qcom_qmp_phy_usb_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
-+ if (cfg->pcs_tbl_sec)
-+ qcom_qmp_phy_usb_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
-+ cfg->pcs_tbl_num_sec);
-
- ret = reset_control_deassert(qmp->ufs_reset);
- if (ret)
-@@ -2408,40 +2341,26 @@ static int qcom_qmp_phy_usb_power_on(struct phy *phy)
- qcom_qmp_phy_usb_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
- cfg->pcs_misc_tbl_num_sec);
-
-- /*
-- * Pull out PHY from POWER DOWN state.
-- * This is active low enable signal to power-down PHY.
-- */
-- if(cfg->type == PHY_TYPE_PCIE)
-- qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
--
- if (cfg->has_pwrdn_delay)
- usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
-
-- if (cfg->type != PHY_TYPE_DP) {
-- /* Pull PHY out of reset state */
-- if (!cfg->no_pcs_sw_reset)
-- qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
-- /* start SerDes and Phy-Coding-Sublayer */
-- qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
--
-- if (cfg->type == PHY_TYPE_UFS) {
-- status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
-- mask = PCS_READY;
-- ready = PCS_READY;
-- } else {
-- status = pcs + cfg->regs[QPHY_PCS_STATUS];
-- mask = cfg->phy_status;
-- ready = 0;
-- }
-+ /* Pull PHY out of reset state */
-+ if (!cfg->no_pcs_sw_reset)
-+ qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
-+ /* start SerDes and Phy-Coding-Sublayer */
-+ qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
-
-- ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
-- PHY_INIT_COMPLETE_TIMEOUT);
-- if (ret) {
-- dev_err(qmp->dev, "phy initialization timed-out\n");
-- goto err_disable_pipe_clk;
-- }
-+ status = pcs + cfg->regs[QPHY_PCS_STATUS];
-+ mask = cfg->phy_status;
-+ ready = 0;
-+
-+ ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
-+ PHY_INIT_COMPLETE_TIMEOUT);
-+ if (ret) {
-+ dev_err(qmp->dev, "phy initialization timed-out\n");
-+ goto err_disable_pipe_clk;
- }
-+
- return 0;
-
- err_disable_pipe_clk:
-@@ -2460,25 +2379,20 @@ static int qcom_qmp_phy_usb_power_off(struct phy *phy)
-
- clk_disable_unprepare(qphy->pipe_clk);
-
-- if (cfg->type == PHY_TYPE_DP) {
-- /* Assert DP PHY power down */
-- writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
-- } else {
-- /* PHY reset */
-- if (!cfg->no_pcs_sw_reset)
-- qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
-+ /* PHY reset */
-+ if (!cfg->no_pcs_sw_reset)
-+ qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
-
-- /* stop SerDes and Phy-Coding-Sublayer */
-- qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
-+ /* stop SerDes and Phy-Coding-Sublayer */
-+ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
-
-- /* Put PHY into POWER DOWN state: active low */
-- if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
-- qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
-- cfg->pwrdn_ctrl);
-- } else {
-- qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
-- cfg->pwrdn_ctrl);
-- }
-+ /* Put PHY into POWER DOWN state: active low */
-+ if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
-+ qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
-+ cfg->pwrdn_ctrl);
-+ } else {
-+ qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
-+ cfg->pwrdn_ctrl);
- }
-
- return 0;
-@@ -2755,223 +2669,13 @@ static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
- return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
- }
-
--/*
-- * Display Port PLL driver block diagram for branch clocks
-- *
-- * +------------------------------+
-- * | DP_VCO_CLK |
-- * | |
-- * | +-------------------+ |
-- * | | (DP PLL/VCO) | |
-- * | +---------+---------+ |
-- * | v |
-- * | +----------+-----------+ |
-- * | | hsclk_divsel_clk_src | |
-- * | +----------+-----------+ |
-- * +------------------------------+
-- * |
-- * +---------<---------v------------>----------+
-- * | |
-- * +--------v----------------+ |
-- * | dp_phy_pll_link_clk | |
-- * | link_clk | |
-- * +--------+----------------+ |
-- * | |
-- * | |
-- * v v
-- * Input to DISPCC block |
-- * for link clk, crypto clk |
-- * and interface clock |
-- * |
-- * |
-- * +--------<------------+-----------------+---<---+
-- * | | |
-- * +----v---------+ +--------v-----+ +--------v------+
-- * | vco_divided | | vco_divided | | vco_divided |
-- * | _clk_src | | _clk_src | | _clk_src |
-- * | | | | | |
-- * |divsel_six | | divsel_two | | divsel_four |
-- * +-------+------+ +-----+--------+ +--------+------+
-- * | | |
-- * v---->----------v-------------<------v
-- * |
-- * +----------+-----------------+
-- * | dp_phy_pll_vco_div_clk |
-- * +---------+------------------+
-- * |
-- * v
-- * Input to DISPCC block
-- * for DP pixel clock
-- *
-- */
--static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw,
-- struct clk_rate_request *req)
--{
-- switch (req->rate) {
-- case 1620000000UL / 2:
-- case 2700000000UL / 2:
-- /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */
-- return 0;
-- default:
-- return -EINVAL;
-- }
--}
--
--static unsigned long
--qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
--{
-- const struct qmp_phy_dp_clks *dp_clks;
-- const struct qmp_phy *qphy;
-- const struct phy_configure_opts_dp *dp_opts;
--
-- dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw);
-- qphy = dp_clks->qphy;
-- dp_opts = &qphy->dp_opts;
--
-- switch (dp_opts->link_rate) {
-- case 1620:
-- return 1620000000UL / 2;
-- case 2700:
-- return 2700000000UL / 2;
-- case 5400:
-- return 5400000000UL / 4;
-- case 8100:
-- return 8100000000UL / 6;
-- default:
-- return 0;
-- }
--}
--
--static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = {
-- .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate,
-- .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate,
--};
--
--static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw,
-- struct clk_rate_request *req)
--{
-- switch (req->rate) {
-- case 162000000:
-- case 270000000:
-- case 540000000:
-- case 810000000:
-- return 0;
-- default:
-- return -EINVAL;
-- }
--}
--
--static unsigned long
--qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
--{
-- const struct qmp_phy_dp_clks *dp_clks;
-- const struct qmp_phy *qphy;
-- const struct phy_configure_opts_dp *dp_opts;
--
-- dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw);
-- qphy = dp_clks->qphy;
-- dp_opts = &qphy->dp_opts;
--
-- switch (dp_opts->link_rate) {
-- case 1620:
-- case 2700:
-- case 5400:
-- case 8100:
-- return dp_opts->link_rate * 100000;
-- default:
-- return 0;
-- }
--}
--
--static const struct clk_ops qcom_qmp_dp_link_clk_ops = {
-- .determine_rate = qcom_qmp_dp_link_clk_determine_rate,
-- .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate,
--};
--
--static struct clk_hw *
--qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data)
--{
-- struct qmp_phy_dp_clks *dp_clks = data;
-- unsigned int idx = clkspec->args[0];
--
-- if (idx >= 2) {
-- pr_err("%s: invalid index %u\n", __func__, idx);
-- return ERR_PTR(-EINVAL);
-- }
--
-- if (idx == 0)
-- return &dp_clks->dp_link_hw;
--
-- return &dp_clks->dp_pixel_hw;
--}
--
--static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy,
-- struct device_node *np)
--{
-- struct clk_init_data init = { };
-- struct qmp_phy_dp_clks *dp_clks;
-- char name[64];
-- int ret;
--
-- dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL);
-- if (!dp_clks)
-- return -ENOMEM;
--
-- dp_clks->qphy = qphy;
-- qphy->dp_clks = dp_clks;
--
-- snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev));
-- init.ops = &qcom_qmp_dp_link_clk_ops;
-- init.name = name;
-- dp_clks->dp_link_hw.init = &init;
-- ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw);
-- if (ret)
-- return ret;
--
-- snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev));
-- init.ops = &qcom_qmp_dp_pixel_clk_ops;
-- init.name = name;
-- dp_clks->dp_pixel_hw.init = &init;
-- ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw);
-- if (ret)
-- return ret;
--
-- ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks);
-- if (ret)
-- return ret;
--
-- /*
-- * Roll a devm action because the clock provider is the child node, but
-- * the child node is not actually a device.
-- */
-- return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
--}
--
--static const struct phy_ops qcom_qmp_phy_usb_gen_ops = {
-+static const struct phy_ops qcom_qmp_phy_usb_ops = {
- .init = qcom_qmp_phy_usb_enable,
- .exit = qcom_qmp_phy_usb_disable,
- .set_mode = qcom_qmp_phy_usb_set_mode,
- .owner = THIS_MODULE,
- };
-
--static const struct phy_ops qcom_qmp_phy_usb_dp_ops = {
-- .init = qcom_qmp_phy_usb_init,
-- .configure = qcom_qmp_dp_phy_configure,
-- .power_on = qcom_qmp_phy_usb_power_on,
-- .calibrate = qcom_qmp_dp_phy_calibrate,
-- .power_off = qcom_qmp_phy_usb_power_off,
-- .exit = qcom_qmp_phy_usb_exit,
-- .set_mode = qcom_qmp_phy_usb_set_mode,
-- .owner = THIS_MODULE,
--};
--
--static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
-- .power_on = qcom_qmp_phy_usb_enable,
-- .power_off = qcom_qmp_phy_usb_disable,
-- .set_mode = qcom_qmp_phy_usb_set_mode,
-- .owner = THIS_MODULE,
--};
--
- static void qcom_qmp_reset_control_put(void *data)
- {
- reset_control_put(data);
-@@ -2984,7 +2688,6 @@ int qcom_qmp_phy_usb_create(struct device *dev, struct device_node *np, int id,
- struct qcom_qmp *qmp = dev_get_drvdata(dev);
- struct phy *generic_phy;
- struct qmp_phy *qphy;
-- const struct phy_ops *ops;
- char prop_name[MAX_PROP_NAME];
- int ret;
-
-@@ -3051,16 +2754,12 @@ int qcom_qmp_phy_usb_create(struct device *dev, struct device_node *np, int id,
- snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
- qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name);
- if (IS_ERR(qphy->pipe_clk)) {
-- if (cfg->type == PHY_TYPE_PCIE ||
-- cfg->type == PHY_TYPE_USB3) {
-- ret = PTR_ERR(qphy->pipe_clk);
-- if (ret != -EPROBE_DEFER)
-- dev_err(dev,
-- "failed to get lane%d pipe_clk, %d\n",
-- id, ret);
-- return ret;
-- }
-- qphy->pipe_clk = NULL;
-+ ret = PTR_ERR(qphy->pipe_clk);
-+ if (ret != -EPROBE_DEFER)
-+ dev_err(dev,
-+ "failed to get lane%d pipe_clk, %d\n",
-+ id, ret);
-+ return ret;
- }
-
- /* Get lane reset, if any */
-@@ -3077,14 +2776,7 @@ int qcom_qmp_phy_usb_create(struct device *dev, struct device_node *np, int id,
- return ret;
- }
-
-- if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE)
-- ops = &qcom_qmp_pcie_ufs_ops;
-- else if (cfg->type == PHY_TYPE_DP)
-- ops = &qcom_qmp_phy_usb_dp_ops;
-- else
-- ops = &qcom_qmp_phy_usb_gen_ops;
--
-- generic_phy = devm_phy_create(dev, np, ops);
-+ generic_phy = devm_phy_create(dev, np, &qcom_qmp_phy_usb_ops);
- if (IS_ERR(generic_phy)) {
- ret = PTR_ERR(generic_phy);
- dev_err(dev, "failed to create qphy %d\n", ret);
-@@ -3172,12 +2864,7 @@ static int qcom_qmp_phy_usb_probe(struct platform_device *pdev)
- struct device_node *child;
- struct phy_provider *phy_provider;
- void __iomem *serdes;
-- void __iomem *usb_serdes;
-- void __iomem *dp_serdes = NULL;
-- const struct qmp_phy_combo_cfg *combo_cfg = NULL;
- const struct qmp_phy_cfg *cfg = NULL;
-- const struct qmp_phy_cfg *usb_cfg = NULL;
-- const struct qmp_phy_cfg *dp_cfg = NULL;
- int num, id, expected_phys;
- int ret;
-
-@@ -3194,28 +2881,18 @@ static int qcom_qmp_phy_usb_probe(struct platform_device *pdev)
- return -EINVAL;
-
- /* per PHY serdes; usually located at base address */
-- usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0);
-+ serdes = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(serdes))
- return PTR_ERR(serdes);
-
- /* per PHY dp_com; if PHY has dp_com control block */
-- if (combo_cfg || cfg->has_phy_dp_com_ctrl) {
-+ if (cfg->has_phy_dp_com_ctrl) {
- qmp->dp_com = devm_platform_ioremap_resource(pdev, 1);
- if (IS_ERR(qmp->dp_com))
- return PTR_ERR(qmp->dp_com);
- }
-
-- if (combo_cfg) {
-- /* Only two serdes for combo PHY */
-- dp_serdes = devm_platform_ioremap_resource(pdev, 2);
-- if (IS_ERR(dp_serdes))
-- return PTR_ERR(dp_serdes);
--
-- dp_cfg = combo_cfg->dp_cfg;
-- expected_phys = 2;
-- } else {
-- expected_phys = cfg->nlanes;
-- }
-+ expected_phys = cfg->nlanes;
-
- mutex_init(&qmp->phy_mutex);
-
-@@ -3256,14 +2933,6 @@ static int qcom_qmp_phy_usb_probe(struct platform_device *pdev)
-
- id = 0;
- for_each_available_child_of_node(dev->of_node, child) {
-- if (of_node_name_eq(child, "dp-phy")) {
-- cfg = dp_cfg;
-- serdes = dp_serdes;
-- } else if (of_node_name_eq(child, "usb3-phy")) {
-- cfg = usb_cfg;
-- serdes = usb_serdes;
-- }
--
- /* Create per-lane phy */
- ret = qcom_qmp_phy_usb_create(dev, child, id, serdes, cfg);
- if (ret) {
-@@ -3276,21 +2945,13 @@ static int qcom_qmp_phy_usb_probe(struct platform_device *pdev)
- * Register the pipe clock provided by phy.
- * See function description to see details of this pipe clock.
- */
-- if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) {
-- ret = phy_pipe_clk_register(qmp, child);
-- if (ret) {
-- dev_err(qmp->dev,
-- "failed to register pipe clock source\n");
-- goto err_node_put;
-- }
-- } else if (cfg->type == PHY_TYPE_DP) {
-- ret = phy_dp_clks_register(qmp, qmp->phys[id], child);
-- if (ret) {
-- dev_err(qmp->dev,
-- "failed to register DP clock source\n");
-- goto err_node_put;
-- }
-+ ret = phy_pipe_clk_register(qmp, child);
-+ if (ret) {
-+ dev_err(qmp->dev,
-+ "failed to register pipe clock source\n");
-+ goto err_node_put;
- }
-+
- id++;
- }
-
---
-2.35.1
-
clk-qcom-sm6115-select-qcom_gdsc.patch
scsi-nvme-fc-add-new-routine-nvme_fc_io_getuuid.patch
mtd-devices-docg3-check-the-return-value-of-devm_ior.patch
-phy-qcom-qmp-create-copies-of-qmp-phy-driver.patch
-phy-qcom-qmp-usb-disable-runtime-pm-on-unbind.patch
-phy-qcom-qmp-pcie-split-pcs_misc-region-for-ipq6018-.patch
-phy-qcom-qmp-pcie-msm8996-drop-all-compatibles-excep.patch
-phy-qcom-qmp-pcie-change-symbol-prefix-to-qcom_qmp_p.patch
-phy-qcom-qmp-pcie-msm8996-drop-support-for-non-pcie-.patch
-phy-qcom-qmp-pcie-msm8996-cleanup-the-driver.patch
-phy-qcom-qmp-usb-drop-all-non-usb-compatibles-suppor.patch
-phy-qcom-qmp-usb-change-symbol-prefix-to-qcom_qmp_ph.patch
-phy-qcom-qmp-usb-drop-support-for-non-usb-phy-types.patch
-phy-qcom-qmp-usb-cleanup-the-driver.patch
-phy-qcom-qmp-usb-clean-up-pipe-clock-handling.patch
phy-amlogic-phy-meson-axg-mipi-pcie-analog-hold-refe.patch
phy-phy-mtk-tphy-fix-the-phy-type-setting-issue.patch
mtd-rawnand-intel-read-the-chip-select-line-from-the.patch
revert-net-ieee802154-reject-zero-sized-raw_sendmsg.patch
net-ieee802154-don-t-warn-zero-sized-raw_sendmsg.patch
drm-amd-display-fix-build-breakage-with-config_debug_fs-n.patch
-phy-qcom-qmp-fix-msm8996-pcie-phy-support.patch
clk-fix-pointer-casting-to-prevent-oops-in-devm_clk_release.patch
net-wwan-t7xx-use-gfp_atomic-under-spin-lock-in-t7xx_cldma_gpd_set_next_ptr.patch
kconfig.debug-simplify-the-dependency-of-debug_info_dwarf4-5.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
