--- /dev/null
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).a
+
+COBJS-y = interrupts.o
+COBJS-$(CONFIG_DRAGONFIRE) += df_board.o
+
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
+
+all: $(obj).depend $(START) $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \
+ -msoft-float
+
+# Make ARMv5 to allow more compilers to work, even though its v6.
+PLATFORM_CPPFLAGS += -march=armv5t
+# =========================================================================
+#
+# Supply options according to compiler version
+#
+# =========================================================================
+#PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
+PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
--- /dev/null
+/*
+ * Originates from Samsung's u-boot 1.1.6 port to S3C6400 / SMDK6400
+ *
+ * Copyright (C) 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+/#include <s3c6400.h>
+
+/ .globl mem_ctrl_asm_init
+/ mem_ctrl_asm_init:
+/ /* Memory subsystem address 0x7e00f120 */
+/ ldr r0, =ELFIN_MEM_SYS_CFG
+
+/ /* Xm0CSn2 = NFCON CS0, Xm0CSn3 = NFCON CS1 */
+/ mov r1, #0xd
+/ str r1, [r0]
+
+/ /* DMC1 base address 0x7e001000 */
+/ ldr r0, =ELFIN_DMC1_BASE
+
+/ ldr r1, =0x4
+/ str r1, [r0, #INDEX_DMC_MEMC_CMD]
+
+/ ldr r1, =DMC_DDR_REFRESH_PRD
+/ str r1, [r0, #INDEX_DMC_REFRESH_PRD]
+
+/ ldr r1, =DMC_DDR_CAS_LATENCY
+/ str r1, [r0, #INDEX_DMC_CAS_LATENCY]
+
+/ ldr r1, =DMC_DDR_t_DQSS
+/ str r1, [r0, #INDEX_DMC_T_DQSS]
+
+/ ldr r1, =DMC_DDR_t_MRD
+/ str r1, [r0, #INDEX_DMC_T_MRD]
+
+/ ldr r1, =DMC_DDR_t_RAS
+/ str r1, [r0, #INDEX_DMC_T_RAS]
+
+/ ldr r1, =DMC_DDR_t_RC
+/ str r1, [r0, #INDEX_DMC_T_RC]
+
+/ ldr r1, =DMC_DDR_t_RCD
+/ ldr r2, =DMC_DDR_schedule_RCD
+/ orr r1, r1, r2
+/ str r1, [r0, #INDEX_DMC_T_RCD]
+
+/ ldr r1, =DMC_DDR_t_RFC
+/ ldr r2, =DMC_DDR_schedule_RFC
+/ orr r1, r1, r2
+/ str r1, [r0, #INDEX_DMC_T_RFC]
+
+/ ldr r1, =DMC_DDR_t_RP
+/ ldr r2, =DMC_DDR_schedule_RP
+/ orr r1, r1, r2
+/ str r1, [r0, #INDEX_DMC_T_RP]
+
+/ ldr r1, =DMC_DDR_t_RRD
+/ str r1, [r0, #INDEX_DMC_T_RRD]
+
+/ ldr r1, =DMC_DDR_t_WR
+/ str r1, [r0, #INDEX_DMC_T_WR]
+
+/ ldr r1, =DMC_DDR_t_WTR
+/ str r1, [r0, #INDEX_DMC_T_WTR]
+
+/ ldr r1, =DMC_DDR_t_XP
+/ str r1, [r0, #INDEX_DMC_T_XP]
+
+/ ldr r1, =DMC_DDR_t_XSR
+/ str r1, [r0, #INDEX_DMC_T_XSR]
+
+/ ldr r1, =DMC_DDR_t_ESR
+/ str r1, [r0, #INDEX_DMC_T_ESR]
+
+/ ldr r1, =DMC1_MEM_CFG
+/ str r1, [r0, #INDEX_DMC_MEMORY_CFG]
+
+/ ldr r1, =DMC1_MEM_CFG2
+/ str r1, [r0, #INDEX_DMC_MEMORY_CFG2]
+
+/ ldr r1, =DMC1_CHIP0_CFG
+/ str r1, [r0, #INDEX_DMC_CHIP_0_CFG]
+
+/ ldr r1, =DMC_DDR_32_CFG
+/ str r1, [r0, #INDEX_DMC_USER_CONFIG]
+
+/ /* DMC0 DDR Chip 0 configuration direct command reg */
+/ ldr r1, =DMC_NOP0
+/ str r1, [r0, #INDEX_DMC_DIRECT_CMD]
+
+/ /* Precharge All */
+/ ldr r1, =DMC_PA0
+/ str r1, [r0, #INDEX_DMC_DIRECT_CMD]
+
+/ /* Auto Refresh 2 time */
+/ ldr r1, =DMC_AR0
+/ str r1, [r0, #INDEX_DMC_DIRECT_CMD]
+/ str r1, [r0, #INDEX_DMC_DIRECT_CMD]
+
+/ /* MRS */
+/ ldr r1, =DMC_mDDR_EMR0
+/ str r1, [r0, #INDEX_DMC_DIRECT_CMD]
+
+/ /* Mode Reg */
+/ ldr r1, =DMC_mDDR_MR0
+/ str r1, [r0, #INDEX_DMC_DIRECT_CMD]
+
+/ /* Enable DMC1 */
+/ mov r1, #0x0
+/ str r1, [r0, #INDEX_DMC_MEMC_CMD]
+
+/ check_dmc1_ready:
+/ ldr r1, [r0, #INDEX_DMC_MEMC_STATUS]
+/ mov r2, #0x3
+/ and r1, r1, r2
+/ cmp r1, #0x1
+/ bne check_dmc1_ready
+/ nop
+
+/ mov pc, lr
+
+/ .ltorg
--- /dev/null
+/*
+ * Just to satisfy init routines..
+ */
+
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ interrupt_init();
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/*
+ * OK, and resets too.
+ */
+void reset_cpu(ulong addr)
+{
+ puts("Warning: this reset doesn't work.");
+ /* hah. */
+ goto *((void*)0x0);
+}
+
+void do_reset(void)
+{
+ reset_cpu(0);
+ goto *((void*)0x0); /* call optimized out? */
+}
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * Texas Instruments <www.ti.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002-2004
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * (C) Copyright 2004
+ * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
+ *
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+ *
+ * And thoroughly mangled into dragonfire form, probably never to escape Xilinx.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/proc-armv/ptrace.h>
+#include <div64.h>
+
+#include <asm/arch/ttc.h>
+
+static ulong timer_load_val;
+
+#define PRESCALER 167
+
+/* read the 16 bit timer */
+static inline ulong read_timer(void)
+{
+ return xdfttc_readl(COUNT_VALUE);
+}
+
+/* Internal tick units */
+/* Last decremneter snapshot */
+static unsigned long lastdec;
+/* Monotonic incrementing timer */
+static unsigned long long timestamp;
+
+int interrupt_init(void)
+{
+/* s3c64xx_timers *const timers = s3c64xx_get_base_timers(); */
+
+/* /\* use PWM Timer 4 because it has no output *\/ */
+/* /\* */
+/* * We use the following scheme for the timer: */
+/* * Prescaler is hard fixed at 167, divider at 1/4. */
+/* * This gives at PCLK frequency 66MHz approx. 10us ticks */
+/* * The timer is set to wrap after 100s, at 66MHz this obviously */
+/* * happens after 10,000,000 ticks. A long variable can thus */
+/* * keep values up to 40,000s, i.e., 11 hours. This should be */
+/* * enough for most uses:-) Possible optimizations: select a */
+/* * binary-friendly frequency, e.g., 1ms / 128. Also calculate */
+/* * the prescaler automatically for other PCLK frequencies. */
+/* *\/ */
+/* timers->TCFG0 = PRESCALER << 8; */
+/* if (timer_load_val == 0) { */
+/* timer_load_val = get_PCLK() / PRESCALER * (100 / 4); /\* 100s *\/ */
+/* timers->TCFG1 = (timers->TCFG1 & ~0xf0000) | 0x20000; */
+/* } */
+
+/* /\* load value for 10 ms timeout *\/ */
+/* lastdec = timers->TCNTB4 = timer_load_val; */
+/* /\* auto load, manual update of Timer 4 *\/ */
+/* timers->TCON = (timers->TCON & ~0x00700000) | TCON_4_AUTO | */
+/* TCON_4_UPDATE; */
+
+/* /\* auto load, start Timer 4 *\/ */
+/* timers->TCON = (timers->TCON & ~0x00700000) | TCON_4_AUTO | COUNT_4_ON; */
+/* timestamp = 0; */
+
+ /* complete garbage. */
+ timer_load_val = 0x800000;
+ lastdec = 0x100;
+
+ return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+ ulong now = read_timer();
+
+ if (lastdec >= now) {
+ /* normal mode */
+ timestamp += lastdec - now;
+ } else {
+ /* we have an overflow ... */
+ timestamp += lastdec + timer_load_val - now;
+ }
+ lastdec = now;
+
+ return timestamp;
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+ /* We overrun in 100s */
+ return (ulong)(timer_load_val / 100);
+}
+
+void reset_timer_masked(void)
+{
+ /* reset time */
+ lastdec = read_timer();
+ timestamp = 0;
+}
+
+void reset_timer(void)
+{
+ reset_timer_masked();
+}
+
+ulong get_timer_masked(void)
+{
+ unsigned long long res = get_ticks();
+ do_div (res, (timer_load_val / (100 * CONFIG_SYS_HZ)));
+ return res;
+}
+
+ulong get_timer(ulong base)
+{
+ return get_timer_masked() - base;
+}
+
+void set_timer(ulong t)
+{
+ timestamp = t * (timer_load_val / (100 * CONFIG_SYS_HZ));
+}
+
+void udelay(unsigned long usec)
+{
+ unsigned long long tmp;
+ ulong tmo;
+
+ tmo = (usec + 9) / 10;
+ tmp = get_ticks() + tmo; /* get current timestamp */
+
+ while (get_ticks() < tmp)/* loop till event */
+ /*NOP*/;
+}
--- /dev/null
+/*
+ * Derived from ep3_1 drivers/ttc_v1_00_a/src/xttcepb_l.h
+ * as of svn rev 1377.
+ */
+
+#ifndef __TTC_H__
+#define __TTC_H__
+
+#include <asm/io.h>
+
+#if defined(CONFIG_TTC0)
+# define TTC_ID 0
+# define TTC_BASE XPSS_TTC0_BASE
+#elif defined(CONFIG_TTC1)
+# define TTC_ID 1
+# define TTC_BASE XPSS_TTC1_BASE
+#else
+# error "Need to configure a TTC (0 or 1)"
+#endif
+
+/* Register offsets */
+#define XDF_TTC_CLK_CNTRL_OFFSET 0x00000000 /* Clock Control Register */
+#define XDF_TTC_CNT_CNTRL_OFFSET 0x0000000C /* Counter Control Register*/
+#define XDF_TTC_COUNT_VALUE_OFFSET 0x00000018 /* Current Counter Value */
+#define XDF_TTC_INTERVAL_VAL_OFFSET 0x00000024 /* Interval Count Value */
+#define XDF_TTC_MATCH_0_OFFSET 0x00000030 /* Match 1 value */
+#define XDF_TTC_MATCH_1_OFFSET 0x0000003C /* Match 2 value */
+#define XDF_TTC_MATCH_2_OFFSET 0x00000048 /* Match 3 value */
+#define XDF_TTC_ISR_OFFSET 0x00000054 /* Interrupt Status Register */
+#define XDF_TTC_IER_OFFSET 0x00000060 /* Interrupt Enable Register */
+
+/* Clock Control Register */
+#define XDF_TTC_CLK_CNTRL_PS_EN_MASK 0x00000001 /* Prescale enable */
+#define XDF_TTC_CLK_CNTRL_PS_VAL_MASK 0x0000001E /* Prescale value */
+#define XDF_TTC_CLK_CNTRL_PS_VAL_SHIFT 1 /* Prescale shift */
+#define XDF_TTC_CLK_CNTRL_PS_DISABLE 16 /* Prescale disable */
+#define XDF_TTC_CLK_CNTRL_SRC_MASK 0x00000020 /* Clock source */
+#define XDF_TTC_CLK_CNTRL_EXT_EDGE_MASK 0x00000040 /* External Clock edge */
+
+/* Counter Control Register */
+#define XDF_TTC_CNT_CNTRL_DIS_MASK 0x00000001 /* Disable the counter */
+#define XDF_TTC_CNT_CNTRL_INT_MASK 0x00000002 /* Interval mode */
+#define XDF_TTC_CNT_CNTRL_DECR_MASK 0x00000004 /* Decriment mode */
+#define XDF_TTC_CNT_CNTRL_MATCH_MASK 0x00000008 /* Match mode */
+#define XDF_TTC_CNT_CNTRL_RST_MASK 0x00000010 /* Reset counter */
+#define XDF_TTC_CNT_CNTRL_EN_WAVE_MASK 0x00000020 /* Enable waveform */
+#define XDF_TTC_CNT_CNTRL_POL_WAVE_MASK 0x00000040 /* Waveform polarity */
+#define XDF_TTC_CNT_CNTRL_RESET_VALUE 0x00000021 /* Reset value */
+
+/* Current Counter Value Register */
+#define XDF_TTC_COUNT_VALUE_MASK 0x0000FFFF /* 16-bit counter value */
+
+/* Interval Value Register */
+#define XDF_TTC_INTERVAL_VAL_MASK 0x0000FFFF /* 16-bit Interval value*/
+
+/* Match Registers */
+#define XDF_TTC_MATCH_MASK 0x0000FFFF /* 16-bit Match value */
+#define XDF_TTC_NUM_MATCH_REG 3
+
+/* Interrupt Registers */
+#define XDF_TTC_IXR_INTERVAL_MASK 0x00000001 /* Interval Interrupt */
+#define XDF_TTC_IXR_MATCH_0_MASK 0x00000002 /* Match 1 Interrupt */
+#define XDF_TTC_IXR_MATCH_1_MASK 0x00000004 /* Match 2 Interrupt */
+#define XDF_TTC_IXR_MATCH_2_MASK 0x00000008 /* Match 3 Interrupt */
+#define XDF_TTC_IXR_CNT_OVR_MASK 0x00000010 /* Counter Overflow */
+#define XDF_TTC_IXR_ALL_MASK 0x0000001F /* All valide Interrupts */
+
+/* Access macros */
+#define xdfttc_readl(reg) \
+ readl((void*)TTC_BASE + XDF_TTC_##reg##_OFFSET)
+#define xdfttc_writel(reg,value) \
+ writel((value),(void*)TTC_BASE + XDF_TTC_##reg##_OFFSET)
+
+#endif /* __TTC_H__ */
--- /dev/null
+/*
+ * Derived from ep3_1 drivers/ttc_v1_00_a/src/xttcepb_l.h
+ * as of svn rev 1377.
+ */
+
+#ifndef __TTC_H__
+#define __TTC_H__
+
+#include <asm/io.h>
+
+#include <dragonfire.h>
+
+#if defined(CONFIG_TTC0)
+# define TTC_ID 0
+# define TTC_BASE DRAGONFIRE_TTC0_BASE
+#elif defined(CONFIG_TTC1)
+# define TTC_ID 1
+# define TTC_BASE DRAGONFIRE_TTC1_BASE
+#else
+# error "Need to configure a TTC (0 or 1)"
+#endif
+
+/* Register offsets */
+#define XDF_TTC_CLK_CNTRL_OFFSET 0x00000000 /* Clock Control Register */
+#define XDF_TTC_CNT_CNTRL_OFFSET 0x0000000C /* Counter Control Register*/
+#define XDF_TTC_COUNT_VALUE_OFFSET 0x00000018 /* Current Counter Value */
+#define XDF_TTC_INTERVAL_VAL_OFFSET 0x00000024 /* Interval Count Value */
+#define XDF_TTC_MATCH_0_OFFSET 0x00000030 /* Match 1 value */
+#define XDF_TTC_MATCH_1_OFFSET 0x0000003C /* Match 2 value */
+#define XDF_TTC_MATCH_2_OFFSET 0x00000048 /* Match 3 value */
+#define XDF_TTC_ISR_OFFSET 0x00000054 /* Interrupt Status Register */
+#define XDF_TTC_IER_OFFSET 0x00000060 /* Interrupt Enable Register */
+
+/* Clock Control Register */
+#define XDF_TTC_CLK_CNTRL_PS_EN_MASK 0x00000001 /* Prescale enable */
+#define XDF_TTC_CLK_CNTRL_PS_VAL_MASK 0x0000001E /* Prescale value */
+#define XDF_TTC_CLK_CNTRL_PS_VAL_SHIFT 1 /* Prescale shift */
+#define XDF_TTC_CLK_CNTRL_PS_DISABLE 16 /* Prescale disable */
+#define XDF_TTC_CLK_CNTRL_SRC_MASK 0x00000020 /* Clock source */
+#define XDF_TTC_CLK_CNTRL_EXT_EDGE_MASK 0x00000040 /* External Clock edge */
+
+/* Counter Control Register */
+#define XDF_TTC_CNT_CNTRL_DIS_MASK 0x00000001 /* Disable the counter */
+#define XDF_TTC_CNT_CNTRL_INT_MASK 0x00000002 /* Interval mode */
+#define XDF_TTC_CNT_CNTRL_DECR_MASK 0x00000004 /* Decriment mode */
+#define XDF_TTC_CNT_CNTRL_MATCH_MASK 0x00000008 /* Match mode */
+#define XDF_TTC_CNT_CNTRL_RST_MASK 0x00000010 /* Reset counter */
+#define XDF_TTC_CNT_CNTRL_EN_WAVE_MASK 0x00000020 /* Enable waveform */
+#define XDF_TTC_CNT_CNTRL_POL_WAVE_MASK 0x00000040 /* Waveform polarity */
+#define XDF_TTC_CNT_CNTRL_RESET_VALUE 0x00000021 /* Reset value */
+
+/* Current Counter Value Register */
+#define XDF_TTC_COUNT_VALUE_MASK 0x0000FFFF /* 16-bit counter value */
+
+/* Interval Value Register */
+#define XDF_TTC_INTERVAL_VAL_MASK 0x0000FFFF /* 16-bit Interval value*/
+
+/* Match Registers */
+#define XDF_TTC_MATCH_MASK 0x0000FFFF /* 16-bit Match value */
+#define XDF_TTC_NUM_MATCH_REG 3
+
+/* Interrupt Registers */
+#define XDF_TTC_IXR_INTERVAL_MASK 0x00000001 /* Interval Interrupt */
+#define XDF_TTC_IXR_MATCH_0_MASK 0x00000002 /* Match 1 Interrupt */
+#define XDF_TTC_IXR_MATCH_1_MASK 0x00000004 /* Match 2 Interrupt */
+#define XDF_TTC_IXR_MATCH_2_MASK 0x00000008 /* Match 3 Interrupt */
+#define XDF_TTC_IXR_CNT_OVR_MASK 0x00000010 /* Counter Overflow */
+#define XDF_TTC_IXR_ALL_MASK 0x0000001F /* All valide Interrupts */
+
+/* Access macros */
+#define xdfttc_readl(reg) \
+ readl((void*)TTC_BASE + XDF_TTC_##reg##_OFFSET)
+#define xdfttc_writel(reg,value) \
+ writel((value),(void*)TTC_BASE + XDF_TTC_##reg##_OFFSET)
+
+#endif /* __TTC_H__ */
--- /dev/null
+/*
+ * Hacked together,
+ * hopefully functional.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_ARM1176 1 /* CPU */
+#define CONFIG_XDF 1 /* Board */
+#define CONFIG_DFE 1 /* Board sub-type ("flavor"?) */
+#define CONFIG_DRAGONFIRE 1 /* SoC? */
+
+//#define CONFIG_BAUDRATE 38400
+#define CONFIG_BAUDRATE 9600
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 38400, 115200 }
+#define CONFIG_BOOTDELAY -1 /* Disable autoboot */
+
+#define CONFIG_PSS_SERIAL
+#define CONFIG_RTC_XPSSRTC
+
+#include <config_cmd_default.h> /* FIXME: check this! */
+#define CONFIG_CMD_DATE /* RTC? */
+#define CONFIG_CMD_PING /* Might be useful for debugging */
+#define CONFIG_CMD_SAVEENV /* Command to save ENV to Flash */
+#define CONFIG_REGINFO /* Again, debugging */
+#undef CONFIG_CMD_SETGETDCR /* README says 4xx only */
+
+#define CONFIG_TIMESTAMP /* print image timestamp on bootm, etc */
+
+/* IPADDR, SERVERIP */
+/* Need I2C for RTC? */
+
+#define CONFIG_IDENT_STRING "\nXilinx Pele Emulaton Platform"
+#define CONFIG_PANIC_HANG 1 /* For development/debugging */
+
+#define CONFIG_AUTO_COMPLETE 1
+#define CONFIG_CMDLINE_EDITING 1
+
+#define CONFIG_SYS_PROMPT "pele-boot> "
+
+/* CONFIG_SYS_TFTP_LOADADDR? */
+
+#define CONFIG_SYS_RAM_BOOT_ADDR 0x04000000
+#define CONFIG_SYS_FLASH_BOOT_ADDR 0xE2010000
+
+#undef CONFIG_SKIP_RELOCATE_UBOOT
+
+/* Uncomment it if you don't want Flash */
+//#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_SYS_SDRAM_BASE 0
+
+#define CONFIG_L2_OFF
+#define PELE_TTC
+//#define DEBUG 1
+
+//#define CONFIG_PELE_INIT_GEM //this is to initialize GEM at uboot start
+#define CONFIG_PELE_IP_ENV //this is to set ipaddr, ethaddr and serverip env variables.
+#define CONFIG_PELE_FLASH_RELOCATE
+
+#ifndef CONFIG_SYS_NO_FLASH
+
+/* FLASH organization */
+#define CONFIG_SYS_FLASH_BASE 0xE2000000
+#define CONFIG_SYS_FLASH_SIZE (16*1024*1024) /* i.e. 16MB */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors/blocks on one chip */
+#define CONFIG_SYS_FLASH_ERASE_TOUT 1000
+
+#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00000000)
+#define CONFIG_ENV_SECT_SIZE 0x10000 /*64 KB*/
+#define CONFIG_ENV_IS_NOWHERE 1
+//#define CONFIG_ENV_IS_IN_FLASH 1
+
+#else
+
+#define CONFIG_ENV_IS_NOWHERE 1
+
+#endif
+
+/*
+#define CONFIG_SYS_FLASH_BASE 0xE2000000
+#define CONFIG_SYS_FLASH_SIZE (32*1024*1024)
+#define CONFIG_SYS_MAX_FLASH_SECT 16
+#define CONFIG_SYS_FLASH_CFI 1
+#define CONFIG_SYS_FLASH_EMPTY_INFO 1
+#define CONFIG_SYS_MAX_FLASH_BANKS 2
+#define CONFIG_SYS_FLASH_PROTECTION 1
+*/
+//#define CONFIG_FLASH_CFI_DRIVER 1
+/* CONFIG_SYS_MONITOR_BASE? */
+/* CONFIG_SYS_MONITOR_LEN? */
+
+#define CONFIG_SYS_CACHELINE_SIZE 32 /* Assuming bytes? */
+
+/* CONFIG_SYS_INIT_RAM_ADDR? */
+/* CONFIG_SYS_GLOBAL_DATA_OFFSET? */
+
+/* Because (at least at first) we're going to be loaded via JTAG_Tcl */
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+
+/* HW to use */
+#define CONFIG_XDF_UART 1
+#define CONFIG_XDF_ETH 1
+#define CONFIG_XDF_RTC 1
+#define CONFIG_UART0 1
+#define CONFIG_TTC0 1
+#define CONFIG_GEM0 1
+
+/* Guessing here...no idea what the "multiplier" is supposed to be */
+#define CONFIG_SYS_HZ 50
+/* And here... */
+#define CONFIG_SYS_LOAD_ADDR 0 /* default? */
+/* Semi-educated guess based on p.48 of DF Arch spec */
+#define PHYS_SDRAM_1 (256 * 1024)
+#define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024) /* Cameron guessed 256 or 512 MB */
+
+#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000)
+
+/*
+ * These were lifted straight from imx31_phycore, and may well be very wrong.
+ */
+//#define CONFIG_ENV_SIZE 4096
+#define CONFIG_ENV_SIZE 0x10000
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_MALLOC_LEN 0x21000
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* phycore */
+
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * Semi-blindly hacked together.
+ */
+
+#ifndef __DRAGONFIRE_H__
+#define __DRAGONFIRE_H__
+
+/* UART base addresses */
+#define DRAGONFIRE_UART0_BASE 0xE0000000
+#define DRAGONFIRE_UART1_BASE 0xE0001000
+
+#ifdef PELE_TTC
+ /* For PELE the base address has changed*/
+ #define DRAGONFIRE_TTC0_BASE 0x90001000
+ #define DRAGONFIRE_TTC1_BASE 0x90002000
+
+#else
+
+ /* Timers forf DFE */
+ #define DRAGONFIRE_TTC0_BASE 0xFE001000
+ #define DRAGONFIRE_TTC1_BASE 0xFE002000
+#endif
+
+/* GEMs */
+#define DRAGONFIRE_GEM0_BASE 0xE000B000
+#define DRAGONFIRE_GEM1_BASE 0xE000C000
+
+#endif /* __DRAGONFIRE_H__ */
projects / thirdparty / u-boot.git / commitdiff
