--- /dev/null
+From 0eb0511d176534674600a1986c3c766756288908 Mon Sep 17 00:00:00 2001
+From: Russell King <rmk+kernel@arm.linux.org.uk>
+Date: Mon, 22 Nov 2010 12:06:28 +0000
+Subject: ARM: SMP: use more sane register allocation for __fixup_smp_on_up
+
+From: Russell King <rmk+kernel@arm.linux.org.uk>
+
+commit 0eb0511d176534674600a1986c3c766756288908 upstream.
+
+Use r0,r3-r6 rather than r0,r3,r4,r6,r7, which makes it easier to
+understand which registers can be modified. Also document which
+registers hold values which must be preserved.
+
+Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+
+---
+ arch/arm/kernel/head.S | 39 ++++++++++++++++++++++-----------------
+ 1 file changed, 22 insertions(+), 17 deletions(-)
+
+--- a/arch/arm/kernel/head.S
++++ b/arch/arm/kernel/head.S
+@@ -91,6 +91,11 @@ ENTRY(stext)
+ movs r8, r5 @ invalid machine (r5=0)?
+ THUMB( it eq ) @ force fixup-able long branch encoding
+ beq __error_a @ yes, error 'a'
++
++ /*
++ * r1 = machine no, r2 = atags,
++ * r8 = machinfo, r9 = cpuid, r10 = procinfo
++ */
+ bl __vet_atags
+ #ifdef CONFIG_SMP_ON_UP
+ bl __fixup_smp
+@@ -387,19 +392,19 @@ ENDPROC(__turn_mmu_on)
+
+ #ifdef CONFIG_SMP_ON_UP
+ __fixup_smp:
+- mov r7, #0x00070000
+- orr r6, r7, #0xff000000 @ mask 0xff070000
+- orr r7, r7, #0x41000000 @ val 0x41070000
+- and r0, r9, r6
+- teq r0, r7 @ ARM CPU and ARMv6/v7?
++ mov r4, #0x00070000
++ orr r3, r4, #0xff000000 @ mask 0xff070000
++ orr r4, r4, #0x41000000 @ val 0x41070000
++ and r0, r9, r3
++ teq r0, r4 @ ARM CPU and ARMv6/v7?
+ bne __fixup_smp_on_up @ no, assume UP
+
+- orr r6, r6, #0x0000ff00
+- orr r6, r6, #0x000000f0 @ mask 0xff07fff0
+- orr r7, r7, #0x0000b000
+- orr r7, r7, #0x00000020 @ val 0x4107b020
+- and r0, r9, r6
+- teq r0, r7 @ ARM 11MPCore?
++ orr r3, r3, #0x0000ff00
++ orr r3, r3, #0x000000f0 @ mask 0xff07fff0
++ orr r4, r4, #0x0000b000
++ orr r4, r4, #0x00000020 @ val 0x4107b020
++ and r0, r9, r3
++ teq r0, r4 @ ARM 11MPCore?
+ moveq pc, lr @ yes, assume SMP
+
+ mrc p15, 0, r0, c0, c0, 5 @ read MPIDR
+@@ -408,13 +413,13 @@ __fixup_smp:
+
+ __fixup_smp_on_up:
+ adr r0, 1f
+- ldmia r0, {r3, r6, r7}
++ ldmia r0, {r3 - r5}
+ sub r3, r0, r3
+- add r6, r6, r3
+- add r7, r7, r3
+-2: cmp r6, r7
+- ldmia r6!, {r0, r4}
+- strlo r4, [r0, r3]
++ add r4, r4, r3
++ add r5, r5, r3
++2: cmp r4, r5
++ ldmia r4!, {r0, r6}
++ strlo r6, [r0, r3]
+ blo 2b
+ mov pc, lr
+ ENDPROC(__fixup_smp)
--- /dev/null
+From e98ff0f55a0232b578c9aa7f1c245868277ac7bc Mon Sep 17 00:00:00 2001
+From: Russell King <rmk+kernel@arm.linux.org.uk>
+Date: Sun, 30 Jan 2011 16:40:20 +0000
+Subject: ARM: smp_on_up: allow non-ARM SMP processors
+
+From: Russell King <rmk+kernel@arm.linux.org.uk>
+
+commit e98ff0f55a0232b578c9aa7f1c245868277ac7bc upstream.
+
+Allow non-ARM SMP processors to use the SMP_ON_UP feature. CPUs
+supporting SMP must have the new CPU ID format, so check for this first.
+Then check for ARM11MPCore, which fails the MPIDR check. Lastly check
+the MPIDR reports multiprocessing extensions and that the CPU is part of
+a multiprocessing system.
+
+Reported-and-Tested-by: Stephen Boyd <sboyd@codeaurora.org>
+Acked-by: Will Deacon <will.deacon@arm.com>
+Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+
+---
+ arch/arm/kernel/head.S | 22 ++++++++++------------
+ 1 file changed, 10 insertions(+), 12 deletions(-)
+
+--- a/arch/arm/kernel/head.S
++++ b/arch/arm/kernel/head.S
+@@ -392,24 +392,22 @@ ENDPROC(__turn_mmu_on)
+
+ #ifdef CONFIG_SMP_ON_UP
+ __fixup_smp:
+- mov r4, #0x00070000
+- orr r3, r4, #0xff000000 @ mask 0xff070000
+- orr r4, r4, #0x41000000 @ val 0x41070000
+- and r0, r9, r3
+- teq r0, r4 @ ARM CPU and ARMv6/v7?
++ and r3, r9, #0x000f0000 @ architecture version
++ teq r3, #0x000f0000 @ CPU ID supported?
+ bne __fixup_smp_on_up @ no, assume UP
+
+- orr r3, r3, #0x0000ff00
+- orr r3, r3, #0x000000f0 @ mask 0xff07fff0
++ bic r3, r9, #0x00ff0000
++ bic r3, r3, #0x0000000f @ mask 0xff00fff0
++ mov r4, #0x41000000
+ orr r4, r4, #0x0000b000
+- orr r4, r4, #0x00000020 @ val 0x4107b020
+- and r0, r9, r3
+- teq r0, r4 @ ARM 11MPCore?
++ orr r4, r4, #0x00000020 @ val 0x4100b020
++ teq r3, r4 @ ARM 11MPCore?
+ moveq pc, lr @ yes, assume SMP
+
+ mrc p15, 0, r0, c0, c0, 5 @ read MPIDR
+- tst r0, #1 << 31
+- movne pc, lr @ bit 31 => SMP
++ and r0, r0, #0xc0000000 @ multiprocessing extensions and
++ teq r0, #0x80000000 @ not part of a uniprocessor system?
++ moveq pc, lr @ yes, assume SMP
+
+ __fixup_smp_on_up:
+ adr r0, 1f
projects / thirdparty / kernel / stable-queue.git / commitdiff
