drm/amd/pm: Add OD_FCLK interface

Add OD_FCLK interface to set customa fclk max

v2: Merge patch1 & 3, check EOPNOTSUPP for all clks (Lijo)

v3: Remove redundant check (Lijo)

Signed-off-by: Asad Kamal <asad.kamal@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index a9b73f4fd4661851f4950300dd1e11b83b4f8f0a..33a1404bb666aea6bd29552a33f8161d75fa95e7 100644 (file)
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -119,6 +119,7 @@ enum pp_clock_type {
        PP_ISPXCLK,
        OD_SCLK,
        OD_MCLK,
+       OD_FCLK,
        OD_VDDC_CURVE,
        OD_RANGE,
        OD_VDDGFX_OFFSET,
@@ -208,6 +209,7 @@ enum {
 enum PP_OD_DPM_TABLE_COMMAND {
        PP_OD_EDIT_SCLK_VDDC_TABLE,
        PP_OD_EDIT_MCLK_VDDC_TABLE,
+       PP_OD_EDIT_FCLK_TABLE,
        PP_OD_EDIT_CCLK_VDDC_TABLE,
        PP_OD_EDIT_VDDC_CURVE,
        PP_OD_RESTORE_DEFAULT_TABLE,

diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index 9e2f69663f960bb39fc70c549da9740e97eb382e..dbf3ae2f5e13f84a1c8ef2b548843bdb80b26803 100644 (file)
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -680,6 +680,8 @@ static ssize_t amdgpu_set_pp_table(struct device *dev,
  * - minimum(not available for Vega20 and Navi1x) and maximum memory
  *   clock labeled OD_MCLK
  *
+ * - minimum and maximum fabric clock labeled OD_FCLK (SMU13)
+ *
  * - three <frequency, voltage> points labeled OD_VDDC_CURVE.
  *   They can be used to calibrate the sclk voltage curve. This is
  *   available for Vega20 and NV1X.
@@ -715,10 +717,11 @@ static ssize_t amdgpu_set_pp_table(struct device *dev,
  * - First select manual using power_dpm_force_performance_level
  *
  * - For clock frequency setting, enter a new value by writing a
- *   string that contains "s/m index clock" to the file. The index
+ *   string that contains "s/m/f index clock" to the file. The index
  *   should be 0 if to set minimum clock. And 1 if to set maximum
  *   clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz.
- *   "m 1 800" will update maximum mclk to be 800Mhz. For core
+ *   "m 1 800" will update maximum mclk to be 800Mhz. "f 1 1600" will
+ *   update maximum fabric clock to be 1600Mhz. For core
  *   clocks on VanGogh, the string contains "p core index clock".
  *   E.g., "p 2 0 800" would set the minimum core clock on core
  *   2 to 800Mhz.
@@ -768,6 +771,8 @@ static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
                type = PP_OD_EDIT_CCLK_VDDC_TABLE;
        else if (*buf == 'm')
                type = PP_OD_EDIT_MCLK_VDDC_TABLE;
+       else if (*buf == 'f')
+               type = PP_OD_EDIT_FCLK_TABLE;
        else if (*buf == 'r')
                type = PP_OD_RESTORE_DEFAULT_TABLE;
        else if (*buf == 'c')
@@ -843,9 +848,10 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
        struct amdgpu_device *adev = drm_to_adev(ddev);
        int size = 0;
        int ret;
-       enum pp_clock_type od_clocks[6] = {
+       enum pp_clock_type od_clocks[] = {
                OD_SCLK,
                OD_MCLK,
+               OD_FCLK,
                OD_VDDC_CURVE,
                OD_RANGE,
                OD_VDDGFX_OFFSET,
@@ -857,10 +863,8 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
        if (ret)
                return ret;
 
-       for (clk_index = 0 ; clk_index < 6 ; clk_index++) {
-               ret = amdgpu_dpm_emit_clock_levels(adev, od_clocks[clk_index], buf, &size);
-               if (ret)
-                       break;
+       for (clk_index = 0 ; clk_index < ARRAY_SIZE(od_clocks) ; clk_index++) {
+               amdgpu_dpm_emit_clock_levels(adev, od_clocks[clk_index], buf, &size);
        }
 
        if (size == 0)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 26b43a6276d0d2bb00adfbe951712330c9a8c585..7a2c0a5fd14047db4786d8fbfc719c55ef6a49fc 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -3056,6 +3056,8 @@ static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type)
                clk_type = SMU_OD_SCLK; break;
        case OD_MCLK:
                clk_type = SMU_OD_MCLK; break;
+       case OD_FCLK:
+               clk_type = SMU_OD_FCLK; break;
        case OD_VDDC_CURVE:
                clk_type = SMU_OD_VDDC_CURVE; break;
        case OD_RANGE:

diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
index 584c4cfd0c16f68ecd61fb709dacace8e3581458..8cdbaf32492ed736ceb4677d1aba370fb235e5ba 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
@@ -324,6 +324,7 @@ enum smu_clk_type {
        SMU_OD_CCLK,
        SMU_OD_SCLK,
        SMU_OD_MCLK,
+       SMU_OD_FCLK,
        SMU_OD_VDDC_CURVE,
        SMU_OD_RANGE,
        SMU_OD_VDDGFX_OFFSET,