#define PCI_DEVICE_ID_ADDIDATA_CPCI7420_NG 0x7025
#define PCI_DEVICE_ID_ADDIDATA_CPCI7300_NG 0x7026
+#define PCI_VENDOR_ID_SYSTEMBASE 0x14a1
+
/* Unknown vendors/cards - this should not be in linux/pci_ids.h */
#define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
#define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
return setup_port(priv, port, bar, offset, 0);
}
+#define SB_OPTR_IMR0 0x0c /* Interrupt mask register, p0 to p7 */
+static int pci_systembase_init(struct pci_dev *dev)
+{
+ resource_size_t iobase;
+
+ if (!IS_ENABLED(CONFIG_HAS_IOPORT))
+ return serial_8250_warn_need_ioport(dev);
+
+ iobase = pci_resource_start(dev, 1);
+
+ /* This will support up to 8 ports */
+ outb(0xff, iobase + SB_OPTR_IMR0);
+
+ return 0;
+}
+
+static void pci_systembase_exit(struct pci_dev *dev)
+{
+ resource_size_t iobase;
+
+ if (!IS_ENABLED(CONFIG_HAS_IOPORT)) {
+ serial_8250_warn_need_ioport(dev);
+ return;
+ }
+
+ iobase = pci_resource_start(dev, 0);
+ outb(0x00, iobase + SB_OPTR_IMR0);
+}
+
/*
* Master list of serial port init/setup/exit quirks.
* This does not describe the general nature of the port.
.init = pci_siig_init,
.setup = pci_siig_setup,
},
+ /* Systembase */
+ {
+ .vendor = PCI_VENDOR_ID_SYSTEMBASE,
+ .device = 0x0008,
+ .subvendor = PCI_ANY_ID,
+ .subdevice = PCI_ANY_ID,
+ .init = pci_systembase_init,
+ .setup = pci_default_setup,
+ .exit = pci_systembase_exit,
+ },
/*
* Titan cards
*/
pbn_b0_1_921600,
pbn_b0_2_921600,
pbn_b0_4_921600,
+ pbn_b0_8_921600,
pbn_b0_2_1130000,
.base_baud = 921600,
.uart_offset = 8,
},
+ [pbn_b0_8_921600] = {
+ .flags = FL_BASE0,
+ .num_ports = 8,
+ .base_baud = 921600,
+ .uart_offset = 8,
+ },
[pbn_b0_2_1130000] = {
.flags = FL_BASE0,
PCI_ANY_ID, PCI_ANY_ID,
0, 0, pbn_b0_1_115200 },
+ /* Systembase Multi I/O cards */
+ { PCI_VDEVICE(SYSTEMBASE, 0x0008), pbn_b0_8_921600 },
+
/* Fintek PCI serial cards */
{ PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
{ PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },