drm/i915: Limit CHV max cdclk

Limit CHV maximum cdclk to 320MHz.

v2: Rebase to the latest
v3: Clean up of if-else tree

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a806f1598a4632229a32fb103457d8176f875c09..3f4891782cf6860b07efde7a0fcc680955f2d3a1 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5271,6 +5271,8 @@ static void intel_update_max_cdclk(struct drm_device *dev)
                        dev_priv->max_cdclk_freq = 540000;
                else
                        dev_priv->max_cdclk_freq = 675000;
+       } else if (IS_CHERRYVIEW(dev)) {
+               dev_priv->max_cdclk_freq = 320000;
        } else if (IS_VALLEYVIEW(dev)) {
                dev_priv->max_cdclk_freq = 400000;
        } else {