arm64: dts: ti: k3-j784s4-j742s2-main-common: Add DSI & DSI PHY

Add DT nodes for DPI to DSI Bridge and DSI Phy. The DSI bridge
is Cadence DSI and the PHY is a Cadence DPHY with TI wrapper.

Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Tested-by: Harikrishna Shenoy <h-shenoy@ti.com>
Reviewed-by: Harikrishna Shenoy <h-shenoy@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20250716060114.52122-2-j-choudhary@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
index 7c5b0c69897dfe5c77365a9a088c7cf2215bbb0d..79d97d46b4c69e08032298220d4b140ca2855593 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
@@ -2522,6 +2522,45 @@
                status = "reserved";
        };
 
+       dphy_tx0: phy@4480000 {
+               compatible = "ti,j721e-dphy";
+               reg = <0x00 0x04480000 0x00 0x00001000>;
+               clocks = <&k3_clks 402 20>, <&k3_clks 402 3>;
+               clock-names = "psm", "pll_ref";
+               #phy-cells = <0>;
+               power-domains = <&k3_pds 402 TI_SCI_PD_EXCLUSIVE>;
+               assigned-clocks = <&k3_clks 402 3>;
+               assigned-clock-parents = <&k3_clks 402 4>;
+               assigned-clock-rates = <19200000>;
+               status = "disabled";
+       };
+
+       dsi0: dsi@4800000 {
+               compatible = "ti,j721e-dsi";
+               reg = <0x00 0x04800000 0x00 0x00100000>,
+                     <0x00 0x04710000 0x00 0x00000100>;
+               clocks = <&k3_clks 215 2>, <&k3_clks 215 5>;
+               clock-names = "dsi_p_clk", "dsi_sys_clk";
+               power-domains = <&k3_pds 215 TI_SCI_PD_EXCLUSIVE>;
+               interrupts = <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>;
+               phys = <&dphy_tx0>;
+               phy-names = "dphy";
+               status = "disabled";
+
+               dsi0_ports: ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       port@0 {
+                               reg = <0>;
+                       };
+
+                       port@1 {
+                               reg = <1>;
+                       };
+               };
+       };
+
        mhdp: bridge@a000000 {
                compatible = "ti,j721e-mhdp8546";
                reg = <0x0 0xa000000 0x0 0x30a00>,