]> git.ipfire.org Git - thirdparty/glibc.git/commitdiff
riscv: memcpy_noalignment: Reorder to store via a3, then bump a3
authorYao Zihong <zihong.plct@isrc.iscas.ac.cn>
Thu, 30 Oct 2025 22:49:21 +0000 (17:49 -0500)
committerPeter Bergner <bergner@tenstorrent.com>
Thu, 30 Oct 2025 22:49:21 +0000 (17:49 -0500)
Rewrite the copy micro-step from:

    REG_L  a4, 0(a5)
    addi   a3, a3, SZREG
    addi   a5, a5, SZREG
    REG_S  a4, -SZREG(a3)

to:

    REG_L  a4, 0(a5)
    addi   a5, a5, SZREG
    REG_S  a4, 0(a3)
    addi   a3, a3, SZREG

Semantics are unchanged: both read *(a5_old), write *(a3_old), and then
increment a3/a5 by SZREG. memcpy assumes non-overlapping regions, so the
reordering preserves correctness.

No functional change.

Signed-off-by: Yao Zihong <zihong.plct@isrc.iscas.ac.cn>
Reviewed-by: Peter Bergner <bergner@tenstorrent.com>
sysdeps/riscv/multiarch/memcpy_noalignment.S

index 6917fc435b009ce52b1245dc316f99453f5487e4..43ce89065705fb4b4110680236f411b15235c0a4 100644 (file)
@@ -109,9 +109,9 @@ L(word_copy):
        mv      a5, a1
 L(word_copy_loop):
        REG_L   a4, 0(a5)
-       addi    a3, a3, SZREG
        addi    a5, a5, SZREG
-       REG_S   a4, -SZREG(a3)
+       REG_S   a4, 0(a3)
+       addi    a3, a3, SZREG
        bne     a3, a6, L(word_copy_loop)
        add     a1, a1, a7
        andi    a2, a2, SZREG-1