iselCondCode: handle literals.

git-svn-id: svn://svn.valgrind.org/vex/trunk@1277

diff --git a/VEX/priv/host-amd64/isel.c b/VEX/priv/host-amd64/isel.c
index c23185a79ac95f74cdbcf9dfdcfe50455331dfa8..3dcf354d1e55d90507f3ec6fd020f10084b44201 100644 (file)
--- a/VEX/priv/host-amd64/isel.c
+++ b/VEX/priv/host-amd64/isel.c
@@ -1934,15 +1934,17 @@ static AMD64CondCode iselCondCode_wrk ( ISelEnv* env, IRExpr* e )
       return Acc_NZ;
    }
 
-//..    /* Constant 1:Bit */
-//..    if (e->tag == Iex_Const && e->Iex.Const.con->Ico.U1 == True) {
-//..       HReg r;
-//..       vassert(e->Iex.Const.con->tag == Ico_U1);
-//..       r = newVRegI(env);
-//..       addInstr(env, X86Instr_Alu32R(Xalu_MOV,X86RMI_Imm(0),r));
-//..       addInstr(env, X86Instr_Alu32R(Xalu_XOR,X86RMI_Reg(r),r));
-//..       return Xcc_Z;
-//..    }
+   /* Constant 1:Bit */
+   if (e->tag == Iex_Const) {
+      HReg r;
+      vassert(e->Iex.Const.con->tag == Ico_U1);
+      vassert(e->Iex.Const.con->Ico.U1 == True 
+              || e->Iex.Const.con->Ico.U1 == False);
+      r = newVRegI(env);
+      addInstr(env, AMD64Instr_Alu64R(Aalu_MOV,AMD64RMI_Imm(0),r));
+      addInstr(env, AMD64Instr_Alu64R(Aalu_XOR,AMD64RMI_Reg(r),r));
+      return e->Iex.Const.con->Ico.U1 ? Acc_Z : Acc_NZ;
+   }
 
    /* Not1(...) */
    if (e->tag == Iex_Unop && e->Iex.Unop.op == Iop_Not1) {