net: zynq: Fix MDC setting for zynq

Based on spec:
"MDC must not exceed 2.5 MHz (MDC is only active during MDIO read and
write operations)"
Zynq is running on 111MHz. Current setting is 32 which is 111/32=3.47
which is above of 2.5MHz.
Using 48 divider will give us correct setting according spec
(111/48=2.31).

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index c54d31a47ff8292b5bff53a50a988e0be571bc77..eccd5acee92eb21214ffa0c4fb1ec51ad8683b11 100644 (file)
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -61,7 +61,7 @@
 #ifdef CONFIG_ARM64
 #define ZYNQ_GEM_NWCFG_MDCCLKDIV       0x0001C0000 /* Div pclk by 224, 540MHz */
 #else
-#define ZYNQ_GEM_NWCFG_MDCCLKDIV       0x000080000 /* Div pclk by 32, 80MHz */
+#define ZYNQ_GEM_NWCFG_MDCCLKDIV       0x0000c0000 /* Div pclk by 48, max 120MHz */
 #endif
 
 #ifdef CONFIG_ARM64