drm/amd/amdgpu: enable uvd&vce clock gating for Fiji.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Acked-by: Jammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 67845ee644ad52fa3a7beb6c0bd7551cf84e2e41..652e76644c31cab37fee1964797d890749fbf0a7 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -1442,7 +1442,8 @@ static int vi_common_early_init(void *handle)
                break;
        case CHIP_FIJI:
                adev->has_uvd = true;
-               adev->cg_flags = 0;
+               adev->cg_flags = AMDGPU_CG_SUPPORT_UVD_MGCG |
+                               AMDGPU_CG_SUPPORT_VCE_MGCG;
                adev->pg_flags = 0;
                adev->external_rev_id = adev->rev_id + 0x3c;
                break;