drm/sun4i: csc: use layer arg instead of mixer

Layer will be more universal, due to DE33 support.

Reviewed-by: Chen-Yu Tsai <wens@kernel.org>
Tested-by: Ryan Walklin <ryan@testtoast.com>
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://patch.msgid.link/20251104180942.61538-22-jernej.skrabec@gmail.com
Signed-off-by: Chen-Yu Tsai <wens@kernel.org>

diff --git a/drivers/gpu/drm/sun4i/sun8i_csc.c b/drivers/gpu/drm/sun4i/sun8i_csc.c
index ac7b62adc7df64f5a55bb272d6024c753b3b8c4c..c371e94b95bdf3e1588d4009ca40324000e38ab5 100644 (file)
--- a/drivers/gpu/drm/sun4i/sun8i_csc.c
+++ b/drivers/gpu/drm/sun4i/sun8i_csc.c
@@ -227,22 +227,22 @@ static u32 sun8i_csc_get_mode(struct drm_plane_state *state)
        }
 }
 
-void sun8i_csc_config(struct sun8i_mixer *mixer, int layer,
+void sun8i_csc_config(struct sun8i_layer *layer,
                      struct drm_plane_state *state)
 {
        u32 mode = sun8i_csc_get_mode(state);
        u32 base;
 
-       if (mixer->cfg->de_type == SUN8I_MIXER_DE3) {
-               sun8i_de3_ccsc_setup(mixer->engine.regs, layer,
+       if (layer->mixer->cfg->de_type == SUN8I_MIXER_DE3) {
+               sun8i_de3_ccsc_setup(layer->regs, layer->channel,
                                     mode, state->color_encoding,
                                     state->color_range);
                return;
        }
 
-       base = ccsc_base[mixer->cfg->ccsc][layer];
+       base = ccsc_base[layer->mixer->cfg->ccsc][layer->channel];
 
-       sun8i_csc_setup(mixer->engine.regs, base,
+       sun8i_csc_setup(layer->regs, base,
                        mode, state->color_encoding,
                        state->color_range);
 }

diff --git a/drivers/gpu/drm/sun4i/sun8i_csc.h b/drivers/gpu/drm/sun4i/sun8i_csc.h
index ce921521aaca35bf90f33391a1b67a20b00d3118..2a4b79599610d972f9c7ea5c78d434a547d4ecd8 100644 (file)
--- a/drivers/gpu/drm/sun4i/sun8i_csc.h
+++ b/drivers/gpu/drm/sun4i/sun8i_csc.h
@@ -9,7 +9,7 @@
 #include <drm/drm_color_mgmt.h>
 
 struct drm_plane_state;
-struct sun8i_mixer;
+struct sun8i_layer;
 
 /* VI channel CSC units offsets */
 #define CCSC00_OFFSET 0xAA050
@@ -23,7 +23,7 @@ struct sun8i_mixer;
 
 #define SUN8I_CSC_CTRL_EN              BIT(0)
 
-void sun8i_csc_config(struct sun8i_mixer *mixer, int layer,
+void sun8i_csc_config(struct sun8i_layer *layer,
                      struct drm_plane_state *state);
 
 #endif

diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
index 3e414d7fe236d55ec3a99e6b233ee58910cd4428..78df7836099fda6f23aa2c65d819c103a056c28b 100644 (file)
--- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
@@ -301,7 +301,7 @@ static void sun8i_vi_layer_atomic_update(struct drm_plane *plane,
 
        sun8i_vi_layer_update_attributes(layer, plane);
        sun8i_vi_layer_update_coord(layer, plane);
-       sun8i_csc_config(layer->mixer, layer->channel, new_state);
+       sun8i_csc_config(layer, new_state);
        sun8i_vi_layer_update_buffer(layer, plane);
 }