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aarch64: Make more use of TARGET_STREAMING_SME2
authorRichard Sandiford <richard.sandiford@arm.com>
Mon, 11 Nov 2024 12:32:14 +0000 (12:32 +0000)
committerRichard Sandiford <richard.sandiford@arm.com>
Mon, 11 Nov 2024 12:32:14 +0000 (12:32 +0000)
Some code was checking TARGET_STREAMING and TARGET_SME2 separately,
but we now have a macro to test both at once.

gcc/
* config/aarch64/aarch64-sme.md: Use TARGET_STREAMING_SME2
instead of separate TARGET_STREAMING and TARGET_SME2 tests.
* config/aarch64/aarch64-sve2.md: Likewise.
* config/aarch64/iterators.md: Likewise.

gcc/config/aarch64/aarch64-sme.md patch | blob | blame | history
gcc/config/aarch64/aarch64-sve2.md patch | blob | blame | history
gcc/config/aarch64/iterators.md patch | blob | blame | history

diff --git a/gcc/config/aarch64/aarch64-sme.md b/gcc/config/aarch64/aarch64-sme.md
index 78ad2fc699f22c9483580c62a9a873ca7129a2c1..9215f51b01f8129b3cca336fe6274959c9acc8a8 100644 (file)
--- a/gcc/config/aarch64/aarch64-sme.md
+++ b/gcc/config/aarch64/aarch64-sme.md
@@ -1334,7 +1334,7 @@
           (match_operand:VNx8HI_ONLY 1 "register_operand" "w")
           (match_operand:VNx8HI_ONLY 2 "register_operand" "x")]
          SME_INT_TERNARY_SLICE))]
-  "TARGET_SME2 && TARGET_SME_I16I64 && TARGET_STREAMING_SME"
+  "TARGET_STREAMING_SME2 && TARGET_SME_I16I64"
   "<optab>ll\tza.d[%w0, 0:3], %1.h, %2.h"
 )
 
@@ -1348,7 +1348,7 @@
           (match_operand:VNx8HI_ONLY 2 "register_operand" "w")
           (match_operand:VNx8HI_ONLY 3 "register_operand" "x")]
          SME_INT_TERNARY_SLICE))]
-  "TARGET_SME2 && TARGET_SME_I16I64 && TARGET_STREAMING_SME"
+  "TARGET_STREAMING_SME2 && TARGET_SME_I16I64"
   {
     operands[4] = GEN_INT (INTVAL (operands[1]) + 3);
     return "<optab>ll\tza.d[%w0, %1:%4], %2.h, %3.h";
@@ -1364,7 +1364,7 @@
           (match_operand:SME_ZA_HIx24 1 "aligned_register_operand" "Uw<vector_count>")
           (match_operand:SME_ZA_HIx24 2 "aligned_register_operand" "Uw<vector_count>")]
          SME_INT_TERNARY_SLICE))]
-  "TARGET_SME2 && TARGET_SME_I16I64 && TARGET_STREAMING_SME"
+  "TARGET_STREAMING_SME2 && TARGET_SME_I16I64"
   "<optab>ll\tza.d[%w0, 0:3, vgx<vector_count>], %1, %2"
 )
 
@@ -1378,7 +1378,7 @@
           (match_operand:SME_ZA_HIx24 2 "aligned_register_operand" "Uw<vector_count>")
           (match_operand:SME_ZA_HIx24 3 "aligned_register_operand" "Uw<vector_count>")]
          SME_INT_TERNARY_SLICE))]
-  "TARGET_SME2 && TARGET_SME_I16I64 && TARGET_STREAMING_SME"
+  "TARGET_STREAMING_SME2 && TARGET_SME_I16I64"
   {
     operands[4] = GEN_INT (INTVAL (operands[1]) + 3);
     return "<optab>ll\tza.d[%w0, %1:%4, vgx<vector_count>], %2, %3";
@@ -1395,7 +1395,7 @@
           (vec_duplicate:SME_ZA_HIx24
             (match_operand:<SME_ZA_HIx24:VSINGLE> 2 "register_operand" "x"))]
          SME_INT_TERNARY_SLICE))]
-  "TARGET_SME2 && TARGET_SME_I16I64 && TARGET_STREAMING_SME"
+  "TARGET_STREAMING_SME2 && TARGET_SME_I16I64"
   "<optab>ll\tza.d[%w0, 0:3, vgx<vector_count>], %1, %2.h"
 )
 
@@ -1410,7 +1410,7 @@
           (vec_duplicate:SME_ZA_HIx24
             (match_operand:<SME_ZA_HIx24:VSINGLE> 3 "register_operand" "x"))]
          SME_INT_TERNARY_SLICE))]
-  "TARGET_SME2 && TARGET_SME_I16I64 && TARGET_STREAMING_SME"
+  "TARGET_STREAMING_SME2 && TARGET_SME_I16I64"
   {
     operands[4] = GEN_INT (INTVAL (operands[1]) + 3);
     return "<optab>ll\tza.d[%w0, %1:%4, vgx<vector_count>], %2, %3.h";
@@ -1429,7 +1429,7 @@
              (match_operand:SI 3 "const_int_operand")]
             UNSPEC_SVE_LANE_SELECT)]
          SME_INT_TERNARY_SLICE))]
-  "TARGET_SME2 && TARGET_SME_I16I64 && TARGET_STREAMING_SME"
+  "TARGET_STREAMING_SME2 && TARGET_SME_I16I64"
   "<optab>ll\tza.d[%w0, 0:3<vg_modifier>], %1<z_suffix>, %2.h[%3]"
 )
 
@@ -1446,7 +1446,7 @@
              (match_operand:SI 4 "const_int_operand")]
             UNSPEC_SVE_LANE_SELECT)]
          SME_INT_TERNARY_SLICE))]
-  "TARGET_SME2 && TARGET_SME_I16I64 && TARGET_STREAMING_SME"
+  "TARGET_STREAMING_SME2 && TARGET_SME_I16I64"
   {
     operands[5] = GEN_INT (INTVAL (operands[1]) + 3);
     return "<optab>ll\tza.d[%w0, %1:%5<vg_modifier>], %2<z_suffix>, %3.h[%4]";
@@ -1642,8 +1642,7 @@
           (match_operand:SME_ZA_SDFx24 1 "aligned_register_operand" "Uw<vector_count>")
           (match_operand:SME_ZA_SDFx24 2 "aligned_register_operand" "Uw<vector_count>")]
          SME_FP_TERNARY_SLICE))]
-  "TARGET_SME2
-   && TARGET_STREAMING_SME
+  "TARGET_STREAMING_SME2
    && <SME_ZA_SDF_I:elem_bits> == <SME_ZA_SDFx24:elem_bits>"
   "<optab>\tza.<SME_ZA_SDF_I:Vetype>[%w0, 0, vgx<vector_count>], %1, %2"
 )
@@ -1658,8 +1657,7 @@
           (match_operand:SME_ZA_SDFx24 2 "aligned_register_operand" "Uw<vector_count>")
           (match_operand:SME_ZA_SDFx24 3 "aligned_register_operand" "Uw<vector_count>")]
          SME_FP_TERNARY_SLICE))]
-  "TARGET_SME2
-   && TARGET_STREAMING_SME
+  "TARGET_STREAMING_SME2
    && <SME_ZA_SDF_I:elem_bits> == <SME_ZA_SDFx24:elem_bits>"
   "<optab>\tza.<SME_ZA_SDF_I:Vetype>[%w0, %1, vgx<vector_count>], %2, %3"
 )
@@ -1674,8 +1672,7 @@
           (vec_duplicate:SME_ZA_SDFx24
             (match_operand:<VSINGLE> 2 "register_operand" "x"))]
          SME_FP_TERNARY_SLICE))]
-  "TARGET_SME2
-   && TARGET_STREAMING_SME
+  "TARGET_STREAMING_SME2
    && <SME_ZA_SDF_I:elem_bits> == <SME_ZA_SDFx24:elem_bits>"
   "<optab>\tza.<SME_ZA_SDF_I:Vetype>[%w0, 0, vgx<vector_count>], %1, %2.<SME_ZA_SDFx24:Vetype>"
 )
@@ -1691,8 +1688,7 @@
           (vec_duplicate:SME_ZA_SDFx24
             (match_operand:<VSINGLE> 3 "register_operand" "x"))]
          SME_FP_TERNARY_SLICE))]
-  "TARGET_SME2
-   && TARGET_STREAMING_SME
+  "TARGET_STREAMING_SME2
    && <SME_ZA_SDF_I:elem_bits> == <SME_ZA_SDFx24:elem_bits>"
   "<optab>\tza.<SME_ZA_SDF_I:Vetype>[%w0, %1, vgx<vector_count>], %2, %3.<SME_ZA_SDFx24:Vetype>"
 )
@@ -1709,8 +1705,7 @@
              (match_operand:SI 3 "const_int_operand")]
             UNSPEC_SVE_LANE_SELECT)]
          SME_FP_TERNARY_SLICE))]
-  "TARGET_SME2
-   && TARGET_STREAMING_SME
+  "TARGET_STREAMING_SME2
    && <SME_ZA_SDF_I:elem_bits> == <SME_ZA_SDFx24:elem_bits>"
   "<optab>\tza.<SME_ZA_SDF_I:Vetype>[%w0, 0, vgx<vector_count>], %1, %2.<SME_ZA_SDFx24:Vetype>[%3]"
 )
@@ -1728,8 +1723,7 @@
              (match_operand:SI 4 "const_int_operand")]
             UNSPEC_SVE_LANE_SELECT)]
          SME_FP_TERNARY_SLICE))]
-  "TARGET_SME2
-   && TARGET_STREAMING_SME
+  "TARGET_STREAMING_SME2
    && <SME_ZA_SDF_I:elem_bits> == <SME_ZA_SDFx24:elem_bits>"
   "<optab>\tza.<SME_ZA_SDF_I:Vetype>[%w0, %1, vgx<vector_count>], %2, %3.<SME_ZA_SDFx24:Vetype>[%4]"
 )
diff --git a/gcc/config/aarch64/aarch64-sve2.md b/gcc/config/aarch64/aarch64-sve2.md
index ac27124fb74e702eabda8c2611b3fc60b802c8d6..38ecdd1ccc1f6aa0bcdee5b37269c526918d6cbf 100644 (file)
--- a/gcc/config/aarch64/aarch64-sve2.md
+++ b/gcc/config/aarch64/aarch64-sve2.md
@@ -2213,7 +2213,7 @@
        (unspec:VNx16QI_ONLY
          [(match_operand:VNx16SI_ONLY 1 "aligned_register_operand" "Uw<vector_count>")]
          SVE_QCVTxN))]
-  "TARGET_SME2 && TARGET_STREAMING"
+  "TARGET_STREAMING_SME2"
   "<optab>\t%0.b, %1"
 )
 
@@ -2222,7 +2222,7 @@
        (unspec:VNx8HI_ONLY
          [(match_operand:VNx8SI_ONLY 1 "aligned_register_operand" "Uw<vector_count>")]
          SVE_QCVTxN))]
-  "TARGET_SME2 && TARGET_STREAMING"
+  "TARGET_STREAMING_SME2"
   "<optab>\t%0.h, %1"
 )
 
@@ -2231,7 +2231,7 @@
        (unspec:VNx8HI_ONLY
          [(match_operand:VNx8DI_ONLY 1 "aligned_register_operand" "Uw<vector_count>")]
          SVE_QCVTxN))]
-  "TARGET_SME2 && TARGET_STREAMING"
+  "TARGET_STREAMING_SME2"
   "<optab>\t%0.h, %1"
 )
 
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index 8269b0cdcd926f524c9c6b9f2f072937d92f7529..4942631aa950969afca27b08d476dcf33342a14e 100644 (file)
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -3051,16 +3051,16 @@
   [UNSPEC_BFDOT
    UNSPEC_BFMLALB
    UNSPEC_BFMLALT
-   (UNSPEC_BFMLSLB "TARGET_SME2 && TARGET_STREAMING_SME")
-   (UNSPEC_BFMLSLT "TARGET_SME2 && TARGET_STREAMING_SME")
+   (UNSPEC_BFMLSLB "TARGET_STREAMING_SME2")
+   (UNSPEC_BFMLSLT "TARGET_STREAMING_SME2")
    (UNSPEC_BFMMLA "TARGET_NON_STREAMING")])
 
 (define_int_iterator SVE_BFLOAT_TERNARY_LONG_LANE
   [UNSPEC_BFDOT
    UNSPEC_BFMLALB
    UNSPEC_BFMLALT
-   (UNSPEC_BFMLSLB "TARGET_SME2 && TARGET_STREAMING_SME")
-   (UNSPEC_BFMLSLT "TARGET_SME2 && TARGET_STREAMING_SME")])
+   (UNSPEC_BFMLSLB "TARGET_STREAMING_SME2")
+   (UNSPEC_BFMLSLT "TARGET_STREAMING_SME2")])
 
 (define_int_iterator SVE_INT_REDUCTION [UNSPEC_ANDV
                                        UNSPEC_IORV
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