drop two broken arm64 patches from 5.12

Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/queue-5.12/arm64-dts-ti-k3-j721e-common-proc-board-re-name-link.patch b/queue-5.12/arm64-dts-ti-k3-j721e-common-proc-board-re-name-link.patch
deleted file mode 100644 (file)
index 5927d4f..0000000
--- a/queue-5.12/arm64-dts-ti-k3-j721e-common-proc-board-re-name-link.patch
+++ /dev/null
@@ -1,73 +0,0 @@
-From ad986868900503268b5d965bee220dfe4c0289dd Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Thu, 3 Jun 2021 20:04:27 +0530
-Subject: arm64: dts: ti: k3-j721e-common-proc-board: Re-name "link" name as
- "phy"
-
-From: Kishon Vijay Abraham I <kishon@ti.com>
-
-[ Upstream commit 02b4d9186121d842a53e347f53a86ec7f2c6b0c7 ]
-
-Commit 66db854b1f62d ("arm64: dts: ti: k3-j721e-common-proc-board:
-Configure the PCIe instances") and
-commit 02c35dca2b488 ("arm64: dts: ti: k3-j721e: Enable Super-Speed
-support for USB0") added PHY DT nodes with node name as "link"
-However nodes with #phy-cells should be named 'phy' as discussed in [1].
-Re-name subnodes of serdes in J721E to 'phy'.
-
-[1] -> http://lore.kernel.org/r/20200909203631.GA3026331@bogus
-
-Fixes: 66db854b1f62d ("arm64: dts: ti: k3-j721e-common-proc-board: Configure the PCIe instances")
-Fixes: 02c35dca2b488 ("arm64: dts: ti: k3-j721e: Enable Super-Speed support for USB0")
-Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
-Reviewed-by: Aswath Govindraju <a-govindraju@ti.com>
-Signed-off-by: Nishanth Menon <nm@ti.com>
-Link: https://lore.kernel.org/r/20210603143427.28735-5-kishon@ti.com
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
-diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
-index 1b25a5ae9635..ffccbc53f1e7 100644
---- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
-+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
-@@ -359,7 +359,7 @@
- };
- 
- &serdes3 {
--      serdes3_usb_link: link@0 {
-+      serdes3_usb_link: phy@0 {
-               reg = <0>;
-               cdns,num-lanes = <2>;
-               #phy-cells = <0>;
-@@ -674,7 +674,7 @@
-       assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>;
-       assigned-clock-parents = <&wiz0_pll1_refclk>;
- 
--      serdes0_pcie_link: link@0 {
-+      serdes0_pcie_link: phy@0 {
-               reg = <0>;
-               cdns,num-lanes = <1>;
-               #phy-cells = <0>;
-@@ -687,7 +687,7 @@
-       assigned-clocks = <&serdes1 CDNS_SIERRA_PLL_CMNLC>;
-       assigned-clock-parents = <&wiz1_pll1_refclk>;
- 
--      serdes1_pcie_link: link@0 {
-+      serdes1_pcie_link: phy@0 {
-               reg = <0>;
-               cdns,num-lanes = <2>;
-               #phy-cells = <0>;
-@@ -700,7 +700,7 @@
-       assigned-clocks = <&serdes2 CDNS_SIERRA_PLL_CMNLC>;
-       assigned-clock-parents = <&wiz2_pll1_refclk>;
- 
--      serdes2_pcie_link: link@0 {
-+      serdes2_pcie_link: phy@0 {
-               reg = <0>;
-               cdns,num-lanes = <2>;
-               #phy-cells = <0>;
--- 
-2.30.2
-

diff --git a/queue-5.12/arm64-dts-ti-k3-j721e-common-proc-board-use-external.patch b/queue-5.12/arm64-dts-ti-k3-j721e-common-proc-board-use-external.patch
deleted file mode 100644 (file)
index 8cf14b7..0000000
--- a/queue-5.12/arm64-dts-ti-k3-j721e-common-proc-board-use-external.patch
+++ /dev/null
@@ -1,99 +0,0 @@
-From 09186fa3ef55f4451e8893ca3154a56a1dca1d59 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Thu, 3 Jun 2021 20:04:26 +0530
-Subject: arm64: dts: ti: k3-j721e-common-proc-board: Use external clock for
- SERDES
-
-From: Kishon Vijay Abraham I <kishon@ti.com>
-
-[ Upstream commit f2a7657ad7a821de9cc77d071a5587b243144cd5 ]
-
-Use external clock for all the SERDES used by PCIe controller. This will
-make the same clock used by the local SERDES as well as the clock
-provided to the PCIe connector.
-
-Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
-Reviewed-by: Aswath Govindraju <a-govindraju@ti.com>
-Signed-off-by: Nishanth Menon <nm@ti.com>
-Link: https://lore.kernel.org/r/20210603143427.28735-4-kishon@ti.com
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- .../dts/ti/k3-j721e-common-proc-board.dts     | 40 +++++++++++++++++++
- 1 file changed, 40 insertions(+)
-
-diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
-index 86f7ab511ee8..1b25a5ae9635 100644
---- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
-+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
-@@ -9,6 +9,7 @@
- #include <dt-bindings/gpio/gpio.h>
- #include <dt-bindings/input/input.h>
- #include <dt-bindings/net/ti-dp83867.h>
-+#include <dt-bindings/phy/phy-cadence.h>
- 
- / {
-       chosen {
-@@ -639,7 +640,40 @@
-       clock-frequency = <100000000>;
- };
- 
-+&wiz0_pll1_refclk {
-+      assigned-clocks = <&wiz0_pll1_refclk>;
-+      assigned-clock-parents = <&cmn_refclk1>;
-+};
-+
-+&wiz0_refclk_dig {
-+      assigned-clocks = <&wiz0_refclk_dig>;
-+      assigned-clock-parents = <&cmn_refclk1>;
-+};
-+
-+&wiz1_pll1_refclk {
-+      assigned-clocks = <&wiz1_pll1_refclk>;
-+      assigned-clock-parents = <&cmn_refclk1>;
-+};
-+
-+&wiz1_refclk_dig {
-+      assigned-clocks = <&wiz1_refclk_dig>;
-+      assigned-clock-parents = <&cmn_refclk1>;
-+};
-+
-+&wiz2_pll1_refclk {
-+      assigned-clocks = <&wiz2_pll1_refclk>;
-+      assigned-clock-parents = <&cmn_refclk1>;
-+};
-+
-+&wiz2_refclk_dig {
-+      assigned-clocks = <&wiz2_refclk_dig>;
-+      assigned-clock-parents = <&cmn_refclk1>;
-+};
-+
- &serdes0 {
-+      assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>;
-+      assigned-clock-parents = <&wiz0_pll1_refclk>;
-+
-       serdes0_pcie_link: link@0 {
-               reg = <0>;
-               cdns,num-lanes = <1>;
-@@ -650,6 +684,9 @@
- };
- 
- &serdes1 {
-+      assigned-clocks = <&serdes1 CDNS_SIERRA_PLL_CMNLC>;
-+      assigned-clock-parents = <&wiz1_pll1_refclk>;
-+
-       serdes1_pcie_link: link@0 {
-               reg = <0>;
-               cdns,num-lanes = <2>;
-@@ -660,6 +697,9 @@
- };
- 
- &serdes2 {
-+      assigned-clocks = <&serdes2 CDNS_SIERRA_PLL_CMNLC>;
-+      assigned-clock-parents = <&wiz2_pll1_refclk>;
-+
-       serdes2_pcie_link: link@0 {
-               reg = <0>;
-               cdns,num-lanes = <2>;
--- 
-2.30.2
-

diff --git a/queue-5.12/series b/queue-5.12/series
index 1dda2792043d24a6e4f3aa36c85b277408c8c4e6..6e04e5353a3e2774042d9aa71374914b76224cc6 100644 (file)
--- a/queue-5.12/series
+++ b/queue-5.12/series
@@ -255,8 +255,6 @@ reset-bail-if-try_module_get-fails.patch
 arm64-dts-renesas-r8a779a0-drop-power-domains-proper.patch
 revert-arm-dts-bcm283x-increase-dwc2-s-rx-fifo-size.patch
 arm64-dts-ti-k3-j721e-main-fix-external-refclk-input.patch
-arm64-dts-ti-k3-j721e-common-proc-board-use-external.patch
-arm64-dts-ti-k3-j721e-common-proc-board-re-name-link.patch
 memory-fsl_ifc-fix-leak-of-io-mapping-on-probe-failu.patch
 memory-fsl_ifc-fix-leak-of-private-memory-on-probe-f.patch
 arm64-dts-allwinner-a64-sopine-baseboard-change-rgmi.patch