clk: meson: Fix GXL HDMI PLL fractional bits width

[ Upstream commit 21310c39ec01e82ef3ef9bf8ac385b53ccdc158c ]

The GXL Documentation specifies 12 bits for the Fractional bit field,
bit the last bits have a different purpose that we cannot handle right
now, so update the bitwidth to have correct fractional calculations.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
[narmstrong: added comment on GXL HHI_HDMI_PLL_CNTL register shift]
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lkml.kernel.org/r/20181121111922.1277-1-narmstrong@baylibre.com
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index d94b65061b9f1b2d378c57f869350d8460fc2c87..b039909e03cf855e53874f6d871744b1dc715377 100644 (file)
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -295,6 +295,12 @@ static struct clk_regmap gxl_hdmi_pll = {
                        .shift   = 9,
                        .width   = 5,
                },
+               /*
+                * On gxl, there is a register shift due to
+                * HHI_HDMI_PLL_CNTL1 which does not exist on gxbb,
+                * so we use the HHI_HDMI_PLL_CNTL2 define from GXBB
+                * instead which is defined at the same offset.
+                */
                .frac = {
                        /*
                         * On gxl, there is a register shift due to
@@ -304,7 +310,7 @@ static struct clk_regmap gxl_hdmi_pll = {
                         */
                        .reg_off = HHI_HDMI_PLL_CNTL + 4,
                        .shift   = 0,
-                       .width   = 12,
+                       .width   = 10,
                },
                .od = {
                        .reg_off = HHI_HDMI_PLL_CNTL + 8,