4.10-stable patches

added patches:
	x86-msr-index.h-define-atom-specific-core-ratio-msr-locations.patch

diff --git a/queue-4.10/series b/queue-4.10/series
index d5e8ba64c17ba6df957af68fc76afea44263dfc8..eac35f4891c71cdb484dc1cee3ea6ec22481b722 100644 (file)
--- a/queue-4.10/series
+++ b/queue-4.10/series
@@ -99,6 +99,7 @@ pci-sort-the-list-of-devices-with-d3-delay-quirk-by-id.patch
 pci-add-acs-quirk-for-qualcomm-qdf2400-and-qdf2432.patch
 watchdog-s3c2410-fix-infinite-interrupt-in-soft-mode.patch
 platform-x86-asus-wmi-detect-quirk_no_rfkill-from-the-dsdt.patch
+x86-msr-index.h-define-atom-specific-core-ratio-msr-locations.patch
 tools-power-turbostat-decode-baytrail-cc6-and-mc6-demotion-configuration.patch
 tools-power-turbostat-dump-atom-p-states-correctly.patch
 x86-reboot-quirks-add-asus-eeebook-x205ta-reboot-quirk.patch

diff --git a/queue-4.10/x86-msr-index.h-define-atom-specific-core-ratio-msr-locations.patch b/queue-4.10/x86-msr-index.h-define-atom-specific-core-ratio-msr-locations.patch
new file mode 100644 (file)
index 0000000..771ef64
--- /dev/null
+++ b/queue-4.10/x86-msr-index.h-define-atom-specific-core-ratio-msr-locations.patch
@@ -0,0 +1,36 @@
+From 8a34fd0226eaae64d61ff9a113d276e28acb6b5c Mon Sep 17 00:00:00 2001
+From: Len Brown <len.brown@intel.com>
+Date: Thu, 12 Jan 2017 23:22:28 -0500
+Subject: x86 msr-index.h: Define Atom specific core ratio MSR locations
+
+From: Len Brown <len.brown@intel.com>
+
+commit 8a34fd0226eaae64d61ff9a113d276e28acb6b5c upstream.
+
+These MSRs are currently used by the intel_pstate driver,
+using a local definition.
+
+Cc: x86@kernel.org
+Signed-off-by: Len Brown <len.brown@intel.com>
+Cc: Andre Tomt <andre@tomt.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/x86/include/asm/msr-index.h |    6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/arch/x86/include/asm/msr-index.h
++++ b/arch/x86/include/asm/msr-index.h
+@@ -207,6 +207,12 @@
+ #define MSR_CC6_DEMOTION_POLICY_CONFIG        0x00000668
+ #define MSR_MC6_DEMOTION_POLICY_CONFIG        0x00000669
+ 
++#define MSR_ATOM_CORE_RATIOS          0x0000066a
++#define MSR_ATOM_CORE_VIDS            0x0000066b
++#define MSR_ATOM_CORE_TURBO_RATIOS    0x0000066c
++#define MSR_ATOM_CORE_TURBO_VIDS      0x0000066d
++
++
+ #define MSR_CORE_PERF_LIMIT_REASONS   0x00000690
+ #define MSR_GFX_PERF_LIMIT_REASONS    0x000006B0
+ #define MSR_RING_PERF_LIMIT_REASONS   0x000006B1