drop queue-5.15/drm-amd-display-add-a-left-edge-pixel-if-in-ycbcr422.patch

breaks the build

diff --git a/queue-5.15/drm-amd-display-add-a-left-edge-pixel-if-in-ycbcr422.patch b/queue-5.15/drm-amd-display-add-a-left-edge-pixel-if-in-ycbcr422.patch
deleted file mode 100644 (file)
index 1be9190..0000000
--- a/queue-5.15/drm-amd-display-add-a-left-edge-pixel-if-in-ycbcr422.patch
+++ /dev/null
@@ -1,87 +0,0 @@
-From 14a54868aaad5c6c93d24c5f5d5d0a5836064a05 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Thu, 7 Nov 2024 19:20:02 -0500
-Subject: drm/amd/display: Add a left edge pixel if in YCbCr422 or YCbCr420 and
- odm
-
-From: Peterson Guo <peterson.guo@amd.com>
-
-[ Upstream commit 63e7ee677c74e981257cedfdd8543510d09096ba ]
-
-[WHY]
-On some cards when odm is used, the monitor will have 2 separate pipes
-split vertically. When compression is used on the YCbCr colour space on
-the second pipe to have correct colours, we need to read a pixel from the
-end of first pipe to accurately display colours. Hardware was programmed
-properly to account for this extra pixel but it was not calculated
-properly in software causing a split screen on some monitors.
-
-[HOW]
-The fix adjusts the second pipe's viewport and timings if the pixel
-encoding is YCbCr422 or YCbCr420.
-
-Cc: Mario Limonciello <mario.limonciello@amd.com>
-Cc: Alex Deucher <alexander.deucher@amd.com>
-Cc: stable@vger.kernel.org
-Reviewed-by: George Shen <george.shen@amd.com>
-Signed-off-by: Peterson Guo <peterson.guo@amd.com>
-Signed-off-by: Alex Hung <alex.hung@amd.com>
-Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- .../drm/amd/display/dc/dcn20/dcn20_resource.c | 23 +++++++++++++++++++
- 1 file changed, 23 insertions(+)
-
-diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
-index 04b370e7e732..6688c40f3c70 100644
---- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
-+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
-@@ -1899,6 +1899,7 @@ bool dcn20_split_stream_for_odm(
- 
-       if (prev_odm_pipe->plane_state) {
-               struct scaler_data *sd = &prev_odm_pipe->plane_res.scl_data;
-+              struct output_pixel_processor *opp = next_odm_pipe->stream_res.opp;
-               int new_width;
- 
-               /* HACTIVE halved for odm combine */
-@@ -1932,7 +1933,28 @@ bool dcn20_split_stream_for_odm(
-               sd->viewport_c.x += dc_fixpt_floor(dc_fixpt_mul_int(
-                               sd->ratios.horz_c, sd->h_active - sd->recout.x));
-               sd->recout.x = 0;
-+
-+              /*
-+               * When odm is used in YcbCr422 or 420 colour space, a split screen
-+               * will be seen with the previous calculations since the extra left
-+               *  edge pixel is accounted for in fmt but not in viewport.
-+               *
-+               * Below are calculations which fix the split by fixing the calculations
-+               * if there is an extra left edge pixel.
-+               */
-+              if (opp && opp->funcs->opp_get_left_edge_extra_pixel_count
-+                              && opp->funcs->opp_get_left_edge_extra_pixel_count(
-+                                      opp, next_odm_pipe->stream->timing.pixel_encoding,
-+                                      resource_is_pipe_type(next_odm_pipe, OTG_MASTER)) == 1) {
-+                      sd->h_active += 1;
-+                      sd->recout.width += 1;
-+                      sd->viewport.x -= dc_fixpt_ceil(dc_fixpt_mul_int(sd->ratios.horz, 1));
-+                      sd->viewport_c.x -= dc_fixpt_ceil(dc_fixpt_mul_int(sd->ratios.horz, 1));
-+                      sd->viewport_c.width += dc_fixpt_ceil(dc_fixpt_mul_int(sd->ratios.horz, 1));
-+                      sd->viewport.width += dc_fixpt_ceil(dc_fixpt_mul_int(sd->ratios.horz, 1));
-+              }
-       }
-+
-       if (!next_odm_pipe->top_pipe)
-               next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx];
-       else
-@@ -2905,6 +2927,7 @@ bool dcn20_fast_validate_bw(
-                       ASSERT(0);
-               }
-       }
-+
-       /* Actual dsc count per stream dsc validation*/
-       if (!dcn20_validate_dsc(dc, context)) {
-               context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] =
--- 
-2.39.5
-

diff --git a/queue-5.15/series b/queue-5.15/series
index c6398b9157e99f82325cf9e228eeef7dbe396cf9..6ce96740b557e0bcd708d27da4fe1b41702cfc9a 100644 (file)
--- a/queue-5.15/series
+++ b/queue-5.15/series
@@ -88,7 +88,6 @@ bpf-check-validity-of-link-type-in-bpf_link_show_fdi.patch
 drm-dp_mst-fix-mst-sideband-message-body-length-chec.patch
 ksmbd-fix-out-of-bounds-read-in-ksmbd_vfs_stream_rea.patch
 ksmbd-fix-out-of-bounds-write-in-ksmbd_vfs_stream_wr.patch
-drm-amd-display-add-a-left-edge-pixel-if-in-ycbcr422.patch
 arm64-mm-rename-asid2idx-to-ctxid2asid.patch
 arm64-ensure-bits-asid-15-8-are-masked-out-when-the-.patch
 drm-dp_mst-verify-request-type-in-the-corresponding-.patch