/* Find the corresponding entry in the right TLB
Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE
*/
-static int find_tlb_entry(CPUSH4State * env, target_ulong address,
+static int find_tlb_entry(CPUSH4State *env, vaddr address,
tlb_t * entries, uint8_t nbtlb, int use_asid)
{
int match = MMU_DTLB_MISS;
- uint32_t start, end;
+ vaddr start, end;
uint8_t asid;
int i;
/* Find itlb entry
Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
*/
-static int find_itlb_entry(CPUSH4State * env, target_ulong address,
+static int find_itlb_entry(CPUSH4State *env, vaddr address,
int use_asid)
{
int e;
/* Find utlb entry
Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
-static int find_utlb_entry(CPUSH4State * env, target_ulong address, int use_asid)
+static int find_utlb_entry(CPUSH4State *env, vaddr address, int use_asid)
{
/* per utlb access */
increment_urc(env);
MMU_IADDR_ERROR, MMU_DADDR_ERROR_READ, MMU_DADDR_ERROR_WRITE.
*/
static int get_mmu_address(CPUSH4State *env, hwaddr *physical,
- int *prot, target_ulong address,
+ int *prot, vaddr address,
MMUAccessType access_type)
{
int use_asid, n;
}
static int get_physical_address(CPUSH4State *env, hwaddr* physical,
- int *prot, target_ulong address,
+ int *prot, vaddr address,
MMUAccessType access_type)
{
/* P1, P2 and P4 areas do not use translation */