RISC-V: Add test for vec_duplicate + vmadd.vv signed combine with GR2VR cost 0, 1...

Add asm dump check and run test for vec_duplicate + vmadd.vv
combine to vmadd.vx, with the GR2VR cost is 0, 2 and 15.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c: Add asm check
	for vmadd.vx.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary.h: Add test
	helper macros.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_data.h: Add test
	data for run test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmadd-run-1-i16.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmadd-run-1-i32.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmadd-run-1-i64.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmadd-run-1-i8.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
index ad2dacd1f25ab5c6c85c181a0eb7d54264322f66..29cab3a2e614f0efff04fe82b42a092e79d2d1ec 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
@@ -25,3 +25,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-times {vaadd.vx} 2 } } */
 /* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vmadd.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
index ebcdb0aeb0f989da7b431d2704da4db0e143eb94..0e7c9675f5a35ddf464766abab2d208d76972e03 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
@@ -25,3 +25,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-times {vaadd.vx} 2 } } */
 /* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vmadd.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
index f15d7b552072a6a76e237548cedd1cae1261b8bf..1524e714200d8484244f0a7d4283ee9bdf470abe 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
@@ -28,3 +28,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
    } } } } */
 /* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vmadd.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
index c9973485e0acbc4464b913160526a204759e72ab..0967fc3980bd978e8b9c85b4fe84224efc4b7033 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
@@ -25,3 +25,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-times {vaadd.vx} 2 } } */
 /* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vmadd.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
index db272ef0f49ee52028bfff406205d33fc9abc271..fd0098d052f219a728c85a528ff3470ba1f4e112 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
@@ -25,3 +25,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vaadd.vx} } } */
 /* { dg-final { scan-assembler-not {vmacc.vx} } } */
 /* { dg-final { scan-assembler-not {vnmsac.vx} } } */
+/* { dg-final { scan-assembler-not {vmadd.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
index b3f99ba7c8b356c40760c9af48d7c267fff18560..e73ef30ca0f87b17bb3480edffe3ce9ff3667512 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
@@ -25,3 +25,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vaadd.vx} } } */
 /* { dg-final { scan-assembler-not {vmacc.vx} } } */
 /* { dg-final { scan-assembler-not {vnmsac.vx} } } */
+/* { dg-final { scan-assembler-not {vmadd.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
index 4fdf8f986fd09c77adf3234b45637a9309f8954a..ab4c6c22722ca18ca66f34457013c4eb049e621b 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
@@ -25,3 +25,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vaadd.vx} } } */
 /* { dg-final { scan-assembler-not {vmacc.vx} } } */
 /* { dg-final { scan-assembler-not {vnmsac.vx} } } */
+/* { dg-final { scan-assembler-not {vmadd.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
index 02cf934f943f688ae471714a2c5d7f6d688aacbc..cb9c25305ce1f204968419539dee7569212399f3 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
@@ -25,3 +25,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vaadd.vx} } } */
 /* { dg-final { scan-assembler-not {vmacc.vx} } } */
 /* { dg-final { scan-assembler-not {vnmsac.vx} } } */
+/* { dg-final { scan-assembler-not {vmadd.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
index 94f83ffe588f70201f04aa8b29a89016d20832a8..881917b95f4f9e48b85d10b8a1e9adff771dc126 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
@@ -25,3 +25,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vaadd.vx} } } */
 /* { dg-final { scan-assembler-not {vmacc.vx} } } */
 /* { dg-final { scan-assembler-not {vnmsac.vx} } } */
+/* { dg-final { scan-assembler-not {vmadd.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
index 77468092cfe91c5ff6c1d616fe27bb1d9e70bc3e..e60e2321b3b3e0258ce9e32d48b14187545475c6 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
@@ -25,3 +25,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vaadd.vx} } } */
 /* { dg-final { scan-assembler-not {vmacc.vx} } } */
 /* { dg-final { scan-assembler-not {vnmsac.vx} } } */
+/* { dg-final { scan-assembler-not {vmadd.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
index ed31e7965ccbb4ca857c9c1a82a5bfdcb8a8cee0..3aade3c1f011740ce36c444aa1da30f0a7446162 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
@@ -25,3 +25,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vaadd.vx} } } */
 /* { dg-final { scan-assembler-not {vmacc.vx} } } */
 /* { dg-final { scan-assembler-not {vnmsac.vx} } } */
+/* { dg-final { scan-assembler-not {vmadd.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
index b9d1ddc039be17339a9f21c0a3004a0cec3e47ec..3c7935d75f2972dfac9d975d8f79d0d23ddc7a9c 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
@@ -25,3 +25,4 @@ TEST_TERNARY_VX_SIGNED_0(T)
 /* { dg-final { scan-assembler-not {vaadd.vx} } } */
 /* { dg-final { scan-assembler-not {vmacc.vx} } } */
 /* { dg-final { scan-assembler-not {vnmsac.vx} } } */
+/* { dg-final { scan-assembler-not {vmadd.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary.h
index a03bd6196bd5ada070155bf497038c60c0df9fea..30f3325a167e1ce35773643746d5f41d1c2ab7b9 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary.h
@@ -30,8 +30,24 @@ test_vx_ternary_##NAME##_##T##_case_0 (T * restrict vd, T * restrict vs2, \
 #define RUN_VX_TERNARY_CASE_0_WRAP(T, NAME, vd, vs2, rs1, n) \
   RUN_VX_TERNARY_CASE_0(T, NAME, vd, vs2, rs1, n)
 
+#define DEF_VX_TERNARY_CASE_1(T, OP_1, OP_2, NAME)                        \
+void                                                                      \
+test_vx_ternary_##NAME##_##T##_case_1 (T * restrict vd, T * restrict vs2, \
+                                       T rs1, unsigned n)                 \
+{                                                                         \
+  for (unsigned i = 0; i < n; i++)                                        \
+    vd[i] = vs2[i] OP_2 rs1 OP_1 vd[i];                                   \
+}
+#define DEF_VX_TERNARY_CASE_1_WRAP(T, OP_1, OP_2, NAME) \
+  DEF_VX_TERNARY_CASE_1(T, OP_1, OP_2, NAME)
+#define RUN_VX_TERNARY_CASE_1(T, NAME, vd, vs2, rs1, n) \
+  test_vx_ternary_##NAME##_##T##_case_1 (vd, vs2, rs1, n)
+#define RUN_VX_TERNARY_CASE_1_WRAP(T, NAME, vd, vs2, rs1, n) \
+  RUN_VX_TERNARY_CASE_1(T, NAME, vd, vs2, rs1, n)
+
 #define TEST_TERNARY_VX_SIGNED_0(T)                                \
   DEF_VX_TERNARY_CASE_0_WRAP(T, *, +, macc)                        \
+  DEF_VX_TERNARY_CASE_1_WRAP(T, *, +, madd)                        \
   DEF_VX_TERNARY_CASE_0_WRAP(T, *, -, nmsac)                       \
 
 #define TEST_TERNARY_VX_UNSIGNED_0(T)                              \

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_data.h
index 9ac1a7ddc3a836e2eab1949b73ea3472cfe428cc..3155d6a693be1969d4d98efb258ce33c2a39b7d8 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_data.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_ternary_data.h
@@ -742,4 +742,188 @@ uint64_t TEST_TERNARY_DATA(uint64_t, nmsac)[][4][N] =
   },
 };
 
+int8_t TEST_TERNARY_DATA(int8_t, madd)[][4][N] =
+{
+  {
+    { 1 }, /* rs1 */
+    { /* vs2 */
+       1,  1,  1,  1,
+       2,  2,  2,  2,
+       0,  0,  0,  0,
+      -1, -1, -1, -1,
+    },
+    { /* vd */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+      -1, -1, -1, -1,
+      -2, -2, -2, -2,
+    },
+    {
+       1,  1,  1,  1,
+       3,  3,  3,  3,
+      -1, -1, -1, -1,
+      -3, -3, -3, -3,
+    },
+  },
+  {
+    { 127 }, /* rs1 */
+    { /* vs2 */
+       127,  127,  127,  127,
+         2,    2,    2,    2,
+         0,    0,    0,    0,
+      -128, -128, -128, -128,
+    },
+    { /* vd */
+       0,  0,  0,  0,
+       9,  9,  9,  9,
+      -8, -8, -8, -8,
+      -2, -2, -2, -2,
+    },
+    {
+       127,  127,  127,  127,
+       121,  121,  121,  121,
+         8,    8,    8,    8,
+      -126, -126, -126, -126,
+    },
+  },
+};
+
+int16_t TEST_TERNARY_DATA(int16_t, madd)[][4][N] =
+{
+  {
+    { 1 }, /* rs1 */
+    { /* vs2 */
+       1,  1,  1,  1,
+       2,  2,  2,  2,
+       0,  0,  0,  0,
+      -1, -1, -1, -1,
+    },
+    { /* vd */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+      -1, -1, -1, -1,
+      -2, -2, -2, -2,
+    },
+    {
+       1,  1,  1,  1,
+       3,  3,  3,  3,
+      -1, -1, -1, -1,
+      -3, -3, -3, -3,
+    },
+  },
+  {
+    { 32767 }, /* rs1 */
+    { /* vs2 */
+       32767,  32767,  32767,  32767,
+           2,      2,      2,      2,
+           0,      0,      0,      0,
+      -32768, -32768, -32768, -32768,
+    },
+    { /* vd */
+       0,  0,  0,  0,
+       9,  9,  9,  9,
+      -8, -8, -8, -8,
+      -2, -2, -2, -2,
+    },
+    {
+       32767,  32767,  32767,  32767,
+       32761,  32761,  32761,  32761,
+           8,      8,      8,      8,
+      -32766, -32766, -32766, -32766,
+    },
+  },
+};
+
+int32_t TEST_TERNARY_DATA(int32_t, madd)[][4][N] =
+{
+  {
+    { 1 }, /* rs1 */
+    { /* vs2 */
+       1,  1,  1,  1,
+       2,  2,  2,  2,
+       0,  0,  0,  0,
+      -1, -1, -1, -1,
+    },
+    { /* vd */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+      -1, -1, -1, -1,
+      -2, -2, -2, -2,
+    },
+    {
+       1,  1,  1,  1,
+       3,  3,  3,  3,
+      -1, -1, -1, -1,
+      -3, -3, -3, -3,
+    },
+  },
+  {
+    { 2147483647 }, /* rs1 */
+    { /* vs2 */
+       2147483647,  2147483647,  2147483647,  2147483647,
+                2,           2,           2,           2,
+                0,           0,           0,           0,
+      -2147483648, -2147483648, -2147483648, -2147483648,
+    },
+    { /* vd */
+       0,  0,  0,  0,
+       9,  9,  9,  9,
+      -8, -8, -8, -8,
+      -2, -2, -2, -2,
+    },
+    {
+       2147483647,  2147483647,  2147483647,  2147483647,
+       2147483641,  2147483641,  2147483641,  2147483641,
+                8,           8,           8,           8,
+      -2147483646, -2147483646, -2147483646, -2147483646,
+    },
+  },
+};
+
+int64_t TEST_TERNARY_DATA(int64_t, madd)[][4][N] =
+{
+  {
+    { 1 }, /* rs1 */
+    { /* vs2 */
+       1,  1,  1,  1,
+       2,  2,  2,  2,
+       0,  0,  0,  0,
+      -1, -1, -1, -1,
+    },
+    { /* vd */
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+      -1, -1, -1, -1,
+      -2, -2, -2, -2,
+    },
+    {
+       1,  1,  1,  1,
+       3,  3,  3,  3,
+      -1, -1, -1, -1,
+      -3, -3, -3, -3,
+    },
+  },
+  {
+    { 9223372036854775807ull }, /* rs1 */
+    { /* vs2 */
+       9223372036854775807ull,  9223372036854775807ull,  9223372036854775807ull,  9223372036854775807ull,
+                            2,                       2,                       2,                       2,
+                            0,                       0,                       0,                       0,
+      -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull,
+    },
+    { /* vd */
+       0,  0,  0,  0,
+       9,  9,  9,  9,
+      -8, -8, -8, -8,
+      -2, -2, -2, -2,
+    },
+    {
+       9223372036854775807ull,  9223372036854775807ull,  9223372036854775807ull,  9223372036854775807ull,
+       9223372036854775801ull,  9223372036854775801ull,  9223372036854775801ull,  9223372036854775801ull,
+                            8,                       8,                       8,                       8,
+      -9223372036854775806ull, -9223372036854775806ull, -9223372036854775806ull, -9223372036854775806ull,
+    },
+  },
+};
+
 #endif

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmadd-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmadd-run-1-i16.c
new file mode 100644 (file)
index 0000000..5c76ec0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmadd-run-1-i16.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_ternary.h"
+#include "vx_ternary_data.h"
+
+#define T          int16_t
+#define NAME       madd
+#define TEST_DATA  TEST_TERNARY_DATA_WRAP(T, NAME)
+
+DEF_VX_TERNARY_CASE_1_WRAP(T, *, +, NAME)
+
+#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \
+  RUN_VX_TERNARY_CASE_1_WRAP(T, NAME, vd, vs2, rs1, n)
+
+#include "vx_ternary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmadd-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmadd-run-1-i32.c
new file mode 100644 (file)
index 0000000..dfbe96b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmadd-run-1-i32.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_ternary.h"
+#include "vx_ternary_data.h"
+
+#define T          int32_t
+#define NAME       madd
+#define TEST_DATA  TEST_TERNARY_DATA_WRAP(T, NAME)
+
+DEF_VX_TERNARY_CASE_1_WRAP(T, *, +, NAME)
+
+#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \
+  RUN_VX_TERNARY_CASE_1_WRAP(T, NAME, vd, vs2, rs1, n)
+
+#include "vx_ternary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmadd-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmadd-run-1-i64.c
new file mode 100644 (file)
index 0000000..b32cd12
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmadd-run-1-i64.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_ternary.h"
+#include "vx_ternary_data.h"
+
+#define T          int64_t
+#define NAME       madd
+#define TEST_DATA  TEST_TERNARY_DATA_WRAP(T, NAME)
+
+DEF_VX_TERNARY_CASE_1_WRAP(T, *, +, NAME)
+
+#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \
+  RUN_VX_TERNARY_CASE_1_WRAP(T, NAME, vd, vs2, rs1, n)
+
+#include "vx_ternary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmadd-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmadd-run-1-i8.c
new file mode 100644 (file)
index 0000000..7975e4e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmadd-run-1-i8.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_ternary.h"
+#include "vx_ternary_data.h"
+
+#define T          int8_t
+#define NAME       madd
+#define TEST_DATA  TEST_TERNARY_DATA_WRAP(T, NAME)
+
+DEF_VX_TERNARY_CASE_1_WRAP(T, *, +, NAME)
+
+#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \
+  RUN_VX_TERNARY_CASE_1_WRAP(T, NAME, vd, vs2, rs1, n)
+
+#include "vx_ternary_run.h"