Xilinx: ARM: Initialize DDR TrustZone to non-secure in lowlevel_init

diff --git a/board/xilinx/dfe/lowlevel_init.S b/board/xilinx/dfe/lowlevel_init.S
index 3e6f90f8c56e0ccbf76d2becdd54f0fc3e6ba11a..4eb5b0b14a1317208fae6477c021697170cb7530 100755 (executable)
--- a/board/xilinx/dfe/lowlevel_init.S
+++ b/board/xilinx/dfe/lowlevel_init.S
@@ -15,6 +15,27 @@
 .globl lowlevel_init
 lowlevel_init:
 
+       # unlock SLCR
+       ldr r1, =(XPSS_SYS_CTRL_BASEADDR + 8)
+       ldr r2, =0x767BDF0D
+       str r2, [r1]
+
+       # clear resets on AXI fabric ports
+       ldr r1, =(XPSS_SYS_CTRL_BASEADDR + 0x240)
+       ldr r2, =0x00F00F0F
+       str r2, [r1]
+
+       # Set DDR trust zone non-secure
+       ldr r1, =(XPSS_SYS_CTRL_BASEADDR + 0x430)
+       ldr r2, =0xFFFFFFFF
+       str r2, [r1]
+
+       # relock SLCR
+       ldr r1, =(XPSS_SYS_CTRL_BASEADDR + 0x4)
+       ldr r2, =0x767BDF0D
+       str r2, [r1]
+
+       # Reset DDR controller
        ldr r1, =(XPSS_DDR_CTRL_BASEADDR + 0)
        ldr r2, =0x200
        str r2, [r1]
@@ -95,4 +116,12 @@ lowlevel_init:
        ldr r2, =0x201
        str r2, [r1]
 
+# Delay spin loop
+       ldr r4, =0x1000000
+loop:  
+       sub r4, r4, #1
+       cmp r4, #0
+       bne loop
+
        mov pc, lr
+