case Creg_ARM_R12: return eec->uregs->r12;
case Creg_ARM_R7: return eec->uregs->r7;
# elif defined(VGA_s390x)
- case Creg_IA_IP: return eec->uregs->ia;
- case Creg_IA_SP: return eec->uregs->sp;
- case Creg_IA_BP: return eec->uregs->fp;
- case Creg_S390_R14: return eec->uregs->lr;
+ case Creg_S390_IA: return eec->uregs->ia;
+ case Creg_S390_SP: return eec->uregs->sp;
+ case Creg_S390_FP: return eec->uregs->fp;
+ case Creg_S390_LR: return eec->uregs->lr;
# elif defined(VGA_mips32) || defined(VGA_mips64)
case Creg_IA_IP: return eec->uregs->pc;
case Creg_IA_SP: return eec->uregs->sp;
Creg_ARM_R14,
Creg_ARM_R7,
Creg_ARM64_X30,
- Creg_S390_R14,
+ Creg_S390_IA,
+ Creg_S390_SP,
+ Creg_S390_FP,
+ Creg_S390_LR,
Creg_MIPS_RA
}
CfiReg;
sizeof(CfiExpr) );
si_m->ra_how = CFIR_EXPR;
si_m->ra_off = ML_(CfiExpr_CfiReg)( debuginfo->cfsi_exprs,
- Creg_S390_R14);
+ Creg_S390_LR);
}
/* knock out some obviously stupid cases */
return ML_(CfiExpr_CfiReg)( dstxa, Creg_ARM_R15 ); /* correct? */
# elif defined(VGA_s390x)
if (dwreg == SP_REG)
- return ML_(CfiExpr_CfiReg)( dstxa, Creg_IA_SP );
+ return ML_(CfiExpr_CfiReg)( dstxa, Creg_S390_SP );
if (dwreg == FP_REG)
- return ML_(CfiExpr_CfiReg)( dstxa, Creg_IA_BP );
+ return ML_(CfiExpr_CfiReg)( dstxa, Creg_S390_FP );
if (dwreg == srcuc->ra_reg)
- return ML_(CfiExpr_CfiReg)( dstxa, Creg_IA_IP ); /* correct? */
+ return ML_(CfiExpr_CfiReg)( dstxa, Creg_S390_IA );
# elif defined(VGA_mips32) || defined(VGA_mips64)
if (dwreg == SP_REG)
return ML_(CfiExpr_CfiReg)( dstxa, Creg_IA_SP );
case Creg_ARM_R7: VG_(printf)("R7"); break;
case Creg_ARM64_X30: VG_(printf)("X30"); break;
case Creg_MIPS_RA: VG_(printf)("RA"); break;
- case Creg_S390_R14: VG_(printf)("R14"); break;
+ case Creg_S390_IA: VG_(printf)("IA"); break;
+ case Creg_S390_SP: VG_(printf)("SP"); break;
+ case Creg_S390_FP: VG_(printf)("FP"); break;
+ case Creg_S390_LR: VG_(printf)("LR"); break;
default: vg_assert(0);
}
}