ARCv2: PAE40: Explicitly set MSB counterpart of SLC region ops addresses

commit 7d79cee2c6540ea64dd917a14e2fd63d4ac3d3c0 upstream.

It is necessary to explicitly set both SLC_AUX_RGN_START1 and SLC_AUX_RGN_END1
which hold MSB bits of the physical address correspondingly of region start
and end otherwise SLC region operation is executed in unpredictable manner

Without this patch, SLC flushes on HSDK (IOC disabled) were taking
seconds.

Reported-by: Vladimir Kondratiev <vladimir.kondratiev@intel.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
[vgupta: PAR40 regs only written if PAE40 exist]
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h
index 210ef3e7233224b099bd40e85106d2d864e70987..0ddd7144c492bd4bfc754f764dfb7114ba383563 100644 (file)
--- a/arch/arc/include/asm/cache.h
+++ b/arch/arc/include/asm/cache.h
@@ -88,7 +88,9 @@ extern int ioc_exists;
 #define ARC_REG_SLC_FLUSH      0x904
 #define ARC_REG_SLC_INVALIDATE 0x905
 #define ARC_REG_SLC_RGN_START  0x914
+#define ARC_REG_SLC_RGN_START1 0x915
 #define ARC_REG_SLC_RGN_END    0x916
+#define ARC_REG_SLC_RGN_END1   0x917
 
 /* Bit val in SLC_CONTROL */
 #define SLC_CTRL_IM            0x040

diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c
index d81b6d7e11e79d64b34de28acc798ceaf6a2d1b5..9a84cbdd44b01827dc9e0c928bc00855c6382ecb 100644 (file)
--- a/arch/arc/mm/cache.c
+++ b/arch/arc/mm/cache.c
@@ -543,6 +543,7 @@ noinline void slc_op(phys_addr_t paddr, unsigned long sz, const int op)
        static DEFINE_SPINLOCK(lock);
        unsigned long flags;
        unsigned int ctrl;
+       phys_addr_t end;
 
        spin_lock_irqsave(&lock, flags);
 
@@ -572,8 +573,16 @@ noinline void slc_op(phys_addr_t paddr, unsigned long sz, const int op)
         * END needs to be setup before START (latter triggers the operation)
         * END can't be same as START, so add (l2_line_sz - 1) to sz
         */
-       write_aux_reg(ARC_REG_SLC_RGN_END, (paddr + sz + l2_line_sz - 1));
-       write_aux_reg(ARC_REG_SLC_RGN_START, paddr);
+       end = paddr + sz + l2_line_sz - 1;
+       if (is_pae40_enabled())
+               write_aux_reg(ARC_REG_SLC_RGN_END1, upper_32_bits(end));
+
+       write_aux_reg(ARC_REG_SLC_RGN_END, lower_32_bits(end));
+
+       if (is_pae40_enabled())
+               write_aux_reg(ARC_REG_SLC_RGN_START1, upper_32_bits(paddr));
+
+       write_aux_reg(ARC_REG_SLC_RGN_START, lower_32_bits(paddr));
 
        while (read_aux_reg(ARC_REG_SLC_CTRL) & SLC_CTRL_BUSY);