}
EXPORT_SYMBOL(rtw89_pci_parse_rpp);
+void rtw89_pci_parse_rpp_v1(struct rtw89_dev *rtwdev, void *_rpp,
+ struct rtw89_pci_rpp_info *rpp_info)
+{
+ const struct rtw89_pci_rpp_fmt_v1 *rpp = _rpp;
+
+ rpp_info->seq = le32_get_bits(rpp->w0, RTW89_PCI_RPP_W0_PCIE_SEQ_V1_MASK);
+ rpp_info->qsel = le32_get_bits(rpp->w1, RTW89_PCI_RPP_W1_QSEL_V1_MASK);
+ rpp_info->tx_status = le32_get_bits(rpp->w0, RTW89_PCI_RPP_W0_TX_STATUS_V1_MASK);
+ rpp_info->txch = le32_get_bits(rpp->w0, RTW89_PCI_RPP_W0_DMA_CH_MASK);
+}
+EXPORT_SYMBOL(rtw89_pci_parse_rpp_v1);
+
static void rtw89_pci_release_rpp(struct rtw89_dev *rtwdev, void *rpp)
{
struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
__le32 dword;
} __packed;
+#define RTW89_PCI_RPP_W0_MACID_V1_MASK GENMASK(9, 0)
+#define RTW89_PCI_RPP_W0_DMA_CH_MASK GENMASK(13, 10)
+#define RTW89_PCI_RPP_W0_TX_STATUS_V1_MASK GENMASK(16, 14)
+#define RTW89_PCI_RPP_W0_PCIE_SEQ_V1_MASK GENMASK(31, 17)
+#define RTW89_PCI_RPP_W1_QSEL_V1_MASK GENMASK(5, 0)
+#define RTW89_PCI_RPP_W1_TID_IND BIT(6)
+#define RTW89_PCI_RPP_W1_CHANGE_LINK BIT(7)
+
+struct rtw89_pci_rpp_fmt_v1 {
+ __le32 w0;
+ __le32 w1;
+} __packed;
+
struct rtw89_pci_rx_bd_32 {
__le16 buf_size;
__le16 opt;
dma_addr_t dma, u8 *add_info_nr);
void rtw89_pci_parse_rpp(struct rtw89_dev *rtwdev, void *_rpp,
struct rtw89_pci_rpp_info *rpp_info);
+void rtw89_pci_parse_rpp_v1(struct rtw89_dev *rtwdev, void *_rpp,
+ struct rtw89_pci_rpp_info *rpp_info);
void rtw89_pci_ctrl_dma_all(struct rtw89_dev *rtwdev, bool enable);
void rtw89_pci_config_intr_mask(struct rtw89_dev *rtwdev);
void rtw89_pci_config_intr_mask_v1(struct rtw89_dev *rtwdev);