drm/i915/dram: s/wm_lv0.../has_16gb_dimms/

The DRAM code shouldn't know anything about watermarks. Rename
wm_lv_0_adjust_needed to has_16gb_dimms. How this gets used is
up to the watermark code.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250902133113.18778-5-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 33885d619a97102596fbdaefc6dc4ad720e80cd2..ae3ce0d65cfc39d3b4666602662a046e1a275d6d 100644 (file)
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -3214,7 +3214,7 @@ adjust_wm_latency(struct intel_display *display,
         * any underrun. If not able to get Dimm info assume 16GB dimm
         * to avoid any underrun.
         */
-       if (!display->platform.dg2 && dram_info->wm_lv_0_adjust_needed)
+       if (!display->platform.dg2 && dram_info->has_16gb_dimms)
                wm[0] += 1;
 }
 

diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c b/drivers/gpu/drm/i915/soc/intel_dram.c
index b4f0793f778dc171970eadaf0e2975f4d61e3c18..efb72e137748e125c1d3925d16ab5140ddc77120 100644 (file)
--- a/drivers/gpu/drm/i915/soc/intel_dram.c
+++ b/drivers/gpu/drm/i915/soc/intel_dram.c
@@ -428,7 +428,7 @@ skl_dram_get_channels_info(struct drm_i915_private *i915, struct dram_info *dram
                return -EINVAL;
        }
 
-       dram_info->wm_lv_0_adjust_needed = ch0.is_16gb_dimm || ch1.is_16gb_dimm;
+       dram_info->has_16gb_dimms = ch0.is_16gb_dimm || ch1.is_16gb_dimm;
 
        dram_info->symmetric_memory = intel_is_dram_symmetric(&ch0, &ch1);
 
@@ -673,7 +673,7 @@ static int gen11_get_dram_info(struct drm_i915_private *i915, struct dram_info *
 
 static int gen12_get_dram_info(struct drm_i915_private *i915, struct dram_info *dram_info)
 {
-       dram_info->wm_lv_0_adjust_needed = false;
+       dram_info->has_16gb_dimms = false;
 
        return icl_pcode_read_mem_global_info(i915, dram_info);
 }
@@ -737,10 +737,10 @@ int intel_dram_detect(struct drm_i915_private *i915)
        i915->dram_info = dram_info;
 
        /*
-        * Assume level 0 watermark latency adjustment is needed until proven
+        * Assume 16Gb DIMMs are present until proven
         * otherwise, this w/a is not needed by bxt/glk.
         */
-       dram_info->wm_lv_0_adjust_needed = !IS_BROXTON(i915) && !IS_GEMINILAKE(i915);
+       dram_info->has_16gb_dimms = !IS_BROXTON(i915) && !IS_GEMINILAKE(i915);
 
        if (DISPLAY_VER(display) >= 14)
                ret = xelpdp_get_dram_info(i915, dram_info);
@@ -766,8 +766,8 @@ int intel_dram_detect(struct drm_i915_private *i915)
 
        drm_dbg_kms(&i915->drm, "DRAM channels: %u\n", dram_info->num_channels);
 
-       drm_dbg_kms(&i915->drm, "Watermark level 0 adjustment needed: %s\n",
-                   str_yes_no(dram_info->wm_lv_0_adjust_needed));
+       drm_dbg_kms(&i915->drm, "16Gb DIMMs: %s\n",
+                   str_yes_no(dram_info->has_16gb_dimms));
 
        return 0;
 }

diff --git a/drivers/gpu/drm/i915/soc/intel_dram.h b/drivers/gpu/drm/i915/soc/intel_dram.h
index 6212944d44aa8c9d0f6adb88cd216c3b76fbd372..03a973f1c941df018f3906e537af6246a440b71d 100644 (file)
--- a/drivers/gpu/drm/i915/soc/intel_dram.h
+++ b/drivers/gpu/drm/i915/soc/intel_dram.h
@@ -31,7 +31,7 @@ struct dram_info {
        u8 num_qgv_points;
        u8 num_psf_gv_points;
        bool symmetric_memory;
-       bool wm_lv_0_adjust_needed;
+       bool has_16gb_dimms;
 };
 
 void intel_dram_edram_detect(struct drm_i915_private *i915);