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arm64: zynqmp: Add new psu_init* files for zcu104 with proper DP setup
authorMichal Simek <michal.simek@xilinx.com>
Wed, 26 Jul 2017 07:18:44 +0000 (09:18 +0200)
committerMichal Simek <michal.simek@xilinx.com>
Thu, 27 Jul 2017 07:37:07 +0000 (09:37 +0200)
Changes are related DP clock setup.
psu_init* are generated with Vivado v2017.3 with these paramaters:
-board zcu104 -build hdf -ddr ddr4auto2133_component -clk video

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
board/xilinx/zynqmp/zynqmp-zcu104-revA/psu_init_gpl.c patch | blob | blame | history
board/xilinx/zynqmp/zynqmp-zcu104-revA/psu_init_gpl.h patch | blob | blame | history

diff --git a/board/xilinx/zynqmp/zynqmp-zcu104-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu104-revA/psu_init_gpl.c
index 7866248cbbbeefe5225ff09bc917f70f12be007f..5368b36d1df7af4c68d06167bf1f96d9a3def389 100644 (file)
--- a/board/xilinx/zynqmp/zynqmp-zcu104-revA/psu_init_gpl.c
+++ b/board/xilinx/zynqmp/zynqmp-zcu104-revA/psu_init_gpl.c
@@ -104,16 +104,16 @@ unsigned long psu_pll_init_data(void)
     *  PSU_CRL_APB_RPLL_CTRL_PRE_SRC                               0x0
 
     * The integer portion of the feedback divider to the PLL
-    *  PSU_CRL_APB_RPLL_CTRL_FBDIV                                 0x48
+    *  PSU_CRL_APB_RPLL_CTRL_FBDIV                                 0x46
 
     * This turns on the divide by 2 that is inside of the PLL. This does not c
     * hange the VCO frequency, just the output frequency
     *  PSU_CRL_APB_RPLL_CTRL_DIV2                                  0x1
 
     * PLL Basic Control
-    * (OFFSET, MASK, VALUE)      (0XFF5E0030, 0x00717F00U ,0x00014800U)
+    * (OFFSET, MASK, VALUE)      (0XFF5E0030, 0x00717F00U ,0x00014600U)
     */
-       PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00717F00U, 0x00014800U);
+       PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00717F00U, 0x00014600U);
 /*##################################################################### */
 
     /*
@@ -753,15 +753,15 @@ unsigned long psu_pll_init_data(void)
     *  PSU_CRF_APB_VPLL_CFG_LFHF                                   0x3
 
     * Lock circuit counter setting
-    *  PSU_CRF_APB_VPLL_CFG_LOCK_CNT                               0x28a
+    *  PSU_CRF_APB_VPLL_CFG_LOCK_CNT                               0x258
 
     * Lock circuit configuration settings for lock windowsize
     *  PSU_CRF_APB_VPLL_CFG_LOCK_DLY                               0x3f
 
     * Helper data. Values are to be looked up in a table from Data Sheet
-    * (OFFSET, MASK, VALUE)      (0XFD1A003C, 0xFE7FEDEFU ,0x7E514C62U)
+    * (OFFSET, MASK, VALUE)      (0XFD1A003C, 0xFE7FEDEFU ,0x7E4B0C62U)
     */
-       PSU_Mask_Write(CRF_APB_VPLL_CFG_OFFSET, 0xFE7FEDEFU, 0x7E514C62U);
+       PSU_Mask_Write(CRF_APB_VPLL_CFG_OFFSET, 0xFE7FEDEFU, 0x7E4B0C62U);
 /*##################################################################### */
 
     /*
@@ -776,16 +776,16 @@ unsigned long psu_pll_init_data(void)
     *  PSU_CRF_APB_VPLL_CTRL_PRE_SRC                               0x0
 
     * The integer portion of the feedback divider to the PLL
-    *  PSU_CRF_APB_VPLL_CTRL_FBDIV                                 0x39
+    *  PSU_CRF_APB_VPLL_CTRL_FBDIV                                 0x47
 
     * This turns on the divide by 2 that is inside of the PLL. This does not c
     * hange the VCO frequency, just the output frequency
     *  PSU_CRF_APB_VPLL_CTRL_DIV2                                  0x1
 
     * PLL Basic Control
-    * (OFFSET, MASK, VALUE)      (0XFD1A0038, 0x00717F00U ,0x00013900U)
+    * (OFFSET, MASK, VALUE)      (0XFD1A0038, 0x00717F00U ,0x00014700U)
     */
-       PSU_Mask_Write(CRF_APB_VPLL_CTRL_OFFSET, 0x00717F00U, 0x00013900U);
+       PSU_Mask_Write(CRF_APB_VPLL_CTRL_OFFSET, 0x00717F00U, 0x00014700U);
 /*##################################################################### */
 
     /*
@@ -893,16 +893,16 @@ unsigned long psu_pll_init_data(void)
     * Fractional SDM bypass control. When 0, PLL is in integer mode and it ign
     * ores all fractional data. When 1, PLL is in fractional mode and uses DAT
     * A of this register for the fractional portion of the feedback divider.
-    *  PSU_CRF_APB_VPLL_FRAC_CFG_ENABLED                           0x1
+    *  PSU_CRF_APB_VPLL_FRAC_CFG_ENABLED                           0x0
 
     * Fractional value for the Feedback value.
-    *  PSU_CRF_APB_VPLL_FRAC_CFG_DATA                              0x820c
+    *  PSU_CRF_APB_VPLL_FRAC_CFG_DATA                              0x0
 
     * Fractional control for the PLL
-    * (OFFSET, MASK, VALUE)      (0XFD1A0040, 0x8000FFFFU ,0x8000820CU)
+    * (OFFSET, MASK, VALUE)      (0XFD1A0040, 0x8000FFFFU ,0x00000000U)
     */
        PSU_Mask_Write(CRF_APB_VPLL_FRAC_CFG_OFFSET,
-               0x8000FFFFU, 0x8000820CU);
+               0x8000FFFFU, 0x00000000U);
 /*##################################################################### */
 
 
@@ -1046,18 +1046,18 @@ unsigned long psu_clock_init_data(void)
     *  PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR1                         0x1
 
     * 6 bit divider
-    *  PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR0                         0x6
+    *  PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR0                         0x8
 
     * 000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled af
     * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
     *  usually an issue, but designers must be aware.)
-    *  PSU_CRL_APB_SDIO1_REF_CTRL_SRCSEL                           0x2
+    *  PSU_CRL_APB_SDIO1_REF_CTRL_SRCSEL                           0x0
 
     * This register controls this reference clock
-    * (OFFSET, MASK, VALUE)      (0XFF5E0070, 0x013F3F07U ,0x01010602U)
+    * (OFFSET, MASK, VALUE)      (0XFF5E0070, 0x013F3F07U ,0x01010800U)
     */
        PSU_Mask_Write(CRL_APB_SDIO1_REF_CTRL_OFFSET,
-               0x013F3F07U, 0x01010602U);
+               0x013F3F07U, 0x01010800U);
 /*##################################################################### */
 
     /*
@@ -1220,17 +1220,17 @@ unsigned long psu_clock_init_data(void)
     *  PSU_CRL_APB_PCAP_CTRL_CLKACT                                0x1
 
     * 6 bit divider
-    *  PSU_CRL_APB_PCAP_CTRL_DIVISOR0                              0x6
+    *  PSU_CRL_APB_PCAP_CTRL_DIVISOR0                              0x8
 
     * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
     * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
     *  usually an issue, but designers must be aware.)
-    *  PSU_CRL_APB_PCAP_CTRL_SRCSEL                                0x2
+    *  PSU_CRL_APB_PCAP_CTRL_SRCSEL                                0x0
 
     * This register controls this reference clock
-    * (OFFSET, MASK, VALUE)      (0XFF5E00A4, 0x01003F07U ,0x01000602U)
+    * (OFFSET, MASK, VALUE)      (0XFF5E00A4, 0x01003F07U ,0x01000800U)
     */
-       PSU_Mask_Write(CRL_APB_PCAP_CTRL_OFFSET, 0x01003F07U, 0x01000602U);
+       PSU_Mask_Write(CRL_APB_PCAP_CTRL_OFFSET, 0x01003F07U, 0x01000800U);
 /*##################################################################### */
 
     /*
@@ -1375,18 +1375,18 @@ unsigned long psu_clock_init_data(void)
     *  PSU_CRL_APB_PL2_REF_CTRL_DIVISOR1                           0x1
 
     * 6 bit divider
-    *  PSU_CRL_APB_PL2_REF_CTRL_DIVISOR0                           0x4
+    *  PSU_CRL_APB_PL2_REF_CTRL_DIVISOR0                           0x5
 
     * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
     * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
     *  usually an issue, but designers must be aware.)
-    *  PSU_CRL_APB_PL2_REF_CTRL_SRCSEL                             0x2
+    *  PSU_CRL_APB_PL2_REF_CTRL_SRCSEL                             0x0
 
     * This register controls this reference clock
-    * (OFFSET, MASK, VALUE)      (0XFF5E00C8, 0x013F3F07U ,0x01010402U)
+    * (OFFSET, MASK, VALUE)      (0XFF5E00C8, 0x013F3F07U ,0x01010500U)
     */
        PSU_Mask_Write(CRL_APB_PL2_REF_CTRL_OFFSET,
-               0x013F3F07U, 0x01010402U);
+               0x013F3F07U, 0x01010500U);
 /*##################################################################### */
 
     /*
@@ -1399,18 +1399,18 @@ unsigned long psu_clock_init_data(void)
     *  PSU_CRL_APB_PL3_REF_CTRL_DIVISOR1                           0x1
 
     * 6 bit divider
-    *  PSU_CRL_APB_PL3_REF_CTRL_DIVISOR0                           0x3
+    *  PSU_CRL_APB_PL3_REF_CTRL_DIVISOR0                           0x4
 
     * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
     * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
     *  usually an issue, but designers must be aware.)
-    *  PSU_CRL_APB_PL3_REF_CTRL_SRCSEL                             0x2
+    *  PSU_CRL_APB_PL3_REF_CTRL_SRCSEL                             0x0
 
     * This register controls this reference clock
-    * (OFFSET, MASK, VALUE)      (0XFF5E00CC, 0x013F3F07U ,0x01010302U)
+    * (OFFSET, MASK, VALUE)      (0XFF5E00CC, 0x013F3F07U ,0x01010400U)
     */
        PSU_Mask_Write(CRL_APB_PL3_REF_CTRL_OFFSET,
-               0x013F3F07U, 0x01010302U);
+               0x013F3F07U, 0x01010400U);
 /*##################################################################### */
 
     /*
@@ -1456,21 +1456,21 @@ unsigned long psu_clock_init_data(void)
     * Register : TIMESTAMP_REF_CTRL @ 0XFF5E0128
 
     * 6 bit divider
-    *  PSU_CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0                     1
+    *  PSU_CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0                     0xf
 
     * 1XX = pss_ref_clk; 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may
     *  only be toggled after 4 cycles of the old clock and 4 cycles of the new
     *  clock. This is not usually an issue, but designers must be aware.)
-    *  PSU_CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL                       4
+    *  PSU_CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL                       0x0
 
     * Clock active signal. Switch to 0 to disable the clock
-    *  PSU_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT                       1
+    *  PSU_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT                       0x1
 
     * This register controls this reference clock
-    * (OFFSET, MASK, VALUE)      (0XFF5E0128, 0x01003F07U ,0x01000104U)
+    * (OFFSET, MASK, VALUE)      (0XFF5E0128, 0x01003F07U ,0x01000F00U)
     */
        PSU_Mask_Write(CRL_APB_TIMESTAMP_REF_CTRL_OFFSET,
-               0x01003F07U, 0x01000104U);
+               0x01003F07U, 0x01000F00U);
 /*##################################################################### */
 
     /*
@@ -1501,22 +1501,22 @@ unsigned long psu_clock_init_data(void)
     *  PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1                      0x1
 
     * 6 bit divider
-    *  PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0                      0x3
+    *  PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0                      0x4
 
     * 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (T
     * his signal may only be toggled after 4 cycles of the old clock and 4 cyc
     * les of the new clock. This is not usually an issue, but designers must b
     * e aware.)
-    *  PSU_CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL                        0x3
+    *  PSU_CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL                        0x0
 
     * Clock active signal. Switch to 0 to disable the clock
     *  PSU_CRF_APB_DP_VIDEO_REF_CTRL_CLKACT                        0x1
 
     * This register controls this reference clock
-    * (OFFSET, MASK, VALUE)      (0XFD1A0070, 0x013F3F07U ,0x01010303U)
+    * (OFFSET, MASK, VALUE)      (0XFD1A0070, 0x013F3F07U ,0x01010400U)
     */
        PSU_Mask_Write(CRF_APB_DP_VIDEO_REF_CTRL_OFFSET,
-               0x013F3F07U, 0x01010303U);
+               0x013F3F07U, 0x01010400U);
 /*##################################################################### */
 
     /*
@@ -1526,22 +1526,22 @@ unsigned long psu_clock_init_data(void)
     *  PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1                      0x1
 
     * 6 bit divider
-    *  PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0                      0x27
+    *  PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0                      0x10
 
     * 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (T
     * his signal may only be toggled after 4 cycles of the old clock and 4 cyc
     * les of the new clock. This is not usually an issue, but designers must b
     * e aware.)
-    *  PSU_CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL                        0x0
+    *  PSU_CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL                        0x3
 
     * Clock active signal. Switch to 0 to disable the clock
     *  PSU_CRF_APB_DP_AUDIO_REF_CTRL_CLKACT                        0x1
 
     * This register controls this reference clock
-    * (OFFSET, MASK, VALUE)      (0XFD1A0074, 0x013F3F07U ,0x01012700U)
+    * (OFFSET, MASK, VALUE)      (0XFD1A0074, 0x013F3F07U ,0x01011003U)
     */
        PSU_Mask_Write(CRF_APB_DP_AUDIO_REF_CTRL_OFFSET,
-               0x013F3F07U, 0x01012700U);
+               0x013F3F07U, 0x01011003U);
 /*##################################################################### */
 
     /*
@@ -1551,7 +1551,7 @@ unsigned long psu_clock_init_data(void)
     *  PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR1                        0x1
 
     * 6 bit divider
-    *  PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR0                        0x11
+    *  PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR0                        0xf
 
     * 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD; (This signal may only be togg
     * led after 4 cycles of the old clock and 4 cycles of the new clock. This
@@ -1562,10 +1562,10 @@ unsigned long psu_clock_init_data(void)
     *  PSU_CRF_APB_DP_STC_REF_CTRL_CLKACT                          0x1
 
     * This register controls this reference clock
-    * (OFFSET, MASK, VALUE)      (0XFD1A007C, 0x013F3F07U ,0x01011103U)
+    * (OFFSET, MASK, VALUE)      (0XFD1A007C, 0x013F3F07U ,0x01010F03U)
     */
        PSU_Mask_Write(CRF_APB_DP_STC_REF_CTRL_OFFSET,
-               0x013F3F07U, 0x01011103U);
+               0x013F3F07U, 0x01010F03U);
 /*##################################################################### */
 
     /*
@@ -1712,16 +1712,16 @@ unsigned long psu_clock_init_data(void)
     * 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft
     * er 4 cycles of the old clock and 4 cycles of the new clock. This is not
     * usually an issue, but designers must be aware.)
-    *  PSU_CRF_APB_TOPSW_MAIN_CTRL_SRCSEL                          0x2
+    *  PSU_CRF_APB_TOPSW_MAIN_CTRL_SRCSEL                          0x3
 
     * Clock active signal. Switch to 0 to disable the clock
     *  PSU_CRF_APB_TOPSW_MAIN_CTRL_CLKACT                          0x1
 
     * This register controls this reference clock
-    * (OFFSET, MASK, VALUE)      (0XFD1A00C0, 0x01003F07U ,0x01000202U)
+    * (OFFSET, MASK, VALUE)      (0XFD1A00C0, 0x01003F07U ,0x01000203U)
     */
        PSU_Mask_Write(CRF_APB_TOPSW_MAIN_CTRL_OFFSET,
-               0x01003F07U, 0x01000202U);
+               0x01003F07U, 0x01000203U);
 /*##################################################################### */
 
     /*
@@ -10801,9 +10801,11 @@ unsigned long psu_ddr_init_data(void)
                0xFFFFFFFFU, 0x012643C4U);
 /*##################################################################### */
 
-    /*
-    * DDR QOS CONTROLLER
-    */
+
+       return 1;
+}
+unsigned long psu_ddr_qos_init_data(void)
+{
 
        return 1;
 }
@@ -14613,6 +14615,34 @@ unsigned long psu_peripherals_init_data(void)
                0x00000006U, 0x00000000U);
 /*##################################################################### */
 
+    /*
+    * DP AUDIO VIDEO CLOCK SOURCE
+    */
+    /*
+    * Register : AV_BUF_AUD_VID_CLK_SOURCE @ 0XFD4AB120
+
+    * Bits[2] - - 0: Timing from PL (Default) - 1: Internal Timing This bit ca
+    * n be used in case where Internal VTC is clocked using PL clock. Typical
+    * use case is, when Video from memory is blended and output to PL
+    *  PSU_DP_AV_BUF_AUD_VID_CLK_SOURCE_VID_TIMING_SRC             1
+
+    * Bits[0] - - 0: clock from PL (Default) dp_live_video_in_clk - 1: Clock f
+    * rom PS(dp_vtc_pixel_clk_in)
+    *  PSU_DP_AV_BUF_AUD_VID_CLK_SOURCE_VID_CLK_SRC                1
+
+    * Bits[1] - - 0: clock from PL (Default) - 1: Clock from PS
+    *  PSU_DP_AV_BUF_AUD_VID_CLK_SOURCE_AUD_CLK_SRC                1
+
+    * AV_BUF_AUD_VID_CLK_SOURCE : When live video from PL is absent, then the
+    * internal clock shall be video pipeline clock. If the live video is prese
+    * nt, then clock from PL shall be the video pipe line clock. Similarly for
+    *  the audio we can select from either PS or PL clock
+    * (OFFSET, MASK, VALUE)      (0XFD4AB120, 0x00000007U ,0x00000007U)
+    */
+       PSU_Mask_Write(DP_AV_BUF_AUD_VID_CLK_SOURCE_OFFSET,
+               0x00000007U, 0x00000007U);
+/*##################################################################### */
+
     /*
     * UART BAUD RATE
     */
@@ -14968,16 +14998,16 @@ unsigned long psu_peripherals_init_data(void)
 
     * Frequency in number of ticks per second. Valid range from 10 MHz to 100
     * MHz.
-    *  PSU_IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ              0x1fc9f08
+    *  PSU_IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ              0x5f5dd17
 
     * Program this register to match the clock frequency of the timestamp gene
     * rator, in ticks per second. For example, for a 50 MHz clock, program 0x0
     * 2FAF080. This register is not accessible to the read-only programming in
     * terface.
-    * (OFFSET, MASK, VALUE)      (0XFF260020, 0xFFFFFFFFU ,0x01FC9F08U)
+    * (OFFSET, MASK, VALUE)      (0XFF260020, 0xFFFFFFFFU ,0x05F5DD17U)
     */
        PSU_Mask_Write(IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_OFFSET,
-               0xFFFFFFFFU, 0x01FC9F08U);
+               0xFFFFFFFFU, 0x05F5DD17U);
 /*##################################################################### */
 
     /*
@@ -19464,7 +19494,7 @@ static u32 mask_read(u32 add, u32 mask)
        return val;
 }
 
-static void __maybe_unused dpll_prog(int ddr_pll_fbdiv, int d_lock_dly, int d_lock_cnt,
+static void dpll_prog(int ddr_pll_fbdiv, int d_lock_dly, int d_lock_cnt,
        int d_lfhf, int d_cp, int d_res) {
 
        unsigned int pll_ctrl_regval;
@@ -19813,6 +19843,9 @@ psu_init(void)
 
        status &=  psu_peripherals_powerdwn_data();
        status &=    psu_afi_config();
+#ifdef PS_DDR_QOS_ENABLE
+       psu_ddr_qos_init_data();
+#endif
 
        if (status == 0)
                return 1;
diff --git a/board/xilinx/zynqmp/zynqmp-zcu104-revA/psu_init_gpl.h b/board/xilinx/zynqmp/zynqmp-zcu104-revA/psu_init_gpl.h
index 0c64f9873a5594d1d00404a26774910c3e5373c1..f555fe4ab7110d588dfe94489891252fa5ed1c51 100644 (file)
--- a/board/xilinx/zynqmp/zynqmp-zcu104-revA/psu_init_gpl.h
+++ b/board/xilinx/zynqmp/zynqmp-zcu104-revA/psu_init_gpl.h
@@ -1,7 +1,7 @@
 /******************************************************************************
 *
 * Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
-* 
+*
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2 of the License, or
@@ -11,11 +11,11 @@
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
-* 
+*
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, see <http://www.gnu.org/licenses/>
-* 
-* 
+*
+*
 ******************************************************************************/
 /****************************************************************************/
 /**
@@ -27,93 +27,93 @@
 *****************************************************************************/
 
 
-#undef CRL_APB_RPLL_CFG_OFFSET 
+#undef CRL_APB_RPLL_CFG_OFFSET
 #define CRL_APB_RPLL_CFG_OFFSET                                                    0XFF5E0034
-#undef CRL_APB_RPLL_CTRL_OFFSET 
+#undef CRL_APB_RPLL_CTRL_OFFSET
 #define CRL_APB_RPLL_CTRL_OFFSET                                                   0XFF5E0030
-#undef CRL_APB_RPLL_CTRL_OFFSET 
+#undef CRL_APB_RPLL_CTRL_OFFSET
 #define CRL_APB_RPLL_CTRL_OFFSET                                                   0XFF5E0030
-#undef CRL_APB_RPLL_CTRL_OFFSET 
+#undef CRL_APB_RPLL_CTRL_OFFSET
 #define CRL_APB_RPLL_CTRL_OFFSET                                                   0XFF5E0030
-#undef CRL_APB_RPLL_CTRL_OFFSET 
+#undef CRL_APB_RPLL_CTRL_OFFSET
 #define CRL_APB_RPLL_CTRL_OFFSET                                                   0XFF5E0030
-#undef CRL_APB_RPLL_CTRL_OFFSET 
+#undef CRL_APB_RPLL_CTRL_OFFSET
 #define CRL_APB_RPLL_CTRL_OFFSET                                                   0XFF5E0030
-#undef CRL_APB_RPLL_TO_FPD_CTRL_OFFSET 
+#undef CRL_APB_RPLL_TO_FPD_CTRL_OFFSET
 #define CRL_APB_RPLL_TO_FPD_CTRL_OFFSET                                            0XFF5E0048
-#undef CRL_APB_RPLL_FRAC_CFG_OFFSET 
+#undef CRL_APB_RPLL_FRAC_CFG_OFFSET
 #define CRL_APB_RPLL_FRAC_CFG_OFFSET                                               0XFF5E0038
-#undef CRL_APB_IOPLL_CFG_OFFSET 
+#undef CRL_APB_IOPLL_CFG_OFFSET
 #define CRL_APB_IOPLL_CFG_OFFSET                                                   0XFF5E0024
-#undef CRL_APB_IOPLL_CTRL_OFFSET 
+#undef CRL_APB_IOPLL_CTRL_OFFSET
 #define CRL_APB_IOPLL_CTRL_OFFSET                                                  0XFF5E0020
-#undef CRL_APB_IOPLL_CTRL_OFFSET 
+#undef CRL_APB_IOPLL_CTRL_OFFSET
 #define CRL_APB_IOPLL_CTRL_OFFSET                                                  0XFF5E0020
-#undef CRL_APB_IOPLL_CTRL_OFFSET 
+#undef CRL_APB_IOPLL_CTRL_OFFSET
 #define CRL_APB_IOPLL_CTRL_OFFSET                                                  0XFF5E0020
-#undef CRL_APB_IOPLL_CTRL_OFFSET 
+#undef CRL_APB_IOPLL_CTRL_OFFSET
 #define CRL_APB_IOPLL_CTRL_OFFSET                                                  0XFF5E0020
-#undef CRL_APB_IOPLL_CTRL_OFFSET 
+#undef CRL_APB_IOPLL_CTRL_OFFSET
 #define CRL_APB_IOPLL_CTRL_OFFSET                                                  0XFF5E0020
-#undef CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET 
+#undef CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET
 #define CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET                                           0XFF5E0044
-#undef CRL_APB_IOPLL_FRAC_CFG_OFFSET 
+#undef CRL_APB_IOPLL_FRAC_CFG_OFFSET
 #define CRL_APB_IOPLL_FRAC_CFG_OFFSET                                              0XFF5E0028
-#undef CRF_APB_APLL_CFG_OFFSET 
+#undef CRF_APB_APLL_CFG_OFFSET
 #define CRF_APB_APLL_CFG_OFFSET                                                    0XFD1A0024
-#undef CRF_APB_APLL_CTRL_OFFSET 
+#undef CRF_APB_APLL_CTRL_OFFSET
 #define CRF_APB_APLL_CTRL_OFFSET                                                   0XFD1A0020
-#undef CRF_APB_APLL_CTRL_OFFSET 
+#undef CRF_APB_APLL_CTRL_OFFSET
 #define CRF_APB_APLL_CTRL_OFFSET                                                   0XFD1A0020
-#undef CRF_APB_APLL_CTRL_OFFSET 
+#undef CRF_APB_APLL_CTRL_OFFSET
 #define CRF_APB_APLL_CTRL_OFFSET                                                   0XFD1A0020
-#undef CRF_APB_APLL_CTRL_OFFSET 
+#undef CRF_APB_APLL_CTRL_OFFSET
 #define CRF_APB_APLL_CTRL_OFFSET                                                   0XFD1A0020
-#undef CRF_APB_APLL_CTRL_OFFSET 
+#undef CRF_APB_APLL_CTRL_OFFSET
 #define CRF_APB_APLL_CTRL_OFFSET                                                   0XFD1A0020
-#undef CRF_APB_APLL_TO_LPD_CTRL_OFFSET 
+#undef CRF_APB_APLL_TO_LPD_CTRL_OFFSET
 #define CRF_APB_APLL_TO_LPD_CTRL_OFFSET                                            0XFD1A0048
-#undef CRF_APB_APLL_FRAC_CFG_OFFSET 
+#undef CRF_APB_APLL_FRAC_CFG_OFFSET
 #define CRF_APB_APLL_FRAC_CFG_OFFSET                                               0XFD1A0028
-#undef CRF_APB_DPLL_CFG_OFFSET 
+#undef CRF_APB_DPLL_CFG_OFFSET
 #define CRF_APB_DPLL_CFG_OFFSET                                                    0XFD1A0030
-#undef CRF_APB_DPLL_CTRL_OFFSET 
+#undef CRF_APB_DPLL_CTRL_OFFSET
 #define CRF_APB_DPLL_CTRL_OFFSET                                                   0XFD1A002C
-#undef CRF_APB_DPLL_CTRL_OFFSET 
+#undef CRF_APB_DPLL_CTRL_OFFSET
 #define CRF_APB_DPLL_CTRL_OFFSET                                                   0XFD1A002C
-#undef CRF_APB_DPLL_CTRL_OFFSET 
+#undef CRF_APB_DPLL_CTRL_OFFSET
 #define CRF_APB_DPLL_CTRL_OFFSET                                                   0XFD1A002C
-#undef CRF_APB_DPLL_CTRL_OFFSET 
+#undef CRF_APB_DPLL_CTRL_OFFSET
 #define CRF_APB_DPLL_CTRL_OFFSET                                                   0XFD1A002C
-#undef CRF_APB_DPLL_CTRL_OFFSET 
+#undef CRF_APB_DPLL_CTRL_OFFSET
 #define CRF_APB_DPLL_CTRL_OFFSET                                                   0XFD1A002C
-#undef CRF_APB_DPLL_TO_LPD_CTRL_OFFSET 
+#undef CRF_APB_DPLL_TO_LPD_CTRL_OFFSET
 #define CRF_APB_DPLL_TO_LPD_CTRL_OFFSET                                            0XFD1A004C
-#undef CRF_APB_DPLL_FRAC_CFG_OFFSET 
+#undef CRF_APB_DPLL_FRAC_CFG_OFFSET
 #define CRF_APB_DPLL_FRAC_CFG_OFFSET                                               0XFD1A0034
-#undef CRF_APB_VPLL_CFG_OFFSET 
+#undef CRF_APB_VPLL_CFG_OFFSET
 #define CRF_APB_VPLL_CFG_OFFSET                                                    0XFD1A003C
-#undef CRF_APB_VPLL_CTRL_OFFSET 
+#undef CRF_APB_VPLL_CTRL_OFFSET
 #define CRF_APB_VPLL_CTRL_OFFSET                                                   0XFD1A0038
-#undef CRF_APB_VPLL_CTRL_OFFSET 
+#undef CRF_APB_VPLL_CTRL_OFFSET
 #define CRF_APB_VPLL_CTRL_OFFSET                                                   0XFD1A0038
-#undef CRF_APB_VPLL_CTRL_OFFSET 
+#undef CRF_APB_VPLL_CTRL_OFFSET
 #define CRF_APB_VPLL_CTRL_OFFSET                                                   0XFD1A0038
-#undef CRF_APB_VPLL_CTRL_OFFSET 
+#undef CRF_APB_VPLL_CTRL_OFFSET
 #define CRF_APB_VPLL_CTRL_OFFSET                                                   0XFD1A0038
-#undef CRF_APB_VPLL_CTRL_OFFSET 
+#undef CRF_APB_VPLL_CTRL_OFFSET
 #define CRF_APB_VPLL_CTRL_OFFSET                                                   0XFD1A0038
-#undef CRF_APB_VPLL_TO_LPD_CTRL_OFFSET 
+#undef CRF_APB_VPLL_TO_LPD_CTRL_OFFSET
 #define CRF_APB_VPLL_TO_LPD_CTRL_OFFSET                                            0XFD1A0050
-#undef CRF_APB_VPLL_FRAC_CFG_OFFSET 
+#undef CRF_APB_VPLL_FRAC_CFG_OFFSET
 #define CRF_APB_VPLL_FRAC_CFG_OFFSET                                               0XFD1A0040
 
 /*
 * PLL loop filter resistor control
 */
-#undef CRL_APB_RPLL_CFG_RES_DEFVAL 
-#undef CRL_APB_RPLL_CFG_RES_SHIFT 
-#undef CRL_APB_RPLL_CFG_RES_MASK 
+#undef CRL_APB_RPLL_CFG_RES_DEFVAL
+#undef CRL_APB_RPLL_CFG_RES_SHIFT
+#undef CRL_APB_RPLL_CFG_RES_MASK
 #define CRL_APB_RPLL_CFG_RES_DEFVAL                            0x00000000
 #define CRL_APB_RPLL_CFG_RES_SHIFT                             0
 #define CRL_APB_RPLL_CFG_RES_MASK                              0x0000000FU
@@ -121,9 +121,9 @@
 /*
 * PLL charge pump control
 */
-#undef CRL_APB_RPLL_CFG_CP_DEFVAL 
-#undef CRL_APB_RPLL_CFG_CP_SHIFT 
-#undef CRL_APB_RPLL_CFG_CP_MASK 
+#undef CRL_APB_RPLL_CFG_CP_DEFVAL
+#undef CRL_APB_RPLL_CFG_CP_SHIFT
+#undef CRL_APB_RPLL_CFG_CP_MASK
 #define CRL_APB_RPLL_CFG_CP_DEFVAL                             0x00000000
 #define CRL_APB_RPLL_CFG_CP_SHIFT                              5
 #define CRL_APB_RPLL_CFG_CP_MASK                               0x000001E0U
@@ -131,9 +131,9 @@
 /*
 * PLL loop filter high frequency capacitor control
 */
-#undef CRL_APB_RPLL_CFG_LFHF_DEFVAL 
-#undef CRL_APB_RPLL_CFG_LFHF_SHIFT 
-#undef CRL_APB_RPLL_CFG_LFHF_MASK 
+#undef CRL_APB_RPLL_CFG_LFHF_DEFVAL
+#undef CRL_APB_RPLL_CFG_LFHF_SHIFT
+#undef CRL_APB_RPLL_CFG_LFHF_MASK
 #define CRL_APB_RPLL_CFG_LFHF_DEFVAL                           0x00000000
 #define CRL_APB_RPLL_CFG_LFHF_SHIFT                            10
 #define CRL_APB_RPLL_CFG_LFHF_MASK                             0x00000C00U
@@ -141,9 +141,9 @@
 /*
 * Lock circuit counter setting
 */
-#undef CRL_APB_RPLL_CFG_LOCK_CNT_DEFVAL 
-#undef CRL_APB_RPLL_CFG_LOCK_CNT_SHIFT 
-#undef CRL_APB_RPLL_CFG_LOCK_CNT_MASK 
+#undef CRL_APB_RPLL_CFG_LOCK_CNT_DEFVAL
+#undef CRL_APB_RPLL_CFG_LOCK_CNT_SHIFT
+#undef CRL_APB_RPLL_CFG_LOCK_CNT_MASK
 #define CRL_APB_RPLL_CFG_LOCK_CNT_DEFVAL                       0x00000000
 #define CRL_APB_RPLL_CFG_LOCK_CNT_SHIFT                        13
 #define CRL_APB_RPLL_CFG_LOCK_CNT_MASK                         0x007FE000U
@@ -151,9 +151,9 @@
 /*
 * Lock circuit configuration settings for lock windowsize
 */
-#undef CRL_APB_RPLL_CFG_LOCK_DLY_DEFVAL 
-#undef CRL_APB_RPLL_CFG_LOCK_DLY_SHIFT 
-#undef CRL_APB_RPLL_CFG_LOCK_DLY_MASK 
+#undef CRL_APB_RPLL_CFG_LOCK_DLY_DEFVAL
+#undef CRL_APB_RPLL_CFG_LOCK_DLY_SHIFT
+#undef CRL_APB_RPLL_CFG_LOCK_DLY_MASK
 #define CRL_APB_RPLL_CFG_LOCK_DLY_DEFVAL                       0x00000000
 #define CRL_APB_RPLL_CFG_LOCK_DLY_SHIFT                        25
 #define CRL_APB_RPLL_CFG_LOCK_DLY_MASK                         0xFE000000U
@@ -163,9 +163,9 @@
     * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour
     * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
 */
-#undef CRL_APB_RPLL_CTRL_PRE_SRC_DEFVAL 
-#undef CRL_APB_RPLL_CTRL_PRE_SRC_SHIFT 
-#undef CRL_APB_RPLL_CTRL_PRE_SRC_MASK 
+#undef CRL_APB_RPLL_CTRL_PRE_SRC_DEFVAL
+#undef CRL_APB_RPLL_CTRL_PRE_SRC_SHIFT
+#undef CRL_APB_RPLL_CTRL_PRE_SRC_MASK
 #define CRL_APB_RPLL_CTRL_PRE_SRC_DEFVAL                       0x00012C09
 #define CRL_APB_RPLL_CTRL_PRE_SRC_SHIFT                        20
 #define CRL_APB_RPLL_CTRL_PRE_SRC_MASK                         0x00700000U
@@ -173,9 +173,9 @@
 /*
 * The integer portion of the feedback divider to the PLL
 */
-#undef CRL_APB_RPLL_CTRL_FBDIV_DEFVAL 
-#undef CRL_APB_RPLL_CTRL_FBDIV_SHIFT 
-#undef CRL_APB_RPLL_CTRL_FBDIV_MASK 
+#undef CRL_APB_RPLL_CTRL_FBDIV_DEFVAL
+#undef CRL_APB_RPLL_CTRL_FBDIV_SHIFT
+#undef CRL_APB_RPLL_CTRL_FBDIV_MASK
 #define CRL_APB_RPLL_CTRL_FBDIV_DEFVAL                         0x00012C09
 #define CRL_APB_RPLL_CTRL_FBDIV_SHIFT                          8
 #define CRL_APB_RPLL_CTRL_FBDIV_MASK                           0x00007F00U
@@ -184,9 +184,9 @@
 * This turns on the divide by 2 that is inside of the PLL. This does not c
     * hange the VCO frequency, just the output frequency
 */
-#undef CRL_APB_RPLL_CTRL_DIV2_DEFVAL 
-#undef CRL_APB_RPLL_CTRL_DIV2_SHIFT 
-#undef CRL_APB_RPLL_CTRL_DIV2_MASK 
+#undef CRL_APB_RPLL_CTRL_DIV2_DEFVAL
+#undef CRL_APB_RPLL_CTRL_DIV2_SHIFT
+#undef CRL_APB_RPLL_CTRL_DIV2_MASK
 #define CRL_APB_RPLL_CTRL_DIV2_DEFVAL                          0x00012C09
 #define CRL_APB_RPLL_CTRL_DIV2_SHIFT                           16
 #define CRL_APB_RPLL_CTRL_DIV2_MASK                            0x00010000U
@@ -197,9 +197,9 @@
     * clock and 4 cycles of the new clock. This is not usually an issue, but d
     * esigners must be aware.)
 */
-#undef CRL_APB_RPLL_CTRL_BYPASS_DEFVAL 
-#undef CRL_APB_RPLL_CTRL_BYPASS_SHIFT 
-#undef CRL_APB_RPLL_CTRL_BYPASS_MASK 
+#undef CRL_APB_RPLL_CTRL_BYPASS_DEFVAL
+#undef CRL_APB_RPLL_CTRL_BYPASS_SHIFT
+#undef CRL_APB_RPLL_CTRL_BYPASS_MASK
 #define CRL_APB_RPLL_CTRL_BYPASS_DEFVAL                        0x00012C09
 #define CRL_APB_RPLL_CTRL_BYPASS_SHIFT                         3
 #define CRL_APB_RPLL_CTRL_BYPASS_MASK                          0x00000008U
@@ -208,9 +208,9 @@
 * Asserts Reset to the PLL. When asserting reset, the PLL must already be
     * in BYPASS.
 */
-#undef CRL_APB_RPLL_CTRL_RESET_DEFVAL 
-#undef CRL_APB_RPLL_CTRL_RESET_SHIFT 
-#undef CRL_APB_RPLL_CTRL_RESET_MASK 
+#undef CRL_APB_RPLL_CTRL_RESET_DEFVAL
+#undef CRL_APB_RPLL_CTRL_RESET_SHIFT
+#undef CRL_APB_RPLL_CTRL_RESET_MASK
 #define CRL_APB_RPLL_CTRL_RESET_DEFVAL                         0x00012C09
 #define CRL_APB_RPLL_CTRL_RESET_SHIFT                          0
 #define CRL_APB_RPLL_CTRL_RESET_MASK                           0x00000001U
@@ -219,9 +219,9 @@
 * Asserts Reset to the PLL. When asserting reset, the PLL must already be
     * in BYPASS.
 */
-#undef CRL_APB_RPLL_CTRL_RESET_DEFVAL 
-#undef CRL_APB_RPLL_CTRL_RESET_SHIFT 
-#undef CRL_APB_RPLL_CTRL_RESET_MASK 
+#undef CRL_APB_RPLL_CTRL_RESET_DEFVAL
+#undef CRL_APB_RPLL_CTRL_RESET_SHIFT
+#undef CRL_APB_RPLL_CTRL_RESET_MASK
 #define CRL_APB_RPLL_CTRL_RESET_DEFVAL                         0x00012C09
 #define CRL_APB_RPLL_CTRL_RESET_SHIFT                          0
 #define CRL_APB_RPLL_CTRL_RESET_MASK                           0x00000001U
@@ -229,9 +229,9 @@
 /*
 * RPLL is locked
 */
-#undef CRL_APB_PLL_STATUS_RPLL_LOCK_DEFVAL 
-#undef CRL_APB_PLL_STATUS_RPLL_LOCK_SHIFT 
-#undef CRL_APB_PLL_STATUS_RPLL_LOCK_MASK 
+#undef CRL_APB_PLL_STATUS_RPLL_LOCK_DEFVAL
+#undef CRL_APB_PLL_STATUS_RPLL_LOCK_SHIFT
+#undef CRL_APB_PLL_STATUS_RPLL_LOCK_MASK
 #define CRL_APB_PLL_STATUS_RPLL_LOCK_DEFVAL                    0x00000018
 #define CRL_APB_PLL_STATUS_RPLL_LOCK_SHIFT                     1
 #define CRL_APB_PLL_STATUS_RPLL_LOCK_MASK                      0x00000002U
@@ -243,9 +243,9 @@
     * clock and 4 cycles of the new clock. This is not usually an issue, but d
     * esigners must be aware.)
 */
-#undef CRL_APB_RPLL_CTRL_BYPASS_DEFVAL 
-#undef CRL_APB_RPLL_CTRL_BYPASS_SHIFT 
-#undef CRL_APB_RPLL_CTRL_BYPASS_MASK 
+#undef CRL_APB_RPLL_CTRL_BYPASS_DEFVAL
+#undef CRL_APB_RPLL_CTRL_BYPASS_SHIFT
+#undef CRL_APB_RPLL_CTRL_BYPASS_MASK
 #define CRL_APB_RPLL_CTRL_BYPASS_DEFVAL                        0x00012C09
 #define CRL_APB_RPLL_CTRL_BYPASS_SHIFT                         3
 #define CRL_APB_RPLL_CTRL_BYPASS_MASK                          0x00000008U
@@ -253,9 +253,9 @@
 /*
 * Divisor value for this clock.
 */
-#undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL 
-#undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT 
-#undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK 
+#undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL
+#undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT
+#undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK
 #define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL               0x00000400
 #define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT                8
 #define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK                 0x00003F00U
@@ -265,9 +265,9 @@
     * ores all fractional data. When 1, PLL is in fractional mode and uses DAT
     * A of this register for the fractional portion of the feedback divider.
 */
-#undef CRL_APB_RPLL_FRAC_CFG_ENABLED_DEFVAL 
-#undef CRL_APB_RPLL_FRAC_CFG_ENABLED_SHIFT 
-#undef CRL_APB_RPLL_FRAC_CFG_ENABLED_MASK 
+#undef CRL_APB_RPLL_FRAC_CFG_ENABLED_DEFVAL
+#undef CRL_APB_RPLL_FRAC_CFG_ENABLED_SHIFT
+#undef CRL_APB_RPLL_FRAC_CFG_ENABLED_MASK
 #define CRL_APB_RPLL_FRAC_CFG_ENABLED_DEFVAL                   0x00000000
 #define CRL_APB_RPLL_FRAC_CFG_ENABLED_SHIFT                    31
 #define CRL_APB_RPLL_FRAC_CFG_ENABLED_MASK                     0x80000000U
@@ -275,9 +275,9 @@
 /*
 * Fractional value for the Feedback value.
 */
-#undef CRL_APB_RPLL_FRAC_CFG_DATA_DEFVAL 
-#undef CRL_APB_RPLL_FRAC_CFG_DATA_SHIFT 
-#undef CRL_APB_RPLL_FRAC_CFG_DATA_MASK 
+#undef CRL_APB_RPLL_FRAC_CFG_DATA_DEFVAL
+#undef CRL_APB_RPLL_FRAC_CFG_DATA_SHIFT
+#undef CRL_APB_RPLL_FRAC_CFG_DATA_MASK
 #define CRL_APB_RPLL_FRAC_CFG_DATA_DEFVAL                      0x00000000
 #define CRL_APB_RPLL_FRAC_CFG_DATA_SHIFT                       0
 #define CRL_APB_RPLL_FRAC_CFG_DATA_MASK                        0x0000FFFFU
@@ -285,9 +285,9 @@
 /*
 * PLL loop filter resistor control
 */
-#undef CRL_APB_IOPLL_CFG_RES_DEFVAL 
-#undef CRL_APB_IOPLL_CFG_RES_SHIFT 
-#undef CRL_APB_IOPLL_CFG_RES_MASK 
+#undef CRL_APB_IOPLL_CFG_RES_DEFVAL
+#undef CRL_APB_IOPLL_CFG_RES_SHIFT
+#undef CRL_APB_IOPLL_CFG_RES_MASK
 #define CRL_APB_IOPLL_CFG_RES_DEFVAL                           0x00000000
 #define CRL_APB_IOPLL_CFG_RES_SHIFT                            0
 #define CRL_APB_IOPLL_CFG_RES_MASK                             0x0000000FU
@@ -295,9 +295,9 @@
 /*
 * PLL charge pump control
 */
-#undef CRL_APB_IOPLL_CFG_CP_DEFVAL 
-#undef CRL_APB_IOPLL_CFG_CP_SHIFT 
-#undef CRL_APB_IOPLL_CFG_CP_MASK 
+#undef CRL_APB_IOPLL_CFG_CP_DEFVAL
+#undef CRL_APB_IOPLL_CFG_CP_SHIFT
+#undef CRL_APB_IOPLL_CFG_CP_MASK
 #define CRL_APB_IOPLL_CFG_CP_DEFVAL                            0x00000000
 #define CRL_APB_IOPLL_CFG_CP_SHIFT                             5
 #define CRL_APB_IOPLL_CFG_CP_MASK                              0x000001E0U
@@ -305,9 +305,9 @@
 /*
 * PLL loop filter high frequency capacitor control
 */
-#undef CRL_APB_IOPLL_CFG_LFHF_DEFVAL 
-#undef CRL_APB_IOPLL_CFG_LFHF_SHIFT 
-#undef CRL_APB_IOPLL_CFG_LFHF_MASK 
+#undef CRL_APB_IOPLL_CFG_LFHF_DEFVAL
+#undef CRL_APB_IOPLL_CFG_LFHF_SHIFT
+#undef CRL_APB_IOPLL_CFG_LFHF_MASK
 #define CRL_APB_IOPLL_CFG_LFHF_DEFVAL                          0x00000000
 #define CRL_APB_IOPLL_CFG_LFHF_SHIFT                           10
 #define CRL_APB_IOPLL_CFG_LFHF_MASK                            0x00000C00U
@@ -315,9 +315,9 @@
 /*
 * Lock circuit counter setting
 */
-#undef CRL_APB_IOPLL_CFG_LOCK_CNT_DEFVAL 
-#undef CRL_APB_IOPLL_CFG_LOCK_CNT_SHIFT 
-#undef CRL_APB_IOPLL_CFG_LOCK_CNT_MASK 
+#undef CRL_APB_IOPLL_CFG_LOCK_CNT_DEFVAL
+#undef CRL_APB_IOPLL_CFG_LOCK_CNT_SHIFT
+#undef CRL_APB_IOPLL_CFG_LOCK_CNT_MASK
 #define CRL_APB_IOPLL_CFG_LOCK_CNT_DEFVAL                      0x00000000
 #define CRL_APB_IOPLL_CFG_LOCK_CNT_SHIFT                       13
 #define CRL_APB_IOPLL_CFG_LOCK_CNT_MASK                        0x007FE000U
@@ -325,9 +325,9 @@
 /*
 * Lock circuit configuration settings for lock windowsize
 */
-#undef CRL_APB_IOPLL_CFG_LOCK_DLY_DEFVAL 
-#undef CRL_APB_IOPLL_CFG_LOCK_DLY_SHIFT 
-#undef CRL_APB_IOPLL_CFG_LOCK_DLY_MASK 
+#undef CRL_APB_IOPLL_CFG_LOCK_DLY_DEFVAL
+#undef CRL_APB_IOPLL_CFG_LOCK_DLY_SHIFT
+#undef CRL_APB_IOPLL_CFG_LOCK_DLY_MASK
 #define CRL_APB_IOPLL_CFG_LOCK_DLY_DEFVAL                      0x00000000
 #define CRL_APB_IOPLL_CFG_LOCK_DLY_SHIFT                       25
 #define CRL_APB_IOPLL_CFG_LOCK_DLY_MASK                        0xFE000000U
@@ -337,9 +337,9 @@
     * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour
     * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
 */
-#undef CRL_APB_IOPLL_CTRL_PRE_SRC_DEFVAL 
-#undef CRL_APB_IOPLL_CTRL_PRE_SRC_SHIFT 
-#undef CRL_APB_IOPLL_CTRL_PRE_SRC_MASK 
+#undef CRL_APB_IOPLL_CTRL_PRE_SRC_DEFVAL
+#undef CRL_APB_IOPLL_CTRL_PRE_SRC_SHIFT
+#undef CRL_APB_IOPLL_CTRL_PRE_SRC_MASK
 #define CRL_APB_IOPLL_CTRL_PRE_SRC_DEFVAL                      0x00012C09
 #define CRL_APB_IOPLL_CTRL_PRE_SRC_SHIFT                       20
 #define CRL_APB_IOPLL_CTRL_PRE_SRC_MASK                        0x00700000U
@@ -347,9 +347,9 @@
 /*
 * The integer portion of the feedback divider to the PLL
 */
-#undef CRL_APB_IOPLL_CTRL_FBDIV_DEFVAL 
-#undef CRL_APB_IOPLL_CTRL_FBDIV_SHIFT 
-#undef CRL_APB_IOPLL_CTRL_FBDIV_MASK 
+#undef CRL_APB_IOPLL_CTRL_FBDIV_DEFVAL
+#undef CRL_APB_IOPLL_CTRL_FBDIV_SHIFT
+#undef CRL_APB_IOPLL_CTRL_FBDIV_MASK
 #define CRL_APB_IOPLL_CTRL_FBDIV_DEFVAL                        0x00012C09
 #define CRL_APB_IOPLL_CTRL_FBDIV_SHIFT                         8
 #define CRL_APB_IOPLL_CTRL_FBDIV_MASK                          0x00007F00U
@@ -358,9 +358,9 @@
 * This turns on the divide by 2 that is inside of the PLL. This does not c
     * hange the VCO frequency, just the output frequency
 */
-#undef CRL_APB_IOPLL_CTRL_DIV2_DEFVAL 
-#undef CRL_APB_IOPLL_CTRL_DIV2_SHIFT 
-#undef CRL_APB_IOPLL_CTRL_DIV2_MASK 
+#undef CRL_APB_IOPLL_CTRL_DIV2_DEFVAL
+#undef CRL_APB_IOPLL_CTRL_DIV2_SHIFT
+#undef CRL_APB_IOPLL_CTRL_DIV2_MASK
 #define CRL_APB_IOPLL_CTRL_DIV2_DEFVAL                         0x00012C09
 #define CRL_APB_IOPLL_CTRL_DIV2_SHIFT                          16
 #define CRL_APB_IOPLL_CTRL_DIV2_MASK                           0x00010000U
@@ -371,9 +371,9 @@
     * clock and 4 cycles of the new clock. This is not usually an issue, but d
     * esigners must be aware.)
 */
-#undef CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL 
-#undef CRL_APB_IOPLL_CTRL_BYPASS_SHIFT 
-#undef CRL_APB_IOPLL_CTRL_BYPASS_MASK 
+#undef CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL
+#undef CRL_APB_IOPLL_CTRL_BYPASS_SHIFT
+#undef CRL_APB_IOPLL_CTRL_BYPASS_MASK
 #define CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL                       0x00012C09
 #define CRL_APB_IOPLL_CTRL_BYPASS_SHIFT                        3
 #define CRL_APB_IOPLL_CTRL_BYPASS_MASK                         0x00000008U
@@ -382,9 +382,9 @@
 * Asserts Reset to the PLL. When asserting reset, the PLL must already be
     * in BYPASS.
 */
-#undef CRL_APB_IOPLL_CTRL_RESET_DEFVAL 
-#undef CRL_APB_IOPLL_CTRL_RESET_SHIFT 
-#undef CRL_APB_IOPLL_CTRL_RESET_MASK 
+#undef CRL_APB_IOPLL_CTRL_RESET_DEFVAL
+#undef CRL_APB_IOPLL_CTRL_RESET_SHIFT
+#undef CRL_APB_IOPLL_CTRL_RESET_MASK
 #define CRL_APB_IOPLL_CTRL_RESET_DEFVAL                        0x00012C09
 #define CRL_APB_IOPLL_CTRL_RESET_SHIFT                         0
 #define CRL_APB_IOPLL_CTRL_RESET_MASK                          0x00000001U
@@ -393,9 +393,9 @@
 * Asserts Reset to the PLL. When asserting reset, the PLL must already be
     * in BYPASS.
 */
-#undef CRL_APB_IOPLL_CTRL_RESET_DEFVAL 
-#undef CRL_APB_IOPLL_CTRL_RESET_SHIFT 
-#undef CRL_APB_IOPLL_CTRL_RESET_MASK 
+#undef CRL_APB_IOPLL_CTRL_RESET_DEFVAL
+#undef CRL_APB_IOPLL_CTRL_RESET_SHIFT
+#undef CRL_APB_IOPLL_CTRL_RESET_MASK
 #define CRL_APB_IOPLL_CTRL_RESET_DEFVAL                        0x00012C09
 #define CRL_APB_IOPLL_CTRL_RESET_SHIFT                         0
 #define CRL_APB_IOPLL_CTRL_RESET_MASK                          0x00000001U
@@ -403,9 +403,9 @@
 /*
 * IOPLL is locked
 */
-#undef CRL_APB_PLL_STATUS_IOPLL_LOCK_DEFVAL 
-#undef CRL_APB_PLL_STATUS_IOPLL_LOCK_SHIFT 
-#undef CRL_APB_PLL_STATUS_IOPLL_LOCK_MASK 
+#undef CRL_APB_PLL_STATUS_IOPLL_LOCK_DEFVAL
+#undef CRL_APB_PLL_STATUS_IOPLL_LOCK_SHIFT
+#undef CRL_APB_PLL_STATUS_IOPLL_LOCK_MASK
 #define CRL_APB_PLL_STATUS_IOPLL_LOCK_DEFVAL                   0x00000018
 #define CRL_APB_PLL_STATUS_IOPLL_LOCK_SHIFT                    0
 #define CRL_APB_PLL_STATUS_IOPLL_LOCK_MASK                     0x00000001U
@@ -417,9 +417,9 @@
     * clock and 4 cycles of the new clock. This is not usually an issue, but d
     * esigners must be aware.)
 */
-#undef CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL 
-#undef CRL_APB_IOPLL_CTRL_BYPASS_SHIFT 
-#undef CRL_APB_IOPLL_CTRL_BYPASS_MASK 
+#undef CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL
+#undef CRL_APB_IOPLL_CTRL_BYPASS_SHIFT
+#undef CRL_APB_IOPLL_CTRL_BYPASS_MASK
 #define CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL                       0x00012C09
 #define CRL_APB_IOPLL_CTRL_BYPASS_SHIFT                        3
 #define CRL_APB_IOPLL_CTRL_BYPASS_MASK                         0x00000008U
@@ -427,9 +427,9 @@
 /*
 * Divisor value for this clock.
 */
-#undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL 
-#undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT 
-#undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK 
+#undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL
+#undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT
+#undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK
 #define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL              0x00000400
 #define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT               8
 #define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK                0x00003F00U
@@ -439,9 +439,9 @@
     * ores all fractional data. When 1, PLL is in fractional mode and uses DAT
     * A of this register for the fractional portion of the feedback divider.
 */
-#undef CRL_APB_IOPLL_FRAC_CFG_ENABLED_DEFVAL 
-#undef CRL_APB_IOPLL_FRAC_CFG_ENABLED_SHIFT 
-#undef CRL_APB_IOPLL_FRAC_CFG_ENABLED_MASK 
+#undef CRL_APB_IOPLL_FRAC_CFG_ENABLED_DEFVAL
+#undef CRL_APB_IOPLL_FRAC_CFG_ENABLED_SHIFT
+#undef CRL_APB_IOPLL_FRAC_CFG_ENABLED_MASK
 #define CRL_APB_IOPLL_FRAC_CFG_ENABLED_DEFVAL                  0x00000000
 #define CRL_APB_IOPLL_FRAC_CFG_ENABLED_SHIFT                   31
 #define CRL_APB_IOPLL_FRAC_CFG_ENABLED_MASK                    0x80000000U
@@ -449,9 +449,9 @@
 /*
 * Fractional value for the Feedback value.
 */
-#undef CRL_APB_IOPLL_FRAC_CFG_DATA_DEFVAL 
-#undef CRL_APB_IOPLL_FRAC_CFG_DATA_SHIFT 
-#undef CRL_APB_IOPLL_FRAC_CFG_DATA_MASK 
+#undef CRL_APB_IOPLL_FRAC_CFG_DATA_DEFVAL
+#undef CRL_APB_IOPLL_FRAC_CFG_DATA_SHIFT
+#undef CRL_APB_IOPLL_FRAC_CFG_DATA_MASK
 #define CRL_APB_IOPLL_FRAC_CFG_DATA_DEFVAL                     0x00000000
 #define CRL_APB_IOPLL_FRAC_CFG_DATA_SHIFT                      0
 #define CRL_APB_IOPLL_FRAC_CFG_DATA_MASK                       0x0000FFFFU
@@ -459,9 +459,9 @@
 /*
 * PLL loop filter resistor control
 */
-#undef CRF_APB_APLL_CFG_RES_DEFVAL 
-#undef CRF_APB_APLL_CFG_RES_SHIFT 
-#undef CRF_APB_APLL_CFG_RES_MASK 
+#undef CRF_APB_APLL_CFG_RES_DEFVAL
+#undef CRF_APB_APLL_CFG_RES_SHIFT
+#undef CRF_APB_APLL_CFG_RES_MASK
 #define CRF_APB_APLL_CFG_RES_DEFVAL                            0x00000000
 #define CRF_APB_APLL_CFG_RES_SHIFT                             0
 #define CRF_APB_APLL_CFG_RES_MASK                              0x0000000FU
@@ -469,9 +469,9 @@
 /*
 * PLL charge pump control
 */
-#undef CRF_APB_APLL_CFG_CP_DEFVAL 
-#undef CRF_APB_APLL_CFG_CP_SHIFT 
-#undef CRF_APB_APLL_CFG_CP_MASK 
+#undef CRF_APB_APLL_CFG_CP_DEFVAL
+#undef CRF_APB_APLL_CFG_CP_SHIFT
+#undef CRF_APB_APLL_CFG_CP_MASK
 #define CRF_APB_APLL_CFG_CP_DEFVAL                             0x00000000
 #define CRF_APB_APLL_CFG_CP_SHIFT                              5
 #define CRF_APB_APLL_CFG_CP_MASK                               0x000001E0U
@@ -479,9 +479,9 @@
 /*
 * PLL loop filter high frequency capacitor control
 */
-#undef CRF_APB_APLL_CFG_LFHF_DEFVAL 
-#undef CRF_APB_APLL_CFG_LFHF_SHIFT 
-#undef CRF_APB_APLL_CFG_LFHF_MASK 
+#undef CRF_APB_APLL_CFG_LFHF_DEFVAL
+#undef CRF_APB_APLL_CFG_LFHF_SHIFT
+#undef CRF_APB_APLL_CFG_LFHF_MASK
 #define CRF_APB_APLL_CFG_LFHF_DEFVAL                           0x00000000
 #define CRF_APB_APLL_CFG_LFHF_SHIFT                            10
 #define CRF_APB_APLL_CFG_LFHF_MASK                             0x00000C00U
@@ -489,9 +489,9 @@
 /*
 * Lock circuit counter setting
 */
-#undef CRF_APB_APLL_CFG_LOCK_CNT_DEFVAL 
-#undef CRF_APB_APLL_CFG_LOCK_CNT_SHIFT 
-#undef CRF_APB_APLL_CFG_LOCK_CNT_MASK 
+#undef CRF_APB_APLL_CFG_LOCK_CNT_DEFVAL
+#undef CRF_APB_APLL_CFG_LOCK_CNT_SHIFT
+#undef CRF_APB_APLL_CFG_LOCK_CNT_MASK
 #define CRF_APB_APLL_CFG_LOCK_CNT_DEFVAL                       0x00000000
 #define CRF_APB_APLL_CFG_LOCK_CNT_SHIFT                        13
 #define CRF_APB_APLL_CFG_LOCK_CNT_MASK                         0x007FE000U
@@ -499,9 +499,9 @@
 /*
 * Lock circuit configuration settings for lock windowsize
 */
-#undef CRF_APB_APLL_CFG_LOCK_DLY_DEFVAL 
-#undef CRF_APB_APLL_CFG_LOCK_DLY_SHIFT 
-#undef CRF_APB_APLL_CFG_LOCK_DLY_MASK 
+#undef CRF_APB_APLL_CFG_LOCK_DLY_DEFVAL
+#undef CRF_APB_APLL_CFG_LOCK_DLY_SHIFT
+#undef CRF_APB_APLL_CFG_LOCK_DLY_MASK
 #define CRF_APB_APLL_CFG_LOCK_DLY_DEFVAL                       0x00000000
 #define CRF_APB_APLL_CFG_LOCK_DLY_SHIFT                        25
 #define CRF_APB_APLL_CFG_LOCK_DLY_MASK                         0xFE000000U
@@ -511,9 +511,9 @@
     * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour
     * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
 */
-#undef CRF_APB_APLL_CTRL_PRE_SRC_DEFVAL 
-#undef CRF_APB_APLL_CTRL_PRE_SRC_SHIFT 
-#undef CRF_APB_APLL_CTRL_PRE_SRC_MASK 
+#undef CRF_APB_APLL_CTRL_PRE_SRC_DEFVAL
+#undef CRF_APB_APLL_CTRL_PRE_SRC_SHIFT
+#undef CRF_APB_APLL_CTRL_PRE_SRC_MASK
 #define CRF_APB_APLL_CTRL_PRE_SRC_DEFVAL                       0x00012C09
 #define CRF_APB_APLL_CTRL_PRE_SRC_SHIFT                        20
 #define CRF_APB_APLL_CTRL_PRE_SRC_MASK                         0x00700000U
@@ -521,9 +521,9 @@
 /*
 * The integer portion of the feedback divider to the PLL
 */
-#undef CRF_APB_APLL_CTRL_FBDIV_DEFVAL 
-#undef CRF_APB_APLL_CTRL_FBDIV_SHIFT 
-#undef CRF_APB_APLL_CTRL_FBDIV_MASK 
+#undef CRF_APB_APLL_CTRL_FBDIV_DEFVAL
+#undef CRF_APB_APLL_CTRL_FBDIV_SHIFT
+#undef CRF_APB_APLL_CTRL_FBDIV_MASK
 #define CRF_APB_APLL_CTRL_FBDIV_DEFVAL                         0x00012C09
 #define CRF_APB_APLL_CTRL_FBDIV_SHIFT                          8
 #define CRF_APB_APLL_CTRL_FBDIV_MASK                           0x00007F00U
@@ -532,9 +532,9 @@
 * This turns on the divide by 2 that is inside of the PLL. This does not c
     * hange the VCO frequency, just the output frequency
 */
-#undef CRF_APB_APLL_CTRL_DIV2_DEFVAL 
-#undef CRF_APB_APLL_CTRL_DIV2_SHIFT 
-#undef CRF_APB_APLL_CTRL_DIV2_MASK 
+#undef CRF_APB_APLL_CTRL_DIV2_DEFVAL
+#undef CRF_APB_APLL_CTRL_DIV2_SHIFT
+#undef CRF_APB_APLL_CTRL_DIV2_MASK
 #define CRF_APB_APLL_CTRL_DIV2_DEFVAL                          0x00012C09
 #define CRF_APB_APLL_CTRL_DIV2_SHIFT                           16
 #define CRF_APB_APLL_CTRL_DIV2_MASK                            0x00010000U
@@ -545,9 +545,9 @@
     * clock and 4 cycles of the new clock. This is not usually an issue, but d
     * esigners must be aware.)
 */
-#undef CRF_APB_APLL_CTRL_BYPASS_DEFVAL 
-#undef CRF_APB_APLL_CTRL_BYPASS_SHIFT 
-#undef CRF_APB_APLL_CTRL_BYPASS_MASK 
+#undef CRF_APB_APLL_CTRL_BYPASS_DEFVAL
+#undef CRF_APB_APLL_CTRL_BYPASS_SHIFT
+#undef CRF_APB_APLL_CTRL_BYPASS_MASK
 #define CRF_APB_APLL_CTRL_BYPASS_DEFVAL                        0x00012C09
 #define CRF_APB_APLL_CTRL_BYPASS_SHIFT                         3
 #define CRF_APB_APLL_CTRL_BYPASS_MASK                          0x00000008U
@@ -556,9 +556,9 @@
 * Asserts Reset to the PLL. When asserting reset, the PLL must already be
     * in BYPASS.
 */
-#undef CRF_APB_APLL_CTRL_RESET_DEFVAL 
-#undef CRF_APB_APLL_CTRL_RESET_SHIFT 
-#undef CRF_APB_APLL_CTRL_RESET_MASK 
+#undef CRF_APB_APLL_CTRL_RESET_DEFVAL
+#undef CRF_APB_APLL_CTRL_RESET_SHIFT
+#undef CRF_APB_APLL_CTRL_RESET_MASK
 #define CRF_APB_APLL_CTRL_RESET_DEFVAL                         0x00012C09
 #define CRF_APB_APLL_CTRL_RESET_SHIFT                          0
 #define CRF_APB_APLL_CTRL_RESET_MASK                           0x00000001U
@@ -567,9 +567,9 @@
 * Asserts Reset to the PLL. When asserting reset, the PLL must already be
     * in BYPASS.
 */
-#undef CRF_APB_APLL_CTRL_RESET_DEFVAL 
-#undef CRF_APB_APLL_CTRL_RESET_SHIFT 
-#undef CRF_APB_APLL_CTRL_RESET_MASK 
+#undef CRF_APB_APLL_CTRL_RESET_DEFVAL
+#undef CRF_APB_APLL_CTRL_RESET_SHIFT
+#undef CRF_APB_APLL_CTRL_RESET_MASK
 #define CRF_APB_APLL_CTRL_RESET_DEFVAL                         0x00012C09
 #define CRF_APB_APLL_CTRL_RESET_SHIFT                          0
 #define CRF_APB_APLL_CTRL_RESET_MASK                           0x00000001U
@@ -577,9 +577,9 @@
 /*
 * APLL is locked
 */
-#undef CRF_APB_PLL_STATUS_APLL_LOCK_DEFVAL 
-#undef CRF_APB_PLL_STATUS_APLL_LOCK_SHIFT 
-#undef CRF_APB_PLL_STATUS_APLL_LOCK_MASK 
+#undef CRF_APB_PLL_STATUS_APLL_LOCK_DEFVAL
+#undef CRF_APB_PLL_STATUS_APLL_LOCK_SHIFT
+#undef CRF_APB_PLL_STATUS_APLL_LOCK_MASK
 #define CRF_APB_PLL_STATUS_APLL_LOCK_DEFVAL                    0x00000038
 #define CRF_APB_PLL_STATUS_APLL_LOCK_SHIFT                     0
 #define CRF_APB_PLL_STATUS_APLL_LOCK_MASK                      0x00000001U
@@ -591,9 +591,9 @@
     * clock and 4 cycles of the new clock. This is not usually an issue, but d
     * esigners must be aware.)
 */
-#undef CRF_APB_APLL_CTRL_BYPASS_DEFVAL 
-#undef CRF_APB_APLL_CTRL_BYPASS_SHIFT 
-#undef CRF_APB_APLL_CTRL_BYPASS_MASK 
+#undef CRF_APB_APLL_CTRL_BYPASS_DEFVAL
+#undef CRF_APB_APLL_CTRL_BYPASS_SHIFT
+#undef CRF_APB_APLL_CTRL_BYPASS_MASK
 #define CRF_APB_APLL_CTRL_BYPASS_DEFVAL                        0x00012C09
 #define CRF_APB_APLL_CTRL_BYPASS_SHIFT                         3
 #define CRF_APB_APLL_CTRL_BYPASS_MASK                          0x00000008U
@@ -601,9 +601,9 @@
 /*
 * Divisor value for this clock.
 */
-#undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 
-#undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT 
-#undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK 
+#undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_DEFVAL
+#undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT
+#undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK
 #define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_DEFVAL               0x00000400
 #define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT                8
 #define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK                 0x00003F00U
@@ -613,9 +613,9 @@
     * ores all fractional data. When 1, PLL is in fractional mode and uses DAT
     * A of this register for the fractional portion of the feedback divider.
 */
-#undef CRF_APB_APLL_FRAC_CFG_ENABLED_DEFVAL 
-#undef CRF_APB_APLL_FRAC_CFG_ENABLED_SHIFT 
-#undef CRF_APB_APLL_FRAC_CFG_ENABLED_MASK 
+#undef CRF_APB_APLL_FRAC_CFG_ENABLED_DEFVAL
+#undef CRF_APB_APLL_FRAC_CFG_ENABLED_SHIFT
+#undef CRF_APB_APLL_FRAC_CFG_ENABLED_MASK
 #define CRF_APB_APLL_FRAC_CFG_ENABLED_DEFVAL                   0x00000000
 #define CRF_APB_APLL_FRAC_CFG_ENABLED_SHIFT                    31
 #define CRF_APB_APLL_FRAC_CFG_ENABLED_MASK                     0x80000000U
@@ -623,9 +623,9 @@
 /*
 * Fractional value for the Feedback value.
 */
-#undef CRF_APB_APLL_FRAC_CFG_DATA_DEFVAL 
-#undef CRF_APB_APLL_FRAC_CFG_DATA_SHIFT 
-#undef CRF_APB_APLL_FRAC_CFG_DATA_MASK 
+#undef CRF_APB_APLL_FRAC_CFG_DATA_DEFVAL
+#undef CRF_APB_APLL_FRAC_CFG_DATA_SHIFT
+#undef CRF_APB_APLL_FRAC_CFG_DATA_MASK
 #define CRF_APB_APLL_FRAC_CFG_DATA_DEFVAL                      0x00000000
 #define CRF_APB_APLL_FRAC_CFG_DATA_SHIFT                       0
 #define CRF_APB_APLL_FRAC_CFG_DATA_MASK                        0x0000FFFFU
@@ -633,9 +633,9 @@
 /*
 * PLL loop filter resistor control
 */
-#undef CRF_APB_DPLL_CFG_RES_DEFVAL 
-#undef CRF_APB_DPLL_CFG_RES_SHIFT 
-#undef CRF_APB_DPLL_CFG_RES_MASK 
+#undef CRF_APB_DPLL_CFG_RES_DEFVAL
+#undef CRF_APB_DPLL_CFG_RES_SHIFT
+#undef CRF_APB_DPLL_CFG_RES_MASK
 #define CRF_APB_DPLL_CFG_RES_DEFVAL                            0x00000000
 #define CRF_APB_DPLL_CFG_RES_SHIFT                             0
 #define CRF_APB_DPLL_CFG_RES_MASK                              0x0000000FU
@@ -643,9 +643,9 @@
 /*
 * PLL charge pump control
 */
-#undef CRF_APB_DPLL_CFG_CP_DEFVAL 
-#undef CRF_APB_DPLL_CFG_CP_SHIFT 
-#undef CRF_APB_DPLL_CFG_CP_MASK 
+#undef CRF_APB_DPLL_CFG_CP_DEFVAL
+#undef CRF_APB_DPLL_CFG_CP_SHIFT
+#undef CRF_APB_DPLL_CFG_CP_MASK
 #define CRF_APB_DPLL_CFG_CP_DEFVAL                             0x00000000
 #define CRF_APB_DPLL_CFG_CP_SHIFT                              5
 #define CRF_APB_DPLL_CFG_CP_MASK                               0x000001E0U
@@ -653,9 +653,9 @@
 /*
 * PLL loop filter high frequency capacitor control
 */
-#undef CRF_APB_DPLL_CFG_LFHF_DEFVAL 
-#undef CRF_APB_DPLL_CFG_LFHF_SHIFT 
-#undef CRF_APB_DPLL_CFG_LFHF_MASK 
+#undef CRF_APB_DPLL_CFG_LFHF_DEFVAL
+#undef CRF_APB_DPLL_CFG_LFHF_SHIFT
+#undef CRF_APB_DPLL_CFG_LFHF_MASK
 #define CRF_APB_DPLL_CFG_LFHF_DEFVAL                           0x00000000
 #define CRF_APB_DPLL_CFG_LFHF_SHIFT                            10
 #define CRF_APB_DPLL_CFG_LFHF_MASK                             0x00000C00U
@@ -663,9 +663,9 @@
 /*
 * Lock circuit counter setting
 */
-#undef CRF_APB_DPLL_CFG_LOCK_CNT_DEFVAL 
-#undef CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT 
-#undef CRF_APB_DPLL_CFG_LOCK_CNT_MASK 
+#undef CRF_APB_DPLL_CFG_LOCK_CNT_DEFVAL
+#undef CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT
+#undef CRF_APB_DPLL_CFG_LOCK_CNT_MASK
 #define CRF_APB_DPLL_CFG_LOCK_CNT_DEFVAL                       0x00000000
 #define CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT                        13
 #define CRF_APB_DPLL_CFG_LOCK_CNT_MASK                         0x007FE000U
@@ -673,9 +673,9 @@
 /*
 * Lock circuit configuration settings for lock windowsize
 */
-#undef CRF_APB_DPLL_CFG_LOCK_DLY_DEFVAL 
-#undef CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT 
-#undef CRF_APB_DPLL_CFG_LOCK_DLY_MASK 
+#undef CRF_APB_DPLL_CFG_LOCK_DLY_DEFVAL
+#undef CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT
+#undef CRF_APB_DPLL_CFG_LOCK_DLY_MASK
 #define CRF_APB_DPLL_CFG_LOCK_DLY_DEFVAL                       0x00000000
 #define CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT                        25
 #define CRF_APB_DPLL_CFG_LOCK_DLY_MASK                         0xFE000000U
@@ -685,9 +685,9 @@
     * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour
     * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
 */
-#undef CRF_APB_DPLL_CTRL_PRE_SRC_DEFVAL 
-#undef CRF_APB_DPLL_CTRL_PRE_SRC_SHIFT 
-#undef CRF_APB_DPLL_CTRL_PRE_SRC_MASK 
+#undef CRF_APB_DPLL_CTRL_PRE_SRC_DEFVAL
+#undef CRF_APB_DPLL_CTRL_PRE_SRC_SHIFT
+#undef CRF_APB_DPLL_CTRL_PRE_SRC_MASK
 #define CRF_APB_DPLL_CTRL_PRE_SRC_DEFVAL                       0x00002C09
 #define CRF_APB_DPLL_CTRL_PRE_SRC_SHIFT                        20
 #define CRF_APB_DPLL_CTRL_PRE_SRC_MASK                         0x00700000U
@@ -695,9 +695,9 @@
 /*
 * The integer portion of the feedback divider to the PLL
 */
-#undef CRF_APB_DPLL_CTRL_FBDIV_DEFVAL 
-#undef CRF_APB_DPLL_CTRL_FBDIV_SHIFT 
-#undef CRF_APB_DPLL_CTRL_FBDIV_MASK 
+#undef CRF_APB_DPLL_CTRL_FBDIV_DEFVAL
+#undef CRF_APB_DPLL_CTRL_FBDIV_SHIFT
+#undef CRF_APB_DPLL_CTRL_FBDIV_MASK
 #define CRF_APB_DPLL_CTRL_FBDIV_DEFVAL                         0x00002C09
 #define CRF_APB_DPLL_CTRL_FBDIV_SHIFT                          8
 #define CRF_APB_DPLL_CTRL_FBDIV_MASK                           0x00007F00U
@@ -706,9 +706,9 @@
 * This turns on the divide by 2 that is inside of the PLL. This does not c
     * hange the VCO frequency, just the output frequency
 */
-#undef CRF_APB_DPLL_CTRL_DIV2_DEFVAL 
-#undef CRF_APB_DPLL_CTRL_DIV2_SHIFT 
-#undef CRF_APB_DPLL_CTRL_DIV2_MASK 
+#undef CRF_APB_DPLL_CTRL_DIV2_DEFVAL
+#undef CRF_APB_DPLL_CTRL_DIV2_SHIFT
+#undef CRF_APB_DPLL_CTRL_DIV2_MASK
 #define CRF_APB_DPLL_CTRL_DIV2_DEFVAL                          0x00002C09
 #define CRF_APB_DPLL_CTRL_DIV2_SHIFT                           16
 #define CRF_APB_DPLL_CTRL_DIV2_MASK                            0x00010000U
@@ -719,9 +719,9 @@
     * clock and 4 cycles of the new clock. This is not usually an issue, but d
     * esigners must be aware.)
 */
-#undef CRF_APB_DPLL_CTRL_BYPASS_DEFVAL 
-#undef CRF_APB_DPLL_CTRL_BYPASS_SHIFT 
-#undef CRF_APB_DPLL_CTRL_BYPASS_MASK 
+#undef CRF_APB_DPLL_CTRL_BYPASS_DEFVAL
+#undef CRF_APB_DPLL_CTRL_BYPASS_SHIFT
+#undef CRF_APB_DPLL_CTRL_BYPASS_MASK
 #define CRF_APB_DPLL_CTRL_BYPASS_DEFVAL                        0x00002C09
 #define CRF_APB_DPLL_CTRL_BYPASS_SHIFT                         3
 #define CRF_APB_DPLL_CTRL_BYPASS_MASK                          0x00000008U
@@ -730,9 +730,9 @@
 * Asserts Reset to the PLL. When asserting reset, the PLL must already be
     * in BYPASS.
 */
-#undef CRF_APB_DPLL_CTRL_RESET_DEFVAL 
-#undef CRF_APB_DPLL_CTRL_RESET_SHIFT 
-#undef CRF_APB_DPLL_CTRL_RESET_MASK 
+#undef CRF_APB_DPLL_CTRL_RESET_DEFVAL
+#undef CRF_APB_DPLL_CTRL_RESET_SHIFT
+#undef CRF_APB_DPLL_CTRL_RESET_MASK
 #define CRF_APB_DPLL_CTRL_RESET_DEFVAL                         0x00002C09
 #define CRF_APB_DPLL_CTRL_RESET_SHIFT                          0
 #define CRF_APB_DPLL_CTRL_RESET_MASK                           0x00000001U
@@ -741,9 +741,9 @@
 * Asserts Reset to the PLL. When asserting reset, the PLL must already be
     * in BYPASS.
 */
-#undef CRF_APB_DPLL_CTRL_RESET_DEFVAL 
-#undef CRF_APB_DPLL_CTRL_RESET_SHIFT 
-#undef CRF_APB_DPLL_CTRL_RESET_MASK 
+#undef CRF_APB_DPLL_CTRL_RESET_DEFVAL
+#undef CRF_APB_DPLL_CTRL_RESET_SHIFT
+#undef CRF_APB_DPLL_CTRL_RESET_MASK
 #define CRF_APB_DPLL_CTRL_RESET_DEFVAL                         0x00002C09
 #define CRF_APB_DPLL_CTRL_RESET_SHIFT                          0
 #define CRF_APB_DPLL_CTRL_RESET_MASK                           0x00000001U
@@ -751,9 +751,9 @@
 /*
 * DPLL is locked
 */
-#undef CRF_APB_PLL_STATUS_DPLL_LOCK_DEFVAL 
-#undef CRF_APB_PLL_STATUS_DPLL_LOCK_SHIFT 
-#undef CRF_APB_PLL_STATUS_DPLL_LOCK_MASK 
+#undef CRF_APB_PLL_STATUS_DPLL_LOCK_DEFVAL
+#undef CRF_APB_PLL_STATUS_DPLL_LOCK_SHIFT
+#undef CRF_APB_PLL_STATUS_DPLL_LOCK_MASK
 #define CRF_APB_PLL_STATUS_DPLL_LOCK_DEFVAL                    0x00000038
 #define CRF_APB_PLL_STATUS_DPLL_LOCK_SHIFT                     1
 #define CRF_APB_PLL_STATUS_DPLL_LOCK_MASK                      0x00000002U
@@ -765,9 +765,9 @@
     * clock and 4 cycles of the new clock. This is not usually an issue, but d
     * esigners must be aware.)
 */
-#undef CRF_APB_DPLL_CTRL_BYPASS_DEFVAL 
-#undef CRF_APB_DPLL_CTRL_BYPASS_SHIFT 
-#undef CRF_APB_DPLL_CTRL_BYPASS_MASK 
+#undef CRF_APB_DPLL_CTRL_BYPASS_DEFVAL
+#undef CRF_APB_DPLL_CTRL_BYPASS_SHIFT
+#undef CRF_APB_DPLL_CTRL_BYPASS_MASK
 #define CRF_APB_DPLL_CTRL_BYPASS_DEFVAL                        0x00002C09
 #define CRF_APB_DPLL_CTRL_BYPASS_SHIFT                         3
 #define CRF_APB_DPLL_CTRL_BYPASS_MASK                          0x00000008U
@@ -775,9 +775,9 @@
 /*
 * Divisor value for this clock.
 */
-#undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 
-#undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT 
-#undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK 
+#undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL
+#undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT
+#undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK
 #define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL               0x00000400
 #define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT                8
 #define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK                 0x00003F00U
@@ -787,9 +787,9 @@
     * ores all fractional data. When 1, PLL is in fractional mode and uses DAT
     * A of this register for the fractional portion of the feedback divider.
 */
-#undef CRF_APB_DPLL_FRAC_CFG_ENABLED_DEFVAL 
-#undef CRF_APB_DPLL_FRAC_CFG_ENABLED_SHIFT 
-#undef CRF_APB_DPLL_FRAC_CFG_ENABLED_MASK 
+#undef CRF_APB_DPLL_FRAC_CFG_ENABLED_DEFVAL
+#undef CRF_APB_DPLL_FRAC_CFG_ENABLED_SHIFT
+#undef CRF_APB_DPLL_FRAC_CFG_ENABLED_MASK
 #define CRF_APB_DPLL_FRAC_CFG_ENABLED_DEFVAL                   0x00000000
 #define CRF_APB_DPLL_FRAC_CFG_ENABLED_SHIFT                    31
 #define CRF_APB_DPLL_FRAC_CFG_ENABLED_MASK                     0x80000000U
@@ -797,9 +797,9 @@
 /*
 * Fractional value for the Feedback value.
 */
-#undef CRF_APB_DPLL_FRAC_CFG_DATA_DEFVAL 
-#undef CRF_APB_DPLL_FRAC_CFG_DATA_SHIFT 
-#undef CRF_APB_DPLL_FRAC_CFG_DATA_MASK 
+#undef CRF_APB_DPLL_FRAC_CFG_DATA_DEFVAL
+#undef CRF_APB_DPLL_FRAC_CFG_DATA_SHIFT
+#undef CRF_APB_DPLL_FRAC_CFG_DATA_MASK
 #define CRF_APB_DPLL_FRAC_CFG_DATA_DEFVAL                      0x00000000
 #define CRF_APB_DPLL_FRAC_CFG_DATA_SHIFT                       0
 #define CRF_APB_DPLL_FRAC_CFG_DATA_MASK                        0x0000FFFFU
@@ -807,9 +807,9 @@
 /*
 * PLL loop filter resistor control
 */
-#undef CRF_APB_VPLL_CFG_RES_DEFVAL 
-#undef CRF_APB_VPLL_CFG_RES_SHIFT 
-#undef CRF_APB_VPLL_CFG_RES_MASK 
+#undef CRF_APB_VPLL_CFG_RES_DEFVAL
+#undef CRF_APB_VPLL_CFG_RES_SHIFT
+#undef CRF_APB_VPLL_CFG_RES_MASK
 #define CRF_APB_VPLL_CFG_RES_DEFVAL                            0x00000000
 #define CRF_APB_VPLL_CFG_RES_SHIFT                             0
 #define CRF_APB_VPLL_CFG_RES_MASK                              0x0000000FU
@@ -817,9 +817,9 @@
 /*
 * PLL charge pump control
 */
-#undef CRF_APB_VPLL_CFG_CP_DEFVAL 
-#undef CRF_APB_VPLL_CFG_CP_SHIFT 
-#undef CRF_APB_VPLL_CFG_CP_MASK 
+#undef CRF_APB_VPLL_CFG_CP_DEFVAL
+#undef CRF_APB_VPLL_CFG_CP_SHIFT
+#undef CRF_APB_VPLL_CFG_CP_MASK
 #define CRF_APB_VPLL_CFG_CP_DEFVAL                             0x00000000
 #define CRF_APB_VPLL_CFG_CP_SHIFT                              5
 #define CRF_APB_VPLL_CFG_CP_MASK                               0x000001E0U
@@ -827,9 +827,9 @@
 /*
 * PLL loop filter high frequency capacitor control
 */
-#undef CRF_APB_VPLL_CFG_LFHF_DEFVAL 
-#undef CRF_APB_VPLL_CFG_LFHF_SHIFT 
-#undef CRF_APB_VPLL_CFG_LFHF_MASK 
+#undef CRF_APB_VPLL_CFG_LFHF_DEFVAL
+#undef CRF_APB_VPLL_CFG_LFHF_SHIFT
+#undef CRF_APB_VPLL_CFG_LFHF_MASK
 #define CRF_APB_VPLL_CFG_LFHF_DEFVAL                           0x00000000
 #define CRF_APB_VPLL_CFG_LFHF_SHIFT                            10
 #define CRF_APB_VPLL_CFG_LFHF_MASK                             0x00000C00U
@@ -837,9 +837,9 @@
 /*
 * Lock circuit counter setting
 */
-#undef CRF_APB_VPLL_CFG_LOCK_CNT_DEFVAL 
-#undef CRF_APB_VPLL_CFG_LOCK_CNT_SHIFT 
-#undef CRF_APB_VPLL_CFG_LOCK_CNT_MASK 
+#undef CRF_APB_VPLL_CFG_LOCK_CNT_DEFVAL
+#undef CRF_APB_VPLL_CFG_LOCK_CNT_SHIFT
+#undef CRF_APB_VPLL_CFG_LOCK_CNT_MASK
 #define CRF_APB_VPLL_CFG_LOCK_CNT_DEFVAL                       0x00000000
 #define CRF_APB_VPLL_CFG_LOCK_CNT_SHIFT                        13
 #define CRF_APB_VPLL_CFG_LOCK_CNT_MASK                         0x007FE000U
@@ -847,9 +847,9 @@
 /*
 * Lock circuit configuration settings for lock windowsize
 */
-#undef CRF_APB_VPLL_CFG_LOCK_DLY_DEFVAL 
-#undef CRF_APB_VPLL_CFG_LOCK_DLY_SHIFT 
-#undef CRF_APB_VPLL_CFG_LOCK_DLY_MASK 
+#undef CRF_APB_VPLL_CFG_LOCK_DLY_DEFVAL
+#undef CRF_APB_VPLL_CFG_LOCK_DLY_SHIFT
+#undef CRF_APB_VPLL_CFG_LOCK_DLY_MASK
 #define CRF_APB_VPLL_CFG_LOCK_DLY_DEFVAL                       0x00000000
 #define CRF_APB_VPLL_CFG_LOCK_DLY_SHIFT                        25
 #define CRF_APB_VPLL_CFG_LOCK_DLY_MASK                         0xFE000000U
@@ -859,9 +859,9 @@
     * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour
     * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
 */
-#undef CRF_APB_VPLL_CTRL_PRE_SRC_DEFVAL 
-#undef CRF_APB_VPLL_CTRL_PRE_SRC_SHIFT 
-#undef CRF_APB_VPLL_CTRL_PRE_SRC_MASK 
+#undef CRF_APB_VPLL_CTRL_PRE_SRC_DEFVAL
+#undef CRF_APB_VPLL_CTRL_PRE_SRC_SHIFT
+#undef CRF_APB_VPLL_CTRL_PRE_SRC_MASK
 #define CRF_APB_VPLL_CTRL_PRE_SRC_DEFVAL                       0x00012809
 #define CRF_APB_VPLL_CTRL_PRE_SRC_SHIFT                        20
 #define CRF_APB_VPLL_CTRL_PRE_SRC_MASK                         0x00700000U
@@ -869,9 +869,9 @@
 /*
 * The integer portion of the feedback divider to the PLL
 */
-#undef CRF_APB_VPLL_CTRL_FBDIV_DEFVAL 
-#undef CRF_APB_VPLL_CTRL_FBDIV_SHIFT 
-#undef CRF_APB_VPLL_CTRL_FBDIV_MASK 
+#undef CRF_APB_VPLL_CTRL_FBDIV_DEFVAL
+#undef CRF_APB_VPLL_CTRL_FBDIV_SHIFT
+#undef CRF_APB_VPLL_CTRL_FBDIV_MASK
 #define CRF_APB_VPLL_CTRL_FBDIV_DEFVAL                         0x00012809
 #define CRF_APB_VPLL_CTRL_FBDIV_SHIFT                          8
 #define CRF_APB_VPLL_CTRL_FBDIV_MASK                           0x00007F00U
@@ -880,9 +880,9 @@
 * This turns on the divide by 2 that is inside of the PLL. This does not c
     * hange the VCO frequency, just the output frequency
 */
-#undef CRF_APB_VPLL_CTRL_DIV2_DEFVAL 
-#undef CRF_APB_VPLL_CTRL_DIV2_SHIFT 
-#undef CRF_APB_VPLL_CTRL_DIV2_MASK 
+#undef CRF_APB_VPLL_CTRL_DIV2_DEFVAL
+#undef CRF_APB_VPLL_CTRL_DIV2_SHIFT
+#undef CRF_APB_VPLL_CTRL_DIV2_MASK
 #define CRF_APB_VPLL_CTRL_DIV2_DEFVAL                          0x00012809
 #define CRF_APB_VPLL_CTRL_DIV2_SHIFT                           16
 #define CRF_APB_VPLL_CTRL_DIV2_MASK                            0x00010000U
@@ -893,9 +893,9 @@
     * clock and 4 cycles of the new clock. This is not usually an issue, but d
     * esigners must be aware.)
 */
-#undef CRF_APB_VPLL_CTRL_BYPASS_DEFVAL 
-#undef CRF_APB_VPLL_CTRL_BYPASS_SHIFT 
-#undef CRF_APB_VPLL_CTRL_BYPASS_MASK 
+#undef CRF_APB_VPLL_CTRL_BYPASS_DEFVAL
+#undef CRF_APB_VPLL_CTRL_BYPASS_SHIFT
+#undef CRF_APB_VPLL_CTRL_BYPASS_MASK
 #define CRF_APB_VPLL_CTRL_BYPASS_DEFVAL                        0x00012809
 #define CRF_APB_VPLL_CTRL_BYPASS_SHIFT                         3
 #define CRF_APB_VPLL_CTRL_BYPASS_MASK                          0x00000008U
@@ -904,9 +904,9 @@
 * Asserts Reset to the PLL. When asserting reset, the PLL must already be
     * in BYPASS.
 */
-#undef CRF_APB_VPLL_CTRL_RESET_DEFVAL 
-#undef CRF_APB_VPLL_CTRL_RESET_SHIFT 
-#undef CRF_APB_VPLL_CTRL_RESET_MASK 
+#undef CRF_APB_VPLL_CTRL_RESET_DEFVAL
+#undef CRF_APB_VPLL_CTRL_RESET_SHIFT
+#undef CRF_APB_VPLL_CTRL_RESET_MASK
 #define CRF_APB_VPLL_CTRL_RESET_DEFVAL                         0x00012809
 #define CRF_APB_VPLL_CTRL_RESET_SHIFT                          0
 #define CRF_APB_VPLL_CTRL_RESET_MASK                           0x00000001U
@@ -915,9 +915,9 @@
 * Asserts Reset to the PLL. When asserting reset, the PLL must already be
     * in BYPASS.
 */
-#undef CRF_APB_VPLL_CTRL_RESET_DEFVAL 
-#undef CRF_APB_VPLL_CTRL_RESET_SHIFT 
-#undef CRF_APB_VPLL_CTRL_RESET_MASK 
+#undef CRF_APB_VPLL_CTRL_RESET_DEFVAL
+#undef CRF_APB_VPLL_CTRL_RESET_SHIFT
+#undef CRF_APB_VPLL_CTRL_RESET_MASK
 #define CRF_APB_VPLL_CTRL_RESET_DEFVAL                         0x00012809
 #define CRF_APB_VPLL_CTRL_RESET_SHIFT                          0
 #define CRF_APB_VPLL_CTRL_RESET_MASK                           0x00000001U
@@ -925,9 +925,9 @@
 /*
 * VPLL is locked
 */
-#undef CRF_APB_PLL_STATUS_VPLL_LOCK_DEFVAL 
-#undef CRF_APB_PLL_STATUS_VPLL_LOCK_SHIFT 
-#undef CRF_APB_PLL_STATUS_VPLL_LOCK_MASK 
+#undef CRF_APB_PLL_STATUS_VPLL_LOCK_DEFVAL
+#undef CRF_APB_PLL_STATUS_VPLL_LOCK_SHIFT
+#undef CRF_APB_PLL_STATUS_VPLL_LOCK_MASK
 #define CRF_APB_PLL_STATUS_VPLL_LOCK_DEFVAL                    0x00000038
 #define CRF_APB_PLL_STATUS_VPLL_LOCK_SHIFT                     2
 #define CRF_APB_PLL_STATUS_VPLL_LOCK_MASK                      0x00000004U
@@ -939,9 +939,9 @@
     * clock and 4 cycles of the new clock. This is not usually an issue, but d
     * esigners must be aware.)
 */
-#undef CRF_APB_VPLL_CTRL_BYPASS_DEFVAL 
-#undef CRF_APB_VPLL_CTRL_BYPASS_SHIFT 
-#undef CRF_APB_VPLL_CTRL_BYPASS_MASK 
+#undef CRF_APB_VPLL_CTRL_BYPASS_DEFVAL
+#undef CRF_APB_VPLL_CTRL_BYPASS_SHIFT
+#undef CRF_APB_VPLL_CTRL_BYPASS_MASK
 #define CRF_APB_VPLL_CTRL_BYPASS_DEFVAL                        0x00012809
 #define CRF_APB_VPLL_CTRL_BYPASS_SHIFT                         3
 #define CRF_APB_VPLL_CTRL_BYPASS_MASK                          0x00000008U
@@ -949,9 +949,9 @@
 /*
 * Divisor value for this clock.
 */
-#undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 
-#undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT 
-#undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK 
+#undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL
+#undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT
+#undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK
 #define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL               0x00000400
 #define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT                8
 #define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK                 0x00003F00U
@@ -961,9 +961,9 @@
     * ores all fractional data. When 1, PLL is in fractional mode and uses DAT
     * A of this register for the fractional portion of the feedback divider.
 */
-#undef CRF_APB_VPLL_FRAC_CFG_ENABLED_DEFVAL 
-#undef CRF_APB_VPLL_FRAC_CFG_ENABLED_SHIFT 
-#undef CRF_APB_VPLL_FRAC_CFG_ENABLED_MASK 
+#undef CRF_APB_VPLL_FRAC_CFG_ENABLED_DEFVAL
+#undef CRF_APB_VPLL_FRAC_CFG_ENABLED_SHIFT
+#undef CRF_APB_VPLL_FRAC_CFG_ENABLED_MASK
 #define CRF_APB_VPLL_FRAC_CFG_ENABLED_DEFVAL                   0x00000000
 #define CRF_APB_VPLL_FRAC_CFG_ENABLED_SHIFT                    31
 #define CRF_APB_VPLL_FRAC_CFG_ENABLED_MASK                     0x80000000U
@@ -971,103 +971,103 @@
 /*
 * Fractional value for the Feedback value.
 */
-#undef CRF_APB_VPLL_FRAC_CFG_DATA_DEFVAL 
-#undef CRF_APB_VPLL_FRAC_CFG_DATA_SHIFT 
-#undef CRF_APB_VPLL_FRAC_CFG_DATA_MASK 
+#undef CRF_APB_VPLL_FRAC_CFG_DATA_DEFVAL
+#undef CRF_APB_VPLL_FRAC_CFG_DATA_SHIFT
+#undef CRF_APB_VPLL_FRAC_CFG_DATA_MASK
 #define CRF_APB_VPLL_FRAC_CFG_DATA_DEFVAL                      0x00000000
 #define CRF_APB_VPLL_FRAC_CFG_DATA_SHIFT                       0
 #define CRF_APB_VPLL_FRAC_CFG_DATA_MASK                        0x0000FFFFU
-#undef CRL_APB_GEM3_REF_CTRL_OFFSET 
+#undef CRL_APB_GEM3_REF_CTRL_OFFSET
 #define CRL_APB_GEM3_REF_CTRL_OFFSET                                               0XFF5E005C
-#undef CRL_APB_GEM_TSU_REF_CTRL_OFFSET 
+#undef CRL_APB_GEM_TSU_REF_CTRL_OFFSET
 #define CRL_APB_GEM_TSU_REF_CTRL_OFFSET                                            0XFF5E0100
-#undef CRL_APB_USB0_BUS_REF_CTRL_OFFSET 
+#undef CRL_APB_USB0_BUS_REF_CTRL_OFFSET
 #define CRL_APB_USB0_BUS_REF_CTRL_OFFSET                                           0XFF5E0060
-#undef CRL_APB_USB3_DUAL_REF_CTRL_OFFSET 
+#undef CRL_APB_USB3_DUAL_REF_CTRL_OFFSET
 #define CRL_APB_USB3_DUAL_REF_CTRL_OFFSET                                          0XFF5E004C
-#undef CRL_APB_QSPI_REF_CTRL_OFFSET 
+#undef CRL_APB_QSPI_REF_CTRL_OFFSET
 #define CRL_APB_QSPI_REF_CTRL_OFFSET                                               0XFF5E0068
-#undef CRL_APB_SDIO1_REF_CTRL_OFFSET 
+#undef CRL_APB_SDIO1_REF_CTRL_OFFSET
 #define CRL_APB_SDIO1_REF_CTRL_OFFSET                                              0XFF5E0070
-#undef IOU_SLCR_SDIO_CLK_CTRL_OFFSET 
+#undef IOU_SLCR_SDIO_CLK_CTRL_OFFSET
 #define IOU_SLCR_SDIO_CLK_CTRL_OFFSET                                              0XFF18030C
-#undef CRL_APB_UART0_REF_CTRL_OFFSET 
+#undef CRL_APB_UART0_REF_CTRL_OFFSET
 #define CRL_APB_UART0_REF_CTRL_OFFSET                                              0XFF5E0074
-#undef CRL_APB_UART1_REF_CTRL_OFFSET 
+#undef CRL_APB_UART1_REF_CTRL_OFFSET
 #define CRL_APB_UART1_REF_CTRL_OFFSET                                              0XFF5E0078
-#undef CRL_APB_I2C1_REF_CTRL_OFFSET 
+#undef CRL_APB_I2C1_REF_CTRL_OFFSET
 #define CRL_APB_I2C1_REF_CTRL_OFFSET                                               0XFF5E0124
-#undef CRL_APB_CAN1_REF_CTRL_OFFSET 
+#undef CRL_APB_CAN1_REF_CTRL_OFFSET
 #define CRL_APB_CAN1_REF_CTRL_OFFSET                                               0XFF5E0088
-#undef CRL_APB_CPU_R5_CTRL_OFFSET 
+#undef CRL_APB_CPU_R5_CTRL_OFFSET
 #define CRL_APB_CPU_R5_CTRL_OFFSET                                                 0XFF5E0090
-#undef CRL_APB_IOU_SWITCH_CTRL_OFFSET 
+#undef CRL_APB_IOU_SWITCH_CTRL_OFFSET
 #define CRL_APB_IOU_SWITCH_CTRL_OFFSET                                             0XFF5E009C
-#undef CRL_APB_PCAP_CTRL_OFFSET 
+#undef CRL_APB_PCAP_CTRL_OFFSET
 #define CRL_APB_PCAP_CTRL_OFFSET                                                   0XFF5E00A4
-#undef CRL_APB_LPD_SWITCH_CTRL_OFFSET 
+#undef CRL_APB_LPD_SWITCH_CTRL_OFFSET
 #define CRL_APB_LPD_SWITCH_CTRL_OFFSET                                             0XFF5E00A8
-#undef CRL_APB_LPD_LSBUS_CTRL_OFFSET 
+#undef CRL_APB_LPD_LSBUS_CTRL_OFFSET
 #define CRL_APB_LPD_LSBUS_CTRL_OFFSET                                              0XFF5E00AC
-#undef CRL_APB_DBG_LPD_CTRL_OFFSET 
+#undef CRL_APB_DBG_LPD_CTRL_OFFSET
 #define CRL_APB_DBG_LPD_CTRL_OFFSET                                                0XFF5E00B0
-#undef CRL_APB_ADMA_REF_CTRL_OFFSET 
+#undef CRL_APB_ADMA_REF_CTRL_OFFSET
 #define CRL_APB_ADMA_REF_CTRL_OFFSET                                               0XFF5E00B8
-#undef CRL_APB_PL0_REF_CTRL_OFFSET 
+#undef CRL_APB_PL0_REF_CTRL_OFFSET
 #define CRL_APB_PL0_REF_CTRL_OFFSET                                                0XFF5E00C0
-#undef CRL_APB_PL1_REF_CTRL_OFFSET 
+#undef CRL_APB_PL1_REF_CTRL_OFFSET
 #define CRL_APB_PL1_REF_CTRL_OFFSET                                                0XFF5E00C4
-#undef CRL_APB_PL2_REF_CTRL_OFFSET 
+#undef CRL_APB_PL2_REF_CTRL_OFFSET
 #define CRL_APB_PL2_REF_CTRL_OFFSET                                                0XFF5E00C8
-#undef CRL_APB_PL3_REF_CTRL_OFFSET 
+#undef CRL_APB_PL3_REF_CTRL_OFFSET
 #define CRL_APB_PL3_REF_CTRL_OFFSET                                                0XFF5E00CC
-#undef CRL_APB_AMS_REF_CTRL_OFFSET 
+#undef CRL_APB_AMS_REF_CTRL_OFFSET
 #define CRL_APB_AMS_REF_CTRL_OFFSET                                                0XFF5E0108
-#undef CRL_APB_DLL_REF_CTRL_OFFSET 
+#undef CRL_APB_DLL_REF_CTRL_OFFSET
 #define CRL_APB_DLL_REF_CTRL_OFFSET                                                0XFF5E0104
-#undef CRL_APB_TIMESTAMP_REF_CTRL_OFFSET 
+#undef CRL_APB_TIMESTAMP_REF_CTRL_OFFSET
 #define CRL_APB_TIMESTAMP_REF_CTRL_OFFSET                                          0XFF5E0128
-#undef CRF_APB_SATA_REF_CTRL_OFFSET 
+#undef CRF_APB_SATA_REF_CTRL_OFFSET
 #define CRF_APB_SATA_REF_CTRL_OFFSET                                               0XFD1A00A0
-#undef CRF_APB_DP_VIDEO_REF_CTRL_OFFSET 
+#undef CRF_APB_DP_VIDEO_REF_CTRL_OFFSET
 #define CRF_APB_DP_VIDEO_REF_CTRL_OFFSET                                           0XFD1A0070
-#undef CRF_APB_DP_AUDIO_REF_CTRL_OFFSET 
+#undef CRF_APB_DP_AUDIO_REF_CTRL_OFFSET
 #define CRF_APB_DP_AUDIO_REF_CTRL_OFFSET                                           0XFD1A0074
-#undef CRF_APB_DP_STC_REF_CTRL_OFFSET 
+#undef CRF_APB_DP_STC_REF_CTRL_OFFSET
 #define CRF_APB_DP_STC_REF_CTRL_OFFSET                                             0XFD1A007C
-#undef CRF_APB_ACPU_CTRL_OFFSET 
+#undef CRF_APB_ACPU_CTRL_OFFSET
 #define CRF_APB_ACPU_CTRL_OFFSET                                                   0XFD1A0060
-#undef CRF_APB_DBG_FPD_CTRL_OFFSET 
+#undef CRF_APB_DBG_FPD_CTRL_OFFSET
 #define CRF_APB_DBG_FPD_CTRL_OFFSET                                                0XFD1A0068
-#undef CRF_APB_DDR_CTRL_OFFSET 
+#undef CRF_APB_DDR_CTRL_OFFSET
 #define CRF_APB_DDR_CTRL_OFFSET                                                    0XFD1A0080
-#undef CRF_APB_GPU_REF_CTRL_OFFSET 
+#undef CRF_APB_GPU_REF_CTRL_OFFSET
 #define CRF_APB_GPU_REF_CTRL_OFFSET                                                0XFD1A0084
-#undef CRF_APB_GDMA_REF_CTRL_OFFSET 
+#undef CRF_APB_GDMA_REF_CTRL_OFFSET
 #define CRF_APB_GDMA_REF_CTRL_OFFSET                                               0XFD1A00B8
-#undef CRF_APB_DPDMA_REF_CTRL_OFFSET 
+#undef CRF_APB_DPDMA_REF_CTRL_OFFSET
 #define CRF_APB_DPDMA_REF_CTRL_OFFSET                                              0XFD1A00BC
-#undef CRF_APB_TOPSW_MAIN_CTRL_OFFSET 
+#undef CRF_APB_TOPSW_MAIN_CTRL_OFFSET
 #define CRF_APB_TOPSW_MAIN_CTRL_OFFSET                                             0XFD1A00C0
-#undef CRF_APB_TOPSW_LSBUS_CTRL_OFFSET 
+#undef CRF_APB_TOPSW_LSBUS_CTRL_OFFSET
 #define CRF_APB_TOPSW_LSBUS_CTRL_OFFSET                                            0XFD1A00C4
-#undef CRF_APB_DBG_TSTMP_CTRL_OFFSET 
+#undef CRF_APB_DBG_TSTMP_CTRL_OFFSET
 #define CRF_APB_DBG_TSTMP_CTRL_OFFSET                                              0XFD1A00F8
-#undef IOU_SLCR_IOU_TTC_APB_CLK_OFFSET 
+#undef IOU_SLCR_IOU_TTC_APB_CLK_OFFSET
 #define IOU_SLCR_IOU_TTC_APB_CLK_OFFSET                                            0XFF180380
-#undef FPD_SLCR_WDT_CLK_SEL_OFFSET 
+#undef FPD_SLCR_WDT_CLK_SEL_OFFSET
 #define FPD_SLCR_WDT_CLK_SEL_OFFSET                                                0XFD610100
-#undef IOU_SLCR_WDT_CLK_SEL_OFFSET 
+#undef IOU_SLCR_WDT_CLK_SEL_OFFSET
 #define IOU_SLCR_WDT_CLK_SEL_OFFSET                                                0XFF180300
-#undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_OFFSET 
+#undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_OFFSET
 #define LPD_SLCR_CSUPMU_WDT_CLK_SEL_OFFSET                                         0XFF410050
 
 /*
 * Clock active for the RX channel
 */
-#undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_DEFVAL 
-#undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT 
-#undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_MASK 
+#undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_DEFVAL
+#undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT
+#undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_MASK
 #define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_DEFVAL                 0x00002500
 #define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT                  26
 #define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_MASK                   0x04000000U
@@ -1075,9 +1075,9 @@
 /*
 * Clock active signal. Switch to 0 to disable the clock
 */
-#undef CRL_APB_GEM3_REF_CTRL_CLKACT_DEFVAL 
-#undef CRL_APB_GEM3_REF_CTRL_CLKACT_SHIFT 
-#undef CRL_APB_GEM3_REF_CTRL_CLKACT_MASK 
+#undef CRL_APB_GEM3_REF_CTRL_CLKACT_DEFVAL
+#undef CRL_APB_GEM3_REF_CTRL_CLKACT_SHIFT
+#undef CRL_APB_GEM3_REF_CTRL_CLKACT_MASK
 #define CRL_APB_GEM3_REF_CTRL_CLKACT_DEFVAL                    0x00002500
 #define CRL_APB_GEM3_REF_CTRL_CLKACT_SHIFT                     25
 #define CRL_APB_GEM3_REF_CTRL_CLKACT_MASK                      0x02000000U
@@ -1085,9 +1085,9 @@
 /*
 * 6 bit divider
 */
-#undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_DEFVAL 
-#undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_SHIFT 
-#undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_MASK 
+#undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_DEFVAL
+#undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_SHIFT
+#undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_MASK
 #define CRL_APB_GEM3_REF_CTRL_DIVISOR1_DEFVAL                  0x00002500
 #define CRL_APB_GEM3_REF_CTRL_DIVISOR1_SHIFT                   16
 #define CRL_APB_GEM3_REF_CTRL_DIVISOR1_MASK                    0x003F0000U
@@ -1095,9 +1095,9 @@
 /*
 * 6 bit divider
 */
-#undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_DEFVAL 
-#undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_SHIFT 
-#undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_MASK 
+#undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_DEFVAL
+#undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_SHIFT
+#undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_MASK
 #define CRL_APB_GEM3_REF_CTRL_DIVISOR0_DEFVAL                  0x00002500
 #define CRL_APB_GEM3_REF_CTRL_DIVISOR0_SHIFT                   8
 #define CRL_APB_GEM3_REF_CTRL_DIVISOR0_MASK                    0x00003F00U
@@ -1107,9 +1107,9 @@
     * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
     *  usually an issue, but designers must be aware.)
 */
-#undef CRL_APB_GEM3_REF_CTRL_SRCSEL_DEFVAL 
-#undef CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT 
-#undef CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK 
+#undef CRL_APB_GEM3_REF_CTRL_SRCSEL_DEFVAL
+#undef CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT
+#undef CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK
 #define CRL_APB_GEM3_REF_CTRL_SRCSEL_DEFVAL                    0x00002500
 #define CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT                     0
 #define CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK                      0x00000007U
@@ -1117,9 +1117,9 @@
 /*
 * 6 bit divider
 */
-#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_DEFVAL 
-#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_SHIFT 
-#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_MASK 
+#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_DEFVAL
+#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_SHIFT
+#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_MASK
 #define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_DEFVAL               0x00051000
 #define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_SHIFT                8
 #define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_MASK                 0x00003F00U
@@ -1129,9 +1129,9 @@
     * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
     *  usually an issue, but designers must be aware.)
 */
-#undef CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_DEFVAL 
-#undef CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_SHIFT 
-#undef CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_MASK 
+#undef CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_DEFVAL
+#undef CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_SHIFT
+#undef CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_MASK
 #define CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_DEFVAL                 0x00051000
 #define CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_SHIFT                  0
 #define CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_MASK                   0x00000007U
@@ -1139,9 +1139,9 @@
 /*
 * 6 bit divider
 */
-#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_DEFVAL 
-#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_SHIFT 
-#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_MASK 
+#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_DEFVAL
+#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_SHIFT
+#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_MASK
 #define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_DEFVAL               0x00051000
 #define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_SHIFT                16
 #define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_MASK                 0x003F0000U
@@ -1149,9 +1149,9 @@
 /*
 * Clock active signal. Switch to 0 to disable the clock
 */
-#undef CRL_APB_GEM_TSU_REF_CTRL_CLKACT_DEFVAL 
-#undef CRL_APB_GEM_TSU_REF_CTRL_CLKACT_SHIFT 
-#undef CRL_APB_GEM_TSU_REF_CTRL_CLKACT_MASK 
+#undef CRL_APB_GEM_TSU_REF_CTRL_CLKACT_DEFVAL
+#undef CRL_APB_GEM_TSU_REF_CTRL_CLKACT_SHIFT
+#undef CRL_APB_GEM_TSU_REF_CTRL_CLKACT_MASK
 #define CRL_APB_GEM_TSU_REF_CTRL_CLKACT_DEFVAL                 0x00051000
 #define CRL_APB_GEM_TSU_REF_CTRL_CLKACT_SHIFT                  24
 #define CRL_APB_GEM_TSU_REF_CTRL_CLKACT_MASK                   0x01000000U
@@ -1159,9 +1159,9 @@
 /*
 * Clock active signal. Switch to 0 to disable the clock
 */
-#undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_DEFVAL 
-#undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT 
-#undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK 
+#undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_DEFVAL
+#undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT
+#undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK
 #define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_DEFVAL                0x00052000
 #define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT                 25
 #define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK                  0x02000000U
@@ -1169,9 +1169,9 @@
 /*
 * 6 bit divider
 */
-#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_DEFVAL 
-#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT 
-#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK 
+#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_DEFVAL
+#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT
+#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK
 #define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_DEFVAL              0x00052000
 #define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT               16
 #define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK                0x003F0000U
@@ -1179,9 +1179,9 @@
 /*
 * 6 bit divider
 */
-#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_DEFVAL 
-#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT 
-#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK 
+#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_DEFVAL
+#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT
+#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK
 #define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_DEFVAL              0x00052000
 #define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT               8
 #define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK                0x00003F00U
@@ -1191,9 +1191,9 @@
     * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
     *  usually an issue, but designers must be aware.)
 */
-#undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_DEFVAL 
-#undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT 
-#undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK 
+#undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_DEFVAL
+#undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT
+#undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK
 #define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_DEFVAL                0x00052000
 #define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT                 0
 #define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK                  0x00000007U
@@ -1201,9 +1201,9 @@
 /*
 * Clock active signal. Switch to 0 to disable the clock
 */
-#undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_DEFVAL 
-#undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT 
-#undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK 
+#undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_DEFVAL
+#undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT
+#undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK
 #define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_DEFVAL               0x00052000
 #define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT                25
 #define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK                 0x02000000U
@@ -1211,9 +1211,9 @@
 /*
 * 6 bit divider
 */
-#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_DEFVAL 
-#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT 
-#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK 
+#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_DEFVAL
+#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT
+#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK
 #define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_DEFVAL             0x00052000
 #define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT              16
 #define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK               0x003F0000U
@@ -1221,9 +1221,9 @@
 /*
 * 6 bit divider
 */
-#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_DEFVAL 
-#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT 
-#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK 
+#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_DEFVAL
+#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT
+#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK
 #define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_DEFVAL             0x00052000
 #define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT              8
 #define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK               0x00003F00U
@@ -1233,9 +1233,9 @@
     * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
     *  usually an issue, but designers must be aware.)
 */
-#undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_DEFVAL 
-#undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT 
-#undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK 
+#undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_DEFVAL
+#undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT
+#undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK
 #define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_DEFVAL               0x00052000
 #define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT                0
 #define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK                 0x00000007U
@@ -1243,9 +1243,9 @@
 /*
 * Clock active signal. Switch to 0 to disable the clock
 */
-#undef CRL_APB_QSPI_REF_CTRL_CLKACT_DEFVAL 
-#undef CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT 
-#undef CRL_APB_QSPI_REF_CTRL_CLKACT_MASK 
+#undef CRL_APB_QSPI_REF_CTRL_CLKACT_DEFVAL
+#undef CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT
+#undef CRL_APB_QSPI_REF_CTRL_CLKACT_MASK
 #define CRL_APB_QSPI_REF_CTRL_CLKACT_DEFVAL                    0x01000800
 #define CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT                     24
 #define CRL_APB_QSPI_REF_CTRL_CLKACT_MASK                      0x01000000U
@@ -1253,9 +1253,9 @@
 /*
 * 6 bit divider
 */
-#undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_DEFVAL 
-#undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT 
-#undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK 
+#undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_DEFVAL
+#undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT
+#undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK
 #define CRL_APB_QSPI_REF_CTRL_DIVISOR1_DEFVAL                  0x01000800
 #define CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT                   16
 #define CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK                    0x003F0000U
@@ -1263,9 +1263,9 @@
 /*
 * 6 bit divider
 */
-#undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_DEFVAL 
-#undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT 
-#undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK 
+#undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_DEFVAL
+#undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT
+#undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK
 #define CRL_APB_QSPI_REF_CTRL_DIVISOR0_DEFVAL                  0x01000800
 #define CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT                   8
 #define CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK                    0x00003F00U
@@ -1275,9 +1275,9 @@
     * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
     *  usually an issue, but designers must be aware.)
 */
-#undef CRL_APB_QSPI_REF_CTRL_SRCSEL_DEFVAL 
-#undef CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT 
-#undef CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK 
+#undef CRL_APB_QSPI_REF_CTRL_SRCSEL_DEFVAL
+#undef CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT
+#undef CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK
 #define CRL_APB_QSPI_REF_CTRL_SRCSEL_DEFVAL                    0x01000800
 #define CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT                     0
 #define CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK                      0x00000007U
@@ -1285,9 +1285,9 @@
 /*
 * Clock active signal. Switch to 0 to disable the clock
 */
-#undef CRL_APB_SDIO1_REF_CTRL_CLKACT_DEFVAL 
-#undef CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT 
-#undef CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK 
+#undef CRL_APB_SDIO1_REF_CTRL_CLKACT_DEFVAL
+#undef CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT
+#undef CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK
 #define CRL_APB_SDIO1_REF_CTRL_CLKACT_DEFVAL                   0x01000F00
 #define CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT                    24
 #define CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK                     0x01000000U
@@ -1295,9 +1295,9 @@
 /*
 * 6 bit divider
 */
-#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_DEFVAL 
-#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT 
-#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK 
+#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_DEFVAL
+#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT
+#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK
 #define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_DEFVAL                 0x01000F00
 #define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT                  16
 #define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK                   0x003F0000U
@@ -1305,9 +1305,9 @@
 /*
 * 6 bit divider
 */
-#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_DEFVAL 
-#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT 
-#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK 
+#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_DEFVAL
+#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT
+#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK
 #define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_DEFVAL                 0x01000F00
 #define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT                  8
 #define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK                   0x00003F00U
@@ -1317,9 +1317,9 @@
     * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
     *  usually an issue, but designers must be aware.)
 */
-#undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_DEFVAL 
-#undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT 
-#undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK 
+#undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_DEFVAL
+#undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT
+#undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK
 #define CRL_APB_SDIO1_REF_CTRL_SRCSEL_DEFVAL                   0x01000F00
 #define CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT                    0
 #define CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK                     0x00000007U
@@ -1328,9 +1328,9 @@
 * MIO pad selection for sdio1_rx_clk (feedback clock from the PAD) 0: MIO
     * [51] 1: MIO [76]
 */
-#undef IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_DEFVAL 
-#undef IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_SHIFT 
-#undef IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_MASK 
+#undef IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_DEFVAL
+#undef IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_SHIFT
+#undef IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_MASK
 #define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_DEFVAL         0x00000000
 #define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_SHIFT          17
 #define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_MASK           0x00020000U
@@ -1338,9 +1338,9 @@
 /*
 * Clock active signal. Switch to 0 to disable the clock
 */
-#undef CRL_APB_UART0_REF_CTRL_CLKACT_DEFVAL 
-#undef CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT 
-#undef CRL_APB_UART0_REF_CTRL_CLKACT_MASK 
+#undef CRL_APB_UART0_REF_CTRL_CLKACT_DEFVAL
+#undef CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT
+#undef CRL_APB_UART0_REF_CTRL_CLKACT_MASK
 #define CRL_APB_UART0_REF_CTRL_CLKACT_DEFVAL                   0x01001800
 #define CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT                    24
 #define CRL_APB_UART0_REF_CTRL_CLKACT_MASK                     0x01000000U
@@ -1348,9 +1348,9 @@
 /*
 * 6 bit divider
 */
-#undef CRL_APB_UART0_REF_CTRL_DIVISOR1_DEFVAL 
-#undef CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT 
-#undef CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK 
+#undef CRL_APB_UART0_REF_CTRL_DIVISOR1_DEFVAL
+#undef CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT
+#undef CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK
 #define CRL_APB_UART0_REF_CTRL_DIVISOR1_DEFVAL                 0x01001800
 #define CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT                  16
 #define CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK                   0x003F0000U
@@ -1358,9 +1358,9 @@
 /*
 * 6 bit divider
 */
-#undef CRL_APB_UART0_REF_CTRL_DIVISOR0_DEFVAL 
-#undef CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT 
-#undef CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK 
+#undef CRL_APB_UART0_REF_CTRL_DIVISOR0_DEFVAL
+#undef CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT
+#undef CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK
 #define CRL_APB_UART0_REF_CTRL_DIVISOR0_DEFVAL                 0x01001800
 #define CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT                  8
 #define CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK                   0x00003F00U
@@ -1370,9 +1370,9 @@
     * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
     *  usually an issue, but designers must be aware.)
 */
-#undef CRL_APB_UART0_REF_CTRL_SRCSEL_DEFVAL 
-#undef CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT 
-#undef CRL_APB_UART0_REF_CTRL_SRCSEL_MASK 
+#undef CRL_APB_UART0_REF_CTRL_SRCSEL_DEFVAL
+#undef CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT
+#undef CRL_APB_UART0_REF_CTRL_SRCSEL_MASK
 #define CRL_APB_UART0_REF_CTRL_SRCSEL_DEFVAL                   0x01001800
 #define CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT                    0
 #define CRL_APB_UART0_REF_CTRL_SRCSEL_MASK                     0x00000007U
@@ -1380,9 +1380,9 @@
 /*
 * Clock active signal. Switch to 0 to disable the clock
 */
-#undef CRL_APB_UART1_REF_CTRL_CLKACT_DEFVAL 
-#undef CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT 
-#undef CRL_APB_UART1_REF_CTRL_CLKACT_MASK 
+#undef CRL_APB_UART1_REF_CTRL_CLKACT_DEFVAL
+#undef CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT
+#undef CRL_APB_UART1_REF_CTRL_CLKACT_MASK
 #define CRL_APB_UART1_REF_CTRL_CLKACT_DEFVAL                   0x01001800
 #define CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT                    24
 #define CRL_APB_UART1_REF_CTRL_CLKACT_MASK                     0x01000000U
@@ -1390,9 +1390,9 @@
 /*
 * 6 bit divider
 */
-#undef CRL_APB_UART1_REF_CTRL_DIVISOR1_DEFVAL 
-#undef CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT 
-#undef CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK 
+#undef CRL_APB_UART1_REF_CTRL_DIVISOR1_DEFVAL
+#undef CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT
+#undef CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK
 #define CRL_APB_UART1_REF_CTRL_DIVISOR1_DEFVAL                 0x01001800
 #define CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT                  16
 #define CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK                   0x003F0000U
@@ -1400,9 +1400,9 @@
 /*
 * 6 bit divider
 */
-#undef CRL_APB_UART1_REF_CTRL_DIVISOR0_DEFVAL 
-#undef CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT 
-#undef CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK 
+#undef CRL_APB_UART1_REF_CTRL_DIVISOR0_DEFVAL
+#undef CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT
+#undef CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK
 #define CRL_APB_UART1_REF_CTRL_DIVISOR0_DEFVAL                 0x01001800
 #define CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT                  8
 #define CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK                   0x00003F00U
@@ -1412,9 +1412,9 @@
     * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
     *  usually an issue, but designers must be aware.)
 */
-#undef CRL_APB_UART1_REF_CTRL_SRCSEL_DEFVAL 
-#undef CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT 
-#undef CRL_APB_UART1_REF_CTRL_SRCSEL_MASK 
+#undef CRL_APB_UART1_REF_CTRL_SRCSEL_DEFVAL
+#undef CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT
+#undef CRL_APB_UART1_REF_CTRL_SRCSEL_MASK
 #define CRL_APB_UART1_REF_CTRL_SRCSEL_DEFVAL                   0x01001800
 #define CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT                    0
 #define CRL_APB_UART1_REF_CTRL_SRCSEL_MASK                     0x00000007U
@@ -1422,9 +1422,9 @@
 /*
 * Clock active signal. Switch to 0 to disable the clock
 */
-#undef CRL_APB_I2C1_REF_CTRL_CLKACT_DEFVAL 
-#undef CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT 
-#undef CRL_APB_I2C1_REF_CTRL_CLKACT_MASK 
+#undef CRL_APB_I2C1_REF_CTRL_CLKACT_DEFVAL
+#undef CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT
+#undef CRL_APB_I2C1_REF_CTRL_CLKACT_MASK
 #define CRL_APB_I2C1_REF_CTRL_CLKACT_DEFVAL                    0x01000500
 #define CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT                     24
 #define CRL_APB_I2C1_REF_CTRL_CLKACT_MASK                      0x01000000U
@@ -1432,9 +1432,9 @@
 /*
 * 6 bit divider
 */
-#undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_DEFVAL 
-#undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT 
-#undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK 
+#undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_DEFVAL
+#undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT
+#undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK
 #define CRL_APB_I2C1_REF_CTRL_DIVISOR1_DEFVAL                  0x01000500
 #define CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT                   16
 #define CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK                    0x003F0000U
@@ -1442,9 +1442,9 @@
 /*
 * 6 bit divider
 */
-#undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_DEFVAL 
-#undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT 
-#undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK 
+#undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_DEFVAL
+#undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT
+#undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK
 #define CRL_APB_I2C1_REF_CTRL_DIVISOR0_DEFVAL                  0x01000500
 #define CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT                   8
 #define CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK                    0x00003F00U
@@ -1454,9 +1454,9 @@
     * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
     *  usually an issue, but designers must be aware.)
 */
-#undef CRL_APB_I2C1_REF_CTRL_SRCSEL_DEFVAL 
-#undef CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT 
-#undef CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK 
+#undef CRL_APB_I2C1_REF_CTRL_SRCSEL_DEFVAL
+#undef CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT
+#undef CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK
 #define CRL_APB_I2C1_REF_CTRL_SRCSEL_DEFVAL                    0x01000500
 #define CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT                     0
 #define CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK                      0x00000007U
@@ -1464,9 +1464,9 @@
 /*
 * Clock active signal. Switch to 0 to disable the clock
 */
-#undef CRL_APB_CAN1_REF_CTRL_CLKACT_DEFVAL 
-#undef CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT 
-#undef CRL_APB_CAN1_REF_CTRL_CLKACT_MASK 
+#undef CRL_APB_CAN1_REF_CTRL_CLKACT_DEFVAL
+#undef CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT
+#undef CRL_APB_CAN1_REF_CTRL_CLKACT_MASK
 #define CRL_APB_CAN1_REF_CTRL_CLKACT_DEFVAL                    0x01001800
 #define CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT                     24
 #define CRL_APB_CAN1_REF_CTRL_CLKACT_MASK                      0x01000000U
@@ -1474,9 +1474,9 @@
 /*
 * 6 bit divider
 */
-#undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_DEFVAL 
-#undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_SHIFT 
-#undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_MASK 
+#undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_DEFVAL
+#undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_SHIFT
+#undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_MASK
 #define CRL_APB_CAN1_REF_CTRL_DIVISOR1_DEFVAL                  0x01001800
 #define CRL_APB_CAN1_REF_CTRL_DIVISOR1_SHIFT                   16
 #define CRL_APB_CAN1_REF_CTRL_DIVISOR1_MASK                    0x003F0000U
@@ -1484,9 +1484,9 @@
 /*
 * 6 bit divider
 */
-#undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_DEFVAL 
-#undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_SHIFT 
-#undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_MASK 
+#undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_DEFVAL
+#undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_SHIFT
+#undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_MASK
 #define CRL_APB_CAN1_REF_CTRL_DIVISOR0_DEFVAL                  0x01001800
 #define CRL_APB_CAN1_REF_CTRL_DIVISOR0_SHIFT                   8
 #define CRL_APB_CAN1_REF_CTRL_DIVISOR0_MASK                    0x00003F00U
@@ -1496,9 +1496,9 @@
     * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
     *  usually an issue, but designers must be aware.)
 */
-#undef CRL_APB_CAN1_REF_CTRL_SRCSEL_DEFVAL 
-#undef CRL_APB_CAN1_REF_CTRL_SRCSEL_SHIFT 
-#undef CRL_APB_CAN1_REF_CTRL_SRCSEL_MASK 
+#undef CRL_APB_CAN1_REF_CTRL_SRCSEL_DEFVAL
+#undef CRL_APB_CAN1_REF_CTRL_SRCSEL_SHIFT
+#undef CRL_APB_CAN1_REF_CTRL_SRCSEL_MASK
 #define CRL_APB_CAN1_REF_CTRL_SRCSEL_DEFVAL                    0x01001800
 #define CRL_APB_CAN1_REF_CTRL_SRCSEL_SHIFT                     0
 #define CRL_APB_CAN1_REF_CTRL_SRCSEL_MASK                      0x00000007U
@@ -1508,9 +1508,9 @@
     * nt transactions going from the FPD to the LPD and could lead to system h
     * ang
 */
-#undef CRL_APB_CPU_R5_CTRL_CLKACT_DEFVAL 
-#undef CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT 
-#undef CRL_APB_CPU_R5_CTRL_CLKACT_MASK 
+#undef CRL_APB_CPU_R5_CTRL_CLKACT_DEFVAL
+#undef CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT
+#undef CRL_APB_CPU_R5_CTRL_CLKACT_MASK
 #define CRL_APB_CPU_R5_CTRL_CLKACT_DEFVAL                      0x03000600
 #define CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT                       24
 #define CRL_APB_CPU_R5_CTRL_CLKACT_MASK                        0x01000000U
@@ -1518,9 +1518,9 @@
 /*
 * 6 bit divider
 */
-#undef CRL_APB_CPU_R5_CTRL_DIVISOR0_DEFVAL 
-#undef CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT 
-#undef CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK 
+#undef CRL_APB_CPU_R5_CTRL_DIVISOR0_DEFVAL
+#undef CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT
+#undef CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK
 #define CRL_APB_CPU_R5_CTRL_DIVISOR0_DEFVAL                    0x03000600
 #define CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT                     8
 #define CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK                      0x00003F00U
@@ -1530,9 +1530,9 @@
     * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
     *  usually an issue, but designers must be aware.)
 */
-#undef CRL_APB_CPU_R5_CTRL_SRCSEL_DEFVAL 
-#undef CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT 
-#undef CRL_APB_CPU_R5_CTRL_SRCSEL_MASK 
+#undef CRL_APB_CPU_R5_CTRL_SRCSEL_DEFVAL
+#undef CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT
+#undef CRL_APB_CPU_R5_CTRL_SRCSEL_MASK
 #define CRL_APB_CPU_R5_CTRL_SRCSEL_DEFVAL                      0x03000600
 #define CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT                       0
 #define CRL_APB_CPU_R5_CTRL_SRCSEL_MASK                        0x00000007U
@@ -1540,9 +1540,9 @@
 /*
 * Clock active signal. Switch to 0 to disable the clock
 */
-#undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_DEFVAL 
-#undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT 
-#undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK 
+#undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_DEFVAL
+#undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT
+#undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK
 #define CRL_APB_IOU_SWITCH_CTRL_CLKACT_DEFVAL                  0x00001500
 #define CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT                   24
 #define CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK                    0x01000000U
@@ -1550,9 +1550,9 @@
 /*
 * 6 bit divider
 */
-#undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_DEFVAL 
-#undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT 
-#undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK 
+#undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_DEFVAL
+#undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT
+#undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK
 #define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_DEFVAL                0x00001500
 #define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT                 8
 #define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK                  0x00003F00U
@@ -1562,9 +1562,9 @@
     * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
     *  usually an issue, but designers must be aware.)
 */
-#undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_DEFVAL 
-#undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT 
-#undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK 
+#undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_DEFVAL
+#undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT
+#undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK
 #define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_DEFVAL                  0x00001500
 #define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT                   0
 #define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK                    0x00000007U
@@ -1572,9 +1572,9 @@
 /*
 * Clock active signal. Switch to 0 to disable the clock
 */
-#undef CRL_APB_PCAP_CTRL_CLKACT_DEFVAL 
-#undef CRL_APB_PCAP_CTRL_CLKACT_SHIFT 
-#undef CRL_APB_PCAP_CTRL_CLKACT_MASK 
+#undef CRL_APB_PCAP_CTRL_CLKACT_DEFVAL
+#undef CRL_APB_PCAP_CTRL_CLKACT_SHIFT
+#undef CRL_APB_PCAP_CTRL_CLKACT_MASK
 #define CRL_APB_PCAP_CTRL_CLKACT_DEFVAL                        0x00001500
 #define CRL_APB_PCAP_CTRL_CLKACT_SHIFT                         24
 #define CRL_APB_PCAP_CTRL_CLKACT_MASK                          0x01000000U
@@ -1582,9 +1582,9 @@
 /*
 * 6 bit divider
 */
-#undef CRL_APB_PCAP_CTRL_DIVISOR0_DEFVAL 
-#undef CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT 
-#undef CRL_APB_PCAP_CTRL_DIVISOR0_MASK 
+#undef CRL_APB_PCAP_CTRL_DIVISOR0_DEFVAL
+#undef CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT
+#undef CRL_APB_PCAP_CTRL_DIVISOR0_MASK
 #define CRL_APB_PCAP_CTRL_DIVISOR0_DEFVAL                      0x00001500
 #define CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT                       8
 #define CRL_APB_PCAP_CTRL_DIVISOR0_MASK                        0x00003F00U
@@ -1594,9 +1594,9 @@
     * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
     *  usually an issue, but designers must be aware.)
 */
-#undef CRL_APB_PCAP_CTRL_SRCSEL_DEFVAL 
-#undef CRL_APB_PCAP_CTRL_SRCSEL_SHIFT 
-#undef CRL_APB_PCAP_CTRL_SRCSEL_MASK 
+#undef CRL_APB_PCAP_CTRL_SRCSEL_DEFVAL
+#undef CRL_APB_PCAP_CTRL_SRCSEL_SHIFT
+#undef CRL_APB_PCAP_CTRL_SRCSEL_MASK
 #define CRL_APB_PCAP_CTRL_SRCSEL_DEFVAL                        0x00001500
 #define CRL_APB_PCAP_CTRL_SRCSEL_SHIFT                         0
 #define CRL_APB_PCAP_CTRL_SRCSEL_MASK                          0x00000007U
@@ -1604,9 +1604,9 @@
 /*
 * Clock active signal. Switch to 0 to disable the clock
 */
-#undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_DEFVAL 
-#undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT 
-#undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK 
+#undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_DEFVAL
+#undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT
+#undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK
 #define CRL_APB_LPD_SWITCH_CTRL_CLKACT_DEFVAL                  0x01000500
 #define CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT                   24
 #define CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK                    0x01000000U
@@ -1614,9 +1614,9 @@
 /*
 * 6 bit divider
 */
-#undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_DEFVAL 
-#undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT 
-#undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK 
+#undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_DEFVAL
+#undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT
+#undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK
 #define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_DEFVAL                0x01000500
 #define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT                 8
 #define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK                  0x00003F00U
@@ -1626,9 +1626,9 @@
     * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
     *  usually an issue, but designers must be aware.)
 */
-#undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_DEFVAL 
-#undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT 
-#undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK 
+#undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_DEFVAL
+#undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT
+#undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK
 #define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_DEFVAL                  0x01000500
 #define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT                   0
 #define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK                    0x00000007U
@@ -1636,9 +1636,9 @@
 /*
 * Clock active signal. Switch to 0 to disable the clock
 */
-#undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_DEFVAL 
-#undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT 
-#undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK 
+#undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_DEFVAL
+#undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT
+#undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK
 #define CRL_APB_LPD_LSBUS_CTRL_CLKACT_DEFVAL                   0x01001800
 #define CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT                    24
 #define CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK                     0x01000000U
@@ -1646,9 +1646,9 @@
 /*
 * 6 bit divider
 */
-#undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_DEFVAL 
-#undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT 
-#undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK 
+#undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_DEFVAL
+#undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT
+#undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK
 #define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_DEFVAL                 0x01001800
 #define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT                  8
 #define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK                   0x00003F00U
@@ -1658,9 +1658,9 @@
     * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
     *  usually an issue, but designers must be aware.)
 */
-#undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_DEFVAL 
-#undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT 
-#undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK 
+#undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_DEFVAL
+#undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT
+#undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK
 #define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_DEFVAL                   0x01001800
 #define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT                    0
 #define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK                     0x00000007U
@@ -1668,9 +1668,9 @@
 /*
 * Clock active signal. Switch to 0 to disable the clock
 */
-#undef CRL_APB_DBG_LPD_CTRL_CLKACT_DEFVAL 
-#undef CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT 
-#undef CRL_APB_DBG_LPD_CTRL_CLKACT_MASK 
+#undef CRL_APB_DBG_LPD_CTRL_CLKACT_DEFVAL
+#undef CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT
+#undef CRL_APB_DBG_LPD_CTRL_CLKACT_MASK
 #define CRL_APB_DBG_LPD_CTRL_CLKACT_DEFVAL                     0x01002000
 #define CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT                      24
 #define CRL_APB_DBG_LPD_CTRL_CLKACT_MASK                       0x01000000U
@@ -1678,9 +1678,9 @@
 /*
 * 6 bit divider
 */
-#undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_DEFVAL 
-#undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT 
-#undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK 
+#undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_DEFVAL
+#undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT
+#undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK
 #define CRL_APB_DBG_LPD_CTRL_DIVISOR0_DEFVAL                   0x01002000
 #define CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT                    8
 #define CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK                     0x00003F00U
@@ -1690,9 +1690,9 @@
     * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
     *  usually an issue, but designers must be aware.)
 */
-#undef CRL_APB_DBG_LPD_CTRL_SRCSEL_DEFVAL 
-#undef CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT 
-#undef CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK 
+#undef CRL_APB_DBG_LPD_CTRL_SRCSEL_DEFVAL
+#undef CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT
+#undef CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK
 #define CRL_APB_DBG_LPD_CTRL_SRCSEL_DEFVAL                     0x01002000
 #define CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT                      0
 #define CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK                       0x00000007U
@@ -1700,9 +1700,9 @@
 /*
 * Clock active signal. Switch to 0 to disable the clock
 */
-#undef CRL_APB_ADMA_REF_CTRL_CLKACT_DEFVAL 
-#undef CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT 
-#undef CRL_APB_ADMA_REF_CTRL_CLKACT_MASK 
+#undef CRL_APB_ADMA_REF_CTRL_CLKACT_DEFVAL
+#undef CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT
+#undef CRL_APB_ADMA_REF_CTRL_CLKACT_MASK
 #define CRL_APB_ADMA_REF_CTRL_CLKACT_DEFVAL                    0x00002000
 #define CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT                     24
 #define CRL_APB_ADMA_REF_CTRL_CLKACT_MASK                      0x01000000U
@@ -1710,9 +1710,9 @@
 /*
 * 6 bit divider
 */
-#undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_DEFVAL 
-#undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT 
-#undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK 
+#undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_DEFVAL
+#undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT
+#undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK
 #define CRL_APB_ADMA_REF_CTRL_DIVISOR0_DEFVAL                  0x00002000
 #define CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT                   8
 #define CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK                    0x00003F00U
@@ -1722,9 +1722,9 @@
     * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
     *  usually an issue, but designers must be aware.)
 */
-#undef CRL_APB_ADMA_REF_CTRL_SRCSEL_DEFVAL 
-#undef CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT 
-#undef CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK 
+#undef CRL_APB_ADMA_REF_CTRL_SRCSEL_DEFVAL
+#undef CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT
+#undef CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK
 #define CRL_APB_ADMA_REF_CTRL_SRCSEL_DEFVAL                    0x00002000
 #define CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT                     0
 #define CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK                      0x00000007U
@@ -1732,9 +1732,9 @@
 /*
 * Clock active signal. Switch to 0 to disable the clock
 */
-#undef CRL_APB_PL0_REF_CTRL_CLKACT_DEFVAL 
-#undef CRL_APB_PL0_REF_CTRL_CLKACT_SHIFT 
-#undef CRL_APB_PL0_REF_CTRL_CLKACT_MASK 
+#undef CRL_APB_PL0_REF_CTRL_CLKACT_DEFVAL
+#undef CRL_APB_PL0_REF_CTRL_CLKACT_SHIFT
+#undef CRL_APB_PL0_REF_CTRL_CLKACT_MASK
 #define CRL_APB_PL0_REF_CTRL_CLKACT_DEFVAL                     0x00052000
 #define CRL_APB_PL0_REF_CTRL_CLKACT_SHIFT                      24
 #define CRL_APB_PL0_REF_CTRL_CLKACT_MASK                       0x01000000U
@@ -1742,9 +1742,9 @@
 /*
 * 6 bit divider
 */
-#undef CRL_APB_PL0_REF_CTRL_DIVISOR1_DEFVAL 
-#undef CRL_APB_PL0_REF_CTRL_DIVISOR1_SHIFT 
-#undef CRL_APB_PL0_REF_CTRL_DIVISOR1_MASK 
+#undef CRL_APB_PL0_REF_CTRL_DIVISOR1_DEFVAL
+#undef CRL_APB_PL0_REF_CTRL_DIVISOR1_SHIFT
+#undef CRL_APB_PL0_REF_CTRL_DIVISOR1_MASK
 #define CRL_APB_PL0_REF_CTRL_DIVISOR1_DEFVAL                   0x00052000
 #define CRL_APB_PL0_REF_CTRL_DIVISOR1_SHIFT                    16
 #define CRL_APB_PL0_REF_CTRL_DIVISOR1_MASK                     0x003F0000U
@@ -1752,9 +1752,9 @@
 /*
 * 6 bit divider
 */
-#undef CRL_APB_PL0_REF_CTRL_DIVISOR0_DEFVAL 
-#undef CRL_APB_PL0_REF_CTRL_DIVISOR0_SHIFT 
-#undef CRL_APB_PL0_REF_CTRL_DIVISOR0_MASK 
+#undef CRL_APB_PL0_REF_CTRL_DIVISOR0_DEFVAL
+#undef CRL_APB_PL0_REF_CTRL_DIVISOR0_SHIFT
+#undef CRL_APB_PL0_REF_CTRL_DIVISOR0_MASK
 #define CRL_APB_PL0_REF_CTRL_DIVISOR0_DEFVAL                   0x00052000
 #define CRL_APB_PL0_REF_CTRL_DIVISOR0_SHIFT                    8
 #define CRL_APB_PL0_REF_CTRL_DIVISOR0_MASK                     0x00003F00U
@@ -1764,9 +1764,9 @@
     * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
     *  usually an issue, but designers must be aware.)
 */
-#undef CRL_APB_PL0_REF_CTRL_SRCSEL_DEFVAL 
-#undef CRL_APB_PL0_REF_CTRL_SRCSEL_SHIFT 
-#undef CRL_APB_PL0_REF_CTRL_SRCSEL_MASK 
+#undef CRL_APB_PL0_REF_CTRL_SRCSEL_DEFVAL
+#undef CRL_APB_PL0_REF_CTRL_SRCSEL_SHIFT
+#undef CRL_APB_PL0_REF_CTRL_SRCSEL_MASK
 #define CRL_APB_PL0_REF_CTRL_SRCSEL_DEFVAL                     0x00052000
 #define CRL_APB_PL0_REF_CTRL_SRCSEL_SHIFT                      0
 #define CRL_APB_PL0_REF_CTRL_SRCSEL_MASK                       0x00000007U
@@ -1774,9 +1774,9 @@
 /*
 * Clock active signal. Switch to 0 to disable the clock
 */
-#undef CRL_APB_PL1_REF_CTRL_CLKACT_DEFVAL 
-#undef CRL_APB_PL1_REF_CTRL_CLKACT_SHIFT 
-#undef CRL_APB_PL1_REF_CTRL_CLKACT_MASK 
+#undef CRL_APB_PL1_REF_CTRL_CLKACT_DEFVAL
+#undef CRL_APB_PL1_REF_CTRL_CLKACT_SHIFT
+#undef CRL_APB_PL1_REF_CTRL_CLKACT_MASK
 #define CRL_APB_PL1_REF_CTRL_CLKACT_DEFVAL                     0x00052000
 #define CRL_APB_PL1_REF_CTRL_CLKACT_SHIFT                      24
 #define CRL_APB_PL1_REF_CTRL_CLKACT_MASK                       0x01000000U
@@ -1784,9 +1784,9 @@
 /*
 * 6 bit divider
 */
-#undef CRL_APB_PL1_REF_CTRL_DIVISOR1_DEFVAL 
-#undef CRL_APB_PL1_REF_CTRL_DIVISOR1_SHIFT 
-#undef CRL_APB_PL1_REF_CTRL_DIVISOR1_MASK 
+#undef CRL_APB_PL1_REF_CTRL_DIVISOR1_DEFVAL
+#undef CRL_APB_PL1_REF_CTRL_DIVISOR1_SHIFT
+#undef CRL_APB_PL1_REF_CTRL_DIVISOR1_MASK
 #define CRL_APB_PL1_REF_CTRL_DIVISOR1_DEFVAL                   0x00052000
 #define CRL_APB_PL1_REF_CTRL_DIVISOR1_SHIFT                    16
 #define CRL_APB_PL1_REF_CTRL_DIVISOR1_MASK                     0x003F0000U
@@ -1794,9 +1794,9 @@
 /*
 * 6 bit divider
 */
-#undef CRL_APB_PL1_REF_CTRL_DIVISOR0_DEFVAL 
-#undef CRL_APB_PL1_REF_CTRL_DIVISOR0_SHIFT 
-#undef CRL_APB_PL1_REF_CTRL_DIVISOR0_MASK 
+#undef CRL_APB_PL1_REF_CTRL_DIVISOR0_DEFVAL
+#undef CRL_APB_PL1_REF_CTRL_DIVISOR0_SHIFT
+#undef CRL_APB_PL1_REF_CTRL_DIVISOR0_MASK
 #define CRL_APB_PL1_REF_CTRL_DIVISOR0_DEFVAL                   0x00052000
 #define CRL_APB_PL1_REF_CTRL_DIVISOR0_SHIFT                    8
 #define CRL_APB_PL1_REF_CTRL_DIVISOR0_MASK                     0x00003F00U
@@ -1806,9 +1806,9 @@
     * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
     *  usually an issue, but designers must be aware.)
 */
-#undef CRL_APB_PL1_REF_CTRL_SRCSEL_DEFVAL 
-#undef CRL_APB_PL1_REF_CTRL_SRCSEL_SHIFT 
-#undef CRL_APB_PL1_REF_CTRL_SRCSEL_MASK 
+#undef CRL_APB_PL1_REF_CTRL_SRCSEL_DEFVAL
+#undef CRL_APB_PL1_REF_CTRL_SRCSEL_SHIFT
+#undef CRL_APB_PL1_REF_CTRL_SRCSEL_MASK
 #define CRL_APB_PL1_REF_CTRL_SRCSEL_DEFVAL                     0x00052000
 #define CRL_APB_PL1_REF_CTRL_SRCSEL_SHIFT                      0
 #define CRL_APB_PL1_REF_CTRL_SRCSEL_MASK                       0x00000007U
@@ -1816,9 +1816,9 @@
 /*
 * Clock active signal. Switch to 0 to disable the clock
 */
-#undef CRL_APB_PL2_REF_CTRL_CLKACT_DEFVAL 
-#undef CRL_APB_PL2_REF_CTRL_CLKACT_SHIFT 
-#undef CRL_APB_PL2_REF_CTRL_CLKACT_MASK 
+#undef CRL_APB_PL2_REF_CTRL_CLKACT_DEFVAL
+#undef CRL_APB_PL2_REF_CTRL_CLKACT_SHIFT
+#undef CRL_APB_PL2_REF_CTRL_CLKACT_MASK
 #define CRL_APB_PL2_REF_CTRL_CLKACT_DEFVAL                     0x00052000
 #define CRL_APB_PL2_REF_CTRL_CLKACT_SHIFT                      24
 #define CRL_APB_PL2_REF_CTRL_CLKACT_MASK                       0x01000000U
@@ -1826,9 +1826,9 @@
 /*
 * 6 bit divider
 */
-#undef CRL_APB_PL2_REF_CTRL_DIVISOR1_DEFVAL 
-#undef CRL_APB_PL2_REF_CTRL_DIVISOR1_SHIFT 
-#undef CRL_APB_PL2_REF_CTRL_DIVISOR1_MASK 
+#undef CRL_APB_PL2_REF_CTRL_DIVISOR1_DEFVAL
+#undef CRL_APB_PL2_REF_CTRL_DIVISOR1_SHIFT
+#undef CRL_APB_PL2_REF_CTRL_DIVISOR1_MASK
 #define CRL_APB_PL2_REF_CTRL_DIVISOR1_DEFVAL                   0x00052000
 #define CRL_APB_PL2_REF_CTRL_DIVISOR1_SHIFT                    16
 #define CRL_APB_PL2_REF_CTRL_DIVISOR1_MASK                     0x003F0000U
@@ -1836,9 +1836,9 @@
 /*
 * 6 bit divider
 */
-#undef CRL_APB_PL2_REF_CTRL_DIVISOR0_DEFVAL 
-#undef CRL_APB_PL2_REF_CTRL_DIVISOR0_SHIFT 
-#undef CRL_APB_PL2_REF_CTRL_DIVISOR0_MASK 
+#undef CRL_APB_PL2_REF_CTRL_DIVISOR0_DEFVAL
+#undef CRL_APB_PL2_REF_CTRL_DIVISOR0_SHIFT
+#undef CRL_APB_PL2_REF_CTRL_DIVISOR0_MASK
 #define CRL_APB_PL2_REF_CTRL_DIVISOR0_DEFVAL                   0x00052000
 #define CRL_APB_PL2_REF_CTRL_DIVISOR0_SHIFT                    8
 #define CRL_APB_PL2_REF_CTRL_DIVISOR0_MASK                     0x00003F00U
@@ -1848,9 +1848,9 @@
     * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
     *  usually an issue, but designers must be aware.)
 */
-#undef CRL_APB_PL2_REF_CTRL_SRCSEL_DEFVAL 
-#undef CRL_APB_PL2_REF_CTRL_SRCSEL_SHIFT 
-#undef CRL_APB_PL2_REF_CTRL_SRCSEL_MASK 
+#undef CRL_APB_PL2_REF_CTRL_SRCSEL_DEFVAL
+#undef CRL_APB_PL2_REF_CTRL_SRCSEL_SHIFT
+#undef CRL_APB_PL2_REF_CTRL_SRCSEL_MASK
 #define CRL_APB_PL2_REF_CTRL_SRCSEL_DEFVAL                     0x00052000
 #define CRL_APB_PL2_REF_CTRL_SRCSEL_SHIFT                      0
 #define CRL_APB_PL2_REF_CTRL_SRCSEL_MASK                       0x00000007U
@@ -1858,9 +1858,9 @@
 /*
 * Clock active signal. Switch to 0 to disable the clock
 */
-#undef CRL_APB_PL3_REF_CTRL_CLKACT_DEFVAL 
-#undef CRL_APB_PL3_REF_CTRL_CLKACT_SHIFT 
-#undef CRL_APB_PL3_REF_CTRL_CLKACT_MASK 
+#undef CRL_APB_PL3_REF_CTRL_CLKACT_DEFVAL
+#undef CRL_APB_PL3_REF_CTRL_CLKACT_SHIFT
+#undef CRL_APB_PL3_REF_CTRL_CLKACT_MASK
 #define CRL_APB_PL3_REF_CTRL_CLKACT_DEFVAL                     0x00052000
 #define CRL_APB_PL3_REF_CTRL_CLKACT_SHIFT                      24
 #define CRL_APB_PL3_REF_CTRL_CLKACT_MASK                       0x01000000U
@@ -1868,9 +1868,9 @@
 /*
 * 6 bit divider
 */
-#undef CRL_APB_PL3_REF_CTRL_DIVISOR1_DEFVAL 
-#undef CRL_APB_PL3_REF_CTRL_DIVISOR1_SHIFT 
-#undef CRL_APB_PL3_REF_CTRL_DIVISOR1_MASK 
+#undef CRL_APB_PL3_REF_CTRL_DIVISOR1_DEFVAL
+#undef CRL_APB_PL3_REF_CTRL_DIVISOR1_SHIFT
+#undef CRL_APB_PL3_REF_CTRL_DIVISOR1_MASK
 #define CRL_APB_PL3_REF_CTRL_DIVISOR1_DEFVAL                   0x00052000
 #define CRL_APB_PL3_REF_CTRL_DIVISOR1_SHIFT                    16
 #define CRL_APB_PL3_REF_CTRL_DIVISOR1_MASK                     0x003F0000U
@@ -1878,9 +1878,9 @@
 /*
 * 6 bit divider
 */
-#undef CRL_APB_PL3_REF_CTRL_DIVISOR0_DEFVAL 
-#undef CRL_APB_PL3_REF_CTRL_DIVISOR0_SHIFT 
-#undef CRL_APB_PL3_REF_CTRL_DIVISOR0_MASK 
+#undef CRL_APB_PL3_REF_CTRL_DIVISOR0_DEFVAL
+#undef CRL_APB_PL3_REF_CTRL_DIVISOR0_SHIFT
+#undef CRL_APB_PL3_REF_CTRL_DIVISOR0_MASK
 #define CRL_APB_PL3_REF_CTRL_DIVISOR0_DEFVAL                   0x00052000
 #define CRL_APB_PL3_REF_CTRL_DIVISOR0_SHIFT                    8
 #define CRL_APB_PL3_REF_CTRL_DIVISOR0_MASK                     0x00003F00U
@@ -1890,9 +1890,9 @@
     * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
     *  usually an issue, but designers must be aware.)
 */
-#undef CRL_APB_PL3_REF_CTRL_SRCSEL_DEFVAL 
-#undef CRL_APB_PL3_REF_CTRL_SRCSEL_SHIFT 
-#undef CRL_APB_PL3_REF_CTRL_SRCSEL_MASK 
+#undef CRL_APB_PL3_REF_CTRL_SRCSEL_DEFVAL
+#undef CRL_APB_PL3_REF_CTRL_SRCSEL_SHIFT
+#undef CRL_APB_PL3_REF_CTRL_SRCSEL_MASK
 #define CRL_APB_PL3_REF_CTRL_SRCSEL_DEFVAL                     0x00052000
 #define CRL_APB_PL3_REF_CTRL_SRCSEL_SHIFT                      0
 #define CRL_APB_PL3_REF_CTRL_SRCSEL_MASK                       0x00000007U
@@ -1900,9 +1900,9 @@
 /*
 * 6 bit divider
 */
-#undef CRL_APB_AMS_REF_CTRL_DIVISOR1_DEFVAL 
-#undef CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT 
-#undef CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK 
+#undef CRL_APB_AMS_REF_CTRL_DIVISOR1_DEFVAL
+#undef CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT
+#undef CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK
 #define CRL_APB_AMS_REF_CTRL_DIVISOR1_DEFVAL                   0x01001800
 #define CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT                    16
 #define CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK                     0x003F0000U
@@ -1910,9 +1910,9 @@
 /*
 * 6 bit divider
 */
-#undef CRL_APB_AMS_REF_CTRL_DIVISOR0_DEFVAL 
-#undef CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT 
-#undef CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK 
+#undef CRL_APB_AMS_REF_CTRL_DIVISOR0_DEFVAL
+#undef CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT
+#undef CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK
 #define CRL_APB_AMS_REF_CTRL_DIVISOR0_DEFVAL                   0x01001800
 #define CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT                    8
 #define CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK                     0x00003F00U
@@ -1922,9 +1922,9 @@
     * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
     *  usually an issue, but designers must be aware.)
 */
-#undef CRL_APB_AMS_REF_CTRL_SRCSEL_DEFVAL 
-#undef CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT 
-#undef CRL_APB_AMS_REF_CTRL_SRCSEL_MASK 
+#undef CRL_APB_AMS_REF_CTRL_SRCSEL_DEFVAL
+#undef CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT
+#undef CRL_APB_AMS_REF_CTRL_SRCSEL_MASK
 #define CRL_APB_AMS_REF_CTRL_SRCSEL_DEFVAL                     0x01001800
 #define CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT                      0
 #define CRL_APB_AMS_REF_CTRL_SRCSEL_MASK                       0x00000007U
@@ -1932,9 +1932,9 @@
 /*
 * Clock active signal. Switch to 0 to disable the clock
 */
-#undef CRL_APB_AMS_REF_CTRL_CLKACT_DEFVAL 
-#undef CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT 
-#undef CRL_APB_AMS_REF_CTRL_CLKACT_MASK 
+#undef CRL_APB_AMS_REF_CTRL_CLKACT_DEFVAL
+#undef CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT
+#undef CRL_APB_AMS_REF_CTRL_CLKACT_MASK
 #define CRL_APB_AMS_REF_CTRL_CLKACT_DEFVAL                     0x01001800
 #define CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT                      24
 #define CRL_APB_AMS_REF_CTRL_CLKACT_MASK                       0x01000000U
@@ -1944,9 +1944,9 @@
     *  of the old clock and 4 cycles of the new clock. This is not usually an
     * issue, but designers must be aware.)
 */
-#undef CRL_APB_DLL_REF_CTRL_SRCSEL_DEFVAL 
-#undef CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT 
-#undef CRL_APB_DLL_REF_CTRL_SRCSEL_MASK 
+#undef CRL_APB_DLL_REF_CTRL_SRCSEL_DEFVAL
+#undef CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT
+#undef CRL_APB_DLL_REF_CTRL_SRCSEL_MASK
 #define CRL_APB_DLL_REF_CTRL_SRCSEL_DEFVAL                     0x00000000
 #define CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT                      0
 #define CRL_APB_DLL_REF_CTRL_SRCSEL_MASK                       0x00000007U
@@ -1954,9 +1954,9 @@
 /*
 * 6 bit divider
 */
-#undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_DEFVAL 
-#undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT 
-#undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK 
+#undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_DEFVAL
+#undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT
+#undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK
 #define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_DEFVAL             0x00001800
 #define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT              8
 #define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK               0x00003F00U
@@ -1966,9 +1966,9 @@
     *  only be toggled after 4 cycles of the old clock and 4 cycles of the new
     *  clock. This is not usually an issue, but designers must be aware.)
 */
-#undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_DEFVAL 
-#undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT 
-#undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK 
+#undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_DEFVAL
+#undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT
+#undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK
 #define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_DEFVAL               0x00001800
 #define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT                0
 #define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK                 0x00000007U
@@ -1976,9 +1976,9 @@
 /*
 * Clock active signal. Switch to 0 to disable the clock
 */
-#undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_DEFVAL 
-#undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT 
-#undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK 
+#undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_DEFVAL
+#undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT
+#undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK
 #define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_DEFVAL               0x00001800
 #define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT                24
 #define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK                 0x01000000U
@@ -1988,9 +1988,9 @@
     * gled after 4 cycles of the old clock and 4 cycles of the new clock. This
     *  is not usually an issue, but designers must be aware.)
 */
-#undef CRF_APB_SATA_REF_CTRL_SRCSEL_DEFVAL 
-#undef CRF_APB_SATA_REF_CTRL_SRCSEL_SHIFT 
-#undef CRF_APB_SATA_REF_CTRL_SRCSEL_MASK 
+#undef CRF_APB_SATA_REF_CTRL_SRCSEL_DEFVAL
+#undef CRF_APB_SATA_REF_CTRL_SRCSEL_SHIFT
+#undef CRF_APB_SATA_REF_CTRL_SRCSEL_MASK
 #define CRF_APB_SATA_REF_CTRL_SRCSEL_DEFVAL                    0x01001600
 #define CRF_APB_SATA_REF_CTRL_SRCSEL_SHIFT                     0
 #define CRF_APB_SATA_REF_CTRL_SRCSEL_MASK                      0x00000007U
@@ -1998,9 +1998,9 @@
 /*
 * Clock active signal. Switch to 0 to disable the clock
 */
-#undef CRF_APB_SATA_REF_CTRL_CLKACT_DEFVAL 
-#undef CRF_APB_SATA_REF_CTRL_CLKACT_SHIFT 
-#undef CRF_APB_SATA_REF_CTRL_CLKACT_MASK 
+#undef CRF_APB_SATA_REF_CTRL_CLKACT_DEFVAL
+#undef CRF_APB_SATA_REF_CTRL_CLKACT_SHIFT
+#undef CRF_APB_SATA_REF_CTRL_CLKACT_MASK
 #define CRF_APB_SATA_REF_CTRL_CLKACT_DEFVAL                    0x01001600
 #define CRF_APB_SATA_REF_CTRL_CLKACT_SHIFT                     24
 #define CRF_APB_SATA_REF_CTRL_CLKACT_MASK                      0x01000000U
@@ -2008,9 +2008,9 @@
 /*
 * 6 bit divider
 */
-#undef CRF_APB_SATA_REF_CTRL_DIVISOR0_DEFVAL 
-#undef CRF_APB_SATA_REF_CTRL_DIVISOR0_SHIFT 
-#undef CRF_APB_SATA_REF_CTRL_DIVISOR0_MASK 
+#undef CRF_APB_SATA_REF_CTRL_DIVISOR0_DEFVAL
+#undef CRF_APB_SATA_REF_CTRL_DIVISOR0_SHIFT
+#undef CRF_APB_SATA_REF_CTRL_DIVISOR0_MASK
 #define CRF_APB_SATA_REF_CTRL_DIVISOR0_DEFVAL                  0x01001600
 #define CRF_APB_SATA_REF_CTRL_DIVISOR0_SHIFT                   8
 #define CRF_APB_SATA_REF_CTRL_DIVISOR0_MASK                    0x00003F00U
@@ -2018,9 +2018,9 @@
 /*
 * 6 bit divider
 */
-#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_DEFVAL 
-#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT 
-#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK 
+#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_DEFVAL
+#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT
+#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK
 #define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_DEFVAL              0x01002300
 #define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT               16
 #define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK                0x003F0000U
@@ -2028,9 +2028,9 @@
 /*
 * 6 bit divider
 */
-#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_DEFVAL 
-#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT 
-#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK 
+#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_DEFVAL
+#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT
+#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK
 #define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_DEFVAL              0x01002300
 #define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT               8
 #define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK                0x00003F00U
@@ -2041,9 +2041,9 @@
     * les of the new clock. This is not usually an issue, but designers must b
     * e aware.)
 */
-#undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_DEFVAL 
-#undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT 
-#undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK 
+#undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_DEFVAL
+#undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT
+#undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK
 #define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_DEFVAL                0x01002300
 #define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT                 0
 #define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK                  0x00000007U
@@ -2051,9 +2051,9 @@
 /*
 * Clock active signal. Switch to 0 to disable the clock
 */
-#undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_DEFVAL 
-#undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT 
-#undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK 
+#undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_DEFVAL
+#undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT
+#undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK
 #define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_DEFVAL                0x01002300
 #define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT                 24
 #define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK                  0x01000000U
@@ -2061,9 +2061,9 @@
 /*
 * 6 bit divider
 */
-#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_DEFVAL 
-#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT 
-#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK 
+#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_DEFVAL
+#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT
+#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK
 #define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_DEFVAL              0x01032300
 #define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT               16
 #define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK                0x003F0000U
@@ -2071,9 +2071,9 @@
 /*
 * 6 bit divider
 */
-#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_DEFVAL 
-#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT 
-#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK 
+#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_DEFVAL
+#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT
+#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK
 #define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_DEFVAL              0x01032300
 #define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT               8
 #define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK                0x00003F00U
@@ -2084,9 +2084,9 @@
     * les of the new clock. This is not usually an issue, but designers must b
     * e aware.)
 */
-#undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_DEFVAL 
-#undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT 
-#undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK 
+#undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_DEFVAL
+#undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT
+#undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK
 #define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_DEFVAL                0x01032300
 #define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT                 0
 #define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK                  0x00000007U
@@ -2094,9 +2094,9 @@
 /*
 * Clock active signal. Switch to 0 to disable the clock
 */
-#undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_DEFVAL 
-#undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT 
-#undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK 
+#undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_DEFVAL
+#undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT
+#undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK
 #define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_DEFVAL                0x01032300
 #define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT                 24
 #define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK                  0x01000000U
@@ -2104,9 +2104,9 @@
 /*
 * 6 bit divider
 */
-#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_DEFVAL 
-#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT 
-#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK 
+#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_DEFVAL
+#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT
+#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK
 #define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_DEFVAL                0x01203200
 #define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT                 16
 #define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK                  0x003F0000U
@@ -2114,9 +2114,9 @@
 /*
 * 6 bit divider
 */
-#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_DEFVAL 
-#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT 
-#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK 
+#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_DEFVAL
+#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT
+#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK
 #define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_DEFVAL                0x01203200
 #define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT                 8
 #define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK                  0x00003F00U
@@ -2126,9 +2126,9 @@
     * led after 4 cycles of the old clock and 4 cycles of the new clock. This
     * is not usually an issue, but designers must be aware.)
 */
-#undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_DEFVAL 
-#undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT 
-#undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK 
+#undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_DEFVAL
+#undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT
+#undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK
 #define CRF_APB_DP_STC_REF_CTRL_SRCSEL_DEFVAL                  0x01203200
 #define CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT                   0
 #define CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK                    0x00000007U
@@ -2136,9 +2136,9 @@
 /*
 * Clock active signal. Switch to 0 to disable the clock
 */
-#undef CRF_APB_DP_STC_REF_CTRL_CLKACT_DEFVAL 
-#undef CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT 
-#undef CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK 
+#undef CRF_APB_DP_STC_REF_CTRL_CLKACT_DEFVAL
+#undef CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT
+#undef CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK
 #define CRF_APB_DP_STC_REF_CTRL_CLKACT_DEFVAL                  0x01203200
 #define CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT                   24
 #define CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK                    0x01000000U
@@ -2146,9 +2146,9 @@
 /*
 * 6 bit divider
 */
-#undef CRF_APB_ACPU_CTRL_DIVISOR0_DEFVAL 
-#undef CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT 
-#undef CRF_APB_ACPU_CTRL_DIVISOR0_MASK 
+#undef CRF_APB_ACPU_CTRL_DIVISOR0_DEFVAL
+#undef CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT
+#undef CRF_APB_ACPU_CTRL_DIVISOR0_MASK
 #define CRF_APB_ACPU_CTRL_DIVISOR0_DEFVAL                      0x03000400
 #define CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT                       8
 #define CRF_APB_ACPU_CTRL_DIVISOR0_MASK                        0x00003F00U
@@ -2158,9 +2158,9 @@
     * er 4 cycles of the old clock and 4 cycles of the new clock. This is not
     * usually an issue, but designers must be aware.)
 */
-#undef CRF_APB_ACPU_CTRL_SRCSEL_DEFVAL 
-#undef CRF_APB_ACPU_CTRL_SRCSEL_SHIFT 
-#undef CRF_APB_ACPU_CTRL_SRCSEL_MASK 
+#undef CRF_APB_ACPU_CTRL_SRCSEL_DEFVAL
+#undef CRF_APB_ACPU_CTRL_SRCSEL_SHIFT
+#undef CRF_APB_ACPU_CTRL_SRCSEL_MASK
 #define CRF_APB_ACPU_CTRL_SRCSEL_DEFVAL                        0x03000400
 #define CRF_APB_ACPU_CTRL_SRCSEL_SHIFT                         0
 #define CRF_APB_ACPU_CTRL_SRCSEL_MASK                          0x00000007U
@@ -2169,9 +2169,9 @@
 * Clock active signal. Switch to 0 to disable the clock. For the half spee
     * d APU Clock
 */
-#undef CRF_APB_ACPU_CTRL_CLKACT_HALF_DEFVAL 
-#undef CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT 
-#undef CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK 
+#undef CRF_APB_ACPU_CTRL_CLKACT_HALF_DEFVAL
+#undef CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT
+#undef CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK
 #define CRF_APB_ACPU_CTRL_CLKACT_HALF_DEFVAL                   0x03000400
 #define CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT                    25
 #define CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK                     0x02000000U
@@ -2180,9 +2180,9 @@
 * Clock active signal. Switch to 0 to disable the clock. For the full spee
     * d ACPUX Clock. This will shut off the high speed clock to the entire APU
 */
-#undef CRF_APB_ACPU_CTRL_CLKACT_FULL_DEFVAL 
-#undef CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT 
-#undef CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK 
+#undef CRF_APB_ACPU_CTRL_CLKACT_FULL_DEFVAL
+#undef CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT
+#undef CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK
 #define CRF_APB_ACPU_CTRL_CLKACT_FULL_DEFVAL                   0x03000400
 #define CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT                    24
 #define CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK                     0x01000000U
@@ -2190,9 +2190,9 @@
 /*
 * 6 bit divider
 */
-#undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_DEFVAL 
-#undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT 
-#undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK 
+#undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_DEFVAL
+#undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT
+#undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK
 #define CRF_APB_DBG_FPD_CTRL_DIVISOR0_DEFVAL                   0x01002500
 #define CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT                    8
 #define CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK                     0x00003F00U
@@ -2202,9 +2202,9 @@
     * gled after 4 cycles of the old clock and 4 cycles of the new clock. This
     *  is not usually an issue, but designers must be aware.)
 */
-#undef CRF_APB_DBG_FPD_CTRL_SRCSEL_DEFVAL 
-#undef CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT 
-#undef CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK 
+#undef CRF_APB_DBG_FPD_CTRL_SRCSEL_DEFVAL
+#undef CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT
+#undef CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK
 #define CRF_APB_DBG_FPD_CTRL_SRCSEL_DEFVAL                     0x01002500
 #define CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT                      0
 #define CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK                       0x00000007U
@@ -2212,9 +2212,9 @@
 /*
 * Clock active signal. Switch to 0 to disable the clock
 */
-#undef CRF_APB_DBG_FPD_CTRL_CLKACT_DEFVAL 
-#undef CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT 
-#undef CRF_APB_DBG_FPD_CTRL_CLKACT_MASK 
+#undef CRF_APB_DBG_FPD_CTRL_CLKACT_DEFVAL
+#undef CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT
+#undef CRF_APB_DBG_FPD_CTRL_CLKACT_MASK
 #define CRF_APB_DBG_FPD_CTRL_CLKACT_DEFVAL                     0x01002500
 #define CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT                      24
 #define CRF_APB_DBG_FPD_CTRL_CLKACT_MASK                       0x01000000U
@@ -2222,9 +2222,9 @@
 /*
 * 6 bit divider
 */
-#undef CRF_APB_DDR_CTRL_DIVISOR0_DEFVAL 
-#undef CRF_APB_DDR_CTRL_DIVISOR0_SHIFT 
-#undef CRF_APB_DDR_CTRL_DIVISOR0_MASK 
+#undef CRF_APB_DDR_CTRL_DIVISOR0_DEFVAL
+#undef CRF_APB_DDR_CTRL_DIVISOR0_SHIFT
+#undef CRF_APB_DDR_CTRL_DIVISOR0_MASK
 #define CRF_APB_DDR_CTRL_DIVISOR0_DEFVAL                       0x01000500
 #define CRF_APB_DDR_CTRL_DIVISOR0_SHIFT                        8
 #define CRF_APB_DDR_CTRL_DIVISOR0_MASK                         0x00003F00U
@@ -2234,9 +2234,9 @@
     * of the old clock and 4 cycles of the new clock. This is not usually an i
     * ssue, but designers must be aware.)
 */
-#undef CRF_APB_DDR_CTRL_SRCSEL_DEFVAL 
-#undef CRF_APB_DDR_CTRL_SRCSEL_SHIFT 
-#undef CRF_APB_DDR_CTRL_SRCSEL_MASK 
+#undef CRF_APB_DDR_CTRL_SRCSEL_DEFVAL
+#undef CRF_APB_DDR_CTRL_SRCSEL_SHIFT
+#undef CRF_APB_DDR_CTRL_SRCSEL_MASK
 #define CRF_APB_DDR_CTRL_SRCSEL_DEFVAL                         0x01000500
 #define CRF_APB_DDR_CTRL_SRCSEL_SHIFT                          0
 #define CRF_APB_DDR_CTRL_SRCSEL_MASK                           0x00000007U
@@ -2244,9 +2244,9 @@
 /*
 * 6 bit divider
 */
-#undef CRF_APB_GPU_REF_CTRL_DIVISOR0_DEFVAL 
-#undef CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT 
-#undef CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK 
+#undef CRF_APB_GPU_REF_CTRL_DIVISOR0_DEFVAL
+#undef CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT
+#undef CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK
 #define CRF_APB_GPU_REF_CTRL_DIVISOR0_DEFVAL                   0x00001500
 #define CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT                    8
 #define CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK                     0x00003F00U
@@ -2256,9 +2256,9 @@
     * gled after 4 cycles of the old clock and 4 cycles of the new clock. This
     *  is not usually an issue, but designers must be aware.)
 */
-#undef CRF_APB_GPU_REF_CTRL_SRCSEL_DEFVAL 
-#undef CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT 
-#undef CRF_APB_GPU_REF_CTRL_SRCSEL_MASK 
+#undef CRF_APB_GPU_REF_CTRL_SRCSEL_DEFVAL
+#undef CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT
+#undef CRF_APB_GPU_REF_CTRL_SRCSEL_MASK
 #define CRF_APB_GPU_REF_CTRL_SRCSEL_DEFVAL                     0x00001500
 #define CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT                      0
 #define CRF_APB_GPU_REF_CTRL_SRCSEL_MASK                       0x00000007U
@@ -2267,9 +2267,9 @@
 * Clock active signal. Switch to 0 to disable the clock, which will stop c
     * lock for GPU (and both Pixel Processors).
 */
-#undef CRF_APB_GPU_REF_CTRL_CLKACT_DEFVAL 
-#undef CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT 
-#undef CRF_APB_GPU_REF_CTRL_CLKACT_MASK 
+#undef CRF_APB_GPU_REF_CTRL_CLKACT_DEFVAL
+#undef CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT
+#undef CRF_APB_GPU_REF_CTRL_CLKACT_MASK
 #define CRF_APB_GPU_REF_CTRL_CLKACT_DEFVAL                     0x00001500
 #define CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT                      24
 #define CRF_APB_GPU_REF_CTRL_CLKACT_MASK                       0x01000000U
@@ -2278,9 +2278,9 @@
 * Clock active signal for Pixel Processor. Switch to 0 to disable the cloc
     * k only to this Pixel Processor
 */
-#undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_DEFVAL 
-#undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT 
-#undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK 
+#undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_DEFVAL
+#undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT
+#undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK
 #define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_DEFVAL                 0x00001500
 #define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT                  25
 #define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK                   0x02000000U
@@ -2289,9 +2289,9 @@
 * Clock active signal for Pixel Processor. Switch to 0 to disable the cloc
     * k only to this Pixel Processor
 */
-#undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_DEFVAL 
-#undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT 
-#undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK 
+#undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_DEFVAL
+#undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT
+#undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK
 #define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_DEFVAL                 0x00001500
 #define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT                  26
 #define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK                   0x04000000U
@@ -2299,9 +2299,9 @@
 /*
 * 6 bit divider
 */
-#undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_DEFVAL 
-#undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT 
-#undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK 
+#undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_DEFVAL
+#undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT
+#undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK
 #define CRF_APB_GDMA_REF_CTRL_DIVISOR0_DEFVAL                  0x01000500
 #define CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT                   8
 #define CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK                    0x00003F00U
@@ -2311,9 +2311,9 @@
     * er 4 cycles of the old clock and 4 cycles of the new clock. This is not
     * usually an issue, but designers must be aware.)
 */
-#undef CRF_APB_GDMA_REF_CTRL_SRCSEL_DEFVAL 
-#undef CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT 
-#undef CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK 
+#undef CRF_APB_GDMA_REF_CTRL_SRCSEL_DEFVAL
+#undef CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT
+#undef CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK
 #define CRF_APB_GDMA_REF_CTRL_SRCSEL_DEFVAL                    0x01000500
 #define CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT                     0
 #define CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK                      0x00000007U
@@ -2321,9 +2321,9 @@
 /*
 * Clock active signal. Switch to 0 to disable the clock
 */
-#undef CRF_APB_GDMA_REF_CTRL_CLKACT_DEFVAL 
-#undef CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT 
-#undef CRF_APB_GDMA_REF_CTRL_CLKACT_MASK 
+#undef CRF_APB_GDMA_REF_CTRL_CLKACT_DEFVAL
+#undef CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT
+#undef CRF_APB_GDMA_REF_CTRL_CLKACT_MASK
 #define CRF_APB_GDMA_REF_CTRL_CLKACT_DEFVAL                    0x01000500
 #define CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT                     24
 #define CRF_APB_GDMA_REF_CTRL_CLKACT_MASK                      0x01000000U
@@ -2331,9 +2331,9 @@
 /*
 * 6 bit divider
 */
-#undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_DEFVAL 
-#undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT 
-#undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK 
+#undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_DEFVAL
+#undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT
+#undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK
 #define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_DEFVAL                 0x01000500
 #define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT                  8
 #define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK                   0x00003F00U
@@ -2343,9 +2343,9 @@
     * er 4 cycles of the old clock and 4 cycles of the new clock. This is not
     * usually an issue, but designers must be aware.)
 */
-#undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_DEFVAL 
-#undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT 
-#undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK 
+#undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_DEFVAL
+#undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT
+#undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK
 #define CRF_APB_DPDMA_REF_CTRL_SRCSEL_DEFVAL                   0x01000500
 #define CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT                    0
 #define CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK                     0x00000007U
@@ -2353,9 +2353,9 @@
 /*
 * Clock active signal. Switch to 0 to disable the clock
 */
-#undef CRF_APB_DPDMA_REF_CTRL_CLKACT_DEFVAL 
-#undef CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT 
-#undef CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK 
+#undef CRF_APB_DPDMA_REF_CTRL_CLKACT_DEFVAL
+#undef CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT
+#undef CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK
 #define CRF_APB_DPDMA_REF_CTRL_CLKACT_DEFVAL                   0x01000500
 #define CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT                    24
 #define CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK                     0x01000000U
@@ -2363,9 +2363,9 @@
 /*
 * 6 bit divider
 */
-#undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_DEFVAL 
-#undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT 
-#undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK 
+#undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_DEFVAL
+#undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT
+#undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK
 #define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_DEFVAL                0x01000400
 #define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT                 8
 #define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK                  0x00003F00U
@@ -2375,9 +2375,9 @@
     * er 4 cycles of the old clock and 4 cycles of the new clock. This is not
     * usually an issue, but designers must be aware.)
 */
-#undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_DEFVAL 
-#undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT 
-#undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK 
+#undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_DEFVAL
+#undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT
+#undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK
 #define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_DEFVAL                  0x01000400
 #define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT                   0
 #define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK                    0x00000007U
@@ -2385,9 +2385,9 @@
 /*
 * Clock active signal. Switch to 0 to disable the clock
 */
-#undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_DEFVAL 
-#undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT 
-#undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK 
+#undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_DEFVAL
+#undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT
+#undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK
 #define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_DEFVAL                  0x01000400
 #define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT                   24
 #define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK                    0x01000000U
@@ -2395,9 +2395,9 @@
 /*
 * 6 bit divider
 */
-#undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_DEFVAL 
-#undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT 
-#undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK 
+#undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_DEFVAL
+#undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT
+#undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK
 #define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_DEFVAL               0x01000800
 #define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT                8
 #define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK                 0x00003F00U
@@ -2407,9 +2407,9 @@
     * gled after 4 cycles of the old clock and 4 cycles of the new clock. This
     *  is not usually an issue, but designers must be aware.)
 */
-#undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_DEFVAL 
-#undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT 
-#undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK 
+#undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_DEFVAL
+#undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT
+#undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK
 #define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_DEFVAL                 0x01000800
 #define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT                  0
 #define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK                   0x00000007U
@@ -2417,9 +2417,9 @@
 /*
 * Clock active signal. Switch to 0 to disable the clock
 */
-#undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_DEFVAL 
-#undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT 
-#undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK 
+#undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_DEFVAL
+#undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT
+#undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK
 #define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_DEFVAL                 0x01000800
 #define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT                  24
 #define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK                   0x01000000U
@@ -2427,9 +2427,9 @@
 /*
 * 6 bit divider
 */
-#undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_DEFVAL 
-#undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT 
-#undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK 
+#undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_DEFVAL
+#undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT
+#undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK
 #define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_DEFVAL                 0x00000A00
 #define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT                  8
 #define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK                   0x00003F00U
@@ -2439,9 +2439,9 @@
     * gled after 4 cycles of the old clock and 4 cycles of the new clock. This
     *  is not usually an issue, but designers must be aware.)
 */
-#undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_DEFVAL 
-#undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT 
-#undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK 
+#undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_DEFVAL
+#undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT
+#undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK
 #define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_DEFVAL                   0x00000A00
 #define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT                    0
 #define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK                     0x00000007U
@@ -2451,9 +2451,9 @@
     * lect the PLL ref clock for the APB interface of TTC0'10" = Select the R5
     *  clock for the APB interface of TTC0
 */
-#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_DEFVAL 
-#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_SHIFT 
-#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_MASK 
+#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_DEFVAL
+#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_SHIFT
+#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_MASK
 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_DEFVAL               0x00000000
 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_SHIFT                0
 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_MASK                 0x00000003U
@@ -2463,9 +2463,9 @@
     * lect the PLL ref clock for the APB interface of TTC1'10" = Select the R5
     *  clock for the APB interface of TTC1
 */
-#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_DEFVAL 
-#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_SHIFT 
-#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_MASK 
+#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_DEFVAL
+#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_SHIFT
+#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_MASK
 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_DEFVAL               0x00000000
 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_SHIFT                2
 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_MASK                 0x0000000CU
@@ -2475,9 +2475,9 @@
     * lect the PLL ref clock for the APB interface of TTC2'10" = Select the R5
     *  clock for the APB interface of TTC2
 */
-#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_DEFVAL 
-#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_SHIFT 
-#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_MASK 
+#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_DEFVAL
+#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_SHIFT
+#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_MASK
 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_DEFVAL               0x00000000
 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_SHIFT                4
 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_MASK                 0x00000030U
@@ -2487,9 +2487,9 @@
     * lect the PLL ref clock for the APB interface of TTC3'10" = Select the R5
     *  clock for the APB interface of TTC3
 */
-#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_DEFVAL 
-#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_SHIFT 
-#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_MASK 
+#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_DEFVAL
+#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_SHIFT
+#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_MASK
 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_DEFVAL               0x00000000
 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_SHIFT                6
 #define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_MASK                 0x000000C0U
@@ -2498,9 +2498,9 @@
 * System watchdog timer clock source selection: 0: Internal APB clock 1: E
     * xternal (PL clock via EMIO or Pinout clock via MIO)
 */
-#undef FPD_SLCR_WDT_CLK_SEL_SELECT_DEFVAL 
-#undef FPD_SLCR_WDT_CLK_SEL_SELECT_SHIFT 
-#undef FPD_SLCR_WDT_CLK_SEL_SELECT_MASK 
+#undef FPD_SLCR_WDT_CLK_SEL_SELECT_DEFVAL
+#undef FPD_SLCR_WDT_CLK_SEL_SELECT_SHIFT
+#undef FPD_SLCR_WDT_CLK_SEL_SELECT_MASK
 #define FPD_SLCR_WDT_CLK_SEL_SELECT_DEFVAL                     0x00000000
 #define FPD_SLCR_WDT_CLK_SEL_SELECT_SHIFT                      0
 #define FPD_SLCR_WDT_CLK_SEL_SELECT_MASK                       0x00000001U
@@ -2509,9 +2509,9 @@
 * System watchdog timer clock source selection: 0: internal clock APB cloc
     * k 1: external clock from PL via EMIO, or from pinout via MIO
 */
-#undef IOU_SLCR_WDT_CLK_SEL_SELECT_DEFVAL 
-#undef IOU_SLCR_WDT_CLK_SEL_SELECT_SHIFT 
-#undef IOU_SLCR_WDT_CLK_SEL_SELECT_MASK 
+#undef IOU_SLCR_WDT_CLK_SEL_SELECT_DEFVAL
+#undef IOU_SLCR_WDT_CLK_SEL_SELECT_SHIFT
+#undef IOU_SLCR_WDT_CLK_SEL_SELECT_MASK
 #define IOU_SLCR_WDT_CLK_SEL_SELECT_DEFVAL                     0x00000000
 #define IOU_SLCR_WDT_CLK_SEL_SELECT_SHIFT                      0
 #define IOU_SLCR_WDT_CLK_SEL_SELECT_MASK                       0x00000001U
@@ -2520,507 +2520,507 @@
 * System watchdog timer clock source selection: 0: internal clock APB cloc
     * k 1: external clock pss_ref_clk
 */
-#undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_DEFVAL 
-#undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_SHIFT 
-#undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_MASK 
+#undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_DEFVAL
+#undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_SHIFT
+#undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_MASK
 #define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_DEFVAL              0x00000000
 #define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_SHIFT               0
 #define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_MASK                0x00000001U
-#undef CRF_APB_RST_DDR_SS_OFFSET 
+#undef CRF_APB_RST_DDR_SS_OFFSET
 #define CRF_APB_RST_DDR_SS_OFFSET                                                  0XFD1A0108
-#undef DDRC_MSTR_OFFSET 
+#undef DDRC_MSTR_OFFSET
 #define DDRC_MSTR_OFFSET                                                           0XFD070000
-#undef DDRC_MRCTRL0_OFFSET 
+#undef DDRC_MRCTRL0_OFFSET
 #define DDRC_MRCTRL0_OFFSET                                                        0XFD070010
-#undef DDRC_DERATEEN_OFFSET 
+#undef DDRC_DERATEEN_OFFSET
 #define DDRC_DERATEEN_OFFSET                                                       0XFD070020
-#undef DDRC_DERATEINT_OFFSET 
+#undef DDRC_DERATEINT_OFFSET
 #define DDRC_DERATEINT_OFFSET                                                      0XFD070024
-#undef DDRC_PWRCTL_OFFSET 
+#undef DDRC_PWRCTL_OFFSET
 #define DDRC_PWRCTL_OFFSET                                                         0XFD070030
-#undef DDRC_PWRTMG_OFFSET 
+#undef DDRC_PWRTMG_OFFSET
 #define DDRC_PWRTMG_OFFSET                                                         0XFD070034
-#undef DDRC_RFSHCTL0_OFFSET 
+#undef DDRC_RFSHCTL0_OFFSET
 #define DDRC_RFSHCTL0_OFFSET                                                       0XFD070050
-#undef DDRC_RFSHCTL1_OFFSET 
+#undef DDRC_RFSHCTL1_OFFSET
 #define DDRC_RFSHCTL1_OFFSET                                                       0XFD070054
-#undef DDRC_RFSHCTL3_OFFSET 
+#undef DDRC_RFSHCTL3_OFFSET
 #define DDRC_RFSHCTL3_OFFSET                                                       0XFD070060
-#undef DDRC_RFSHTMG_OFFSET 
+#undef DDRC_RFSHTMG_OFFSET
 #define DDRC_RFSHTMG_OFFSET                                                        0XFD070064
-#undef DDRC_ECCCFG0_OFFSET 
+#undef DDRC_ECCCFG0_OFFSET
 #define DDRC_ECCCFG0_OFFSET                                                        0XFD070070
-#undef DDRC_ECCCFG1_OFFSET 
+#undef DDRC_ECCCFG1_OFFSET
 #define DDRC_ECCCFG1_OFFSET                                                        0XFD070074
-#undef DDRC_CRCPARCTL1_OFFSET 
+#undef DDRC_CRCPARCTL1_OFFSET
 #define DDRC_CRCPARCTL1_OFFSET                                                     0XFD0700C4
-#undef DDRC_CRCPARCTL2_OFFSET 
+#undef DDRC_CRCPARCTL2_OFFSET
 #define DDRC_CRCPARCTL2_OFFSET                                                     0XFD0700C8
-#undef DDRC_INIT0_OFFSET 
+#undef DDRC_INIT0_OFFSET
 #define DDRC_INIT0_OFFSET                                                          0XFD0700D0
-#undef DDRC_INIT1_OFFSET 
+#undef DDRC_INIT1_OFFSET
 #define DDRC_INIT1_OFFSET                                                          0XFD0700D4
-#undef DDRC_INIT2_OFFSET 
+#undef DDRC_INIT2_OFFSET
 #define DDRC_INIT2_OFFSET                                                          0XFD0700D8
-#undef DDRC_INIT3_OFFSET 
+#undef DDRC_INIT3_OFFSET
 #define DDRC_INIT3_OFFSET                                                          0XFD0700DC
-#undef DDRC_INIT4_OFFSET 
+#undef DDRC_INIT4_OFFSET
 #define DDRC_INIT4_OFFSET                                                          0XFD0700E0
-#undef DDRC_INIT5_OFFSET 
+#undef DDRC_INIT5_OFFSET
 #define DDRC_INIT5_OFFSET                                                          0XFD0700E4
-#undef DDRC_INIT6_OFFSET 
+#undef DDRC_INIT6_OFFSET
 #define DDRC_INIT6_OFFSET                                                          0XFD0700E8
-#undef DDRC_INIT7_OFFSET 
+#undef DDRC_INIT7_OFFSET
 #define DDRC_INIT7_OFFSET                                                          0XFD0700EC
-#undef DDRC_DIMMCTL_OFFSET 
+#undef DDRC_DIMMCTL_OFFSET
 #define DDRC_DIMMCTL_OFFSET                                                        0XFD0700F0
-#undef DDRC_RANKCTL_OFFSET 
+#undef DDRC_RANKCTL_OFFSET
 #define DDRC_RANKCTL_OFFSET                                                        0XFD0700F4
-#undef DDRC_DRAMTMG0_OFFSET 
+#undef DDRC_DRAMTMG0_OFFSET
 #define DDRC_DRAMTMG0_OFFSET                                                       0XFD070100
-#undef DDRC_DRAMTMG1_OFFSET 
+#undef DDRC_DRAMTMG1_OFFSET
 #define DDRC_DRAMTMG1_OFFSET                                                       0XFD070104
-#undef DDRC_DRAMTMG2_OFFSET 
+#undef DDRC_DRAMTMG2_OFFSET
 #define DDRC_DRAMTMG2_OFFSET                                                       0XFD070108
-#undef DDRC_DRAMTMG3_OFFSET 
+#undef DDRC_DRAMTMG3_OFFSET
 #define DDRC_DRAMTMG3_OFFSET                                                       0XFD07010C
-#undef DDRC_DRAMTMG4_OFFSET 
+#undef DDRC_DRAMTMG4_OFFSET
 #define DDRC_DRAMTMG4_OFFSET                                                       0XFD070110
-#undef DDRC_DRAMTMG5_OFFSET 
+#undef DDRC_DRAMTMG5_OFFSET
 #define DDRC_DRAMTMG5_OFFSET                                                       0XFD070114
-#undef DDRC_DRAMTMG6_OFFSET 
+#undef DDRC_DRAMTMG6_OFFSET
 #define DDRC_DRAMTMG6_OFFSET                                                       0XFD070118
-#undef DDRC_DRAMTMG7_OFFSET 
+#undef DDRC_DRAMTMG7_OFFSET
 #define DDRC_DRAMTMG7_OFFSET                                                       0XFD07011C
-#undef DDRC_DRAMTMG8_OFFSET 
+#undef DDRC_DRAMTMG8_OFFSET
 #define DDRC_DRAMTMG8_OFFSET                                                       0XFD070120
-#undef DDRC_DRAMTMG9_OFFSET 
+#undef DDRC_DRAMTMG9_OFFSET
 #define DDRC_DRAMTMG9_OFFSET                                                       0XFD070124
-#undef DDRC_DRAMTMG11_OFFSET 
+#undef DDRC_DRAMTMG11_OFFSET
 #define DDRC_DRAMTMG11_OFFSET                                                      0XFD07012C
-#undef DDRC_DRAMTMG12_OFFSET 
+#undef DDRC_DRAMTMG12_OFFSET
 #define DDRC_DRAMTMG12_OFFSET                                                      0XFD070130
-#undef DDRC_ZQCTL0_OFFSET 
+#undef DDRC_ZQCTL0_OFFSET
 #define DDRC_ZQCTL0_OFFSET                                                         0XFD070180
-#undef DDRC_ZQCTL1_OFFSET 
+#undef DDRC_ZQCTL1_OFFSET
 #define DDRC_ZQCTL1_OFFSET                                                         0XFD070184
-#undef DDRC_DFITMG0_OFFSET 
+#undef DDRC_DFITMG0_OFFSET
 #define DDRC_DFITMG0_OFFSET                                                        0XFD070190
-#undef DDRC_DFITMG1_OFFSET 
+#undef DDRC_DFITMG1_OFFSET
 #define DDRC_DFITMG1_OFFSET                                                        0XFD070194
-#undef DDRC_DFILPCFG0_OFFSET 
+#undef DDRC_DFILPCFG0_OFFSET
 #define DDRC_DFILPCFG0_OFFSET                                                      0XFD070198
-#undef DDRC_DFILPCFG1_OFFSET 
+#undef DDRC_DFILPCFG1_OFFSET
 #define DDRC_DFILPCFG1_OFFSET                                                      0XFD07019C
-#undef DDRC_DFIUPD0_OFFSET 
+#undef DDRC_DFIUPD0_OFFSET
 #define DDRC_DFIUPD0_OFFSET                                                        0XFD0701A0
-#undef DDRC_DFIUPD1_OFFSET 
+#undef DDRC_DFIUPD1_OFFSET
 #define DDRC_DFIUPD1_OFFSET                                                        0XFD0701A4
-#undef DDRC_DFIMISC_OFFSET 
+#undef DDRC_DFIMISC_OFFSET
 #define DDRC_DFIMISC_OFFSET                                                        0XFD0701B0
-#undef DDRC_DFITMG2_OFFSET 
+#undef DDRC_DFITMG2_OFFSET
 #define DDRC_DFITMG2_OFFSET                                                        0XFD0701B4
-#undef DDRC_DBICTL_OFFSET 
+#undef DDRC_DBICTL_OFFSET
 #define DDRC_DBICTL_OFFSET                                                         0XFD0701C0
-#undef DDRC_ADDRMAP0_OFFSET 
+#undef DDRC_ADDRMAP0_OFFSET
 #define DDRC_ADDRMAP0_OFFSET                                                       0XFD070200
-#undef DDRC_ADDRMAP1_OFFSET 
+#undef DDRC_ADDRMAP1_OFFSET
 #define DDRC_ADDRMAP1_OFFSET                                                       0XFD070204
-#undef DDRC_ADDRMAP2_OFFSET 
+#undef DDRC_ADDRMAP2_OFFSET
 #define DDRC_ADDRMAP2_OFFSET                                                       0XFD070208
-#undef DDRC_ADDRMAP3_OFFSET 
+#undef DDRC_ADDRMAP3_OFFSET
 #define DDRC_ADDRMAP3_OFFSET                                                       0XFD07020C
-#undef DDRC_ADDRMAP4_OFFSET 
+#undef DDRC_ADDRMAP4_OFFSET
 #define DDRC_ADDRMAP4_OFFSET                                                       0XFD070210
-#undef DDRC_ADDRMAP5_OFFSET 
+#undef DDRC_ADDRMAP5_OFFSET
 #define DDRC_ADDRMAP5_OFFSET                                                       0XFD070214
-#undef DDRC_ADDRMAP6_OFFSET 
+#undef DDRC_ADDRMAP6_OFFSET
 #define DDRC_ADDRMAP6_OFFSET                                                       0XFD070218
-#undef DDRC_ADDRMAP7_OFFSET 
+#undef DDRC_ADDRMAP7_OFFSET
 #define DDRC_ADDRMAP7_OFFSET                                                       0XFD07021C
-#undef DDRC_ADDRMAP8_OFFSET 
+#undef DDRC_ADDRMAP8_OFFSET
 #define DDRC_ADDRMAP8_OFFSET                                                       0XFD070220
-#undef DDRC_ADDRMAP9_OFFSET 
+#undef DDRC_ADDRMAP9_OFFSET
 #define DDRC_ADDRMAP9_OFFSET                                                       0XFD070224
-#undef DDRC_ADDRMAP10_OFFSET 
+#undef DDRC_ADDRMAP10_OFFSET
 #define DDRC_ADDRMAP10_OFFSET                                                      0XFD070228
-#undef DDRC_ADDRMAP11_OFFSET 
+#undef DDRC_ADDRMAP11_OFFSET
 #define DDRC_ADDRMAP11_OFFSET                                                      0XFD07022C
-#undef DDRC_ODTCFG_OFFSET 
+#undef DDRC_ODTCFG_OFFSET
 #define DDRC_ODTCFG_OFFSET                                                         0XFD070240
-#undef DDRC_ODTMAP_OFFSET 
+#undef DDRC_ODTMAP_OFFSET
 #define DDRC_ODTMAP_OFFSET                                                         0XFD070244
-#undef DDRC_SCHED_OFFSET 
+#undef DDRC_SCHED_OFFSET
 #define DDRC_SCHED_OFFSET                                                          0XFD070250
-#undef DDRC_PERFLPR1_OFFSET 
+#undef DDRC_PERFLPR1_OFFSET
 #define DDRC_PERFLPR1_OFFSET                                                       0XFD070264
-#undef DDRC_PERFWR1_OFFSET 
+#undef DDRC_PERFWR1_OFFSET
 #define DDRC_PERFWR1_OFFSET                                                        0XFD07026C
-#undef DDRC_DQMAP0_OFFSET 
+#undef DDRC_DQMAP0_OFFSET
 #define DDRC_DQMAP0_OFFSET                                                         0XFD070280
-#undef DDRC_DQMAP1_OFFSET 
+#undef DDRC_DQMAP1_OFFSET
 #define DDRC_DQMAP1_OFFSET                                                         0XFD070284
-#undef DDRC_DQMAP2_OFFSET 
+#undef DDRC_DQMAP2_OFFSET
 #define DDRC_DQMAP2_OFFSET                                                         0XFD070288
-#undef DDRC_DQMAP3_OFFSET 
+#undef DDRC_DQMAP3_OFFSET
 #define DDRC_DQMAP3_OFFSET                                                         0XFD07028C
-#undef DDRC_DQMAP4_OFFSET 
+#undef DDRC_DQMAP4_OFFSET
 #define DDRC_DQMAP4_OFFSET                                                         0XFD070290
-#undef DDRC_DQMAP5_OFFSET 
+#undef DDRC_DQMAP5_OFFSET
 #define DDRC_DQMAP5_OFFSET                                                         0XFD070294
-#undef DDRC_DBG0_OFFSET 
+#undef DDRC_DBG0_OFFSET
 #define DDRC_DBG0_OFFSET                                                           0XFD070300
-#undef DDRC_DBGCMD_OFFSET 
+#undef DDRC_DBGCMD_OFFSET
 #define DDRC_DBGCMD_OFFSET                                                         0XFD07030C
-#undef DDRC_SWCTL_OFFSET 
+#undef DDRC_SWCTL_OFFSET
 #define DDRC_SWCTL_OFFSET                                                          0XFD070320
-#undef DDRC_PCCFG_OFFSET 
+#undef DDRC_PCCFG_OFFSET
 #define DDRC_PCCFG_OFFSET                                                          0XFD070400
-#undef DDRC_PCFGR_0_OFFSET 
+#undef DDRC_PCFGR_0_OFFSET
 #define DDRC_PCFGR_0_OFFSET                                                        0XFD070404
-#undef DDRC_PCFGW_0_OFFSET 
+#undef DDRC_PCFGW_0_OFFSET
 #define DDRC_PCFGW_0_OFFSET                                                        0XFD070408
-#undef DDRC_PCTRL_0_OFFSET 
+#undef DDRC_PCTRL_0_OFFSET
 #define DDRC_PCTRL_0_OFFSET                                                        0XFD070490
-#undef DDRC_PCFGQOS0_0_OFFSET 
+#undef DDRC_PCFGQOS0_0_OFFSET
 #define DDRC_PCFGQOS0_0_OFFSET                                                     0XFD070494
-#undef DDRC_PCFGQOS1_0_OFFSET 
+#undef DDRC_PCFGQOS1_0_OFFSET
 #define DDRC_PCFGQOS1_0_OFFSET                                                     0XFD070498
-#undef DDRC_PCFGR_1_OFFSET 
+#undef DDRC_PCFGR_1_OFFSET
 #define DDRC_PCFGR_1_OFFSET                                                        0XFD0704B4
-#undef DDRC_PCFGW_1_OFFSET 
+#undef DDRC_PCFGW_1_OFFSET
 #define DDRC_PCFGW_1_OFFSET                                                        0XFD0704B8
-#undef DDRC_PCTRL_1_OFFSET 
+#undef DDRC_PCTRL_1_OFFSET
 #define DDRC_PCTRL_1_OFFSET                                                        0XFD070540
-#undef DDRC_PCFGQOS0_1_OFFSET 
+#undef DDRC_PCFGQOS0_1_OFFSET
 #define DDRC_PCFGQOS0_1_OFFSET                                                     0XFD070544
-#undef DDRC_PCFGQOS1_1_OFFSET 
+#undef DDRC_PCFGQOS1_1_OFFSET
 #define DDRC_PCFGQOS1_1_OFFSET                                                     0XFD070548
-#undef DDRC_PCFGR_2_OFFSET 
+#undef DDRC_PCFGR_2_OFFSET
 #define DDRC_PCFGR_2_OFFSET                                                        0XFD070564
-#undef DDRC_PCFGW_2_OFFSET 
+#undef DDRC_PCFGW_2_OFFSET
 #define DDRC_PCFGW_2_OFFSET                                                        0XFD070568
-#undef DDRC_PCTRL_2_OFFSET 
+#undef DDRC_PCTRL_2_OFFSET
 #define DDRC_PCTRL_2_OFFSET                                                        0XFD0705F0
-#undef DDRC_PCFGQOS0_2_OFFSET 
+#undef DDRC_PCFGQOS0_2_OFFSET
 #define DDRC_PCFGQOS0_2_OFFSET                                                     0XFD0705F4
-#undef DDRC_PCFGQOS1_2_OFFSET 
+#undef DDRC_PCFGQOS1_2_OFFSET
 #define DDRC_PCFGQOS1_2_OFFSET                                                     0XFD0705F8
-#undef DDRC_PCFGR_3_OFFSET 
+#undef DDRC_PCFGR_3_OFFSET
 #define DDRC_PCFGR_3_OFFSET                                                        0XFD070614
-#undef DDRC_PCFGW_3_OFFSET 
+#undef DDRC_PCFGW_3_OFFSET
 #define DDRC_PCFGW_3_OFFSET                                                        0XFD070618
-#undef DDRC_PCTRL_3_OFFSET 
+#undef DDRC_PCTRL_3_OFFSET
 #define DDRC_PCTRL_3_OFFSET                                                        0XFD0706A0
-#undef DDRC_PCFGQOS0_3_OFFSET 
+#undef DDRC_PCFGQOS0_3_OFFSET
 #define DDRC_PCFGQOS0_3_OFFSET                                                     0XFD0706A4
-#undef DDRC_PCFGQOS1_3_OFFSET 
+#undef DDRC_PCFGQOS1_3_OFFSET
 #define DDRC_PCFGQOS1_3_OFFSET                                                     0XFD0706A8
-#undef DDRC_PCFGWQOS0_3_OFFSET 
+#undef DDRC_PCFGWQOS0_3_OFFSET
 #define DDRC_PCFGWQOS0_3_OFFSET                                                    0XFD0706AC
-#undef DDRC_PCFGWQOS1_3_OFFSET 
+#undef DDRC_PCFGWQOS1_3_OFFSET
 #define DDRC_PCFGWQOS1_3_OFFSET                                                    0XFD0706B0
-#undef DDRC_PCFGR_4_OFFSET 
+#undef DDRC_PCFGR_4_OFFSET
 #define DDRC_PCFGR_4_OFFSET                                                        0XFD0706C4
-#undef DDRC_PCFGW_4_OFFSET 
+#undef DDRC_PCFGW_4_OFFSET
 #define DDRC_PCFGW_4_OFFSET                                                        0XFD0706C8
-#undef DDRC_PCTRL_4_OFFSET 
+#undef DDRC_PCTRL_4_OFFSET
 #define DDRC_PCTRL_4_OFFSET                                                        0XFD070750
-#undef DDRC_PCFGQOS0_4_OFFSET 
+#undef DDRC_PCFGQOS0_4_OFFSET
 #define DDRC_PCFGQOS0_4_OFFSET                                                     0XFD070754
-#undef DDRC_PCFGQOS1_4_OFFSET 
+#undef DDRC_PCFGQOS1_4_OFFSET
 #define DDRC_PCFGQOS1_4_OFFSET                                                     0XFD070758
-#undef DDRC_PCFGWQOS0_4_OFFSET 
+#undef DDRC_PCFGWQOS0_4_OFFSET
 #define DDRC_PCFGWQOS0_4_OFFSET                                                    0XFD07075C
-#undef DDRC_PCFGWQOS1_4_OFFSET 
+#undef DDRC_PCFGWQOS1_4_OFFSET
 #define DDRC_PCFGWQOS1_4_OFFSET                                                    0XFD070760
-#undef DDRC_PCFGR_5_OFFSET 
+#undef DDRC_PCFGR_5_OFFSET
 #define DDRC_PCFGR_5_OFFSET                                                        0XFD070774
-#undef DDRC_PCFGW_5_OFFSET 
+#undef DDRC_PCFGW_5_OFFSET
 #define DDRC_PCFGW_5_OFFSET                                                        0XFD070778
-#undef DDRC_PCTRL_5_OFFSET 
+#undef DDRC_PCTRL_5_OFFSET
 #define DDRC_PCTRL_5_OFFSET                                                        0XFD070800
-#undef DDRC_PCFGQOS0_5_OFFSET 
+#undef DDRC_PCFGQOS0_5_OFFSET
 #define DDRC_PCFGQOS0_5_OFFSET                                                     0XFD070804
-#undef DDRC_PCFGQOS1_5_OFFSET 
+#undef DDRC_PCFGQOS1_5_OFFSET
 #define DDRC_PCFGQOS1_5_OFFSET                                                     0XFD070808
-#undef DDRC_PCFGWQOS0_5_OFFSET 
+#undef DDRC_PCFGWQOS0_5_OFFSET
 #define DDRC_PCFGWQOS0_5_OFFSET                                                    0XFD07080C
-#undef DDRC_PCFGWQOS1_5_OFFSET 
+#undef DDRC_PCFGWQOS1_5_OFFSET
 #define DDRC_PCFGWQOS1_5_OFFSET                                                    0XFD070810
-#undef DDRC_SARBASE0_OFFSET 
+#undef DDRC_SARBASE0_OFFSET
 #define DDRC_SARBASE0_OFFSET                                                       0XFD070F04
-#undef DDRC_SARSIZE0_OFFSET 
+#undef DDRC_SARSIZE0_OFFSET
 #define DDRC_SARSIZE0_OFFSET                                                       0XFD070F08
-#undef DDRC_SARBASE1_OFFSET 
+#undef DDRC_SARBASE1_OFFSET
 #define DDRC_SARBASE1_OFFSET                                                       0XFD070F0C
-#undef DDRC_SARSIZE1_OFFSET 
+#undef DDRC_SARSIZE1_OFFSET
 #define DDRC_SARSIZE1_OFFSET                                                       0XFD070F10
-#undef DDRC_DFITMG0_SHADOW_OFFSET 
+#undef DDRC_DFITMG0_SHADOW_OFFSET
 #define DDRC_DFITMG0_SHADOW_OFFSET                                                 0XFD072190
-#undef CRF_APB_RST_DDR_SS_OFFSET 
+#undef CRF_APB_RST_DDR_SS_OFFSET
 #define CRF_APB_RST_DDR_SS_OFFSET                                                  0XFD1A0108
-#undef DDR_PHY_PGCR0_OFFSET 
+#undef DDR_PHY_PGCR0_OFFSET
 #define DDR_PHY_PGCR0_OFFSET                                                       0XFD080010
-#undef DDR_PHY_PGCR2_OFFSET 
+#undef DDR_PHY_PGCR2_OFFSET
 #define DDR_PHY_PGCR2_OFFSET                                                       0XFD080018
-#undef DDR_PHY_PGCR3_OFFSET 
+#undef DDR_PHY_PGCR3_OFFSET
 #define DDR_PHY_PGCR3_OFFSET                                                       0XFD08001C
-#undef DDR_PHY_PGCR5_OFFSET 
+#undef DDR_PHY_PGCR5_OFFSET
 #define DDR_PHY_PGCR5_OFFSET                                                       0XFD080024
-#undef DDR_PHY_PTR0_OFFSET 
+#undef DDR_PHY_PTR0_OFFSET
 #define DDR_PHY_PTR0_OFFSET                                                        0XFD080040
-#undef DDR_PHY_PTR1_OFFSET 
+#undef DDR_PHY_PTR1_OFFSET
 #define DDR_PHY_PTR1_OFFSET                                                        0XFD080044
-#undef DDR_PHY_PLLCR0_OFFSET 
+#undef DDR_PHY_PLLCR0_OFFSET
 #define DDR_PHY_PLLCR0_OFFSET                                                      0XFD080068
-#undef DDR_PHY_DSGCR_OFFSET 
+#undef DDR_PHY_DSGCR_OFFSET
 #define DDR_PHY_DSGCR_OFFSET                                                       0XFD080090
-#undef DDR_PHY_GPR0_OFFSET 
+#undef DDR_PHY_GPR0_OFFSET
 #define DDR_PHY_GPR0_OFFSET                                                        0XFD0800C0
-#undef DDR_PHY_DCR_OFFSET 
+#undef DDR_PHY_DCR_OFFSET
 #define DDR_PHY_DCR_OFFSET                                                         0XFD080100
-#undef DDR_PHY_DTPR0_OFFSET 
+#undef DDR_PHY_DTPR0_OFFSET
 #define DDR_PHY_DTPR0_OFFSET                                                       0XFD080110
-#undef DDR_PHY_DTPR1_OFFSET 
+#undef DDR_PHY_DTPR1_OFFSET
 #define DDR_PHY_DTPR1_OFFSET                                                       0XFD080114
-#undef DDR_PHY_DTPR2_OFFSET 
+#undef DDR_PHY_DTPR2_OFFSET
 #define DDR_PHY_DTPR2_OFFSET                                                       0XFD080118
-#undef DDR_PHY_DTPR3_OFFSET 
+#undef DDR_PHY_DTPR3_OFFSET
 #define DDR_PHY_DTPR3_OFFSET                                                       0XFD08011C
-#undef DDR_PHY_DTPR4_OFFSET 
+#undef DDR_PHY_DTPR4_OFFSET
 #define DDR_PHY_DTPR4_OFFSET                                                       0XFD080120
-#undef DDR_PHY_DTPR5_OFFSET 
+#undef DDR_PHY_DTPR5_OFFSET
 #define DDR_PHY_DTPR5_OFFSET                                                       0XFD080124
-#undef DDR_PHY_DTPR6_OFFSET 
+#undef DDR_PHY_DTPR6_OFFSET
 #define DDR_PHY_DTPR6_OFFSET                                                       0XFD080128
-#undef DDR_PHY_RDIMMGCR0_OFFSET 
+#undef DDR_PHY_RDIMMGCR0_OFFSET
 #define DDR_PHY_RDIMMGCR0_OFFSET                                                   0XFD080140
-#undef DDR_PHY_RDIMMGCR1_OFFSET 
+#undef DDR_PHY_RDIMMGCR1_OFFSET
 #define DDR_PHY_RDIMMGCR1_OFFSET                                                   0XFD080144
-#undef DDR_PHY_RDIMMCR0_OFFSET 
+#undef DDR_PHY_RDIMMCR0_OFFSET
 #define DDR_PHY_RDIMMCR0_OFFSET                                                    0XFD080150
-#undef DDR_PHY_RDIMMCR1_OFFSET 
+#undef DDR_PHY_RDIMMCR1_OFFSET
 #define DDR_PHY_RDIMMCR1_OFFSET                                                    0XFD080154
-#undef DDR_PHY_MR0_OFFSET 
+#undef DDR_PHY_MR0_OFFSET
 #define DDR_PHY_MR0_OFFSET                                                         0XFD080180
-#undef DDR_PHY_MR1_OFFSET 
+#undef DDR_PHY_MR1_OFFSET
 #define DDR_PHY_MR1_OFFSET                                                         0XFD080184
-#undef DDR_PHY_MR2_OFFSET 
+#undef DDR_PHY_MR2_OFFSET
 #define DDR_PHY_MR2_OFFSET                                                         0XFD080188
-#undef DDR_PHY_MR3_OFFSET 
+#undef DDR_PHY_MR3_OFFSET
 #define DDR_PHY_MR3_OFFSET                                                         0XFD08018C
-#undef DDR_PHY_MR4_OFFSET 
+#undef DDR_PHY_MR4_OFFSET
 #define DDR_PHY_MR4_OFFSET                                                         0XFD080190
-#undef DDR_PHY_MR5_OFFSET 
+#undef DDR_PHY_MR5_OFFSET
 #define DDR_PHY_MR5_OFFSET                                                         0XFD080194
-#undef DDR_PHY_MR6_OFFSET 
+#undef DDR_PHY_MR6_OFFSET
 #define DDR_PHY_MR6_OFFSET                                                         0XFD080198
-#undef DDR_PHY_MR11_OFFSET 
+#undef DDR_PHY_MR11_OFFSET
 #define DDR_PHY_MR11_OFFSET                                                        0XFD0801AC
-#undef DDR_PHY_MR12_OFFSET 
+#undef DDR_PHY_MR12_OFFSET
 #define DDR_PHY_MR12_OFFSET                                                        0XFD0801B0
-#undef DDR_PHY_MR13_OFFSET 
+#undef DDR_PHY_MR13_OFFSET
 #define DDR_PHY_MR13_OFFSET                                                        0XFD0801B4
-#undef DDR_PHY_MR14_OFFSET 
+#undef DDR_PHY_MR14_OFFSET
 #define DDR_PHY_MR14_OFFSET                                                        0XFD0801B8
-#undef DDR_PHY_MR22_OFFSET 
+#undef DDR_PHY_MR22_OFFSET
 #define DDR_PHY_MR22_OFFSET                                                        0XFD0801D8
-#undef DDR_PHY_DTCR0_OFFSET 
+#undef DDR_PHY_DTCR0_OFFSET
 #define DDR_PHY_DTCR0_OFFSET                                                       0XFD080200
-#undef DDR_PHY_DTCR1_OFFSET 
+#undef DDR_PHY_DTCR1_OFFSET
 #define DDR_PHY_DTCR1_OFFSET                                                       0XFD080204
-#undef DDR_PHY_CATR0_OFFSET 
+#undef DDR_PHY_CATR0_OFFSET
 #define DDR_PHY_CATR0_OFFSET                                                       0XFD080240
-#undef DDR_PHY_DQSDR0_OFFSET 
+#undef DDR_PHY_DQSDR0_OFFSET
 #define DDR_PHY_DQSDR0_OFFSET                                                      0XFD080250
-#undef DDR_PHY_BISTLSR_OFFSET 
+#undef DDR_PHY_BISTLSR_OFFSET
 #define DDR_PHY_BISTLSR_OFFSET                                                     0XFD080414
-#undef DDR_PHY_RIOCR5_OFFSET 
+#undef DDR_PHY_RIOCR5_OFFSET
 #define DDR_PHY_RIOCR5_OFFSET                                                      0XFD0804F4
-#undef DDR_PHY_ACIOCR0_OFFSET 
+#undef DDR_PHY_ACIOCR0_OFFSET
 #define DDR_PHY_ACIOCR0_OFFSET                                                     0XFD080500
-#undef DDR_PHY_ACIOCR2_OFFSET 
+#undef DDR_PHY_ACIOCR2_OFFSET
 #define DDR_PHY_ACIOCR2_OFFSET                                                     0XFD080508
-#undef DDR_PHY_ACIOCR3_OFFSET 
+#undef DDR_PHY_ACIOCR3_OFFSET
 #define DDR_PHY_ACIOCR3_OFFSET                                                     0XFD08050C
-#undef DDR_PHY_ACIOCR4_OFFSET 
+#undef DDR_PHY_ACIOCR4_OFFSET
 #define DDR_PHY_ACIOCR4_OFFSET                                                     0XFD080510
-#undef DDR_PHY_IOVCR0_OFFSET 
+#undef DDR_PHY_IOVCR0_OFFSET
 #define DDR_PHY_IOVCR0_OFFSET                                                      0XFD080520
-#undef DDR_PHY_VTCR0_OFFSET 
+#undef DDR_PHY_VTCR0_OFFSET
 #define DDR_PHY_VTCR0_OFFSET                                                       0XFD080528
-#undef DDR_PHY_VTCR1_OFFSET 
+#undef DDR_PHY_VTCR1_OFFSET
 #define DDR_PHY_VTCR1_OFFSET                                                       0XFD08052C
-#undef DDR_PHY_ACBDLR1_OFFSET 
+#undef DDR_PHY_ACBDLR1_OFFSET
 #define DDR_PHY_ACBDLR1_OFFSET                                                     0XFD080544
-#undef DDR_PHY_ACBDLR2_OFFSET 
+#undef DDR_PHY_ACBDLR2_OFFSET
 #define DDR_PHY_ACBDLR2_OFFSET                                                     0XFD080548
-#undef DDR_PHY_ACBDLR6_OFFSET 
+#undef DDR_PHY_ACBDLR6_OFFSET
 #define DDR_PHY_ACBDLR6_OFFSET                                                     0XFD080558
-#undef DDR_PHY_ACBDLR7_OFFSET 
+#undef DDR_PHY_ACBDLR7_OFFSET
 #define DDR_PHY_ACBDLR7_OFFSET                                                     0XFD08055C
-#undef DDR_PHY_ACBDLR8_OFFSET 
+#undef DDR_PHY_ACBDLR8_OFFSET
 #define DDR_PHY_ACBDLR8_OFFSET                                                     0XFD080560
-#undef DDR_PHY_ACBDLR9_OFFSET 
+#undef DDR_PHY_ACBDLR9_OFFSET
 #define DDR_PHY_ACBDLR9_OFFSET                                                     0XFD080564
-#undef DDR_PHY_ZQCR_OFFSET 
+#undef DDR_PHY_ZQCR_OFFSET
 #define DDR_PHY_ZQCR_OFFSET                                                        0XFD080680
-#undef DDR_PHY_ZQ0PR0_OFFSET 
+#undef DDR_PHY_ZQ0PR0_OFFSET
 #define DDR_PHY_ZQ0PR0_OFFSET                                                      0XFD080684
-#undef DDR_PHY_ZQ0OR0_OFFSET 
+#undef DDR_PHY_ZQ0OR0_OFFSET
 #define DDR_PHY_ZQ0OR0_OFFSET                                                      0XFD080694
-#undef DDR_PHY_ZQ0OR1_OFFSET 
+#undef DDR_PHY_ZQ0OR1_OFFSET
 #define DDR_PHY_ZQ0OR1_OFFSET                                                      0XFD080698
-#undef DDR_PHY_ZQ1PR0_OFFSET 
+#undef DDR_PHY_ZQ1PR0_OFFSET
 #define DDR_PHY_ZQ1PR0_OFFSET                                                      0XFD0806A4
-#undef DDR_PHY_DX0GCR0_OFFSET 
+#undef DDR_PHY_DX0GCR0_OFFSET
 #define DDR_PHY_DX0GCR0_OFFSET                                                     0XFD080700
-#undef DDR_PHY_DX0GCR4_OFFSET 
+#undef DDR_PHY_DX0GCR4_OFFSET
 #define DDR_PHY_DX0GCR4_OFFSET                                                     0XFD080710
-#undef DDR_PHY_DX0GCR5_OFFSET 
+#undef DDR_PHY_DX0GCR5_OFFSET
 #define DDR_PHY_DX0GCR5_OFFSET                                                     0XFD080714
-#undef DDR_PHY_DX0GCR6_OFFSET 
+#undef DDR_PHY_DX0GCR6_OFFSET
 #define DDR_PHY_DX0GCR6_OFFSET                                                     0XFD080718
-#undef DDR_PHY_DX1GCR0_OFFSET 
+#undef DDR_PHY_DX1GCR0_OFFSET
 #define DDR_PHY_DX1GCR0_OFFSET                                                     0XFD080800
-#undef DDR_PHY_DX1GCR4_OFFSET 
+#undef DDR_PHY_DX1GCR4_OFFSET
 #define DDR_PHY_DX1GCR4_OFFSET                                                     0XFD080810
-#undef DDR_PHY_DX1GCR5_OFFSET 
+#undef DDR_PHY_DX1GCR5_OFFSET
 #define DDR_PHY_DX1GCR5_OFFSET                                                     0XFD080814
-#undef DDR_PHY_DX1GCR6_OFFSET 
+#undef DDR_PHY_DX1GCR6_OFFSET
 #define DDR_PHY_DX1GCR6_OFFSET                                                     0XFD080818
-#undef DDR_PHY_DX2GCR0_OFFSET 
+#undef DDR_PHY_DX2GCR0_OFFSET
 #define DDR_PHY_DX2GCR0_OFFSET                                                     0XFD080900
-#undef DDR_PHY_DX2GCR1_OFFSET 
+#undef DDR_PHY_DX2GCR1_OFFSET
 #define DDR_PHY_DX2GCR1_OFFSET                                                     0XFD080904
-#undef DDR_PHY_DX2GCR4_OFFSET 
+#undef DDR_PHY_DX2GCR4_OFFSET
 #define DDR_PHY_DX2GCR4_OFFSET                                                     0XFD080910
-#undef DDR_PHY_DX2GCR5_OFFSET 
+#undef DDR_PHY_DX2GCR5_OFFSET
 #define DDR_PHY_DX2GCR5_OFFSET                                                     0XFD080914
-#undef DDR_PHY_DX2GCR6_OFFSET 
+#undef DDR_PHY_DX2GCR6_OFFSET
 #define DDR_PHY_DX2GCR6_OFFSET                                                     0XFD080918
-#undef DDR_PHY_DX3GCR0_OFFSET 
+#undef DDR_PHY_DX3GCR0_OFFSET
 #define DDR_PHY_DX3GCR0_OFFSET                                                     0XFD080A00
-#undef DDR_PHY_DX3GCR1_OFFSET 
+#undef DDR_PHY_DX3GCR1_OFFSET
 #define DDR_PHY_DX3GCR1_OFFSET                                                     0XFD080A04
-#undef DDR_PHY_DX3GCR4_OFFSET 
+#undef DDR_PHY_DX3GCR4_OFFSET
 #define DDR_PHY_DX3GCR4_OFFSET                                                     0XFD080A10
-#undef DDR_PHY_DX3GCR5_OFFSET 
+#undef DDR_PHY_DX3GCR5_OFFSET
 #define DDR_PHY_DX3GCR5_OFFSET                                                     0XFD080A14
-#undef DDR_PHY_DX3GCR6_OFFSET 
+#undef DDR_PHY_DX3GCR6_OFFSET
 #define DDR_PHY_DX3GCR6_OFFSET                                                     0XFD080A18
-#undef DDR_PHY_DX4GCR0_OFFSET 
+#undef DDR_PHY_DX4GCR0_OFFSET
 #define DDR_PHY_DX4GCR0_OFFSET                                                     0XFD080B00
-#undef DDR_PHY_DX4GCR1_OFFSET 
+#undef DDR_PHY_DX4GCR1_OFFSET
 #define DDR_PHY_DX4GCR1_OFFSET                                                     0XFD080B04
-#undef DDR_PHY_DX4GCR4_OFFSET 
+#undef DDR_PHY_DX4GCR4_OFFSET
 #define DDR_PHY_DX4GCR4_OFFSET                                                     0XFD080B10
-#undef DDR_PHY_DX4GCR5_OFFSET 
+#undef DDR_PHY_DX4GCR5_OFFSET
 #define DDR_PHY_DX4GCR5_OFFSET                                                     0XFD080B14
-#undef DDR_PHY_DX4GCR6_OFFSET 
+#undef DDR_PHY_DX4GCR6_OFFSET
 #define DDR_PHY_DX4GCR6_OFFSET                                                     0XFD080B18
-#undef DDR_PHY_DX5GCR0_OFFSET 
+#undef DDR_PHY_DX5GCR0_OFFSET
 #define DDR_PHY_DX5GCR0_OFFSET                                                     0XFD080C00
-#undef DDR_PHY_DX5GCR1_OFFSET 
+#undef DDR_PHY_DX5GCR1_OFFSET
 #define DDR_PHY_DX5GCR1_OFFSET                                                     0XFD080C04
-#undef DDR_PHY_DX5GCR4_OFFSET 
+#undef DDR_PHY_DX5GCR4_OFFSET
 #define DDR_PHY_DX5GCR4_OFFSET                                                     0XFD080C10
-#undef DDR_PHY_DX5GCR5_OFFSET 
+#undef DDR_PHY_DX5GCR5_OFFSET
 #define DDR_PHY_DX5GCR5_OFFSET                                                     0XFD080C14
-#undef DDR_PHY_DX5GCR6_OFFSET 
+#undef DDR_PHY_DX5GCR6_OFFSET
 #define DDR_PHY_DX5GCR6_OFFSET                                                     0XFD080C18
-#undef DDR_PHY_DX6GCR0_OFFSET 
+#undef DDR_PHY_DX6GCR0_OFFSET
 #define DDR_PHY_DX6GCR0_OFFSET                                                     0XFD080D00
-#undef DDR_PHY_DX6GCR1_OFFSET 
+#undef DDR_PHY_DX6GCR1_OFFSET
 #define DDR_PHY_DX6GCR1_OFFSET                                                     0XFD080D04
-#undef DDR_PHY_DX6GCR4_OFFSET 
+#undef DDR_PHY_DX6GCR4_OFFSET
 #define DDR_PHY_DX6GCR4_OFFSET                                                     0XFD080D10
-#undef DDR_PHY_DX6GCR5_OFFSET 
+#undef DDR_PHY_DX6GCR5_OFFSET
 #define DDR_PHY_DX6GCR5_OFFSET                                                     0XFD080D14
-#undef DDR_PHY_DX6GCR6_OFFSET 
+#undef DDR_PHY_DX6GCR6_OFFSET
 #define DDR_PHY_DX6GCR6_OFFSET                                                     0XFD080D18
-#undef DDR_PHY_DX7GCR0_OFFSET 
+#undef DDR_PHY_DX7GCR0_OFFSET
 #define DDR_PHY_DX7GCR0_OFFSET                                                     0XFD080E00
-#undef DDR_PHY_DX7GCR1_OFFSET 
+#undef DDR_PHY_DX7GCR1_OFFSET
 #define DDR_PHY_DX7GCR1_OFFSET                                                     0XFD080E04
-#undef DDR_PHY_DX7GCR4_OFFSET 
+#undef DDR_PHY_DX7GCR4_OFFSET
 #define DDR_PHY_DX7GCR4_OFFSET                                                     0XFD080E10
-#undef DDR_PHY_DX7GCR5_OFFSET 
+#undef DDR_PHY_DX7GCR5_OFFSET
 #define DDR_PHY_DX7GCR5_OFFSET                                                     0XFD080E14
-#undef DDR_PHY_DX7GCR6_OFFSET 
+#undef DDR_PHY_DX7GCR6_OFFSET
 #define DDR_PHY_DX7GCR6_OFFSET                                                     0XFD080E18
-#undef DDR_PHY_DX8GCR0_OFFSET 
+#undef DDR_PHY_DX8GCR0_OFFSET
 #define DDR_PHY_DX8GCR0_OFFSET                                                     0XFD080F00
-#undef DDR_PHY_DX8GCR1_OFFSET 
+#undef DDR_PHY_DX8GCR1_OFFSET
 #define DDR_PHY_DX8GCR1_OFFSET                                                     0XFD080F04
-#undef DDR_PHY_DX8GCR4_OFFSET 
+#undef DDR_PHY_DX8GCR4_OFFSET
 #define DDR_PHY_DX8GCR4_OFFSET                                                     0XFD080F10
-#undef DDR_PHY_DX8GCR5_OFFSET 
+#undef DDR_PHY_DX8GCR5_OFFSET
 #define DDR_PHY_DX8GCR5_OFFSET                                                     0XFD080F14
-#undef DDR_PHY_DX8GCR6_OFFSET 
+#undef DDR_PHY_DX8GCR6_OFFSET
 #define DDR_PHY_DX8GCR6_OFFSET                                                     0XFD080F18
-#undef DDR_PHY_DX8SL0OSC_OFFSET 
+#undef DDR_PHY_DX8SL0OSC_OFFSET
 #define DDR_PHY_DX8SL0OSC_OFFSET                                                   0XFD081400
-#undef DDR_PHY_DX8SL0PLLCR0_OFFSET 
+#undef DDR_PHY_DX8SL0PLLCR0_OFFSET
 #define DDR_PHY_DX8SL0PLLCR0_OFFSET                                                0XFD081404
-#undef DDR_PHY_DX8SL0DQSCTL_OFFSET 
+#undef DDR_PHY_DX8SL0DQSCTL_OFFSET
 #define DDR_PHY_DX8SL0DQSCTL_OFFSET                                                0XFD08141C
-#undef DDR_PHY_DX8SL0DXCTL2_OFFSET 
+#undef DDR_PHY_DX8SL0DXCTL2_OFFSET
 #define DDR_PHY_DX8SL0DXCTL2_OFFSET                                                0XFD08142C
-#undef DDR_PHY_DX8SL0IOCR_OFFSET 
+#undef DDR_PHY_DX8SL0IOCR_OFFSET
 #define DDR_PHY_DX8SL0IOCR_OFFSET                                                  0XFD081430
-#undef DDR_PHY_DX8SL1OSC_OFFSET 
+#undef DDR_PHY_DX8SL1OSC_OFFSET
 #define DDR_PHY_DX8SL1OSC_OFFSET                                                   0XFD081440
-#undef DDR_PHY_DX8SL1PLLCR0_OFFSET 
+#undef DDR_PHY_DX8SL1PLLCR0_OFFSET
 #define DDR_PHY_DX8SL1PLLCR0_OFFSET                                                0XFD081444
-#undef DDR_PHY_DX8SL1DQSCTL_OFFSET 
+#undef DDR_PHY_DX8SL1DQSCTL_OFFSET
 #define DDR_PHY_DX8SL1DQSCTL_OFFSET                                                0XFD08145C
-#undef DDR_PHY_DX8SL1DXCTL2_OFFSET 
+#undef DDR_PHY_DX8SL1DXCTL2_OFFSET
 #define DDR_PHY_DX8SL1DXCTL2_OFFSET                                                0XFD08146C
-#undef DDR_PHY_DX8SL1IOCR_OFFSET 
+#undef DDR_PHY_DX8SL1IOCR_OFFSET
 #define DDR_PHY_DX8SL1IOCR_OFFSET                                                  0XFD081470
-#undef DDR_PHY_DX8SL2OSC_OFFSET 
+#undef DDR_PHY_DX8SL2OSC_OFFSET
 #define DDR_PHY_DX8SL2OSC_OFFSET                                                   0XFD081480
-#undef DDR_PHY_DX8SL2PLLCR0_OFFSET 
+#undef DDR_PHY_DX8SL2PLLCR0_OFFSET
 #define DDR_PHY_DX8SL2PLLCR0_OFFSET                                                0XFD081484
-#undef DDR_PHY_DX8SL2DQSCTL_OFFSET 
+#undef DDR_PHY_DX8SL2DQSCTL_OFFSET
 #define DDR_PHY_DX8SL2DQSCTL_OFFSET                                                0XFD08149C
-#undef DDR_PHY_DX8SL2DXCTL2_OFFSET 
+#undef DDR_PHY_DX8SL2DXCTL2_OFFSET
 #define DDR_PHY_DX8SL2DXCTL2_OFFSET                                                0XFD0814AC
-#undef DDR_PHY_DX8SL2IOCR_OFFSET 
+#undef DDR_PHY_DX8SL2IOCR_OFFSET
 #define DDR_PHY_DX8SL2IOCR_OFFSET                                                  0XFD0814B0
-#undef DDR_PHY_DX8SL3OSC_OFFSET 
+#undef DDR_PHY_DX8SL3OSC_OFFSET
 #define DDR_PHY_DX8SL3OSC_OFFSET                                                   0XFD0814C0
-#undef DDR_PHY_DX8SL3PLLCR0_OFFSET 
+#undef DDR_PHY_DX8SL3PLLCR0_OFFSET
 #define DDR_PHY_DX8SL3PLLCR0_OFFSET                                                0XFD0814C4
-#undef DDR_PHY_DX8SL3DQSCTL_OFFSET 
+#undef DDR_PHY_DX8SL3DQSCTL_OFFSET
 #define DDR_PHY_DX8SL3DQSCTL_OFFSET                                                0XFD0814DC
-#undef DDR_PHY_DX8SL3DXCTL2_OFFSET 
+#undef DDR_PHY_DX8SL3DXCTL2_OFFSET
 #define DDR_PHY_DX8SL3DXCTL2_OFFSET                                                0XFD0814EC
-#undef DDR_PHY_DX8SL3IOCR_OFFSET 
+#undef DDR_PHY_DX8SL3IOCR_OFFSET
 #define DDR_PHY_DX8SL3IOCR_OFFSET                                                  0XFD0814F0
-#undef DDR_PHY_DX8SL4OSC_OFFSET 
+#undef DDR_PHY_DX8SL4OSC_OFFSET
 #define DDR_PHY_DX8SL4OSC_OFFSET                                                   0XFD081500
-#undef DDR_PHY_DX8SL4PLLCR0_OFFSET 
+#undef DDR_PHY_DX8SL4PLLCR0_OFFSET
 #define DDR_PHY_DX8SL4PLLCR0_OFFSET                                                0XFD081504
-#undef DDR_PHY_DX8SL4DQSCTL_OFFSET 
+#undef DDR_PHY_DX8SL4DQSCTL_OFFSET
 #define DDR_PHY_DX8SL4DQSCTL_OFFSET                                                0XFD08151C
-#undef DDR_PHY_DX8SL4DXCTL2_OFFSET 
+#undef DDR_PHY_DX8SL4DXCTL2_OFFSET
 #define DDR_PHY_DX8SL4DXCTL2_OFFSET                                                0XFD08152C
-#undef DDR_PHY_DX8SL4IOCR_OFFSET 
+#undef DDR_PHY_DX8SL4IOCR_OFFSET
 #define DDR_PHY_DX8SL4IOCR_OFFSET                                                  0XFD081530
-#undef DDR_PHY_DX8SLBPLLCR0_OFFSET 
+#undef DDR_PHY_DX8SLBPLLCR0_OFFSET
 #define DDR_PHY_DX8SLBPLLCR0_OFFSET                                                0XFD0817C4
-#undef DDR_PHY_DX8SLBDQSCTL_OFFSET 
+#undef DDR_PHY_DX8SLBDQSCTL_OFFSET
 #define DDR_PHY_DX8SLBDQSCTL_OFFSET                                                0XFD0817DC
 
 /*
 * DDR block level reset inside of the DDR Sub System
 */
-#undef CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL 
-#undef CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT 
-#undef CRF_APB_RST_DDR_SS_DDR_RESET_MASK 
+#undef CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL
+#undef CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT
+#undef CRF_APB_RST_DDR_SS_DDR_RESET_MASK
 #define CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL                    0x0000000F
 #define CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT                     3
 #define CRF_APB_RST_DDR_SS_DDR_RESET_MASK                      0x00000008U
@@ -3029,9 +3029,9 @@
 * Indicates the configuration of the device used in the system. - 00 - x4
     * device - 01 - x8 device - 10 - x16 device - 11 - x32 device
 */
-#undef DDRC_MSTR_DEVICE_CONFIG_DEFVAL 
-#undef DDRC_MSTR_DEVICE_CONFIG_SHIFT 
-#undef DDRC_MSTR_DEVICE_CONFIG_MASK 
+#undef DDRC_MSTR_DEVICE_CONFIG_DEFVAL
+#undef DDRC_MSTR_DEVICE_CONFIG_SHIFT
+#undef DDRC_MSTR_DEVICE_CONFIG_MASK
 #define DDRC_MSTR_DEVICE_CONFIG_DEFVAL                         0x03040001
 #define DDRC_MSTR_DEVICE_CONFIG_SHIFT                          30
 #define DDRC_MSTR_DEVICE_CONFIG_MASK                           0xC0000000U
@@ -3040,9 +3040,9 @@
 * Choose which registers are used. - 0 - Original registers - 1 - Shadow r
     * egisters
 */
-#undef DDRC_MSTR_FREQUENCY_MODE_DEFVAL 
-#undef DDRC_MSTR_FREQUENCY_MODE_SHIFT 
-#undef DDRC_MSTR_FREQUENCY_MODE_MASK 
+#undef DDRC_MSTR_FREQUENCY_MODE_DEFVAL
+#undef DDRC_MSTR_FREQUENCY_MODE_SHIFT
+#undef DDRC_MSTR_FREQUENCY_MODE_MASK
 #define DDRC_MSTR_FREQUENCY_MODE_DEFVAL                        0x03040001
 #define DDRC_MSTR_FREQUENCY_MODE_SHIFT                         29
 #define DDRC_MSTR_FREQUENCY_MODE_MASK                          0x20000000U
@@ -3055,9 +3055,9 @@
     * Reserved. For 4 ranks following combinations are legal: - 0001 - One ran
     * k - 0011 - Two ranks - 1111 - Four ranks
 */
-#undef DDRC_MSTR_ACTIVE_RANKS_DEFVAL 
-#undef DDRC_MSTR_ACTIVE_RANKS_SHIFT 
-#undef DDRC_MSTR_ACTIVE_RANKS_MASK 
+#undef DDRC_MSTR_ACTIVE_RANKS_DEFVAL
+#undef DDRC_MSTR_ACTIVE_RANKS_SHIFT
+#undef DDRC_MSTR_ACTIVE_RANKS_MASK
 #define DDRC_MSTR_ACTIVE_RANKS_DEFVAL                          0x03040001
 #define DDRC_MSTR_ACTIVE_RANKS_SHIFT                           24
 #define DDRC_MSTR_ACTIVE_RANKS_MASK                            0x03000000U
@@ -3072,9 +3072,9 @@
     * Burst length of 2 is not supported with AXI ports when MEMC_BURST_LENGTH
     *  is 8. Burst length of 2 is only supported with MEMC_FREQ_RATIO = 1
 */
-#undef DDRC_MSTR_BURST_RDWR_DEFVAL 
-#undef DDRC_MSTR_BURST_RDWR_SHIFT 
-#undef DDRC_MSTR_BURST_RDWR_MASK 
+#undef DDRC_MSTR_BURST_RDWR_DEFVAL
+#undef DDRC_MSTR_BURST_RDWR_SHIFT
+#undef DDRC_MSTR_BURST_RDWR_MASK
 #define DDRC_MSTR_BURST_RDWR_DEFVAL                            0x03040001
 #define DDRC_MSTR_BURST_RDWR_SHIFT                             16
 #define DDRC_MSTR_BURST_RDWR_MASK                              0x000F0000U
@@ -3086,9 +3086,9 @@
     * TL1.crc_parity_retry_enable = 1), dll_off_mode is not supported, and thi
     * s bit must be set to '0'.
 */
-#undef DDRC_MSTR_DLL_OFF_MODE_DEFVAL 
-#undef DDRC_MSTR_DLL_OFF_MODE_SHIFT 
-#undef DDRC_MSTR_DLL_OFF_MODE_MASK 
+#undef DDRC_MSTR_DLL_OFF_MODE_DEFVAL
+#undef DDRC_MSTR_DLL_OFF_MODE_SHIFT
+#undef DDRC_MSTR_DLL_OFF_MODE_MASK
 #define DDRC_MSTR_DLL_OFF_MODE_DEFVAL                          0x03040001
 #define DDRC_MSTR_DLL_OFF_MODE_SHIFT                           15
 #define DDRC_MSTR_DLL_OFF_MODE_MASK                            0x00008000U
@@ -3102,9 +3102,9 @@
     *  of 32 and the configuration parameter MEMC_QBUS_SUPPORT is set. Bus wid
     * th refers to DQ bus width (excluding any ECC width).
 */
-#undef DDRC_MSTR_DATA_BUS_WIDTH_DEFVAL 
-#undef DDRC_MSTR_DATA_BUS_WIDTH_SHIFT 
-#undef DDRC_MSTR_DATA_BUS_WIDTH_MASK 
+#undef DDRC_MSTR_DATA_BUS_WIDTH_DEFVAL
+#undef DDRC_MSTR_DATA_BUS_WIDTH_SHIFT
+#undef DDRC_MSTR_DATA_BUS_WIDTH_MASK
 #define DDRC_MSTR_DATA_BUS_WIDTH_DEFVAL                        0x03040001
 #define DDRC_MSTR_DATA_BUS_WIDTH_SHIFT                         12
 #define DDRC_MSTR_DATA_BUS_WIDTH_MASK                          0x00003000U
@@ -3116,9 +3116,9 @@
     * as MR3 bit A3. Note: Geardown mode is not supported if the configuration
     *  parameter MEMC_CMD_RTN2IDLE is set
 */
-#undef DDRC_MSTR_GEARDOWN_MODE_DEFVAL 
-#undef DDRC_MSTR_GEARDOWN_MODE_SHIFT 
-#undef DDRC_MSTR_GEARDOWN_MODE_MASK 
+#undef DDRC_MSTR_GEARDOWN_MODE_DEFVAL
+#undef DDRC_MSTR_GEARDOWN_MODE_SHIFT
+#undef DDRC_MSTR_GEARDOWN_MODE_MASK
 #define DDRC_MSTR_GEARDOWN_MODE_DEFVAL                         0x03040001
 #define DDRC_MSTR_GEARDOWN_MODE_SHIFT                          11
 #define DDRC_MSTR_GEARDOWN_MODE_MASK                           0x00000800U
@@ -3131,9 +3131,9 @@
     * ming is not supported if the configuration parameter MEMC_CMD_RTN2IDLE i
     * s set Note: 2T timing is not supported in DDR4 geardown mode.
 */
-#undef DDRC_MSTR_EN_2T_TIMING_MODE_DEFVAL 
-#undef DDRC_MSTR_EN_2T_TIMING_MODE_SHIFT 
-#undef DDRC_MSTR_EN_2T_TIMING_MODE_MASK 
+#undef DDRC_MSTR_EN_2T_TIMING_MODE_DEFVAL
+#undef DDRC_MSTR_EN_2T_TIMING_MODE_SHIFT
+#undef DDRC_MSTR_EN_2T_TIMING_MODE_MASK
 #define DDRC_MSTR_EN_2T_TIMING_MODE_DEFVAL                     0x03040001
 #define DDRC_MSTR_EN_2T_TIMING_MODE_SHIFT                      10
 #define DDRC_MSTR_EN_2T_TIMING_MODE_MASK                       0x00000400U
@@ -3147,9 +3147,9 @@
     * ed (CRCPARCTL1.crc_parity_retry_enable = 1), burst chop is not supported
     * , and this bit must be set to '0'
 */
-#undef DDRC_MSTR_BURSTCHOP_DEFVAL 
-#undef DDRC_MSTR_BURSTCHOP_SHIFT 
-#undef DDRC_MSTR_BURSTCHOP_MASK 
+#undef DDRC_MSTR_BURSTCHOP_DEFVAL
+#undef DDRC_MSTR_BURSTCHOP_SHIFT
+#undef DDRC_MSTR_BURSTCHOP_MASK
 #define DDRC_MSTR_BURSTCHOP_DEFVAL                             0x03040001
 #define DDRC_MSTR_BURSTCHOP_SHIFT                              9
 #define DDRC_MSTR_BURSTCHOP_MASK                               0x00000200U
@@ -3158,9 +3158,9 @@
 * Select LPDDR4 SDRAM - 1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 d
     * evice in use Present only in designs configured to support LPDDR4.
 */
-#undef DDRC_MSTR_LPDDR4_DEFVAL 
-#undef DDRC_MSTR_LPDDR4_SHIFT 
-#undef DDRC_MSTR_LPDDR4_MASK 
+#undef DDRC_MSTR_LPDDR4_DEFVAL
+#undef DDRC_MSTR_LPDDR4_SHIFT
+#undef DDRC_MSTR_LPDDR4_MASK
 #define DDRC_MSTR_LPDDR4_DEFVAL                                0x03040001
 #define DDRC_MSTR_LPDDR4_SHIFT                                 5
 #define DDRC_MSTR_LPDDR4_MASK                                  0x00000020U
@@ -3169,9 +3169,9 @@
 * Select DDR4 SDRAM - 1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device
     * in use Present only in designs configured to support DDR4.
 */
-#undef DDRC_MSTR_DDR4_DEFVAL 
-#undef DDRC_MSTR_DDR4_SHIFT 
-#undef DDRC_MSTR_DDR4_MASK 
+#undef DDRC_MSTR_DDR4_DEFVAL
+#undef DDRC_MSTR_DDR4_SHIFT
+#undef DDRC_MSTR_DDR4_MASK
 #define DDRC_MSTR_DDR4_DEFVAL                                  0x03040001
 #define DDRC_MSTR_DDR4_SHIFT                                   4
 #define DDRC_MSTR_DDR4_MASK                                    0x00000010U
@@ -3180,9 +3180,9 @@
 * Select LPDDR3 SDRAM - 1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 d
     * evice in use Present only in designs configured to support LPDDR3.
 */
-#undef DDRC_MSTR_LPDDR3_DEFVAL 
-#undef DDRC_MSTR_LPDDR3_SHIFT 
-#undef DDRC_MSTR_LPDDR3_MASK 
+#undef DDRC_MSTR_LPDDR3_DEFVAL
+#undef DDRC_MSTR_LPDDR3_SHIFT
+#undef DDRC_MSTR_LPDDR3_MASK
 #define DDRC_MSTR_LPDDR3_DEFVAL                                0x03040001
 #define DDRC_MSTR_LPDDR3_SHIFT                                 3
 #define DDRC_MSTR_LPDDR3_MASK                                  0x00000008U
@@ -3191,9 +3191,9 @@
 * Select LPDDR2 SDRAM - 1 - LPDDR2 SDRAM device in use. - 0 - non-LPDDR2 d
     * evice in use Present only in designs configured to support LPDDR2.
 */
-#undef DDRC_MSTR_LPDDR2_DEFVAL 
-#undef DDRC_MSTR_LPDDR2_SHIFT 
-#undef DDRC_MSTR_LPDDR2_MASK 
+#undef DDRC_MSTR_LPDDR2_DEFVAL
+#undef DDRC_MSTR_LPDDR2_SHIFT
+#undef DDRC_MSTR_LPDDR2_MASK
 #define DDRC_MSTR_LPDDR2_DEFVAL                                0x03040001
 #define DDRC_MSTR_LPDDR2_SHIFT                                 2
 #define DDRC_MSTR_LPDDR2_MASK                                  0x00000004U
@@ -3202,9 +3202,9 @@
 * Select DDR3 SDRAM - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM de
     * vice in use Only present in designs that support DDR3.
 */
-#undef DDRC_MSTR_DDR3_DEFVAL 
-#undef DDRC_MSTR_DDR3_SHIFT 
-#undef DDRC_MSTR_DDR3_MASK 
+#undef DDRC_MSTR_DDR3_DEFVAL
+#undef DDRC_MSTR_DDR3_SHIFT
+#undef DDRC_MSTR_DDR3_MASK
 #define DDRC_MSTR_DDR3_DEFVAL                                  0x03040001
 #define DDRC_MSTR_DDR3_SHIFT                                   0
 #define DDRC_MSTR_DDR3_MASK                                    0x00000001U
@@ -3217,9 +3217,9 @@
     * ommended NOT to set this signal if in Init, Deep power-down or MPSM oper
     * ating modes.
 */
-#undef DDRC_MRCTRL0_MR_WR_DEFVAL 
-#undef DDRC_MRCTRL0_MR_WR_SHIFT 
-#undef DDRC_MRCTRL0_MR_WR_MASK 
+#undef DDRC_MRCTRL0_MR_WR_DEFVAL
+#undef DDRC_MRCTRL0_MR_WR_SHIFT
+#undef DDRC_MRCTRL0_MR_WR_MASK
 #define DDRC_MRCTRL0_MR_WR_DEFVAL                              0x00000030
 #define DDRC_MRCTRL0_MR_WR_SHIFT                               31
 #define DDRC_MRCTRL0_MR_WR_MASK                                0x80000000U
@@ -3236,9 +3236,9 @@
     * oth the Address Mirroring of UDIMMs/RDIMMs and the Output Inversion of R
     * DIMMs.
 */
-#undef DDRC_MRCTRL0_MR_ADDR_DEFVAL 
-#undef DDRC_MRCTRL0_MR_ADDR_SHIFT 
-#undef DDRC_MRCTRL0_MR_ADDR_MASK 
+#undef DDRC_MRCTRL0_MR_ADDR_DEFVAL
+#undef DDRC_MRCTRL0_MR_ADDR_SHIFT
+#undef DDRC_MRCTRL0_MR_ADDR_MASK
 #define DDRC_MRCTRL0_MR_ADDR_DEFVAL                            0x00000030
 #define DDRC_MRCTRL0_MR_ADDR_SHIFT                             12
 #define DDRC_MRCTRL0_MR_ADDR_MASK                              0x0000F000U
@@ -3252,9 +3252,9 @@
     * 5 - select ranks 0 and 2 - 0xA - select ranks 1 and 3 - 0xF - select ran
     * ks 0, 1, 2 and 3
 */
-#undef DDRC_MRCTRL0_MR_RANK_DEFVAL 
-#undef DDRC_MRCTRL0_MR_RANK_SHIFT 
-#undef DDRC_MRCTRL0_MR_RANK_MASK 
+#undef DDRC_MRCTRL0_MR_RANK_DEFVAL
+#undef DDRC_MRCTRL0_MR_RANK_SHIFT
+#undef DDRC_MRCTRL0_MR_RANK_MASK
 #define DDRC_MRCTRL0_MR_RANK_DEFVAL                            0x00000030
 #define DDRC_MRCTRL0_MR_RANK_SHIFT                             4
 #define DDRC_MRCTRL0_MR_RANK_MASK                              0x00000030U
@@ -3269,9 +3269,9 @@
     * RAM initialization routine will not re-start. - 0 - Software interventio
     * n is not allowed - 1 - Software intervention is allowed
 */
-#undef DDRC_MRCTRL0_SW_INIT_INT_DEFVAL 
-#undef DDRC_MRCTRL0_SW_INIT_INT_SHIFT 
-#undef DDRC_MRCTRL0_SW_INIT_INT_MASK 
+#undef DDRC_MRCTRL0_SW_INIT_INT_DEFVAL
+#undef DDRC_MRCTRL0_SW_INIT_INT_SHIFT
+#undef DDRC_MRCTRL0_SW_INIT_INT_MASK
 #define DDRC_MRCTRL0_SW_INIT_INT_DEFVAL                        0x00000030
 #define DDRC_MRCTRL0_SW_INIT_INT_SHIFT                         3
 #define DDRC_MRCTRL0_SW_INIT_INT_MASK                          0x00000008U
@@ -3280,9 +3280,9 @@
 * Indicates whether the mode register operation is MRS in PDA mode or not
     * - 0 - MRS - 1 - MRS in Per DRAM Addressability mode
 */
-#undef DDRC_MRCTRL0_PDA_EN_DEFVAL 
-#undef DDRC_MRCTRL0_PDA_EN_SHIFT 
-#undef DDRC_MRCTRL0_PDA_EN_MASK 
+#undef DDRC_MRCTRL0_PDA_EN_DEFVAL
+#undef DDRC_MRCTRL0_PDA_EN_SHIFT
+#undef DDRC_MRCTRL0_PDA_EN_MASK
 #define DDRC_MRCTRL0_PDA_EN_DEFVAL                             0x00000030
 #define DDRC_MRCTRL0_PDA_EN_SHIFT                              2
 #define DDRC_MRCTRL0_PDA_EN_MASK                               0x00000004U
@@ -3291,9 +3291,9 @@
 * Indicates whether the mode register operation is MRS or WR/RD for MPR (o
     * nly supported for DDR4) - 0 - MRS - 1 - WR/RD for MPR
 */
-#undef DDRC_MRCTRL0_MPR_EN_DEFVAL 
-#undef DDRC_MRCTRL0_MPR_EN_SHIFT 
-#undef DDRC_MRCTRL0_MPR_EN_MASK 
+#undef DDRC_MRCTRL0_MPR_EN_DEFVAL
+#undef DDRC_MRCTRL0_MPR_EN_SHIFT
+#undef DDRC_MRCTRL0_MPR_EN_MASK
 #define DDRC_MRCTRL0_MPR_EN_DEFVAL                             0x00000030
 #define DDRC_MRCTRL0_MPR_EN_SHIFT                              1
 #define DDRC_MRCTRL0_MPR_EN_MASK                               0x00000002U
@@ -3302,9 +3302,9 @@
 * Indicates whether the mode register operation is read or write. Only use
     * d for LPDDR2/LPDDR3/LPDDR4/DDR4. - 0 - Write - 1 - Read
 */
-#undef DDRC_MRCTRL0_MR_TYPE_DEFVAL 
-#undef DDRC_MRCTRL0_MR_TYPE_SHIFT 
-#undef DDRC_MRCTRL0_MR_TYPE_MASK 
+#undef DDRC_MRCTRL0_MR_TYPE_DEFVAL
+#undef DDRC_MRCTRL0_MR_TYPE_SHIFT
+#undef DDRC_MRCTRL0_MR_TYPE_MASK
 #define DDRC_MRCTRL0_MR_TYPE_DEFVAL                            0x00000030
 #define DDRC_MRCTRL0_MR_TYPE_SHIFT                             0
 #define DDRC_MRCTRL0_MR_TYPE_MASK                              0x00000001U
@@ -3316,9 +3316,9 @@
     * erating can be determined by dividing 3.75ns by the core_ddrc_core_clk p
     * eriod, and rounding up the next integer.
 */
-#undef DDRC_DERATEEN_RC_DERATE_VALUE_DEFVAL 
-#undef DDRC_DERATEEN_RC_DERATE_VALUE_SHIFT 
-#undef DDRC_DERATEEN_RC_DERATE_VALUE_MASK 
+#undef DDRC_DERATEEN_RC_DERATE_VALUE_DEFVAL
+#undef DDRC_DERATEEN_RC_DERATE_VALUE_SHIFT
+#undef DDRC_DERATEEN_RC_DERATE_VALUE_MASK
 #define DDRC_DERATEEN_RC_DERATE_VALUE_DEFVAL                   0x00000000
 #define DDRC_DERATEEN_RC_DERATE_VALUE_SHIFT                    8
 #define DDRC_DERATEEN_RC_DERATE_VALUE_MASK                     0x00000300U
@@ -3328,9 +3328,9 @@
     * LPDDR4 Indicates which byte of the MRR data is used for derating. The ma
     * ximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH.
 */
-#undef DDRC_DERATEEN_DERATE_BYTE_DEFVAL 
-#undef DDRC_DERATEEN_DERATE_BYTE_SHIFT 
-#undef DDRC_DERATEEN_DERATE_BYTE_MASK 
+#undef DDRC_DERATEEN_DERATE_BYTE_DEFVAL
+#undef DDRC_DERATEEN_DERATE_BYTE_SHIFT
+#undef DDRC_DERATEEN_DERATE_BYTE_MASK
 #define DDRC_DERATEEN_DERATE_BYTE_DEFVAL                       0x00000000
 #define DDRC_DERATEEN_DERATE_BYTE_SHIFT                        4
 #define DDRC_DERATEEN_DERATE_BYTE_MASK                         0x000000F0U
@@ -3342,9 +3342,9 @@
     * ddrc_core_clk period. Can be 0 or 1 for LPDDR3/LPDDR4, depending if +1.8
     * 75 ns is less than a core_ddrc_core_clk period or not.
 */
-#undef DDRC_DERATEEN_DERATE_VALUE_DEFVAL 
-#undef DDRC_DERATEEN_DERATE_VALUE_SHIFT 
-#undef DDRC_DERATEEN_DERATE_VALUE_MASK 
+#undef DDRC_DERATEEN_DERATE_VALUE_DEFVAL
+#undef DDRC_DERATEEN_DERATE_VALUE_SHIFT
+#undef DDRC_DERATEEN_DERATE_VALUE_MASK
 #define DDRC_DERATEEN_DERATE_VALUE_DEFVAL                      0x00000000
 #define DDRC_DERATEEN_DERATE_VALUE_SHIFT                       1
 #define DDRC_DERATEEN_DERATE_VALUE_MASK                        0x00000002U
@@ -3355,9 +3355,9 @@
     * signs configured to support LPDDR2/LPDDR3/LPDDR4 This field must be set
     * to '0' for non-LPDDR2/LPDDR3/LPDDR4 mode.
 */
-#undef DDRC_DERATEEN_DERATE_ENABLE_DEFVAL 
-#undef DDRC_DERATEEN_DERATE_ENABLE_SHIFT 
-#undef DDRC_DERATEEN_DERATE_ENABLE_MASK 
+#undef DDRC_DERATEEN_DERATE_ENABLE_DEFVAL
+#undef DDRC_DERATEEN_DERATE_ENABLE_SHIFT
+#undef DDRC_DERATEEN_DERATE_ENABLE_MASK
 #define DDRC_DERATEEN_DERATE_ENABLE_DEFVAL                     0x00000000
 #define DDRC_DERATEEN_DERATE_ENABLE_SHIFT                      0
 #define DDRC_DERATEEN_DERATE_ENABLE_MASK                       0x00000001U
@@ -3367,10 +3367,10 @@
     * esent only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This r
     * egister must not be set to zero
 */
-#undef DDRC_DERATEINT_MR4_READ_INTERVAL_DEFVAL 
-#undef DDRC_DERATEINT_MR4_READ_INTERVAL_SHIFT 
-#undef DDRC_DERATEINT_MR4_READ_INTERVAL_MASK 
-#define DDRC_DERATEINT_MR4_READ_INTERVAL_DEFVAL                
+#undef DDRC_DERATEINT_MR4_READ_INTERVAL_DEFVAL
+#undef DDRC_DERATEINT_MR4_READ_INTERVAL_SHIFT
+#undef DDRC_DERATEINT_MR4_READ_INTERVAL_MASK
+#define DDRC_DERATEINT_MR4_READ_INTERVAL_DEFVAL
 #define DDRC_DERATEINT_MR4_READ_INTERVAL_SHIFT                 0
 #define DDRC_DERATEINT_MR4_READ_INTERVAL_MASK                  0xFFFFFFFFU
 
@@ -3381,9 +3381,9 @@
     * ansition from Self refresh state - 0 - Allow transition from Self refres
     * h state
 */
-#undef DDRC_PWRCTL_STAY_IN_SELFREF_DEFVAL 
-#undef DDRC_PWRCTL_STAY_IN_SELFREF_SHIFT 
-#undef DDRC_PWRCTL_STAY_IN_SELFREF_MASK 
+#undef DDRC_PWRCTL_STAY_IN_SELFREF_DEFVAL
+#undef DDRC_PWRCTL_STAY_IN_SELFREF_SHIFT
+#undef DDRC_PWRCTL_STAY_IN_SELFREF_MASK
 #define DDRC_PWRCTL_STAY_IN_SELFREF_DEFVAL                     0x00000000
 #define DDRC_PWRCTL_STAY_IN_SELFREF_SHIFT                      6
 #define DDRC_PWRCTL_STAY_IN_SELFREF_MASK                       0x00000040U
@@ -3394,9 +3394,9 @@
     * This is referred to as Software Entry/Exit to Self Refresh. - 1 - Softwa
     * re Entry to Self Refresh - 0 - Software Exit from Self Refresh
 */
-#undef DDRC_PWRCTL_SELFREF_SW_DEFVAL 
-#undef DDRC_PWRCTL_SELFREF_SW_SHIFT 
-#undef DDRC_PWRCTL_SELFREF_SW_MASK 
+#undef DDRC_PWRCTL_SELFREF_SW_DEFVAL
+#undef DDRC_PWRCTL_SELFREF_SW_SHIFT
+#undef DDRC_PWRCTL_SELFREF_SW_MASK
 #define DDRC_PWRCTL_SELFREF_SW_DEFVAL                          0x00000000
 #define DDRC_PWRCTL_SELFREF_SW_SHIFT                           5
 #define DDRC_PWRCTL_SELFREF_SW_MASK                            0x00000020U
@@ -3410,9 +3410,9 @@
     * the PHY parameter DWC_AC_CS_USE is disabled, as the MPSM exit sequence r
     * equires the chip-select signal to toggle. FOR PERFORMANCE ONLY.
 */
-#undef DDRC_PWRCTL_MPSM_EN_DEFVAL 
-#undef DDRC_PWRCTL_MPSM_EN_SHIFT 
-#undef DDRC_PWRCTL_MPSM_EN_MASK 
+#undef DDRC_PWRCTL_MPSM_EN_DEFVAL
+#undef DDRC_PWRCTL_MPSM_EN_SHIFT
+#undef DDRC_PWRCTL_MPSM_EN_MASK
 #define DDRC_PWRCTL_MPSM_EN_DEFVAL                             0x00000000
 #define DDRC_PWRCTL_MPSM_EN_SHIFT                              4
 #define DDRC_PWRCTL_MPSM_EN_MASK                               0x00000010U
@@ -3428,9 +3428,9 @@
     * rted in following: - in Self Refresh Power Down - in Power Down - during
     *  Normal operation (Clock Stop)
 */
-#undef DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_DEFVAL 
-#undef DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT 
-#undef DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK 
+#undef DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_DEFVAL
+#undef DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT
+#undef DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK
 #define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_DEFVAL             0x00000000
 #define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT              3
 #define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK               0x00000008U
@@ -3443,9 +3443,9 @@
     * red to support mDDR or LPDDR2 or LPDDR3. For non-mDDR/non-LPDDR2/non-LPD
     * DR3, this register should not be set to 1. FOR PERFORMANCE ONLY.
 */
-#undef DDRC_PWRCTL_DEEPPOWERDOWN_EN_DEFVAL 
-#undef DDRC_PWRCTL_DEEPPOWERDOWN_EN_SHIFT 
-#undef DDRC_PWRCTL_DEEPPOWERDOWN_EN_MASK 
+#undef DDRC_PWRCTL_DEEPPOWERDOWN_EN_DEFVAL
+#undef DDRC_PWRCTL_DEEPPOWERDOWN_EN_SHIFT
+#undef DDRC_PWRCTL_DEEPPOWERDOWN_EN_MASK
 #define DDRC_PWRCTL_DEEPPOWERDOWN_EN_DEFVAL                    0x00000000
 #define DDRC_PWRCTL_DEEPPOWERDOWN_EN_SHIFT                     2
 #define DDRC_PWRCTL_DEEPPOWERDOWN_EN_MASK                      0x00000004U
@@ -3456,9 +3456,9 @@
     * x32). This register bit may be re-programmed during the course of normal
     *  operation.
 */
-#undef DDRC_PWRCTL_POWERDOWN_EN_DEFVAL 
-#undef DDRC_PWRCTL_POWERDOWN_EN_SHIFT 
-#undef DDRC_PWRCTL_POWERDOWN_EN_MASK 
+#undef DDRC_PWRCTL_POWERDOWN_EN_DEFVAL
+#undef DDRC_PWRCTL_POWERDOWN_EN_SHIFT
+#undef DDRC_PWRCTL_POWERDOWN_EN_MASK
 #define DDRC_PWRCTL_POWERDOWN_EN_DEFVAL                        0x00000000
 #define DDRC_PWRCTL_POWERDOWN_EN_SHIFT                         1
 #define DDRC_PWRCTL_POWERDOWN_EN_MASK                          0x00000002U
@@ -3469,9 +3469,9 @@
     * selfref_to_x32)'. This register bit may be re-programmed during the cour
     * se of normal operation.
 */
-#undef DDRC_PWRCTL_SELFREF_EN_DEFVAL 
-#undef DDRC_PWRCTL_SELFREF_EN_SHIFT 
-#undef DDRC_PWRCTL_SELFREF_EN_MASK 
+#undef DDRC_PWRCTL_SELFREF_EN_DEFVAL
+#undef DDRC_PWRCTL_SELFREF_EN_SHIFT
+#undef DDRC_PWRCTL_SELFREF_EN_MASK
 #define DDRC_PWRCTL_SELFREF_EN_DEFVAL                          0x00000000
 #define DDRC_PWRCTL_SELFREF_EN_SHIFT                           0
 #define DDRC_PWRCTL_SELFREF_EN_MASK                            0x00000001U
@@ -3481,9 +3481,9 @@
     * the SDRAM into Self Refresh. This must be enabled in the PWRCTL.selfref_
     * en. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY.
 */
-#undef DDRC_PWRTMG_SELFREF_TO_X32_DEFVAL 
-#undef DDRC_PWRTMG_SELFREF_TO_X32_SHIFT 
-#undef DDRC_PWRTMG_SELFREF_TO_X32_MASK 
+#undef DDRC_PWRTMG_SELFREF_TO_X32_DEFVAL
+#undef DDRC_PWRTMG_SELFREF_TO_X32_SHIFT
+#undef DDRC_PWRTMG_SELFREF_TO_X32_MASK
 #define DDRC_PWRTMG_SELFREF_TO_X32_DEFVAL                      0x00402010
 #define DDRC_PWRTMG_SELFREF_TO_X32_SHIFT                       16
 #define DDRC_PWRTMG_SELFREF_TO_X32_MASK                        0x00FF0000U
@@ -3496,9 +3496,9 @@
     * n designs configured to support mDDR, LPDDR2 or LPDDR3. FOR PERFORMANCE
     * ONLY.
 */
-#undef DDRC_PWRTMG_T_DPD_X4096_DEFVAL 
-#undef DDRC_PWRTMG_T_DPD_X4096_SHIFT 
-#undef DDRC_PWRTMG_T_DPD_X4096_MASK 
+#undef DDRC_PWRTMG_T_DPD_X4096_DEFVAL
+#undef DDRC_PWRTMG_T_DPD_X4096_SHIFT
+#undef DDRC_PWRTMG_T_DPD_X4096_MASK
 #define DDRC_PWRTMG_T_DPD_X4096_DEFVAL                         0x00402010
 #define DDRC_PWRTMG_T_DPD_X4096_SHIFT                          8
 #define DDRC_PWRTMG_T_DPD_X4096_MASK                           0x0000FF00U
@@ -3508,9 +3508,9 @@
     * the SDRAM into power-down. This must be enabled in the PWRCTL.powerdown_
     * en. Unit: Multiples of 32 clocks FOR PERFORMANCE ONLY.
 */
-#undef DDRC_PWRTMG_POWERDOWN_TO_X32_DEFVAL 
-#undef DDRC_PWRTMG_POWERDOWN_TO_X32_SHIFT 
-#undef DDRC_PWRTMG_POWERDOWN_TO_X32_MASK 
+#undef DDRC_PWRTMG_POWERDOWN_TO_X32_DEFVAL
+#undef DDRC_PWRTMG_POWERDOWN_TO_X32_SHIFT
+#undef DDRC_PWRTMG_POWERDOWN_TO_X32_MASK
 #define DDRC_PWRTMG_POWERDOWN_TO_X32_DEFVAL                    0x00402010
 #define DDRC_PWRTMG_POWERDOWN_TO_X32_SHIFT                     0
 #define DDRC_PWRTMG_POWERDOWN_TO_X32_MASK                      0x0000001FU
@@ -3526,9 +3526,9 @@
     * om_x32 will be equal to RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 clo
     * cks.
 */
-#undef DDRC_RFSHCTL0_REFRESH_MARGIN_DEFVAL 
-#undef DDRC_RFSHCTL0_REFRESH_MARGIN_SHIFT 
-#undef DDRC_RFSHCTL0_REFRESH_MARGIN_MASK 
+#undef DDRC_RFSHCTL0_REFRESH_MARGIN_DEFVAL
+#undef DDRC_RFSHCTL0_REFRESH_MARGIN_SHIFT
+#undef DDRC_RFSHCTL0_REFRESH_MARGIN_MASK
 #define DDRC_RFSHCTL0_REFRESH_MARGIN_DEFVAL                    0x00210000
 #define DDRC_RFSHCTL0_REFRESH_MARGIN_SHIFT                     20
 #define DDRC_RFSHCTL0_REFRESH_MARGIN_MASK                      0x00F00000U
@@ -3545,9 +3545,9 @@
     * refreshes pending or until new reads or writes are issued to the uMCTL2.
     *  FOR PERFORMANCE ONLY.
 */
-#undef DDRC_RFSHCTL0_REFRESH_TO_X32_DEFVAL 
-#undef DDRC_RFSHCTL0_REFRESH_TO_X32_SHIFT 
-#undef DDRC_RFSHCTL0_REFRESH_TO_X32_MASK 
+#undef DDRC_RFSHCTL0_REFRESH_TO_X32_DEFVAL
+#undef DDRC_RFSHCTL0_REFRESH_TO_X32_SHIFT
+#undef DDRC_RFSHCTL0_REFRESH_TO_X32_MASK
 #define DDRC_RFSHCTL0_REFRESH_TO_X32_DEFVAL                    0x00210000
 #define DDRC_RFSHCTL0_REFRESH_TO_X32_SHIFT                     12
 #define DDRC_RFSHCTL0_REFRESH_TO_X32_MASK                      0x0001F000U
@@ -3572,9 +3572,9 @@
     *  shortly before a refresh burst was due. In this situation, the refresh
     * burst will be delayed until the PHY-initiated update is complete.
 */
-#undef DDRC_RFSHCTL0_REFRESH_BURST_DEFVAL 
-#undef DDRC_RFSHCTL0_REFRESH_BURST_SHIFT 
-#undef DDRC_RFSHCTL0_REFRESH_BURST_MASK 
+#undef DDRC_RFSHCTL0_REFRESH_BURST_DEFVAL
+#undef DDRC_RFSHCTL0_REFRESH_BURST_SHIFT
+#undef DDRC_RFSHCTL0_REFRESH_BURST_MASK
 #define DDRC_RFSHCTL0_REFRESH_BURST_DEFVAL                     0x00210000
 #define DDRC_RFSHCTL0_REFRESH_BURST_SHIFT                      4
 #define DDRC_RFSHCTL0_REFRESH_BURST_MASK                       0x000001F0U
@@ -3585,9 +3585,9 @@
     *  LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. Pr
     * esent only in designs configured to support LPDDR2/LPDDR3/LPDDR4
 */
-#undef DDRC_RFSHCTL0_PER_BANK_REFRESH_DEFVAL 
-#undef DDRC_RFSHCTL0_PER_BANK_REFRESH_SHIFT 
-#undef DDRC_RFSHCTL0_PER_BANK_REFRESH_MASK 
+#undef DDRC_RFSHCTL0_PER_BANK_REFRESH_DEFVAL
+#undef DDRC_RFSHCTL0_PER_BANK_REFRESH_SHIFT
+#undef DDRC_RFSHCTL0_PER_BANK_REFRESH_MASK
 #define DDRC_RFSHCTL0_PER_BANK_REFRESH_DEFVAL                  0x00210000
 #define DDRC_RFSHCTL0_PER_BANK_REFRESH_SHIFT                   2
 #define DDRC_RFSHCTL0_PER_BANK_REFRESH_MASK                    0x00000004U
@@ -3598,9 +3598,9 @@
     *  traffic to proceed. This is explained in Refresh Controls section of ar
     * chitecture chapter. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY.
 */
-#undef DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_DEFVAL 
-#undef DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_SHIFT 
-#undef DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_MASK 
+#undef DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_DEFVAL
+#undef DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_SHIFT
+#undef DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_MASK
 #define DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_DEFVAL    0x00000000
 #define DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_SHIFT     16
 #define DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_MASK      0x0FFF0000U
@@ -3611,9 +3611,9 @@
     *  traffic to proceed. This is explained in Refresh Controls section of ar
     * chitecture chapter. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY.
 */
-#undef DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_DEFVAL 
-#undef DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_SHIFT 
-#undef DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_MASK 
+#undef DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_DEFVAL
+#undef DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_SHIFT
+#undef DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_MASK
 #define DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_DEFVAL    0x00000000
 #define DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_SHIFT     0
 #define DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_MASK      0x00000FFFU
@@ -3628,9 +3628,9 @@
     * on is not allowed. Making this a dynamic register will be supported in f
     * uture version of the uMCTL2.
 */
-#undef DDRC_RFSHCTL3_REFRESH_MODE_DEFVAL 
-#undef DDRC_RFSHCTL3_REFRESH_MODE_SHIFT 
-#undef DDRC_RFSHCTL3_REFRESH_MODE_MASK 
+#undef DDRC_RFSHCTL3_REFRESH_MODE_DEFVAL
+#undef DDRC_RFSHCTL3_REFRESH_MODE_SHIFT
+#undef DDRC_RFSHCTL3_REFRESH_MODE_MASK
 #define DDRC_RFSHCTL3_REFRESH_MODE_DEFVAL                      0x00000000
 #define DDRC_RFSHCTL3_REFRESH_MODE_SHIFT                       4
 #define DDRC_RFSHCTL3_REFRESH_MODE_MASK                        0x00000070U
@@ -3640,9 +3640,9 @@
     * the refresh register(s) have been updated. The value is automatically up
     * dated when exiting reset, so it does not need to be toggled initially.
 */
-#undef DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_DEFVAL 
-#undef DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT 
-#undef DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK 
+#undef DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_DEFVAL
+#undef DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT
+#undef DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK
 #define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_DEFVAL              0x00000000
 #define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT               1
 #define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK                0x00000002U
@@ -3657,9 +3657,9 @@
     * isable auto-refresh is not supported, and this bit must be set to '0'. T
     * his register field is changeable on the fly.
 */
-#undef DDRC_RFSHCTL3_DIS_AUTO_REFRESH_DEFVAL 
-#undef DDRC_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT 
-#undef DDRC_RFSHCTL3_DIS_AUTO_REFRESH_MASK 
+#undef DDRC_RFSHCTL3_DIS_AUTO_REFRESH_DEFVAL
+#undef DDRC_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT
+#undef DDRC_RFSHCTL3_DIS_AUTO_REFRESH_MASK
 #define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_DEFVAL                  0x00000000
 #define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT                   0
 #define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_MASK                    0x00000001U
@@ -3678,9 +3678,9 @@
     * ter than RFSHTMG.t_rfc_min, and RFSHTMG.t_rfc_nom_x32 must be greater th
     * an 0x1. Unit: Multiples of 32 clocks.
 */
-#undef DDRC_RFSHTMG_T_RFC_NOM_X32_DEFVAL 
-#undef DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT 
-#undef DDRC_RFSHTMG_T_RFC_NOM_X32_MASK 
+#undef DDRC_RFSHTMG_T_RFC_NOM_X32_DEFVAL
+#undef DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT
+#undef DDRC_RFSHTMG_T_RFC_NOM_X32_MASK
 #define DDRC_RFSHTMG_T_RFC_NOM_X32_DEFVAL                      0x0062008C
 #define DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT                       16
 #define DDRC_RFSHTMG_T_RFC_NOM_X32_MASK                        0x0FFF0000U
@@ -3692,9 +3692,9 @@
     *  LPDDR3 JEDEC specification) or not: - 0 - tREFBW parameter not used - 1
     *  - tREFBW parameter used
 */
-#undef DDRC_RFSHTMG_LPDDR3_TREFBW_EN_DEFVAL 
-#undef DDRC_RFSHTMG_LPDDR3_TREFBW_EN_SHIFT 
-#undef DDRC_RFSHTMG_LPDDR3_TREFBW_EN_MASK 
+#undef DDRC_RFSHTMG_LPDDR3_TREFBW_EN_DEFVAL
+#undef DDRC_RFSHTMG_LPDDR3_TREFBW_EN_SHIFT
+#undef DDRC_RFSHTMG_LPDDR3_TREFBW_EN_MASK
 #define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_DEFVAL                   0x0062008C
 #define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_SHIFT                    15
 #define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_MASK                     0x00008000U
@@ -3712,9 +3712,9 @@
     *  the spec based on the 'refresh_mode' and the device density that is use
     * d. Unit: Clocks.
 */
-#undef DDRC_RFSHTMG_T_RFC_MIN_DEFVAL 
-#undef DDRC_RFSHTMG_T_RFC_MIN_SHIFT 
-#undef DDRC_RFSHTMG_T_RFC_MIN_MASK 
+#undef DDRC_RFSHTMG_T_RFC_MIN_DEFVAL
+#undef DDRC_RFSHTMG_T_RFC_MIN_SHIFT
+#undef DDRC_RFSHTMG_T_RFC_MIN_MASK
 #define DDRC_RFSHTMG_T_RFC_MIN_DEFVAL                          0x0062008C
 #define DDRC_RFSHTMG_T_RFC_MIN_SHIFT                           0
 #define DDRC_RFSHTMG_T_RFC_MIN_MASK                            0x000003FFU
@@ -3723,9 +3723,9 @@
 * Disable ECC scrubs. Valid only when ECCCFG0.ecc_mode = 3'b100 and MEMC_U
     * SE_RMW is defined
 */
-#undef DDRC_ECCCFG0_DIS_SCRUB_DEFVAL 
-#undef DDRC_ECCCFG0_DIS_SCRUB_SHIFT 
-#undef DDRC_ECCCFG0_DIS_SCRUB_MASK 
+#undef DDRC_ECCCFG0_DIS_SCRUB_DEFVAL
+#undef DDRC_ECCCFG0_DIS_SCRUB_SHIFT
+#undef DDRC_ECCCFG0_DIS_SCRUB_MASK
 #define DDRC_ECCCFG0_DIS_SCRUB_DEFVAL                          0x00000000
 #define DDRC_ECCCFG0_DIS_SCRUB_SHIFT                           4
 #define DDRC_ECCCFG0_DIS_SCRUB_MASK                            0x00000010U
@@ -3734,9 +3734,9 @@
 * ECC mode indicator - 000 - ECC disabled - 100 - ECC enabled - SEC/DED ov
     * er 1 beat - all other settings are reserved for future use
 */
-#undef DDRC_ECCCFG0_ECC_MODE_DEFVAL 
-#undef DDRC_ECCCFG0_ECC_MODE_SHIFT 
-#undef DDRC_ECCCFG0_ECC_MODE_MASK 
+#undef DDRC_ECCCFG0_ECC_MODE_DEFVAL
+#undef DDRC_ECCCFG0_ECC_MODE_SHIFT
+#undef DDRC_ECCCFG0_ECC_MODE_MASK
 #define DDRC_ECCCFG0_ECC_MODE_DEFVAL                           0x00000000
 #define DDRC_ECCCFG0_ECC_MODE_SHIFT                            0
 #define DDRC_ECCCFG0_ECC_MODE_MASK                             0x00000007U
@@ -3746,9 +3746,9 @@
     * ta poisoning, if 1 -> 1-bit (correctable) data poisoning, if ECCCFG1.dat
     * a_poison_en=1
 */
-#undef DDRC_ECCCFG1_DATA_POISON_BIT_DEFVAL 
-#undef DDRC_ECCCFG1_DATA_POISON_BIT_SHIFT 
-#undef DDRC_ECCCFG1_DATA_POISON_BIT_MASK 
+#undef DDRC_ECCCFG1_DATA_POISON_BIT_DEFVAL
+#undef DDRC_ECCCFG1_DATA_POISON_BIT_SHIFT
+#undef DDRC_ECCCFG1_DATA_POISON_BIT_MASK
 #define DDRC_ECCCFG1_DATA_POISON_BIT_DEFVAL                    0x00000000
 #define DDRC_ECCCFG1_DATA_POISON_BIT_SHIFT                     1
 #define DDRC_ECCCFG1_DATA_POISON_BIT_MASK                      0x00000002U
@@ -3757,9 +3757,9 @@
 * Enable ECC data poisoning - introduces ECC errors on writes to address s
     * pecified by the ECCPOISONADDR0/1 registers
 */
-#undef DDRC_ECCCFG1_DATA_POISON_EN_DEFVAL 
-#undef DDRC_ECCCFG1_DATA_POISON_EN_SHIFT 
-#undef DDRC_ECCCFG1_DATA_POISON_EN_MASK 
+#undef DDRC_ECCCFG1_DATA_POISON_EN_DEFVAL
+#undef DDRC_ECCCFG1_DATA_POISON_EN_SHIFT
+#undef DDRC_ECCCFG1_DATA_POISON_EN_MASK
 #define DDRC_ECCCFG1_DATA_POISON_EN_DEFVAL                     0x00000000
 #define DDRC_ECCCFG1_DATA_POISON_EN_SHIFT                      0
 #define DDRC_ECCCFG1_DATA_POISON_EN_MASK                       0x00000001U
@@ -3777,9 +3777,9 @@
     * fi_rddata_use_sdr == 0 : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_
     * rdlat < 'd114 Unit: DFI Clocks
 */
-#undef DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_DEFVAL 
-#undef DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_SHIFT 
-#undef DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_MASK 
+#undef DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_DEFVAL
+#undef DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_SHIFT
+#undef DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_MASK
 #define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_DEFVAL                 0x10000200
 #define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_SHIFT                  24
 #define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_MASK                   0x3F000000U
@@ -3805,9 +3805,9 @@
     * R5[4] is cleared, the error log in MPR Page 1 should be treated as 'Don'
     * t care'.
 */
-#undef DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_DEFVAL 
-#undef DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_SHIFT 
-#undef DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_MASK 
+#undef DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_DEFVAL
+#undef DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_SHIFT
+#undef DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_MASK
 #define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_DEFVAL               0x10000200
 #define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_SHIFT                9
 #define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_MASK                 0x00000200U
@@ -3819,9 +3819,9 @@
     *  enabled (MSTR.burstchop = 1) and/or disable auto-refresh is enabled (RF
     * SHCTL3.dis_auto_refresh = 1)
 */
-#undef DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_DEFVAL 
-#undef DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_SHIFT 
-#undef DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_MASK 
+#undef DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_DEFVAL
+#undef DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_SHIFT
+#undef DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_MASK
 #define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_DEFVAL         0x10000200
 #define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_SHIFT          8
 #define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_MASK           0x00000100U
@@ -3830,9 +3830,9 @@
 * CRC Calculation setting register - 1: CRC includes DM signal - 0: CRC no
     * t includes DM signal Present only in designs configured to support DDR4.
 */
-#undef DDRC_CRCPARCTL1_CRC_INC_DM_DEFVAL 
-#undef DDRC_CRCPARCTL1_CRC_INC_DM_SHIFT 
-#undef DDRC_CRCPARCTL1_CRC_INC_DM_MASK 
+#undef DDRC_CRCPARCTL1_CRC_INC_DM_DEFVAL
+#undef DDRC_CRCPARCTL1_CRC_INC_DM_SHIFT
+#undef DDRC_CRCPARCTL1_CRC_INC_DM_MASK
 #define DDRC_CRCPARCTL1_CRC_INC_DM_DEFVAL                      0x10000200
 #define DDRC_CRCPARCTL1_CRC_INC_DM_SHIFT                       7
 #define DDRC_CRCPARCTL1_CRC_INC_DM_MASK                        0x00000080U
@@ -3842,9 +3842,9 @@
     * n of CRC The setting of this register should match the CRC mode register
     *  setting in the DRAM.
 */
-#undef DDRC_CRCPARCTL1_CRC_ENABLE_DEFVAL 
-#undef DDRC_CRCPARCTL1_CRC_ENABLE_SHIFT 
-#undef DDRC_CRCPARCTL1_CRC_ENABLE_MASK 
+#undef DDRC_CRCPARCTL1_CRC_ENABLE_DEFVAL
+#undef DDRC_CRCPARCTL1_CRC_ENABLE_SHIFT
+#undef DDRC_CRCPARCTL1_CRC_ENABLE_MASK
 #define DDRC_CRCPARCTL1_CRC_ENABLE_DEFVAL                      0x10000200
 #define DDRC_CRCPARCTL1_CRC_ENABLE_SHIFT                       4
 #define DDRC_CRCPARCTL1_CRC_ENABLE_MASK                        0x00000010U
@@ -3855,9 +3855,9 @@
     * ble detection of C/A parity error If RCD's parity error detection or SDR
     * AM's parity detection is enabled, this register should be 1.
 */
-#undef DDRC_CRCPARCTL1_PARITY_ENABLE_DEFVAL 
-#undef DDRC_CRCPARCTL1_PARITY_ENABLE_SHIFT 
-#undef DDRC_CRCPARCTL1_PARITY_ENABLE_MASK 
+#undef DDRC_CRCPARCTL1_PARITY_ENABLE_DEFVAL
+#undef DDRC_CRCPARCTL1_PARITY_ENABLE_SHIFT
+#undef DDRC_CRCPARCTL1_PARITY_ENABLE_MASK
 #define DDRC_CRCPARCTL1_PARITY_ENABLE_DEFVAL                   0x10000200
 #define DDRC_CRCPARCTL1_PARITY_ENABLE_SHIFT                    0
 #define DDRC_CRCPARCTL1_PARITY_ENABLE_MASK                     0x00000001U
@@ -3869,9 +3869,9 @@
     * _PW.MAX/2 and round up to next integer value. Values of 0, 1 and 2 are i
     * llegal. This value must be greater than CRCPARCTL2.t_crc_alert_pw_max.
 */
-#undef DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_DEFVAL 
-#undef DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_SHIFT 
-#undef DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_MASK 
+#undef DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_DEFVAL
+#undef DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_SHIFT
+#undef DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_MASK
 #define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_DEFVAL              0x0030050C
 #define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_SHIFT               16
 #define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_MASK                0x01FF0000U
@@ -3883,9 +3883,9 @@
     * .MAX/2 and round up to next integer value. Values of 0, 1 and 2 are ille
     * gal. This value must be less than CRCPARCTL2.t_par_alert_pw_max.
 */
-#undef DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_DEFVAL 
-#undef DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_SHIFT 
-#undef DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_MASK 
+#undef DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_DEFVAL
+#undef DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_SHIFT
+#undef DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_MASK
 #define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_DEFVAL              0x0030050C
 #define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_SHIFT               8
 #define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_MASK                0x00001F00U
@@ -3925,9 +3925,9 @@
     * x value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Values of 0, 1 and 2 are illegal
     * .
 */
-#undef DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_DEFVAL 
-#undef DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_SHIFT 
-#undef DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_MASK 
+#undef DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_DEFVAL
+#undef DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_SHIFT
+#undef DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_MASK
 #define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_DEFVAL    0x0030050C
 #define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_SHIFT     0
 #define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_MASK      0x0000003FU
@@ -3942,9 +3942,9 @@
     * ation routine is run after power-up. Note: The only 2'b00 is supported f
     * or LPDDR4 in this version of the uMCTL2.
 */
-#undef DDRC_INIT0_SKIP_DRAM_INIT_DEFVAL 
-#undef DDRC_INIT0_SKIP_DRAM_INIT_SHIFT 
-#undef DDRC_INIT0_SKIP_DRAM_INIT_MASK 
+#undef DDRC_INIT0_SKIP_DRAM_INIT_DEFVAL
+#undef DDRC_INIT0_SKIP_DRAM_INIT_SHIFT
+#undef DDRC_INIT0_SKIP_DRAM_INIT_MASK
 #define DDRC_INIT0_SKIP_DRAM_INIT_DEFVAL                       0x0002004E
 #define DDRC_INIT0_SKIP_DRAM_INIT_SHIFT                        30
 #define DDRC_INIT0_SKIP_DRAM_INIT_MASK                         0xC0000000U
@@ -3958,9 +3958,9 @@
     * igurations with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divi
     * ded by 2, and round it up to next integer value.
 */
-#undef DDRC_INIT0_POST_CKE_X1024_DEFVAL 
-#undef DDRC_INIT0_POST_CKE_X1024_SHIFT 
-#undef DDRC_INIT0_POST_CKE_X1024_MASK 
+#undef DDRC_INIT0_POST_CKE_X1024_DEFVAL
+#undef DDRC_INIT0_POST_CKE_X1024_SHIFT
+#undef DDRC_INIT0_POST_CKE_X1024_MASK
 #define DDRC_INIT0_POST_CKE_X1024_DEFVAL                       0x0002004E
 #define DDRC_INIT0_POST_CKE_X1024_SHIFT                        16
 #define DDRC_INIT0_POST_CKE_X1024_MASK                         0x03FF0000U
@@ -3973,9 +3973,9 @@
     * ons with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divided by
     * 2, and round it up to next integer value.
 */
-#undef DDRC_INIT0_PRE_CKE_X1024_DEFVAL 
-#undef DDRC_INIT0_PRE_CKE_X1024_SHIFT 
-#undef DDRC_INIT0_PRE_CKE_X1024_MASK 
+#undef DDRC_INIT0_PRE_CKE_X1024_DEFVAL
+#undef DDRC_INIT0_PRE_CKE_X1024_SHIFT
+#undef DDRC_INIT0_PRE_CKE_X1024_MASK
 #define DDRC_INIT0_PRE_CKE_X1024_DEFVAL                        0x0002004E
 #define DDRC_INIT0_PRE_CKE_X1024_SHIFT                         0
 #define DDRC_INIT0_PRE_CKE_X1024_MASK                          0x00000FFFU
@@ -3985,9 +3985,9 @@
     *  is only present for designs supporting DDR3, DDR4 or LPDDR4 devices. Fo
     * r use with a DDR PHY, this should be set to a minimum of 1
 */
-#undef DDRC_INIT1_DRAM_RSTN_X1024_DEFVAL 
-#undef DDRC_INIT1_DRAM_RSTN_X1024_SHIFT 
-#undef DDRC_INIT1_DRAM_RSTN_X1024_MASK 
+#undef DDRC_INIT1_DRAM_RSTN_X1024_DEFVAL
+#undef DDRC_INIT1_DRAM_RSTN_X1024_SHIFT
+#undef DDRC_INIT1_DRAM_RSTN_X1024_MASK
 #define DDRC_INIT1_DRAM_RSTN_X1024_DEFVAL                      0x00000000
 #define DDRC_INIT1_DRAM_RSTN_X1024_SHIFT                       16
 #define DDRC_INIT1_DRAM_RSTN_X1024_MASK                        0x01FF0000U
@@ -3998,9 +3998,9 @@
     * ses every 32 clock cycles. There is no known specific requirement for th
     * is; it may be set to zero.
 */
-#undef DDRC_INIT1_FINAL_WAIT_X32_DEFVAL 
-#undef DDRC_INIT1_FINAL_WAIT_X32_SHIFT 
-#undef DDRC_INIT1_FINAL_WAIT_X32_MASK 
+#undef DDRC_INIT1_FINAL_WAIT_X32_DEFVAL
+#undef DDRC_INIT1_FINAL_WAIT_X32_SHIFT
+#undef DDRC_INIT1_FINAL_WAIT_X32_MASK
 #define DDRC_INIT1_FINAL_WAIT_X32_DEFVAL                       0x00000000
 #define DDRC_INIT1_FINAL_WAIT_X32_SHIFT                        8
 #define DDRC_INIT1_FINAL_WAIT_X32_MASK                         0x00007F00U
@@ -4010,9 +4010,9 @@
     * ts of a global timer that pulses every 32 clock cycles. There is no know
     * n specific requirement for this; it may be set to zero.
 */
-#undef DDRC_INIT1_PRE_OCD_X32_DEFVAL 
-#undef DDRC_INIT1_PRE_OCD_X32_SHIFT 
-#undef DDRC_INIT1_PRE_OCD_X32_MASK 
+#undef DDRC_INIT1_PRE_OCD_X32_DEFVAL
+#undef DDRC_INIT1_PRE_OCD_X32_SHIFT
+#undef DDRC_INIT1_PRE_OCD_X32_MASK
 #define DDRC_INIT1_PRE_OCD_X32_DEFVAL                          0x00000000
 #define DDRC_INIT1_PRE_OCD_X32_SHIFT                           0
 #define DDRC_INIT1_PRE_OCD_X32_MASK                            0x0000000FU
@@ -4021,9 +4021,9 @@
 * Idle time after the reset command, tINIT4. Present only in designs confi
     * gured to support LPDDR2. Unit: 32 clock cycles.
 */
-#undef DDRC_INIT2_IDLE_AFTER_RESET_X32_DEFVAL 
-#undef DDRC_INIT2_IDLE_AFTER_RESET_X32_SHIFT 
-#undef DDRC_INIT2_IDLE_AFTER_RESET_X32_MASK 
+#undef DDRC_INIT2_IDLE_AFTER_RESET_X32_DEFVAL
+#undef DDRC_INIT2_IDLE_AFTER_RESET_X32_SHIFT
+#undef DDRC_INIT2_IDLE_AFTER_RESET_X32_MASK
 #define DDRC_INIT2_IDLE_AFTER_RESET_X32_DEFVAL                 0x00000D05
 #define DDRC_INIT2_IDLE_AFTER_RESET_X32_SHIFT                  8
 #define DDRC_INIT2_IDLE_AFTER_RESET_X32_MASK                   0x0000FF00U
@@ -4033,9 +4033,9 @@
     * onfigured to support LPDDR2/LPDDR3. Unit: 1 clock cycle. LPDDR2/LPDDR3 t
     * ypically requires 5 x tCK delay.
 */
-#undef DDRC_INIT2_MIN_STABLE_CLOCK_X1_DEFVAL 
-#undef DDRC_INIT2_MIN_STABLE_CLOCK_X1_SHIFT 
-#undef DDRC_INIT2_MIN_STABLE_CLOCK_X1_MASK 
+#undef DDRC_INIT2_MIN_STABLE_CLOCK_X1_DEFVAL
+#undef DDRC_INIT2_MIN_STABLE_CLOCK_X1_SHIFT
+#undef DDRC_INIT2_MIN_STABLE_CLOCK_X1_MASK
 #define DDRC_INIT2_MIN_STABLE_CLOCK_X1_DEFVAL                  0x00000D05
 #define DDRC_INIT2_MIN_STABLE_CLOCK_X1_SHIFT                   0
 #define DDRC_INIT2_MIN_STABLE_CLOCK_X1_MASK                    0x0000000FU
@@ -4046,9 +4046,9 @@
     * loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LP
     * DDR3/LPDDR4 - Value to write to MR1 register
 */
-#undef DDRC_INIT3_MR_DEFVAL 
-#undef DDRC_INIT3_MR_SHIFT 
-#undef DDRC_INIT3_MR_MASK 
+#undef DDRC_INIT3_MR_DEFVAL
+#undef DDRC_INIT3_MR_SHIFT
+#undef DDRC_INIT3_MR_MASK
 #define DDRC_INIT3_MR_DEFVAL                                   0x00000510
 #define DDRC_INIT3_MR_SHIFT                                    16
 #define DDRC_INIT3_MR_MASK                                     0xFFFF0000U
@@ -4061,9 +4061,9 @@
     * TL2 during write leveling. mDDR: Value to write to EMR register. LPDDR2/
     * LPDDR3/LPDDR4 - Value to write to MR2 register
 */
-#undef DDRC_INIT3_EMR_DEFVAL 
-#undef DDRC_INIT3_EMR_SHIFT 
-#undef DDRC_INIT3_EMR_MASK 
+#undef DDRC_INIT3_EMR_DEFVAL
+#undef DDRC_INIT3_EMR_SHIFT
+#undef DDRC_INIT3_EMR_MASK
 #define DDRC_INIT3_EMR_DEFVAL                                  0x00000510
 #define DDRC_INIT3_EMR_SHIFT                                   0
 #define DDRC_INIT3_EMR_MASK                                    0x0000FFFFU
@@ -4073,9 +4073,9 @@
     * register LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 register mDDR: Unus
     * ed
 */
-#undef DDRC_INIT4_EMR2_DEFVAL 
-#undef DDRC_INIT4_EMR2_SHIFT 
-#undef DDRC_INIT4_EMR2_MASK 
+#undef DDRC_INIT4_EMR2_DEFVAL
+#undef DDRC_INIT4_EMR2_SHIFT
+#undef DDRC_INIT4_EMR2_MASK
 #define DDRC_INIT4_EMR2_DEFVAL                                 0x00000000
 #define DDRC_INIT4_EMR2_SHIFT                                  16
 #define DDRC_INIT4_EMR2_MASK                                   0xFFFF0000U
@@ -4085,9 +4085,9 @@
     * register mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to write to MR13 regis
     * ter
 */
-#undef DDRC_INIT4_EMR3_DEFVAL 
-#undef DDRC_INIT4_EMR3_SHIFT 
-#undef DDRC_INIT4_EMR3_MASK 
+#undef DDRC_INIT4_EMR3_DEFVAL
+#undef DDRC_INIT4_EMR3_SHIFT
+#undef DDRC_INIT4_EMR3_MASK
 #define DDRC_INIT4_EMR3_DEFVAL                                 0x00000000
 #define DDRC_INIT4_EMR3_SHIFT                                  0
 #define DDRC_INIT4_EMR3_MASK                                   0x0000FFFFU
@@ -4098,9 +4098,9 @@
     * lly requires 512 clocks. DDR4 requires 1024 clocks. LPDDR2/LPDDR3 requir
     * es 1 us.
 */
-#undef DDRC_INIT5_DEV_ZQINIT_X32_DEFVAL 
-#undef DDRC_INIT5_DEV_ZQINIT_X32_SHIFT 
-#undef DDRC_INIT5_DEV_ZQINIT_X32_MASK 
+#undef DDRC_INIT5_DEV_ZQINIT_X32_DEFVAL
+#undef DDRC_INIT5_DEV_ZQINIT_X32_SHIFT
+#undef DDRC_INIT5_DEV_ZQINIT_X32_MASK
 #define DDRC_INIT5_DEV_ZQINIT_X32_DEFVAL                       0x00100004
 #define DDRC_INIT5_DEV_ZQINIT_X32_SHIFT                        16
 #define DDRC_INIT5_DEV_ZQINIT_X32_MASK                         0x00FF0000U
@@ -4110,9 +4110,9 @@
     * igns configured to support LPDDR2/LPDDR3. LPDDR2/LPDDR3 typically requir
     * es 10 us.
 */
-#undef DDRC_INIT5_MAX_AUTO_INIT_X1024_DEFVAL 
-#undef DDRC_INIT5_MAX_AUTO_INIT_X1024_SHIFT 
-#undef DDRC_INIT5_MAX_AUTO_INIT_X1024_MASK 
+#undef DDRC_INIT5_MAX_AUTO_INIT_X1024_DEFVAL
+#undef DDRC_INIT5_MAX_AUTO_INIT_X1024_SHIFT
+#undef DDRC_INIT5_MAX_AUTO_INIT_X1024_MASK
 #define DDRC_INIT5_MAX_AUTO_INIT_X1024_DEFVAL                  0x00100004
 #define DDRC_INIT5_MAX_AUTO_INIT_X1024_SHIFT                   0
 #define DDRC_INIT5_MAX_AUTO_INIT_X1024_MASK                    0x000003FFU
@@ -4121,9 +4121,9 @@
 * DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs
     * only.
 */
-#undef DDRC_INIT6_MR4_DEFVAL 
-#undef DDRC_INIT6_MR4_SHIFT 
-#undef DDRC_INIT6_MR4_MASK 
+#undef DDRC_INIT6_MR4_DEFVAL
+#undef DDRC_INIT6_MR4_SHIFT
+#undef DDRC_INIT6_MR4_MASK
 #define DDRC_INIT6_MR4_DEFVAL                                  0x00000000
 #define DDRC_INIT6_MR4_SHIFT                                   16
 #define DDRC_INIT6_MR4_MASK                                    0xFFFF0000U
@@ -4132,9 +4132,9 @@
 * DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs
     * only.
 */
-#undef DDRC_INIT6_MR5_DEFVAL 
-#undef DDRC_INIT6_MR5_SHIFT 
-#undef DDRC_INIT6_MR5_MASK 
+#undef DDRC_INIT6_MR5_DEFVAL
+#undef DDRC_INIT6_MR5_SHIFT
+#undef DDRC_INIT6_MR5_MASK
 #define DDRC_INIT6_MR5_DEFVAL                                  0x00000000
 #define DDRC_INIT6_MR5_SHIFT                                   0
 #define DDRC_INIT6_MR5_MASK                                    0x0000FFFFU
@@ -4143,10 +4143,10 @@
 * DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs
     * only.
 */
-#undef DDRC_INIT7_MR6_DEFVAL 
-#undef DDRC_INIT7_MR6_SHIFT 
-#undef DDRC_INIT7_MR6_MASK 
-#define DDRC_INIT7_MR6_DEFVAL                                  
+#undef DDRC_INIT7_MR6_DEFVAL
+#undef DDRC_INIT7_MR6_SHIFT
+#undef DDRC_INIT7_MR6_MASK
+#define DDRC_INIT7_MR6_DEFVAL
 #define DDRC_INIT7_MR6_SHIFT                                   16
 #define DDRC_INIT7_MR6_MASK                                    0xFFFF0000U
 
@@ -4156,9 +4156,9 @@
     * equired for DDR4 DIMMs with x16 devices. - 1 - BG0 and BG1 are NOT swapp
     * ed. - 0 - BG0 and BG1 are swapped if address mirroring is enabled.
 */
-#undef DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_DEFVAL 
-#undef DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_SHIFT 
-#undef DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_MASK 
+#undef DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_DEFVAL
+#undef DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_SHIFT
+#undef DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_MASK
 #define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_DEFVAL              0x00000000
 #define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_SHIFT               5
 #define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_MASK                0x00000020U
@@ -4174,9 +4174,9 @@
     * led, this is applied to BG1 of even ranks and BG0 of odd ranks. - 1 - En
     * abled - 0 - Disabled
 */
-#undef DDRC_DIMMCTL_MRS_BG1_EN_DEFVAL 
-#undef DDRC_DIMMCTL_MRS_BG1_EN_SHIFT 
-#undef DDRC_DIMMCTL_MRS_BG1_EN_MASK 
+#undef DDRC_DIMMCTL_MRS_BG1_EN_DEFVAL
+#undef DDRC_DIMMCTL_MRS_BG1_EN_SHIFT
+#undef DDRC_DIMMCTL_MRS_BG1_EN_MASK
 #define DDRC_DIMMCTL_MRS_BG1_EN_DEFVAL                         0x00000000
 #define DDRC_DIMMCTL_MRS_BG1_EN_SHIFT                          4
 #define DDRC_DIMMCTL_MRS_BG1_EN_MASK                           0x00000010U
@@ -4190,9 +4190,9 @@
     * t on the address of any other memory accesses, or of software-driven mod
     * e register accesses. - 1 - Enabled - 0 - Disabled
 */
-#undef DDRC_DIMMCTL_MRS_A17_EN_DEFVAL 
-#undef DDRC_DIMMCTL_MRS_A17_EN_SHIFT 
-#undef DDRC_DIMMCTL_MRS_A17_EN_MASK 
+#undef DDRC_DIMMCTL_MRS_A17_EN_DEFVAL
+#undef DDRC_DIMMCTL_MRS_A17_EN_SHIFT
+#undef DDRC_DIMMCTL_MRS_A17_EN_MASK
 #define DDRC_DIMMCTL_MRS_A17_EN_DEFVAL                         0x00000000
 #define DDRC_DIMMCTL_MRS_A17_EN_SHIFT                          3
 #define DDRC_DIMMCTL_MRS_A17_EN_MASK                           0x00000008U
@@ -4211,9 +4211,9 @@
     * ister accesses. - 1 - Implement output inversion for B-side DRAMs. - 0 -
     *  Do not implement output inversion for B-side DRAMs.
 */
-#undef DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_DEFVAL 
-#undef DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_SHIFT 
-#undef DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_MASK 
+#undef DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_DEFVAL
+#undef DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_SHIFT
+#undef DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_MASK
 #define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_DEFVAL                 0x00000000
 #define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_SHIFT                  2
 #define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_MASK                   0x00000004U
@@ -4238,9 +4238,9 @@
     * n and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM imp
     * lements address mirroring) - 0 - Do not implement address mirroring
 */
-#undef DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_DEFVAL 
-#undef DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT 
-#undef DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK 
+#undef DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_DEFVAL
+#undef DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT
+#undef DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK
 #define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_DEFVAL                  0x00000000
 #define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT                   1
 #define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK                    0x00000002U
@@ -4254,9 +4254,9 @@
     * nd MRS commands to each ranks seperately - 1 - (non-DDR4) Send all comma
     * nds to even and odd ranks seperately - 0 - Do not stagger accesses
 */
-#undef DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_DEFVAL 
-#undef DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT 
-#undef DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_MASK 
+#undef DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_DEFVAL
+#undef DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT
+#undef DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_MASK
 #define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_DEFVAL                 0x00000000
 #define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT                  0
 #define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_MASK                   0x00000001U
@@ -4278,9 +4278,9 @@
     * RATIO=2, program this to the larger value divided by two and round it up
     *  to the next integer.
 */
-#undef DDRC_RANKCTL_DIFF_RANK_WR_GAP_DEFVAL 
-#undef DDRC_RANKCTL_DIFF_RANK_WR_GAP_SHIFT 
-#undef DDRC_RANKCTL_DIFF_RANK_WR_GAP_MASK 
+#undef DDRC_RANKCTL_DIFF_RANK_WR_GAP_DEFVAL
+#undef DDRC_RANKCTL_DIFF_RANK_WR_GAP_SHIFT
+#undef DDRC_RANKCTL_DIFF_RANK_WR_GAP_MASK
 #define DDRC_RANKCTL_DIFF_RANK_WR_GAP_DEFVAL                   0x0000066F
 #define DDRC_RANKCTL_DIFF_RANK_WR_GAP_SHIFT                    8
 #define DDRC_RANKCTL_DIFF_RANK_WR_GAP_MASK                     0x00000F00U
@@ -4300,9 +4300,9 @@
     * nfigurations with MEMC_FREQ_RATIO=2, program this to the larger value di
     * vided by two and round it up to the next integer.
 */
-#undef DDRC_RANKCTL_DIFF_RANK_RD_GAP_DEFVAL 
-#undef DDRC_RANKCTL_DIFF_RANK_RD_GAP_SHIFT 
-#undef DDRC_RANKCTL_DIFF_RANK_RD_GAP_MASK 
+#undef DDRC_RANKCTL_DIFF_RANK_RD_GAP_DEFVAL
+#undef DDRC_RANKCTL_DIFF_RANK_RD_GAP_SHIFT
+#undef DDRC_RANKCTL_DIFF_RANK_RD_GAP_MASK
 #define DDRC_RANKCTL_DIFF_RANK_RD_GAP_DEFVAL                   0x0000066F
 #define DDRC_RANKCTL_DIFF_RANK_RD_GAP_SHIFT                    4
 #define DDRC_RANKCTL_DIFF_RANK_RD_GAP_MASK                     0x000000F0U
@@ -4327,9 +4327,9 @@
     * e available for it. Minimum programmable value is 0 (feature disabled) a
     * nd maximum programmable value is 0xF. FOR PERFORMANCE ONLY.
 */
-#undef DDRC_RANKCTL_MAX_RANK_RD_DEFVAL 
-#undef DDRC_RANKCTL_MAX_RANK_RD_SHIFT 
-#undef DDRC_RANKCTL_MAX_RANK_RD_MASK 
+#undef DDRC_RANKCTL_MAX_RANK_RD_DEFVAL
+#undef DDRC_RANKCTL_MAX_RANK_RD_SHIFT
+#undef DDRC_RANKCTL_MAX_RANK_RD_MASK
 #define DDRC_RANKCTL_MAX_RANK_RD_DEFVAL                        0x0000066F
 #define DDRC_RANKCTL_MAX_RANK_RD_SHIFT                         0
 #define DDRC_RANKCTL_MAX_RANK_RD_MASK                          0x0000000FU
@@ -4347,9 +4347,9 @@
     * IO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it u
     * p to the next integer value.
 */
-#undef DDRC_DRAMTMG0_WR2PRE_DEFVAL 
-#undef DDRC_DRAMTMG0_WR2PRE_SHIFT 
-#undef DDRC_DRAMTMG0_WR2PRE_MASK 
+#undef DDRC_DRAMTMG0_WR2PRE_DEFVAL
+#undef DDRC_DRAMTMG0_WR2PRE_SHIFT
+#undef DDRC_DRAMTMG0_WR2PRE_MASK
 #define DDRC_DRAMTMG0_WR2PRE_DEFVAL                            0x0F101B0F
 #define DDRC_DRAMTMG0_WR2PRE_SHIFT                             24
 #define DDRC_DRAMTMG0_WR2PRE_MASK                              0x7F000000U
@@ -4362,9 +4362,9 @@
     * t this register to 0x1 independent of the MEMC_FREQ_RATIO configuration.
     *  Unit: Clocks
 */
-#undef DDRC_DRAMTMG0_T_FAW_DEFVAL 
-#undef DDRC_DRAMTMG0_T_FAW_SHIFT 
-#undef DDRC_DRAMTMG0_T_FAW_MASK 
+#undef DDRC_DRAMTMG0_T_FAW_DEFVAL
+#undef DDRC_DRAMTMG0_T_FAW_SHIFT
+#undef DDRC_DRAMTMG0_T_FAW_MASK
 #define DDRC_DRAMTMG0_T_FAW_DEFVAL                             0x0F101B0F
 #define DDRC_DRAMTMG0_T_FAW_SHIFT                              16
 #define DDRC_DRAMTMG0_T_FAW_MASK                               0x003F0000U
@@ -4376,9 +4376,9 @@
     * =2, program this to (tRAS(max)-1)/2. No rounding up. Unit: Multiples of
     * 1024 clocks.
 */
-#undef DDRC_DRAMTMG0_T_RAS_MAX_DEFVAL 
-#undef DDRC_DRAMTMG0_T_RAS_MAX_SHIFT 
-#undef DDRC_DRAMTMG0_T_RAS_MAX_MASK 
+#undef DDRC_DRAMTMG0_T_RAS_MAX_DEFVAL
+#undef DDRC_DRAMTMG0_T_RAS_MAX_SHIFT
+#undef DDRC_DRAMTMG0_T_RAS_MAX_MASK
 #define DDRC_DRAMTMG0_T_RAS_MAX_DEFVAL                         0x0F101B0F
 #define DDRC_DRAMTMG0_T_RAS_MAX_SHIFT                          8
 #define DDRC_DRAMTMG0_T_RAS_MAX_MASK                           0x00007F00U
@@ -4390,9 +4390,9 @@
     * mode or LPDDR4 mode, program this to (tRAS(min)/2) and round it up to th
     * e next integer value. Unit: Clocks
 */
-#undef DDRC_DRAMTMG0_T_RAS_MIN_DEFVAL 
-#undef DDRC_DRAMTMG0_T_RAS_MIN_SHIFT 
-#undef DDRC_DRAMTMG0_T_RAS_MIN_MASK 
+#undef DDRC_DRAMTMG0_T_RAS_MIN_DEFVAL
+#undef DDRC_DRAMTMG0_T_RAS_MIN_SHIFT
+#undef DDRC_DRAMTMG0_T_RAS_MIN_MASK
 #define DDRC_DRAMTMG0_T_RAS_MIN_DEFVAL                         0x0F101B0F
 #define DDRC_DRAMTMG0_T_RAS_MIN_SHIFT                          0
 #define DDRC_DRAMTMG0_T_RAS_MIN_MASK                           0x0000003FU
@@ -4404,9 +4404,9 @@
     * igurations with MEMC_FREQ_RATIO=2, program this to (tXP/2) and round it
     * up to the next integer value. Units: Clocks
 */
-#undef DDRC_DRAMTMG1_T_XP_DEFVAL 
-#undef DDRC_DRAMTMG1_T_XP_SHIFT 
-#undef DDRC_DRAMTMG1_T_XP_MASK 
+#undef DDRC_DRAMTMG1_T_XP_DEFVAL
+#undef DDRC_DRAMTMG1_T_XP_SHIFT
+#undef DDRC_DRAMTMG1_T_XP_MASK
 #define DDRC_DRAMTMG1_T_XP_DEFVAL                              0x00080414
 #define DDRC_DRAMTMG1_T_XP_SHIFT                               16
 #define DDRC_DRAMTMG1_T_XP_MASK                                0x001F0000U
@@ -4422,9 +4422,9 @@
     * gurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the abo
     * ve value by 2 and round it up to the next integer value. Unit: Clocks.
 */
-#undef DDRC_DRAMTMG1_RD2PRE_DEFVAL 
-#undef DDRC_DRAMTMG1_RD2PRE_SHIFT 
-#undef DDRC_DRAMTMG1_RD2PRE_MASK 
+#undef DDRC_DRAMTMG1_RD2PRE_DEFVAL
+#undef DDRC_DRAMTMG1_RD2PRE_SHIFT
+#undef DDRC_DRAMTMG1_RD2PRE_MASK
 #define DDRC_DRAMTMG1_RD2PRE_DEFVAL                            0x00080414
 #define DDRC_DRAMTMG1_RD2PRE_SHIFT                             8
 #define DDRC_DRAMTMG1_RD2PRE_MASK                              0x00001F00U
@@ -4434,9 +4434,9 @@
     * h MEMC_FREQ_RATIO=2, program this to (tRC/2) and round up to next intege
     * r value. Unit: Clocks.
 */
-#undef DDRC_DRAMTMG1_T_RC_DEFVAL 
-#undef DDRC_DRAMTMG1_T_RC_SHIFT 
-#undef DDRC_DRAMTMG1_T_RC_MASK 
+#undef DDRC_DRAMTMG1_T_RC_DEFVAL
+#undef DDRC_DRAMTMG1_T_RC_SHIFT
+#undef DDRC_DRAMTMG1_T_RC_MASK
 #define DDRC_DRAMTMG1_T_RC_DEFVAL                              0x00080414
 #define DDRC_DRAMTMG1_T_RC_SHIFT                               0
 #define DDRC_DRAMTMG1_T_RC_MASK                                0x0000007FU
@@ -4452,9 +4452,9 @@
     *  is set), as the DFI read and write latencies defined in DFITMG0 and DFI
     * TMG1 are sufficient for those protocols Unit: clocks
 */
-#undef DDRC_DRAMTMG2_WRITE_LATENCY_DEFVAL 
-#undef DDRC_DRAMTMG2_WRITE_LATENCY_SHIFT 
-#undef DDRC_DRAMTMG2_WRITE_LATENCY_MASK 
+#undef DDRC_DRAMTMG2_WRITE_LATENCY_DEFVAL
+#undef DDRC_DRAMTMG2_WRITE_LATENCY_SHIFT
+#undef DDRC_DRAMTMG2_WRITE_LATENCY_MASK
 #define DDRC_DRAMTMG2_WRITE_LATENCY_DEFVAL                     0x0305060D
 #define DDRC_DRAMTMG2_WRITE_LATENCY_SHIFT                      24
 #define DDRC_DRAMTMG2_WRITE_LATENCY_MASK                       0x3F000000U
@@ -4470,9 +4470,9 @@
     * s defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit
     * : clocks
 */
-#undef DDRC_DRAMTMG2_READ_LATENCY_DEFVAL 
-#undef DDRC_DRAMTMG2_READ_LATENCY_SHIFT 
-#undef DDRC_DRAMTMG2_READ_LATENCY_MASK 
+#undef DDRC_DRAMTMG2_READ_LATENCY_DEFVAL
+#undef DDRC_DRAMTMG2_READ_LATENCY_SHIFT
+#undef DDRC_DRAMTMG2_READ_LATENCY_MASK
 #define DDRC_DRAMTMG2_READ_LATENCY_DEFVAL                      0x0305060D
 #define DDRC_DRAMTMG2_READ_LATENCY_SHIFT                       16
 #define DDRC_DRAMTMG2_READ_LATENCY_MASK                        0x003F0000U
@@ -4493,9 +4493,9 @@
     * be used. For configurations with MEMC_FREQ_RATIO=2, divide the value cal
     * culated using the above equation by 2, and round it up to next integer.
 */
-#undef DDRC_DRAMTMG2_RD2WR_DEFVAL 
-#undef DDRC_DRAMTMG2_RD2WR_SHIFT 
-#undef DDRC_DRAMTMG2_RD2WR_MASK 
+#undef DDRC_DRAMTMG2_RD2WR_DEFVAL
+#undef DDRC_DRAMTMG2_RD2WR_SHIFT
+#undef DDRC_DRAMTMG2_RD2WR_MASK
 #define DDRC_DRAMTMG2_RD2WR_DEFVAL                             0x0305060D
 #define DDRC_DRAMTMG2_RD2WR_SHIFT                              8
 #define DDRC_DRAMTMG2_RD2WR_MASK                               0x00003F00U
@@ -4515,9 +4515,9 @@
     * e the value calculated using the above equation by 2, and round it up to
     *  next integer.
 */
-#undef DDRC_DRAMTMG2_WR2RD_DEFVAL 
-#undef DDRC_DRAMTMG2_WR2RD_SHIFT 
-#undef DDRC_DRAMTMG2_WR2RD_MASK 
+#undef DDRC_DRAMTMG2_WR2RD_DEFVAL
+#undef DDRC_DRAMTMG2_WR2RD_SHIFT
+#undef DDRC_DRAMTMG2_WR2RD_MASK
 #define DDRC_DRAMTMG2_WR2RD_DEFVAL                             0x0305060D
 #define DDRC_DRAMTMG2_WR2RD_SHIFT                              0
 #define DDRC_DRAMTMG2_WR2RD_MASK                               0x0000003FU
@@ -4530,9 +4530,9 @@
     * er is used for the time from a MRW/MRR to all other commands. For LDPDR3
     * , this register is used for the time from a MRW/MRR to a MRW/MRR.
 */
-#undef DDRC_DRAMTMG3_T_MRW_DEFVAL 
-#undef DDRC_DRAMTMG3_T_MRW_SHIFT 
-#undef DDRC_DRAMTMG3_T_MRW_MASK 
+#undef DDRC_DRAMTMG3_T_MRW_DEFVAL
+#undef DDRC_DRAMTMG3_T_MRW_SHIFT
+#undef DDRC_DRAMTMG3_T_MRW_MASK
 #define DDRC_DRAMTMG3_T_MRW_DEFVAL                             0x0050400C
 #define DDRC_DRAMTMG3_T_MRW_SHIFT                              20
 #define DDRC_DRAMTMG3_T_MRW_MASK                               0x3FF00000U
@@ -4545,9 +4545,9 @@
     *  program this to (tMRD/2) and round it up to the next integer value. If
     * C/A parity for DDR4 is used, set to tMRD_PAR(tMOD+PL) instead.
 */
-#undef DDRC_DRAMTMG3_T_MRD_DEFVAL 
-#undef DDRC_DRAMTMG3_T_MRD_SHIFT 
-#undef DDRC_DRAMTMG3_T_MRD_MASK 
+#undef DDRC_DRAMTMG3_T_MRD_DEFVAL
+#undef DDRC_DRAMTMG3_T_MRD_SHIFT
+#undef DDRC_DRAMTMG3_T_MRD_MASK
 #define DDRC_DRAMTMG3_T_MRD_DEFVAL                             0x0050400C
 #define DDRC_DRAMTMG3_T_MRD_SHIFT                              12
 #define DDRC_DRAMTMG3_T_MRD_MASK                               0x0003F000U
@@ -4561,9 +4561,9 @@
     *  tMOD + 1 or (tMOD + 1)/2 to compensate for the extra cycle of latency a
     * pplied to mode register writes by the RDIMM chip.
 */
-#undef DDRC_DRAMTMG3_T_MOD_DEFVAL 
-#undef DDRC_DRAMTMG3_T_MOD_SHIFT 
-#undef DDRC_DRAMTMG3_T_MOD_MASK 
+#undef DDRC_DRAMTMG3_T_MOD_DEFVAL
+#undef DDRC_DRAMTMG3_T_MOD_SHIFT
+#undef DDRC_DRAMTMG3_T_MOD_MASK
 #define DDRC_DRAMTMG3_T_MOD_DEFVAL                             0x0050400C
 #define DDRC_DRAMTMG3_T_MOD_SHIFT                              0
 #define DDRC_DRAMTMG3_T_MOD_MASK                               0x000003FFU
@@ -4575,9 +4575,9 @@
     * ed for this register is 1, which implies minimum (tRCD - tAL) value to b
     * e 2 in configurations with MEMC_FREQ_RATIO=2. Unit: Clocks.
 */
-#undef DDRC_DRAMTMG4_T_RCD_DEFVAL 
-#undef DDRC_DRAMTMG4_T_RCD_SHIFT 
-#undef DDRC_DRAMTMG4_T_RCD_MASK 
+#undef DDRC_DRAMTMG4_T_RCD_DEFVAL
+#undef DDRC_DRAMTMG4_T_RCD_SHIFT
+#undef DDRC_DRAMTMG4_T_RCD_MASK
 #define DDRC_DRAMTMG4_T_RCD_DEFVAL                             0x05040405
 #define DDRC_DRAMTMG4_T_RCD_SHIFT                              24
 #define DDRC_DRAMTMG4_T_RCD_MASK                               0x1F000000U
@@ -4589,9 +4589,9 @@
     * his to (tCCD_L/2 or tCCD/2) and round it up to the next integer value. U
     * nit: clocks.
 */
-#undef DDRC_DRAMTMG4_T_CCD_DEFVAL 
-#undef DDRC_DRAMTMG4_T_CCD_SHIFT 
-#undef DDRC_DRAMTMG4_T_CCD_MASK 
+#undef DDRC_DRAMTMG4_T_CCD_DEFVAL
+#undef DDRC_DRAMTMG4_T_CCD_SHIFT
+#undef DDRC_DRAMTMG4_T_CCD_MASK
 #define DDRC_DRAMTMG4_T_CCD_DEFVAL                             0x05040405
 #define DDRC_DRAMTMG4_T_CCD_SHIFT                              16
 #define DDRC_DRAMTMG4_T_CCD_MASK                               0x000F0000U
@@ -4603,9 +4603,9 @@
     * s to (tRRD_L/2 or tRRD/2) and round it up to the next integer value. Uni
     * t: Clocks.
 */
-#undef DDRC_DRAMTMG4_T_RRD_DEFVAL 
-#undef DDRC_DRAMTMG4_T_RRD_SHIFT 
-#undef DDRC_DRAMTMG4_T_RRD_MASK 
+#undef DDRC_DRAMTMG4_T_RRD_DEFVAL
+#undef DDRC_DRAMTMG4_T_RRD_SHIFT
+#undef DDRC_DRAMTMG4_T_RRD_MASK
 #define DDRC_DRAMTMG4_T_RRD_DEFVAL                             0x05040405
 #define DDRC_DRAMTMG4_T_RRD_SHIFT                              8
 #define DDRC_DRAMTMG4_T_RRD_MASK                               0x00000F00U
@@ -4617,9 +4617,9 @@
     * RP/tCK)/2) + 1. For MEMC_FREQ_RATIO=2 configurations in LPDDR4, t_rp sho
     * uld be set to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks.
 */
-#undef DDRC_DRAMTMG4_T_RP_DEFVAL 
-#undef DDRC_DRAMTMG4_T_RP_SHIFT 
-#undef DDRC_DRAMTMG4_T_RP_MASK 
+#undef DDRC_DRAMTMG4_T_RP_DEFVAL
+#undef DDRC_DRAMTMG4_T_RP_SHIFT
+#undef DDRC_DRAMTMG4_T_RP_MASK
 #define DDRC_DRAMTMG4_T_RP_DEFVAL                              0x05040405
 #define DDRC_DRAMTMG4_T_RP_SHIFT                               0
 #define DDRC_DRAMTMG4_T_RP_MASK                                0x0000001FU
@@ -4632,9 +4632,9 @@
     * FREQ_RATIO=2, program this to recommended value divided by two and round
     *  it up to next integer.
 */
-#undef DDRC_DRAMTMG5_T_CKSRX_DEFVAL 
-#undef DDRC_DRAMTMG5_T_CKSRX_SHIFT 
-#undef DDRC_DRAMTMG5_T_CKSRX_MASK 
+#undef DDRC_DRAMTMG5_T_CKSRX_DEFVAL
+#undef DDRC_DRAMTMG5_T_CKSRX_SHIFT
+#undef DDRC_DRAMTMG5_T_CKSRX_MASK
 #define DDRC_DRAMTMG5_T_CKSRX_DEFVAL                           0x05050403
 #define DDRC_DRAMTMG5_T_CKSRX_SHIFT                            24
 #define DDRC_DRAMTMG5_T_CKSRX_MASK                             0x0F000000U
@@ -4647,9 +4647,9 @@
     *  with MEMC_FREQ_RATIO=2, program this to recommended value divided by tw
     * o and round it up to next integer.
 */
-#undef DDRC_DRAMTMG5_T_CKSRE_DEFVAL 
-#undef DDRC_DRAMTMG5_T_CKSRE_SHIFT 
-#undef DDRC_DRAMTMG5_T_CKSRE_MASK 
+#undef DDRC_DRAMTMG5_T_CKSRE_DEFVAL
+#undef DDRC_DRAMTMG5_T_CKSRE_SHIFT
+#undef DDRC_DRAMTMG5_T_CKSRE_MASK
 #define DDRC_DRAMTMG5_T_CKSRE_DEFVAL                           0x05050403
 #define DDRC_DRAMTMG5_T_CKSRE_SHIFT                            16
 #define DDRC_DRAMTMG5_T_CKSRE_MASK                             0x000F0000U
@@ -4662,9 +4662,9 @@
     * _RATIO=2, program this to recommended value divided by two and round it
     * up to next integer.
 */
-#undef DDRC_DRAMTMG5_T_CKESR_DEFVAL 
-#undef DDRC_DRAMTMG5_T_CKESR_SHIFT 
-#undef DDRC_DRAMTMG5_T_CKESR_MASK 
+#undef DDRC_DRAMTMG5_T_CKESR_DEFVAL
+#undef DDRC_DRAMTMG5_T_CKESR_SHIFT
+#undef DDRC_DRAMTMG5_T_CKESR_MASK
 #define DDRC_DRAMTMG5_T_CKESR_DEFVAL                           0x05050403
 #define DDRC_DRAMTMG5_T_CKESR_SHIFT                            8
 #define DDRC_DRAMTMG5_T_CKESR_MASK                             0x00003F00U
@@ -4677,9 +4677,9 @@
     * s with MEMC_FREQ_RATIO=2, program this to (value described above)/2 and
     * round it up to the next integer value. Unit: Clocks.
 */
-#undef DDRC_DRAMTMG5_T_CKE_DEFVAL 
-#undef DDRC_DRAMTMG5_T_CKE_SHIFT 
-#undef DDRC_DRAMTMG5_T_CKE_MASK 
+#undef DDRC_DRAMTMG5_T_CKE_DEFVAL
+#undef DDRC_DRAMTMG5_T_CKE_SHIFT
+#undef DDRC_DRAMTMG5_T_CKE_MASK
 #define DDRC_DRAMTMG5_T_CKE_DEFVAL                             0x05050403
 #define DDRC_DRAMTMG5_T_CKE_SHIFT                              0
 #define DDRC_DRAMTMG5_T_CKE_MASK                               0x0000001FU
@@ -4692,9 +4692,9 @@
     *  it up to next integer. This is only present for designs supporting mDDR
     *  or LPDDR2/LPDDR3 devices.
 */
-#undef DDRC_DRAMTMG6_T_CKDPDE_DEFVAL 
-#undef DDRC_DRAMTMG6_T_CKDPDE_SHIFT 
-#undef DDRC_DRAMTMG6_T_CKDPDE_MASK 
+#undef DDRC_DRAMTMG6_T_CKDPDE_DEFVAL
+#undef DDRC_DRAMTMG6_T_CKDPDE_SHIFT
+#undef DDRC_DRAMTMG6_T_CKDPDE_MASK
 #define DDRC_DRAMTMG6_T_CKDPDE_DEFVAL                          0x02020005
 #define DDRC_DRAMTMG6_T_CKDPDE_SHIFT                           24
 #define DDRC_DRAMTMG6_T_CKDPDE_MASK                            0x0F000000U
@@ -4707,9 +4707,9 @@
     * ed by two and round it up to next integer. This is only present for desi
     * gns supporting mDDR or LPDDR2 devices.
 */
-#undef DDRC_DRAMTMG6_T_CKDPDX_DEFVAL 
-#undef DDRC_DRAMTMG6_T_CKDPDX_SHIFT 
-#undef DDRC_DRAMTMG6_T_CKDPDX_MASK 
+#undef DDRC_DRAMTMG6_T_CKDPDX_DEFVAL
+#undef DDRC_DRAMTMG6_T_CKDPDX_SHIFT
+#undef DDRC_DRAMTMG6_T_CKDPDX_MASK
 #define DDRC_DRAMTMG6_T_CKDPDX_DEFVAL                          0x02020005
 #define DDRC_DRAMTMG6_T_CKDPDX_SHIFT                           16
 #define DDRC_DRAMTMG6_T_CKDPDX_MASK                            0x000F0000U
@@ -4723,9 +4723,9 @@
     * two and round it up to next integer. This is only present for designs su
     * pporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
 */
-#undef DDRC_DRAMTMG6_T_CKCSX_DEFVAL 
-#undef DDRC_DRAMTMG6_T_CKCSX_SHIFT 
-#undef DDRC_DRAMTMG6_T_CKCSX_MASK 
+#undef DDRC_DRAMTMG6_T_CKCSX_DEFVAL
+#undef DDRC_DRAMTMG6_T_CKCSX_SHIFT
+#undef DDRC_DRAMTMG6_T_CKCSX_MASK
 #define DDRC_DRAMTMG6_T_CKCSX_DEFVAL                           0x02020005
 #define DDRC_DRAMTMG6_T_CKCSX_SHIFT                            0
 #define DDRC_DRAMTMG6_T_CKCSX_MASK                             0x0000000FU
@@ -4738,9 +4738,9 @@
     * wo and round it up to next integer. This is only present for designs sup
     * porting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
 */
-#undef DDRC_DRAMTMG7_T_CKPDE_DEFVAL 
-#undef DDRC_DRAMTMG7_T_CKPDE_SHIFT 
-#undef DDRC_DRAMTMG7_T_CKPDE_MASK 
+#undef DDRC_DRAMTMG7_T_CKPDE_DEFVAL
+#undef DDRC_DRAMTMG7_T_CKPDE_SHIFT
+#undef DDRC_DRAMTMG7_T_CKPDE_MASK
 #define DDRC_DRAMTMG7_T_CKPDE_DEFVAL                           0x00000202
 #define DDRC_DRAMTMG7_T_CKPDE_SHIFT                            8
 #define DDRC_DRAMTMG7_T_CKPDE_MASK                             0x00000F00U
@@ -4753,9 +4753,9 @@
     * divided by two and round it up to next integer. This is only present for
     *  designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
 */
-#undef DDRC_DRAMTMG7_T_CKPDX_DEFVAL 
-#undef DDRC_DRAMTMG7_T_CKPDX_SHIFT 
-#undef DDRC_DRAMTMG7_T_CKPDX_MASK 
+#undef DDRC_DRAMTMG7_T_CKPDX_DEFVAL
+#undef DDRC_DRAMTMG7_T_CKPDX_SHIFT
+#undef DDRC_DRAMTMG7_T_CKPDX_MASK
 #define DDRC_DRAMTMG7_T_CKPDX_DEFVAL                           0x00000202
 #define DDRC_DRAMTMG7_T_CKPDX_SHIFT                            0
 #define DDRC_DRAMTMG7_T_CKPDX_MASK                             0x0000000FU
@@ -4767,9 +4767,9 @@
     * : Multiples of 32 clocks. Note: This is applicable to only ZQCL/ZQCS com
     * mands. Note: Ensure this is less than or equal to t_xs_x32.
 */
-#undef DDRC_DRAMTMG8_T_XS_FAST_X32_DEFVAL 
-#undef DDRC_DRAMTMG8_T_XS_FAST_X32_SHIFT 
-#undef DDRC_DRAMTMG8_T_XS_FAST_X32_MASK 
+#undef DDRC_DRAMTMG8_T_XS_FAST_X32_DEFVAL
+#undef DDRC_DRAMTMG8_T_XS_FAST_X32_SHIFT
+#undef DDRC_DRAMTMG8_T_XS_FAST_X32_MASK
 #define DDRC_DRAMTMG8_T_XS_FAST_X32_DEFVAL                     0x03034405
 #define DDRC_DRAMTMG8_T_XS_FAST_X32_SHIFT                      24
 #define DDRC_DRAMTMG8_T_XS_FAST_X32_MASK                       0x7F000000U
@@ -4781,9 +4781,9 @@
     * nit: Multiples of 32 clocks. Note: Ensure this is less than or equal to
     * t_xs_x32.
 */
-#undef DDRC_DRAMTMG8_T_XS_ABORT_X32_DEFVAL 
-#undef DDRC_DRAMTMG8_T_XS_ABORT_X32_SHIFT 
-#undef DDRC_DRAMTMG8_T_XS_ABORT_X32_MASK 
+#undef DDRC_DRAMTMG8_T_XS_ABORT_X32_DEFVAL
+#undef DDRC_DRAMTMG8_T_XS_ABORT_X32_SHIFT
+#undef DDRC_DRAMTMG8_T_XS_ABORT_X32_MASK
 #define DDRC_DRAMTMG8_T_XS_ABORT_X32_DEFVAL                    0x03034405
 #define DDRC_DRAMTMG8_T_XS_ABORT_X32_SHIFT                     16
 #define DDRC_DRAMTMG8_T_XS_ABORT_X32_MASK                      0x007F0000U
@@ -4794,9 +4794,9 @@
     *  by 2 and round up to next integer value. Unit: Multiples of 32 clocks.
     * Note: Used only for DDR2, DDR3 and DDR4 SDRAMs.
 */
-#undef DDRC_DRAMTMG8_T_XS_DLL_X32_DEFVAL 
-#undef DDRC_DRAMTMG8_T_XS_DLL_X32_SHIFT 
-#undef DDRC_DRAMTMG8_T_XS_DLL_X32_MASK 
+#undef DDRC_DRAMTMG8_T_XS_DLL_X32_DEFVAL
+#undef DDRC_DRAMTMG8_T_XS_DLL_X32_SHIFT
+#undef DDRC_DRAMTMG8_T_XS_DLL_X32_MASK
 #define DDRC_DRAMTMG8_T_XS_DLL_X32_DEFVAL                      0x03034405
 #define DDRC_DRAMTMG8_T_XS_DLL_X32_SHIFT                       8
 #define DDRC_DRAMTMG8_T_XS_DLL_X32_MASK                        0x00007F00U
@@ -4807,9 +4807,9 @@
     * d by 2 and round up to next integer value. Unit: Multiples of 32 clocks.
     *  Note: Used only for DDR2, DDR3 and DDR4 SDRAMs.
 */
-#undef DDRC_DRAMTMG8_T_XS_X32_DEFVAL 
-#undef DDRC_DRAMTMG8_T_XS_X32_SHIFT 
-#undef DDRC_DRAMTMG8_T_XS_X32_MASK 
+#undef DDRC_DRAMTMG8_T_XS_X32_DEFVAL
+#undef DDRC_DRAMTMG8_T_XS_X32_SHIFT
+#undef DDRC_DRAMTMG8_T_XS_X32_MASK
 #define DDRC_DRAMTMG8_T_XS_X32_DEFVAL                          0x03034405
 #define DDRC_DRAMTMG8_T_XS_X32_SHIFT                           0
 #define DDRC_DRAMTMG8_T_XS_X32_MASK                            0x0000007FU
@@ -4818,9 +4818,9 @@
 * DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present o
     * nly with MEMC_FREQ_RATIO=2
 */
-#undef DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_DEFVAL 
-#undef DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_SHIFT 
-#undef DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_MASK 
+#undef DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_DEFVAL
+#undef DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_SHIFT
+#undef DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_MASK
 #define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_DEFVAL                  0x0004040D
 #define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_SHIFT                   30
 #define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_MASK                    0x40000000U
@@ -4832,9 +4832,9 @@
     * , program this to (tCCD_S/2) and round it up to the next integer value.
     * Present only in designs configured to support DDR4. Unit: clocks.
 */
-#undef DDRC_DRAMTMG9_T_CCD_S_DEFVAL 
-#undef DDRC_DRAMTMG9_T_CCD_S_SHIFT 
-#undef DDRC_DRAMTMG9_T_CCD_S_MASK 
+#undef DDRC_DRAMTMG9_T_CCD_S_DEFVAL
+#undef DDRC_DRAMTMG9_T_CCD_S_SHIFT
+#undef DDRC_DRAMTMG9_T_CCD_S_MASK
 #define DDRC_DRAMTMG9_T_CCD_S_DEFVAL                           0x0004040D
 #define DDRC_DRAMTMG9_T_CCD_S_SHIFT                            16
 #define DDRC_DRAMTMG9_T_CCD_S_MASK                             0x00070000U
@@ -4845,9 +4845,9 @@
     * is to (tRRD_S/2) and round it up to the next integer value. Present only
     *  in designs configured to support DDR4. Unit: Clocks.
 */
-#undef DDRC_DRAMTMG9_T_RRD_S_DEFVAL 
-#undef DDRC_DRAMTMG9_T_RRD_S_SHIFT 
-#undef DDRC_DRAMTMG9_T_RRD_S_MASK 
+#undef DDRC_DRAMTMG9_T_RRD_S_DEFVAL
+#undef DDRC_DRAMTMG9_T_RRD_S_SHIFT
+#undef DDRC_DRAMTMG9_T_RRD_S_MASK
 #define DDRC_DRAMTMG9_T_RRD_S_DEFVAL                           0x0004040D
 #define DDRC_DRAMTMG9_T_RRD_S_SHIFT                            8
 #define DDRC_DRAMTMG9_T_RRD_S_MASK                             0x00000F00U
@@ -4864,9 +4864,9 @@
     * MEMC_FREQ_RATIO=2, divide the value calculated using the above equation
     * by 2, and round it up to next integer.
 */
-#undef DDRC_DRAMTMG9_WR2RD_S_DEFVAL 
-#undef DDRC_DRAMTMG9_WR2RD_S_SHIFT 
-#undef DDRC_DRAMTMG9_WR2RD_S_MASK 
+#undef DDRC_DRAMTMG9_WR2RD_S_DEFVAL
+#undef DDRC_DRAMTMG9_WR2RD_S_SHIFT
+#undef DDRC_DRAMTMG9_WR2RD_S_MASK
 #define DDRC_DRAMTMG9_WR2RD_S_DEFVAL                           0x0004040D
 #define DDRC_DRAMTMG9_WR2RD_S_SHIFT                            0
 #define DDRC_DRAMTMG9_WR2RD_S_MASK                             0x0000003FU
@@ -4877,9 +4877,9 @@
     * ) and round it up to the next integer value. Present only in designs con
     * figured to support DDR4. Unit: Multiples of 32 clocks.
 */
-#undef DDRC_DRAMTMG11_POST_MPSM_GAP_X32_DEFVAL 
-#undef DDRC_DRAMTMG11_POST_MPSM_GAP_X32_SHIFT 
-#undef DDRC_DRAMTMG11_POST_MPSM_GAP_X32_MASK 
+#undef DDRC_DRAMTMG11_POST_MPSM_GAP_X32_DEFVAL
+#undef DDRC_DRAMTMG11_POST_MPSM_GAP_X32_SHIFT
+#undef DDRC_DRAMTMG11_POST_MPSM_GAP_X32_MASK
 #define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_DEFVAL                0x440C021C
 #define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_SHIFT                 24
 #define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_MASK                  0x7F000000U
@@ -4889,9 +4889,9 @@
     * configurations with MEMC_FREQ_RATIO=2, program this to RoundUp(tMPX_LH/2
     * )+1. Present only in designs configured to support DDR4. Unit: clocks.
 */
-#undef DDRC_DRAMTMG11_T_MPX_LH_DEFVAL 
-#undef DDRC_DRAMTMG11_T_MPX_LH_SHIFT 
-#undef DDRC_DRAMTMG11_T_MPX_LH_MASK 
+#undef DDRC_DRAMTMG11_T_MPX_LH_DEFVAL
+#undef DDRC_DRAMTMG11_T_MPX_LH_SHIFT
+#undef DDRC_DRAMTMG11_T_MPX_LH_MASK
 #define DDRC_DRAMTMG11_T_MPX_LH_DEFVAL                         0x440C021C
 #define DDRC_DRAMTMG11_T_MPX_LH_SHIFT                          16
 #define DDRC_DRAMTMG11_T_MPX_LH_MASK                           0x001F0000U
@@ -4902,9 +4902,9 @@
     * eger value. Present only in designs configured to support DDR4. Unit: Cl
     * ocks.
 */
-#undef DDRC_DRAMTMG11_T_MPX_S_DEFVAL 
-#undef DDRC_DRAMTMG11_T_MPX_S_SHIFT 
-#undef DDRC_DRAMTMG11_T_MPX_S_MASK 
+#undef DDRC_DRAMTMG11_T_MPX_S_DEFVAL
+#undef DDRC_DRAMTMG11_T_MPX_S_SHIFT
+#undef DDRC_DRAMTMG11_T_MPX_S_MASK
 #define DDRC_DRAMTMG11_T_MPX_S_DEFVAL                          0x440C021C
 #define DDRC_DRAMTMG11_T_MPX_S_SHIFT                           8
 #define DDRC_DRAMTMG11_T_MPX_S_MASK                            0x00000300U
@@ -4915,9 +4915,9 @@
     * ith MEMC_FREQ_RATIO=2, divide the value calculated using the above equat
     * ion by 2, and round it up to next integer.
 */
-#undef DDRC_DRAMTMG11_T_CKMPE_DEFVAL 
-#undef DDRC_DRAMTMG11_T_CKMPE_SHIFT 
-#undef DDRC_DRAMTMG11_T_CKMPE_MASK 
+#undef DDRC_DRAMTMG11_T_CKMPE_DEFVAL
+#undef DDRC_DRAMTMG11_T_CKMPE_SHIFT
+#undef DDRC_DRAMTMG11_T_CKMPE_MASK
 #define DDRC_DRAMTMG11_T_CKMPE_DEFVAL                          0x440C021C
 #define DDRC_DRAMTMG11_T_CKMPE_SHIFT                           0
 #define DDRC_DRAMTMG11_T_CKMPE_MASK                            0x0000001FU
@@ -4928,9 +4928,9 @@
     * am this to (max(tESCKE, tCMDCKE)/2) and round it up to next integer valu
     * e.
 */
-#undef DDRC_DRAMTMG12_T_CMDCKE_DEFVAL 
-#undef DDRC_DRAMTMG12_T_CMDCKE_SHIFT 
-#undef DDRC_DRAMTMG12_T_CMDCKE_MASK 
+#undef DDRC_DRAMTMG12_T_CMDCKE_DEFVAL
+#undef DDRC_DRAMTMG12_T_CMDCKE_SHIFT
+#undef DDRC_DRAMTMG12_T_CMDCKE_MASK
 #define DDRC_DRAMTMG12_T_CMDCKE_DEFVAL                         0x00020610
 #define DDRC_DRAMTMG12_T_CMDCKE_SHIFT                          16
 #define DDRC_DRAMTMG12_T_CMDCKE_MASK                           0x00030000U
@@ -4940,9 +4940,9 @@
     * ions with MEMC_FREQ_RATIO=2, program this to (tCKEHCMD/2) and round it u
     * p to next integer value.
 */
-#undef DDRC_DRAMTMG12_T_CKEHCMD_DEFVAL 
-#undef DDRC_DRAMTMG12_T_CKEHCMD_SHIFT 
-#undef DDRC_DRAMTMG12_T_CKEHCMD_MASK 
+#undef DDRC_DRAMTMG12_T_CKEHCMD_DEFVAL
+#undef DDRC_DRAMTMG12_T_CKEHCMD_SHIFT
+#undef DDRC_DRAMTMG12_T_CKEHCMD_MASK
 #define DDRC_DRAMTMG12_T_CKEHCMD_DEFVAL                        0x00020610
 #define DDRC_DRAMTMG12_T_CKEHCMD_SHIFT                         8
 #define DDRC_DRAMTMG12_T_CKEHCMD_MASK                          0x00000F00U
@@ -4952,9 +4952,9 @@
     * For configurations with MEMC_FREQ_RATIO=2, program this to (tMRD_PDA/2)
     * and round it up to next integer value.
 */
-#undef DDRC_DRAMTMG12_T_MRD_PDA_DEFVAL 
-#undef DDRC_DRAMTMG12_T_MRD_PDA_SHIFT 
-#undef DDRC_DRAMTMG12_T_MRD_PDA_MASK 
+#undef DDRC_DRAMTMG12_T_MRD_PDA_DEFVAL
+#undef DDRC_DRAMTMG12_T_MRD_PDA_SHIFT
+#undef DDRC_DRAMTMG12_T_MRD_PDA_MASK
 #define DDRC_DRAMTMG12_T_MRD_PDA_DEFVAL                        0x00020610
 #define DDRC_DRAMTMG12_T_MRD_PDA_SHIFT                         0
 #define DDRC_DRAMTMG12_T_MRD_PDA_MASK                          0x0000001FU
@@ -4966,9 +4966,9 @@
     * on) commands based on ZQCTL1.t_zq_short_interval_x1024. This is only pre
     * sent for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
 */
-#undef DDRC_ZQCTL0_DIS_AUTO_ZQ_DEFVAL 
-#undef DDRC_ZQCTL0_DIS_AUTO_ZQ_SHIFT 
-#undef DDRC_ZQCTL0_DIS_AUTO_ZQ_MASK 
+#undef DDRC_ZQCTL0_DIS_AUTO_ZQ_DEFVAL
+#undef DDRC_ZQCTL0_DIS_AUTO_ZQ_SHIFT
+#undef DDRC_ZQCTL0_DIS_AUTO_ZQ_MASK
 #define DDRC_ZQCTL0_DIS_AUTO_ZQ_DEFVAL                         0x02000040
 #define DDRC_ZQCTL0_DIS_AUTO_ZQ_SHIFT                          31
 #define DDRC_ZQCTL0_DIS_AUTO_ZQ_MASK                           0x80000000U
@@ -4981,9 +4981,9 @@
     * n DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present
     * for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
 */
-#undef DDRC_ZQCTL0_DIS_SRX_ZQCL_DEFVAL 
-#undef DDRC_ZQCTL0_DIS_SRX_ZQCL_SHIFT 
-#undef DDRC_ZQCTL0_DIS_SRX_ZQCL_MASK 
+#undef DDRC_ZQCTL0_DIS_SRX_ZQCL_DEFVAL
+#undef DDRC_ZQCTL0_DIS_SRX_ZQCL_SHIFT
+#undef DDRC_ZQCTL0_DIS_SRX_ZQCL_MASK
 #define DDRC_ZQCTL0_DIS_SRX_ZQCL_DEFVAL                        0x02000040
 #define DDRC_ZQCTL0_DIS_SRX_ZQCL_SHIFT                         30
 #define DDRC_ZQCTL0_DIS_SRX_ZQCL_MASK                          0x40000000U
@@ -4996,9 +4996,9 @@
     * d. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR
     * 3/LPDDR4 devices.
 */
-#undef DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_DEFVAL 
-#undef DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT 
-#undef DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_MASK 
+#undef DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_DEFVAL
+#undef DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT
+#undef DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_MASK
 #define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_DEFVAL                  0x02000040
 #define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT                   29
 #define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_MASK                    0x20000000U
@@ -5009,9 +5009,9 @@
     * mand at Maximum Power Saving Mode exit. Only applicable when run in DDR4
     *  mode. This is only present for designs supporting DDR4 devices.
 */
-#undef DDRC_ZQCTL0_DIS_MPSMX_ZQCL_DEFVAL 
-#undef DDRC_ZQCTL0_DIS_MPSMX_ZQCL_SHIFT 
-#undef DDRC_ZQCTL0_DIS_MPSMX_ZQCL_MASK 
+#undef DDRC_ZQCTL0_DIS_MPSMX_ZQCL_DEFVAL
+#undef DDRC_ZQCTL0_DIS_MPSMX_ZQCL_SHIFT
+#undef DDRC_ZQCTL0_DIS_MPSMX_ZQCL_MASK
 #define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_DEFVAL                      0x02000040
 #define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_SHIFT                       28
 #define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_MASK                        0x10000000U
@@ -5026,9 +5026,9 @@
     * o the next integer value. Unit: Clock cycles. This is only present for d
     * esigns supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
 */
-#undef DDRC_ZQCTL0_T_ZQ_LONG_NOP_DEFVAL 
-#undef DDRC_ZQCTL0_T_ZQ_LONG_NOP_SHIFT 
-#undef DDRC_ZQCTL0_T_ZQ_LONG_NOP_MASK 
+#undef DDRC_ZQCTL0_T_ZQ_LONG_NOP_DEFVAL
+#undef DDRC_ZQCTL0_T_ZQ_LONG_NOP_SHIFT
+#undef DDRC_ZQCTL0_T_ZQ_LONG_NOP_MASK
 #define DDRC_ZQCTL0_T_ZQ_LONG_NOP_DEFVAL                       0x02000040
 #define DDRC_ZQCTL0_T_ZQ_LONG_NOP_SHIFT                        16
 #define DDRC_ZQCTL0_T_ZQ_LONG_NOP_MASK                         0x07FF0000U
@@ -5041,9 +5041,9 @@
     * cles. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LP
     * DDR3/LPDDR4 devices.
 */
-#undef DDRC_ZQCTL0_T_ZQ_SHORT_NOP_DEFVAL 
-#undef DDRC_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT 
-#undef DDRC_ZQCTL0_T_ZQ_SHORT_NOP_MASK 
+#undef DDRC_ZQCTL0_T_ZQ_SHORT_NOP_DEFVAL
+#undef DDRC_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT
+#undef DDRC_ZQCTL0_T_ZQ_SHORT_NOP_MASK
 #define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_DEFVAL                      0x02000040
 #define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT                       0
 #define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_MASK                        0x000003FFU
@@ -5055,9 +5055,9 @@
     * value. Unit: Clock cycles. This is only present for designs supporting L
     * PDDR2/LPDDR3/LPDDR4 devices.
 */
-#undef DDRC_ZQCTL1_T_ZQ_RESET_NOP_DEFVAL 
-#undef DDRC_ZQCTL1_T_ZQ_RESET_NOP_SHIFT 
-#undef DDRC_ZQCTL1_T_ZQ_RESET_NOP_MASK 
+#undef DDRC_ZQCTL1_T_ZQ_RESET_NOP_DEFVAL
+#undef DDRC_ZQCTL1_T_ZQ_RESET_NOP_SHIFT
+#undef DDRC_ZQCTL1_T_ZQ_RESET_NOP_MASK
 #define DDRC_ZQCTL1_T_ZQ_RESET_NOP_DEFVAL                      0x02000100
 #define DDRC_ZQCTL1_T_ZQ_RESET_NOP_SHIFT                       20
 #define DDRC_ZQCTL1_T_ZQ_RESET_NOP_MASK                        0x3FF00000U
@@ -5069,9 +5069,9 @@
     * . This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3
     * /LPDDR4 devices.
 */
-#undef DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_DEFVAL 
-#undef DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT 
-#undef DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK 
+#undef DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_DEFVAL
+#undef DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT
+#undef DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK
 #define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_DEFVAL           0x02000100
 #define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT            0
 #define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK             0x000FFFFFU
@@ -5085,9 +5085,9 @@
     * ssary to increment this parameter by RDIMM's extra cycle of latency in t
     * erms of DFI clock.
 */
-#undef DDRC_DFITMG0_DFI_T_CTRL_DELAY_DEFVAL 
-#undef DDRC_DFITMG0_DFI_T_CTRL_DELAY_SHIFT 
-#undef DDRC_DFITMG0_DFI_T_CTRL_DELAY_MASK 
+#undef DDRC_DFITMG0_DFI_T_CTRL_DELAY_DEFVAL
+#undef DDRC_DFITMG0_DFI_T_CTRL_DELAY_SHIFT
+#undef DDRC_DFITMG0_DFI_T_CTRL_DELAY_MASK
 #define DDRC_DFITMG0_DFI_T_CTRL_DELAY_DEFVAL                   0x07020002
 #define DDRC_DFITMG0_DFI_T_CTRL_DELAY_SHIFT                    24
 #define DDRC_DFITMG0_DFI_T_CTRL_DELAY_MASK                     0x1F000000U
@@ -5099,9 +5099,9 @@
     *  - 1 in terms of SDR clock cycles Refer to PHY specification for correct
     *  value.
 */
-#undef DDRC_DFITMG0_DFI_RDDATA_USE_SDR_DEFVAL 
-#undef DDRC_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT 
-#undef DDRC_DFITMG0_DFI_RDDATA_USE_SDR_MASK 
+#undef DDRC_DFITMG0_DFI_RDDATA_USE_SDR_DEFVAL
+#undef DDRC_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT
+#undef DDRC_DFITMG0_DFI_RDDATA_USE_SDR_MASK
 #define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_DEFVAL                 0x07020002
 #define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT                  23
 #define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_MASK                   0x00800000U
@@ -5114,9 +5114,9 @@
     * ue (CL + 1) in the calculation of trddata_en. This is to compensate for
     * the extra cycle of latency through the RDIMM. Unit: Clocks
 */
-#undef DDRC_DFITMG0_DFI_T_RDDATA_EN_DEFVAL 
-#undef DDRC_DFITMG0_DFI_T_RDDATA_EN_SHIFT 
-#undef DDRC_DFITMG0_DFI_T_RDDATA_EN_MASK 
+#undef DDRC_DFITMG0_DFI_T_RDDATA_EN_DEFVAL
+#undef DDRC_DFITMG0_DFI_T_RDDATA_EN_SHIFT
+#undef DDRC_DFITMG0_DFI_T_RDDATA_EN_MASK
 #define DDRC_DFITMG0_DFI_T_RDDATA_EN_DEFVAL                    0x07020002
 #define DDRC_DFITMG0_DFI_T_RDDATA_EN_SHIFT                     16
 #define DDRC_DFITMG0_DFI_T_RDDATA_EN_MASK                      0x003F0000U
@@ -5129,9 +5129,9 @@
     *  clock cycles - 1 in terms of SDR clock cycles Refer to PHY specificatio
     * n for correct value.
 */
-#undef DDRC_DFITMG0_DFI_WRDATA_USE_SDR_DEFVAL 
-#undef DDRC_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT 
-#undef DDRC_DFITMG0_DFI_WRDATA_USE_SDR_MASK 
+#undef DDRC_DFITMG0_DFI_WRDATA_USE_SDR_DEFVAL
+#undef DDRC_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT
+#undef DDRC_DFITMG0_DFI_WRDATA_USE_SDR_MASK
 #define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_DEFVAL                 0x07020002
 #define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT                  15
 #define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_MASK                   0x00008000U
@@ -5143,9 +5143,9 @@
     *  specification for correct value. Note, max supported value is 8. Unit:
     * Clocks
 */
-#undef DDRC_DFITMG0_DFI_TPHY_WRDATA_DEFVAL 
-#undef DDRC_DFITMG0_DFI_TPHY_WRDATA_SHIFT 
-#undef DDRC_DFITMG0_DFI_TPHY_WRDATA_MASK 
+#undef DDRC_DFITMG0_DFI_TPHY_WRDATA_DEFVAL
+#undef DDRC_DFITMG0_DFI_TPHY_WRDATA_SHIFT
+#undef DDRC_DFITMG0_DFI_TPHY_WRDATA_MASK
 #define DDRC_DFITMG0_DFI_TPHY_WRDATA_DEFVAL                    0x07020002
 #define DDRC_DFITMG0_DFI_TPHY_WRDATA_SHIFT                     8
 #define DDRC_DFITMG0_DFI_TPHY_WRDATA_MASK                      0x00003F00U
@@ -5158,9 +5158,9 @@
     *  in the calculation of tphy_wrlat. This is to compensate for the extra c
     * ycle of latency through the RDIMM.
 */
-#undef DDRC_DFITMG0_DFI_TPHY_WRLAT_DEFVAL 
-#undef DDRC_DFITMG0_DFI_TPHY_WRLAT_SHIFT 
-#undef DDRC_DFITMG0_DFI_TPHY_WRLAT_MASK 
+#undef DDRC_DFITMG0_DFI_TPHY_WRLAT_DEFVAL
+#undef DDRC_DFITMG0_DFI_TPHY_WRLAT_SHIFT
+#undef DDRC_DFITMG0_DFI_TPHY_WRLAT_MASK
 #define DDRC_DFITMG0_DFI_TPHY_WRLAT_DEFVAL                     0x07020002
 #define DDRC_DFITMG0_DFI_TPHY_WRLAT_SHIFT                      0
 #define DDRC_DFITMG0_DFI_TPHY_WRLAT_MASK                       0x0000003FU
@@ -5172,9 +5172,9 @@
     * de register setting in the DRAM. If the PHY can add the latency for CAL
     * mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8
 */
-#undef DDRC_DFITMG1_DFI_T_CMD_LAT_DEFVAL 
-#undef DDRC_DFITMG1_DFI_T_CMD_LAT_SHIFT 
-#undef DDRC_DFITMG1_DFI_T_CMD_LAT_MASK 
+#undef DDRC_DFITMG1_DFI_T_CMD_LAT_DEFVAL
+#undef DDRC_DFITMG1_DFI_T_CMD_LAT_SHIFT
+#undef DDRC_DFITMG1_DFI_T_CMD_LAT_MASK
 #define DDRC_DFITMG1_DFI_T_CMD_LAT_DEFVAL                      0x00000404
 #define DDRC_DFITMG1_DFI_T_CMD_LAT_SHIFT                       28
 #define DDRC_DFITMG1_DFI_T_CMD_LAT_MASK                        0xF0000000U
@@ -5183,9 +5183,9 @@
 * Specifies the number of DFI PHY clocks between when the dfi_cs signal is
     *  asserted and when the associated dfi_parity_in signal is driven.
 */
-#undef DDRC_DFITMG1_DFI_T_PARIN_LAT_DEFVAL 
-#undef DDRC_DFITMG1_DFI_T_PARIN_LAT_SHIFT 
-#undef DDRC_DFITMG1_DFI_T_PARIN_LAT_MASK 
+#undef DDRC_DFITMG1_DFI_T_PARIN_LAT_DEFVAL
+#undef DDRC_DFITMG1_DFI_T_PARIN_LAT_SHIFT
+#undef DDRC_DFITMG1_DFI_T_PARIN_LAT_MASK
 #define DDRC_DFITMG1_DFI_T_PARIN_LAT_DEFVAL                    0x00000404
 #define DDRC_DFITMG1_DFI_T_PARIN_LAT_SHIFT                     24
 #define DDRC_DFITMG1_DFI_T_PARIN_LAT_MASK                      0x03000000U
@@ -5201,9 +5201,9 @@
     * RATIO=2, divide PHY's value by 2 and round up to next integer. If using
     * DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Unit: Clocks
 */
-#undef DDRC_DFITMG1_DFI_T_WRDATA_DELAY_DEFVAL 
-#undef DDRC_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT 
-#undef DDRC_DFITMG1_DFI_T_WRDATA_DELAY_MASK 
+#undef DDRC_DFITMG1_DFI_T_WRDATA_DELAY_DEFVAL
+#undef DDRC_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT
+#undef DDRC_DFITMG1_DFI_T_WRDATA_DELAY_MASK
 #define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_DEFVAL                 0x00000404
 #define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT                  16
 #define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_MASK                   0x001F0000U
@@ -5215,9 +5215,9 @@
     * and the memory clock are not phase aligned, this timing parameter should
     *  be rounded up to the next integer value.
 */
-#undef DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_DEFVAL 
-#undef DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT 
-#undef DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK 
+#undef DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_DEFVAL
+#undef DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT
+#undef DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK
 #define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_DEFVAL             0x00000404
 #define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT              8
 #define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK               0x00000F00U
@@ -5229,9 +5229,9 @@
     *  DFI clock and the memory clock are not phase aligned, this timing param
     * eter should be rounded up to the next integer value.
 */
-#undef DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_DEFVAL 
-#undef DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT 
-#undef DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK 
+#undef DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_DEFVAL
+#undef DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT
+#undef DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK
 #define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_DEFVAL              0x00000404
 #define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT               0
 #define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK                0x0000000FU
@@ -5241,9 +5241,9 @@
     *  Self Refresh, Deep Power Down and Maximum Power Saving modes. DFI 2.1 s
     * pecification onwards, recommends using a fixed value of 7 always.
 */
-#undef DDRC_DFILPCFG0_DFI_TLP_RESP_DEFVAL 
-#undef DDRC_DFILPCFG0_DFI_TLP_RESP_SHIFT 
-#undef DDRC_DFILPCFG0_DFI_TLP_RESP_MASK 
+#undef DDRC_DFILPCFG0_DFI_TLP_RESP_DEFVAL
+#undef DDRC_DFILPCFG0_DFI_TLP_RESP_SHIFT
+#undef DDRC_DFILPCFG0_DFI_TLP_RESP_MASK
 #define DDRC_DFILPCFG0_DFI_TLP_RESP_DEFVAL                     0x07000000
 #define DDRC_DFILPCFG0_DFI_TLP_RESP_SHIFT                      24
 #define DDRC_DFILPCFG0_DFI_TLP_RESP_MASK                       0x0F000000U
@@ -5258,9 +5258,9 @@
     * his is only present for designs supporting mDDR or LPDDR2/LPDDR3 devices
     * .
 */
-#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_DEFVAL 
-#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_SHIFT 
-#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_MASK 
+#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_DEFVAL
+#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_SHIFT
+#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_MASK
 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_DEFVAL                0x07000000
 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_SHIFT                 20
 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_MASK                  0x00F00000U
@@ -5270,9 +5270,9 @@
     * /Exit. - 0 - Disabled - 1 - Enabled This is only present for designs sup
     * porting mDDR or LPDDR2/LPDDR3 devices.
 */
-#undef DDRC_DFILPCFG0_DFI_LP_EN_DPD_DEFVAL 
-#undef DDRC_DFILPCFG0_DFI_LP_EN_DPD_SHIFT 
-#undef DDRC_DFILPCFG0_DFI_LP_EN_DPD_MASK 
+#undef DDRC_DFILPCFG0_DFI_LP_EN_DPD_DEFVAL
+#undef DDRC_DFILPCFG0_DFI_LP_EN_DPD_SHIFT
+#undef DDRC_DFILPCFG0_DFI_LP_EN_DPD_MASK
 #define DDRC_DFILPCFG0_DFI_LP_EN_DPD_DEFVAL                    0x07000000
 #define DDRC_DFILPCFG0_DFI_LP_EN_DPD_SHIFT                     16
 #define DDRC_DFILPCFG0_DFI_LP_EN_DPD_MASK                      0x00010000U
@@ -5285,9 +5285,9 @@
     *  - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 c
     * ycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited
 */
-#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_DEFVAL 
-#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT 
-#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK 
+#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_DEFVAL
+#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT
+#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK
 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_DEFVAL                 0x07000000
 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT                  12
 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK                   0x0000F000U
@@ -5296,9 +5296,9 @@
 * Enables DFI Low Power interface handshaking during Self Refresh Entry/Ex
     * it. - 0 - Disabled - 1 - Enabled
 */
-#undef DDRC_DFILPCFG0_DFI_LP_EN_SR_DEFVAL 
-#undef DDRC_DFILPCFG0_DFI_LP_EN_SR_SHIFT 
-#undef DDRC_DFILPCFG0_DFI_LP_EN_SR_MASK 
+#undef DDRC_DFILPCFG0_DFI_LP_EN_SR_DEFVAL
+#undef DDRC_DFILPCFG0_DFI_LP_EN_SR_SHIFT
+#undef DDRC_DFILPCFG0_DFI_LP_EN_SR_MASK
 #define DDRC_DFILPCFG0_DFI_LP_EN_SR_DEFVAL                     0x07000000
 #define DDRC_DFILPCFG0_DFI_LP_EN_SR_SHIFT                      8
 #define DDRC_DFILPCFG0_DFI_LP_EN_SR_MASK                       0x00000100U
@@ -5311,9 +5311,9 @@
     *  8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cyc
     * les - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited
 */
-#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_DEFVAL 
-#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT 
-#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK 
+#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_DEFVAL
+#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT
+#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK
 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_DEFVAL                 0x07000000
 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT                  4
 #define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK                   0x000000F0U
@@ -5322,9 +5322,9 @@
 * Enables DFI Low Power interface handshaking during Power Down Entry/Exit
     * . - 0 - Disabled - 1 - Enabled
 */
-#undef DDRC_DFILPCFG0_DFI_LP_EN_PD_DEFVAL 
-#undef DDRC_DFILPCFG0_DFI_LP_EN_PD_SHIFT 
-#undef DDRC_DFILPCFG0_DFI_LP_EN_PD_MASK 
+#undef DDRC_DFILPCFG0_DFI_LP_EN_PD_DEFVAL
+#undef DDRC_DFILPCFG0_DFI_LP_EN_PD_SHIFT
+#undef DDRC_DFILPCFG0_DFI_LP_EN_PD_MASK
 #define DDRC_DFILPCFG0_DFI_LP_EN_PD_DEFVAL                     0x07000000
 #define DDRC_DFILPCFG0_DFI_LP_EN_PD_SHIFT                      0
 #define DDRC_DFILPCFG0_DFI_LP_EN_PD_MASK                       0x00000001U
@@ -5338,9 +5338,9 @@
     *  65536 cycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimi
     * ted This is only present for designs supporting DDR4 devices.
 */
-#undef DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_DEFVAL 
-#undef DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_SHIFT 
-#undef DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_MASK 
+#undef DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_DEFVAL
+#undef DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_SHIFT
+#undef DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_MASK
 #define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_DEFVAL               0x00000000
 #define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_SHIFT                4
 #define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_MASK                 0x000000F0U
@@ -5350,9 +5350,9 @@
     * Mode Entry/Exit. - 0 - Disabled - 1 - Enabled This is only present for d
     * esigns supporting DDR4 devices.
 */
-#undef DDRC_DFILPCFG1_DFI_LP_EN_MPSM_DEFVAL 
-#undef DDRC_DFILPCFG1_DFI_LP_EN_MPSM_SHIFT 
-#undef DDRC_DFILPCFG1_DFI_LP_EN_MPSM_MASK 
+#undef DDRC_DFILPCFG1_DFI_LP_EN_MPSM_DEFVAL
+#undef DDRC_DFILPCFG1_DFI_LP_EN_MPSM_SHIFT
+#undef DDRC_DFILPCFG1_DFI_LP_EN_MPSM_MASK
 #define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_DEFVAL                   0x00000000
 #define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_SHIFT                    0
 #define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_MASK                     0x00000001U
@@ -5362,9 +5362,9 @@
     * . The core must issue the dfi_ctrlupd_req signal using register reg_ddrc
     * _ctrlupd. When '0', uMCTL2 issues dfi_ctrlupd_req periodically.
 */
-#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_DEFVAL 
-#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SHIFT 
-#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_MASK 
+#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_DEFVAL
+#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SHIFT
+#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_MASK
 #define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_DEFVAL                   0x00400003
 #define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SHIFT                    31
 #define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_MASK                     0x80000000U
@@ -5375,9 +5375,9 @@
     * signal using register reg_ddrc_ctrlupd. When '0', uMCTL2 issues a dfi_ct
     * rlupd_req after exiting self-refresh.
 */
-#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_DEFVAL 
-#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_SHIFT 
-#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_MASK 
+#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_DEFVAL
+#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_SHIFT
+#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_MASK
 #define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_DEFVAL               0x00400003
 #define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_SHIFT                30
 #define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_MASK                 0x40000000U
@@ -5387,9 +5387,9 @@
     * gnal can assert. Lowest value to assign to this variable is 0x40. Unit:
     * Clocks
 */
-#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_DEFVAL 
-#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_SHIFT 
-#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_MASK 
+#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_DEFVAL
+#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_SHIFT
+#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_MASK
 #define DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_DEFVAL                   0x00400003
 #define DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_SHIFT                    16
 #define DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_MASK                     0x03FF0000U
@@ -5401,9 +5401,9 @@
     * d_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this
     * variable is 0x3. Unit: Clocks
 */
-#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_DEFVAL 
-#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_SHIFT 
-#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_MASK 
+#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_DEFVAL
+#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_SHIFT
+#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_MASK
 #define DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_DEFVAL                   0x00400003
 #define DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_SHIFT                    0
 #define DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_MASK                     0x000003FFU
@@ -5415,9 +5415,9 @@
     * ll impact on the latency of the first read request when the uMCTL2 is id
     * le. Unit: 1024 clocks
 */
-#undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_DEFVAL 
-#undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT 
-#undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK 
+#undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_DEFVAL
+#undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT
+#undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK
 #define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_DEFVAL   0x00000000
 #define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT    16
 #define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK     0x00FF0000U
@@ -5434,9 +5434,9 @@
     *  be greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x1024. Unit: 1024 cl
     * ocks
 */
-#undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_DEFVAL 
-#undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT 
-#undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK 
+#undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_DEFVAL
+#undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT
+#undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK
 #define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_DEFVAL   0x00000000
 #define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT    0
 #define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK     0x000000FFU
@@ -5445,9 +5445,9 @@
 * Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals. - 0: Signal
     * s are active low - 1: Signals are active high
 */
-#undef DDRC_DFIMISC_DFI_DATA_CS_POLARITY_DEFVAL 
-#undef DDRC_DFIMISC_DFI_DATA_CS_POLARITY_SHIFT 
-#undef DDRC_DFIMISC_DFI_DATA_CS_POLARITY_MASK 
+#undef DDRC_DFIMISC_DFI_DATA_CS_POLARITY_DEFVAL
+#undef DDRC_DFIMISC_DFI_DATA_CS_POLARITY_SHIFT
+#undef DDRC_DFIMISC_DFI_DATA_CS_POLARITY_MASK
 #define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_DEFVAL               0x00000001
 #define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_SHIFT                2
 #define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_MASK                 0x00000004U
@@ -5457,9 +5457,9 @@
     *  - 1 - PHY implements DBI functionality. Present only in designs configu
     * red to support DDR4 and LPDDR4.
 */
-#undef DDRC_DFIMISC_PHY_DBI_MODE_DEFVAL 
-#undef DDRC_DFIMISC_PHY_DBI_MODE_SHIFT 
-#undef DDRC_DFIMISC_PHY_DBI_MODE_MASK 
+#undef DDRC_DFIMISC_PHY_DBI_MODE_DEFVAL
+#undef DDRC_DFIMISC_PHY_DBI_MODE_SHIFT
+#undef DDRC_DFIMISC_PHY_DBI_MODE_MASK
 #define DDRC_DFIMISC_PHY_DBI_MODE_DEFVAL                       0x00000001
 #define DDRC_DFIMISC_PHY_DBI_MODE_SHIFT                        1
 #define DDRC_DFIMISC_PHY_DBI_MODE_MASK                         0x00000002U
@@ -5468,9 +5468,9 @@
 * PHY initialization complete enable signal. When asserted the dfi_init_co
     * mplete signal can be used to trigger SDRAM initialisation
 */
-#undef DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_DEFVAL 
-#undef DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT 
-#undef DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_MASK 
+#undef DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_DEFVAL
+#undef DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT
+#undef DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_MASK
 #define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_DEFVAL               0x00000001
 #define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT                0
 #define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_MASK                 0x00000001U
@@ -5481,9 +5481,9 @@
     * s corresponds to the DFI timing parameter tphy_rdcslat. Refer to PHY spe
     * cification for correct value.
 */
-#undef DDRC_DFITMG2_DFI_TPHY_RDCSLAT_DEFVAL 
-#undef DDRC_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT 
-#undef DDRC_DFITMG2_DFI_TPHY_RDCSLAT_MASK 
+#undef DDRC_DFITMG2_DFI_TPHY_RDCSLAT_DEFVAL
+#undef DDRC_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT
+#undef DDRC_DFITMG2_DFI_TPHY_RDCSLAT_MASK
 #define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_DEFVAL                   0x00000202
 #define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT                    8
 #define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_MASK                     0x00003F00U
@@ -5494,9 +5494,9 @@
     * s corresponds to the DFI timing parameter tphy_wrcslat. Refer to PHY spe
     * cification for correct value.
 */
-#undef DDRC_DFITMG2_DFI_TPHY_WRCSLAT_DEFVAL 
-#undef DDRC_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT 
-#undef DDRC_DFITMG2_DFI_TPHY_WRCSLAT_MASK 
+#undef DDRC_DFITMG2_DFI_TPHY_WRCSLAT_DEFVAL
+#undef DDRC_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT
+#undef DDRC_DFITMG2_DFI_TPHY_WRCSLAT_MASK
 #define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_DEFVAL                   0x00000202
 #define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT                    0
 #define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_MASK                     0x0000003FU
@@ -5507,9 +5507,9 @@
     * ister. - DDR4: MR5 bit A12. When x4 devices are used, this signal must b
     * e set to 0. - LPDDR4: MR3[6]
 */
-#undef DDRC_DBICTL_RD_DBI_EN_DEFVAL 
-#undef DDRC_DBICTL_RD_DBI_EN_SHIFT 
-#undef DDRC_DBICTL_RD_DBI_EN_MASK 
+#undef DDRC_DBICTL_RD_DBI_EN_DEFVAL
+#undef DDRC_DBICTL_RD_DBI_EN_SHIFT
+#undef DDRC_DBICTL_RD_DBI_EN_MASK
 #define DDRC_DBICTL_RD_DBI_EN_DEFVAL                           0x00000001
 #define DDRC_DBICTL_RD_DBI_EN_SHIFT                            2
 #define DDRC_DBICTL_RD_DBI_EN_MASK                             0x00000004U
@@ -5520,9 +5520,9 @@
     * register. - DDR4: MR5 bit A11. When x4 devices are used, this signal mus
     * t be set to 0. - LPDDR4: MR3[7]
 */
-#undef DDRC_DBICTL_WR_DBI_EN_DEFVAL 
-#undef DDRC_DBICTL_WR_DBI_EN_SHIFT 
-#undef DDRC_DBICTL_WR_DBI_EN_MASK 
+#undef DDRC_DBICTL_WR_DBI_EN_DEFVAL
+#undef DDRC_DBICTL_WR_DBI_EN_SHIFT
+#undef DDRC_DBICTL_WR_DBI_EN_MASK
 #define DDRC_DBICTL_WR_DBI_EN_DEFVAL                           0x00000001
 #define DDRC_DBICTL_WR_DBI_EN_SHIFT                            1
 #define DDRC_DBICTL_WR_DBI_EN_MASK                             0x00000002U
@@ -5534,9 +5534,9 @@
     * is signal must be set to 0. - LPDDR4: Set this to inverted value of MR13
     * [5] which is opposite polarity from this signal
 */
-#undef DDRC_DBICTL_DM_EN_DEFVAL 
-#undef DDRC_DBICTL_DM_EN_SHIFT 
-#undef DDRC_DBICTL_DM_EN_MASK 
+#undef DDRC_DBICTL_DM_EN_DEFVAL
+#undef DDRC_DBICTL_DM_EN_SHIFT
+#undef DDRC_DBICTL_DM_EN_MASK
 #define DDRC_DBICTL_DM_EN_DEFVAL                               0x00000001
 #define DDRC_DBICTL_DM_EN_SHIFT                                0
 #define DDRC_DBICTL_DM_EN_MASK                                 0x00000001U
@@ -5547,10 +5547,10 @@
     *  by adding the internal base to the value of this field. If set to 31, r
     * ank address bit 0 is set to 0.
 */
-#undef DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_DEFVAL 
-#undef DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT 
-#undef DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_MASK 
-#define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_DEFVAL                   
+#undef DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_DEFVAL
+#undef DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT
+#undef DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_MASK
+#define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_DEFVAL
 #define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT                    0
 #define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_MASK                     0x0000001FU
 
@@ -5560,9 +5560,9 @@
     * by adding the internal base to the value of this field. If set to 31, ba
     * nk address bit 2 is set to 0.
 */
-#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B2_DEFVAL 
-#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT 
-#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B2_MASK 
+#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B2_DEFVAL
+#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT
+#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B2_MASK
 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_DEFVAL                   0x00000000
 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT                    16
 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_MASK                     0x001F0000U
@@ -5573,9 +5573,9 @@
     *  address bits is determined by adding the internal base to the value of
     * this field.
 */
-#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B1_DEFVAL 
-#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT 
-#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B1_MASK 
+#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B1_DEFVAL
+#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT
+#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B1_MASK
 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_DEFVAL                   0x00000000
 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT                    8
 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_MASK                     0x00001F00U
@@ -5586,9 +5586,9 @@
     *  address bits is determined by adding the internal base to the value of
     * this field.
 */
-#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B0_DEFVAL 
-#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT 
-#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B0_MASK 
+#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B0_DEFVAL
+#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT
+#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B0_MASK
 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_DEFVAL                   0x00000000
 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT                    0
 #define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_MASK                     0x0000001FU
@@ -5602,9 +5602,9 @@
     * se to the value of this field. If set to 15, this column address bit is
     * set to 0.
 */
-#undef DDRC_ADDRMAP2_ADDRMAP_COL_B5_DEFVAL 
-#undef DDRC_ADDRMAP2_ADDRMAP_COL_B5_SHIFT 
-#undef DDRC_ADDRMAP2_ADDRMAP_COL_B5_MASK 
+#undef DDRC_ADDRMAP2_ADDRMAP_COL_B5_DEFVAL
+#undef DDRC_ADDRMAP2_ADDRMAP_COL_B5_SHIFT
+#undef DDRC_ADDRMAP2_ADDRMAP_COL_B5_MASK
 #define DDRC_ADDRMAP2_ADDRMAP_COL_B5_DEFVAL                    0x00000000
 #define DDRC_ADDRMAP2_ADDRMAP_COL_B5_SHIFT                     24
 #define DDRC_ADDRMAP2_ADDRMAP_COL_B5_MASK                      0x0F000000U
@@ -5618,9 +5618,9 @@
     * e to the value of this field. If set to 15, this column address bit is s
     * et to 0.
 */
-#undef DDRC_ADDRMAP2_ADDRMAP_COL_B4_DEFVAL 
-#undef DDRC_ADDRMAP2_ADDRMAP_COL_B4_SHIFT 
-#undef DDRC_ADDRMAP2_ADDRMAP_COL_B4_MASK 
+#undef DDRC_ADDRMAP2_ADDRMAP_COL_B4_DEFVAL
+#undef DDRC_ADDRMAP2_ADDRMAP_COL_B4_SHIFT
+#undef DDRC_ADDRMAP2_ADDRMAP_COL_B4_MASK
 #define DDRC_ADDRMAP2_ADDRMAP_COL_B4_DEFVAL                    0x00000000
 #define DDRC_ADDRMAP2_ADDRMAP_COL_B4_SHIFT                     16
 #define DDRC_ADDRMAP2_ADDRMAP_COL_B4_MASK                      0x000F0000U
@@ -5635,9 +5635,9 @@
     * 6, it is required to program this to 0, hence register does not exist in
     *  this case.
 */
-#undef DDRC_ADDRMAP2_ADDRMAP_COL_B3_DEFVAL 
-#undef DDRC_ADDRMAP2_ADDRMAP_COL_B3_SHIFT 
-#undef DDRC_ADDRMAP2_ADDRMAP_COL_B3_MASK 
+#undef DDRC_ADDRMAP2_ADDRMAP_COL_B3_DEFVAL
+#undef DDRC_ADDRMAP2_ADDRMAP_COL_B3_SHIFT
+#undef DDRC_ADDRMAP2_ADDRMAP_COL_B3_MASK
 #define DDRC_ADDRMAP2_ADDRMAP_COL_B3_DEFVAL                    0x00000000
 #define DDRC_ADDRMAP2_ADDRMAP_COL_B3_SHIFT                     8
 #define DDRC_ADDRMAP2_ADDRMAP_COL_B3_MASK                      0x00000F00U
@@ -5651,9 +5651,9 @@
     *  value of this field. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=8
     *  or 16, it is required to program this to 0.
 */
-#undef DDRC_ADDRMAP2_ADDRMAP_COL_B2_DEFVAL 
-#undef DDRC_ADDRMAP2_ADDRMAP_COL_B2_SHIFT 
-#undef DDRC_ADDRMAP2_ADDRMAP_COL_B2_MASK 
+#undef DDRC_ADDRMAP2_ADDRMAP_COL_B2_DEFVAL
+#undef DDRC_ADDRMAP2_ADDRMAP_COL_B2_SHIFT
+#undef DDRC_ADDRMAP2_ADDRMAP_COL_B2_MASK
 #define DDRC_ADDRMAP2_ADDRMAP_COL_B2_DEFVAL                    0x00000000
 #define DDRC_ADDRMAP2_ADDRMAP_COL_B2_SHIFT                     0
 #define DDRC_ADDRMAP2_ADDRMAP_COL_B2_MASK                      0x0000000FU
@@ -5671,9 +5671,9 @@
     * ed to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit
     * for auto-precharge in the CA bus and hence column bit 10 is used.
 */
-#undef DDRC_ADDRMAP3_ADDRMAP_COL_B9_DEFVAL 
-#undef DDRC_ADDRMAP3_ADDRMAP_COL_B9_SHIFT 
-#undef DDRC_ADDRMAP3_ADDRMAP_COL_B9_MASK 
+#undef DDRC_ADDRMAP3_ADDRMAP_COL_B9_DEFVAL
+#undef DDRC_ADDRMAP3_ADDRMAP_COL_B9_SHIFT
+#undef DDRC_ADDRMAP3_ADDRMAP_COL_B9_MASK
 #define DDRC_ADDRMAP3_ADDRMAP_COL_B9_DEFVAL                    0x00000000
 #define DDRC_ADDRMAP3_ADDRMAP_COL_B9_SHIFT                     24
 #define DDRC_ADDRMAP3_ADDRMAP_COL_B9_MASK                      0x0F000000U
@@ -5691,9 +5691,9 @@
     *  In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA
     *  bus and hence column bit 10 is used.
 */
-#undef DDRC_ADDRMAP3_ADDRMAP_COL_B8_DEFVAL 
-#undef DDRC_ADDRMAP3_ADDRMAP_COL_B8_SHIFT 
-#undef DDRC_ADDRMAP3_ADDRMAP_COL_B8_MASK 
+#undef DDRC_ADDRMAP3_ADDRMAP_COL_B8_DEFVAL
+#undef DDRC_ADDRMAP3_ADDRMAP_COL_B8_SHIFT
+#undef DDRC_ADDRMAP3_ADDRMAP_COL_B8_MASK
 #define DDRC_ADDRMAP3_ADDRMAP_COL_B8_DEFVAL                    0x00000000
 #define DDRC_ADDRMAP3_ADDRMAP_COL_B8_SHIFT                     16
 #define DDRC_ADDRMAP3_ADDRMAP_COL_B8_MASK                      0x000F0000U
@@ -5707,9 +5707,9 @@
     * e to the value of this field. If set to 15, this column address bit is s
     * et to 0.
 */
-#undef DDRC_ADDRMAP3_ADDRMAP_COL_B7_DEFVAL 
-#undef DDRC_ADDRMAP3_ADDRMAP_COL_B7_SHIFT 
-#undef DDRC_ADDRMAP3_ADDRMAP_COL_B7_MASK 
+#undef DDRC_ADDRMAP3_ADDRMAP_COL_B7_DEFVAL
+#undef DDRC_ADDRMAP3_ADDRMAP_COL_B7_SHIFT
+#undef DDRC_ADDRMAP3_ADDRMAP_COL_B7_MASK
 #define DDRC_ADDRMAP3_ADDRMAP_COL_B7_DEFVAL                    0x00000000
 #define DDRC_ADDRMAP3_ADDRMAP_COL_B7_SHIFT                     8
 #define DDRC_ADDRMAP3_ADDRMAP_COL_B7_MASK                      0x00000F00U
@@ -5723,9 +5723,9 @@
     * e to the value of this field. If set to 15, this column address bit is s
     * et to 0.
 */
-#undef DDRC_ADDRMAP3_ADDRMAP_COL_B6_DEFVAL 
-#undef DDRC_ADDRMAP3_ADDRMAP_COL_B6_SHIFT 
-#undef DDRC_ADDRMAP3_ADDRMAP_COL_B6_MASK 
+#undef DDRC_ADDRMAP3_ADDRMAP_COL_B6_DEFVAL
+#undef DDRC_ADDRMAP3_ADDRMAP_COL_B6_SHIFT
+#undef DDRC_ADDRMAP3_ADDRMAP_COL_B6_MASK
 #define DDRC_ADDRMAP3_ADDRMAP_COL_B6_DEFVAL                    0x00000000
 #define DDRC_ADDRMAP3_ADDRMAP_COL_B6_SHIFT                     0
 #define DDRC_ADDRMAP3_ADDRMAP_COL_B6_MASK                      0x0000000FU
@@ -5743,9 +5743,9 @@
     * PDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus
     * and hence column bit 10 is used.
 */
-#undef DDRC_ADDRMAP4_ADDRMAP_COL_B11_DEFVAL 
-#undef DDRC_ADDRMAP4_ADDRMAP_COL_B11_SHIFT 
-#undef DDRC_ADDRMAP4_ADDRMAP_COL_B11_MASK 
+#undef DDRC_ADDRMAP4_ADDRMAP_COL_B11_DEFVAL
+#undef DDRC_ADDRMAP4_ADDRMAP_COL_B11_SHIFT
+#undef DDRC_ADDRMAP4_ADDRMAP_COL_B11_MASK
 #define DDRC_ADDRMAP4_ADDRMAP_COL_B11_DEFVAL                   0x00000000
 #define DDRC_ADDRMAP4_ADDRMAP_COL_B11_SHIFT                    8
 #define DDRC_ADDRMAP4_ADDRMAP_COL_B11_MASK                     0x00000F00U
@@ -5763,9 +5763,9 @@
     * to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for
     *  auto-precharge in the CA bus and hence column bit 10 is used.
 */
-#undef DDRC_ADDRMAP4_ADDRMAP_COL_B10_DEFVAL 
-#undef DDRC_ADDRMAP4_ADDRMAP_COL_B10_SHIFT 
-#undef DDRC_ADDRMAP4_ADDRMAP_COL_B10_MASK 
+#undef DDRC_ADDRMAP4_ADDRMAP_COL_B10_DEFVAL
+#undef DDRC_ADDRMAP4_ADDRMAP_COL_B10_SHIFT
+#undef DDRC_ADDRMAP4_ADDRMAP_COL_B10_MASK
 #define DDRC_ADDRMAP4_ADDRMAP_COL_B10_DEFVAL                   0x00000000
 #define DDRC_ADDRMAP4_ADDRMAP_COL_B10_SHIFT                    0
 #define DDRC_ADDRMAP4_ADDRMAP_COL_B10_MASK                     0x0000000FU
@@ -5776,9 +5776,9 @@
     * d by adding the internal base to the value of this field. If set to 15,
     * row address bit 11 is set to 0.
 */
-#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B11_DEFVAL 
-#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT 
-#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B11_MASK 
+#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B11_DEFVAL
+#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT
+#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B11_MASK
 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_DEFVAL                   0x00000000
 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT                    24
 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_MASK                     0x0F000000U
@@ -5792,9 +5792,9 @@
     * ield. When value 15 is used the values of row address bits 2 to 10 are d
     * efined by registers ADDRMAP9, ADDRMAP10, ADDRMAP11.
 */
-#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_DEFVAL 
-#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT 
-#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK 
+#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_DEFVAL
+#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT
+#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK
 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_DEFVAL                 0x00000000
 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT                  16
 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK                   0x000F0000U
@@ -5805,9 +5805,9 @@
     * ddress bits is determined by adding the internal base to the value of th
     * is field.
 */
-#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B1_DEFVAL 
-#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT 
-#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B1_MASK 
+#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B1_DEFVAL
+#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT
+#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B1_MASK
 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_DEFVAL                    0x00000000
 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT                     8
 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_MASK                      0x00000F00U
@@ -5818,9 +5818,9 @@
     * ddress bits is determined by adding the internal base to the value of th
     * is field.
 */
-#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B0_DEFVAL 
-#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT 
-#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B0_MASK 
+#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B0_DEFVAL
+#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT
+#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B0_MASK
 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_DEFVAL                    0x00000000
 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT                     0
 #define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_MASK                      0x0000000FU
@@ -5832,9 +5832,9 @@
     *  All addresses are valid Present only in designs configured to support L
     * PDDR3.
 */
-#undef DDRC_ADDRMAP6_LPDDR3_6GB_12GB_DEFVAL 
-#undef DDRC_ADDRMAP6_LPDDR3_6GB_12GB_SHIFT 
-#undef DDRC_ADDRMAP6_LPDDR3_6GB_12GB_MASK 
+#undef DDRC_ADDRMAP6_LPDDR3_6GB_12GB_DEFVAL
+#undef DDRC_ADDRMAP6_LPDDR3_6GB_12GB_SHIFT
+#undef DDRC_ADDRMAP6_LPDDR3_6GB_12GB_MASK
 #define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_DEFVAL                   0x00000000
 #define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_SHIFT                    31
 #define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_MASK                     0x80000000U
@@ -5845,9 +5845,9 @@
     * d by adding the internal base to the value of this field. If set to 15,
     * row address bit 15 is set to 0.
 */
-#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B15_DEFVAL 
-#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT 
-#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B15_MASK 
+#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B15_DEFVAL
+#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT
+#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B15_MASK
 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_DEFVAL                   0x00000000
 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT                    24
 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_MASK                     0x0F000000U
@@ -5858,9 +5858,9 @@
     * d by adding the internal base to the value of this field. If set to 15,
     * row address bit 14 is set to 0.
 */
-#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B14_DEFVAL 
-#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT 
-#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B14_MASK 
+#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B14_DEFVAL
+#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT
+#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B14_MASK
 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_DEFVAL                   0x00000000
 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT                    16
 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_MASK                     0x000F0000U
@@ -5871,9 +5871,9 @@
     * d by adding the internal base to the value of this field. If set to 15,
     * row address bit 13 is set to 0.
 */
-#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B13_DEFVAL 
-#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT 
-#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B13_MASK 
+#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B13_DEFVAL
+#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT
+#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B13_MASK
 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_DEFVAL                   0x00000000
 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT                    8
 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_MASK                     0x00000F00U
@@ -5884,9 +5884,9 @@
     * d by adding the internal base to the value of this field. If set to 15,
     * row address bit 12 is set to 0.
 */
-#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B12_DEFVAL 
-#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT 
-#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B12_MASK 
+#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B12_DEFVAL
+#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT
+#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B12_MASK
 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_DEFVAL                   0x00000000
 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT                    0
 #define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_MASK                     0x0000000FU
@@ -5897,9 +5897,9 @@
     * d by adding the internal base to the value of this field. If set to 15,
     * row address bit 17 is set to 0.
 */
-#undef DDRC_ADDRMAP7_ADDRMAP_ROW_B17_DEFVAL 
-#undef DDRC_ADDRMAP7_ADDRMAP_ROW_B17_SHIFT 
-#undef DDRC_ADDRMAP7_ADDRMAP_ROW_B17_MASK 
+#undef DDRC_ADDRMAP7_ADDRMAP_ROW_B17_DEFVAL
+#undef DDRC_ADDRMAP7_ADDRMAP_ROW_B17_SHIFT
+#undef DDRC_ADDRMAP7_ADDRMAP_ROW_B17_MASK
 #define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_DEFVAL                   0x00000000
 #define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_SHIFT                    8
 #define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_MASK                     0x00000F00U
@@ -5910,9 +5910,9 @@
     * d by adding the internal base to the value of this field. If set to 15,
     * row address bit 16 is set to 0.
 */
-#undef DDRC_ADDRMAP7_ADDRMAP_ROW_B16_DEFVAL 
-#undef DDRC_ADDRMAP7_ADDRMAP_ROW_B16_SHIFT 
-#undef DDRC_ADDRMAP7_ADDRMAP_ROW_B16_MASK 
+#undef DDRC_ADDRMAP7_ADDRMAP_ROW_B16_DEFVAL
+#undef DDRC_ADDRMAP7_ADDRMAP_ROW_B16_SHIFT
+#undef DDRC_ADDRMAP7_ADDRMAP_ROW_B16_MASK
 #define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_DEFVAL                   0x00000000
 #define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_SHIFT                    0
 #define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_MASK                     0x0000000FU
@@ -5924,9 +5924,9 @@
     * ase to the value of this field. If set to 31, bank group address bit 1 i
     * s set to 0.
 */
-#undef DDRC_ADDRMAP8_ADDRMAP_BG_B1_DEFVAL 
-#undef DDRC_ADDRMAP8_ADDRMAP_BG_B1_SHIFT 
-#undef DDRC_ADDRMAP8_ADDRMAP_BG_B1_MASK 
+#undef DDRC_ADDRMAP8_ADDRMAP_BG_B1_DEFVAL
+#undef DDRC_ADDRMAP8_ADDRMAP_BG_B1_SHIFT
+#undef DDRC_ADDRMAP8_ADDRMAP_BG_B1_MASK
 #define DDRC_ADDRMAP8_ADDRMAP_BG_B1_DEFVAL                     0x00000000
 #define DDRC_ADDRMAP8_ADDRMAP_BG_B1_SHIFT                      8
 #define DDRC_ADDRMAP8_ADDRMAP_BG_B1_MASK                       0x00001F00U
@@ -5937,9 +5937,9 @@
     * e bank group address bits is determined by adding the internal base to t
     * he value of this field.
 */
-#undef DDRC_ADDRMAP8_ADDRMAP_BG_B0_DEFVAL 
-#undef DDRC_ADDRMAP8_ADDRMAP_BG_B0_SHIFT 
-#undef DDRC_ADDRMAP8_ADDRMAP_BG_B0_MASK 
+#undef DDRC_ADDRMAP8_ADDRMAP_BG_B0_DEFVAL
+#undef DDRC_ADDRMAP8_ADDRMAP_BG_B0_SHIFT
+#undef DDRC_ADDRMAP8_ADDRMAP_BG_B0_MASK
 #define DDRC_ADDRMAP8_ADDRMAP_BG_B0_DEFVAL                     0x00000000
 #define DDRC_ADDRMAP8_ADDRMAP_BG_B0_SHIFT                      0
 #define DDRC_ADDRMAP8_ADDRMAP_BG_B0_MASK                       0x0000001FU
@@ -5951,9 +5951,9 @@
     * his field. This register field is used only when ADDRMAP5.addrmap_row_b2
     * _10 is set to value 15.
 */
-#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B5_DEFVAL 
-#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B5_SHIFT 
-#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B5_MASK 
+#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B5_DEFVAL
+#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B5_SHIFT
+#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B5_MASK
 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_DEFVAL                    0x00000000
 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_SHIFT                     24
 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_MASK                      0x0F000000U
@@ -5965,9 +5965,9 @@
     * his field. This register field is used only when ADDRMAP5.addrmap_row_b2
     * _10 is set to value 15.
 */
-#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B4_DEFVAL 
-#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B4_SHIFT 
-#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B4_MASK 
+#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B4_DEFVAL
+#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B4_SHIFT
+#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B4_MASK
 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_DEFVAL                    0x00000000
 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_SHIFT                     16
 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_MASK                      0x000F0000U
@@ -5979,9 +5979,9 @@
     * is field. This register field is used only when ADDRMAP5.addrmap_row_b2_
     * 10 is set to value 15.
 */
-#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B3_DEFVAL 
-#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B3_SHIFT 
-#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B3_MASK 
+#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B3_DEFVAL
+#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B3_SHIFT
+#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B3_MASK
 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_DEFVAL                    0x00000000
 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_SHIFT                     8
 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_MASK                      0x00000F00U
@@ -5993,9 +5993,9 @@
     * is field. This register field is used only when ADDRMAP5.addrmap_row_b2_
     * 10 is set to value 15.
 */
-#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B2_DEFVAL 
-#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B2_SHIFT 
-#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B2_MASK 
+#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B2_DEFVAL
+#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B2_SHIFT
+#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B2_MASK
 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_DEFVAL                    0x00000000
 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_SHIFT                     0
 #define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_MASK                      0x0000000FU
@@ -6007,9 +6007,9 @@
     * his field. This register field is used only when ADDRMAP5.addrmap_row_b2
     * _10 is set to value 15.
 */
-#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B9_DEFVAL 
-#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B9_SHIFT 
-#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B9_MASK 
+#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B9_DEFVAL
+#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B9_SHIFT
+#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B9_MASK
 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_DEFVAL                   0x00000000
 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_SHIFT                    24
 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_MASK                     0x0F000000U
@@ -6021,9 +6021,9 @@
     * his field. This register field is used only when ADDRMAP5.addrmap_row_b2
     * _10 is set to value 15.
 */
-#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B8_DEFVAL 
-#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B8_SHIFT 
-#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B8_MASK 
+#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B8_DEFVAL
+#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B8_SHIFT
+#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B8_MASK
 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_DEFVAL                   0x00000000
 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_SHIFT                    16
 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_MASK                     0x000F0000U
@@ -6035,9 +6035,9 @@
     * his field. This register field is used only when ADDRMAP5.addrmap_row_b2
     * _10 is set to value 15.
 */
-#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B7_DEFVAL 
-#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B7_SHIFT 
-#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B7_MASK 
+#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B7_DEFVAL
+#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B7_SHIFT
+#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B7_MASK
 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_DEFVAL                   0x00000000
 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_SHIFT                    8
 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_MASK                     0x00000F00U
@@ -6049,9 +6049,9 @@
     * his field. This register field is used only when ADDRMAP5.addrmap_row_b2
     * _10 is set to value 15.
 */
-#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B6_DEFVAL 
-#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B6_SHIFT 
-#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B6_MASK 
+#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B6_DEFVAL
+#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B6_SHIFT
+#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B6_MASK
 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_DEFVAL                   0x00000000
 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_SHIFT                    0
 #define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_MASK                     0x0000000FU
@@ -6063,10 +6063,10 @@
     * this field. This register field is used only when ADDRMAP5.addrmap_row_b
     * 2_10 is set to value 15.
 */
-#undef DDRC_ADDRMAP11_ADDRMAP_ROW_B10_DEFVAL 
-#undef DDRC_ADDRMAP11_ADDRMAP_ROW_B10_SHIFT 
-#undef DDRC_ADDRMAP11_ADDRMAP_ROW_B10_MASK 
-#define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_DEFVAL                  
+#undef DDRC_ADDRMAP11_ADDRMAP_ROW_B10_DEFVAL
+#undef DDRC_ADDRMAP11_ADDRMAP_ROW_B10_SHIFT
+#undef DDRC_ADDRMAP11_ADDRMAP_ROW_B10_MASK
+#define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_DEFVAL
 #define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_SHIFT                   0
 #define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_MASK                    0x0000000FU
 
@@ -6078,9 +6078,9 @@
     * EAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) CRC_MODE = 0 (
     * not CRC mode), 1 (CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK)
 */
-#undef DDRC_ODTCFG_WR_ODT_HOLD_DEFVAL 
-#undef DDRC_ODTCFG_WR_ODT_HOLD_SHIFT 
-#undef DDRC_ODTCFG_WR_ODT_HOLD_MASK 
+#undef DDRC_ODTCFG_WR_ODT_HOLD_DEFVAL
+#undef DDRC_ODTCFG_WR_ODT_HOLD_SHIFT
+#undef DDRC_ODTCFG_WR_ODT_HOLD_MASK
 #define DDRC_ODTCFG_WR_ODT_HOLD_DEFVAL                         0x04000400
 #define DDRC_ODTCFG_WR_ODT_HOLD_SHIFT                          24
 #define DDRC_ODTCFG_WR_ODT_HOLD_MASK                           0x0F000000U
@@ -6094,9 +6094,9 @@
     * r write operation. DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust
     * for CAL mode) LPDDR3: - WL - 1 - RU(tODTon(max)/tCK))
 */
-#undef DDRC_ODTCFG_WR_ODT_DELAY_DEFVAL 
-#undef DDRC_ODTCFG_WR_ODT_DELAY_SHIFT 
-#undef DDRC_ODTCFG_WR_ODT_DELAY_MASK 
+#undef DDRC_ODTCFG_WR_ODT_DELAY_DEFVAL
+#undef DDRC_ODTCFG_WR_ODT_DELAY_SHIFT
+#undef DDRC_ODTCFG_WR_ODT_DELAY_MASK
 #define DDRC_ODTCFG_WR_ODT_DELAY_DEFVAL                        0x04000400
 #define DDRC_ODTCFG_WR_ODT_DELAY_SHIFT                         16
 #define DDRC_ODTCFG_WR_ODT_DELAY_MASK                          0x001F0000U
@@ -6109,9 +6109,9 @@
     * reamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) - RD(tDQSCK(min)/tCK) +
     * RU(tODTon(max)/tCK)
 */
-#undef DDRC_ODTCFG_RD_ODT_HOLD_DEFVAL 
-#undef DDRC_ODTCFG_RD_ODT_HOLD_SHIFT 
-#undef DDRC_ODTCFG_RD_ODT_HOLD_MASK 
+#undef DDRC_ODTCFG_RD_ODT_HOLD_DEFVAL
+#undef DDRC_ODTCFG_RD_ODT_HOLD_SHIFT
+#undef DDRC_ODTCFG_RD_ODT_HOLD_MASK
 #define DDRC_ODTCFG_RD_ODT_HOLD_DEFVAL                         0x04000400
 #define DDRC_ODTCFG_RD_ODT_HOLD_SHIFT                          8
 #define DDRC_ODTCFG_RD_ODT_HOLD_MASK                           0x00000F00U
@@ -6129,9 +6129,9 @@
     * pport ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - R
     * U(tODTon(max)/tCK)
 */
-#undef DDRC_ODTCFG_RD_ODT_DELAY_DEFVAL 
-#undef DDRC_ODTCFG_RD_ODT_DELAY_SHIFT 
-#undef DDRC_ODTCFG_RD_ODT_DELAY_MASK 
+#undef DDRC_ODTCFG_RD_ODT_DELAY_DEFVAL
+#undef DDRC_ODTCFG_RD_ODT_DELAY_SHIFT
+#undef DDRC_ODTCFG_RD_ODT_DELAY_MASK
 #define DDRC_ODTCFG_RD_ODT_DELAY_DEFVAL                        0x04000400
 #define DDRC_ODTCFG_RD_ODT_DELAY_SHIFT                         2
 #define DDRC_ODTCFG_RD_ODT_DELAY_MASK                          0x0000007CU
@@ -6144,9 +6144,9 @@
     * 1 to enable its ODT. Present only in configurations that have 2 or more
     * ranks
 */
-#undef DDRC_ODTMAP_RANK1_RD_ODT_DEFVAL 
-#undef DDRC_ODTMAP_RANK1_RD_ODT_SHIFT 
-#undef DDRC_ODTMAP_RANK1_RD_ODT_MASK 
+#undef DDRC_ODTMAP_RANK1_RD_ODT_DEFVAL
+#undef DDRC_ODTMAP_RANK1_RD_ODT_SHIFT
+#undef DDRC_ODTMAP_RANK1_RD_ODT_MASK
 #define DDRC_ODTMAP_RANK1_RD_ODT_DEFVAL                        0x00002211
 #define DDRC_ODTMAP_RANK1_RD_ODT_SHIFT                         12
 #define DDRC_ODTMAP_RANK1_RD_ODT_MASK                          0x00003000U
@@ -6159,9 +6159,9 @@
     *  to enable its ODT. Present only in configurations that have 2 or more r
     * anks
 */
-#undef DDRC_ODTMAP_RANK1_WR_ODT_DEFVAL 
-#undef DDRC_ODTMAP_RANK1_WR_ODT_SHIFT 
-#undef DDRC_ODTMAP_RANK1_WR_ODT_MASK 
+#undef DDRC_ODTMAP_RANK1_WR_ODT_DEFVAL
+#undef DDRC_ODTMAP_RANK1_WR_ODT_SHIFT
+#undef DDRC_ODTMAP_RANK1_WR_ODT_MASK
 #define DDRC_ODTMAP_RANK1_WR_ODT_DEFVAL                        0x00002211
 #define DDRC_ODTMAP_RANK1_WR_ODT_SHIFT                         8
 #define DDRC_ODTMAP_RANK1_WR_ODT_MASK                          0x00000300U
@@ -6173,9 +6173,9 @@
     * s controlled by bit next to the LSB, etc. For each rank, set its bit to
     * 1 to enable its ODT.
 */
-#undef DDRC_ODTMAP_RANK0_RD_ODT_DEFVAL 
-#undef DDRC_ODTMAP_RANK0_RD_ODT_SHIFT 
-#undef DDRC_ODTMAP_RANK0_RD_ODT_MASK 
+#undef DDRC_ODTMAP_RANK0_RD_ODT_DEFVAL
+#undef DDRC_ODTMAP_RANK0_RD_ODT_SHIFT
+#undef DDRC_ODTMAP_RANK0_RD_ODT_MASK
 #define DDRC_ODTMAP_RANK0_RD_ODT_DEFVAL                        0x00002211
 #define DDRC_ODTMAP_RANK0_RD_ODT_SHIFT                         4
 #define DDRC_ODTMAP_RANK0_RD_ODT_MASK                          0x00000030U
@@ -6187,9 +6187,9 @@
     *  controlled by bit next to the LSB, etc. For each rank, set its bit to 1
     *  to enable its ODT.
 */
-#undef DDRC_ODTMAP_RANK0_WR_ODT_DEFVAL 
-#undef DDRC_ODTMAP_RANK0_WR_ODT_SHIFT 
-#undef DDRC_ODTMAP_RANK0_WR_ODT_MASK 
+#undef DDRC_ODTMAP_RANK0_WR_ODT_DEFVAL
+#undef DDRC_ODTMAP_RANK0_WR_ODT_SHIFT
+#undef DDRC_ODTMAP_RANK0_WR_ODT_MASK
 #define DDRC_ODTMAP_RANK0_WR_ODT_DEFVAL                        0x00002211
 #define DDRC_ODTMAP_RANK0_WR_ODT_SHIFT                         0
 #define DDRC_ODTMAP_RANK0_WR_ODT_MASK                          0x00000003U
@@ -6204,9 +6204,9 @@
     * ing will happen immediately when the switching conditions become true. F
     * OR PERFORMANCE ONLY
 */
-#undef DDRC_SCHED_RDWR_IDLE_GAP_DEFVAL 
-#undef DDRC_SCHED_RDWR_IDLE_GAP_SHIFT 
-#undef DDRC_SCHED_RDWR_IDLE_GAP_MASK 
+#undef DDRC_SCHED_RDWR_IDLE_GAP_DEFVAL
+#undef DDRC_SCHED_RDWR_IDLE_GAP_SHIFT
+#undef DDRC_SCHED_RDWR_IDLE_GAP_MASK
 #define DDRC_SCHED_RDWR_IDLE_GAP_DEFVAL                        0x00002005
 #define DDRC_SCHED_RDWR_IDLE_GAP_SHIFT                         24
 #define DDRC_SCHED_RDWR_IDLE_GAP_MASK                          0x7F000000U
@@ -6214,9 +6214,9 @@
 /*
 * UNUSED
 */
-#undef DDRC_SCHED_GO2CRITICAL_HYSTERESIS_DEFVAL 
-#undef DDRC_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT 
-#undef DDRC_SCHED_GO2CRITICAL_HYSTERESIS_MASK 
+#undef DDRC_SCHED_GO2CRITICAL_HYSTERESIS_DEFVAL
+#undef DDRC_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT
+#undef DDRC_SCHED_GO2CRITICAL_HYSTERESIS_MASK
 #define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_DEFVAL               0x00002005
 #define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT                16
 #define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_MASK                 0x00FF0000U
@@ -6233,9 +6233,9 @@
     * ow-priority read CAMs for storing the RMW requests arising out of single
     *  bit error correction RMW operation.
 */
-#undef DDRC_SCHED_LPR_NUM_ENTRIES_DEFVAL 
-#undef DDRC_SCHED_LPR_NUM_ENTRIES_SHIFT 
-#undef DDRC_SCHED_LPR_NUM_ENTRIES_MASK 
+#undef DDRC_SCHED_LPR_NUM_ENTRIES_DEFVAL
+#undef DDRC_SCHED_LPR_NUM_ENTRIES_SHIFT
+#undef DDRC_SCHED_LPR_NUM_ENTRIES_MASK
 #define DDRC_SCHED_LPR_NUM_ENTRIES_DEFVAL                      0x00002005
 #define DDRC_SCHED_LPR_NUM_ENTRIES_SHIFT                       8
 #define DDRC_SCHED_LPR_NUM_ENTRIES_MASK                        0x00003F00U
@@ -6256,9 +6256,9 @@
     * The pageclose feature provids a midway between Open and Close page polic
     * ies. FOR PERFORMANCE ONLY.
 */
-#undef DDRC_SCHED_PAGECLOSE_DEFVAL 
-#undef DDRC_SCHED_PAGECLOSE_SHIFT 
-#undef DDRC_SCHED_PAGECLOSE_MASK 
+#undef DDRC_SCHED_PAGECLOSE_DEFVAL
+#undef DDRC_SCHED_PAGECLOSE_SHIFT
+#undef DDRC_SCHED_PAGECLOSE_MASK
 #define DDRC_SCHED_PAGECLOSE_DEFVAL                            0x00002005
 #define DDRC_SCHED_PAGECLOSE_SHIFT                             2
 #define DDRC_SCHED_PAGECLOSE_MASK                              0x00000004U
@@ -6266,9 +6266,9 @@
 /*
 * If set then the bank selector prefers writes over reads. FOR DEBUG ONLY.
 */
-#undef DDRC_SCHED_PREFER_WRITE_DEFVAL 
-#undef DDRC_SCHED_PREFER_WRITE_SHIFT 
-#undef DDRC_SCHED_PREFER_WRITE_MASK 
+#undef DDRC_SCHED_PREFER_WRITE_DEFVAL
+#undef DDRC_SCHED_PREFER_WRITE_SHIFT
+#undef DDRC_SCHED_PREFER_WRITE_MASK
 #define DDRC_SCHED_PREFER_WRITE_DEFVAL                         0x00002005
 #define DDRC_SCHED_PREFER_WRITE_SHIFT                          1
 #define DDRC_SCHED_PREFER_WRITE_MASK                           0x00000002U
@@ -6282,9 +6282,9 @@
     * ng the incoming transactions to low priority implicitly turns off Bypass
     *  path for read commands. FOR PERFORMANCE ONLY.
 */
-#undef DDRC_SCHED_FORCE_LOW_PRI_N_DEFVAL 
-#undef DDRC_SCHED_FORCE_LOW_PRI_N_SHIFT 
-#undef DDRC_SCHED_FORCE_LOW_PRI_N_MASK 
+#undef DDRC_SCHED_FORCE_LOW_PRI_N_DEFVAL
+#undef DDRC_SCHED_FORCE_LOW_PRI_N_SHIFT
+#undef DDRC_SCHED_FORCE_LOW_PRI_N_MASK
 #define DDRC_SCHED_FORCE_LOW_PRI_N_DEFVAL                      0x00002005
 #define DDRC_SCHED_FORCE_LOW_PRI_N_SHIFT                       0
 #define DDRC_SCHED_FORCE_LOW_PRI_N_MASK                        0x00000001U
@@ -6294,9 +6294,9 @@
     * l is the smaller of: - (a) This number - (b) Number of transactions avai
     * lable. Unit: Transaction. FOR PERFORMANCE ONLY.
 */
-#undef DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_DEFVAL 
-#undef DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT 
-#undef DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK 
+#undef DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_DEFVAL
+#undef DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT
+#undef DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK
 #define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_DEFVAL               0x0F00007F
 #define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT                24
 #define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK                 0xFF000000U
@@ -6308,9 +6308,9 @@
     * operation, this function should not be disabled as it will cause excessi
     * ve latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY.
 */
-#undef DDRC_PERFLPR1_LPR_MAX_STARVE_DEFVAL 
-#undef DDRC_PERFLPR1_LPR_MAX_STARVE_SHIFT 
-#undef DDRC_PERFLPR1_LPR_MAX_STARVE_MASK 
+#undef DDRC_PERFLPR1_LPR_MAX_STARVE_DEFVAL
+#undef DDRC_PERFLPR1_LPR_MAX_STARVE_SHIFT
+#undef DDRC_PERFLPR1_LPR_MAX_STARVE_MASK
 #define DDRC_PERFLPR1_LPR_MAX_STARVE_DEFVAL                    0x0F00007F
 #define DDRC_PERFLPR1_LPR_MAX_STARVE_SHIFT                     0
 #define DDRC_PERFLPR1_LPR_MAX_STARVE_MASK                      0x0000FFFFU
@@ -6320,9 +6320,9 @@
     *  is the smaller of: - (a) This number - (b) Number of transactions avail
     * able. Unit: Transaction. FOR PERFORMANCE ONLY.
 */
-#undef DDRC_PERFWR1_W_XACT_RUN_LENGTH_DEFVAL 
-#undef DDRC_PERFWR1_W_XACT_RUN_LENGTH_SHIFT 
-#undef DDRC_PERFWR1_W_XACT_RUN_LENGTH_MASK 
+#undef DDRC_PERFWR1_W_XACT_RUN_LENGTH_DEFVAL
+#undef DDRC_PERFWR1_W_XACT_RUN_LENGTH_SHIFT
+#undef DDRC_PERFWR1_W_XACT_RUN_LENGTH_MASK
 #define DDRC_PERFWR1_W_XACT_RUN_LENGTH_DEFVAL                  0x0F00007F
 #define DDRC_PERFWR1_W_XACT_RUN_LENGTH_SHIFT                   24
 #define DDRC_PERFWR1_W_XACT_RUN_LENGTH_MASK                    0xFF000000U
@@ -6334,9 +6334,9 @@
     * peration, this function should not be disabled as it will cause excessiv
     * e latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY.
 */
-#undef DDRC_PERFWR1_W_MAX_STARVE_DEFVAL 
-#undef DDRC_PERFWR1_W_MAX_STARVE_SHIFT 
-#undef DDRC_PERFWR1_W_MAX_STARVE_MASK 
+#undef DDRC_PERFWR1_W_MAX_STARVE_DEFVAL
+#undef DDRC_PERFWR1_W_MAX_STARVE_SHIFT
+#undef DDRC_PERFWR1_W_MAX_STARVE_MASK
 #define DDRC_PERFWR1_W_MAX_STARVE_DEFVAL                       0x0F00007F
 #define DDRC_PERFWR1_W_MAX_STARVE_SHIFT                        0
 #define DDRC_PERFWR1_W_MAX_STARVE_MASK                         0x0000FFFFU
@@ -6345,9 +6345,9 @@
 * DQ nibble map for DQ bits [12-15] Present only in designs configured to
     * support DDR4.
 */
-#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_DEFVAL 
-#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_SHIFT 
-#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_MASK 
+#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_DEFVAL
+#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_SHIFT
+#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_MASK
 #define DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_DEFVAL                 0x00000000
 #define DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_SHIFT                  24
 #define DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_MASK                   0xFF000000U
@@ -6356,9 +6356,9 @@
 * DQ nibble map for DQ bits [8-11] Present only in designs configured to s
     * upport DDR4.
 */
-#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_DEFVAL 
-#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_SHIFT 
-#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_MASK 
+#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_DEFVAL
+#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_SHIFT
+#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_MASK
 #define DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_DEFVAL                  0x00000000
 #define DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_SHIFT                   16
 #define DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_MASK                    0x00FF0000U
@@ -6367,9 +6367,9 @@
 * DQ nibble map for DQ bits [4-7] Present only in designs configured to su
     * pport DDR4.
 */
-#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_DEFVAL 
-#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_SHIFT 
-#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_MASK 
+#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_DEFVAL
+#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_SHIFT
+#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_MASK
 #define DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_DEFVAL                   0x00000000
 #define DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_SHIFT                    8
 #define DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_MASK                     0x0000FF00U
@@ -6378,9 +6378,9 @@
 * DQ nibble map for DQ bits [0-3] Present only in designs configured to su
     * pport DDR4.
 */
-#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_DEFVAL 
-#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_SHIFT 
-#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_MASK 
+#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_DEFVAL
+#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_SHIFT
+#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_MASK
 #define DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_DEFVAL                   0x00000000
 #define DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_SHIFT                    0
 #define DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_MASK                     0x000000FFU
@@ -6389,9 +6389,9 @@
 * DQ nibble map for DQ bits [28-31] Present only in designs configured to
     * support DDR4.
 */
-#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_DEFVAL 
-#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_SHIFT 
-#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_MASK 
+#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_DEFVAL
+#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_SHIFT
+#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_MASK
 #define DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_DEFVAL                 0x00000000
 #define DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_SHIFT                  24
 #define DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_MASK                   0xFF000000U
@@ -6400,9 +6400,9 @@
 * DQ nibble map for DQ bits [24-27] Present only in designs configured to
     * support DDR4.
 */
-#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_DEFVAL 
-#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_SHIFT 
-#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_MASK 
+#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_DEFVAL
+#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_SHIFT
+#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_MASK
 #define DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_DEFVAL                 0x00000000
 #define DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_SHIFT                  16
 #define DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_MASK                   0x00FF0000U
@@ -6411,9 +6411,9 @@
 * DQ nibble map for DQ bits [20-23] Present only in designs configured to
     * support DDR4.
 */
-#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_DEFVAL 
-#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_SHIFT 
-#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_MASK 
+#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_DEFVAL
+#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_SHIFT
+#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_MASK
 #define DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_DEFVAL                 0x00000000
 #define DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_SHIFT                  8
 #define DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_MASK                   0x0000FF00U
@@ -6422,9 +6422,9 @@
 * DQ nibble map for DQ bits [16-19] Present only in designs configured to
     * support DDR4.
 */
-#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_DEFVAL 
-#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_SHIFT 
-#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_MASK 
+#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_DEFVAL
+#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_SHIFT
+#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_MASK
 #define DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_DEFVAL                 0x00000000
 #define DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_SHIFT                  0
 #define DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_MASK                   0x000000FFU
@@ -6433,9 +6433,9 @@
 * DQ nibble map for DQ bits [44-47] Present only in designs configured to
     * support DDR4.
 */
-#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_DEFVAL 
-#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_SHIFT 
-#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_MASK 
+#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_DEFVAL
+#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_SHIFT
+#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_MASK
 #define DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_DEFVAL                 0x00000000
 #define DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_SHIFT                  24
 #define DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_MASK                   0xFF000000U
@@ -6444,9 +6444,9 @@
 * DQ nibble map for DQ bits [40-43] Present only in designs configured to
     * support DDR4.
 */
-#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_DEFVAL 
-#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_SHIFT 
-#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_MASK 
+#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_DEFVAL
+#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_SHIFT
+#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_MASK
 #define DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_DEFVAL                 0x00000000
 #define DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_SHIFT                  16
 #define DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_MASK                   0x00FF0000U
@@ -6455,9 +6455,9 @@
 * DQ nibble map for DQ bits [36-39] Present only in designs configured to
     * support DDR4.
 */
-#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_DEFVAL 
-#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_SHIFT 
-#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_MASK 
+#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_DEFVAL
+#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_SHIFT
+#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_MASK
 #define DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_DEFVAL                 0x00000000
 #define DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_SHIFT                  8
 #define DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_MASK                   0x0000FF00U
@@ -6466,9 +6466,9 @@
 * DQ nibble map for DQ bits [32-35] Present only in designs configured to
     * support DDR4.
 */
-#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_DEFVAL 
-#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_SHIFT 
-#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_MASK 
+#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_DEFVAL
+#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_SHIFT
+#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_MASK
 #define DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_DEFVAL                 0x00000000
 #define DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_SHIFT                  0
 #define DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_MASK                   0x000000FFU
@@ -6477,9 +6477,9 @@
 * DQ nibble map for DQ bits [60-63] Present only in designs configured to
     * support DDR4.
 */
-#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_DEFVAL 
-#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_SHIFT 
-#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_MASK 
+#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_DEFVAL
+#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_SHIFT
+#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_MASK
 #define DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_DEFVAL                 0x00000000
 #define DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_SHIFT                  24
 #define DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_MASK                   0xFF000000U
@@ -6488,9 +6488,9 @@
 * DQ nibble map for DQ bits [56-59] Present only in designs configured to
     * support DDR4.
 */
-#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_DEFVAL 
-#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_SHIFT 
-#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_MASK 
+#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_DEFVAL
+#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_SHIFT
+#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_MASK
 #define DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_DEFVAL                 0x00000000
 #define DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_SHIFT                  16
 #define DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_MASK                   0x00FF0000U
@@ -6499,9 +6499,9 @@
 * DQ nibble map for DQ bits [52-55] Present only in designs configured to
     * support DDR4.
 */
-#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_DEFVAL 
-#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_SHIFT 
-#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_MASK 
+#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_DEFVAL
+#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_SHIFT
+#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_MASK
 #define DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_DEFVAL                 0x00000000
 #define DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_SHIFT                  8
 #define DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_MASK                   0x0000FF00U
@@ -6510,9 +6510,9 @@
 * DQ nibble map for DQ bits [48-51] Present only in designs configured to
     * support DDR4.
 */
-#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_DEFVAL 
-#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_SHIFT 
-#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_MASK 
+#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_DEFVAL
+#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_SHIFT
+#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_MASK
 #define DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_DEFVAL                 0x00000000
 #define DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_SHIFT                  0
 #define DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_MASK                   0x000000FFU
@@ -6521,9 +6521,9 @@
 * DQ nibble map for DIMM ECC check bits [4-7] Present only in designs conf
     * igured to support DDR4.
 */
-#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_DEFVAL 
-#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_SHIFT 
-#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_MASK 
+#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_DEFVAL
+#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_SHIFT
+#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_MASK
 #define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_DEFVAL                0x00000000
 #define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_SHIFT                 8
 #define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_MASK                  0x0000FF00U
@@ -6532,9 +6532,9 @@
 * DQ nibble map for DIMM ECC check bits [0-3] Present only in designs conf
     * igured to support DDR4.
 */
-#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_DEFVAL 
-#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_SHIFT 
-#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_MASK 
+#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_DEFVAL
+#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_SHIFT
+#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_MASK
 #define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_DEFVAL                0x00000000
 #define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_SHIFT                 0
 #define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_MASK                  0x000000FFU
@@ -6547,10 +6547,10 @@
     * sed DQ swapping 0: Enable rank based DQ swapping Present only in designs
     *  configured to support DDR4.
 */
-#undef DDRC_DQMAP5_DIS_DQ_RANK_SWAP_DEFVAL 
-#undef DDRC_DQMAP5_DIS_DQ_RANK_SWAP_SHIFT 
-#undef DDRC_DQMAP5_DIS_DQ_RANK_SWAP_MASK 
-#define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_DEFVAL                    
+#undef DDRC_DQMAP5_DIS_DQ_RANK_SWAP_DEFVAL
+#undef DDRC_DQMAP5_DIS_DQ_RANK_SWAP_SHIFT
+#undef DDRC_DQMAP5_DIS_DQ_RANK_SWAP_MASK
+#define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_DEFVAL
 #define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_SHIFT                     0
 #define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_MASK                      0x00000001U
 
@@ -6562,9 +6562,9 @@
     * parisons exclude the two address bits representing critical word). FOR D
     * EBUG ONLY.
 */
-#undef DDRC_DBG0_DIS_COLLISION_PAGE_OPT_DEFVAL 
-#undef DDRC_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT 
-#undef DDRC_DBG0_DIS_COLLISION_PAGE_OPT_MASK 
+#undef DDRC_DBG0_DIS_COLLISION_PAGE_OPT_DEFVAL
+#undef DDRC_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT
+#undef DDRC_DBG0_DIS_COLLISION_PAGE_OPT_MASK
 #define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_DEFVAL                0x00000000
 #define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT                 4
 #define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_MASK                  0x00000010U
@@ -6572,9 +6572,9 @@
 /*
 * When 1, disable write combine. FOR DEBUG ONLY
 */
-#undef DDRC_DBG0_DIS_WC_DEFVAL 
-#undef DDRC_DBG0_DIS_WC_SHIFT 
-#undef DDRC_DBG0_DIS_WC_MASK 
+#undef DDRC_DBG0_DIS_WC_DEFVAL
+#undef DDRC_DBG0_DIS_WC_SHIFT
+#undef DDRC_DBG0_DIS_WC_MASK
 #define DDRC_DBG0_DIS_WC_DEFVAL                                0x00000000
 #define DDRC_DBG0_DIS_WC_SHIFT                                 0
 #define DDRC_DBG0_DIS_WC_MASK                                  0x00000001U
@@ -6590,9 +6590,9 @@
     *  and may only be changed when the DDRC reset signal, core_ddrc_rstn, is
     * asserted (0).
 */
-#undef DDRC_DBGCMD_HW_REF_ZQ_EN_DEFVAL 
-#undef DDRC_DBGCMD_HW_REF_ZQ_EN_SHIFT 
-#undef DDRC_DBGCMD_HW_REF_ZQ_EN_MASK 
+#undef DDRC_DBGCMD_HW_REF_ZQ_EN_DEFVAL
+#undef DDRC_DBGCMD_HW_REF_ZQ_EN_SHIFT
+#undef DDRC_DBGCMD_HW_REF_ZQ_EN_MASK
 #define DDRC_DBGCMD_HW_REF_ZQ_EN_DEFVAL                        0x00000000
 #define DDRC_DBGCMD_HW_REF_ZQ_EN_SHIFT                         31
 #define DDRC_DBGCMD_HW_REF_ZQ_EN_MASK                          0x80000000U
@@ -6603,9 +6603,9 @@
     *  is automatically cleared. This operation must only be performed when DF
     * IUPD0.dis_auto_ctrlupd=1.
 */
-#undef DDRC_DBGCMD_CTRLUPD_DEFVAL 
-#undef DDRC_DBGCMD_CTRLUPD_SHIFT 
-#undef DDRC_DBGCMD_CTRLUPD_MASK 
+#undef DDRC_DBGCMD_CTRLUPD_DEFVAL
+#undef DDRC_DBGCMD_CTRLUPD_SHIFT
+#undef DDRC_DBGCMD_CTRLUPD_MASK
 #define DDRC_DBGCMD_CTRLUPD_DEFVAL                             0x00000000
 #define DDRC_DBGCMD_CTRLUPD_SHIFT                              5
 #define DDRC_DBGCMD_CTRLUPD_MASK                               0x00000020U
@@ -6620,9 +6620,9 @@
     * (LPDDR4) and Deep power-down operating modes and Maximum Power Saving Mo
     * de.
 */
-#undef DDRC_DBGCMD_ZQ_CALIB_SHORT_DEFVAL 
-#undef DDRC_DBGCMD_ZQ_CALIB_SHORT_SHIFT 
-#undef DDRC_DBGCMD_ZQ_CALIB_SHORT_MASK 
+#undef DDRC_DBGCMD_ZQ_CALIB_SHORT_DEFVAL
+#undef DDRC_DBGCMD_ZQ_CALIB_SHORT_SHIFT
+#undef DDRC_DBGCMD_ZQ_CALIB_SHORT_MASK
 #define DDRC_DBGCMD_ZQ_CALIB_SHORT_DEFVAL                      0x00000000
 #define DDRC_DBGCMD_ZQ_CALIB_SHORT_SHIFT                       4
 #define DDRC_DBGCMD_ZQ_CALIB_SHORT_MASK                        0x00000010U
@@ -6635,9 +6635,9 @@
     * auto_refresh=1. It is recommended NOT to set this register bit if in Ini
     * t or Deep power-down operating modes or Maximum Power Saving Mode.
 */
-#undef DDRC_DBGCMD_RANK1_REFRESH_DEFVAL 
-#undef DDRC_DBGCMD_RANK1_REFRESH_SHIFT 
-#undef DDRC_DBGCMD_RANK1_REFRESH_MASK 
+#undef DDRC_DBGCMD_RANK1_REFRESH_DEFVAL
+#undef DDRC_DBGCMD_RANK1_REFRESH_SHIFT
+#undef DDRC_DBGCMD_RANK1_REFRESH_MASK
 #define DDRC_DBGCMD_RANK1_REFRESH_DEFVAL                       0x00000000
 #define DDRC_DBGCMD_RANK1_REFRESH_SHIFT                        1
 #define DDRC_DBGCMD_RANK1_REFRESH_MASK                         0x00000002U
@@ -6650,9 +6650,9 @@
     * auto_refresh=1. It is recommended NOT to set this register bit if in Ini
     * t or Deep power-down operating modes or Maximum Power Saving Mode.
 */
-#undef DDRC_DBGCMD_RANK0_REFRESH_DEFVAL 
-#undef DDRC_DBGCMD_RANK0_REFRESH_SHIFT 
-#undef DDRC_DBGCMD_RANK0_REFRESH_MASK 
+#undef DDRC_DBGCMD_RANK0_REFRESH_DEFVAL
+#undef DDRC_DBGCMD_RANK0_REFRESH_SHIFT
+#undef DDRC_DBGCMD_RANK0_REFRESH_MASK
 #define DDRC_DBGCMD_RANK0_REFRESH_DEFVAL                       0x00000000
 #define DDRC_DBGCMD_RANK0_REFRESH_SHIFT                        0
 #define DDRC_DBGCMD_RANK0_REFRESH_MASK                         0x00000001U
@@ -6662,10 +6662,10 @@
     * r to 0 to enable quasi-dynamic programming. Set back register to 1 once
     * programming is done.
 */
-#undef DDRC_SWCTL_SW_DONE_DEFVAL 
-#undef DDRC_SWCTL_SW_DONE_SHIFT 
-#undef DDRC_SWCTL_SW_DONE_MASK 
-#define DDRC_SWCTL_SW_DONE_DEFVAL                              
+#undef DDRC_SWCTL_SW_DONE_DEFVAL
+#undef DDRC_SWCTL_SW_DONE_SHIFT
+#undef DDRC_SWCTL_SW_DONE_MASK
+#define DDRC_SWCTL_SW_DONE_DEFVAL
 #define DDRC_SWCTL_SW_DONE_SHIFT                               0
 #define DDRC_SWCTL_SW_DONE_MASK                                0x00000001U
 
@@ -6686,9 +6686,9 @@
     * CTL1.reg_ddrc_crc_enable=1 Functionality is also not supported if Shared
     * -AC is enabled
 */
-#undef DDRC_PCCFG_BL_EXP_MODE_DEFVAL 
-#undef DDRC_PCCFG_BL_EXP_MODE_SHIFT 
-#undef DDRC_PCCFG_BL_EXP_MODE_MASK 
+#undef DDRC_PCCFG_BL_EXP_MODE_DEFVAL
+#undef DDRC_PCCFG_BL_EXP_MODE_SHIFT
+#undef DDRC_PCCFG_BL_EXP_MODE_MASK
 #define DDRC_PCCFG_BL_EXP_MODE_DEFVAL                          0x00000000
 #define DDRC_PCCFG_BL_EXP_MODE_SHIFT                           8
 #define DDRC_PCCFG_BL_EXP_MODE_MASK                            0x00000100U
@@ -6699,9 +6699,9 @@
     *  when Page Match feature is enabled. If set to 0, there is no limit impo
     * sed on number of consecutive same page DDRC transactions.
 */
-#undef DDRC_PCCFG_PAGEMATCH_LIMIT_DEFVAL 
-#undef DDRC_PCCFG_PAGEMATCH_LIMIT_SHIFT 
-#undef DDRC_PCCFG_PAGEMATCH_LIMIT_MASK 
+#undef DDRC_PCCFG_PAGEMATCH_LIMIT_DEFVAL
+#undef DDRC_PCCFG_PAGEMATCH_LIMIT_SHIFT
+#undef DDRC_PCCFG_PAGEMATCH_LIMIT_MASK
 #define DDRC_PCCFG_PAGEMATCH_LIMIT_DEFVAL                      0x00000000
 #define DDRC_PCCFG_PAGEMATCH_LIMIT_SHIFT                       4
 #define DDRC_PCCFG_PAGEMATCH_LIMIT_MASK                        0x00000010U
@@ -6713,9 +6713,9 @@
     * go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals a
     * t DDRC are driven to 1b'0.
 */
-#undef DDRC_PCCFG_GO2CRITICAL_EN_DEFVAL 
-#undef DDRC_PCCFG_GO2CRITICAL_EN_SHIFT 
-#undef DDRC_PCCFG_GO2CRITICAL_EN_MASK 
+#undef DDRC_PCCFG_GO2CRITICAL_EN_DEFVAL
+#undef DDRC_PCCFG_GO2CRITICAL_EN_SHIFT
+#undef DDRC_PCCFG_GO2CRITICAL_EN_MASK
 #define DDRC_PCCFG_GO2CRITICAL_EN_DEFVAL                       0x00000000
 #define DDRC_PCCFG_GO2CRITICAL_EN_SHIFT                        0
 #define DDRC_PCCFG_GO2CRITICAL_EN_MASK                         0x00000001U
@@ -6726,9 +6726,9 @@
     *  immediate commands are to the same memory page (same bank and same row)
     * . See also related PCCFG.pagematch_limit register.
 */
-#undef DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_DEFVAL 
-#undef DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_SHIFT 
-#undef DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_MASK 
+#undef DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_DEFVAL
+#undef DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_SHIFT
+#undef DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_MASK
 #define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_DEFVAL               0x00000000
 #define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_SHIFT                14
 #define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_MASK                 0x00004000U
@@ -6742,9 +6742,9 @@
     * ndependent of address handshaking (it is not associated with any particu
     * lar command).
 */
-#undef DDRC_PCFGR_0_RD_PORT_URGENT_EN_DEFVAL 
-#undef DDRC_PCFGR_0_RD_PORT_URGENT_EN_SHIFT 
-#undef DDRC_PCFGR_0_RD_PORT_URGENT_EN_MASK 
+#undef DDRC_PCFGR_0_RD_PORT_URGENT_EN_DEFVAL
+#undef DDRC_PCFGR_0_RD_PORT_URGENT_EN_SHIFT
+#undef DDRC_PCFGR_0_RD_PORT_URGENT_EN_MASK
 #define DDRC_PCFGR_0_RD_PORT_URGENT_EN_DEFVAL                  0x00000000
 #define DDRC_PCFGR_0_RD_PORT_URGENT_EN_SHIFT                   13
 #define DDRC_PCFGR_0_RD_PORT_URGENT_EN_MASK                    0x00002000U
@@ -6752,9 +6752,9 @@
 /*
 * If set to 1, enables aging function for the read channel of the port.
 */
-#undef DDRC_PCFGR_0_RD_PORT_AGING_EN_DEFVAL 
-#undef DDRC_PCFGR_0_RD_PORT_AGING_EN_SHIFT 
-#undef DDRC_PCFGR_0_RD_PORT_AGING_EN_MASK 
+#undef DDRC_PCFGR_0_RD_PORT_AGING_EN_DEFVAL
+#undef DDRC_PCFGR_0_RD_PORT_AGING_EN_SHIFT
+#undef DDRC_PCFGR_0_RD_PORT_AGING_EN_MASK
 #define DDRC_PCFGR_0_RD_PORT_AGING_EN_DEFVAL                   0x00000000
 #define DDRC_PCFGR_0_RD_PORT_AGING_EN_SHIFT                    12
 #define DDRC_PCFGR_0_RD_PORT_AGING_EN_MASK                     0x00001000U
@@ -6778,9 +6778,9 @@
     * ity read - HPR) on a command by command basis. Note: The two LSBs of thi
     * s register field are tied internally to 2'b00.
 */
-#undef DDRC_PCFGR_0_RD_PORT_PRIORITY_DEFVAL 
-#undef DDRC_PCFGR_0_RD_PORT_PRIORITY_SHIFT 
-#undef DDRC_PCFGR_0_RD_PORT_PRIORITY_MASK 
+#undef DDRC_PCFGR_0_RD_PORT_PRIORITY_DEFVAL
+#undef DDRC_PCFGR_0_RD_PORT_PRIORITY_SHIFT
+#undef DDRC_PCFGR_0_RD_PORT_PRIORITY_MASK
 #define DDRC_PCFGR_0_RD_PORT_PRIORITY_DEFVAL                   0x00000000
 #define DDRC_PCFGR_0_RD_PORT_PRIORITY_SHIFT                    0
 #define DDRC_PCFGR_0_RD_PORT_PRIORITY_MASK                     0x000003FFU
@@ -6791,9 +6791,9 @@
     *  immediate commands are to the same memory page (same bank and same row)
     * . See also related PCCFG.pagematch_limit register.
 */
-#undef DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_DEFVAL 
-#undef DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_SHIFT 
-#undef DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_MASK 
+#undef DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_DEFVAL
+#undef DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_SHIFT
+#undef DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_MASK
 #define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_DEFVAL               0x00004000
 #define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_SHIFT                14
 #define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_MASK                 0x00004000U
@@ -6806,9 +6806,9 @@
     * serted anytime and as long as required which is independent of address h
     * andshaking (it is not associated with any particular command).
 */
-#undef DDRC_PCFGW_0_WR_PORT_URGENT_EN_DEFVAL 
-#undef DDRC_PCFGW_0_WR_PORT_URGENT_EN_SHIFT 
-#undef DDRC_PCFGW_0_WR_PORT_URGENT_EN_MASK 
+#undef DDRC_PCFGW_0_WR_PORT_URGENT_EN_DEFVAL
+#undef DDRC_PCFGW_0_WR_PORT_URGENT_EN_SHIFT
+#undef DDRC_PCFGW_0_WR_PORT_URGENT_EN_MASK
 #define DDRC_PCFGW_0_WR_PORT_URGENT_EN_DEFVAL                  0x00004000
 #define DDRC_PCFGW_0_WR_PORT_URGENT_EN_SHIFT                   13
 #define DDRC_PCFGW_0_WR_PORT_URGENT_EN_MASK                    0x00002000U
@@ -6816,9 +6816,9 @@
 /*
 * If set to 1, enables aging function for the write channel of the port.
 */
-#undef DDRC_PCFGW_0_WR_PORT_AGING_EN_DEFVAL 
-#undef DDRC_PCFGW_0_WR_PORT_AGING_EN_SHIFT 
-#undef DDRC_PCFGW_0_WR_PORT_AGING_EN_MASK 
+#undef DDRC_PCFGW_0_WR_PORT_AGING_EN_DEFVAL
+#undef DDRC_PCFGW_0_WR_PORT_AGING_EN_SHIFT
+#undef DDRC_PCFGW_0_WR_PORT_AGING_EN_MASK
 #define DDRC_PCFGW_0_WR_PORT_AGING_EN_DEFVAL                   0x00004000
 #define DDRC_PCFGW_0_WR_PORT_AGING_EN_SHIFT                    12
 #define DDRC_PCFGW_0_WR_PORT_AGING_EN_MASK                     0x00001000U
@@ -6839,9 +6839,9 @@
     *  direction switching. Note: The two LSBs of this register field are tied
     *  internally to 2'b00.
 */
-#undef DDRC_PCFGW_0_WR_PORT_PRIORITY_DEFVAL 
-#undef DDRC_PCFGW_0_WR_PORT_PRIORITY_SHIFT 
-#undef DDRC_PCFGW_0_WR_PORT_PRIORITY_MASK 
+#undef DDRC_PCFGW_0_WR_PORT_PRIORITY_DEFVAL
+#undef DDRC_PCFGW_0_WR_PORT_PRIORITY_SHIFT
+#undef DDRC_PCFGW_0_WR_PORT_PRIORITY_MASK
 #define DDRC_PCFGW_0_WR_PORT_PRIORITY_DEFVAL                   0x00004000
 #define DDRC_PCFGW_0_WR_PORT_PRIORITY_SHIFT                    0
 #define DDRC_PCFGW_0_WR_PORT_PRIORITY_MASK                     0x000003FFU
@@ -6849,10 +6849,10 @@
 /*
 * Enables port n.
 */
-#undef DDRC_PCTRL_0_PORT_EN_DEFVAL 
-#undef DDRC_PCTRL_0_PORT_EN_SHIFT 
-#undef DDRC_PCTRL_0_PORT_EN_MASK 
-#define DDRC_PCTRL_0_PORT_EN_DEFVAL                            
+#undef DDRC_PCTRL_0_PORT_EN_DEFVAL
+#undef DDRC_PCTRL_0_PORT_EN_SHIFT
+#undef DDRC_PCTRL_0_PORT_EN_MASK
+#define DDRC_PCTRL_0_PORT_EN_DEFVAL
 #define DDRC_PCTRL_0_PORT_EN_SHIFT                             0
 #define DDRC_PCTRL_0_PORT_EN_MASK                              0x00000001U
 
@@ -6864,9 +6864,9 @@
     * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR
     * traffic.
 */
-#undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_DEFVAL 
-#undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_SHIFT 
-#undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_MASK 
+#undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_DEFVAL
+#undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_SHIFT
+#undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_MASK
 #define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_DEFVAL                0x00000000
 #define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_SHIFT                 20
 #define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_MASK                  0x00300000U
@@ -6879,9 +6879,9 @@
     * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR
     * traffic.
 */
-#undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_DEFVAL 
-#undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_SHIFT 
-#undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_MASK 
+#undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_DEFVAL
+#undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_SHIFT
+#undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_MASK
 #define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_DEFVAL                0x00000000
 #define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_SHIFT                 16
 #define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_MASK                  0x00030000U
@@ -6894,9 +6894,9 @@
     * rresponds to higher port priority. All of the map_level* registers must
     * be set to distinct values.
 */
-#undef DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_DEFVAL 
-#undef DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_SHIFT 
-#undef DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_MASK 
+#undef DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_DEFVAL
+#undef DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_SHIFT
+#undef DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_MASK
 #define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_DEFVAL                 0x00000000
 #define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_SHIFT                  0
 #define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_MASK                   0x0000000FU
@@ -6905,9 +6905,9 @@
 * Specifies the timeout value for transactions mapped to the red address q
     * ueue.
 */
-#undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_DEFVAL 
-#undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_SHIFT 
-#undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_MASK 
+#undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_DEFVAL
+#undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_SHIFT
+#undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_MASK
 #define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_DEFVAL               0x00000000
 #define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_SHIFT                16
 #define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_MASK                 0x07FF0000U
@@ -6916,9 +6916,9 @@
 * Specifies the timeout value for transactions mapped to the blue address
     * queue.
 */
-#undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_DEFVAL 
-#undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_SHIFT 
-#undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_MASK 
+#undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_DEFVAL
+#undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_SHIFT
+#undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_MASK
 #define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_DEFVAL               0x00000000
 #define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_SHIFT                0
 #define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_MASK                 0x000007FFU
@@ -6929,9 +6929,9 @@
     *  immediate commands are to the same memory page (same bank and same row)
     * . See also related PCCFG.pagematch_limit register.
 */
-#undef DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_DEFVAL 
-#undef DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_SHIFT 
-#undef DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_MASK 
+#undef DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_DEFVAL
+#undef DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_SHIFT
+#undef DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_MASK
 #define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_DEFVAL               0x00000000
 #define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_SHIFT                14
 #define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_MASK                 0x00004000U
@@ -6945,9 +6945,9 @@
     * ndependent of address handshaking (it is not associated with any particu
     * lar command).
 */
-#undef DDRC_PCFGR_1_RD_PORT_URGENT_EN_DEFVAL 
-#undef DDRC_PCFGR_1_RD_PORT_URGENT_EN_SHIFT 
-#undef DDRC_PCFGR_1_RD_PORT_URGENT_EN_MASK 
+#undef DDRC_PCFGR_1_RD_PORT_URGENT_EN_DEFVAL
+#undef DDRC_PCFGR_1_RD_PORT_URGENT_EN_SHIFT
+#undef DDRC_PCFGR_1_RD_PORT_URGENT_EN_MASK
 #define DDRC_PCFGR_1_RD_PORT_URGENT_EN_DEFVAL                  0x00000000
 #define DDRC_PCFGR_1_RD_PORT_URGENT_EN_SHIFT                   13
 #define DDRC_PCFGR_1_RD_PORT_URGENT_EN_MASK                    0x00002000U
@@ -6955,9 +6955,9 @@
 /*
 * If set to 1, enables aging function for the read channel of the port.
 */
-#undef DDRC_PCFGR_1_RD_PORT_AGING_EN_DEFVAL 
-#undef DDRC_PCFGR_1_RD_PORT_AGING_EN_SHIFT 
-#undef DDRC_PCFGR_1_RD_PORT_AGING_EN_MASK 
+#undef DDRC_PCFGR_1_RD_PORT_AGING_EN_DEFVAL
+#undef DDRC_PCFGR_1_RD_PORT_AGING_EN_SHIFT
+#undef DDRC_PCFGR_1_RD_PORT_AGING_EN_MASK
 #define DDRC_PCFGR_1_RD_PORT_AGING_EN_DEFVAL                   0x00000000
 #define DDRC_PCFGR_1_RD_PORT_AGING_EN_SHIFT                    12
 #define DDRC_PCFGR_1_RD_PORT_AGING_EN_MASK                     0x00001000U
@@ -6981,9 +6981,9 @@
     * ity read - HPR) on a command by command basis. Note: The two LSBs of thi
     * s register field are tied internally to 2'b00.
 */
-#undef DDRC_PCFGR_1_RD_PORT_PRIORITY_DEFVAL 
-#undef DDRC_PCFGR_1_RD_PORT_PRIORITY_SHIFT 
-#undef DDRC_PCFGR_1_RD_PORT_PRIORITY_MASK 
+#undef DDRC_PCFGR_1_RD_PORT_PRIORITY_DEFVAL
+#undef DDRC_PCFGR_1_RD_PORT_PRIORITY_SHIFT
+#undef DDRC_PCFGR_1_RD_PORT_PRIORITY_MASK
 #define DDRC_PCFGR_1_RD_PORT_PRIORITY_DEFVAL                   0x00000000
 #define DDRC_PCFGR_1_RD_PORT_PRIORITY_SHIFT                    0
 #define DDRC_PCFGR_1_RD_PORT_PRIORITY_MASK                     0x000003FFU
@@ -6994,9 +6994,9 @@
     *  immediate commands are to the same memory page (same bank and same row)
     * . See also related PCCFG.pagematch_limit register.
 */
-#undef DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_DEFVAL 
-#undef DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_SHIFT 
-#undef DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_MASK 
+#undef DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_DEFVAL
+#undef DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_SHIFT
+#undef DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_MASK
 #define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_DEFVAL               0x00004000
 #define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_SHIFT                14
 #define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_MASK                 0x00004000U
@@ -7009,9 +7009,9 @@
     * serted anytime and as long as required which is independent of address h
     * andshaking (it is not associated with any particular command).
 */
-#undef DDRC_PCFGW_1_WR_PORT_URGENT_EN_DEFVAL 
-#undef DDRC_PCFGW_1_WR_PORT_URGENT_EN_SHIFT 
-#undef DDRC_PCFGW_1_WR_PORT_URGENT_EN_MASK 
+#undef DDRC_PCFGW_1_WR_PORT_URGENT_EN_DEFVAL
+#undef DDRC_PCFGW_1_WR_PORT_URGENT_EN_SHIFT
+#undef DDRC_PCFGW_1_WR_PORT_URGENT_EN_MASK
 #define DDRC_PCFGW_1_WR_PORT_URGENT_EN_DEFVAL                  0x00004000
 #define DDRC_PCFGW_1_WR_PORT_URGENT_EN_SHIFT                   13
 #define DDRC_PCFGW_1_WR_PORT_URGENT_EN_MASK                    0x00002000U
@@ -7019,9 +7019,9 @@
 /*
 * If set to 1, enables aging function for the write channel of the port.
 */
-#undef DDRC_PCFGW_1_WR_PORT_AGING_EN_DEFVAL 
-#undef DDRC_PCFGW_1_WR_PORT_AGING_EN_SHIFT 
-#undef DDRC_PCFGW_1_WR_PORT_AGING_EN_MASK 
+#undef DDRC_PCFGW_1_WR_PORT_AGING_EN_DEFVAL
+#undef DDRC_PCFGW_1_WR_PORT_AGING_EN_SHIFT
+#undef DDRC_PCFGW_1_WR_PORT_AGING_EN_MASK
 #define DDRC_PCFGW_1_WR_PORT_AGING_EN_DEFVAL                   0x00004000
 #define DDRC_PCFGW_1_WR_PORT_AGING_EN_SHIFT                    12
 #define DDRC_PCFGW_1_WR_PORT_AGING_EN_MASK                     0x00001000U
@@ -7042,9 +7042,9 @@
     *  direction switching. Note: The two LSBs of this register field are tied
     *  internally to 2'b00.
 */
-#undef DDRC_PCFGW_1_WR_PORT_PRIORITY_DEFVAL 
-#undef DDRC_PCFGW_1_WR_PORT_PRIORITY_SHIFT 
-#undef DDRC_PCFGW_1_WR_PORT_PRIORITY_MASK 
+#undef DDRC_PCFGW_1_WR_PORT_PRIORITY_DEFVAL
+#undef DDRC_PCFGW_1_WR_PORT_PRIORITY_SHIFT
+#undef DDRC_PCFGW_1_WR_PORT_PRIORITY_MASK
 #define DDRC_PCFGW_1_WR_PORT_PRIORITY_DEFVAL                   0x00004000
 #define DDRC_PCFGW_1_WR_PORT_PRIORITY_SHIFT                    0
 #define DDRC_PCFGW_1_WR_PORT_PRIORITY_MASK                     0x000003FFU
@@ -7052,10 +7052,10 @@
 /*
 * Enables port n.
 */
-#undef DDRC_PCTRL_1_PORT_EN_DEFVAL 
-#undef DDRC_PCTRL_1_PORT_EN_SHIFT 
-#undef DDRC_PCTRL_1_PORT_EN_MASK 
-#define DDRC_PCTRL_1_PORT_EN_DEFVAL                            
+#undef DDRC_PCTRL_1_PORT_EN_DEFVAL
+#undef DDRC_PCTRL_1_PORT_EN_SHIFT
+#undef DDRC_PCTRL_1_PORT_EN_MASK
+#define DDRC_PCTRL_1_PORT_EN_DEFVAL
 #define DDRC_PCTRL_1_PORT_EN_SHIFT                             0
 #define DDRC_PCTRL_1_PORT_EN_MASK                              0x00000001U
 
@@ -7066,9 +7066,9 @@
     *  = 0) and traffic class of region2 is set to 1 (VPR), VPR traffic is ali
     * ased to LPR traffic.
 */
-#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_DEFVAL 
-#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_SHIFT 
-#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_MASK 
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_DEFVAL
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_SHIFT
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_MASK
 #define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_DEFVAL                0x02000E00
 #define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_SHIFT                 24
 #define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_MASK                  0x03000000U
@@ -7081,9 +7081,9 @@
     * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR
     * traffic.
 */
-#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_DEFVAL 
-#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_SHIFT 
-#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_MASK 
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_DEFVAL
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_SHIFT
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_MASK
 #define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_DEFVAL                0x02000E00
 #define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_SHIFT                 20
 #define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_MASK                  0x00300000U
@@ -7096,9 +7096,9 @@
     * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR
     * traffic.
 */
-#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_DEFVAL 
-#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_SHIFT 
-#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_MASK 
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_DEFVAL
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_SHIFT
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_MASK
 #define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_DEFVAL                0x02000E00
 #define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_SHIFT                 16
 #define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_MASK                  0x00030000U
@@ -7111,9 +7111,9 @@
     * he higher the value corresponds to higher port priority. All of the map_
     * level* registers must be set to distinct values.
 */
-#undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_DEFVAL 
-#undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_SHIFT 
-#undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_MASK 
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_DEFVAL
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_SHIFT
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_MASK
 #define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_DEFVAL                 0x02000E00
 #define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_SHIFT                  8
 #define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_MASK                   0x00000F00U
@@ -7126,9 +7126,9 @@
     * rresponds to higher port priority. All of the map_level* registers must
     * be set to distinct values.
 */
-#undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_DEFVAL 
-#undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_SHIFT 
-#undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_MASK 
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_DEFVAL
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_SHIFT
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_MASK
 #define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_DEFVAL                 0x02000E00
 #define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_SHIFT                  0
 #define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_MASK                   0x0000000FU
@@ -7137,9 +7137,9 @@
 * Specifies the timeout value for transactions mapped to the red address q
     * ueue.
 */
-#undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_DEFVAL 
-#undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_SHIFT 
-#undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_MASK 
+#undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_DEFVAL
+#undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_SHIFT
+#undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_MASK
 #define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_DEFVAL               0x00000000
 #define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_SHIFT                16
 #define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_MASK                 0x07FF0000U
@@ -7148,9 +7148,9 @@
 * Specifies the timeout value for transactions mapped to the blue address
     * queue.
 */
-#undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_DEFVAL 
-#undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_SHIFT 
-#undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_MASK 
+#undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_DEFVAL
+#undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_SHIFT
+#undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_MASK
 #define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_DEFVAL               0x00000000
 #define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_SHIFT                0
 #define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_MASK                 0x000007FFU
@@ -7161,9 +7161,9 @@
     *  immediate commands are to the same memory page (same bank and same row)
     * . See also related PCCFG.pagematch_limit register.
 */
-#undef DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_DEFVAL 
-#undef DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_SHIFT 
-#undef DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_MASK 
+#undef DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_DEFVAL
+#undef DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_SHIFT
+#undef DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_MASK
 #define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_DEFVAL               0x00000000
 #define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_SHIFT                14
 #define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_MASK                 0x00004000U
@@ -7177,9 +7177,9 @@
     * ndependent of address handshaking (it is not associated with any particu
     * lar command).
 */
-#undef DDRC_PCFGR_2_RD_PORT_URGENT_EN_DEFVAL 
-#undef DDRC_PCFGR_2_RD_PORT_URGENT_EN_SHIFT 
-#undef DDRC_PCFGR_2_RD_PORT_URGENT_EN_MASK 
+#undef DDRC_PCFGR_2_RD_PORT_URGENT_EN_DEFVAL
+#undef DDRC_PCFGR_2_RD_PORT_URGENT_EN_SHIFT
+#undef DDRC_PCFGR_2_RD_PORT_URGENT_EN_MASK
 #define DDRC_PCFGR_2_RD_PORT_URGENT_EN_DEFVAL                  0x00000000
 #define DDRC_PCFGR_2_RD_PORT_URGENT_EN_SHIFT                   13
 #define DDRC_PCFGR_2_RD_PORT_URGENT_EN_MASK                    0x00002000U
@@ -7187,9 +7187,9 @@
 /*
 * If set to 1, enables aging function for the read channel of the port.
 */
-#undef DDRC_PCFGR_2_RD_PORT_AGING_EN_DEFVAL 
-#undef DDRC_PCFGR_2_RD_PORT_AGING_EN_SHIFT 
-#undef DDRC_PCFGR_2_RD_PORT_AGING_EN_MASK 
+#undef DDRC_PCFGR_2_RD_PORT_AGING_EN_DEFVAL
+#undef DDRC_PCFGR_2_RD_PORT_AGING_EN_SHIFT
+#undef DDRC_PCFGR_2_RD_PORT_AGING_EN_MASK
 #define DDRC_PCFGR_2_RD_PORT_AGING_EN_DEFVAL                   0x00000000
 #define DDRC_PCFGR_2_RD_PORT_AGING_EN_SHIFT                    12
 #define DDRC_PCFGR_2_RD_PORT_AGING_EN_MASK                     0x00001000U
@@ -7213,9 +7213,9 @@
     * ity read - HPR) on a command by command basis. Note: The two LSBs of thi
     * s register field are tied internally to 2'b00.
 */
-#undef DDRC_PCFGR_2_RD_PORT_PRIORITY_DEFVAL 
-#undef DDRC_PCFGR_2_RD_PORT_PRIORITY_SHIFT 
-#undef DDRC_PCFGR_2_RD_PORT_PRIORITY_MASK 
+#undef DDRC_PCFGR_2_RD_PORT_PRIORITY_DEFVAL
+#undef DDRC_PCFGR_2_RD_PORT_PRIORITY_SHIFT
+#undef DDRC_PCFGR_2_RD_PORT_PRIORITY_MASK
 #define DDRC_PCFGR_2_RD_PORT_PRIORITY_DEFVAL                   0x00000000
 #define DDRC_PCFGR_2_RD_PORT_PRIORITY_SHIFT                    0
 #define DDRC_PCFGR_2_RD_PORT_PRIORITY_MASK                     0x000003FFU
@@ -7226,9 +7226,9 @@
     *  immediate commands are to the same memory page (same bank and same row)
     * . See also related PCCFG.pagematch_limit register.
 */
-#undef DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_DEFVAL 
-#undef DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_SHIFT 
-#undef DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_MASK 
+#undef DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_DEFVAL
+#undef DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_SHIFT
+#undef DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_MASK
 #define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_DEFVAL               0x00004000
 #define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_SHIFT                14
 #define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_MASK                 0x00004000U
@@ -7241,9 +7241,9 @@
     * serted anytime and as long as required which is independent of address h
     * andshaking (it is not associated with any particular command).
 */
-#undef DDRC_PCFGW_2_WR_PORT_URGENT_EN_DEFVAL 
-#undef DDRC_PCFGW_2_WR_PORT_URGENT_EN_SHIFT 
-#undef DDRC_PCFGW_2_WR_PORT_URGENT_EN_MASK 
+#undef DDRC_PCFGW_2_WR_PORT_URGENT_EN_DEFVAL
+#undef DDRC_PCFGW_2_WR_PORT_URGENT_EN_SHIFT
+#undef DDRC_PCFGW_2_WR_PORT_URGENT_EN_MASK
 #define DDRC_PCFGW_2_WR_PORT_URGENT_EN_DEFVAL                  0x00004000
 #define DDRC_PCFGW_2_WR_PORT_URGENT_EN_SHIFT                   13
 #define DDRC_PCFGW_2_WR_PORT_URGENT_EN_MASK                    0x00002000U
@@ -7251,9 +7251,9 @@
 /*
 * If set to 1, enables aging function for the write channel of the port.
 */
-#undef DDRC_PCFGW_2_WR_PORT_AGING_EN_DEFVAL 
-#undef DDRC_PCFGW_2_WR_PORT_AGING_EN_SHIFT 
-#undef DDRC_PCFGW_2_WR_PORT_AGING_EN_MASK 
+#undef DDRC_PCFGW_2_WR_PORT_AGING_EN_DEFVAL
+#undef DDRC_PCFGW_2_WR_PORT_AGING_EN_SHIFT
+#undef DDRC_PCFGW_2_WR_PORT_AGING_EN_MASK
 #define DDRC_PCFGW_2_WR_PORT_AGING_EN_DEFVAL                   0x00004000
 #define DDRC_PCFGW_2_WR_PORT_AGING_EN_SHIFT                    12
 #define DDRC_PCFGW_2_WR_PORT_AGING_EN_MASK                     0x00001000U
@@ -7274,9 +7274,9 @@
     *  direction switching. Note: The two LSBs of this register field are tied
     *  internally to 2'b00.
 */
-#undef DDRC_PCFGW_2_WR_PORT_PRIORITY_DEFVAL 
-#undef DDRC_PCFGW_2_WR_PORT_PRIORITY_SHIFT 
-#undef DDRC_PCFGW_2_WR_PORT_PRIORITY_MASK 
+#undef DDRC_PCFGW_2_WR_PORT_PRIORITY_DEFVAL
+#undef DDRC_PCFGW_2_WR_PORT_PRIORITY_SHIFT
+#undef DDRC_PCFGW_2_WR_PORT_PRIORITY_MASK
 #define DDRC_PCFGW_2_WR_PORT_PRIORITY_DEFVAL                   0x00004000
 #define DDRC_PCFGW_2_WR_PORT_PRIORITY_SHIFT                    0
 #define DDRC_PCFGW_2_WR_PORT_PRIORITY_MASK                     0x000003FFU
@@ -7284,10 +7284,10 @@
 /*
 * Enables port n.
 */
-#undef DDRC_PCTRL_2_PORT_EN_DEFVAL 
-#undef DDRC_PCTRL_2_PORT_EN_SHIFT 
-#undef DDRC_PCTRL_2_PORT_EN_MASK 
-#define DDRC_PCTRL_2_PORT_EN_DEFVAL                            
+#undef DDRC_PCTRL_2_PORT_EN_DEFVAL
+#undef DDRC_PCTRL_2_PORT_EN_SHIFT
+#undef DDRC_PCTRL_2_PORT_EN_MASK
+#define DDRC_PCTRL_2_PORT_EN_DEFVAL
 #define DDRC_PCTRL_2_PORT_EN_SHIFT                             0
 #define DDRC_PCTRL_2_PORT_EN_MASK                              0x00000001U
 
@@ -7298,9 +7298,9 @@
     *  = 0) and traffic class of region2 is set to 1 (VPR), VPR traffic is ali
     * ased to LPR traffic.
 */
-#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_DEFVAL 
-#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_SHIFT 
-#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_MASK 
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_DEFVAL
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_SHIFT
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_MASK
 #define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_DEFVAL                0x02000E00
 #define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_SHIFT                 24
 #define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_MASK                  0x03000000U
@@ -7313,9 +7313,9 @@
     * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR
     * traffic.
 */
-#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_DEFVAL 
-#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_SHIFT 
-#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_MASK 
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_DEFVAL
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_SHIFT
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_MASK
 #define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_DEFVAL                0x02000E00
 #define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_SHIFT                 20
 #define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_MASK                  0x00300000U
@@ -7328,9 +7328,9 @@
     * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR
     * traffic.
 */
-#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_DEFVAL 
-#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_SHIFT 
-#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_MASK 
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_DEFVAL
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_SHIFT
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_MASK
 #define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_DEFVAL                0x02000E00
 #define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_SHIFT                 16
 #define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_MASK                  0x00030000U
@@ -7343,9 +7343,9 @@
     * he higher the value corresponds to higher port priority. All of the map_
     * level* registers must be set to distinct values.
 */
-#undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_DEFVAL 
-#undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_SHIFT 
-#undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_MASK 
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_DEFVAL
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_SHIFT
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_MASK
 #define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_DEFVAL                 0x02000E00
 #define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_SHIFT                  8
 #define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_MASK                   0x00000F00U
@@ -7358,9 +7358,9 @@
     * rresponds to higher port priority. All of the map_level* registers must
     * be set to distinct values.
 */
-#undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_DEFVAL 
-#undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_SHIFT 
-#undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_MASK 
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_DEFVAL
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_SHIFT
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_MASK
 #define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_DEFVAL                 0x02000E00
 #define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_SHIFT                  0
 #define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_MASK                   0x0000000FU
@@ -7369,9 +7369,9 @@
 * Specifies the timeout value for transactions mapped to the red address q
     * ueue.
 */
-#undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_DEFVAL 
-#undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_SHIFT 
-#undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_MASK 
+#undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_DEFVAL
+#undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_SHIFT
+#undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_MASK
 #define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_DEFVAL               0x00000000
 #define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_SHIFT                16
 #define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_MASK                 0x07FF0000U
@@ -7380,9 +7380,9 @@
 * Specifies the timeout value for transactions mapped to the blue address
     * queue.
 */
-#undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_DEFVAL 
-#undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_SHIFT 
-#undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_MASK 
+#undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_DEFVAL
+#undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_SHIFT
+#undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_MASK
 #define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_DEFVAL               0x00000000
 #define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_SHIFT                0
 #define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_MASK                 0x000007FFU
@@ -7393,9 +7393,9 @@
     *  immediate commands are to the same memory page (same bank and same row)
     * . See also related PCCFG.pagematch_limit register.
 */
-#undef DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_DEFVAL 
-#undef DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_SHIFT 
-#undef DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_MASK 
+#undef DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_DEFVAL
+#undef DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_SHIFT
+#undef DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_MASK
 #define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_DEFVAL               0x00000000
 #define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_SHIFT                14
 #define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_MASK                 0x00004000U
@@ -7409,9 +7409,9 @@
     * ndependent of address handshaking (it is not associated with any particu
     * lar command).
 */
-#undef DDRC_PCFGR_3_RD_PORT_URGENT_EN_DEFVAL 
-#undef DDRC_PCFGR_3_RD_PORT_URGENT_EN_SHIFT 
-#undef DDRC_PCFGR_3_RD_PORT_URGENT_EN_MASK 
+#undef DDRC_PCFGR_3_RD_PORT_URGENT_EN_DEFVAL
+#undef DDRC_PCFGR_3_RD_PORT_URGENT_EN_SHIFT
+#undef DDRC_PCFGR_3_RD_PORT_URGENT_EN_MASK
 #define DDRC_PCFGR_3_RD_PORT_URGENT_EN_DEFVAL                  0x00000000
 #define DDRC_PCFGR_3_RD_PORT_URGENT_EN_SHIFT                   13
 #define DDRC_PCFGR_3_RD_PORT_URGENT_EN_MASK                    0x00002000U
@@ -7419,9 +7419,9 @@
 /*
 * If set to 1, enables aging function for the read channel of the port.
 */
-#undef DDRC_PCFGR_3_RD_PORT_AGING_EN_DEFVAL 
-#undef DDRC_PCFGR_3_RD_PORT_AGING_EN_SHIFT 
-#undef DDRC_PCFGR_3_RD_PORT_AGING_EN_MASK 
+#undef DDRC_PCFGR_3_RD_PORT_AGING_EN_DEFVAL
+#undef DDRC_PCFGR_3_RD_PORT_AGING_EN_SHIFT
+#undef DDRC_PCFGR_3_RD_PORT_AGING_EN_MASK
 #define DDRC_PCFGR_3_RD_PORT_AGING_EN_DEFVAL                   0x00000000
 #define DDRC_PCFGR_3_RD_PORT_AGING_EN_SHIFT                    12
 #define DDRC_PCFGR_3_RD_PORT_AGING_EN_MASK                     0x00001000U
@@ -7445,9 +7445,9 @@
     * ity read - HPR) on a command by command basis. Note: The two LSBs of thi
     * s register field are tied internally to 2'b00.
 */
-#undef DDRC_PCFGR_3_RD_PORT_PRIORITY_DEFVAL 
-#undef DDRC_PCFGR_3_RD_PORT_PRIORITY_SHIFT 
-#undef DDRC_PCFGR_3_RD_PORT_PRIORITY_MASK 
+#undef DDRC_PCFGR_3_RD_PORT_PRIORITY_DEFVAL
+#undef DDRC_PCFGR_3_RD_PORT_PRIORITY_SHIFT
+#undef DDRC_PCFGR_3_RD_PORT_PRIORITY_MASK
 #define DDRC_PCFGR_3_RD_PORT_PRIORITY_DEFVAL                   0x00000000
 #define DDRC_PCFGR_3_RD_PORT_PRIORITY_SHIFT                    0
 #define DDRC_PCFGR_3_RD_PORT_PRIORITY_MASK                     0x000003FFU
@@ -7458,9 +7458,9 @@
     *  immediate commands are to the same memory page (same bank and same row)
     * . See also related PCCFG.pagematch_limit register.
 */
-#undef DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_DEFVAL 
-#undef DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_SHIFT 
-#undef DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_MASK 
+#undef DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_DEFVAL
+#undef DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_SHIFT
+#undef DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_MASK
 #define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_DEFVAL               0x00004000
 #define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_SHIFT                14
 #define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_MASK                 0x00004000U
@@ -7473,9 +7473,9 @@
     * serted anytime and as long as required which is independent of address h
     * andshaking (it is not associated with any particular command).
 */
-#undef DDRC_PCFGW_3_WR_PORT_URGENT_EN_DEFVAL 
-#undef DDRC_PCFGW_3_WR_PORT_URGENT_EN_SHIFT 
-#undef DDRC_PCFGW_3_WR_PORT_URGENT_EN_MASK 
+#undef DDRC_PCFGW_3_WR_PORT_URGENT_EN_DEFVAL
+#undef DDRC_PCFGW_3_WR_PORT_URGENT_EN_SHIFT
+#undef DDRC_PCFGW_3_WR_PORT_URGENT_EN_MASK
 #define DDRC_PCFGW_3_WR_PORT_URGENT_EN_DEFVAL                  0x00004000
 #define DDRC_PCFGW_3_WR_PORT_URGENT_EN_SHIFT                   13
 #define DDRC_PCFGW_3_WR_PORT_URGENT_EN_MASK                    0x00002000U
@@ -7483,9 +7483,9 @@
 /*
 * If set to 1, enables aging function for the write channel of the port.
 */
-#undef DDRC_PCFGW_3_WR_PORT_AGING_EN_DEFVAL 
-#undef DDRC_PCFGW_3_WR_PORT_AGING_EN_SHIFT 
-#undef DDRC_PCFGW_3_WR_PORT_AGING_EN_MASK 
+#undef DDRC_PCFGW_3_WR_PORT_AGING_EN_DEFVAL
+#undef DDRC_PCFGW_3_WR_PORT_AGING_EN_SHIFT
+#undef DDRC_PCFGW_3_WR_PORT_AGING_EN_MASK
 #define DDRC_PCFGW_3_WR_PORT_AGING_EN_DEFVAL                   0x00004000
 #define DDRC_PCFGW_3_WR_PORT_AGING_EN_SHIFT                    12
 #define DDRC_PCFGW_3_WR_PORT_AGING_EN_MASK                     0x00001000U
@@ -7506,9 +7506,9 @@
     *  direction switching. Note: The two LSBs of this register field are tied
     *  internally to 2'b00.
 */
-#undef DDRC_PCFGW_3_WR_PORT_PRIORITY_DEFVAL 
-#undef DDRC_PCFGW_3_WR_PORT_PRIORITY_SHIFT 
-#undef DDRC_PCFGW_3_WR_PORT_PRIORITY_MASK 
+#undef DDRC_PCFGW_3_WR_PORT_PRIORITY_DEFVAL
+#undef DDRC_PCFGW_3_WR_PORT_PRIORITY_SHIFT
+#undef DDRC_PCFGW_3_WR_PORT_PRIORITY_MASK
 #define DDRC_PCFGW_3_WR_PORT_PRIORITY_DEFVAL                   0x00004000
 #define DDRC_PCFGW_3_WR_PORT_PRIORITY_SHIFT                    0
 #define DDRC_PCFGW_3_WR_PORT_PRIORITY_MASK                     0x000003FFU
@@ -7516,10 +7516,10 @@
 /*
 * Enables port n.
 */
-#undef DDRC_PCTRL_3_PORT_EN_DEFVAL 
-#undef DDRC_PCTRL_3_PORT_EN_SHIFT 
-#undef DDRC_PCTRL_3_PORT_EN_MASK 
-#define DDRC_PCTRL_3_PORT_EN_DEFVAL                            
+#undef DDRC_PCTRL_3_PORT_EN_DEFVAL
+#undef DDRC_PCTRL_3_PORT_EN_SHIFT
+#undef DDRC_PCTRL_3_PORT_EN_MASK
+#define DDRC_PCTRL_3_PORT_EN_DEFVAL
 #define DDRC_PCTRL_3_PORT_EN_SHIFT                             0
 #define DDRC_PCTRL_3_PORT_EN_MASK                              0x00000001U
 
@@ -7531,9 +7531,9 @@
     * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR
     * traffic.
 */
-#undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_DEFVAL 
-#undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_SHIFT 
-#undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_MASK 
+#undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_DEFVAL
+#undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_SHIFT
+#undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_MASK
 #define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_DEFVAL                0x00000000
 #define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_SHIFT                 20
 #define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_MASK                  0x00300000U
@@ -7546,9 +7546,9 @@
     * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR
     * traffic.
 */
-#undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_DEFVAL 
-#undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_SHIFT 
-#undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_MASK 
+#undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_DEFVAL
+#undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_SHIFT
+#undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_MASK
 #define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_DEFVAL                0x00000000
 #define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_SHIFT                 16
 #define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_MASK                  0x00030000U
@@ -7561,9 +7561,9 @@
     * rresponds to higher port priority. All of the map_level* registers must
     * be set to distinct values.
 */
-#undef DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_DEFVAL 
-#undef DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_SHIFT 
-#undef DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_MASK 
+#undef DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_DEFVAL
+#undef DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_SHIFT
+#undef DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_MASK
 #define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_DEFVAL                 0x00000000
 #define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_SHIFT                  0
 #define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_MASK                   0x0000000FU
@@ -7572,9 +7572,9 @@
 * Specifies the timeout value for transactions mapped to the red address q
     * ueue.
 */
-#undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_DEFVAL 
-#undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_SHIFT 
-#undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_MASK 
+#undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_DEFVAL
+#undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_SHIFT
+#undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_MASK
 #define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_DEFVAL               0x00000000
 #define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_SHIFT                16
 #define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_MASK                 0x07FF0000U
@@ -7583,9 +7583,9 @@
 * Specifies the timeout value for transactions mapped to the blue address
     * queue.
 */
-#undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_DEFVAL 
-#undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_SHIFT 
-#undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_MASK 
+#undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_DEFVAL
+#undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_SHIFT
+#undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_MASK
 #define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_DEFVAL               0x00000000
 #define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_SHIFT                0
 #define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_MASK                 0x000007FFU
@@ -7596,9 +7596,9 @@
     * affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW
     *  traffic.
 */
-#undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_DEFVAL 
-#undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_SHIFT 
-#undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_MASK 
+#undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_DEFVAL
+#undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_SHIFT
+#undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_MASK
 #define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_DEFVAL               0x00000000
 #define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_SHIFT                20
 #define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_MASK                 0x00300000U
@@ -7609,9 +7609,9 @@
     * affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW
     * traffic.
 */
-#undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_DEFVAL 
-#undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_SHIFT 
-#undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_MASK 
+#undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_DEFVAL
+#undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_SHIFT
+#undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_MASK
 #define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_DEFVAL               0x00000000
 #define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_SHIFT                16
 #define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_MASK                 0x00030000U
@@ -7622,9 +7622,9 @@
     * . Note that for PA, awqos values are used directly as port priorities, w
     * here the higher the value corresponds to higher port priority.
 */
-#undef DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_DEFVAL 
-#undef DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_SHIFT 
-#undef DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_MASK 
+#undef DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_DEFVAL
+#undef DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_SHIFT
+#undef DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_MASK
 #define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_DEFVAL                 0x00000000
 #define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_SHIFT                  0
 #define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_MASK                   0x0000000FU
@@ -7632,10 +7632,10 @@
 /*
 * Specifies the timeout value for write transactions.
 */
-#undef DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_DEFVAL 
-#undef DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_SHIFT 
-#undef DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_MASK 
-#define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_DEFVAL               
+#undef DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_DEFVAL
+#undef DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_SHIFT
+#undef DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_MASK
+#define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_DEFVAL
 #define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_SHIFT                0
 #define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_MASK                 0x000007FFU
 
@@ -7645,9 +7645,9 @@
     *  immediate commands are to the same memory page (same bank and same row)
     * . See also related PCCFG.pagematch_limit register.
 */
-#undef DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_DEFVAL 
-#undef DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_SHIFT 
-#undef DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_MASK 
+#undef DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_DEFVAL
+#undef DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_SHIFT
+#undef DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_MASK
 #define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_DEFVAL               0x00000000
 #define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_SHIFT                14
 #define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_MASK                 0x00004000U
@@ -7661,9 +7661,9 @@
     * ndependent of address handshaking (it is not associated with any particu
     * lar command).
 */
-#undef DDRC_PCFGR_4_RD_PORT_URGENT_EN_DEFVAL 
-#undef DDRC_PCFGR_4_RD_PORT_URGENT_EN_SHIFT 
-#undef DDRC_PCFGR_4_RD_PORT_URGENT_EN_MASK 
+#undef DDRC_PCFGR_4_RD_PORT_URGENT_EN_DEFVAL
+#undef DDRC_PCFGR_4_RD_PORT_URGENT_EN_SHIFT
+#undef DDRC_PCFGR_4_RD_PORT_URGENT_EN_MASK
 #define DDRC_PCFGR_4_RD_PORT_URGENT_EN_DEFVAL                  0x00000000
 #define DDRC_PCFGR_4_RD_PORT_URGENT_EN_SHIFT                   13
 #define DDRC_PCFGR_4_RD_PORT_URGENT_EN_MASK                    0x00002000U
@@ -7671,9 +7671,9 @@
 /*
 * If set to 1, enables aging function for the read channel of the port.
 */
-#undef DDRC_PCFGR_4_RD_PORT_AGING_EN_DEFVAL 
-#undef DDRC_PCFGR_4_RD_PORT_AGING_EN_SHIFT 
-#undef DDRC_PCFGR_4_RD_PORT_AGING_EN_MASK 
+#undef DDRC_PCFGR_4_RD_PORT_AGING_EN_DEFVAL
+#undef DDRC_PCFGR_4_RD_PORT_AGING_EN_SHIFT
+#undef DDRC_PCFGR_4_RD_PORT_AGING_EN_MASK
 #define DDRC_PCFGR_4_RD_PORT_AGING_EN_DEFVAL                   0x00000000
 #define DDRC_PCFGR_4_RD_PORT_AGING_EN_SHIFT                    12
 #define DDRC_PCFGR_4_RD_PORT_AGING_EN_MASK                     0x00001000U
@@ -7697,9 +7697,9 @@
     * ity read - HPR) on a command by command basis. Note: The two LSBs of thi
     * s register field are tied internally to 2'b00.
 */
-#undef DDRC_PCFGR_4_RD_PORT_PRIORITY_DEFVAL 
-#undef DDRC_PCFGR_4_RD_PORT_PRIORITY_SHIFT 
-#undef DDRC_PCFGR_4_RD_PORT_PRIORITY_MASK 
+#undef DDRC_PCFGR_4_RD_PORT_PRIORITY_DEFVAL
+#undef DDRC_PCFGR_4_RD_PORT_PRIORITY_SHIFT
+#undef DDRC_PCFGR_4_RD_PORT_PRIORITY_MASK
 #define DDRC_PCFGR_4_RD_PORT_PRIORITY_DEFVAL                   0x00000000
 #define DDRC_PCFGR_4_RD_PORT_PRIORITY_SHIFT                    0
 #define DDRC_PCFGR_4_RD_PORT_PRIORITY_MASK                     0x000003FFU
@@ -7710,9 +7710,9 @@
     *  immediate commands are to the same memory page (same bank and same row)
     * . See also related PCCFG.pagematch_limit register.
 */
-#undef DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_DEFVAL 
-#undef DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_SHIFT 
-#undef DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_MASK 
+#undef DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_DEFVAL
+#undef DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_SHIFT
+#undef DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_MASK
 #define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_DEFVAL               0x00004000
 #define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_SHIFT                14
 #define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_MASK                 0x00004000U
@@ -7725,9 +7725,9 @@
     * serted anytime and as long as required which is independent of address h
     * andshaking (it is not associated with any particular command).
 */
-#undef DDRC_PCFGW_4_WR_PORT_URGENT_EN_DEFVAL 
-#undef DDRC_PCFGW_4_WR_PORT_URGENT_EN_SHIFT 
-#undef DDRC_PCFGW_4_WR_PORT_URGENT_EN_MASK 
+#undef DDRC_PCFGW_4_WR_PORT_URGENT_EN_DEFVAL
+#undef DDRC_PCFGW_4_WR_PORT_URGENT_EN_SHIFT
+#undef DDRC_PCFGW_4_WR_PORT_URGENT_EN_MASK
 #define DDRC_PCFGW_4_WR_PORT_URGENT_EN_DEFVAL                  0x00004000
 #define DDRC_PCFGW_4_WR_PORT_URGENT_EN_SHIFT                   13
 #define DDRC_PCFGW_4_WR_PORT_URGENT_EN_MASK                    0x00002000U
@@ -7735,9 +7735,9 @@
 /*
 * If set to 1, enables aging function for the write channel of the port.
 */
-#undef DDRC_PCFGW_4_WR_PORT_AGING_EN_DEFVAL 
-#undef DDRC_PCFGW_4_WR_PORT_AGING_EN_SHIFT 
-#undef DDRC_PCFGW_4_WR_PORT_AGING_EN_MASK 
+#undef DDRC_PCFGW_4_WR_PORT_AGING_EN_DEFVAL
+#undef DDRC_PCFGW_4_WR_PORT_AGING_EN_SHIFT
+#undef DDRC_PCFGW_4_WR_PORT_AGING_EN_MASK
 #define DDRC_PCFGW_4_WR_PORT_AGING_EN_DEFVAL                   0x00004000
 #define DDRC_PCFGW_4_WR_PORT_AGING_EN_SHIFT                    12
 #define DDRC_PCFGW_4_WR_PORT_AGING_EN_MASK                     0x00001000U
@@ -7758,9 +7758,9 @@
     *  direction switching. Note: The two LSBs of this register field are tied
     *  internally to 2'b00.
 */
-#undef DDRC_PCFGW_4_WR_PORT_PRIORITY_DEFVAL 
-#undef DDRC_PCFGW_4_WR_PORT_PRIORITY_SHIFT 
-#undef DDRC_PCFGW_4_WR_PORT_PRIORITY_MASK 
+#undef DDRC_PCFGW_4_WR_PORT_PRIORITY_DEFVAL
+#undef DDRC_PCFGW_4_WR_PORT_PRIORITY_SHIFT
+#undef DDRC_PCFGW_4_WR_PORT_PRIORITY_MASK
 #define DDRC_PCFGW_4_WR_PORT_PRIORITY_DEFVAL                   0x00004000
 #define DDRC_PCFGW_4_WR_PORT_PRIORITY_SHIFT                    0
 #define DDRC_PCFGW_4_WR_PORT_PRIORITY_MASK                     0x000003FFU
@@ -7768,10 +7768,10 @@
 /*
 * Enables port n.
 */
-#undef DDRC_PCTRL_4_PORT_EN_DEFVAL 
-#undef DDRC_PCTRL_4_PORT_EN_SHIFT 
-#undef DDRC_PCTRL_4_PORT_EN_MASK 
-#define DDRC_PCTRL_4_PORT_EN_DEFVAL                            
+#undef DDRC_PCTRL_4_PORT_EN_DEFVAL
+#undef DDRC_PCTRL_4_PORT_EN_SHIFT
+#undef DDRC_PCTRL_4_PORT_EN_MASK
+#define DDRC_PCTRL_4_PORT_EN_DEFVAL
 #define DDRC_PCTRL_4_PORT_EN_SHIFT                             0
 #define DDRC_PCTRL_4_PORT_EN_MASK                              0x00000001U
 
@@ -7783,9 +7783,9 @@
     * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR
     * traffic.
 */
-#undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_DEFVAL 
-#undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_SHIFT 
-#undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_MASK 
+#undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_DEFVAL
+#undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_SHIFT
+#undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_MASK
 #define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_DEFVAL                0x00000000
 #define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_SHIFT                 20
 #define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_MASK                  0x00300000U
@@ -7798,9 +7798,9 @@
     * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR
     * traffic.
 */
-#undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_DEFVAL 
-#undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_SHIFT 
-#undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_MASK 
+#undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_DEFVAL
+#undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_SHIFT
+#undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_MASK
 #define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_DEFVAL                0x00000000
 #define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_SHIFT                 16
 #define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_MASK                  0x00030000U
@@ -7813,9 +7813,9 @@
     * rresponds to higher port priority. All of the map_level* registers must
     * be set to distinct values.
 */
-#undef DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_DEFVAL 
-#undef DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_SHIFT 
-#undef DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_MASK 
+#undef DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_DEFVAL
+#undef DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_SHIFT
+#undef DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_MASK
 #define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_DEFVAL                 0x00000000
 #define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_SHIFT                  0
 #define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_MASK                   0x0000000FU
@@ -7824,9 +7824,9 @@
 * Specifies the timeout value for transactions mapped to the red address q
     * ueue.
 */
-#undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_DEFVAL 
-#undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_SHIFT 
-#undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_MASK 
+#undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_DEFVAL
+#undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_SHIFT
+#undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_MASK
 #define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_DEFVAL               0x00000000
 #define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_SHIFT                16
 #define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_MASK                 0x07FF0000U
@@ -7835,9 +7835,9 @@
 * Specifies the timeout value for transactions mapped to the blue address
     * queue.
 */
-#undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_DEFVAL 
-#undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_SHIFT 
-#undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_MASK 
+#undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_DEFVAL
+#undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_SHIFT
+#undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_MASK
 #define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_DEFVAL               0x00000000
 #define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_SHIFT                0
 #define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_MASK                 0x000007FFU
@@ -7848,9 +7848,9 @@
     * affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW
     *  traffic.
 */
-#undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_DEFVAL 
-#undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_SHIFT 
-#undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_MASK 
+#undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_DEFVAL
+#undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_SHIFT
+#undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_MASK
 #define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_DEFVAL               0x00000000
 #define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_SHIFT                20
 #define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_MASK                 0x00300000U
@@ -7861,9 +7861,9 @@
     * affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW
     * traffic.
 */
-#undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_DEFVAL 
-#undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_SHIFT 
-#undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_MASK 
+#undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_DEFVAL
+#undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_SHIFT
+#undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_MASK
 #define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_DEFVAL               0x00000000
 #define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_SHIFT                16
 #define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_MASK                 0x00030000U
@@ -7874,9 +7874,9 @@
     * . Note that for PA, awqos values are used directly as port priorities, w
     * here the higher the value corresponds to higher port priority.
 */
-#undef DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_DEFVAL 
-#undef DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_SHIFT 
-#undef DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_MASK 
+#undef DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_DEFVAL
+#undef DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_SHIFT
+#undef DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_MASK
 #define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_DEFVAL                 0x00000000
 #define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_SHIFT                  0
 #define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_MASK                   0x0000000FU
@@ -7884,10 +7884,10 @@
 /*
 * Specifies the timeout value for write transactions.
 */
-#undef DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_DEFVAL 
-#undef DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_SHIFT 
-#undef DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_MASK 
-#define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_DEFVAL               
+#undef DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_DEFVAL
+#undef DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_SHIFT
+#undef DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_MASK
+#define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_DEFVAL
 #define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_SHIFT                0
 #define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_MASK                 0x000007FFU
 
@@ -7897,9 +7897,9 @@
     *  immediate commands are to the same memory page (same bank and same row)
     * . See also related PCCFG.pagematch_limit register.
 */
-#undef DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_DEFVAL 
-#undef DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_SHIFT 
-#undef DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_MASK 
+#undef DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_DEFVAL
+#undef DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_SHIFT
+#undef DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_MASK
 #define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_DEFVAL               0x00000000
 #define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_SHIFT                14
 #define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_MASK                 0x00004000U
@@ -7913,9 +7913,9 @@
     * ndependent of address handshaking (it is not associated with any particu
     * lar command).
 */
-#undef DDRC_PCFGR_5_RD_PORT_URGENT_EN_DEFVAL 
-#undef DDRC_PCFGR_5_RD_PORT_URGENT_EN_SHIFT 
-#undef DDRC_PCFGR_5_RD_PORT_URGENT_EN_MASK 
+#undef DDRC_PCFGR_5_RD_PORT_URGENT_EN_DEFVAL
+#undef DDRC_PCFGR_5_RD_PORT_URGENT_EN_SHIFT
+#undef DDRC_PCFGR_5_RD_PORT_URGENT_EN_MASK
 #define DDRC_PCFGR_5_RD_PORT_URGENT_EN_DEFVAL                  0x00000000
 #define DDRC_PCFGR_5_RD_PORT_URGENT_EN_SHIFT                   13
 #define DDRC_PCFGR_5_RD_PORT_URGENT_EN_MASK                    0x00002000U
@@ -7923,9 +7923,9 @@
 /*
 * If set to 1, enables aging function for the read channel of the port.
 */
-#undef DDRC_PCFGR_5_RD_PORT_AGING_EN_DEFVAL 
-#undef DDRC_PCFGR_5_RD_PORT_AGING_EN_SHIFT 
-#undef DDRC_PCFGR_5_RD_PORT_AGING_EN_MASK 
+#undef DDRC_PCFGR_5_RD_PORT_AGING_EN_DEFVAL
+#undef DDRC_PCFGR_5_RD_PORT_AGING_EN_SHIFT
+#undef DDRC_PCFGR_5_RD_PORT_AGING_EN_MASK
 #define DDRC_PCFGR_5_RD_PORT_AGING_EN_DEFVAL                   0x00000000
 #define DDRC_PCFGR_5_RD_PORT_AGING_EN_SHIFT                    12
 #define DDRC_PCFGR_5_RD_PORT_AGING_EN_MASK                     0x00001000U
@@ -7949,9 +7949,9 @@
     * ity read - HPR) on a command by command basis. Note: The two LSBs of thi
     * s register field are tied internally to 2'b00.
 */
-#undef DDRC_PCFGR_5_RD_PORT_PRIORITY_DEFVAL 
-#undef DDRC_PCFGR_5_RD_PORT_PRIORITY_SHIFT 
-#undef DDRC_PCFGR_5_RD_PORT_PRIORITY_MASK 
+#undef DDRC_PCFGR_5_RD_PORT_PRIORITY_DEFVAL
+#undef DDRC_PCFGR_5_RD_PORT_PRIORITY_SHIFT
+#undef DDRC_PCFGR_5_RD_PORT_PRIORITY_MASK
 #define DDRC_PCFGR_5_RD_PORT_PRIORITY_DEFVAL                   0x00000000
 #define DDRC_PCFGR_5_RD_PORT_PRIORITY_SHIFT                    0
 #define DDRC_PCFGR_5_RD_PORT_PRIORITY_MASK                     0x000003FFU
@@ -7962,9 +7962,9 @@
     *  immediate commands are to the same memory page (same bank and same row)
     * . See also related PCCFG.pagematch_limit register.
 */
-#undef DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_DEFVAL 
-#undef DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_SHIFT 
-#undef DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_MASK 
+#undef DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_DEFVAL
+#undef DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_SHIFT
+#undef DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_MASK
 #define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_DEFVAL               0x00004000
 #define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_SHIFT                14
 #define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_MASK                 0x00004000U
@@ -7977,9 +7977,9 @@
     * serted anytime and as long as required which is independent of address h
     * andshaking (it is not associated with any particular command).
 */
-#undef DDRC_PCFGW_5_WR_PORT_URGENT_EN_DEFVAL 
-#undef DDRC_PCFGW_5_WR_PORT_URGENT_EN_SHIFT 
-#undef DDRC_PCFGW_5_WR_PORT_URGENT_EN_MASK 
+#undef DDRC_PCFGW_5_WR_PORT_URGENT_EN_DEFVAL
+#undef DDRC_PCFGW_5_WR_PORT_URGENT_EN_SHIFT
+#undef DDRC_PCFGW_5_WR_PORT_URGENT_EN_MASK
 #define DDRC_PCFGW_5_WR_PORT_URGENT_EN_DEFVAL                  0x00004000
 #define DDRC_PCFGW_5_WR_PORT_URGENT_EN_SHIFT                   13
 #define DDRC_PCFGW_5_WR_PORT_URGENT_EN_MASK                    0x00002000U
@@ -7987,9 +7987,9 @@
 /*
 * If set to 1, enables aging function for the write channel of the port.
 */
-#undef DDRC_PCFGW_5_WR_PORT_AGING_EN_DEFVAL 
-#undef DDRC_PCFGW_5_WR_PORT_AGING_EN_SHIFT 
-#undef DDRC_PCFGW_5_WR_PORT_AGING_EN_MASK 
+#undef DDRC_PCFGW_5_WR_PORT_AGING_EN_DEFVAL
+#undef DDRC_PCFGW_5_WR_PORT_AGING_EN_SHIFT
+#undef DDRC_PCFGW_5_WR_PORT_AGING_EN_MASK
 #define DDRC_PCFGW_5_WR_PORT_AGING_EN_DEFVAL                   0x00004000
 #define DDRC_PCFGW_5_WR_PORT_AGING_EN_SHIFT                    12
 #define DDRC_PCFGW_5_WR_PORT_AGING_EN_MASK                     0x00001000U
@@ -8010,9 +8010,9 @@
     *  direction switching. Note: The two LSBs of this register field are tied
     *  internally to 2'b00.
 */
-#undef DDRC_PCFGW_5_WR_PORT_PRIORITY_DEFVAL 
-#undef DDRC_PCFGW_5_WR_PORT_PRIORITY_SHIFT 
-#undef DDRC_PCFGW_5_WR_PORT_PRIORITY_MASK 
+#undef DDRC_PCFGW_5_WR_PORT_PRIORITY_DEFVAL
+#undef DDRC_PCFGW_5_WR_PORT_PRIORITY_SHIFT
+#undef DDRC_PCFGW_5_WR_PORT_PRIORITY_MASK
 #define DDRC_PCFGW_5_WR_PORT_PRIORITY_DEFVAL                   0x00004000
 #define DDRC_PCFGW_5_WR_PORT_PRIORITY_SHIFT                    0
 #define DDRC_PCFGW_5_WR_PORT_PRIORITY_MASK                     0x000003FFU
@@ -8020,10 +8020,10 @@
 /*
 * Enables port n.
 */
-#undef DDRC_PCTRL_5_PORT_EN_DEFVAL 
-#undef DDRC_PCTRL_5_PORT_EN_SHIFT 
-#undef DDRC_PCTRL_5_PORT_EN_MASK 
-#define DDRC_PCTRL_5_PORT_EN_DEFVAL                            
+#undef DDRC_PCTRL_5_PORT_EN_DEFVAL
+#undef DDRC_PCTRL_5_PORT_EN_SHIFT
+#undef DDRC_PCTRL_5_PORT_EN_MASK
+#define DDRC_PCTRL_5_PORT_EN_DEFVAL
 #define DDRC_PCTRL_5_PORT_EN_SHIFT                             0
 #define DDRC_PCTRL_5_PORT_EN_MASK                              0x00000001U
 
@@ -8035,9 +8035,9 @@
     * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR
     * traffic.
 */
-#undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_DEFVAL 
-#undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_SHIFT 
-#undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_MASK 
+#undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_DEFVAL
+#undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_SHIFT
+#undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_MASK
 #define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_DEFVAL                0x00000000
 #define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_SHIFT                 20
 #define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_MASK                  0x00300000U
@@ -8050,9 +8050,9 @@
     * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR
     * traffic.
 */
-#undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_DEFVAL 
-#undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_SHIFT 
-#undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_MASK 
+#undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_DEFVAL
+#undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_SHIFT
+#undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_MASK
 #define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_DEFVAL                0x00000000
 #define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_SHIFT                 16
 #define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_MASK                  0x00030000U
@@ -8065,9 +8065,9 @@
     * rresponds to higher port priority. All of the map_level* registers must
     * be set to distinct values.
 */
-#undef DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_DEFVAL 
-#undef DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_SHIFT 
-#undef DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_MASK 
+#undef DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_DEFVAL
+#undef DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_SHIFT
+#undef DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_MASK
 #define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_DEFVAL                 0x00000000
 #define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_SHIFT                  0
 #define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_MASK                   0x0000000FU
@@ -8076,9 +8076,9 @@
 * Specifies the timeout value for transactions mapped to the red address q
     * ueue.
 */
-#undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_DEFVAL 
-#undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_SHIFT 
-#undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_MASK 
+#undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_DEFVAL
+#undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_SHIFT
+#undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_MASK
 #define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_DEFVAL               0x00000000
 #define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_SHIFT                16
 #define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_MASK                 0x07FF0000U
@@ -8087,9 +8087,9 @@
 * Specifies the timeout value for transactions mapped to the blue address
     * queue.
 */
-#undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_DEFVAL 
-#undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_SHIFT 
-#undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_MASK 
+#undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_DEFVAL
+#undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_SHIFT
+#undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_MASK
 #define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_DEFVAL               0x00000000
 #define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_SHIFT                0
 #define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_MASK                 0x000007FFU
@@ -8100,9 +8100,9 @@
     * affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW
     *  traffic.
 */
-#undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_DEFVAL 
-#undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_SHIFT 
-#undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_MASK 
+#undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_DEFVAL
+#undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_SHIFT
+#undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_MASK
 #define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_DEFVAL               0x00000000
 #define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_SHIFT                20
 #define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_MASK                 0x00300000U
@@ -8113,9 +8113,9 @@
     * affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW
     * traffic.
 */
-#undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_DEFVAL 
-#undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_SHIFT 
-#undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_MASK 
+#undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_DEFVAL
+#undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_SHIFT
+#undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_MASK
 #define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_DEFVAL               0x00000000
 #define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_SHIFT                16
 #define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_MASK                 0x00030000U
@@ -8126,9 +8126,9 @@
     * . Note that for PA, awqos values are used directly as port priorities, w
     * here the higher the value corresponds to higher port priority.
 */
-#undef DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_DEFVAL 
-#undef DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_SHIFT 
-#undef DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_MASK 
+#undef DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_DEFVAL
+#undef DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_SHIFT
+#undef DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_MASK
 #define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_DEFVAL                 0x00000000
 #define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_SHIFT                  0
 #define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_MASK                   0x0000000FU
@@ -8136,10 +8136,10 @@
 /*
 * Specifies the timeout value for write transactions.
 */
-#undef DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_DEFVAL 
-#undef DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_SHIFT 
-#undef DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_MASK 
-#define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_DEFVAL               
+#undef DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_DEFVAL
+#undef DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_SHIFT
+#undef DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_MASK
+#define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_DEFVAL
 #define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_SHIFT                0
 #define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_MASK                 0x000007FFU
 
@@ -8148,10 +8148,10 @@
     * ] and araddr[UMCTL2_A_ADDRW-1:x] where x is determined by the minimum bl
     * ock size parameter UMCTL2_SARMINSIZE: (x=log2(block size)).
 */
-#undef DDRC_SARBASE0_BASE_ADDR_DEFVAL 
-#undef DDRC_SARBASE0_BASE_ADDR_SHIFT 
-#undef DDRC_SARBASE0_BASE_ADDR_MASK 
-#define DDRC_SARBASE0_BASE_ADDR_DEFVAL                         
+#undef DDRC_SARBASE0_BASE_ADDR_DEFVAL
+#undef DDRC_SARBASE0_BASE_ADDR_SHIFT
+#undef DDRC_SARBASE0_BASE_ADDR_MASK
+#define DDRC_SARBASE0_BASE_ADDR_DEFVAL
 #define DDRC_SARBASE0_BASE_ADDR_SHIFT                          0
 #define DDRC_SARBASE0_BASE_ADDR_MASK                           0x000001FFU
 
@@ -8162,10 +8162,10 @@
     * as number of blocks = nblocks + 1. For example, if register is programme
     * d to 0, region will have 1 block.
 */
-#undef DDRC_SARSIZE0_NBLOCKS_DEFVAL 
-#undef DDRC_SARSIZE0_NBLOCKS_SHIFT 
-#undef DDRC_SARSIZE0_NBLOCKS_MASK 
-#define DDRC_SARSIZE0_NBLOCKS_DEFVAL                           
+#undef DDRC_SARSIZE0_NBLOCKS_DEFVAL
+#undef DDRC_SARSIZE0_NBLOCKS_SHIFT
+#undef DDRC_SARSIZE0_NBLOCKS_MASK
+#define DDRC_SARSIZE0_NBLOCKS_DEFVAL
 #define DDRC_SARSIZE0_NBLOCKS_SHIFT                            0
 #define DDRC_SARSIZE0_NBLOCKS_MASK                             0x000000FFU
 
@@ -8174,10 +8174,10 @@
     * ] and araddr[UMCTL2_A_ADDRW-1:x] where x is determined by the minimum bl
     * ock size parameter UMCTL2_SARMINSIZE: (x=log2(block size)).
 */
-#undef DDRC_SARBASE1_BASE_ADDR_DEFVAL 
-#undef DDRC_SARBASE1_BASE_ADDR_SHIFT 
-#undef DDRC_SARBASE1_BASE_ADDR_MASK 
-#define DDRC_SARBASE1_BASE_ADDR_DEFVAL                         
+#undef DDRC_SARBASE1_BASE_ADDR_DEFVAL
+#undef DDRC_SARBASE1_BASE_ADDR_SHIFT
+#undef DDRC_SARBASE1_BASE_ADDR_MASK
+#define DDRC_SARBASE1_BASE_ADDR_DEFVAL
 #define DDRC_SARBASE1_BASE_ADDR_SHIFT                          0
 #define DDRC_SARBASE1_BASE_ADDR_MASK                           0x000001FFU
 
@@ -8188,10 +8188,10 @@
     * as number of blocks = nblocks + 1. For example, if register is programme
     * d to 0, region will have 1 block.
 */
-#undef DDRC_SARSIZE1_NBLOCKS_DEFVAL 
-#undef DDRC_SARSIZE1_NBLOCKS_SHIFT 
-#undef DDRC_SARSIZE1_NBLOCKS_MASK 
-#define DDRC_SARSIZE1_NBLOCKS_DEFVAL                           
+#undef DDRC_SARSIZE1_NBLOCKS_DEFVAL
+#undef DDRC_SARSIZE1_NBLOCKS_SHIFT
+#undef DDRC_SARSIZE1_NBLOCKS_MASK
+#define DDRC_SARSIZE1_NBLOCKS_DEFVAL
 #define DDRC_SARSIZE1_NBLOCKS_SHIFT                            0
 #define DDRC_SARSIZE1_NBLOCKS_MASK                             0x000000FFU
 
@@ -8204,9 +8204,9 @@
     * ssary to increment this parameter by RDIMM's extra cycle of latency in t
     * erms of DFI clock.
 */
-#undef DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_DEFVAL 
-#undef DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_SHIFT 
-#undef DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_MASK 
+#undef DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_DEFVAL
+#undef DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_SHIFT
+#undef DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_MASK
 #define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_DEFVAL            0x07020002
 #define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_SHIFT             24
 #define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_MASK              0x1F000000U
@@ -8218,9 +8218,9 @@
     *  - 1 in terms of SDR clock cycles Refer to PHY specification for correct
     *  value.
 */
-#undef DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_DEFVAL 
-#undef DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_SHIFT 
-#undef DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_MASK 
+#undef DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_DEFVAL
+#undef DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_SHIFT
+#undef DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_MASK
 #define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_DEFVAL          0x07020002
 #define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_SHIFT           23
 #define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_MASK            0x00800000U
@@ -8233,9 +8233,9 @@
     * ue (CL + 1) in the calculation of trddata_en. This is to compensate for
     * the extra cycle of latency through the RDIMM. Unit: Clocks
 */
-#undef DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_DEFVAL 
-#undef DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_SHIFT 
-#undef DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_MASK 
+#undef DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_DEFVAL
+#undef DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_SHIFT
+#undef DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_MASK
 #define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_DEFVAL             0x07020002
 #define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_SHIFT              16
 #define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_MASK               0x003F0000U
@@ -8248,9 +8248,9 @@
     *  clock cycles - 1 in terms of SDR clock cycles Refer to PHY specificatio
     * n for correct value.
 */
-#undef DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_DEFVAL 
-#undef DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_SHIFT 
-#undef DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_MASK 
+#undef DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_DEFVAL
+#undef DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_SHIFT
+#undef DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_MASK
 #define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_DEFVAL          0x07020002
 #define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_SHIFT           15
 #define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_MASK            0x00008000U
@@ -8262,9 +8262,9 @@
     *  specification for correct value. Note, max supported value is 8. Unit:
     * Clocks
 */
-#undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_DEFVAL 
-#undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_SHIFT 
-#undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_MASK 
+#undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_DEFVAL
+#undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_SHIFT
+#undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_MASK
 #define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_DEFVAL             0x07020002
 #define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_SHIFT              8
 #define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_MASK               0x00003F00U
@@ -8277,9 +8277,9 @@
     *  in the calculation of tphy_wrlat. This is to compensate for the extra c
     * ycle of latency through the RDIMM.
 */
-#undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_DEFVAL 
-#undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_SHIFT 
-#undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_MASK 
+#undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_DEFVAL
+#undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_SHIFT
+#undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_MASK
 #define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_DEFVAL              0x07020002
 #define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_SHIFT               0
 #define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_MASK                0x0000003FU
@@ -8287,9 +8287,9 @@
 /*
 * DDR block level reset inside of the DDR Sub System
 */
-#undef CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL 
-#undef CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT 
-#undef CRF_APB_RST_DDR_SS_DDR_RESET_MASK 
+#undef CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL
+#undef CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT
+#undef CRF_APB_RST_DDR_SS_DDR_RESET_MASK
 #define CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL                    0x0000000F
 #define CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT                     3
 #define CRF_APB_RST_DDR_SS_DDR_RESET_MASK                      0x00000008U
@@ -8297,9 +8297,9 @@
 /*
 * APM block level reset inside of the DDR Sub System
 */
-#undef CRF_APB_RST_DDR_SS_APM_RESET_DEFVAL 
-#undef CRF_APB_RST_DDR_SS_APM_RESET_SHIFT 
-#undef CRF_APB_RST_DDR_SS_APM_RESET_MASK 
+#undef CRF_APB_RST_DDR_SS_APM_RESET_DEFVAL
+#undef CRF_APB_RST_DDR_SS_APM_RESET_SHIFT
+#undef CRF_APB_RST_DDR_SS_APM_RESET_MASK
 #define CRF_APB_RST_DDR_SS_APM_RESET_DEFVAL                    0x0000000F
 #define CRF_APB_RST_DDR_SS_APM_RESET_SHIFT                     2
 #define CRF_APB_RST_DDR_SS_APM_RESET_MASK                      0x00000004U
@@ -8307,9 +8307,9 @@
 /*
 * Address Copy
 */
-#undef DDR_PHY_PGCR0_ADCP_DEFVAL 
-#undef DDR_PHY_PGCR0_ADCP_SHIFT 
-#undef DDR_PHY_PGCR0_ADCP_MASK 
+#undef DDR_PHY_PGCR0_ADCP_DEFVAL
+#undef DDR_PHY_PGCR0_ADCP_SHIFT
+#undef DDR_PHY_PGCR0_ADCP_MASK
 #define DDR_PHY_PGCR0_ADCP_DEFVAL                              0x07001E00
 #define DDR_PHY_PGCR0_ADCP_SHIFT                               31
 #define DDR_PHY_PGCR0_ADCP_MASK                                0x80000000U
@@ -8317,9 +8317,9 @@
 /*
 * Reserved. Returns zeroes on reads.
 */
-#undef DDR_PHY_PGCR0_RESERVED_30_27_DEFVAL 
-#undef DDR_PHY_PGCR0_RESERVED_30_27_SHIFT 
-#undef DDR_PHY_PGCR0_RESERVED_30_27_MASK 
+#undef DDR_PHY_PGCR0_RESERVED_30_27_DEFVAL
+#undef DDR_PHY_PGCR0_RESERVED_30_27_SHIFT
+#undef DDR_PHY_PGCR0_RESERVED_30_27_MASK
 #define DDR_PHY_PGCR0_RESERVED_30_27_DEFVAL                    0x07001E00
 #define DDR_PHY_PGCR0_RESERVED_30_27_SHIFT                     27
 #define DDR_PHY_PGCR0_RESERVED_30_27_MASK                      0x78000000U
@@ -8327,9 +8327,9 @@
 /*
 * PHY FIFO Reset
 */
-#undef DDR_PHY_PGCR0_PHYFRST_DEFVAL 
-#undef DDR_PHY_PGCR0_PHYFRST_SHIFT 
-#undef DDR_PHY_PGCR0_PHYFRST_MASK 
+#undef DDR_PHY_PGCR0_PHYFRST_DEFVAL
+#undef DDR_PHY_PGCR0_PHYFRST_SHIFT
+#undef DDR_PHY_PGCR0_PHYFRST_MASK
 #define DDR_PHY_PGCR0_PHYFRST_DEFVAL                           0x07001E00
 #define DDR_PHY_PGCR0_PHYFRST_SHIFT                            26
 #define DDR_PHY_PGCR0_PHYFRST_MASK                             0x04000000U
@@ -8337,9 +8337,9 @@
 /*
 * Oscillator Mode Address/Command Delay Line Select
 */
-#undef DDR_PHY_PGCR0_OSCACDL_DEFVAL 
-#undef DDR_PHY_PGCR0_OSCACDL_SHIFT 
-#undef DDR_PHY_PGCR0_OSCACDL_MASK 
+#undef DDR_PHY_PGCR0_OSCACDL_DEFVAL
+#undef DDR_PHY_PGCR0_OSCACDL_SHIFT
+#undef DDR_PHY_PGCR0_OSCACDL_MASK
 #define DDR_PHY_PGCR0_OSCACDL_DEFVAL                           0x07001E00
 #define DDR_PHY_PGCR0_OSCACDL_SHIFT                            24
 #define DDR_PHY_PGCR0_OSCACDL_MASK                             0x03000000U
@@ -8347,9 +8347,9 @@
 /*
 * Reserved. Returns zeroes on reads.
 */
-#undef DDR_PHY_PGCR0_RESERVED_23_19_DEFVAL 
-#undef DDR_PHY_PGCR0_RESERVED_23_19_SHIFT 
-#undef DDR_PHY_PGCR0_RESERVED_23_19_MASK 
+#undef DDR_PHY_PGCR0_RESERVED_23_19_DEFVAL
+#undef DDR_PHY_PGCR0_RESERVED_23_19_SHIFT
+#undef DDR_PHY_PGCR0_RESERVED_23_19_MASK
 #define DDR_PHY_PGCR0_RESERVED_23_19_DEFVAL                    0x07001E00
 #define DDR_PHY_PGCR0_RESERVED_23_19_SHIFT                     19
 #define DDR_PHY_PGCR0_RESERVED_23_19_MASK                      0x00F80000U
@@ -8357,9 +8357,9 @@
 /*
 * Digital Test Output Select
 */
-#undef DDR_PHY_PGCR0_DTOSEL_DEFVAL 
-#undef DDR_PHY_PGCR0_DTOSEL_SHIFT 
-#undef DDR_PHY_PGCR0_DTOSEL_MASK 
+#undef DDR_PHY_PGCR0_DTOSEL_DEFVAL
+#undef DDR_PHY_PGCR0_DTOSEL_SHIFT
+#undef DDR_PHY_PGCR0_DTOSEL_MASK
 #define DDR_PHY_PGCR0_DTOSEL_DEFVAL                            0x07001E00
 #define DDR_PHY_PGCR0_DTOSEL_SHIFT                             14
 #define DDR_PHY_PGCR0_DTOSEL_MASK                              0x0007C000U
@@ -8367,9 +8367,9 @@
 /*
 * Reserved. Returns zeroes on reads.
 */
-#undef DDR_PHY_PGCR0_RESERVED_13_DEFVAL 
-#undef DDR_PHY_PGCR0_RESERVED_13_SHIFT 
-#undef DDR_PHY_PGCR0_RESERVED_13_MASK 
+#undef DDR_PHY_PGCR0_RESERVED_13_DEFVAL
+#undef DDR_PHY_PGCR0_RESERVED_13_SHIFT
+#undef DDR_PHY_PGCR0_RESERVED_13_MASK
 #define DDR_PHY_PGCR0_RESERVED_13_DEFVAL                       0x07001E00
 #define DDR_PHY_PGCR0_RESERVED_13_SHIFT                        13
 #define DDR_PHY_PGCR0_RESERVED_13_MASK                         0x00002000U
@@ -8377,9 +8377,9 @@
 /*
 * Oscillator Mode Division
 */
-#undef DDR_PHY_PGCR0_OSCDIV_DEFVAL 
-#undef DDR_PHY_PGCR0_OSCDIV_SHIFT 
-#undef DDR_PHY_PGCR0_OSCDIV_MASK 
+#undef DDR_PHY_PGCR0_OSCDIV_DEFVAL
+#undef DDR_PHY_PGCR0_OSCDIV_SHIFT
+#undef DDR_PHY_PGCR0_OSCDIV_MASK
 #define DDR_PHY_PGCR0_OSCDIV_DEFVAL                            0x07001E00
 #define DDR_PHY_PGCR0_OSCDIV_SHIFT                             9
 #define DDR_PHY_PGCR0_OSCDIV_MASK                              0x00001E00U
@@ -8387,9 +8387,9 @@
 /*
 * Oscillator Enable
 */
-#undef DDR_PHY_PGCR0_OSCEN_DEFVAL 
-#undef DDR_PHY_PGCR0_OSCEN_SHIFT 
-#undef DDR_PHY_PGCR0_OSCEN_MASK 
+#undef DDR_PHY_PGCR0_OSCEN_DEFVAL
+#undef DDR_PHY_PGCR0_OSCEN_SHIFT
+#undef DDR_PHY_PGCR0_OSCEN_MASK
 #define DDR_PHY_PGCR0_OSCEN_DEFVAL                             0x07001E00
 #define DDR_PHY_PGCR0_OSCEN_SHIFT                              8
 #define DDR_PHY_PGCR0_OSCEN_MASK                               0x00000100U
@@ -8397,9 +8397,9 @@
 /*
 * Reserved. Returns zeroes on reads.
 */
-#undef DDR_PHY_PGCR0_RESERVED_7_0_DEFVAL 
-#undef DDR_PHY_PGCR0_RESERVED_7_0_SHIFT 
-#undef DDR_PHY_PGCR0_RESERVED_7_0_MASK 
+#undef DDR_PHY_PGCR0_RESERVED_7_0_DEFVAL
+#undef DDR_PHY_PGCR0_RESERVED_7_0_SHIFT
+#undef DDR_PHY_PGCR0_RESERVED_7_0_MASK
 #define DDR_PHY_PGCR0_RESERVED_7_0_DEFVAL                      0x07001E00
 #define DDR_PHY_PGCR0_RESERVED_7_0_SHIFT                       0
 #define DDR_PHY_PGCR0_RESERVED_7_0_MASK                        0x000000FFU
@@ -8407,9 +8407,9 @@
 /*
 * Clear Training Status Registers
 */
-#undef DDR_PHY_PGCR2_CLRTSTAT_DEFVAL 
-#undef DDR_PHY_PGCR2_CLRTSTAT_SHIFT 
-#undef DDR_PHY_PGCR2_CLRTSTAT_MASK 
+#undef DDR_PHY_PGCR2_CLRTSTAT_DEFVAL
+#undef DDR_PHY_PGCR2_CLRTSTAT_SHIFT
+#undef DDR_PHY_PGCR2_CLRTSTAT_MASK
 #define DDR_PHY_PGCR2_CLRTSTAT_DEFVAL                          0x00F12480
 #define DDR_PHY_PGCR2_CLRTSTAT_SHIFT                           31
 #define DDR_PHY_PGCR2_CLRTSTAT_MASK                            0x80000000U
@@ -8417,9 +8417,9 @@
 /*
 * Clear Impedance Calibration
 */
-#undef DDR_PHY_PGCR2_CLRZCAL_DEFVAL 
-#undef DDR_PHY_PGCR2_CLRZCAL_SHIFT 
-#undef DDR_PHY_PGCR2_CLRZCAL_MASK 
+#undef DDR_PHY_PGCR2_CLRZCAL_DEFVAL
+#undef DDR_PHY_PGCR2_CLRZCAL_SHIFT
+#undef DDR_PHY_PGCR2_CLRZCAL_MASK
 #define DDR_PHY_PGCR2_CLRZCAL_DEFVAL                           0x00F12480
 #define DDR_PHY_PGCR2_CLRZCAL_SHIFT                            30
 #define DDR_PHY_PGCR2_CLRZCAL_MASK                             0x40000000U
@@ -8427,9 +8427,9 @@
 /*
 * Clear Parity Error
 */
-#undef DDR_PHY_PGCR2_CLRPERR_DEFVAL 
-#undef DDR_PHY_PGCR2_CLRPERR_SHIFT 
-#undef DDR_PHY_PGCR2_CLRPERR_MASK 
+#undef DDR_PHY_PGCR2_CLRPERR_DEFVAL
+#undef DDR_PHY_PGCR2_CLRPERR_SHIFT
+#undef DDR_PHY_PGCR2_CLRPERR_MASK
 #define DDR_PHY_PGCR2_CLRPERR_DEFVAL                           0x00F12480
 #define DDR_PHY_PGCR2_CLRPERR_SHIFT                            29
 #define DDR_PHY_PGCR2_CLRPERR_MASK                             0x20000000U
@@ -8437,9 +8437,9 @@
 /*
 * Initialization Complete Pin Configuration
 */
-#undef DDR_PHY_PGCR2_ICPC_DEFVAL 
-#undef DDR_PHY_PGCR2_ICPC_SHIFT 
-#undef DDR_PHY_PGCR2_ICPC_MASK 
+#undef DDR_PHY_PGCR2_ICPC_DEFVAL
+#undef DDR_PHY_PGCR2_ICPC_SHIFT
+#undef DDR_PHY_PGCR2_ICPC_MASK
 #define DDR_PHY_PGCR2_ICPC_DEFVAL                              0x00F12480
 #define DDR_PHY_PGCR2_ICPC_SHIFT                               28
 #define DDR_PHY_PGCR2_ICPC_MASK                                0x10000000U
@@ -8447,9 +8447,9 @@
 /*
 * Data Training PUB Mode Exit Timer
 */
-#undef DDR_PHY_PGCR2_DTPMXTMR_DEFVAL 
-#undef DDR_PHY_PGCR2_DTPMXTMR_SHIFT 
-#undef DDR_PHY_PGCR2_DTPMXTMR_MASK 
+#undef DDR_PHY_PGCR2_DTPMXTMR_DEFVAL
+#undef DDR_PHY_PGCR2_DTPMXTMR_SHIFT
+#undef DDR_PHY_PGCR2_DTPMXTMR_MASK
 #define DDR_PHY_PGCR2_DTPMXTMR_DEFVAL                          0x00F12480
 #define DDR_PHY_PGCR2_DTPMXTMR_SHIFT                           20
 #define DDR_PHY_PGCR2_DTPMXTMR_MASK                            0x0FF00000U
@@ -8457,9 +8457,9 @@
 /*
 * Initialization Bypass
 */
-#undef DDR_PHY_PGCR2_INITFSMBYP_DEFVAL 
-#undef DDR_PHY_PGCR2_INITFSMBYP_SHIFT 
-#undef DDR_PHY_PGCR2_INITFSMBYP_MASK 
+#undef DDR_PHY_PGCR2_INITFSMBYP_DEFVAL
+#undef DDR_PHY_PGCR2_INITFSMBYP_SHIFT
+#undef DDR_PHY_PGCR2_INITFSMBYP_MASK
 #define DDR_PHY_PGCR2_INITFSMBYP_DEFVAL                        0x00F12480
 #define DDR_PHY_PGCR2_INITFSMBYP_SHIFT                         19
 #define DDR_PHY_PGCR2_INITFSMBYP_MASK                          0x00080000U
@@ -8467,9 +8467,9 @@
 /*
 * PLL FSM Bypass
 */
-#undef DDR_PHY_PGCR2_PLLFSMBYP_DEFVAL 
-#undef DDR_PHY_PGCR2_PLLFSMBYP_SHIFT 
-#undef DDR_PHY_PGCR2_PLLFSMBYP_MASK 
+#undef DDR_PHY_PGCR2_PLLFSMBYP_DEFVAL
+#undef DDR_PHY_PGCR2_PLLFSMBYP_SHIFT
+#undef DDR_PHY_PGCR2_PLLFSMBYP_MASK
 #define DDR_PHY_PGCR2_PLLFSMBYP_DEFVAL                         0x00F12480
 #define DDR_PHY_PGCR2_PLLFSMBYP_SHIFT                          18
 #define DDR_PHY_PGCR2_PLLFSMBYP_MASK                           0x00040000U
@@ -8477,9 +8477,9 @@
 /*
 * Refresh Period
 */
-#undef DDR_PHY_PGCR2_TREFPRD_DEFVAL 
-#undef DDR_PHY_PGCR2_TREFPRD_SHIFT 
-#undef DDR_PHY_PGCR2_TREFPRD_MASK 
+#undef DDR_PHY_PGCR2_TREFPRD_DEFVAL
+#undef DDR_PHY_PGCR2_TREFPRD_SHIFT
+#undef DDR_PHY_PGCR2_TREFPRD_MASK
 #define DDR_PHY_PGCR2_TREFPRD_DEFVAL                           0x00F12480
 #define DDR_PHY_PGCR2_TREFPRD_SHIFT                            0
 #define DDR_PHY_PGCR2_TREFPRD_MASK                             0x0003FFFFU
@@ -8487,9 +8487,9 @@
 /*
 * CKN Enable
 */
-#undef DDR_PHY_PGCR3_CKNEN_DEFVAL 
-#undef DDR_PHY_PGCR3_CKNEN_SHIFT 
-#undef DDR_PHY_PGCR3_CKNEN_MASK 
+#undef DDR_PHY_PGCR3_CKNEN_DEFVAL
+#undef DDR_PHY_PGCR3_CKNEN_SHIFT
+#undef DDR_PHY_PGCR3_CKNEN_MASK
 #define DDR_PHY_PGCR3_CKNEN_DEFVAL                             0x55AA0080
 #define DDR_PHY_PGCR3_CKNEN_SHIFT                              24
 #define DDR_PHY_PGCR3_CKNEN_MASK                               0xFF000000U
@@ -8497,9 +8497,9 @@
 /*
 * CK Enable
 */
-#undef DDR_PHY_PGCR3_CKEN_DEFVAL 
-#undef DDR_PHY_PGCR3_CKEN_SHIFT 
-#undef DDR_PHY_PGCR3_CKEN_MASK 
+#undef DDR_PHY_PGCR3_CKEN_DEFVAL
+#undef DDR_PHY_PGCR3_CKEN_SHIFT
+#undef DDR_PHY_PGCR3_CKEN_MASK
 #define DDR_PHY_PGCR3_CKEN_DEFVAL                              0x55AA0080
 #define DDR_PHY_PGCR3_CKEN_SHIFT                               16
 #define DDR_PHY_PGCR3_CKEN_MASK                                0x00FF0000U
@@ -8507,9 +8507,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_PGCR3_RESERVED_15_DEFVAL 
-#undef DDR_PHY_PGCR3_RESERVED_15_SHIFT 
-#undef DDR_PHY_PGCR3_RESERVED_15_MASK 
+#undef DDR_PHY_PGCR3_RESERVED_15_DEFVAL
+#undef DDR_PHY_PGCR3_RESERVED_15_SHIFT
+#undef DDR_PHY_PGCR3_RESERVED_15_MASK
 #define DDR_PHY_PGCR3_RESERVED_15_DEFVAL                       0x55AA0080
 #define DDR_PHY_PGCR3_RESERVED_15_SHIFT                        15
 #define DDR_PHY_PGCR3_RESERVED_15_MASK                         0x00008000U
@@ -8517,9 +8517,9 @@
 /*
 * Enable Clock Gating for AC [0] ctl_rd_clk
 */
-#undef DDR_PHY_PGCR3_GATEACRDCLK_DEFVAL 
-#undef DDR_PHY_PGCR3_GATEACRDCLK_SHIFT 
-#undef DDR_PHY_PGCR3_GATEACRDCLK_MASK 
+#undef DDR_PHY_PGCR3_GATEACRDCLK_DEFVAL
+#undef DDR_PHY_PGCR3_GATEACRDCLK_SHIFT
+#undef DDR_PHY_PGCR3_GATEACRDCLK_MASK
 #define DDR_PHY_PGCR3_GATEACRDCLK_DEFVAL                       0x55AA0080
 #define DDR_PHY_PGCR3_GATEACRDCLK_SHIFT                        13
 #define DDR_PHY_PGCR3_GATEACRDCLK_MASK                         0x00006000U
@@ -8527,9 +8527,9 @@
 /*
 * Enable Clock Gating for AC [0] ddr_clk
 */
-#undef DDR_PHY_PGCR3_GATEACDDRCLK_DEFVAL 
-#undef DDR_PHY_PGCR3_GATEACDDRCLK_SHIFT 
-#undef DDR_PHY_PGCR3_GATEACDDRCLK_MASK 
+#undef DDR_PHY_PGCR3_GATEACDDRCLK_DEFVAL
+#undef DDR_PHY_PGCR3_GATEACDDRCLK_SHIFT
+#undef DDR_PHY_PGCR3_GATEACDDRCLK_MASK
 #define DDR_PHY_PGCR3_GATEACDDRCLK_DEFVAL                      0x55AA0080
 #define DDR_PHY_PGCR3_GATEACDDRCLK_SHIFT                       11
 #define DDR_PHY_PGCR3_GATEACDDRCLK_MASK                        0x00001800U
@@ -8537,9 +8537,9 @@
 /*
 * Enable Clock Gating for AC [0] ctl_clk
 */
-#undef DDR_PHY_PGCR3_GATEACCTLCLK_DEFVAL 
-#undef DDR_PHY_PGCR3_GATEACCTLCLK_SHIFT 
-#undef DDR_PHY_PGCR3_GATEACCTLCLK_MASK 
+#undef DDR_PHY_PGCR3_GATEACCTLCLK_DEFVAL
+#undef DDR_PHY_PGCR3_GATEACCTLCLK_SHIFT
+#undef DDR_PHY_PGCR3_GATEACCTLCLK_MASK
 #define DDR_PHY_PGCR3_GATEACCTLCLK_DEFVAL                      0x55AA0080
 #define DDR_PHY_PGCR3_GATEACCTLCLK_SHIFT                       9
 #define DDR_PHY_PGCR3_GATEACCTLCLK_MASK                        0x00000600U
@@ -8547,9 +8547,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_PGCR3_RESERVED_8_DEFVAL 
-#undef DDR_PHY_PGCR3_RESERVED_8_SHIFT 
-#undef DDR_PHY_PGCR3_RESERVED_8_MASK 
+#undef DDR_PHY_PGCR3_RESERVED_8_DEFVAL
+#undef DDR_PHY_PGCR3_RESERVED_8_SHIFT
+#undef DDR_PHY_PGCR3_RESERVED_8_MASK
 #define DDR_PHY_PGCR3_RESERVED_8_DEFVAL                        0x55AA0080
 #define DDR_PHY_PGCR3_RESERVED_8_SHIFT                         8
 #define DDR_PHY_PGCR3_RESERVED_8_MASK                          0x00000100U
@@ -8557,9 +8557,9 @@
 /*
 * Controls DDL Bypass Modes
 */
-#undef DDR_PHY_PGCR3_DDLBYPMODE_DEFVAL 
-#undef DDR_PHY_PGCR3_DDLBYPMODE_SHIFT 
-#undef DDR_PHY_PGCR3_DDLBYPMODE_MASK 
+#undef DDR_PHY_PGCR3_DDLBYPMODE_DEFVAL
+#undef DDR_PHY_PGCR3_DDLBYPMODE_SHIFT
+#undef DDR_PHY_PGCR3_DDLBYPMODE_MASK
 #define DDR_PHY_PGCR3_DDLBYPMODE_DEFVAL                        0x55AA0080
 #define DDR_PHY_PGCR3_DDLBYPMODE_SHIFT                         6
 #define DDR_PHY_PGCR3_DDLBYPMODE_MASK                          0x000000C0U
@@ -8567,9 +8567,9 @@
 /*
 * IO Loop-Back Select
 */
-#undef DDR_PHY_PGCR3_IOLB_DEFVAL 
-#undef DDR_PHY_PGCR3_IOLB_SHIFT 
-#undef DDR_PHY_PGCR3_IOLB_MASK 
+#undef DDR_PHY_PGCR3_IOLB_DEFVAL
+#undef DDR_PHY_PGCR3_IOLB_SHIFT
+#undef DDR_PHY_PGCR3_IOLB_MASK
 #define DDR_PHY_PGCR3_IOLB_DEFVAL                              0x55AA0080
 #define DDR_PHY_PGCR3_IOLB_SHIFT                               5
 #define DDR_PHY_PGCR3_IOLB_MASK                                0x00000020U
@@ -8577,9 +8577,9 @@
 /*
 * AC Receive FIFO Read Mode
 */
-#undef DDR_PHY_PGCR3_RDMODE_DEFVAL 
-#undef DDR_PHY_PGCR3_RDMODE_SHIFT 
-#undef DDR_PHY_PGCR3_RDMODE_MASK 
+#undef DDR_PHY_PGCR3_RDMODE_DEFVAL
+#undef DDR_PHY_PGCR3_RDMODE_SHIFT
+#undef DDR_PHY_PGCR3_RDMODE_MASK
 #define DDR_PHY_PGCR3_RDMODE_DEFVAL                            0x55AA0080
 #define DDR_PHY_PGCR3_RDMODE_SHIFT                             3
 #define DDR_PHY_PGCR3_RDMODE_MASK                              0x00000018U
@@ -8587,9 +8587,9 @@
 /*
 * Read FIFO Reset Disable
 */
-#undef DDR_PHY_PGCR3_DISRST_DEFVAL 
-#undef DDR_PHY_PGCR3_DISRST_SHIFT 
-#undef DDR_PHY_PGCR3_DISRST_MASK 
+#undef DDR_PHY_PGCR3_DISRST_DEFVAL
+#undef DDR_PHY_PGCR3_DISRST_SHIFT
+#undef DDR_PHY_PGCR3_DISRST_MASK
 #define DDR_PHY_PGCR3_DISRST_DEFVAL                            0x55AA0080
 #define DDR_PHY_PGCR3_DISRST_SHIFT                             2
 #define DDR_PHY_PGCR3_DISRST_MASK                              0x00000004U
@@ -8597,9 +8597,9 @@
 /*
 * Clock Level when Clock Gating
 */
-#undef DDR_PHY_PGCR3_CLKLEVEL_DEFVAL 
-#undef DDR_PHY_PGCR3_CLKLEVEL_SHIFT 
-#undef DDR_PHY_PGCR3_CLKLEVEL_MASK 
+#undef DDR_PHY_PGCR3_CLKLEVEL_DEFVAL
+#undef DDR_PHY_PGCR3_CLKLEVEL_SHIFT
+#undef DDR_PHY_PGCR3_CLKLEVEL_MASK
 #define DDR_PHY_PGCR3_CLKLEVEL_DEFVAL                          0x55AA0080
 #define DDR_PHY_PGCR3_CLKLEVEL_SHIFT                           0
 #define DDR_PHY_PGCR3_CLKLEVEL_MASK                            0x00000003U
@@ -8607,9 +8607,9 @@
 /*
 * Frequency B Ratio Term
 */
-#undef DDR_PHY_PGCR5_FRQBT_DEFVAL 
-#undef DDR_PHY_PGCR5_FRQBT_SHIFT 
-#undef DDR_PHY_PGCR5_FRQBT_MASK 
+#undef DDR_PHY_PGCR5_FRQBT_DEFVAL
+#undef DDR_PHY_PGCR5_FRQBT_SHIFT
+#undef DDR_PHY_PGCR5_FRQBT_MASK
 #define DDR_PHY_PGCR5_FRQBT_DEFVAL                             0x01010000
 #define DDR_PHY_PGCR5_FRQBT_SHIFT                              24
 #define DDR_PHY_PGCR5_FRQBT_MASK                               0xFF000000U
@@ -8617,9 +8617,9 @@
 /*
 * Frequency A Ratio Term
 */
-#undef DDR_PHY_PGCR5_FRQAT_DEFVAL 
-#undef DDR_PHY_PGCR5_FRQAT_SHIFT 
-#undef DDR_PHY_PGCR5_FRQAT_MASK 
+#undef DDR_PHY_PGCR5_FRQAT_DEFVAL
+#undef DDR_PHY_PGCR5_FRQAT_SHIFT
+#undef DDR_PHY_PGCR5_FRQAT_MASK
 #define DDR_PHY_PGCR5_FRQAT_DEFVAL                             0x01010000
 #define DDR_PHY_PGCR5_FRQAT_SHIFT                              16
 #define DDR_PHY_PGCR5_FRQAT_MASK                               0x00FF0000U
@@ -8627,9 +8627,9 @@
 /*
 * DFI Disconnect Time Period
 */
-#undef DDR_PHY_PGCR5_DISCNPERIOD_DEFVAL 
-#undef DDR_PHY_PGCR5_DISCNPERIOD_SHIFT 
-#undef DDR_PHY_PGCR5_DISCNPERIOD_MASK 
+#undef DDR_PHY_PGCR5_DISCNPERIOD_DEFVAL
+#undef DDR_PHY_PGCR5_DISCNPERIOD_SHIFT
+#undef DDR_PHY_PGCR5_DISCNPERIOD_MASK
 #define DDR_PHY_PGCR5_DISCNPERIOD_DEFVAL                       0x01010000
 #define DDR_PHY_PGCR5_DISCNPERIOD_SHIFT                        8
 #define DDR_PHY_PGCR5_DISCNPERIOD_MASK                         0x0000FF00U
@@ -8637,9 +8637,9 @@
 /*
 * Receiver bias core side control
 */
-#undef DDR_PHY_PGCR5_VREF_RBCTRL_DEFVAL 
-#undef DDR_PHY_PGCR5_VREF_RBCTRL_SHIFT 
-#undef DDR_PHY_PGCR5_VREF_RBCTRL_MASK 
+#undef DDR_PHY_PGCR5_VREF_RBCTRL_DEFVAL
+#undef DDR_PHY_PGCR5_VREF_RBCTRL_SHIFT
+#undef DDR_PHY_PGCR5_VREF_RBCTRL_MASK
 #define DDR_PHY_PGCR5_VREF_RBCTRL_DEFVAL                       0x01010000
 #define DDR_PHY_PGCR5_VREF_RBCTRL_SHIFT                        4
 #define DDR_PHY_PGCR5_VREF_RBCTRL_MASK                         0x000000F0U
@@ -8647,9 +8647,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_PGCR5_RESERVED_3_DEFVAL 
-#undef DDR_PHY_PGCR5_RESERVED_3_SHIFT 
-#undef DDR_PHY_PGCR5_RESERVED_3_MASK 
+#undef DDR_PHY_PGCR5_RESERVED_3_DEFVAL
+#undef DDR_PHY_PGCR5_RESERVED_3_SHIFT
+#undef DDR_PHY_PGCR5_RESERVED_3_MASK
 #define DDR_PHY_PGCR5_RESERVED_3_DEFVAL                        0x01010000
 #define DDR_PHY_PGCR5_RESERVED_3_SHIFT                         3
 #define DDR_PHY_PGCR5_RESERVED_3_MASK                          0x00000008U
@@ -8657,9 +8657,9 @@
 /*
 * Internal VREF generator REFSEL ragne select
 */
-#undef DDR_PHY_PGCR5_DXREFISELRANGE_DEFVAL 
-#undef DDR_PHY_PGCR5_DXREFISELRANGE_SHIFT 
-#undef DDR_PHY_PGCR5_DXREFISELRANGE_MASK 
+#undef DDR_PHY_PGCR5_DXREFISELRANGE_DEFVAL
+#undef DDR_PHY_PGCR5_DXREFISELRANGE_SHIFT
+#undef DDR_PHY_PGCR5_DXREFISELRANGE_MASK
 #define DDR_PHY_PGCR5_DXREFISELRANGE_DEFVAL                    0x01010000
 #define DDR_PHY_PGCR5_DXREFISELRANGE_SHIFT                     2
 #define DDR_PHY_PGCR5_DXREFISELRANGE_MASK                      0x00000004U
@@ -8667,9 +8667,9 @@
 /*
 * DDL Page Read Write select
 */
-#undef DDR_PHY_PGCR5_DDLPGACT_DEFVAL 
-#undef DDR_PHY_PGCR5_DDLPGACT_SHIFT 
-#undef DDR_PHY_PGCR5_DDLPGACT_MASK 
+#undef DDR_PHY_PGCR5_DDLPGACT_DEFVAL
+#undef DDR_PHY_PGCR5_DDLPGACT_SHIFT
+#undef DDR_PHY_PGCR5_DDLPGACT_MASK
 #define DDR_PHY_PGCR5_DDLPGACT_DEFVAL                          0x01010000
 #define DDR_PHY_PGCR5_DDLPGACT_SHIFT                           1
 #define DDR_PHY_PGCR5_DDLPGACT_MASK                            0x00000002U
@@ -8677,9 +8677,9 @@
 /*
 * DDL Page Read Write select
 */
-#undef DDR_PHY_PGCR5_DDLPGRW_DEFVAL 
-#undef DDR_PHY_PGCR5_DDLPGRW_SHIFT 
-#undef DDR_PHY_PGCR5_DDLPGRW_MASK 
+#undef DDR_PHY_PGCR5_DDLPGRW_DEFVAL
+#undef DDR_PHY_PGCR5_DDLPGRW_SHIFT
+#undef DDR_PHY_PGCR5_DDLPGRW_MASK
 #define DDR_PHY_PGCR5_DDLPGRW_DEFVAL                           0x01010000
 #define DDR_PHY_PGCR5_DDLPGRW_SHIFT                            0
 #define DDR_PHY_PGCR5_DDLPGRW_MASK                             0x00000001U
@@ -8687,9 +8687,9 @@
 /*
 * PLL Power-Down Time
 */
-#undef DDR_PHY_PTR0_TPLLPD_DEFVAL 
-#undef DDR_PHY_PTR0_TPLLPD_SHIFT 
-#undef DDR_PHY_PTR0_TPLLPD_MASK 
+#undef DDR_PHY_PTR0_TPLLPD_DEFVAL
+#undef DDR_PHY_PTR0_TPLLPD_SHIFT
+#undef DDR_PHY_PTR0_TPLLPD_MASK
 #define DDR_PHY_PTR0_TPLLPD_DEFVAL                             0x42C21590
 #define DDR_PHY_PTR0_TPLLPD_SHIFT                              21
 #define DDR_PHY_PTR0_TPLLPD_MASK                               0xFFE00000U
@@ -8697,9 +8697,9 @@
 /*
 * PLL Gear Shift Time
 */
-#undef DDR_PHY_PTR0_TPLLGS_DEFVAL 
-#undef DDR_PHY_PTR0_TPLLGS_SHIFT 
-#undef DDR_PHY_PTR0_TPLLGS_MASK 
+#undef DDR_PHY_PTR0_TPLLGS_DEFVAL
+#undef DDR_PHY_PTR0_TPLLGS_SHIFT
+#undef DDR_PHY_PTR0_TPLLGS_MASK
 #define DDR_PHY_PTR0_TPLLGS_DEFVAL                             0x42C21590
 #define DDR_PHY_PTR0_TPLLGS_SHIFT                              6
 #define DDR_PHY_PTR0_TPLLGS_MASK                               0x001FFFC0U
@@ -8707,9 +8707,9 @@
 /*
 * PHY Reset Time
 */
-#undef DDR_PHY_PTR0_TPHYRST_DEFVAL 
-#undef DDR_PHY_PTR0_TPHYRST_SHIFT 
-#undef DDR_PHY_PTR0_TPHYRST_MASK 
+#undef DDR_PHY_PTR0_TPHYRST_DEFVAL
+#undef DDR_PHY_PTR0_TPHYRST_SHIFT
+#undef DDR_PHY_PTR0_TPHYRST_MASK
 #define DDR_PHY_PTR0_TPHYRST_DEFVAL                            0x42C21590
 #define DDR_PHY_PTR0_TPHYRST_SHIFT                             0
 #define DDR_PHY_PTR0_TPHYRST_MASK                              0x0000003FU
@@ -8717,9 +8717,9 @@
 /*
 * PLL Lock Time
 */
-#undef DDR_PHY_PTR1_TPLLLOCK_DEFVAL 
-#undef DDR_PHY_PTR1_TPLLLOCK_SHIFT 
-#undef DDR_PHY_PTR1_TPLLLOCK_MASK 
+#undef DDR_PHY_PTR1_TPLLLOCK_DEFVAL
+#undef DDR_PHY_PTR1_TPLLLOCK_SHIFT
+#undef DDR_PHY_PTR1_TPLLLOCK_MASK
 #define DDR_PHY_PTR1_TPLLLOCK_DEFVAL                           0xD05612C0
 #define DDR_PHY_PTR1_TPLLLOCK_SHIFT                            16
 #define DDR_PHY_PTR1_TPLLLOCK_MASK                             0xFFFF0000U
@@ -8727,9 +8727,9 @@
 /*
 * Reserved. Returns zeroes on reads.
 */
-#undef DDR_PHY_PTR1_RESERVED_15_13_DEFVAL 
-#undef DDR_PHY_PTR1_RESERVED_15_13_SHIFT 
-#undef DDR_PHY_PTR1_RESERVED_15_13_MASK 
+#undef DDR_PHY_PTR1_RESERVED_15_13_DEFVAL
+#undef DDR_PHY_PTR1_RESERVED_15_13_SHIFT
+#undef DDR_PHY_PTR1_RESERVED_15_13_MASK
 #define DDR_PHY_PTR1_RESERVED_15_13_DEFVAL                     0xD05612C0
 #define DDR_PHY_PTR1_RESERVED_15_13_SHIFT                      13
 #define DDR_PHY_PTR1_RESERVED_15_13_MASK                       0x0000E000U
@@ -8737,9 +8737,9 @@
 /*
 * PLL Reset Time
 */
-#undef DDR_PHY_PTR1_TPLLRST_DEFVAL 
-#undef DDR_PHY_PTR1_TPLLRST_SHIFT 
-#undef DDR_PHY_PTR1_TPLLRST_MASK 
+#undef DDR_PHY_PTR1_TPLLRST_DEFVAL
+#undef DDR_PHY_PTR1_TPLLRST_SHIFT
+#undef DDR_PHY_PTR1_TPLLRST_MASK
 #define DDR_PHY_PTR1_TPLLRST_DEFVAL                            0xD05612C0
 #define DDR_PHY_PTR1_TPLLRST_SHIFT                             0
 #define DDR_PHY_PTR1_TPLLRST_MASK                              0x00001FFFU
@@ -8747,9 +8747,9 @@
 /*
 * PLL Bypass
 */
-#undef DDR_PHY_PLLCR0_PLLBYP_DEFVAL 
-#undef DDR_PHY_PLLCR0_PLLBYP_SHIFT 
-#undef DDR_PHY_PLLCR0_PLLBYP_MASK 
+#undef DDR_PHY_PLLCR0_PLLBYP_DEFVAL
+#undef DDR_PHY_PLLCR0_PLLBYP_SHIFT
+#undef DDR_PHY_PLLCR0_PLLBYP_MASK
 #define DDR_PHY_PLLCR0_PLLBYP_DEFVAL                           0x001C0000
 #define DDR_PHY_PLLCR0_PLLBYP_SHIFT                            31
 #define DDR_PHY_PLLCR0_PLLBYP_MASK                             0x80000000U
@@ -8757,9 +8757,9 @@
 /*
 * PLL Reset
 */
-#undef DDR_PHY_PLLCR0_PLLRST_DEFVAL 
-#undef DDR_PHY_PLLCR0_PLLRST_SHIFT 
-#undef DDR_PHY_PLLCR0_PLLRST_MASK 
+#undef DDR_PHY_PLLCR0_PLLRST_DEFVAL
+#undef DDR_PHY_PLLCR0_PLLRST_SHIFT
+#undef DDR_PHY_PLLCR0_PLLRST_MASK
 #define DDR_PHY_PLLCR0_PLLRST_DEFVAL                           0x001C0000
 #define DDR_PHY_PLLCR0_PLLRST_SHIFT                            30
 #define DDR_PHY_PLLCR0_PLLRST_MASK                             0x40000000U
@@ -8767,9 +8767,9 @@
 /*
 * PLL Power Down
 */
-#undef DDR_PHY_PLLCR0_PLLPD_DEFVAL 
-#undef DDR_PHY_PLLCR0_PLLPD_SHIFT 
-#undef DDR_PHY_PLLCR0_PLLPD_MASK 
+#undef DDR_PHY_PLLCR0_PLLPD_DEFVAL
+#undef DDR_PHY_PLLCR0_PLLPD_SHIFT
+#undef DDR_PHY_PLLCR0_PLLPD_MASK
 #define DDR_PHY_PLLCR0_PLLPD_DEFVAL                            0x001C0000
 #define DDR_PHY_PLLCR0_PLLPD_SHIFT                             29
 #define DDR_PHY_PLLCR0_PLLPD_MASK                              0x20000000U
@@ -8777,9 +8777,9 @@
 /*
 * Reference Stop Mode
 */
-#undef DDR_PHY_PLLCR0_RSTOPM_DEFVAL 
-#undef DDR_PHY_PLLCR0_RSTOPM_SHIFT 
-#undef DDR_PHY_PLLCR0_RSTOPM_MASK 
+#undef DDR_PHY_PLLCR0_RSTOPM_DEFVAL
+#undef DDR_PHY_PLLCR0_RSTOPM_SHIFT
+#undef DDR_PHY_PLLCR0_RSTOPM_MASK
 #define DDR_PHY_PLLCR0_RSTOPM_DEFVAL                           0x001C0000
 #define DDR_PHY_PLLCR0_RSTOPM_SHIFT                            28
 #define DDR_PHY_PLLCR0_RSTOPM_MASK                             0x10000000U
@@ -8787,9 +8787,9 @@
 /*
 * PLL Frequency Select
 */
-#undef DDR_PHY_PLLCR0_FRQSEL_DEFVAL 
-#undef DDR_PHY_PLLCR0_FRQSEL_SHIFT 
-#undef DDR_PHY_PLLCR0_FRQSEL_MASK 
+#undef DDR_PHY_PLLCR0_FRQSEL_DEFVAL
+#undef DDR_PHY_PLLCR0_FRQSEL_SHIFT
+#undef DDR_PHY_PLLCR0_FRQSEL_MASK
 #define DDR_PHY_PLLCR0_FRQSEL_DEFVAL                           0x001C0000
 #define DDR_PHY_PLLCR0_FRQSEL_SHIFT                            24
 #define DDR_PHY_PLLCR0_FRQSEL_MASK                             0x0F000000U
@@ -8797,9 +8797,9 @@
 /*
 * Relock Mode
 */
-#undef DDR_PHY_PLLCR0_RLOCKM_DEFVAL 
-#undef DDR_PHY_PLLCR0_RLOCKM_SHIFT 
-#undef DDR_PHY_PLLCR0_RLOCKM_MASK 
+#undef DDR_PHY_PLLCR0_RLOCKM_DEFVAL
+#undef DDR_PHY_PLLCR0_RLOCKM_SHIFT
+#undef DDR_PHY_PLLCR0_RLOCKM_MASK
 #define DDR_PHY_PLLCR0_RLOCKM_DEFVAL                           0x001C0000
 #define DDR_PHY_PLLCR0_RLOCKM_SHIFT                            23
 #define DDR_PHY_PLLCR0_RLOCKM_MASK                             0x00800000U
@@ -8807,9 +8807,9 @@
 /*
 * Charge Pump Proportional Current Control
 */
-#undef DDR_PHY_PLLCR0_CPPC_DEFVAL 
-#undef DDR_PHY_PLLCR0_CPPC_SHIFT 
-#undef DDR_PHY_PLLCR0_CPPC_MASK 
+#undef DDR_PHY_PLLCR0_CPPC_DEFVAL
+#undef DDR_PHY_PLLCR0_CPPC_SHIFT
+#undef DDR_PHY_PLLCR0_CPPC_MASK
 #define DDR_PHY_PLLCR0_CPPC_DEFVAL                             0x001C0000
 #define DDR_PHY_PLLCR0_CPPC_SHIFT                              17
 #define DDR_PHY_PLLCR0_CPPC_MASK                               0x007E0000U
@@ -8817,9 +8817,9 @@
 /*
 * Charge Pump Integrating Current Control
 */
-#undef DDR_PHY_PLLCR0_CPIC_DEFVAL 
-#undef DDR_PHY_PLLCR0_CPIC_SHIFT 
-#undef DDR_PHY_PLLCR0_CPIC_MASK 
+#undef DDR_PHY_PLLCR0_CPIC_DEFVAL
+#undef DDR_PHY_PLLCR0_CPIC_SHIFT
+#undef DDR_PHY_PLLCR0_CPIC_MASK
 #define DDR_PHY_PLLCR0_CPIC_DEFVAL                             0x001C0000
 #define DDR_PHY_PLLCR0_CPIC_SHIFT                              13
 #define DDR_PHY_PLLCR0_CPIC_MASK                               0x0001E000U
@@ -8827,9 +8827,9 @@
 /*
 * Gear Shift
 */
-#undef DDR_PHY_PLLCR0_GSHIFT_DEFVAL 
-#undef DDR_PHY_PLLCR0_GSHIFT_SHIFT 
-#undef DDR_PHY_PLLCR0_GSHIFT_MASK 
+#undef DDR_PHY_PLLCR0_GSHIFT_DEFVAL
+#undef DDR_PHY_PLLCR0_GSHIFT_SHIFT
+#undef DDR_PHY_PLLCR0_GSHIFT_MASK
 #define DDR_PHY_PLLCR0_GSHIFT_DEFVAL                           0x001C0000
 #define DDR_PHY_PLLCR0_GSHIFT_SHIFT                            12
 #define DDR_PHY_PLLCR0_GSHIFT_MASK                             0x00001000U
@@ -8837,9 +8837,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_PLLCR0_RESERVED_11_9_DEFVAL 
-#undef DDR_PHY_PLLCR0_RESERVED_11_9_SHIFT 
-#undef DDR_PHY_PLLCR0_RESERVED_11_9_MASK 
+#undef DDR_PHY_PLLCR0_RESERVED_11_9_DEFVAL
+#undef DDR_PHY_PLLCR0_RESERVED_11_9_SHIFT
+#undef DDR_PHY_PLLCR0_RESERVED_11_9_MASK
 #define DDR_PHY_PLLCR0_RESERVED_11_9_DEFVAL                    0x001C0000
 #define DDR_PHY_PLLCR0_RESERVED_11_9_SHIFT                     9
 #define DDR_PHY_PLLCR0_RESERVED_11_9_MASK                      0x00000E00U
@@ -8847,9 +8847,9 @@
 /*
 * Analog Test Enable
 */
-#undef DDR_PHY_PLLCR0_ATOEN_DEFVAL 
-#undef DDR_PHY_PLLCR0_ATOEN_SHIFT 
-#undef DDR_PHY_PLLCR0_ATOEN_MASK 
+#undef DDR_PHY_PLLCR0_ATOEN_DEFVAL
+#undef DDR_PHY_PLLCR0_ATOEN_SHIFT
+#undef DDR_PHY_PLLCR0_ATOEN_MASK
 #define DDR_PHY_PLLCR0_ATOEN_DEFVAL                            0x001C0000
 #define DDR_PHY_PLLCR0_ATOEN_SHIFT                             8
 #define DDR_PHY_PLLCR0_ATOEN_MASK                              0x00000100U
@@ -8857,9 +8857,9 @@
 /*
 * Analog Test Control
 */
-#undef DDR_PHY_PLLCR0_ATC_DEFVAL 
-#undef DDR_PHY_PLLCR0_ATC_SHIFT 
-#undef DDR_PHY_PLLCR0_ATC_MASK 
+#undef DDR_PHY_PLLCR0_ATC_DEFVAL
+#undef DDR_PHY_PLLCR0_ATC_SHIFT
+#undef DDR_PHY_PLLCR0_ATC_MASK
 #define DDR_PHY_PLLCR0_ATC_DEFVAL                              0x001C0000
 #define DDR_PHY_PLLCR0_ATC_SHIFT                               4
 #define DDR_PHY_PLLCR0_ATC_MASK                                0x000000F0U
@@ -8867,9 +8867,9 @@
 /*
 * Digital Test Control
 */
-#undef DDR_PHY_PLLCR0_DTC_DEFVAL 
-#undef DDR_PHY_PLLCR0_DTC_SHIFT 
-#undef DDR_PHY_PLLCR0_DTC_MASK 
+#undef DDR_PHY_PLLCR0_DTC_DEFVAL
+#undef DDR_PHY_PLLCR0_DTC_SHIFT
+#undef DDR_PHY_PLLCR0_DTC_MASK
 #define DDR_PHY_PLLCR0_DTC_DEFVAL                              0x001C0000
 #define DDR_PHY_PLLCR0_DTC_SHIFT                               0
 #define DDR_PHY_PLLCR0_DTC_MASK                                0x0000000FU
@@ -8877,9 +8877,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DSGCR_RESERVED_31_28_DEFVAL 
-#undef DDR_PHY_DSGCR_RESERVED_31_28_SHIFT 
-#undef DDR_PHY_DSGCR_RESERVED_31_28_MASK 
+#undef DDR_PHY_DSGCR_RESERVED_31_28_DEFVAL
+#undef DDR_PHY_DSGCR_RESERVED_31_28_SHIFT
+#undef DDR_PHY_DSGCR_RESERVED_31_28_MASK
 #define DDR_PHY_DSGCR_RESERVED_31_28_DEFVAL                    0x02A04101
 #define DDR_PHY_DSGCR_RESERVED_31_28_SHIFT                     28
 #define DDR_PHY_DSGCR_RESERVED_31_28_MASK                      0xF0000000U
@@ -8888,9 +8888,9 @@
 * When RDBI enabled, this bit is used to select RDBI CL calculation, if it
     *  is 1b1, calculation will use RDBICL, otherwise use default calculation.
 */
-#undef DDR_PHY_DSGCR_RDBICLSEL_DEFVAL 
-#undef DDR_PHY_DSGCR_RDBICLSEL_SHIFT 
-#undef DDR_PHY_DSGCR_RDBICLSEL_MASK 
+#undef DDR_PHY_DSGCR_RDBICLSEL_DEFVAL
+#undef DDR_PHY_DSGCR_RDBICLSEL_SHIFT
+#undef DDR_PHY_DSGCR_RDBICLSEL_MASK
 #define DDR_PHY_DSGCR_RDBICLSEL_DEFVAL                         0x02A04101
 #define DDR_PHY_DSGCR_RDBICLSEL_SHIFT                          27
 #define DDR_PHY_DSGCR_RDBICLSEL_MASK                           0x08000000U
@@ -8899,9 +8899,9 @@
 * When RDBI enabled, if RDBICLSEL is asserted, RDBI CL adjust using this v
     * alue.
 */
-#undef DDR_PHY_DSGCR_RDBICL_DEFVAL 
-#undef DDR_PHY_DSGCR_RDBICL_SHIFT 
-#undef DDR_PHY_DSGCR_RDBICL_MASK 
+#undef DDR_PHY_DSGCR_RDBICL_DEFVAL
+#undef DDR_PHY_DSGCR_RDBICL_SHIFT
+#undef DDR_PHY_DSGCR_RDBICL_MASK
 #define DDR_PHY_DSGCR_RDBICL_DEFVAL                            0x02A04101
 #define DDR_PHY_DSGCR_RDBICL_SHIFT                             24
 #define DDR_PHY_DSGCR_RDBICL_MASK                              0x07000000U
@@ -8909,9 +8909,9 @@
 /*
 * PHY Impedance Update Enable
 */
-#undef DDR_PHY_DSGCR_PHYZUEN_DEFVAL 
-#undef DDR_PHY_DSGCR_PHYZUEN_SHIFT 
-#undef DDR_PHY_DSGCR_PHYZUEN_MASK 
+#undef DDR_PHY_DSGCR_PHYZUEN_DEFVAL
+#undef DDR_PHY_DSGCR_PHYZUEN_SHIFT
+#undef DDR_PHY_DSGCR_PHYZUEN_MASK
 #define DDR_PHY_DSGCR_PHYZUEN_DEFVAL                           0x02A04101
 #define DDR_PHY_DSGCR_PHYZUEN_SHIFT                            23
 #define DDR_PHY_DSGCR_PHYZUEN_MASK                             0x00800000U
@@ -8919,9 +8919,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DSGCR_RESERVED_22_DEFVAL 
-#undef DDR_PHY_DSGCR_RESERVED_22_SHIFT 
-#undef DDR_PHY_DSGCR_RESERVED_22_MASK 
+#undef DDR_PHY_DSGCR_RESERVED_22_DEFVAL
+#undef DDR_PHY_DSGCR_RESERVED_22_SHIFT
+#undef DDR_PHY_DSGCR_RESERVED_22_MASK
 #define DDR_PHY_DSGCR_RESERVED_22_DEFVAL                       0x02A04101
 #define DDR_PHY_DSGCR_RESERVED_22_SHIFT                        22
 #define DDR_PHY_DSGCR_RESERVED_22_MASK                         0x00400000U
@@ -8929,9 +8929,9 @@
 /*
 * SDRAM Reset Output Enable
 */
-#undef DDR_PHY_DSGCR_RSTOE_DEFVAL 
-#undef DDR_PHY_DSGCR_RSTOE_SHIFT 
-#undef DDR_PHY_DSGCR_RSTOE_MASK 
+#undef DDR_PHY_DSGCR_RSTOE_DEFVAL
+#undef DDR_PHY_DSGCR_RSTOE_SHIFT
+#undef DDR_PHY_DSGCR_RSTOE_MASK
 #define DDR_PHY_DSGCR_RSTOE_DEFVAL                             0x02A04101
 #define DDR_PHY_DSGCR_RSTOE_SHIFT                              21
 #define DDR_PHY_DSGCR_RSTOE_MASK                               0x00200000U
@@ -8939,9 +8939,9 @@
 /*
 * Single Data Rate Mode
 */
-#undef DDR_PHY_DSGCR_SDRMODE_DEFVAL 
-#undef DDR_PHY_DSGCR_SDRMODE_SHIFT 
-#undef DDR_PHY_DSGCR_SDRMODE_MASK 
+#undef DDR_PHY_DSGCR_SDRMODE_DEFVAL
+#undef DDR_PHY_DSGCR_SDRMODE_SHIFT
+#undef DDR_PHY_DSGCR_SDRMODE_MASK
 #define DDR_PHY_DSGCR_SDRMODE_DEFVAL                           0x02A04101
 #define DDR_PHY_DSGCR_SDRMODE_SHIFT                            19
 #define DDR_PHY_DSGCR_SDRMODE_MASK                             0x00180000U
@@ -8949,9 +8949,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DSGCR_RESERVED_18_DEFVAL 
-#undef DDR_PHY_DSGCR_RESERVED_18_SHIFT 
-#undef DDR_PHY_DSGCR_RESERVED_18_MASK 
+#undef DDR_PHY_DSGCR_RESERVED_18_DEFVAL
+#undef DDR_PHY_DSGCR_RESERVED_18_SHIFT
+#undef DDR_PHY_DSGCR_RESERVED_18_MASK
 #define DDR_PHY_DSGCR_RESERVED_18_DEFVAL                       0x02A04101
 #define DDR_PHY_DSGCR_RESERVED_18_SHIFT                        18
 #define DDR_PHY_DSGCR_RESERVED_18_MASK                         0x00040000U
@@ -8959,9 +8959,9 @@
 /*
 * ATO Analog Test Enable
 */
-#undef DDR_PHY_DSGCR_ATOAE_DEFVAL 
-#undef DDR_PHY_DSGCR_ATOAE_SHIFT 
-#undef DDR_PHY_DSGCR_ATOAE_MASK 
+#undef DDR_PHY_DSGCR_ATOAE_DEFVAL
+#undef DDR_PHY_DSGCR_ATOAE_SHIFT
+#undef DDR_PHY_DSGCR_ATOAE_MASK
 #define DDR_PHY_DSGCR_ATOAE_DEFVAL                             0x02A04101
 #define DDR_PHY_DSGCR_ATOAE_SHIFT                              17
 #define DDR_PHY_DSGCR_ATOAE_MASK                               0x00020000U
@@ -8969,9 +8969,9 @@
 /*
 * DTO Output Enable
 */
-#undef DDR_PHY_DSGCR_DTOOE_DEFVAL 
-#undef DDR_PHY_DSGCR_DTOOE_SHIFT 
-#undef DDR_PHY_DSGCR_DTOOE_MASK 
+#undef DDR_PHY_DSGCR_DTOOE_DEFVAL
+#undef DDR_PHY_DSGCR_DTOOE_SHIFT
+#undef DDR_PHY_DSGCR_DTOOE_MASK
 #define DDR_PHY_DSGCR_DTOOE_DEFVAL                             0x02A04101
 #define DDR_PHY_DSGCR_DTOOE_SHIFT                              16
 #define DDR_PHY_DSGCR_DTOOE_MASK                               0x00010000U
@@ -8979,9 +8979,9 @@
 /*
 * DTO I/O Mode
 */
-#undef DDR_PHY_DSGCR_DTOIOM_DEFVAL 
-#undef DDR_PHY_DSGCR_DTOIOM_SHIFT 
-#undef DDR_PHY_DSGCR_DTOIOM_MASK 
+#undef DDR_PHY_DSGCR_DTOIOM_DEFVAL
+#undef DDR_PHY_DSGCR_DTOIOM_SHIFT
+#undef DDR_PHY_DSGCR_DTOIOM_MASK
 #define DDR_PHY_DSGCR_DTOIOM_DEFVAL                            0x02A04101
 #define DDR_PHY_DSGCR_DTOIOM_SHIFT                             15
 #define DDR_PHY_DSGCR_DTOIOM_MASK                              0x00008000U
@@ -8989,9 +8989,9 @@
 /*
 * DTO Power Down Receiver
 */
-#undef DDR_PHY_DSGCR_DTOPDR_DEFVAL 
-#undef DDR_PHY_DSGCR_DTOPDR_SHIFT 
-#undef DDR_PHY_DSGCR_DTOPDR_MASK 
+#undef DDR_PHY_DSGCR_DTOPDR_DEFVAL
+#undef DDR_PHY_DSGCR_DTOPDR_SHIFT
+#undef DDR_PHY_DSGCR_DTOPDR_MASK
 #define DDR_PHY_DSGCR_DTOPDR_DEFVAL                            0x02A04101
 #define DDR_PHY_DSGCR_DTOPDR_SHIFT                             14
 #define DDR_PHY_DSGCR_DTOPDR_MASK                              0x00004000U
@@ -8999,9 +8999,9 @@
 /*
 * Reserved. Return zeroes on reads
 */
-#undef DDR_PHY_DSGCR_RESERVED_13_DEFVAL 
-#undef DDR_PHY_DSGCR_RESERVED_13_SHIFT 
-#undef DDR_PHY_DSGCR_RESERVED_13_MASK 
+#undef DDR_PHY_DSGCR_RESERVED_13_DEFVAL
+#undef DDR_PHY_DSGCR_RESERVED_13_SHIFT
+#undef DDR_PHY_DSGCR_RESERVED_13_MASK
 #define DDR_PHY_DSGCR_RESERVED_13_DEFVAL                       0x02A04101
 #define DDR_PHY_DSGCR_RESERVED_13_SHIFT                        13
 #define DDR_PHY_DSGCR_RESERVED_13_MASK                         0x00002000U
@@ -9009,9 +9009,9 @@
 /*
 * DTO On-Die Termination
 */
-#undef DDR_PHY_DSGCR_DTOODT_DEFVAL 
-#undef DDR_PHY_DSGCR_DTOODT_SHIFT 
-#undef DDR_PHY_DSGCR_DTOODT_MASK 
+#undef DDR_PHY_DSGCR_DTOODT_DEFVAL
+#undef DDR_PHY_DSGCR_DTOODT_SHIFT
+#undef DDR_PHY_DSGCR_DTOODT_MASK
 #define DDR_PHY_DSGCR_DTOODT_DEFVAL                            0x02A04101
 #define DDR_PHY_DSGCR_DTOODT_SHIFT                             12
 #define DDR_PHY_DSGCR_DTOODT_MASK                              0x00001000U
@@ -9019,9 +9019,9 @@
 /*
 * PHY Update Acknowledge Delay
 */
-#undef DDR_PHY_DSGCR_PUAD_DEFVAL 
-#undef DDR_PHY_DSGCR_PUAD_SHIFT 
-#undef DDR_PHY_DSGCR_PUAD_MASK 
+#undef DDR_PHY_DSGCR_PUAD_DEFVAL
+#undef DDR_PHY_DSGCR_PUAD_SHIFT
+#undef DDR_PHY_DSGCR_PUAD_MASK
 #define DDR_PHY_DSGCR_PUAD_DEFVAL                              0x02A04101
 #define DDR_PHY_DSGCR_PUAD_SHIFT                               6
 #define DDR_PHY_DSGCR_PUAD_MASK                                0x00000FC0U
@@ -9029,9 +9029,9 @@
 /*
 * Controller Update Acknowledge Enable
 */
-#undef DDR_PHY_DSGCR_CUAEN_DEFVAL 
-#undef DDR_PHY_DSGCR_CUAEN_SHIFT 
-#undef DDR_PHY_DSGCR_CUAEN_MASK 
+#undef DDR_PHY_DSGCR_CUAEN_DEFVAL
+#undef DDR_PHY_DSGCR_CUAEN_SHIFT
+#undef DDR_PHY_DSGCR_CUAEN_MASK
 #define DDR_PHY_DSGCR_CUAEN_DEFVAL                             0x02A04101
 #define DDR_PHY_DSGCR_CUAEN_SHIFT                              5
 #define DDR_PHY_DSGCR_CUAEN_MASK                               0x00000020U
@@ -9039,9 +9039,9 @@
 /*
 * Reserved. Return zeroes on reads
 */
-#undef DDR_PHY_DSGCR_RESERVED_4_3_DEFVAL 
-#undef DDR_PHY_DSGCR_RESERVED_4_3_SHIFT 
-#undef DDR_PHY_DSGCR_RESERVED_4_3_MASK 
+#undef DDR_PHY_DSGCR_RESERVED_4_3_DEFVAL
+#undef DDR_PHY_DSGCR_RESERVED_4_3_SHIFT
+#undef DDR_PHY_DSGCR_RESERVED_4_3_MASK
 #define DDR_PHY_DSGCR_RESERVED_4_3_DEFVAL                      0x02A04101
 #define DDR_PHY_DSGCR_RESERVED_4_3_SHIFT                       3
 #define DDR_PHY_DSGCR_RESERVED_4_3_MASK                        0x00000018U
@@ -9049,9 +9049,9 @@
 /*
 * Controller Impedance Update Enable
 */
-#undef DDR_PHY_DSGCR_CTLZUEN_DEFVAL 
-#undef DDR_PHY_DSGCR_CTLZUEN_SHIFT 
-#undef DDR_PHY_DSGCR_CTLZUEN_MASK 
+#undef DDR_PHY_DSGCR_CTLZUEN_DEFVAL
+#undef DDR_PHY_DSGCR_CTLZUEN_SHIFT
+#undef DDR_PHY_DSGCR_CTLZUEN_MASK
 #define DDR_PHY_DSGCR_CTLZUEN_DEFVAL                           0x02A04101
 #define DDR_PHY_DSGCR_CTLZUEN_SHIFT                            2
 #define DDR_PHY_DSGCR_CTLZUEN_MASK                             0x00000004U
@@ -9059,9 +9059,9 @@
 /*
 * Reserved. Return zeroes on reads
 */
-#undef DDR_PHY_DSGCR_RESERVED_1_DEFVAL 
-#undef DDR_PHY_DSGCR_RESERVED_1_SHIFT 
-#undef DDR_PHY_DSGCR_RESERVED_1_MASK 
+#undef DDR_PHY_DSGCR_RESERVED_1_DEFVAL
+#undef DDR_PHY_DSGCR_RESERVED_1_SHIFT
+#undef DDR_PHY_DSGCR_RESERVED_1_MASK
 #define DDR_PHY_DSGCR_RESERVED_1_DEFVAL                        0x02A04101
 #define DDR_PHY_DSGCR_RESERVED_1_SHIFT                         1
 #define DDR_PHY_DSGCR_RESERVED_1_MASK                          0x00000002U
@@ -9069,9 +9069,9 @@
 /*
 * PHY Update Request Enable
 */
-#undef DDR_PHY_DSGCR_PUREN_DEFVAL 
-#undef DDR_PHY_DSGCR_PUREN_SHIFT 
-#undef DDR_PHY_DSGCR_PUREN_MASK 
+#undef DDR_PHY_DSGCR_PUREN_DEFVAL
+#undef DDR_PHY_DSGCR_PUREN_SHIFT
+#undef DDR_PHY_DSGCR_PUREN_MASK
 #define DDR_PHY_DSGCR_PUREN_DEFVAL                             0x02A04101
 #define DDR_PHY_DSGCR_PUREN_SHIFT                              0
 #define DDR_PHY_DSGCR_PUREN_MASK                               0x00000001U
@@ -9079,19 +9079,19 @@
 /*
 * General Purpose Register 0
 */
-#undef DDR_PHY_GPR0_GPR0_DEFVAL 
-#undef DDR_PHY_GPR0_GPR0_SHIFT 
-#undef DDR_PHY_GPR0_GPR0_MASK 
-#define DDR_PHY_GPR0_GPR0_DEFVAL                               
+#undef DDR_PHY_GPR0_GPR0_DEFVAL
+#undef DDR_PHY_GPR0_GPR0_SHIFT
+#undef DDR_PHY_GPR0_GPR0_MASK
+#define DDR_PHY_GPR0_GPR0_DEFVAL
 #define DDR_PHY_GPR0_GPR0_SHIFT                                0
 #define DDR_PHY_GPR0_GPR0_MASK                                 0xFFFFFFFFU
 
 /*
 * DDR4 Gear Down Timing.
 */
-#undef DDR_PHY_DCR_GEARDN_DEFVAL 
-#undef DDR_PHY_DCR_GEARDN_SHIFT 
-#undef DDR_PHY_DCR_GEARDN_MASK 
+#undef DDR_PHY_DCR_GEARDN_DEFVAL
+#undef DDR_PHY_DCR_GEARDN_SHIFT
+#undef DDR_PHY_DCR_GEARDN_MASK
 #define DDR_PHY_DCR_GEARDN_DEFVAL                              0x0000040D
 #define DDR_PHY_DCR_GEARDN_SHIFT                               31
 #define DDR_PHY_DCR_GEARDN_MASK                                0x80000000U
@@ -9099,9 +9099,9 @@
 /*
 * Un-used Bank Group
 */
-#undef DDR_PHY_DCR_UBG_DEFVAL 
-#undef DDR_PHY_DCR_UBG_SHIFT 
-#undef DDR_PHY_DCR_UBG_MASK 
+#undef DDR_PHY_DCR_UBG_DEFVAL
+#undef DDR_PHY_DCR_UBG_SHIFT
+#undef DDR_PHY_DCR_UBG_MASK
 #define DDR_PHY_DCR_UBG_DEFVAL                                 0x0000040D
 #define DDR_PHY_DCR_UBG_SHIFT                                  30
 #define DDR_PHY_DCR_UBG_MASK                                   0x40000000U
@@ -9109,9 +9109,9 @@
 /*
 * Un-buffered DIMM Address Mirroring
 */
-#undef DDR_PHY_DCR_UDIMM_DEFVAL 
-#undef DDR_PHY_DCR_UDIMM_SHIFT 
-#undef DDR_PHY_DCR_UDIMM_MASK 
+#undef DDR_PHY_DCR_UDIMM_DEFVAL
+#undef DDR_PHY_DCR_UDIMM_SHIFT
+#undef DDR_PHY_DCR_UDIMM_MASK
 #define DDR_PHY_DCR_UDIMM_DEFVAL                               0x0000040D
 #define DDR_PHY_DCR_UDIMM_SHIFT                                29
 #define DDR_PHY_DCR_UDIMM_MASK                                 0x20000000U
@@ -9119,9 +9119,9 @@
 /*
 * DDR 2T Timing
 */
-#undef DDR_PHY_DCR_DDR2T_DEFVAL 
-#undef DDR_PHY_DCR_DDR2T_SHIFT 
-#undef DDR_PHY_DCR_DDR2T_MASK 
+#undef DDR_PHY_DCR_DDR2T_DEFVAL
+#undef DDR_PHY_DCR_DDR2T_SHIFT
+#undef DDR_PHY_DCR_DDR2T_MASK
 #define DDR_PHY_DCR_DDR2T_DEFVAL                               0x0000040D
 #define DDR_PHY_DCR_DDR2T_SHIFT                                28
 #define DDR_PHY_DCR_DDR2T_MASK                                 0x10000000U
@@ -9129,9 +9129,9 @@
 /*
 * No Simultaneous Rank Access
 */
-#undef DDR_PHY_DCR_NOSRA_DEFVAL 
-#undef DDR_PHY_DCR_NOSRA_SHIFT 
-#undef DDR_PHY_DCR_NOSRA_MASK 
+#undef DDR_PHY_DCR_NOSRA_DEFVAL
+#undef DDR_PHY_DCR_NOSRA_SHIFT
+#undef DDR_PHY_DCR_NOSRA_MASK
 #define DDR_PHY_DCR_NOSRA_DEFVAL                               0x0000040D
 #define DDR_PHY_DCR_NOSRA_SHIFT                                27
 #define DDR_PHY_DCR_NOSRA_MASK                                 0x08000000U
@@ -9139,9 +9139,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DCR_RESERVED_26_18_DEFVAL 
-#undef DDR_PHY_DCR_RESERVED_26_18_SHIFT 
-#undef DDR_PHY_DCR_RESERVED_26_18_MASK 
+#undef DDR_PHY_DCR_RESERVED_26_18_DEFVAL
+#undef DDR_PHY_DCR_RESERVED_26_18_SHIFT
+#undef DDR_PHY_DCR_RESERVED_26_18_MASK
 #define DDR_PHY_DCR_RESERVED_26_18_DEFVAL                      0x0000040D
 #define DDR_PHY_DCR_RESERVED_26_18_SHIFT                       18
 #define DDR_PHY_DCR_RESERVED_26_18_MASK                        0x07FC0000U
@@ -9149,9 +9149,9 @@
 /*
 * Byte Mask
 */
-#undef DDR_PHY_DCR_BYTEMASK_DEFVAL 
-#undef DDR_PHY_DCR_BYTEMASK_SHIFT 
-#undef DDR_PHY_DCR_BYTEMASK_MASK 
+#undef DDR_PHY_DCR_BYTEMASK_DEFVAL
+#undef DDR_PHY_DCR_BYTEMASK_SHIFT
+#undef DDR_PHY_DCR_BYTEMASK_MASK
 #define DDR_PHY_DCR_BYTEMASK_DEFVAL                            0x0000040D
 #define DDR_PHY_DCR_BYTEMASK_SHIFT                             10
 #define DDR_PHY_DCR_BYTEMASK_MASK                              0x0003FC00U
@@ -9159,9 +9159,9 @@
 /*
 * DDR Type
 */
-#undef DDR_PHY_DCR_DDRTYPE_DEFVAL 
-#undef DDR_PHY_DCR_DDRTYPE_SHIFT 
-#undef DDR_PHY_DCR_DDRTYPE_MASK 
+#undef DDR_PHY_DCR_DDRTYPE_DEFVAL
+#undef DDR_PHY_DCR_DDRTYPE_SHIFT
+#undef DDR_PHY_DCR_DDRTYPE_MASK
 #define DDR_PHY_DCR_DDRTYPE_DEFVAL                             0x0000040D
 #define DDR_PHY_DCR_DDRTYPE_SHIFT                              8
 #define DDR_PHY_DCR_DDRTYPE_MASK                               0x00000300U
@@ -9169,9 +9169,9 @@
 /*
 * Multi-Purpose Register (MPR) DQ (DDR3 Only)
 */
-#undef DDR_PHY_DCR_MPRDQ_DEFVAL 
-#undef DDR_PHY_DCR_MPRDQ_SHIFT 
-#undef DDR_PHY_DCR_MPRDQ_MASK 
+#undef DDR_PHY_DCR_MPRDQ_DEFVAL
+#undef DDR_PHY_DCR_MPRDQ_SHIFT
+#undef DDR_PHY_DCR_MPRDQ_MASK
 #define DDR_PHY_DCR_MPRDQ_DEFVAL                               0x0000040D
 #define DDR_PHY_DCR_MPRDQ_SHIFT                                7
 #define DDR_PHY_DCR_MPRDQ_MASK                                 0x00000080U
@@ -9179,9 +9179,9 @@
 /*
 * Primary DQ (DDR3 Only)
 */
-#undef DDR_PHY_DCR_PDQ_DEFVAL 
-#undef DDR_PHY_DCR_PDQ_SHIFT 
-#undef DDR_PHY_DCR_PDQ_MASK 
+#undef DDR_PHY_DCR_PDQ_DEFVAL
+#undef DDR_PHY_DCR_PDQ_SHIFT
+#undef DDR_PHY_DCR_PDQ_MASK
 #define DDR_PHY_DCR_PDQ_DEFVAL                                 0x0000040D
 #define DDR_PHY_DCR_PDQ_SHIFT                                  4
 #define DDR_PHY_DCR_PDQ_MASK                                   0x00000070U
@@ -9189,9 +9189,9 @@
 /*
 * DDR 8-Bank
 */
-#undef DDR_PHY_DCR_DDR8BNK_DEFVAL 
-#undef DDR_PHY_DCR_DDR8BNK_SHIFT 
-#undef DDR_PHY_DCR_DDR8BNK_MASK 
+#undef DDR_PHY_DCR_DDR8BNK_DEFVAL
+#undef DDR_PHY_DCR_DDR8BNK_SHIFT
+#undef DDR_PHY_DCR_DDR8BNK_MASK
 #define DDR_PHY_DCR_DDR8BNK_DEFVAL                             0x0000040D
 #define DDR_PHY_DCR_DDR8BNK_SHIFT                              3
 #define DDR_PHY_DCR_DDR8BNK_MASK                               0x00000008U
@@ -9199,9 +9199,9 @@
 /*
 * DDR Mode
 */
-#undef DDR_PHY_DCR_DDRMD_DEFVAL 
-#undef DDR_PHY_DCR_DDRMD_SHIFT 
-#undef DDR_PHY_DCR_DDRMD_MASK 
+#undef DDR_PHY_DCR_DDRMD_DEFVAL
+#undef DDR_PHY_DCR_DDRMD_SHIFT
+#undef DDR_PHY_DCR_DDRMD_MASK
 #define DDR_PHY_DCR_DDRMD_DEFVAL                               0x0000040D
 #define DDR_PHY_DCR_DDRMD_SHIFT                                0
 #define DDR_PHY_DCR_DDRMD_MASK                                 0x00000007U
@@ -9209,9 +9209,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DTPR0_RESERVED_31_29_DEFVAL 
-#undef DDR_PHY_DTPR0_RESERVED_31_29_SHIFT 
-#undef DDR_PHY_DTPR0_RESERVED_31_29_MASK 
+#undef DDR_PHY_DTPR0_RESERVED_31_29_DEFVAL
+#undef DDR_PHY_DTPR0_RESERVED_31_29_SHIFT
+#undef DDR_PHY_DTPR0_RESERVED_31_29_MASK
 #define DDR_PHY_DTPR0_RESERVED_31_29_DEFVAL                    0x105A2D08
 #define DDR_PHY_DTPR0_RESERVED_31_29_SHIFT                     29
 #define DDR_PHY_DTPR0_RESERVED_31_29_MASK                      0xE0000000U
@@ -9219,9 +9219,9 @@
 /*
 * Activate to activate command delay (different banks)
 */
-#undef DDR_PHY_DTPR0_TRRD_DEFVAL 
-#undef DDR_PHY_DTPR0_TRRD_SHIFT 
-#undef DDR_PHY_DTPR0_TRRD_MASK 
+#undef DDR_PHY_DTPR0_TRRD_DEFVAL
+#undef DDR_PHY_DTPR0_TRRD_SHIFT
+#undef DDR_PHY_DTPR0_TRRD_MASK
 #define DDR_PHY_DTPR0_TRRD_DEFVAL                              0x105A2D08
 #define DDR_PHY_DTPR0_TRRD_SHIFT                               24
 #define DDR_PHY_DTPR0_TRRD_MASK                                0x1F000000U
@@ -9229,9 +9229,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DTPR0_RESERVED_23_DEFVAL 
-#undef DDR_PHY_DTPR0_RESERVED_23_SHIFT 
-#undef DDR_PHY_DTPR0_RESERVED_23_MASK 
+#undef DDR_PHY_DTPR0_RESERVED_23_DEFVAL
+#undef DDR_PHY_DTPR0_RESERVED_23_SHIFT
+#undef DDR_PHY_DTPR0_RESERVED_23_MASK
 #define DDR_PHY_DTPR0_RESERVED_23_DEFVAL                       0x105A2D08
 #define DDR_PHY_DTPR0_RESERVED_23_SHIFT                        23
 #define DDR_PHY_DTPR0_RESERVED_23_MASK                         0x00800000U
@@ -9239,9 +9239,9 @@
 /*
 * Activate to precharge command delay
 */
-#undef DDR_PHY_DTPR0_TRAS_DEFVAL 
-#undef DDR_PHY_DTPR0_TRAS_SHIFT 
-#undef DDR_PHY_DTPR0_TRAS_MASK 
+#undef DDR_PHY_DTPR0_TRAS_DEFVAL
+#undef DDR_PHY_DTPR0_TRAS_SHIFT
+#undef DDR_PHY_DTPR0_TRAS_MASK
 #define DDR_PHY_DTPR0_TRAS_DEFVAL                              0x105A2D08
 #define DDR_PHY_DTPR0_TRAS_SHIFT                               16
 #define DDR_PHY_DTPR0_TRAS_MASK                                0x007F0000U
@@ -9249,9 +9249,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DTPR0_RESERVED_15_DEFVAL 
-#undef DDR_PHY_DTPR0_RESERVED_15_SHIFT 
-#undef DDR_PHY_DTPR0_RESERVED_15_MASK 
+#undef DDR_PHY_DTPR0_RESERVED_15_DEFVAL
+#undef DDR_PHY_DTPR0_RESERVED_15_SHIFT
+#undef DDR_PHY_DTPR0_RESERVED_15_MASK
 #define DDR_PHY_DTPR0_RESERVED_15_DEFVAL                       0x105A2D08
 #define DDR_PHY_DTPR0_RESERVED_15_SHIFT                        15
 #define DDR_PHY_DTPR0_RESERVED_15_MASK                         0x00008000U
@@ -9259,9 +9259,9 @@
 /*
 * Precharge command period
 */
-#undef DDR_PHY_DTPR0_TRP_DEFVAL 
-#undef DDR_PHY_DTPR0_TRP_SHIFT 
-#undef DDR_PHY_DTPR0_TRP_MASK 
+#undef DDR_PHY_DTPR0_TRP_DEFVAL
+#undef DDR_PHY_DTPR0_TRP_SHIFT
+#undef DDR_PHY_DTPR0_TRP_MASK
 #define DDR_PHY_DTPR0_TRP_DEFVAL                               0x105A2D08
 #define DDR_PHY_DTPR0_TRP_SHIFT                                8
 #define DDR_PHY_DTPR0_TRP_MASK                                 0x00007F00U
@@ -9269,9 +9269,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DTPR0_RESERVED_7_5_DEFVAL 
-#undef DDR_PHY_DTPR0_RESERVED_7_5_SHIFT 
-#undef DDR_PHY_DTPR0_RESERVED_7_5_MASK 
+#undef DDR_PHY_DTPR0_RESERVED_7_5_DEFVAL
+#undef DDR_PHY_DTPR0_RESERVED_7_5_SHIFT
+#undef DDR_PHY_DTPR0_RESERVED_7_5_MASK
 #define DDR_PHY_DTPR0_RESERVED_7_5_DEFVAL                      0x105A2D08
 #define DDR_PHY_DTPR0_RESERVED_7_5_SHIFT                       5
 #define DDR_PHY_DTPR0_RESERVED_7_5_MASK                        0x000000E0U
@@ -9279,9 +9279,9 @@
 /*
 * Internal read to precharge command delay
 */
-#undef DDR_PHY_DTPR0_TRTP_DEFVAL 
-#undef DDR_PHY_DTPR0_TRTP_SHIFT 
-#undef DDR_PHY_DTPR0_TRTP_MASK 
+#undef DDR_PHY_DTPR0_TRTP_DEFVAL
+#undef DDR_PHY_DTPR0_TRTP_SHIFT
+#undef DDR_PHY_DTPR0_TRTP_MASK
 #define DDR_PHY_DTPR0_TRTP_DEFVAL                              0x105A2D08
 #define DDR_PHY_DTPR0_TRTP_SHIFT                               0
 #define DDR_PHY_DTPR0_TRTP_MASK                                0x0000001FU
@@ -9289,9 +9289,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DTPR1_RESERVED_31_DEFVAL 
-#undef DDR_PHY_DTPR1_RESERVED_31_SHIFT 
-#undef DDR_PHY_DTPR1_RESERVED_31_MASK 
+#undef DDR_PHY_DTPR1_RESERVED_31_DEFVAL
+#undef DDR_PHY_DTPR1_RESERVED_31_SHIFT
+#undef DDR_PHY_DTPR1_RESERVED_31_MASK
 #define DDR_PHY_DTPR1_RESERVED_31_DEFVAL                       0x5656041E
 #define DDR_PHY_DTPR1_RESERVED_31_SHIFT                        31
 #define DDR_PHY_DTPR1_RESERVED_31_MASK                         0x80000000U
@@ -9300,9 +9300,9 @@
 * Minimum delay from when write leveling mode is programmed to the first D
     * QS/DQS# rising edge.
 */
-#undef DDR_PHY_DTPR1_TWLMRD_DEFVAL 
-#undef DDR_PHY_DTPR1_TWLMRD_SHIFT 
-#undef DDR_PHY_DTPR1_TWLMRD_MASK 
+#undef DDR_PHY_DTPR1_TWLMRD_DEFVAL
+#undef DDR_PHY_DTPR1_TWLMRD_SHIFT
+#undef DDR_PHY_DTPR1_TWLMRD_MASK
 #define DDR_PHY_DTPR1_TWLMRD_DEFVAL                            0x5656041E
 #define DDR_PHY_DTPR1_TWLMRD_SHIFT                             24
 #define DDR_PHY_DTPR1_TWLMRD_MASK                              0x7F000000U
@@ -9310,9 +9310,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DTPR1_RESERVED_23_DEFVAL 
-#undef DDR_PHY_DTPR1_RESERVED_23_SHIFT 
-#undef DDR_PHY_DTPR1_RESERVED_23_MASK 
+#undef DDR_PHY_DTPR1_RESERVED_23_DEFVAL
+#undef DDR_PHY_DTPR1_RESERVED_23_SHIFT
+#undef DDR_PHY_DTPR1_RESERVED_23_MASK
 #define DDR_PHY_DTPR1_RESERVED_23_DEFVAL                       0x5656041E
 #define DDR_PHY_DTPR1_RESERVED_23_SHIFT                        23
 #define DDR_PHY_DTPR1_RESERVED_23_MASK                         0x00800000U
@@ -9320,9 +9320,9 @@
 /*
 * 4-bank activate period
 */
-#undef DDR_PHY_DTPR1_TFAW_DEFVAL 
-#undef DDR_PHY_DTPR1_TFAW_SHIFT 
-#undef DDR_PHY_DTPR1_TFAW_MASK 
+#undef DDR_PHY_DTPR1_TFAW_DEFVAL
+#undef DDR_PHY_DTPR1_TFAW_SHIFT
+#undef DDR_PHY_DTPR1_TFAW_MASK
 #define DDR_PHY_DTPR1_TFAW_DEFVAL                              0x5656041E
 #define DDR_PHY_DTPR1_TFAW_SHIFT                               16
 #define DDR_PHY_DTPR1_TFAW_MASK                                0x007F0000U
@@ -9330,9 +9330,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DTPR1_RESERVED_15_11_DEFVAL 
-#undef DDR_PHY_DTPR1_RESERVED_15_11_SHIFT 
-#undef DDR_PHY_DTPR1_RESERVED_15_11_MASK 
+#undef DDR_PHY_DTPR1_RESERVED_15_11_DEFVAL
+#undef DDR_PHY_DTPR1_RESERVED_15_11_SHIFT
+#undef DDR_PHY_DTPR1_RESERVED_15_11_MASK
 #define DDR_PHY_DTPR1_RESERVED_15_11_DEFVAL                    0x5656041E
 #define DDR_PHY_DTPR1_RESERVED_15_11_SHIFT                     11
 #define DDR_PHY_DTPR1_RESERVED_15_11_MASK                      0x0000F800U
@@ -9340,9 +9340,9 @@
 /*
 * Load mode update delay (DDR4 and DDR3 only)
 */
-#undef DDR_PHY_DTPR1_TMOD_DEFVAL 
-#undef DDR_PHY_DTPR1_TMOD_SHIFT 
-#undef DDR_PHY_DTPR1_TMOD_MASK 
+#undef DDR_PHY_DTPR1_TMOD_DEFVAL
+#undef DDR_PHY_DTPR1_TMOD_SHIFT
+#undef DDR_PHY_DTPR1_TMOD_MASK
 #define DDR_PHY_DTPR1_TMOD_DEFVAL                              0x5656041E
 #define DDR_PHY_DTPR1_TMOD_SHIFT                               8
 #define DDR_PHY_DTPR1_TMOD_MASK                                0x00000700U
@@ -9350,9 +9350,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DTPR1_RESERVED_7_5_DEFVAL 
-#undef DDR_PHY_DTPR1_RESERVED_7_5_SHIFT 
-#undef DDR_PHY_DTPR1_RESERVED_7_5_MASK 
+#undef DDR_PHY_DTPR1_RESERVED_7_5_DEFVAL
+#undef DDR_PHY_DTPR1_RESERVED_7_5_SHIFT
+#undef DDR_PHY_DTPR1_RESERVED_7_5_MASK
 #define DDR_PHY_DTPR1_RESERVED_7_5_DEFVAL                      0x5656041E
 #define DDR_PHY_DTPR1_RESERVED_7_5_SHIFT                       5
 #define DDR_PHY_DTPR1_RESERVED_7_5_MASK                        0x000000E0U
@@ -9360,9 +9360,9 @@
 /*
 * Load mode cycle time
 */
-#undef DDR_PHY_DTPR1_TMRD_DEFVAL 
-#undef DDR_PHY_DTPR1_TMRD_SHIFT 
-#undef DDR_PHY_DTPR1_TMRD_MASK 
+#undef DDR_PHY_DTPR1_TMRD_DEFVAL
+#undef DDR_PHY_DTPR1_TMRD_SHIFT
+#undef DDR_PHY_DTPR1_TMRD_MASK
 #define DDR_PHY_DTPR1_TMRD_DEFVAL                              0x5656041E
 #define DDR_PHY_DTPR1_TMRD_SHIFT                               0
 #define DDR_PHY_DTPR1_TMRD_MASK                                0x0000001FU
@@ -9370,9 +9370,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DTPR2_RESERVED_31_29_DEFVAL 
-#undef DDR_PHY_DTPR2_RESERVED_31_29_SHIFT 
-#undef DDR_PHY_DTPR2_RESERVED_31_29_MASK 
+#undef DDR_PHY_DTPR2_RESERVED_31_29_DEFVAL
+#undef DDR_PHY_DTPR2_RESERVED_31_29_SHIFT
+#undef DDR_PHY_DTPR2_RESERVED_31_29_MASK
 #define DDR_PHY_DTPR2_RESERVED_31_29_DEFVAL                    0x000B01D0
 #define DDR_PHY_DTPR2_RESERVED_31_29_SHIFT                     29
 #define DDR_PHY_DTPR2_RESERVED_31_29_MASK                      0xE0000000U
@@ -9380,9 +9380,9 @@
 /*
 * Read to Write command delay. Valid values are
 */
-#undef DDR_PHY_DTPR2_TRTW_DEFVAL 
-#undef DDR_PHY_DTPR2_TRTW_SHIFT 
-#undef DDR_PHY_DTPR2_TRTW_MASK 
+#undef DDR_PHY_DTPR2_TRTW_DEFVAL
+#undef DDR_PHY_DTPR2_TRTW_SHIFT
+#undef DDR_PHY_DTPR2_TRTW_MASK
 #define DDR_PHY_DTPR2_TRTW_DEFVAL                              0x000B01D0
 #define DDR_PHY_DTPR2_TRTW_SHIFT                               28
 #define DDR_PHY_DTPR2_TRTW_MASK                                0x10000000U
@@ -9390,9 +9390,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DTPR2_RESERVED_27_25_DEFVAL 
-#undef DDR_PHY_DTPR2_RESERVED_27_25_SHIFT 
-#undef DDR_PHY_DTPR2_RESERVED_27_25_MASK 
+#undef DDR_PHY_DTPR2_RESERVED_27_25_DEFVAL
+#undef DDR_PHY_DTPR2_RESERVED_27_25_SHIFT
+#undef DDR_PHY_DTPR2_RESERVED_27_25_MASK
 #define DDR_PHY_DTPR2_RESERVED_27_25_DEFVAL                    0x000B01D0
 #define DDR_PHY_DTPR2_RESERVED_27_25_SHIFT                     25
 #define DDR_PHY_DTPR2_RESERVED_27_25_MASK                      0x0E000000U
@@ -9400,9 +9400,9 @@
 /*
 * Read to ODT delay (DDR3 only)
 */
-#undef DDR_PHY_DTPR2_TRTODT_DEFVAL 
-#undef DDR_PHY_DTPR2_TRTODT_SHIFT 
-#undef DDR_PHY_DTPR2_TRTODT_MASK 
+#undef DDR_PHY_DTPR2_TRTODT_DEFVAL
+#undef DDR_PHY_DTPR2_TRTODT_SHIFT
+#undef DDR_PHY_DTPR2_TRTODT_MASK
 #define DDR_PHY_DTPR2_TRTODT_DEFVAL                            0x000B01D0
 #define DDR_PHY_DTPR2_TRTODT_SHIFT                             24
 #define DDR_PHY_DTPR2_TRTODT_MASK                              0x01000000U
@@ -9410,9 +9410,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DTPR2_RESERVED_23_20_DEFVAL 
-#undef DDR_PHY_DTPR2_RESERVED_23_20_SHIFT 
-#undef DDR_PHY_DTPR2_RESERVED_23_20_MASK 
+#undef DDR_PHY_DTPR2_RESERVED_23_20_DEFVAL
+#undef DDR_PHY_DTPR2_RESERVED_23_20_SHIFT
+#undef DDR_PHY_DTPR2_RESERVED_23_20_MASK
 #define DDR_PHY_DTPR2_RESERVED_23_20_DEFVAL                    0x000B01D0
 #define DDR_PHY_DTPR2_RESERVED_23_20_SHIFT                     20
 #define DDR_PHY_DTPR2_RESERVED_23_20_MASK                      0x00F00000U
@@ -9420,9 +9420,9 @@
 /*
 * CKE minimum pulse width
 */
-#undef DDR_PHY_DTPR2_TCKE_DEFVAL 
-#undef DDR_PHY_DTPR2_TCKE_SHIFT 
-#undef DDR_PHY_DTPR2_TCKE_MASK 
+#undef DDR_PHY_DTPR2_TCKE_DEFVAL
+#undef DDR_PHY_DTPR2_TCKE_SHIFT
+#undef DDR_PHY_DTPR2_TCKE_MASK
 #define DDR_PHY_DTPR2_TCKE_DEFVAL                              0x000B01D0
 #define DDR_PHY_DTPR2_TCKE_SHIFT                               16
 #define DDR_PHY_DTPR2_TCKE_MASK                                0x000F0000U
@@ -9430,9 +9430,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DTPR2_RESERVED_15_10_DEFVAL 
-#undef DDR_PHY_DTPR2_RESERVED_15_10_SHIFT 
-#undef DDR_PHY_DTPR2_RESERVED_15_10_MASK 
+#undef DDR_PHY_DTPR2_RESERVED_15_10_DEFVAL
+#undef DDR_PHY_DTPR2_RESERVED_15_10_SHIFT
+#undef DDR_PHY_DTPR2_RESERVED_15_10_MASK
 #define DDR_PHY_DTPR2_RESERVED_15_10_DEFVAL                    0x000B01D0
 #define DDR_PHY_DTPR2_RESERVED_15_10_SHIFT                     10
 #define DDR_PHY_DTPR2_RESERVED_15_10_MASK                      0x0000FC00U
@@ -9440,9 +9440,9 @@
 /*
 * Self refresh exit delay
 */
-#undef DDR_PHY_DTPR2_TXS_DEFVAL 
-#undef DDR_PHY_DTPR2_TXS_SHIFT 
-#undef DDR_PHY_DTPR2_TXS_MASK 
+#undef DDR_PHY_DTPR2_TXS_DEFVAL
+#undef DDR_PHY_DTPR2_TXS_SHIFT
+#undef DDR_PHY_DTPR2_TXS_MASK
 #define DDR_PHY_DTPR2_TXS_DEFVAL                               0x000B01D0
 #define DDR_PHY_DTPR2_TXS_SHIFT                                0
 #define DDR_PHY_DTPR2_TXS_MASK                                 0x000003FFU
@@ -9450,9 +9450,9 @@
 /*
 * ODT turn-off delay extension
 */
-#undef DDR_PHY_DTPR3_TOFDX_DEFVAL 
-#undef DDR_PHY_DTPR3_TOFDX_SHIFT 
-#undef DDR_PHY_DTPR3_TOFDX_MASK 
+#undef DDR_PHY_DTPR3_TOFDX_DEFVAL
+#undef DDR_PHY_DTPR3_TOFDX_SHIFT
+#undef DDR_PHY_DTPR3_TOFDX_MASK
 #define DDR_PHY_DTPR3_TOFDX_DEFVAL                             0x02000804
 #define DDR_PHY_DTPR3_TOFDX_SHIFT                              29
 #define DDR_PHY_DTPR3_TOFDX_MASK                               0xE0000000U
@@ -9460,9 +9460,9 @@
 /*
 * Read to read and write to write command delay
 */
-#undef DDR_PHY_DTPR3_TCCD_DEFVAL 
-#undef DDR_PHY_DTPR3_TCCD_SHIFT 
-#undef DDR_PHY_DTPR3_TCCD_MASK 
+#undef DDR_PHY_DTPR3_TCCD_DEFVAL
+#undef DDR_PHY_DTPR3_TCCD_SHIFT
+#undef DDR_PHY_DTPR3_TCCD_MASK
 #define DDR_PHY_DTPR3_TCCD_DEFVAL                              0x02000804
 #define DDR_PHY_DTPR3_TCCD_SHIFT                               26
 #define DDR_PHY_DTPR3_TCCD_MASK                                0x1C000000U
@@ -9470,9 +9470,9 @@
 /*
 * DLL locking time
 */
-#undef DDR_PHY_DTPR3_TDLLK_DEFVAL 
-#undef DDR_PHY_DTPR3_TDLLK_SHIFT 
-#undef DDR_PHY_DTPR3_TDLLK_MASK 
+#undef DDR_PHY_DTPR3_TDLLK_DEFVAL
+#undef DDR_PHY_DTPR3_TDLLK_SHIFT
+#undef DDR_PHY_DTPR3_TDLLK_MASK
 #define DDR_PHY_DTPR3_TDLLK_DEFVAL                             0x02000804
 #define DDR_PHY_DTPR3_TDLLK_SHIFT                              16
 #define DDR_PHY_DTPR3_TDLLK_MASK                               0x03FF0000U
@@ -9480,9 +9480,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DTPR3_RESERVED_15_12_DEFVAL 
-#undef DDR_PHY_DTPR3_RESERVED_15_12_SHIFT 
-#undef DDR_PHY_DTPR3_RESERVED_15_12_MASK 
+#undef DDR_PHY_DTPR3_RESERVED_15_12_DEFVAL
+#undef DDR_PHY_DTPR3_RESERVED_15_12_SHIFT
+#undef DDR_PHY_DTPR3_RESERVED_15_12_MASK
 #define DDR_PHY_DTPR3_RESERVED_15_12_DEFVAL                    0x02000804
 #define DDR_PHY_DTPR3_RESERVED_15_12_SHIFT                     12
 #define DDR_PHY_DTPR3_RESERVED_15_12_MASK                      0x0000F000U
@@ -9490,9 +9490,9 @@
 /*
 * Maximum DQS output access time from CK/CK# (LPDDR2/3 only)
 */
-#undef DDR_PHY_DTPR3_TDQSCKMAX_DEFVAL 
-#undef DDR_PHY_DTPR3_TDQSCKMAX_SHIFT 
-#undef DDR_PHY_DTPR3_TDQSCKMAX_MASK 
+#undef DDR_PHY_DTPR3_TDQSCKMAX_DEFVAL
+#undef DDR_PHY_DTPR3_TDQSCKMAX_SHIFT
+#undef DDR_PHY_DTPR3_TDQSCKMAX_MASK
 #define DDR_PHY_DTPR3_TDQSCKMAX_DEFVAL                         0x02000804
 #define DDR_PHY_DTPR3_TDQSCKMAX_SHIFT                          8
 #define DDR_PHY_DTPR3_TDQSCKMAX_MASK                           0x00000F00U
@@ -9500,9 +9500,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DTPR3_RESERVED_7_3_DEFVAL 
-#undef DDR_PHY_DTPR3_RESERVED_7_3_SHIFT 
-#undef DDR_PHY_DTPR3_RESERVED_7_3_MASK 
+#undef DDR_PHY_DTPR3_RESERVED_7_3_DEFVAL
+#undef DDR_PHY_DTPR3_RESERVED_7_3_SHIFT
+#undef DDR_PHY_DTPR3_RESERVED_7_3_MASK
 #define DDR_PHY_DTPR3_RESERVED_7_3_DEFVAL                      0x02000804
 #define DDR_PHY_DTPR3_RESERVED_7_3_SHIFT                       3
 #define DDR_PHY_DTPR3_RESERVED_7_3_MASK                        0x000000F8U
@@ -9510,9 +9510,9 @@
 /*
 * DQS output access time from CK/CK# (LPDDR2/3 only)
 */
-#undef DDR_PHY_DTPR3_TDQSCK_DEFVAL 
-#undef DDR_PHY_DTPR3_TDQSCK_SHIFT 
-#undef DDR_PHY_DTPR3_TDQSCK_MASK 
+#undef DDR_PHY_DTPR3_TDQSCK_DEFVAL
+#undef DDR_PHY_DTPR3_TDQSCK_SHIFT
+#undef DDR_PHY_DTPR3_TDQSCK_MASK
 #define DDR_PHY_DTPR3_TDQSCK_DEFVAL                            0x02000804
 #define DDR_PHY_DTPR3_TDQSCK_SHIFT                             0
 #define DDR_PHY_DTPR3_TDQSCK_MASK                              0x00000007U
@@ -9520,9 +9520,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DTPR4_RESERVED_31_30_DEFVAL 
-#undef DDR_PHY_DTPR4_RESERVED_31_30_SHIFT 
-#undef DDR_PHY_DTPR4_RESERVED_31_30_MASK 
+#undef DDR_PHY_DTPR4_RESERVED_31_30_DEFVAL
+#undef DDR_PHY_DTPR4_RESERVED_31_30_SHIFT
+#undef DDR_PHY_DTPR4_RESERVED_31_30_MASK
 #define DDR_PHY_DTPR4_RESERVED_31_30_DEFVAL                    0x01C02B10
 #define DDR_PHY_DTPR4_RESERVED_31_30_SHIFT                     30
 #define DDR_PHY_DTPR4_RESERVED_31_30_MASK                      0xC0000000U
@@ -9530,9 +9530,9 @@
 /*
 * ODT turn-on/turn-off delays (DDR2 only)
 */
-#undef DDR_PHY_DTPR4_TAOND_TAOFD_DEFVAL 
-#undef DDR_PHY_DTPR4_TAOND_TAOFD_SHIFT 
-#undef DDR_PHY_DTPR4_TAOND_TAOFD_MASK 
+#undef DDR_PHY_DTPR4_TAOND_TAOFD_DEFVAL
+#undef DDR_PHY_DTPR4_TAOND_TAOFD_SHIFT
+#undef DDR_PHY_DTPR4_TAOND_TAOFD_MASK
 #define DDR_PHY_DTPR4_TAOND_TAOFD_DEFVAL                       0x01C02B10
 #define DDR_PHY_DTPR4_TAOND_TAOFD_SHIFT                        28
 #define DDR_PHY_DTPR4_TAOND_TAOFD_MASK                         0x30000000U
@@ -9540,9 +9540,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DTPR4_RESERVED_27_26_DEFVAL 
-#undef DDR_PHY_DTPR4_RESERVED_27_26_SHIFT 
-#undef DDR_PHY_DTPR4_RESERVED_27_26_MASK 
+#undef DDR_PHY_DTPR4_RESERVED_27_26_DEFVAL
+#undef DDR_PHY_DTPR4_RESERVED_27_26_SHIFT
+#undef DDR_PHY_DTPR4_RESERVED_27_26_MASK
 #define DDR_PHY_DTPR4_RESERVED_27_26_DEFVAL                    0x01C02B10
 #define DDR_PHY_DTPR4_RESERVED_27_26_SHIFT                     26
 #define DDR_PHY_DTPR4_RESERVED_27_26_MASK                      0x0C000000U
@@ -9550,9 +9550,9 @@
 /*
 * Refresh-to-Refresh
 */
-#undef DDR_PHY_DTPR4_TRFC_DEFVAL 
-#undef DDR_PHY_DTPR4_TRFC_SHIFT 
-#undef DDR_PHY_DTPR4_TRFC_MASK 
+#undef DDR_PHY_DTPR4_TRFC_DEFVAL
+#undef DDR_PHY_DTPR4_TRFC_SHIFT
+#undef DDR_PHY_DTPR4_TRFC_MASK
 #define DDR_PHY_DTPR4_TRFC_DEFVAL                              0x01C02B10
 #define DDR_PHY_DTPR4_TRFC_SHIFT                               16
 #define DDR_PHY_DTPR4_TRFC_MASK                                0x03FF0000U
@@ -9560,9 +9560,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DTPR4_RESERVED_15_14_DEFVAL 
-#undef DDR_PHY_DTPR4_RESERVED_15_14_SHIFT 
-#undef DDR_PHY_DTPR4_RESERVED_15_14_MASK 
+#undef DDR_PHY_DTPR4_RESERVED_15_14_DEFVAL
+#undef DDR_PHY_DTPR4_RESERVED_15_14_SHIFT
+#undef DDR_PHY_DTPR4_RESERVED_15_14_MASK
 #define DDR_PHY_DTPR4_RESERVED_15_14_DEFVAL                    0x01C02B10
 #define DDR_PHY_DTPR4_RESERVED_15_14_SHIFT                     14
 #define DDR_PHY_DTPR4_RESERVED_15_14_MASK                      0x0000C000U
@@ -9570,9 +9570,9 @@
 /*
 * Write leveling output delay
 */
-#undef DDR_PHY_DTPR4_TWLO_DEFVAL 
-#undef DDR_PHY_DTPR4_TWLO_SHIFT 
-#undef DDR_PHY_DTPR4_TWLO_MASK 
+#undef DDR_PHY_DTPR4_TWLO_DEFVAL
+#undef DDR_PHY_DTPR4_TWLO_SHIFT
+#undef DDR_PHY_DTPR4_TWLO_MASK
 #define DDR_PHY_DTPR4_TWLO_DEFVAL                              0x01C02B10
 #define DDR_PHY_DTPR4_TWLO_SHIFT                               8
 #define DDR_PHY_DTPR4_TWLO_MASK                                0x00003F00U
@@ -9580,9 +9580,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DTPR4_RESERVED_7_5_DEFVAL 
-#undef DDR_PHY_DTPR4_RESERVED_7_5_SHIFT 
-#undef DDR_PHY_DTPR4_RESERVED_7_5_MASK 
+#undef DDR_PHY_DTPR4_RESERVED_7_5_DEFVAL
+#undef DDR_PHY_DTPR4_RESERVED_7_5_SHIFT
+#undef DDR_PHY_DTPR4_RESERVED_7_5_MASK
 #define DDR_PHY_DTPR4_RESERVED_7_5_DEFVAL                      0x01C02B10
 #define DDR_PHY_DTPR4_RESERVED_7_5_SHIFT                       5
 #define DDR_PHY_DTPR4_RESERVED_7_5_MASK                        0x000000E0U
@@ -9590,9 +9590,9 @@
 /*
 * Power down exit delay
 */
-#undef DDR_PHY_DTPR4_TXP_DEFVAL 
-#undef DDR_PHY_DTPR4_TXP_SHIFT 
-#undef DDR_PHY_DTPR4_TXP_MASK 
+#undef DDR_PHY_DTPR4_TXP_DEFVAL
+#undef DDR_PHY_DTPR4_TXP_SHIFT
+#undef DDR_PHY_DTPR4_TXP_MASK
 #define DDR_PHY_DTPR4_TXP_DEFVAL                               0x01C02B10
 #define DDR_PHY_DTPR4_TXP_SHIFT                                0
 #define DDR_PHY_DTPR4_TXP_MASK                                 0x0000001FU
@@ -9600,9 +9600,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DTPR5_RESERVED_31_24_DEFVAL 
-#undef DDR_PHY_DTPR5_RESERVED_31_24_SHIFT 
-#undef DDR_PHY_DTPR5_RESERVED_31_24_MASK 
+#undef DDR_PHY_DTPR5_RESERVED_31_24_DEFVAL
+#undef DDR_PHY_DTPR5_RESERVED_31_24_SHIFT
+#undef DDR_PHY_DTPR5_RESERVED_31_24_MASK
 #define DDR_PHY_DTPR5_RESERVED_31_24_DEFVAL                    0x00872716
 #define DDR_PHY_DTPR5_RESERVED_31_24_SHIFT                     24
 #define DDR_PHY_DTPR5_RESERVED_31_24_MASK                      0xFF000000U
@@ -9610,9 +9610,9 @@
 /*
 * Activate to activate command delay (same bank)
 */
-#undef DDR_PHY_DTPR5_TRC_DEFVAL 
-#undef DDR_PHY_DTPR5_TRC_SHIFT 
-#undef DDR_PHY_DTPR5_TRC_MASK 
+#undef DDR_PHY_DTPR5_TRC_DEFVAL
+#undef DDR_PHY_DTPR5_TRC_SHIFT
+#undef DDR_PHY_DTPR5_TRC_MASK
 #define DDR_PHY_DTPR5_TRC_DEFVAL                               0x00872716
 #define DDR_PHY_DTPR5_TRC_SHIFT                                16
 #define DDR_PHY_DTPR5_TRC_MASK                                 0x00FF0000U
@@ -9620,9 +9620,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DTPR5_RESERVED_15_DEFVAL 
-#undef DDR_PHY_DTPR5_RESERVED_15_SHIFT 
-#undef DDR_PHY_DTPR5_RESERVED_15_MASK 
+#undef DDR_PHY_DTPR5_RESERVED_15_DEFVAL
+#undef DDR_PHY_DTPR5_RESERVED_15_SHIFT
+#undef DDR_PHY_DTPR5_RESERVED_15_MASK
 #define DDR_PHY_DTPR5_RESERVED_15_DEFVAL                       0x00872716
 #define DDR_PHY_DTPR5_RESERVED_15_SHIFT                        15
 #define DDR_PHY_DTPR5_RESERVED_15_MASK                         0x00008000U
@@ -9630,9 +9630,9 @@
 /*
 * Activate to read or write delay
 */
-#undef DDR_PHY_DTPR5_TRCD_DEFVAL 
-#undef DDR_PHY_DTPR5_TRCD_SHIFT 
-#undef DDR_PHY_DTPR5_TRCD_MASK 
+#undef DDR_PHY_DTPR5_TRCD_DEFVAL
+#undef DDR_PHY_DTPR5_TRCD_SHIFT
+#undef DDR_PHY_DTPR5_TRCD_MASK
 #define DDR_PHY_DTPR5_TRCD_DEFVAL                              0x00872716
 #define DDR_PHY_DTPR5_TRCD_SHIFT                               8
 #define DDR_PHY_DTPR5_TRCD_MASK                                0x00007F00U
@@ -9640,9 +9640,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DTPR5_RESERVED_7_5_DEFVAL 
-#undef DDR_PHY_DTPR5_RESERVED_7_5_SHIFT 
-#undef DDR_PHY_DTPR5_RESERVED_7_5_MASK 
+#undef DDR_PHY_DTPR5_RESERVED_7_5_DEFVAL
+#undef DDR_PHY_DTPR5_RESERVED_7_5_SHIFT
+#undef DDR_PHY_DTPR5_RESERVED_7_5_MASK
 #define DDR_PHY_DTPR5_RESERVED_7_5_DEFVAL                      0x00872716
 #define DDR_PHY_DTPR5_RESERVED_7_5_SHIFT                       5
 #define DDR_PHY_DTPR5_RESERVED_7_5_MASK                        0x000000E0U
@@ -9650,9 +9650,9 @@
 /*
 * Internal write to read command delay
 */
-#undef DDR_PHY_DTPR5_TWTR_DEFVAL 
-#undef DDR_PHY_DTPR5_TWTR_SHIFT 
-#undef DDR_PHY_DTPR5_TWTR_MASK 
+#undef DDR_PHY_DTPR5_TWTR_DEFVAL
+#undef DDR_PHY_DTPR5_TWTR_SHIFT
+#undef DDR_PHY_DTPR5_TWTR_MASK
 #define DDR_PHY_DTPR5_TWTR_DEFVAL                              0x00872716
 #define DDR_PHY_DTPR5_TWTR_SHIFT                               0
 #define DDR_PHY_DTPR5_TWTR_MASK                                0x0000001FU
@@ -9660,9 +9660,9 @@
 /*
 * PUB Write Latency Enable
 */
-#undef DDR_PHY_DTPR6_PUBWLEN_DEFVAL 
-#undef DDR_PHY_DTPR6_PUBWLEN_SHIFT 
-#undef DDR_PHY_DTPR6_PUBWLEN_MASK 
+#undef DDR_PHY_DTPR6_PUBWLEN_DEFVAL
+#undef DDR_PHY_DTPR6_PUBWLEN_SHIFT
+#undef DDR_PHY_DTPR6_PUBWLEN_MASK
 #define DDR_PHY_DTPR6_PUBWLEN_DEFVAL                           0x00000505
 #define DDR_PHY_DTPR6_PUBWLEN_SHIFT                            31
 #define DDR_PHY_DTPR6_PUBWLEN_MASK                             0x80000000U
@@ -9670,9 +9670,9 @@
 /*
 * PUB Read Latency Enable
 */
-#undef DDR_PHY_DTPR6_PUBRLEN_DEFVAL 
-#undef DDR_PHY_DTPR6_PUBRLEN_SHIFT 
-#undef DDR_PHY_DTPR6_PUBRLEN_MASK 
+#undef DDR_PHY_DTPR6_PUBRLEN_DEFVAL
+#undef DDR_PHY_DTPR6_PUBRLEN_SHIFT
+#undef DDR_PHY_DTPR6_PUBRLEN_MASK
 #define DDR_PHY_DTPR6_PUBRLEN_DEFVAL                           0x00000505
 #define DDR_PHY_DTPR6_PUBRLEN_SHIFT                            30
 #define DDR_PHY_DTPR6_PUBRLEN_MASK                             0x40000000U
@@ -9680,9 +9680,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DTPR6_RESERVED_29_14_DEFVAL 
-#undef DDR_PHY_DTPR6_RESERVED_29_14_SHIFT 
-#undef DDR_PHY_DTPR6_RESERVED_29_14_MASK 
+#undef DDR_PHY_DTPR6_RESERVED_29_14_DEFVAL
+#undef DDR_PHY_DTPR6_RESERVED_29_14_SHIFT
+#undef DDR_PHY_DTPR6_RESERVED_29_14_MASK
 #define DDR_PHY_DTPR6_RESERVED_29_14_DEFVAL                    0x00000505
 #define DDR_PHY_DTPR6_RESERVED_29_14_SHIFT                     14
 #define DDR_PHY_DTPR6_RESERVED_29_14_MASK                      0x3FFFC000U
@@ -9690,9 +9690,9 @@
 /*
 * Write Latency
 */
-#undef DDR_PHY_DTPR6_PUBWL_DEFVAL 
-#undef DDR_PHY_DTPR6_PUBWL_SHIFT 
-#undef DDR_PHY_DTPR6_PUBWL_MASK 
+#undef DDR_PHY_DTPR6_PUBWL_DEFVAL
+#undef DDR_PHY_DTPR6_PUBWL_SHIFT
+#undef DDR_PHY_DTPR6_PUBWL_MASK
 #define DDR_PHY_DTPR6_PUBWL_DEFVAL                             0x00000505
 #define DDR_PHY_DTPR6_PUBWL_SHIFT                              8
 #define DDR_PHY_DTPR6_PUBWL_MASK                               0x00003F00U
@@ -9700,9 +9700,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DTPR6_RESERVED_7_6_DEFVAL 
-#undef DDR_PHY_DTPR6_RESERVED_7_6_SHIFT 
-#undef DDR_PHY_DTPR6_RESERVED_7_6_MASK 
+#undef DDR_PHY_DTPR6_RESERVED_7_6_DEFVAL
+#undef DDR_PHY_DTPR6_RESERVED_7_6_SHIFT
+#undef DDR_PHY_DTPR6_RESERVED_7_6_MASK
 #define DDR_PHY_DTPR6_RESERVED_7_6_DEFVAL                      0x00000505
 #define DDR_PHY_DTPR6_RESERVED_7_6_SHIFT                       6
 #define DDR_PHY_DTPR6_RESERVED_7_6_MASK                        0x000000C0U
@@ -9710,9 +9710,9 @@
 /*
 * Read Latency
 */
-#undef DDR_PHY_DTPR6_PUBRL_DEFVAL 
-#undef DDR_PHY_DTPR6_PUBRL_SHIFT 
-#undef DDR_PHY_DTPR6_PUBRL_MASK 
+#undef DDR_PHY_DTPR6_PUBRL_DEFVAL
+#undef DDR_PHY_DTPR6_PUBRL_SHIFT
+#undef DDR_PHY_DTPR6_PUBRL_MASK
 #define DDR_PHY_DTPR6_PUBRL_DEFVAL                             0x00000505
 #define DDR_PHY_DTPR6_PUBRL_SHIFT                              0
 #define DDR_PHY_DTPR6_PUBRL_MASK                               0x0000003FU
@@ -9720,9 +9720,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_RDIMMGCR0_RESERVED_31_DEFVAL 
-#undef DDR_PHY_RDIMMGCR0_RESERVED_31_SHIFT 
-#undef DDR_PHY_RDIMMGCR0_RESERVED_31_MASK 
+#undef DDR_PHY_RDIMMGCR0_RESERVED_31_DEFVAL
+#undef DDR_PHY_RDIMMGCR0_RESERVED_31_SHIFT
+#undef DDR_PHY_RDIMMGCR0_RESERVED_31_MASK
 #define DDR_PHY_RDIMMGCR0_RESERVED_31_DEFVAL                   0x08400020
 #define DDR_PHY_RDIMMGCR0_RESERVED_31_SHIFT                    31
 #define DDR_PHY_RDIMMGCR0_RESERVED_31_MASK                     0x80000000U
@@ -9730,9 +9730,9 @@
 /*
 * RDMIMM Quad CS Enable
 */
-#undef DDR_PHY_RDIMMGCR0_QCSEN_DEFVAL 
-#undef DDR_PHY_RDIMMGCR0_QCSEN_SHIFT 
-#undef DDR_PHY_RDIMMGCR0_QCSEN_MASK 
+#undef DDR_PHY_RDIMMGCR0_QCSEN_DEFVAL
+#undef DDR_PHY_RDIMMGCR0_QCSEN_SHIFT
+#undef DDR_PHY_RDIMMGCR0_QCSEN_MASK
 #define DDR_PHY_RDIMMGCR0_QCSEN_DEFVAL                         0x08400020
 #define DDR_PHY_RDIMMGCR0_QCSEN_SHIFT                          30
 #define DDR_PHY_RDIMMGCR0_QCSEN_MASK                           0x40000000U
@@ -9740,9 +9740,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_RDIMMGCR0_RESERVED_29_28_DEFVAL 
-#undef DDR_PHY_RDIMMGCR0_RESERVED_29_28_SHIFT 
-#undef DDR_PHY_RDIMMGCR0_RESERVED_29_28_MASK 
+#undef DDR_PHY_RDIMMGCR0_RESERVED_29_28_DEFVAL
+#undef DDR_PHY_RDIMMGCR0_RESERVED_29_28_SHIFT
+#undef DDR_PHY_RDIMMGCR0_RESERVED_29_28_MASK
 #define DDR_PHY_RDIMMGCR0_RESERVED_29_28_DEFVAL                0x08400020
 #define DDR_PHY_RDIMMGCR0_RESERVED_29_28_SHIFT                 28
 #define DDR_PHY_RDIMMGCR0_RESERVED_29_28_MASK                  0x30000000U
@@ -9750,9 +9750,9 @@
 /*
 * RDIMM Outputs I/O Mode
 */
-#undef DDR_PHY_RDIMMGCR0_RDIMMIOM_DEFVAL 
-#undef DDR_PHY_RDIMMGCR0_RDIMMIOM_SHIFT 
-#undef DDR_PHY_RDIMMGCR0_RDIMMIOM_MASK 
+#undef DDR_PHY_RDIMMGCR0_RDIMMIOM_DEFVAL
+#undef DDR_PHY_RDIMMGCR0_RDIMMIOM_SHIFT
+#undef DDR_PHY_RDIMMGCR0_RDIMMIOM_MASK
 #define DDR_PHY_RDIMMGCR0_RDIMMIOM_DEFVAL                      0x08400020
 #define DDR_PHY_RDIMMGCR0_RDIMMIOM_SHIFT                       27
 #define DDR_PHY_RDIMMGCR0_RDIMMIOM_MASK                        0x08000000U
@@ -9760,9 +9760,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_RDIMMGCR0_RESERVED_26_24_DEFVAL 
-#undef DDR_PHY_RDIMMGCR0_RESERVED_26_24_SHIFT 
-#undef DDR_PHY_RDIMMGCR0_RESERVED_26_24_MASK 
+#undef DDR_PHY_RDIMMGCR0_RESERVED_26_24_DEFVAL
+#undef DDR_PHY_RDIMMGCR0_RESERVED_26_24_SHIFT
+#undef DDR_PHY_RDIMMGCR0_RESERVED_26_24_MASK
 #define DDR_PHY_RDIMMGCR0_RESERVED_26_24_DEFVAL                0x08400020
 #define DDR_PHY_RDIMMGCR0_RESERVED_26_24_SHIFT                 24
 #define DDR_PHY_RDIMMGCR0_RESERVED_26_24_MASK                  0x07000000U
@@ -9770,9 +9770,9 @@
 /*
 * ERROUT# Output Enable
 */
-#undef DDR_PHY_RDIMMGCR0_ERROUTOE_DEFVAL 
-#undef DDR_PHY_RDIMMGCR0_ERROUTOE_SHIFT 
-#undef DDR_PHY_RDIMMGCR0_ERROUTOE_MASK 
+#undef DDR_PHY_RDIMMGCR0_ERROUTOE_DEFVAL
+#undef DDR_PHY_RDIMMGCR0_ERROUTOE_SHIFT
+#undef DDR_PHY_RDIMMGCR0_ERROUTOE_MASK
 #define DDR_PHY_RDIMMGCR0_ERROUTOE_DEFVAL                      0x08400020
 #define DDR_PHY_RDIMMGCR0_ERROUTOE_SHIFT                       23
 #define DDR_PHY_RDIMMGCR0_ERROUTOE_MASK                        0x00800000U
@@ -9780,9 +9780,9 @@
 /*
 * ERROUT# I/O Mode
 */
-#undef DDR_PHY_RDIMMGCR0_ERROUTIOM_DEFVAL 
-#undef DDR_PHY_RDIMMGCR0_ERROUTIOM_SHIFT 
-#undef DDR_PHY_RDIMMGCR0_ERROUTIOM_MASK 
+#undef DDR_PHY_RDIMMGCR0_ERROUTIOM_DEFVAL
+#undef DDR_PHY_RDIMMGCR0_ERROUTIOM_SHIFT
+#undef DDR_PHY_RDIMMGCR0_ERROUTIOM_MASK
 #define DDR_PHY_RDIMMGCR0_ERROUTIOM_DEFVAL                     0x08400020
 #define DDR_PHY_RDIMMGCR0_ERROUTIOM_SHIFT                      22
 #define DDR_PHY_RDIMMGCR0_ERROUTIOM_MASK                       0x00400000U
@@ -9790,9 +9790,9 @@
 /*
 * ERROUT# Power Down Receiver
 */
-#undef DDR_PHY_RDIMMGCR0_ERROUTPDR_DEFVAL 
-#undef DDR_PHY_RDIMMGCR0_ERROUTPDR_SHIFT 
-#undef DDR_PHY_RDIMMGCR0_ERROUTPDR_MASK 
+#undef DDR_PHY_RDIMMGCR0_ERROUTPDR_DEFVAL
+#undef DDR_PHY_RDIMMGCR0_ERROUTPDR_SHIFT
+#undef DDR_PHY_RDIMMGCR0_ERROUTPDR_MASK
 #define DDR_PHY_RDIMMGCR0_ERROUTPDR_DEFVAL                     0x08400020
 #define DDR_PHY_RDIMMGCR0_ERROUTPDR_SHIFT                      21
 #define DDR_PHY_RDIMMGCR0_ERROUTPDR_MASK                       0x00200000U
@@ -9800,9 +9800,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_RDIMMGCR0_RESERVED_20_DEFVAL 
-#undef DDR_PHY_RDIMMGCR0_RESERVED_20_SHIFT 
-#undef DDR_PHY_RDIMMGCR0_RESERVED_20_MASK 
+#undef DDR_PHY_RDIMMGCR0_RESERVED_20_DEFVAL
+#undef DDR_PHY_RDIMMGCR0_RESERVED_20_SHIFT
+#undef DDR_PHY_RDIMMGCR0_RESERVED_20_MASK
 #define DDR_PHY_RDIMMGCR0_RESERVED_20_DEFVAL                   0x08400020
 #define DDR_PHY_RDIMMGCR0_RESERVED_20_SHIFT                    20
 #define DDR_PHY_RDIMMGCR0_RESERVED_20_MASK                     0x00100000U
@@ -9810,9 +9810,9 @@
 /*
 * ERROUT# On-Die Termination
 */
-#undef DDR_PHY_RDIMMGCR0_ERROUTODT_DEFVAL 
-#undef DDR_PHY_RDIMMGCR0_ERROUTODT_SHIFT 
-#undef DDR_PHY_RDIMMGCR0_ERROUTODT_MASK 
+#undef DDR_PHY_RDIMMGCR0_ERROUTODT_DEFVAL
+#undef DDR_PHY_RDIMMGCR0_ERROUTODT_SHIFT
+#undef DDR_PHY_RDIMMGCR0_ERROUTODT_MASK
 #define DDR_PHY_RDIMMGCR0_ERROUTODT_DEFVAL                     0x08400020
 #define DDR_PHY_RDIMMGCR0_ERROUTODT_SHIFT                      19
 #define DDR_PHY_RDIMMGCR0_ERROUTODT_MASK                       0x00080000U
@@ -9820,9 +9820,9 @@
 /*
 * Load Reduced DIMM
 */
-#undef DDR_PHY_RDIMMGCR0_LRDIMM_DEFVAL 
-#undef DDR_PHY_RDIMMGCR0_LRDIMM_SHIFT 
-#undef DDR_PHY_RDIMMGCR0_LRDIMM_MASK 
+#undef DDR_PHY_RDIMMGCR0_LRDIMM_DEFVAL
+#undef DDR_PHY_RDIMMGCR0_LRDIMM_SHIFT
+#undef DDR_PHY_RDIMMGCR0_LRDIMM_MASK
 #define DDR_PHY_RDIMMGCR0_LRDIMM_DEFVAL                        0x08400020
 #define DDR_PHY_RDIMMGCR0_LRDIMM_SHIFT                         18
 #define DDR_PHY_RDIMMGCR0_LRDIMM_MASK                          0x00040000U
@@ -9830,9 +9830,9 @@
 /*
 * PAR_IN I/O Mode
 */
-#undef DDR_PHY_RDIMMGCR0_PARINIOM_DEFVAL 
-#undef DDR_PHY_RDIMMGCR0_PARINIOM_SHIFT 
-#undef DDR_PHY_RDIMMGCR0_PARINIOM_MASK 
+#undef DDR_PHY_RDIMMGCR0_PARINIOM_DEFVAL
+#undef DDR_PHY_RDIMMGCR0_PARINIOM_SHIFT
+#undef DDR_PHY_RDIMMGCR0_PARINIOM_MASK
 #define DDR_PHY_RDIMMGCR0_PARINIOM_DEFVAL                      0x08400020
 #define DDR_PHY_RDIMMGCR0_PARINIOM_SHIFT                       17
 #define DDR_PHY_RDIMMGCR0_PARINIOM_MASK                        0x00020000U
@@ -9840,9 +9840,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_RDIMMGCR0_RESERVED_16_8_DEFVAL 
-#undef DDR_PHY_RDIMMGCR0_RESERVED_16_8_SHIFT 
-#undef DDR_PHY_RDIMMGCR0_RESERVED_16_8_MASK 
+#undef DDR_PHY_RDIMMGCR0_RESERVED_16_8_DEFVAL
+#undef DDR_PHY_RDIMMGCR0_RESERVED_16_8_SHIFT
+#undef DDR_PHY_RDIMMGCR0_RESERVED_16_8_MASK
 #define DDR_PHY_RDIMMGCR0_RESERVED_16_8_DEFVAL                 0x08400020
 #define DDR_PHY_RDIMMGCR0_RESERVED_16_8_SHIFT                  8
 #define DDR_PHY_RDIMMGCR0_RESERVED_16_8_MASK                   0x0001FF00U
@@ -9850,9 +9850,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_DEFVAL 
-#undef DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_SHIFT 
-#undef DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_MASK 
+#undef DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_DEFVAL
+#undef DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_SHIFT
+#undef DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_MASK
 #define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_DEFVAL                 0x08400020
 #define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_SHIFT                  6
 #define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_MASK                   0x000000C0U
@@ -9860,9 +9860,9 @@
 /*
 * Rank Mirror Enable.
 */
-#undef DDR_PHY_RDIMMGCR0_RNKMRREN_DEFVAL 
-#undef DDR_PHY_RDIMMGCR0_RNKMRREN_SHIFT 
-#undef DDR_PHY_RDIMMGCR0_RNKMRREN_MASK 
+#undef DDR_PHY_RDIMMGCR0_RNKMRREN_DEFVAL
+#undef DDR_PHY_RDIMMGCR0_RNKMRREN_SHIFT
+#undef DDR_PHY_RDIMMGCR0_RNKMRREN_MASK
 #define DDR_PHY_RDIMMGCR0_RNKMRREN_DEFVAL                      0x08400020
 #define DDR_PHY_RDIMMGCR0_RNKMRREN_SHIFT                       4
 #define DDR_PHY_RDIMMGCR0_RNKMRREN_MASK                        0x00000030U
@@ -9870,9 +9870,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_RDIMMGCR0_RESERVED_3_DEFVAL 
-#undef DDR_PHY_RDIMMGCR0_RESERVED_3_SHIFT 
-#undef DDR_PHY_RDIMMGCR0_RESERVED_3_MASK 
+#undef DDR_PHY_RDIMMGCR0_RESERVED_3_DEFVAL
+#undef DDR_PHY_RDIMMGCR0_RESERVED_3_SHIFT
+#undef DDR_PHY_RDIMMGCR0_RESERVED_3_MASK
 #define DDR_PHY_RDIMMGCR0_RESERVED_3_DEFVAL                    0x08400020
 #define DDR_PHY_RDIMMGCR0_RESERVED_3_SHIFT                     3
 #define DDR_PHY_RDIMMGCR0_RESERVED_3_MASK                      0x00000008U
@@ -9880,9 +9880,9 @@
 /*
 * Stop on Parity Error
 */
-#undef DDR_PHY_RDIMMGCR0_SOPERR_DEFVAL 
-#undef DDR_PHY_RDIMMGCR0_SOPERR_SHIFT 
-#undef DDR_PHY_RDIMMGCR0_SOPERR_MASK 
+#undef DDR_PHY_RDIMMGCR0_SOPERR_DEFVAL
+#undef DDR_PHY_RDIMMGCR0_SOPERR_SHIFT
+#undef DDR_PHY_RDIMMGCR0_SOPERR_MASK
 #define DDR_PHY_RDIMMGCR0_SOPERR_DEFVAL                        0x08400020
 #define DDR_PHY_RDIMMGCR0_SOPERR_SHIFT                         2
 #define DDR_PHY_RDIMMGCR0_SOPERR_MASK                          0x00000004U
@@ -9890,9 +9890,9 @@
 /*
 * Parity Error No Registering
 */
-#undef DDR_PHY_RDIMMGCR0_ERRNOREG_DEFVAL 
-#undef DDR_PHY_RDIMMGCR0_ERRNOREG_SHIFT 
-#undef DDR_PHY_RDIMMGCR0_ERRNOREG_MASK 
+#undef DDR_PHY_RDIMMGCR0_ERRNOREG_DEFVAL
+#undef DDR_PHY_RDIMMGCR0_ERRNOREG_SHIFT
+#undef DDR_PHY_RDIMMGCR0_ERRNOREG_MASK
 #define DDR_PHY_RDIMMGCR0_ERRNOREG_DEFVAL                      0x08400020
 #define DDR_PHY_RDIMMGCR0_ERRNOREG_SHIFT                       1
 #define DDR_PHY_RDIMMGCR0_ERRNOREG_MASK                        0x00000002U
@@ -9900,9 +9900,9 @@
 /*
 * Registered DIMM
 */
-#undef DDR_PHY_RDIMMGCR0_RDIMM_DEFVAL 
-#undef DDR_PHY_RDIMMGCR0_RDIMM_SHIFT 
-#undef DDR_PHY_RDIMMGCR0_RDIMM_MASK 
+#undef DDR_PHY_RDIMMGCR0_RDIMM_DEFVAL
+#undef DDR_PHY_RDIMMGCR0_RDIMM_SHIFT
+#undef DDR_PHY_RDIMMGCR0_RDIMM_MASK
 #define DDR_PHY_RDIMMGCR0_RDIMM_DEFVAL                         0x08400020
 #define DDR_PHY_RDIMMGCR0_RDIMM_SHIFT                          0
 #define DDR_PHY_RDIMMGCR0_RDIMM_MASK                           0x00000001U
@@ -9910,9 +9910,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_RDIMMGCR1_RESERVED_31_29_DEFVAL 
-#undef DDR_PHY_RDIMMGCR1_RESERVED_31_29_SHIFT 
-#undef DDR_PHY_RDIMMGCR1_RESERVED_31_29_MASK 
+#undef DDR_PHY_RDIMMGCR1_RESERVED_31_29_DEFVAL
+#undef DDR_PHY_RDIMMGCR1_RESERVED_31_29_SHIFT
+#undef DDR_PHY_RDIMMGCR1_RESERVED_31_29_MASK
 #define DDR_PHY_RDIMMGCR1_RESERVED_31_29_DEFVAL                0x00000C80
 #define DDR_PHY_RDIMMGCR1_RESERVED_31_29_SHIFT                 29
 #define DDR_PHY_RDIMMGCR1_RESERVED_31_29_MASK                  0xE0000000U
@@ -9920,9 +9920,9 @@
 /*
 * Address [17] B-side Inversion Disable
 */
-#undef DDR_PHY_RDIMMGCR1_A17BID_DEFVAL 
-#undef DDR_PHY_RDIMMGCR1_A17BID_SHIFT 
-#undef DDR_PHY_RDIMMGCR1_A17BID_MASK 
+#undef DDR_PHY_RDIMMGCR1_A17BID_DEFVAL
+#undef DDR_PHY_RDIMMGCR1_A17BID_SHIFT
+#undef DDR_PHY_RDIMMGCR1_A17BID_MASK
 #define DDR_PHY_RDIMMGCR1_A17BID_DEFVAL                        0x00000C80
 #define DDR_PHY_RDIMMGCR1_A17BID_SHIFT                         28
 #define DDR_PHY_RDIMMGCR1_A17BID_MASK                          0x10000000U
@@ -9930,9 +9930,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_RDIMMGCR1_RESERVED_27_DEFVAL 
-#undef DDR_PHY_RDIMMGCR1_RESERVED_27_SHIFT 
-#undef DDR_PHY_RDIMMGCR1_RESERVED_27_MASK 
+#undef DDR_PHY_RDIMMGCR1_RESERVED_27_DEFVAL
+#undef DDR_PHY_RDIMMGCR1_RESERVED_27_SHIFT
+#undef DDR_PHY_RDIMMGCR1_RESERVED_27_MASK
 #define DDR_PHY_RDIMMGCR1_RESERVED_27_DEFVAL                   0x00000C80
 #define DDR_PHY_RDIMMGCR1_RESERVED_27_SHIFT                    27
 #define DDR_PHY_RDIMMGCR1_RESERVED_27_MASK                     0x08000000U
@@ -9940,9 +9940,9 @@
 /*
 * Command word to command word programming delay
 */
-#undef DDR_PHY_RDIMMGCR1_TBCMRD_L2_DEFVAL 
-#undef DDR_PHY_RDIMMGCR1_TBCMRD_L2_SHIFT 
-#undef DDR_PHY_RDIMMGCR1_TBCMRD_L2_MASK 
+#undef DDR_PHY_RDIMMGCR1_TBCMRD_L2_DEFVAL
+#undef DDR_PHY_RDIMMGCR1_TBCMRD_L2_SHIFT
+#undef DDR_PHY_RDIMMGCR1_TBCMRD_L2_MASK
 #define DDR_PHY_RDIMMGCR1_TBCMRD_L2_DEFVAL                     0x00000C80
 #define DDR_PHY_RDIMMGCR1_TBCMRD_L2_SHIFT                      24
 #define DDR_PHY_RDIMMGCR1_TBCMRD_L2_MASK                       0x07000000U
@@ -9950,9 +9950,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_RDIMMGCR1_RESERVED_23_DEFVAL 
-#undef DDR_PHY_RDIMMGCR1_RESERVED_23_SHIFT 
-#undef DDR_PHY_RDIMMGCR1_RESERVED_23_MASK 
+#undef DDR_PHY_RDIMMGCR1_RESERVED_23_DEFVAL
+#undef DDR_PHY_RDIMMGCR1_RESERVED_23_SHIFT
+#undef DDR_PHY_RDIMMGCR1_RESERVED_23_MASK
 #define DDR_PHY_RDIMMGCR1_RESERVED_23_DEFVAL                   0x00000C80
 #define DDR_PHY_RDIMMGCR1_RESERVED_23_SHIFT                    23
 #define DDR_PHY_RDIMMGCR1_RESERVED_23_MASK                     0x00800000U
@@ -9960,9 +9960,9 @@
 /*
 * Command word to command word programming delay
 */
-#undef DDR_PHY_RDIMMGCR1_TBCMRD_L_DEFVAL 
-#undef DDR_PHY_RDIMMGCR1_TBCMRD_L_SHIFT 
-#undef DDR_PHY_RDIMMGCR1_TBCMRD_L_MASK 
+#undef DDR_PHY_RDIMMGCR1_TBCMRD_L_DEFVAL
+#undef DDR_PHY_RDIMMGCR1_TBCMRD_L_SHIFT
+#undef DDR_PHY_RDIMMGCR1_TBCMRD_L_MASK
 #define DDR_PHY_RDIMMGCR1_TBCMRD_L_DEFVAL                      0x00000C80
 #define DDR_PHY_RDIMMGCR1_TBCMRD_L_SHIFT                       20
 #define DDR_PHY_RDIMMGCR1_TBCMRD_L_MASK                        0x00700000U
@@ -9970,9 +9970,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_RDIMMGCR1_RESERVED_19_DEFVAL 
-#undef DDR_PHY_RDIMMGCR1_RESERVED_19_SHIFT 
-#undef DDR_PHY_RDIMMGCR1_RESERVED_19_MASK 
+#undef DDR_PHY_RDIMMGCR1_RESERVED_19_DEFVAL
+#undef DDR_PHY_RDIMMGCR1_RESERVED_19_SHIFT
+#undef DDR_PHY_RDIMMGCR1_RESERVED_19_MASK
 #define DDR_PHY_RDIMMGCR1_RESERVED_19_DEFVAL                   0x00000C80
 #define DDR_PHY_RDIMMGCR1_RESERVED_19_SHIFT                    19
 #define DDR_PHY_RDIMMGCR1_RESERVED_19_MASK                     0x00080000U
@@ -9980,9 +9980,9 @@
 /*
 * Command word to command word programming delay
 */
-#undef DDR_PHY_RDIMMGCR1_TBCMRD_DEFVAL 
-#undef DDR_PHY_RDIMMGCR1_TBCMRD_SHIFT 
-#undef DDR_PHY_RDIMMGCR1_TBCMRD_MASK 
+#undef DDR_PHY_RDIMMGCR1_TBCMRD_DEFVAL
+#undef DDR_PHY_RDIMMGCR1_TBCMRD_SHIFT
+#undef DDR_PHY_RDIMMGCR1_TBCMRD_MASK
 #define DDR_PHY_RDIMMGCR1_TBCMRD_DEFVAL                        0x00000C80
 #define DDR_PHY_RDIMMGCR1_TBCMRD_SHIFT                         16
 #define DDR_PHY_RDIMMGCR1_TBCMRD_MASK                          0x00070000U
@@ -9990,9 +9990,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_RDIMMGCR1_RESERVED_15_14_DEFVAL 
-#undef DDR_PHY_RDIMMGCR1_RESERVED_15_14_SHIFT 
-#undef DDR_PHY_RDIMMGCR1_RESERVED_15_14_MASK 
+#undef DDR_PHY_RDIMMGCR1_RESERVED_15_14_DEFVAL
+#undef DDR_PHY_RDIMMGCR1_RESERVED_15_14_SHIFT
+#undef DDR_PHY_RDIMMGCR1_RESERVED_15_14_MASK
 #define DDR_PHY_RDIMMGCR1_RESERVED_15_14_DEFVAL                0x00000C80
 #define DDR_PHY_RDIMMGCR1_RESERVED_15_14_SHIFT                 14
 #define DDR_PHY_RDIMMGCR1_RESERVED_15_14_MASK                  0x0000C000U
@@ -10000,9 +10000,9 @@
 /*
 * Stabilization time
 */
-#undef DDR_PHY_RDIMMGCR1_TBCSTAB_DEFVAL 
-#undef DDR_PHY_RDIMMGCR1_TBCSTAB_SHIFT 
-#undef DDR_PHY_RDIMMGCR1_TBCSTAB_MASK 
+#undef DDR_PHY_RDIMMGCR1_TBCSTAB_DEFVAL
+#undef DDR_PHY_RDIMMGCR1_TBCSTAB_SHIFT
+#undef DDR_PHY_RDIMMGCR1_TBCSTAB_MASK
 #define DDR_PHY_RDIMMGCR1_TBCSTAB_DEFVAL                       0x00000C80
 #define DDR_PHY_RDIMMGCR1_TBCSTAB_SHIFT                        0
 #define DDR_PHY_RDIMMGCR1_TBCSTAB_MASK                         0x00003FFFU
@@ -10010,9 +10010,9 @@
 /*
 * DDR4/DDR3 Control Word 7
 */
-#undef DDR_PHY_RDIMMCR0_RC7_DEFVAL 
-#undef DDR_PHY_RDIMMCR0_RC7_SHIFT 
-#undef DDR_PHY_RDIMMCR0_RC7_MASK 
+#undef DDR_PHY_RDIMMCR0_RC7_DEFVAL
+#undef DDR_PHY_RDIMMCR0_RC7_SHIFT
+#undef DDR_PHY_RDIMMCR0_RC7_MASK
 #define DDR_PHY_RDIMMCR0_RC7_DEFVAL                            0x00000000
 #define DDR_PHY_RDIMMCR0_RC7_SHIFT                             28
 #define DDR_PHY_RDIMMCR0_RC7_MASK                              0xF0000000U
@@ -10020,9 +10020,9 @@
 /*
 * DDR4 Control Word 6 (Comman space Control Word) / DDR3 Reserved
 */
-#undef DDR_PHY_RDIMMCR0_RC6_DEFVAL 
-#undef DDR_PHY_RDIMMCR0_RC6_SHIFT 
-#undef DDR_PHY_RDIMMCR0_RC6_MASK 
+#undef DDR_PHY_RDIMMCR0_RC6_DEFVAL
+#undef DDR_PHY_RDIMMCR0_RC6_SHIFT
+#undef DDR_PHY_RDIMMCR0_RC6_MASK
 #define DDR_PHY_RDIMMCR0_RC6_DEFVAL                            0x00000000
 #define DDR_PHY_RDIMMCR0_RC6_SHIFT                             24
 #define DDR_PHY_RDIMMCR0_RC6_MASK                              0x0F000000U
@@ -10030,9 +10030,9 @@
 /*
 * DDR4/DDR3 Control Word 5 (CK Driver Characteristics Control Word)
 */
-#undef DDR_PHY_RDIMMCR0_RC5_DEFVAL 
-#undef DDR_PHY_RDIMMCR0_RC5_SHIFT 
-#undef DDR_PHY_RDIMMCR0_RC5_MASK 
+#undef DDR_PHY_RDIMMCR0_RC5_DEFVAL
+#undef DDR_PHY_RDIMMCR0_RC5_SHIFT
+#undef DDR_PHY_RDIMMCR0_RC5_MASK
 #define DDR_PHY_RDIMMCR0_RC5_DEFVAL                            0x00000000
 #define DDR_PHY_RDIMMCR0_RC5_SHIFT                             20
 #define DDR_PHY_RDIMMCR0_RC5_MASK                              0x00F00000U
@@ -10042,9 +10042,9 @@
     * Word) / DDR3 Control Word 4 (Control Signals Driver Characteristics Cont
     * rol Word)
 */
-#undef DDR_PHY_RDIMMCR0_RC4_DEFVAL 
-#undef DDR_PHY_RDIMMCR0_RC4_SHIFT 
-#undef DDR_PHY_RDIMMCR0_RC4_MASK 
+#undef DDR_PHY_RDIMMCR0_RC4_DEFVAL
+#undef DDR_PHY_RDIMMCR0_RC4_SHIFT
+#undef DDR_PHY_RDIMMCR0_RC4_MASK
 #define DDR_PHY_RDIMMCR0_RC4_DEFVAL                            0x00000000
 #define DDR_PHY_RDIMMCR0_RC4_SHIFT                             16
 #define DDR_PHY_RDIMMCR0_RC4_MASK                              0x000F0000U
@@ -10054,9 +10054,9 @@
     * rd) / DDR3 Control Word 3 (Command/Address Signals Driver Characteristri
     * cs Control Word)
 */
-#undef DDR_PHY_RDIMMCR0_RC3_DEFVAL 
-#undef DDR_PHY_RDIMMCR0_RC3_SHIFT 
-#undef DDR_PHY_RDIMMCR0_RC3_MASK 
+#undef DDR_PHY_RDIMMCR0_RC3_DEFVAL
+#undef DDR_PHY_RDIMMCR0_RC3_SHIFT
+#undef DDR_PHY_RDIMMCR0_RC3_MASK
 #define DDR_PHY_RDIMMCR0_RC3_DEFVAL                            0x00000000
 #define DDR_PHY_RDIMMCR0_RC3_SHIFT                             12
 #define DDR_PHY_RDIMMCR0_RC3_MASK                              0x0000F000U
@@ -10065,9 +10065,9 @@
 * DDR4 Control Word 2 (Timing and IBT Control Word) / DDR3 Control Word 2
     * (Timing Control Word)
 */
-#undef DDR_PHY_RDIMMCR0_RC2_DEFVAL 
-#undef DDR_PHY_RDIMMCR0_RC2_SHIFT 
-#undef DDR_PHY_RDIMMCR0_RC2_MASK 
+#undef DDR_PHY_RDIMMCR0_RC2_DEFVAL
+#undef DDR_PHY_RDIMMCR0_RC2_SHIFT
+#undef DDR_PHY_RDIMMCR0_RC2_MASK
 #define DDR_PHY_RDIMMCR0_RC2_DEFVAL                            0x00000000
 #define DDR_PHY_RDIMMCR0_RC2_SHIFT                             8
 #define DDR_PHY_RDIMMCR0_RC2_MASK                              0x00000F00U
@@ -10075,9 +10075,9 @@
 /*
 * DDR4/DDR3 Control Word 1 (Clock Driver Enable Control Word)
 */
-#undef DDR_PHY_RDIMMCR0_RC1_DEFVAL 
-#undef DDR_PHY_RDIMMCR0_RC1_SHIFT 
-#undef DDR_PHY_RDIMMCR0_RC1_MASK 
+#undef DDR_PHY_RDIMMCR0_RC1_DEFVAL
+#undef DDR_PHY_RDIMMCR0_RC1_SHIFT
+#undef DDR_PHY_RDIMMCR0_RC1_MASK
 #define DDR_PHY_RDIMMCR0_RC1_DEFVAL                            0x00000000
 #define DDR_PHY_RDIMMCR0_RC1_SHIFT                             4
 #define DDR_PHY_RDIMMCR0_RC1_MASK                              0x000000F0U
@@ -10085,9 +10085,9 @@
 /*
 * DDR4/DDR3 Control Word 0 (Global Features Control Word)
 */
-#undef DDR_PHY_RDIMMCR0_RC0_DEFVAL 
-#undef DDR_PHY_RDIMMCR0_RC0_SHIFT 
-#undef DDR_PHY_RDIMMCR0_RC0_MASK 
+#undef DDR_PHY_RDIMMCR0_RC0_DEFVAL
+#undef DDR_PHY_RDIMMCR0_RC0_SHIFT
+#undef DDR_PHY_RDIMMCR0_RC0_MASK
 #define DDR_PHY_RDIMMCR0_RC0_DEFVAL                            0x00000000
 #define DDR_PHY_RDIMMCR0_RC0_SHIFT                             0
 #define DDR_PHY_RDIMMCR0_RC0_MASK                              0x0000000FU
@@ -10095,9 +10095,9 @@
 /*
 * Control Word 15
 */
-#undef DDR_PHY_RDIMMCR1_RC15_DEFVAL 
-#undef DDR_PHY_RDIMMCR1_RC15_SHIFT 
-#undef DDR_PHY_RDIMMCR1_RC15_MASK 
+#undef DDR_PHY_RDIMMCR1_RC15_DEFVAL
+#undef DDR_PHY_RDIMMCR1_RC15_SHIFT
+#undef DDR_PHY_RDIMMCR1_RC15_MASK
 #define DDR_PHY_RDIMMCR1_RC15_DEFVAL                           0x00000000
 #define DDR_PHY_RDIMMCR1_RC15_SHIFT                            28
 #define DDR_PHY_RDIMMCR1_RC15_MASK                             0xF0000000U
@@ -10105,9 +10105,9 @@
 /*
 * DDR4 Control Word 14 (Parity Control Word) / DDR3 Reserved
 */
-#undef DDR_PHY_RDIMMCR1_RC14_DEFVAL 
-#undef DDR_PHY_RDIMMCR1_RC14_SHIFT 
-#undef DDR_PHY_RDIMMCR1_RC14_MASK 
+#undef DDR_PHY_RDIMMCR1_RC14_DEFVAL
+#undef DDR_PHY_RDIMMCR1_RC14_SHIFT
+#undef DDR_PHY_RDIMMCR1_RC14_MASK
 #define DDR_PHY_RDIMMCR1_RC14_DEFVAL                           0x00000000
 #define DDR_PHY_RDIMMCR1_RC14_SHIFT                            24
 #define DDR_PHY_RDIMMCR1_RC14_MASK                             0x0F000000U
@@ -10115,9 +10115,9 @@
 /*
 * DDR4 Control Word 13 (DIMM Configuration Control Word) / DDR3 Reserved
 */
-#undef DDR_PHY_RDIMMCR1_RC13_DEFVAL 
-#undef DDR_PHY_RDIMMCR1_RC13_SHIFT 
-#undef DDR_PHY_RDIMMCR1_RC13_MASK 
+#undef DDR_PHY_RDIMMCR1_RC13_DEFVAL
+#undef DDR_PHY_RDIMMCR1_RC13_SHIFT
+#undef DDR_PHY_RDIMMCR1_RC13_MASK
 #define DDR_PHY_RDIMMCR1_RC13_DEFVAL                           0x00000000
 #define DDR_PHY_RDIMMCR1_RC13_SHIFT                            20
 #define DDR_PHY_RDIMMCR1_RC13_MASK                             0x00F00000U
@@ -10125,9 +10125,9 @@
 /*
 * DDR4 Control Word 12 (Training Control Word) / DDR3 Reserved
 */
-#undef DDR_PHY_RDIMMCR1_RC12_DEFVAL 
-#undef DDR_PHY_RDIMMCR1_RC12_SHIFT 
-#undef DDR_PHY_RDIMMCR1_RC12_MASK 
+#undef DDR_PHY_RDIMMCR1_RC12_DEFVAL
+#undef DDR_PHY_RDIMMCR1_RC12_SHIFT
+#undef DDR_PHY_RDIMMCR1_RC12_MASK
 #define DDR_PHY_RDIMMCR1_RC12_DEFVAL                           0x00000000
 #define DDR_PHY_RDIMMCR1_RC12_SHIFT                            16
 #define DDR_PHY_RDIMMCR1_RC12_MASK                             0x000F0000U
@@ -10136,9 +10136,9 @@
 * DDR4 Control Word 11 (Operating Voltage VDD and VREFCA Source Control Wo
     * rd) / DDR3 Control Word 11 (Operation Voltage VDD Control Word)
 */
-#undef DDR_PHY_RDIMMCR1_RC11_DEFVAL 
-#undef DDR_PHY_RDIMMCR1_RC11_SHIFT 
-#undef DDR_PHY_RDIMMCR1_RC11_MASK 
+#undef DDR_PHY_RDIMMCR1_RC11_DEFVAL
+#undef DDR_PHY_RDIMMCR1_RC11_SHIFT
+#undef DDR_PHY_RDIMMCR1_RC11_MASK
 #define DDR_PHY_RDIMMCR1_RC11_DEFVAL                           0x00000000
 #define DDR_PHY_RDIMMCR1_RC11_SHIFT                            12
 #define DDR_PHY_RDIMMCR1_RC11_MASK                             0x0000F000U
@@ -10146,9 +10146,9 @@
 /*
 * DDR4/DDR3 Control Word 10 (RDIMM Operating Speed Control Word)
 */
-#undef DDR_PHY_RDIMMCR1_RC10_DEFVAL 
-#undef DDR_PHY_RDIMMCR1_RC10_SHIFT 
-#undef DDR_PHY_RDIMMCR1_RC10_MASK 
+#undef DDR_PHY_RDIMMCR1_RC10_DEFVAL
+#undef DDR_PHY_RDIMMCR1_RC10_SHIFT
+#undef DDR_PHY_RDIMMCR1_RC10_MASK
 #define DDR_PHY_RDIMMCR1_RC10_DEFVAL                           0x00000000
 #define DDR_PHY_RDIMMCR1_RC10_SHIFT                            8
 #define DDR_PHY_RDIMMCR1_RC10_MASK                             0x00000F00U
@@ -10156,9 +10156,9 @@
 /*
 * DDR4/DDR3 Control Word 9 (Power Saving Settings Control Word)
 */
-#undef DDR_PHY_RDIMMCR1_RC9_DEFVAL 
-#undef DDR_PHY_RDIMMCR1_RC9_SHIFT 
-#undef DDR_PHY_RDIMMCR1_RC9_MASK 
+#undef DDR_PHY_RDIMMCR1_RC9_DEFVAL
+#undef DDR_PHY_RDIMMCR1_RC9_SHIFT
+#undef DDR_PHY_RDIMMCR1_RC9_MASK
 #define DDR_PHY_RDIMMCR1_RC9_DEFVAL                            0x00000000
 #define DDR_PHY_RDIMMCR1_RC9_SHIFT                             4
 #define DDR_PHY_RDIMMCR1_RC9_MASK                              0x000000F0U
@@ -10167,9 +10167,9 @@
 * DDR4 Control Word 8 (Input/Output Configuration Control Word) / DDR3 Con
     * trol Word 8 (Additional Input Bus Termination Setting Control Word)
 */
-#undef DDR_PHY_RDIMMCR1_RC8_DEFVAL 
-#undef DDR_PHY_RDIMMCR1_RC8_SHIFT 
-#undef DDR_PHY_RDIMMCR1_RC8_MASK 
+#undef DDR_PHY_RDIMMCR1_RC8_DEFVAL
+#undef DDR_PHY_RDIMMCR1_RC8_SHIFT
+#undef DDR_PHY_RDIMMCR1_RC8_MASK
 #define DDR_PHY_RDIMMCR1_RC8_DEFVAL                            0x00000000
 #define DDR_PHY_RDIMMCR1_RC8_SHIFT                             0
 #define DDR_PHY_RDIMMCR1_RC8_MASK                              0x0000000FU
@@ -10177,9 +10177,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_MR0_RESERVED_31_8_DEFVAL 
-#undef DDR_PHY_MR0_RESERVED_31_8_SHIFT 
-#undef DDR_PHY_MR0_RESERVED_31_8_MASK 
+#undef DDR_PHY_MR0_RESERVED_31_8_DEFVAL
+#undef DDR_PHY_MR0_RESERVED_31_8_SHIFT
+#undef DDR_PHY_MR0_RESERVED_31_8_MASK
 #define DDR_PHY_MR0_RESERVED_31_8_DEFVAL                       0x00000052
 #define DDR_PHY_MR0_RESERVED_31_8_SHIFT                        8
 #define DDR_PHY_MR0_RESERVED_31_8_MASK                         0xFFFFFF00U
@@ -10187,9 +10187,9 @@
 /*
 * CA Terminating Rank
 */
-#undef DDR_PHY_MR0_CATR_DEFVAL 
-#undef DDR_PHY_MR0_CATR_SHIFT 
-#undef DDR_PHY_MR0_CATR_MASK 
+#undef DDR_PHY_MR0_CATR_DEFVAL
+#undef DDR_PHY_MR0_CATR_SHIFT
+#undef DDR_PHY_MR0_CATR_MASK
 #define DDR_PHY_MR0_CATR_DEFVAL                                0x00000052
 #define DDR_PHY_MR0_CATR_SHIFT                                 7
 #define DDR_PHY_MR0_CATR_MASK                                  0x00000080U
@@ -10198,9 +10198,9 @@
 * Reserved. These are JEDEC reserved bits and are recommended by JEDEC to
     * be programmed to 0x0.
 */
-#undef DDR_PHY_MR0_RSVD_6_5_DEFVAL 
-#undef DDR_PHY_MR0_RSVD_6_5_SHIFT 
-#undef DDR_PHY_MR0_RSVD_6_5_MASK 
+#undef DDR_PHY_MR0_RSVD_6_5_DEFVAL
+#undef DDR_PHY_MR0_RSVD_6_5_SHIFT
+#undef DDR_PHY_MR0_RSVD_6_5_MASK
 #define DDR_PHY_MR0_RSVD_6_5_DEFVAL                            0x00000052
 #define DDR_PHY_MR0_RSVD_6_5_SHIFT                             5
 #define DDR_PHY_MR0_RSVD_6_5_MASK                              0x00000060U
@@ -10208,9 +10208,9 @@
 /*
 * Built-in Self-Test for RZQ
 */
-#undef DDR_PHY_MR0_RZQI_DEFVAL 
-#undef DDR_PHY_MR0_RZQI_SHIFT 
-#undef DDR_PHY_MR0_RZQI_MASK 
+#undef DDR_PHY_MR0_RZQI_DEFVAL
+#undef DDR_PHY_MR0_RZQI_SHIFT
+#undef DDR_PHY_MR0_RZQI_MASK
 #define DDR_PHY_MR0_RZQI_DEFVAL                                0x00000052
 #define DDR_PHY_MR0_RZQI_SHIFT                                 3
 #define DDR_PHY_MR0_RZQI_MASK                                  0x00000018U
@@ -10219,9 +10219,9 @@
 * Reserved. These are JEDEC reserved bits and are recommended by JEDEC to
     * be programmed to 0x0.
 */
-#undef DDR_PHY_MR0_RSVD_2_0_DEFVAL 
-#undef DDR_PHY_MR0_RSVD_2_0_SHIFT 
-#undef DDR_PHY_MR0_RSVD_2_0_MASK 
+#undef DDR_PHY_MR0_RSVD_2_0_DEFVAL
+#undef DDR_PHY_MR0_RSVD_2_0_SHIFT
+#undef DDR_PHY_MR0_RSVD_2_0_MASK
 #define DDR_PHY_MR0_RSVD_2_0_DEFVAL                            0x00000052
 #define DDR_PHY_MR0_RSVD_2_0_SHIFT                             0
 #define DDR_PHY_MR0_RSVD_2_0_MASK                              0x00000007U
@@ -10229,9 +10229,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_MR1_RESERVED_31_8_DEFVAL 
-#undef DDR_PHY_MR1_RESERVED_31_8_SHIFT 
-#undef DDR_PHY_MR1_RESERVED_31_8_MASK 
+#undef DDR_PHY_MR1_RESERVED_31_8_DEFVAL
+#undef DDR_PHY_MR1_RESERVED_31_8_SHIFT
+#undef DDR_PHY_MR1_RESERVED_31_8_MASK
 #define DDR_PHY_MR1_RESERVED_31_8_DEFVAL                       0x00000004
 #define DDR_PHY_MR1_RESERVED_31_8_SHIFT                        8
 #define DDR_PHY_MR1_RESERVED_31_8_MASK                         0xFFFFFF00U
@@ -10239,9 +10239,9 @@
 /*
 * Read Postamble Length
 */
-#undef DDR_PHY_MR1_RDPST_DEFVAL 
-#undef DDR_PHY_MR1_RDPST_SHIFT 
-#undef DDR_PHY_MR1_RDPST_MASK 
+#undef DDR_PHY_MR1_RDPST_DEFVAL
+#undef DDR_PHY_MR1_RDPST_SHIFT
+#undef DDR_PHY_MR1_RDPST_MASK
 #define DDR_PHY_MR1_RDPST_DEFVAL                               0x00000004
 #define DDR_PHY_MR1_RDPST_SHIFT                                7
 #define DDR_PHY_MR1_RDPST_MASK                                 0x00000080U
@@ -10249,9 +10249,9 @@
 /*
 * Write-recovery for auto-precharge command
 */
-#undef DDR_PHY_MR1_NWR_DEFVAL 
-#undef DDR_PHY_MR1_NWR_SHIFT 
-#undef DDR_PHY_MR1_NWR_MASK 
+#undef DDR_PHY_MR1_NWR_DEFVAL
+#undef DDR_PHY_MR1_NWR_SHIFT
+#undef DDR_PHY_MR1_NWR_MASK
 #define DDR_PHY_MR1_NWR_DEFVAL                                 0x00000004
 #define DDR_PHY_MR1_NWR_SHIFT                                  4
 #define DDR_PHY_MR1_NWR_MASK                                   0x00000070U
@@ -10259,9 +10259,9 @@
 /*
 * Read Preamble Length
 */
-#undef DDR_PHY_MR1_RDPRE_DEFVAL 
-#undef DDR_PHY_MR1_RDPRE_SHIFT 
-#undef DDR_PHY_MR1_RDPRE_MASK 
+#undef DDR_PHY_MR1_RDPRE_DEFVAL
+#undef DDR_PHY_MR1_RDPRE_SHIFT
+#undef DDR_PHY_MR1_RDPRE_MASK
 #define DDR_PHY_MR1_RDPRE_DEFVAL                               0x00000004
 #define DDR_PHY_MR1_RDPRE_SHIFT                                3
 #define DDR_PHY_MR1_RDPRE_MASK                                 0x00000008U
@@ -10269,9 +10269,9 @@
 /*
 * Write Preamble Length
 */
-#undef DDR_PHY_MR1_WRPRE_DEFVAL 
-#undef DDR_PHY_MR1_WRPRE_SHIFT 
-#undef DDR_PHY_MR1_WRPRE_MASK 
+#undef DDR_PHY_MR1_WRPRE_DEFVAL
+#undef DDR_PHY_MR1_WRPRE_SHIFT
+#undef DDR_PHY_MR1_WRPRE_MASK
 #define DDR_PHY_MR1_WRPRE_DEFVAL                               0x00000004
 #define DDR_PHY_MR1_WRPRE_SHIFT                                2
 #define DDR_PHY_MR1_WRPRE_MASK                                 0x00000004U
@@ -10279,9 +10279,9 @@
 /*
 * Burst Length
 */
-#undef DDR_PHY_MR1_BL_DEFVAL 
-#undef DDR_PHY_MR1_BL_SHIFT 
-#undef DDR_PHY_MR1_BL_MASK 
+#undef DDR_PHY_MR1_BL_DEFVAL
+#undef DDR_PHY_MR1_BL_SHIFT
+#undef DDR_PHY_MR1_BL_MASK
 #define DDR_PHY_MR1_BL_DEFVAL                                  0x00000004
 #define DDR_PHY_MR1_BL_SHIFT                                   0
 #define DDR_PHY_MR1_BL_MASK                                    0x00000003U
@@ -10289,9 +10289,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_MR2_RESERVED_31_8_DEFVAL 
-#undef DDR_PHY_MR2_RESERVED_31_8_SHIFT 
-#undef DDR_PHY_MR2_RESERVED_31_8_MASK 
+#undef DDR_PHY_MR2_RESERVED_31_8_DEFVAL
+#undef DDR_PHY_MR2_RESERVED_31_8_SHIFT
+#undef DDR_PHY_MR2_RESERVED_31_8_MASK
 #define DDR_PHY_MR2_RESERVED_31_8_DEFVAL                       0x00000000
 #define DDR_PHY_MR2_RESERVED_31_8_SHIFT                        8
 #define DDR_PHY_MR2_RESERVED_31_8_MASK                         0xFFFFFF00U
@@ -10299,9 +10299,9 @@
 /*
 * Write Leveling
 */
-#undef DDR_PHY_MR2_WRL_DEFVAL 
-#undef DDR_PHY_MR2_WRL_SHIFT 
-#undef DDR_PHY_MR2_WRL_MASK 
+#undef DDR_PHY_MR2_WRL_DEFVAL
+#undef DDR_PHY_MR2_WRL_SHIFT
+#undef DDR_PHY_MR2_WRL_MASK
 #define DDR_PHY_MR2_WRL_DEFVAL                                 0x00000000
 #define DDR_PHY_MR2_WRL_SHIFT                                  7
 #define DDR_PHY_MR2_WRL_MASK                                   0x00000080U
@@ -10309,9 +10309,9 @@
 /*
 * Write Latency Set
 */
-#undef DDR_PHY_MR2_WLS_DEFVAL 
-#undef DDR_PHY_MR2_WLS_SHIFT 
-#undef DDR_PHY_MR2_WLS_MASK 
+#undef DDR_PHY_MR2_WLS_DEFVAL
+#undef DDR_PHY_MR2_WLS_SHIFT
+#undef DDR_PHY_MR2_WLS_MASK
 #define DDR_PHY_MR2_WLS_DEFVAL                                 0x00000000
 #define DDR_PHY_MR2_WLS_SHIFT                                  6
 #define DDR_PHY_MR2_WLS_MASK                                   0x00000040U
@@ -10319,9 +10319,9 @@
 /*
 * Write Latency
 */
-#undef DDR_PHY_MR2_WL_DEFVAL 
-#undef DDR_PHY_MR2_WL_SHIFT 
-#undef DDR_PHY_MR2_WL_MASK 
+#undef DDR_PHY_MR2_WL_DEFVAL
+#undef DDR_PHY_MR2_WL_SHIFT
+#undef DDR_PHY_MR2_WL_MASK
 #define DDR_PHY_MR2_WL_DEFVAL                                  0x00000000
 #define DDR_PHY_MR2_WL_SHIFT                                   3
 #define DDR_PHY_MR2_WL_MASK                                    0x00000038U
@@ -10329,9 +10329,9 @@
 /*
 * Read Latency
 */
-#undef DDR_PHY_MR2_RL_DEFVAL 
-#undef DDR_PHY_MR2_RL_SHIFT 
-#undef DDR_PHY_MR2_RL_MASK 
+#undef DDR_PHY_MR2_RL_DEFVAL
+#undef DDR_PHY_MR2_RL_SHIFT
+#undef DDR_PHY_MR2_RL_MASK
 #define DDR_PHY_MR2_RL_DEFVAL                                  0x00000000
 #define DDR_PHY_MR2_RL_SHIFT                                   0
 #define DDR_PHY_MR2_RL_MASK                                    0x00000007U
@@ -10339,9 +10339,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_MR3_RESERVED_31_8_DEFVAL 
-#undef DDR_PHY_MR3_RESERVED_31_8_SHIFT 
-#undef DDR_PHY_MR3_RESERVED_31_8_MASK 
+#undef DDR_PHY_MR3_RESERVED_31_8_DEFVAL
+#undef DDR_PHY_MR3_RESERVED_31_8_SHIFT
+#undef DDR_PHY_MR3_RESERVED_31_8_MASK
 #define DDR_PHY_MR3_RESERVED_31_8_DEFVAL                       0x00000031
 #define DDR_PHY_MR3_RESERVED_31_8_SHIFT                        8
 #define DDR_PHY_MR3_RESERVED_31_8_MASK                         0xFFFFFF00U
@@ -10349,9 +10349,9 @@
 /*
 * DBI-Write Enable
 */
-#undef DDR_PHY_MR3_DBIWR_DEFVAL 
-#undef DDR_PHY_MR3_DBIWR_SHIFT 
-#undef DDR_PHY_MR3_DBIWR_MASK 
+#undef DDR_PHY_MR3_DBIWR_DEFVAL
+#undef DDR_PHY_MR3_DBIWR_SHIFT
+#undef DDR_PHY_MR3_DBIWR_MASK
 #define DDR_PHY_MR3_DBIWR_DEFVAL                               0x00000031
 #define DDR_PHY_MR3_DBIWR_SHIFT                                7
 #define DDR_PHY_MR3_DBIWR_MASK                                 0x00000080U
@@ -10359,9 +10359,9 @@
 /*
 * DBI-Read Enable
 */
-#undef DDR_PHY_MR3_DBIRD_DEFVAL 
-#undef DDR_PHY_MR3_DBIRD_SHIFT 
-#undef DDR_PHY_MR3_DBIRD_MASK 
+#undef DDR_PHY_MR3_DBIRD_DEFVAL
+#undef DDR_PHY_MR3_DBIRD_SHIFT
+#undef DDR_PHY_MR3_DBIRD_MASK
 #define DDR_PHY_MR3_DBIRD_DEFVAL                               0x00000031
 #define DDR_PHY_MR3_DBIRD_SHIFT                                6
 #define DDR_PHY_MR3_DBIRD_MASK                                 0x00000040U
@@ -10369,9 +10369,9 @@
 /*
 * Pull-down Drive Strength
 */
-#undef DDR_PHY_MR3_PDDS_DEFVAL 
-#undef DDR_PHY_MR3_PDDS_SHIFT 
-#undef DDR_PHY_MR3_PDDS_MASK 
+#undef DDR_PHY_MR3_PDDS_DEFVAL
+#undef DDR_PHY_MR3_PDDS_SHIFT
+#undef DDR_PHY_MR3_PDDS_MASK
 #define DDR_PHY_MR3_PDDS_DEFVAL                                0x00000031
 #define DDR_PHY_MR3_PDDS_SHIFT                                 3
 #define DDR_PHY_MR3_PDDS_MASK                                  0x00000038U
@@ -10380,9 +10380,9 @@
 * These are JEDEC reserved bits and are recommended by JEDEC to be program
     * med to 0x0.
 */
-#undef DDR_PHY_MR3_RSVD_DEFVAL 
-#undef DDR_PHY_MR3_RSVD_SHIFT 
-#undef DDR_PHY_MR3_RSVD_MASK 
+#undef DDR_PHY_MR3_RSVD_DEFVAL
+#undef DDR_PHY_MR3_RSVD_SHIFT
+#undef DDR_PHY_MR3_RSVD_MASK
 #define DDR_PHY_MR3_RSVD_DEFVAL                                0x00000031
 #define DDR_PHY_MR3_RSVD_SHIFT                                 2
 #define DDR_PHY_MR3_RSVD_MASK                                  0x00000004U
@@ -10390,9 +10390,9 @@
 /*
 * Write Postamble Length
 */
-#undef DDR_PHY_MR3_WRPST_DEFVAL 
-#undef DDR_PHY_MR3_WRPST_SHIFT 
-#undef DDR_PHY_MR3_WRPST_MASK 
+#undef DDR_PHY_MR3_WRPST_DEFVAL
+#undef DDR_PHY_MR3_WRPST_SHIFT
+#undef DDR_PHY_MR3_WRPST_MASK
 #define DDR_PHY_MR3_WRPST_DEFVAL                               0x00000031
 #define DDR_PHY_MR3_WRPST_SHIFT                                1
 #define DDR_PHY_MR3_WRPST_MASK                                 0x00000002U
@@ -10400,9 +10400,9 @@
 /*
 * Pull-up Calibration Point
 */
-#undef DDR_PHY_MR3_PUCAL_DEFVAL 
-#undef DDR_PHY_MR3_PUCAL_SHIFT 
-#undef DDR_PHY_MR3_PUCAL_MASK 
+#undef DDR_PHY_MR3_PUCAL_DEFVAL
+#undef DDR_PHY_MR3_PUCAL_SHIFT
+#undef DDR_PHY_MR3_PUCAL_MASK
 #define DDR_PHY_MR3_PUCAL_DEFVAL                               0x00000031
 #define DDR_PHY_MR3_PUCAL_SHIFT                                0
 #define DDR_PHY_MR3_PUCAL_MASK                                 0x00000001U
@@ -10410,9 +10410,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_MR4_RESERVED_31_16_DEFVAL 
-#undef DDR_PHY_MR4_RESERVED_31_16_SHIFT 
-#undef DDR_PHY_MR4_RESERVED_31_16_MASK 
+#undef DDR_PHY_MR4_RESERVED_31_16_DEFVAL
+#undef DDR_PHY_MR4_RESERVED_31_16_SHIFT
+#undef DDR_PHY_MR4_RESERVED_31_16_MASK
 #define DDR_PHY_MR4_RESERVED_31_16_DEFVAL                      0x00000000
 #define DDR_PHY_MR4_RESERVED_31_16_SHIFT                       16
 #define DDR_PHY_MR4_RESERVED_31_16_MASK                        0xFFFF0000U
@@ -10421,9 +10421,9 @@
 * These are JEDEC reserved bits and are recommended by JEDEC to be program
     * med to 0x0.
 */
-#undef DDR_PHY_MR4_RSVD_15_13_DEFVAL 
-#undef DDR_PHY_MR4_RSVD_15_13_SHIFT 
-#undef DDR_PHY_MR4_RSVD_15_13_MASK 
+#undef DDR_PHY_MR4_RSVD_15_13_DEFVAL
+#undef DDR_PHY_MR4_RSVD_15_13_SHIFT
+#undef DDR_PHY_MR4_RSVD_15_13_MASK
 #define DDR_PHY_MR4_RSVD_15_13_DEFVAL                          0x00000000
 #define DDR_PHY_MR4_RSVD_15_13_SHIFT                           13
 #define DDR_PHY_MR4_RSVD_15_13_MASK                            0x0000E000U
@@ -10431,9 +10431,9 @@
 /*
 * Write Preamble
 */
-#undef DDR_PHY_MR4_WRP_DEFVAL 
-#undef DDR_PHY_MR4_WRP_SHIFT 
-#undef DDR_PHY_MR4_WRP_MASK 
+#undef DDR_PHY_MR4_WRP_DEFVAL
+#undef DDR_PHY_MR4_WRP_SHIFT
+#undef DDR_PHY_MR4_WRP_MASK
 #define DDR_PHY_MR4_WRP_DEFVAL                                 0x00000000
 #define DDR_PHY_MR4_WRP_SHIFT                                  12
 #define DDR_PHY_MR4_WRP_MASK                                   0x00001000U
@@ -10441,9 +10441,9 @@
 /*
 * Read Preamble
 */
-#undef DDR_PHY_MR4_RDP_DEFVAL 
-#undef DDR_PHY_MR4_RDP_SHIFT 
-#undef DDR_PHY_MR4_RDP_MASK 
+#undef DDR_PHY_MR4_RDP_DEFVAL
+#undef DDR_PHY_MR4_RDP_SHIFT
+#undef DDR_PHY_MR4_RDP_MASK
 #define DDR_PHY_MR4_RDP_DEFVAL                                 0x00000000
 #define DDR_PHY_MR4_RDP_SHIFT                                  11
 #define DDR_PHY_MR4_RDP_MASK                                   0x00000800U
@@ -10451,9 +10451,9 @@
 /*
 * Read Preamble Training Mode
 */
-#undef DDR_PHY_MR4_RPTM_DEFVAL 
-#undef DDR_PHY_MR4_RPTM_SHIFT 
-#undef DDR_PHY_MR4_RPTM_MASK 
+#undef DDR_PHY_MR4_RPTM_DEFVAL
+#undef DDR_PHY_MR4_RPTM_SHIFT
+#undef DDR_PHY_MR4_RPTM_MASK
 #define DDR_PHY_MR4_RPTM_DEFVAL                                0x00000000
 #define DDR_PHY_MR4_RPTM_SHIFT                                 10
 #define DDR_PHY_MR4_RPTM_MASK                                  0x00000400U
@@ -10461,9 +10461,9 @@
 /*
 * Self Refresh Abort
 */
-#undef DDR_PHY_MR4_SRA_DEFVAL 
-#undef DDR_PHY_MR4_SRA_SHIFT 
-#undef DDR_PHY_MR4_SRA_MASK 
+#undef DDR_PHY_MR4_SRA_DEFVAL
+#undef DDR_PHY_MR4_SRA_SHIFT
+#undef DDR_PHY_MR4_SRA_MASK
 #define DDR_PHY_MR4_SRA_DEFVAL                                 0x00000000
 #define DDR_PHY_MR4_SRA_SHIFT                                  9
 #define DDR_PHY_MR4_SRA_MASK                                   0x00000200U
@@ -10471,9 +10471,9 @@
 /*
 * CS to Command Latency Mode
 */
-#undef DDR_PHY_MR4_CS2CMDL_DEFVAL 
-#undef DDR_PHY_MR4_CS2CMDL_SHIFT 
-#undef DDR_PHY_MR4_CS2CMDL_MASK 
+#undef DDR_PHY_MR4_CS2CMDL_DEFVAL
+#undef DDR_PHY_MR4_CS2CMDL_SHIFT
+#undef DDR_PHY_MR4_CS2CMDL_MASK
 #define DDR_PHY_MR4_CS2CMDL_DEFVAL                             0x00000000
 #define DDR_PHY_MR4_CS2CMDL_SHIFT                              6
 #define DDR_PHY_MR4_CS2CMDL_MASK                               0x000001C0U
@@ -10482,9 +10482,9 @@
 * These are JEDEC reserved bits and are recommended by JEDEC to be program
     * med to 0x0.
 */
-#undef DDR_PHY_MR4_RSVD1_DEFVAL 
-#undef DDR_PHY_MR4_RSVD1_SHIFT 
-#undef DDR_PHY_MR4_RSVD1_MASK 
+#undef DDR_PHY_MR4_RSVD1_DEFVAL
+#undef DDR_PHY_MR4_RSVD1_SHIFT
+#undef DDR_PHY_MR4_RSVD1_MASK
 #define DDR_PHY_MR4_RSVD1_DEFVAL                               0x00000000
 #define DDR_PHY_MR4_RSVD1_SHIFT                                5
 #define DDR_PHY_MR4_RSVD1_MASK                                 0x00000020U
@@ -10492,9 +10492,9 @@
 /*
 * Internal VREF Monitor
 */
-#undef DDR_PHY_MR4_IVM_DEFVAL 
-#undef DDR_PHY_MR4_IVM_SHIFT 
-#undef DDR_PHY_MR4_IVM_MASK 
+#undef DDR_PHY_MR4_IVM_DEFVAL
+#undef DDR_PHY_MR4_IVM_SHIFT
+#undef DDR_PHY_MR4_IVM_MASK
 #define DDR_PHY_MR4_IVM_DEFVAL                                 0x00000000
 #define DDR_PHY_MR4_IVM_SHIFT                                  4
 #define DDR_PHY_MR4_IVM_MASK                                   0x00000010U
@@ -10502,9 +10502,9 @@
 /*
 * Temperature Controlled Refresh Mode
 */
-#undef DDR_PHY_MR4_TCRM_DEFVAL 
-#undef DDR_PHY_MR4_TCRM_SHIFT 
-#undef DDR_PHY_MR4_TCRM_MASK 
+#undef DDR_PHY_MR4_TCRM_DEFVAL
+#undef DDR_PHY_MR4_TCRM_SHIFT
+#undef DDR_PHY_MR4_TCRM_MASK
 #define DDR_PHY_MR4_TCRM_DEFVAL                                0x00000000
 #define DDR_PHY_MR4_TCRM_SHIFT                                 3
 #define DDR_PHY_MR4_TCRM_MASK                                  0x00000008U
@@ -10512,9 +10512,9 @@
 /*
 * Temperature Controlled Refresh Range
 */
-#undef DDR_PHY_MR4_TCRR_DEFVAL 
-#undef DDR_PHY_MR4_TCRR_SHIFT 
-#undef DDR_PHY_MR4_TCRR_MASK 
+#undef DDR_PHY_MR4_TCRR_DEFVAL
+#undef DDR_PHY_MR4_TCRR_SHIFT
+#undef DDR_PHY_MR4_TCRR_MASK
 #define DDR_PHY_MR4_TCRR_DEFVAL                                0x00000000
 #define DDR_PHY_MR4_TCRR_SHIFT                                 2
 #define DDR_PHY_MR4_TCRR_MASK                                  0x00000004U
@@ -10522,9 +10522,9 @@
 /*
 * Maximum Power Down Mode
 */
-#undef DDR_PHY_MR4_MPDM_DEFVAL 
-#undef DDR_PHY_MR4_MPDM_SHIFT 
-#undef DDR_PHY_MR4_MPDM_MASK 
+#undef DDR_PHY_MR4_MPDM_DEFVAL
+#undef DDR_PHY_MR4_MPDM_SHIFT
+#undef DDR_PHY_MR4_MPDM_MASK
 #define DDR_PHY_MR4_MPDM_DEFVAL                                0x00000000
 #define DDR_PHY_MR4_MPDM_SHIFT                                 1
 #define DDR_PHY_MR4_MPDM_MASK                                  0x00000002U
@@ -10533,9 +10533,9 @@
 * This is a JEDEC reserved bit and is recommended by JEDEC to be programme
     * d to 0x0.
 */
-#undef DDR_PHY_MR4_RSVD_0_DEFVAL 
-#undef DDR_PHY_MR4_RSVD_0_SHIFT 
-#undef DDR_PHY_MR4_RSVD_0_MASK 
+#undef DDR_PHY_MR4_RSVD_0_DEFVAL
+#undef DDR_PHY_MR4_RSVD_0_SHIFT
+#undef DDR_PHY_MR4_RSVD_0_MASK
 #define DDR_PHY_MR4_RSVD_0_DEFVAL                              0x00000000
 #define DDR_PHY_MR4_RSVD_0_SHIFT                               0
 #define DDR_PHY_MR4_RSVD_0_MASK                                0x00000001U
@@ -10543,9 +10543,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_MR5_RESERVED_31_16_DEFVAL 
-#undef DDR_PHY_MR5_RESERVED_31_16_SHIFT 
-#undef DDR_PHY_MR5_RESERVED_31_16_MASK 
+#undef DDR_PHY_MR5_RESERVED_31_16_DEFVAL
+#undef DDR_PHY_MR5_RESERVED_31_16_SHIFT
+#undef DDR_PHY_MR5_RESERVED_31_16_MASK
 #define DDR_PHY_MR5_RESERVED_31_16_DEFVAL                      0x00000000
 #define DDR_PHY_MR5_RESERVED_31_16_SHIFT                       16
 #define DDR_PHY_MR5_RESERVED_31_16_MASK                        0xFFFF0000U
@@ -10554,9 +10554,9 @@
 * These are JEDEC reserved bits and are recommended by JEDEC to be program
     * med to 0x0.
 */
-#undef DDR_PHY_MR5_RSVD_DEFVAL 
-#undef DDR_PHY_MR5_RSVD_SHIFT 
-#undef DDR_PHY_MR5_RSVD_MASK 
+#undef DDR_PHY_MR5_RSVD_DEFVAL
+#undef DDR_PHY_MR5_RSVD_SHIFT
+#undef DDR_PHY_MR5_RSVD_MASK
 #define DDR_PHY_MR5_RSVD_DEFVAL                                0x00000000
 #define DDR_PHY_MR5_RSVD_SHIFT                                 13
 #define DDR_PHY_MR5_RSVD_MASK                                  0x0000E000U
@@ -10564,9 +10564,9 @@
 /*
 * Read DBI
 */
-#undef DDR_PHY_MR5_RDBI_DEFVAL 
-#undef DDR_PHY_MR5_RDBI_SHIFT 
-#undef DDR_PHY_MR5_RDBI_MASK 
+#undef DDR_PHY_MR5_RDBI_DEFVAL
+#undef DDR_PHY_MR5_RDBI_SHIFT
+#undef DDR_PHY_MR5_RDBI_MASK
 #define DDR_PHY_MR5_RDBI_DEFVAL                                0x00000000
 #define DDR_PHY_MR5_RDBI_SHIFT                                 12
 #define DDR_PHY_MR5_RDBI_MASK                                  0x00001000U
@@ -10574,9 +10574,9 @@
 /*
 * Write DBI
 */
-#undef DDR_PHY_MR5_WDBI_DEFVAL 
-#undef DDR_PHY_MR5_WDBI_SHIFT 
-#undef DDR_PHY_MR5_WDBI_MASK 
+#undef DDR_PHY_MR5_WDBI_DEFVAL
+#undef DDR_PHY_MR5_WDBI_SHIFT
+#undef DDR_PHY_MR5_WDBI_MASK
 #define DDR_PHY_MR5_WDBI_DEFVAL                                0x00000000
 #define DDR_PHY_MR5_WDBI_SHIFT                                 11
 #define DDR_PHY_MR5_WDBI_MASK                                  0x00000800U
@@ -10584,9 +10584,9 @@
 /*
 * Data Mask
 */
-#undef DDR_PHY_MR5_DM_DEFVAL 
-#undef DDR_PHY_MR5_DM_SHIFT 
-#undef DDR_PHY_MR5_DM_MASK 
+#undef DDR_PHY_MR5_DM_DEFVAL
+#undef DDR_PHY_MR5_DM_SHIFT
+#undef DDR_PHY_MR5_DM_MASK
 #define DDR_PHY_MR5_DM_DEFVAL                                  0x00000000
 #define DDR_PHY_MR5_DM_SHIFT                                   10
 #define DDR_PHY_MR5_DM_MASK                                    0x00000400U
@@ -10594,9 +10594,9 @@
 /*
 * CA Parity Persistent Error
 */
-#undef DDR_PHY_MR5_CAPPE_DEFVAL 
-#undef DDR_PHY_MR5_CAPPE_SHIFT 
-#undef DDR_PHY_MR5_CAPPE_MASK 
+#undef DDR_PHY_MR5_CAPPE_DEFVAL
+#undef DDR_PHY_MR5_CAPPE_SHIFT
+#undef DDR_PHY_MR5_CAPPE_MASK
 #define DDR_PHY_MR5_CAPPE_DEFVAL                               0x00000000
 #define DDR_PHY_MR5_CAPPE_SHIFT                                9
 #define DDR_PHY_MR5_CAPPE_MASK                                 0x00000200U
@@ -10604,9 +10604,9 @@
 /*
 * RTT_PARK
 */
-#undef DDR_PHY_MR5_RTTPARK_DEFVAL 
-#undef DDR_PHY_MR5_RTTPARK_SHIFT 
-#undef DDR_PHY_MR5_RTTPARK_MASK 
+#undef DDR_PHY_MR5_RTTPARK_DEFVAL
+#undef DDR_PHY_MR5_RTTPARK_SHIFT
+#undef DDR_PHY_MR5_RTTPARK_MASK
 #define DDR_PHY_MR5_RTTPARK_DEFVAL                             0x00000000
 #define DDR_PHY_MR5_RTTPARK_SHIFT                              6
 #define DDR_PHY_MR5_RTTPARK_MASK                               0x000001C0U
@@ -10614,9 +10614,9 @@
 /*
 * ODT Input Buffer during Power Down mode
 */
-#undef DDR_PHY_MR5_ODTIBPD_DEFVAL 
-#undef DDR_PHY_MR5_ODTIBPD_SHIFT 
-#undef DDR_PHY_MR5_ODTIBPD_MASK 
+#undef DDR_PHY_MR5_ODTIBPD_DEFVAL
+#undef DDR_PHY_MR5_ODTIBPD_SHIFT
+#undef DDR_PHY_MR5_ODTIBPD_MASK
 #define DDR_PHY_MR5_ODTIBPD_DEFVAL                             0x00000000
 #define DDR_PHY_MR5_ODTIBPD_SHIFT                              5
 #define DDR_PHY_MR5_ODTIBPD_MASK                               0x00000020U
@@ -10624,9 +10624,9 @@
 /*
 * C/A Parity Error Status
 */
-#undef DDR_PHY_MR5_CAPES_DEFVAL 
-#undef DDR_PHY_MR5_CAPES_SHIFT 
-#undef DDR_PHY_MR5_CAPES_MASK 
+#undef DDR_PHY_MR5_CAPES_DEFVAL
+#undef DDR_PHY_MR5_CAPES_SHIFT
+#undef DDR_PHY_MR5_CAPES_MASK
 #define DDR_PHY_MR5_CAPES_DEFVAL                               0x00000000
 #define DDR_PHY_MR5_CAPES_SHIFT                                4
 #define DDR_PHY_MR5_CAPES_MASK                                 0x00000010U
@@ -10634,9 +10634,9 @@
 /*
 * CRC Error Clear
 */
-#undef DDR_PHY_MR5_CRCEC_DEFVAL 
-#undef DDR_PHY_MR5_CRCEC_SHIFT 
-#undef DDR_PHY_MR5_CRCEC_MASK 
+#undef DDR_PHY_MR5_CRCEC_DEFVAL
+#undef DDR_PHY_MR5_CRCEC_SHIFT
+#undef DDR_PHY_MR5_CRCEC_MASK
 #define DDR_PHY_MR5_CRCEC_DEFVAL                               0x00000000
 #define DDR_PHY_MR5_CRCEC_SHIFT                                3
 #define DDR_PHY_MR5_CRCEC_MASK                                 0x00000008U
@@ -10644,9 +10644,9 @@
 /*
 * C/A Parity Latency Mode
 */
-#undef DDR_PHY_MR5_CAPM_DEFVAL 
-#undef DDR_PHY_MR5_CAPM_SHIFT 
-#undef DDR_PHY_MR5_CAPM_MASK 
+#undef DDR_PHY_MR5_CAPM_DEFVAL
+#undef DDR_PHY_MR5_CAPM_SHIFT
+#undef DDR_PHY_MR5_CAPM_MASK
 #define DDR_PHY_MR5_CAPM_DEFVAL                                0x00000000
 #define DDR_PHY_MR5_CAPM_SHIFT                                 0
 #define DDR_PHY_MR5_CAPM_MASK                                  0x00000007U
@@ -10654,9 +10654,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_MR6_RESERVED_31_16_DEFVAL 
-#undef DDR_PHY_MR6_RESERVED_31_16_SHIFT 
-#undef DDR_PHY_MR6_RESERVED_31_16_MASK 
+#undef DDR_PHY_MR6_RESERVED_31_16_DEFVAL
+#undef DDR_PHY_MR6_RESERVED_31_16_SHIFT
+#undef DDR_PHY_MR6_RESERVED_31_16_MASK
 #define DDR_PHY_MR6_RESERVED_31_16_DEFVAL                      0x00000000
 #define DDR_PHY_MR6_RESERVED_31_16_SHIFT                       16
 #define DDR_PHY_MR6_RESERVED_31_16_MASK                        0xFFFF0000U
@@ -10665,9 +10665,9 @@
 * These are JEDEC reserved bits and are recommended by JEDEC to be program
     * med to 0x0.
 */
-#undef DDR_PHY_MR6_RSVD_15_13_DEFVAL 
-#undef DDR_PHY_MR6_RSVD_15_13_SHIFT 
-#undef DDR_PHY_MR6_RSVD_15_13_MASK 
+#undef DDR_PHY_MR6_RSVD_15_13_DEFVAL
+#undef DDR_PHY_MR6_RSVD_15_13_SHIFT
+#undef DDR_PHY_MR6_RSVD_15_13_MASK
 #define DDR_PHY_MR6_RSVD_15_13_DEFVAL                          0x00000000
 #define DDR_PHY_MR6_RSVD_15_13_SHIFT                           13
 #define DDR_PHY_MR6_RSVD_15_13_MASK                            0x0000E000U
@@ -10675,9 +10675,9 @@
 /*
 * CAS_n to CAS_n command delay for same bank group (tCCD_L)
 */
-#undef DDR_PHY_MR6_TCCDL_DEFVAL 
-#undef DDR_PHY_MR6_TCCDL_SHIFT 
-#undef DDR_PHY_MR6_TCCDL_MASK 
+#undef DDR_PHY_MR6_TCCDL_DEFVAL
+#undef DDR_PHY_MR6_TCCDL_SHIFT
+#undef DDR_PHY_MR6_TCCDL_MASK
 #define DDR_PHY_MR6_TCCDL_DEFVAL                               0x00000000
 #define DDR_PHY_MR6_TCCDL_SHIFT                                10
 #define DDR_PHY_MR6_TCCDL_MASK                                 0x00001C00U
@@ -10686,9 +10686,9 @@
 * These are JEDEC reserved bits and are recommended by JEDEC to be program
     * med to 0x0.
 */
-#undef DDR_PHY_MR6_RSVD_9_8_DEFVAL 
-#undef DDR_PHY_MR6_RSVD_9_8_SHIFT 
-#undef DDR_PHY_MR6_RSVD_9_8_MASK 
+#undef DDR_PHY_MR6_RSVD_9_8_DEFVAL
+#undef DDR_PHY_MR6_RSVD_9_8_SHIFT
+#undef DDR_PHY_MR6_RSVD_9_8_MASK
 #define DDR_PHY_MR6_RSVD_9_8_DEFVAL                            0x00000000
 #define DDR_PHY_MR6_RSVD_9_8_SHIFT                             8
 #define DDR_PHY_MR6_RSVD_9_8_MASK                              0x00000300U
@@ -10696,9 +10696,9 @@
 /*
 * VrefDQ Training Enable
 */
-#undef DDR_PHY_MR6_VDDQTEN_DEFVAL 
-#undef DDR_PHY_MR6_VDDQTEN_SHIFT 
-#undef DDR_PHY_MR6_VDDQTEN_MASK 
+#undef DDR_PHY_MR6_VDDQTEN_DEFVAL
+#undef DDR_PHY_MR6_VDDQTEN_SHIFT
+#undef DDR_PHY_MR6_VDDQTEN_MASK
 #define DDR_PHY_MR6_VDDQTEN_DEFVAL                             0x00000000
 #define DDR_PHY_MR6_VDDQTEN_SHIFT                              7
 #define DDR_PHY_MR6_VDDQTEN_MASK                               0x00000080U
@@ -10706,9 +10706,9 @@
 /*
 * VrefDQ Training Range
 */
-#undef DDR_PHY_MR6_VDQTRG_DEFVAL 
-#undef DDR_PHY_MR6_VDQTRG_SHIFT 
-#undef DDR_PHY_MR6_VDQTRG_MASK 
+#undef DDR_PHY_MR6_VDQTRG_DEFVAL
+#undef DDR_PHY_MR6_VDQTRG_SHIFT
+#undef DDR_PHY_MR6_VDQTRG_MASK
 #define DDR_PHY_MR6_VDQTRG_DEFVAL                              0x00000000
 #define DDR_PHY_MR6_VDQTRG_SHIFT                               6
 #define DDR_PHY_MR6_VDQTRG_MASK                                0x00000040U
@@ -10716,9 +10716,9 @@
 /*
 * VrefDQ Training Values
 */
-#undef DDR_PHY_MR6_VDQTVAL_DEFVAL 
-#undef DDR_PHY_MR6_VDQTVAL_SHIFT 
-#undef DDR_PHY_MR6_VDQTVAL_MASK 
+#undef DDR_PHY_MR6_VDQTVAL_DEFVAL
+#undef DDR_PHY_MR6_VDQTVAL_SHIFT
+#undef DDR_PHY_MR6_VDQTVAL_MASK
 #define DDR_PHY_MR6_VDQTVAL_DEFVAL                             0x00000000
 #define DDR_PHY_MR6_VDQTVAL_SHIFT                              0
 #define DDR_PHY_MR6_VDQTVAL_MASK                               0x0000003FU
@@ -10726,9 +10726,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_MR11_RESERVED_31_8_DEFVAL 
-#undef DDR_PHY_MR11_RESERVED_31_8_SHIFT 
-#undef DDR_PHY_MR11_RESERVED_31_8_MASK 
+#undef DDR_PHY_MR11_RESERVED_31_8_DEFVAL
+#undef DDR_PHY_MR11_RESERVED_31_8_SHIFT
+#undef DDR_PHY_MR11_RESERVED_31_8_MASK
 #define DDR_PHY_MR11_RESERVED_31_8_DEFVAL                      0x00000000
 #define DDR_PHY_MR11_RESERVED_31_8_SHIFT                       8
 #define DDR_PHY_MR11_RESERVED_31_8_MASK                        0xFFFFFF00U
@@ -10737,9 +10737,9 @@
 * These are JEDEC reserved bits and are recommended by JEDEC to be program
     * med to 0x0.
 */
-#undef DDR_PHY_MR11_RSVD_DEFVAL 
-#undef DDR_PHY_MR11_RSVD_SHIFT 
-#undef DDR_PHY_MR11_RSVD_MASK 
+#undef DDR_PHY_MR11_RSVD_DEFVAL
+#undef DDR_PHY_MR11_RSVD_SHIFT
+#undef DDR_PHY_MR11_RSVD_MASK
 #define DDR_PHY_MR11_RSVD_DEFVAL                               0x00000000
 #define DDR_PHY_MR11_RSVD_SHIFT                                3
 #define DDR_PHY_MR11_RSVD_MASK                                 0x000000F8U
@@ -10747,9 +10747,9 @@
 /*
 * Power Down Control
 */
-#undef DDR_PHY_MR11_PDCTL_DEFVAL 
-#undef DDR_PHY_MR11_PDCTL_SHIFT 
-#undef DDR_PHY_MR11_PDCTL_MASK 
+#undef DDR_PHY_MR11_PDCTL_DEFVAL
+#undef DDR_PHY_MR11_PDCTL_SHIFT
+#undef DDR_PHY_MR11_PDCTL_MASK
 #define DDR_PHY_MR11_PDCTL_DEFVAL                              0x00000000
 #define DDR_PHY_MR11_PDCTL_SHIFT                               2
 #define DDR_PHY_MR11_PDCTL_MASK                                0x00000004U
@@ -10757,9 +10757,9 @@
 /*
 * DQ Bus Receiver On-Die-Termination
 */
-#undef DDR_PHY_MR11_DQODT_DEFVAL 
-#undef DDR_PHY_MR11_DQODT_SHIFT 
-#undef DDR_PHY_MR11_DQODT_MASK 
+#undef DDR_PHY_MR11_DQODT_DEFVAL
+#undef DDR_PHY_MR11_DQODT_SHIFT
+#undef DDR_PHY_MR11_DQODT_MASK
 #define DDR_PHY_MR11_DQODT_DEFVAL                              0x00000000
 #define DDR_PHY_MR11_DQODT_SHIFT                               0
 #define DDR_PHY_MR11_DQODT_MASK                                0x00000003U
@@ -10767,9 +10767,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_MR12_RESERVED_31_8_DEFVAL 
-#undef DDR_PHY_MR12_RESERVED_31_8_SHIFT 
-#undef DDR_PHY_MR12_RESERVED_31_8_MASK 
+#undef DDR_PHY_MR12_RESERVED_31_8_DEFVAL
+#undef DDR_PHY_MR12_RESERVED_31_8_SHIFT
+#undef DDR_PHY_MR12_RESERVED_31_8_MASK
 #define DDR_PHY_MR12_RESERVED_31_8_DEFVAL                      0x0000004D
 #define DDR_PHY_MR12_RESERVED_31_8_SHIFT                       8
 #define DDR_PHY_MR12_RESERVED_31_8_MASK                        0xFFFFFF00U
@@ -10778,9 +10778,9 @@
 * These are JEDEC reserved bits and are recommended by JEDEC to be program
     * med to 0x0.
 */
-#undef DDR_PHY_MR12_RSVD_DEFVAL 
-#undef DDR_PHY_MR12_RSVD_SHIFT 
-#undef DDR_PHY_MR12_RSVD_MASK 
+#undef DDR_PHY_MR12_RSVD_DEFVAL
+#undef DDR_PHY_MR12_RSVD_SHIFT
+#undef DDR_PHY_MR12_RSVD_MASK
 #define DDR_PHY_MR12_RSVD_DEFVAL                               0x0000004D
 #define DDR_PHY_MR12_RSVD_SHIFT                                7
 #define DDR_PHY_MR12_RSVD_MASK                                 0x00000080U
@@ -10788,9 +10788,9 @@
 /*
 * VREF_CA Range Select.
 */
-#undef DDR_PHY_MR12_VR_CA_DEFVAL 
-#undef DDR_PHY_MR12_VR_CA_SHIFT 
-#undef DDR_PHY_MR12_VR_CA_MASK 
+#undef DDR_PHY_MR12_VR_CA_DEFVAL
+#undef DDR_PHY_MR12_VR_CA_SHIFT
+#undef DDR_PHY_MR12_VR_CA_MASK
 #define DDR_PHY_MR12_VR_CA_DEFVAL                              0x0000004D
 #define DDR_PHY_MR12_VR_CA_SHIFT                               6
 #define DDR_PHY_MR12_VR_CA_MASK                                0x00000040U
@@ -10798,9 +10798,9 @@
 /*
 * Controls the VREF(ca) levels for Frequency-Set-Point[1:0].
 */
-#undef DDR_PHY_MR12_VREF_CA_DEFVAL 
-#undef DDR_PHY_MR12_VREF_CA_SHIFT 
-#undef DDR_PHY_MR12_VREF_CA_MASK 
+#undef DDR_PHY_MR12_VREF_CA_DEFVAL
+#undef DDR_PHY_MR12_VREF_CA_SHIFT
+#undef DDR_PHY_MR12_VREF_CA_MASK
 #define DDR_PHY_MR12_VREF_CA_DEFVAL                            0x0000004D
 #define DDR_PHY_MR12_VREF_CA_SHIFT                             0
 #define DDR_PHY_MR12_VREF_CA_MASK                              0x0000003FU
@@ -10808,9 +10808,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_MR13_RESERVED_31_8_DEFVAL 
-#undef DDR_PHY_MR13_RESERVED_31_8_SHIFT 
-#undef DDR_PHY_MR13_RESERVED_31_8_MASK 
+#undef DDR_PHY_MR13_RESERVED_31_8_DEFVAL
+#undef DDR_PHY_MR13_RESERVED_31_8_SHIFT
+#undef DDR_PHY_MR13_RESERVED_31_8_MASK
 #define DDR_PHY_MR13_RESERVED_31_8_DEFVAL                      0x00000000
 #define DDR_PHY_MR13_RESERVED_31_8_SHIFT                       8
 #define DDR_PHY_MR13_RESERVED_31_8_MASK                        0xFFFFFF00U
@@ -10818,9 +10818,9 @@
 /*
 * Frequency Set Point Operation Mode
 */
-#undef DDR_PHY_MR13_FSPOP_DEFVAL 
-#undef DDR_PHY_MR13_FSPOP_SHIFT 
-#undef DDR_PHY_MR13_FSPOP_MASK 
+#undef DDR_PHY_MR13_FSPOP_DEFVAL
+#undef DDR_PHY_MR13_FSPOP_SHIFT
+#undef DDR_PHY_MR13_FSPOP_MASK
 #define DDR_PHY_MR13_FSPOP_DEFVAL                              0x00000000
 #define DDR_PHY_MR13_FSPOP_SHIFT                               7
 #define DDR_PHY_MR13_FSPOP_MASK                                0x00000080U
@@ -10828,9 +10828,9 @@
 /*
 * Frequency Set Point Write Enable
 */
-#undef DDR_PHY_MR13_FSPWR_DEFVAL 
-#undef DDR_PHY_MR13_FSPWR_SHIFT 
-#undef DDR_PHY_MR13_FSPWR_MASK 
+#undef DDR_PHY_MR13_FSPWR_DEFVAL
+#undef DDR_PHY_MR13_FSPWR_SHIFT
+#undef DDR_PHY_MR13_FSPWR_MASK
 #define DDR_PHY_MR13_FSPWR_DEFVAL                              0x00000000
 #define DDR_PHY_MR13_FSPWR_SHIFT                               6
 #define DDR_PHY_MR13_FSPWR_MASK                                0x00000040U
@@ -10838,9 +10838,9 @@
 /*
 * Data Mask Enable
 */
-#undef DDR_PHY_MR13_DMD_DEFVAL 
-#undef DDR_PHY_MR13_DMD_SHIFT 
-#undef DDR_PHY_MR13_DMD_MASK 
+#undef DDR_PHY_MR13_DMD_DEFVAL
+#undef DDR_PHY_MR13_DMD_SHIFT
+#undef DDR_PHY_MR13_DMD_MASK
 #define DDR_PHY_MR13_DMD_DEFVAL                                0x00000000
 #define DDR_PHY_MR13_DMD_SHIFT                                 5
 #define DDR_PHY_MR13_DMD_MASK                                  0x00000020U
@@ -10848,9 +10848,9 @@
 /*
 * Refresh Rate Option
 */
-#undef DDR_PHY_MR13_RRO_DEFVAL 
-#undef DDR_PHY_MR13_RRO_SHIFT 
-#undef DDR_PHY_MR13_RRO_MASK 
+#undef DDR_PHY_MR13_RRO_DEFVAL
+#undef DDR_PHY_MR13_RRO_SHIFT
+#undef DDR_PHY_MR13_RRO_MASK
 #define DDR_PHY_MR13_RRO_DEFVAL                                0x00000000
 #define DDR_PHY_MR13_RRO_SHIFT                                 4
 #define DDR_PHY_MR13_RRO_MASK                                  0x00000010U
@@ -10858,9 +10858,9 @@
 /*
 * VREF Current Generator
 */
-#undef DDR_PHY_MR13_VRCG_DEFVAL 
-#undef DDR_PHY_MR13_VRCG_SHIFT 
-#undef DDR_PHY_MR13_VRCG_MASK 
+#undef DDR_PHY_MR13_VRCG_DEFVAL
+#undef DDR_PHY_MR13_VRCG_SHIFT
+#undef DDR_PHY_MR13_VRCG_MASK
 #define DDR_PHY_MR13_VRCG_DEFVAL                               0x00000000
 #define DDR_PHY_MR13_VRCG_SHIFT                                3
 #define DDR_PHY_MR13_VRCG_MASK                                 0x00000008U
@@ -10868,9 +10868,9 @@
 /*
 * VREF Output
 */
-#undef DDR_PHY_MR13_VRO_DEFVAL 
-#undef DDR_PHY_MR13_VRO_SHIFT 
-#undef DDR_PHY_MR13_VRO_MASK 
+#undef DDR_PHY_MR13_VRO_DEFVAL
+#undef DDR_PHY_MR13_VRO_SHIFT
+#undef DDR_PHY_MR13_VRO_MASK
 #define DDR_PHY_MR13_VRO_DEFVAL                                0x00000000
 #define DDR_PHY_MR13_VRO_SHIFT                                 2
 #define DDR_PHY_MR13_VRO_MASK                                  0x00000004U
@@ -10878,9 +10878,9 @@
 /*
 * Read Preamble Training Mode
 */
-#undef DDR_PHY_MR13_RPT_DEFVAL 
-#undef DDR_PHY_MR13_RPT_SHIFT 
-#undef DDR_PHY_MR13_RPT_MASK 
+#undef DDR_PHY_MR13_RPT_DEFVAL
+#undef DDR_PHY_MR13_RPT_SHIFT
+#undef DDR_PHY_MR13_RPT_MASK
 #define DDR_PHY_MR13_RPT_DEFVAL                                0x00000000
 #define DDR_PHY_MR13_RPT_SHIFT                                 1
 #define DDR_PHY_MR13_RPT_MASK                                  0x00000002U
@@ -10888,9 +10888,9 @@
 /*
 * Command Bus Training
 */
-#undef DDR_PHY_MR13_CBT_DEFVAL 
-#undef DDR_PHY_MR13_CBT_SHIFT 
-#undef DDR_PHY_MR13_CBT_MASK 
+#undef DDR_PHY_MR13_CBT_DEFVAL
+#undef DDR_PHY_MR13_CBT_SHIFT
+#undef DDR_PHY_MR13_CBT_MASK
 #define DDR_PHY_MR13_CBT_DEFVAL                                0x00000000
 #define DDR_PHY_MR13_CBT_SHIFT                                 0
 #define DDR_PHY_MR13_CBT_MASK                                  0x00000001U
@@ -10898,9 +10898,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_MR14_RESERVED_31_8_DEFVAL 
-#undef DDR_PHY_MR14_RESERVED_31_8_SHIFT 
-#undef DDR_PHY_MR14_RESERVED_31_8_MASK 
+#undef DDR_PHY_MR14_RESERVED_31_8_DEFVAL
+#undef DDR_PHY_MR14_RESERVED_31_8_SHIFT
+#undef DDR_PHY_MR14_RESERVED_31_8_MASK
 #define DDR_PHY_MR14_RESERVED_31_8_DEFVAL                      0x0000004D
 #define DDR_PHY_MR14_RESERVED_31_8_SHIFT                       8
 #define DDR_PHY_MR14_RESERVED_31_8_MASK                        0xFFFFFF00U
@@ -10909,9 +10909,9 @@
 * These are JEDEC reserved bits and are recommended by JEDEC to be program
     * med to 0x0.
 */
-#undef DDR_PHY_MR14_RSVD_DEFVAL 
-#undef DDR_PHY_MR14_RSVD_SHIFT 
-#undef DDR_PHY_MR14_RSVD_MASK 
+#undef DDR_PHY_MR14_RSVD_DEFVAL
+#undef DDR_PHY_MR14_RSVD_SHIFT
+#undef DDR_PHY_MR14_RSVD_MASK
 #define DDR_PHY_MR14_RSVD_DEFVAL                               0x0000004D
 #define DDR_PHY_MR14_RSVD_SHIFT                                7
 #define DDR_PHY_MR14_RSVD_MASK                                 0x00000080U
@@ -10919,9 +10919,9 @@
 /*
 * VREFDQ Range Selects.
 */
-#undef DDR_PHY_MR14_VR_DQ_DEFVAL 
-#undef DDR_PHY_MR14_VR_DQ_SHIFT 
-#undef DDR_PHY_MR14_VR_DQ_MASK 
+#undef DDR_PHY_MR14_VR_DQ_DEFVAL
+#undef DDR_PHY_MR14_VR_DQ_SHIFT
+#undef DDR_PHY_MR14_VR_DQ_MASK
 #define DDR_PHY_MR14_VR_DQ_DEFVAL                              0x0000004D
 #define DDR_PHY_MR14_VR_DQ_SHIFT                               6
 #define DDR_PHY_MR14_VR_DQ_MASK                                0x00000040U
@@ -10929,9 +10929,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_MR14_VREF_DQ_DEFVAL 
-#undef DDR_PHY_MR14_VREF_DQ_SHIFT 
-#undef DDR_PHY_MR14_VREF_DQ_MASK 
+#undef DDR_PHY_MR14_VREF_DQ_DEFVAL
+#undef DDR_PHY_MR14_VREF_DQ_SHIFT
+#undef DDR_PHY_MR14_VREF_DQ_MASK
 #define DDR_PHY_MR14_VREF_DQ_DEFVAL                            0x0000004D
 #define DDR_PHY_MR14_VREF_DQ_SHIFT                             0
 #define DDR_PHY_MR14_VREF_DQ_MASK                              0x0000003FU
@@ -10939,9 +10939,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_MR22_RESERVED_31_8_DEFVAL 
-#undef DDR_PHY_MR22_RESERVED_31_8_SHIFT 
-#undef DDR_PHY_MR22_RESERVED_31_8_MASK 
+#undef DDR_PHY_MR22_RESERVED_31_8_DEFVAL
+#undef DDR_PHY_MR22_RESERVED_31_8_SHIFT
+#undef DDR_PHY_MR22_RESERVED_31_8_MASK
 #define DDR_PHY_MR22_RESERVED_31_8_DEFVAL                      0x00000000
 #define DDR_PHY_MR22_RESERVED_31_8_SHIFT                       8
 #define DDR_PHY_MR22_RESERVED_31_8_MASK                        0xFFFFFF00U
@@ -10950,9 +10950,9 @@
 * These are JEDEC reserved bits and are recommended by JEDEC to be program
     * med to 0x0.
 */
-#undef DDR_PHY_MR22_RSVD_DEFVAL 
-#undef DDR_PHY_MR22_RSVD_SHIFT 
-#undef DDR_PHY_MR22_RSVD_MASK 
+#undef DDR_PHY_MR22_RSVD_DEFVAL
+#undef DDR_PHY_MR22_RSVD_SHIFT
+#undef DDR_PHY_MR22_RSVD_MASK
 #define DDR_PHY_MR22_RSVD_DEFVAL                               0x00000000
 #define DDR_PHY_MR22_RSVD_SHIFT                                6
 #define DDR_PHY_MR22_RSVD_MASK                                 0x000000C0U
@@ -10960,9 +10960,9 @@
 /*
 * CA ODT termination disable.
 */
-#undef DDR_PHY_MR22_ODTD_CA_DEFVAL 
-#undef DDR_PHY_MR22_ODTD_CA_SHIFT 
-#undef DDR_PHY_MR22_ODTD_CA_MASK 
+#undef DDR_PHY_MR22_ODTD_CA_DEFVAL
+#undef DDR_PHY_MR22_ODTD_CA_SHIFT
+#undef DDR_PHY_MR22_ODTD_CA_MASK
 #define DDR_PHY_MR22_ODTD_CA_DEFVAL                            0x00000000
 #define DDR_PHY_MR22_ODTD_CA_SHIFT                             5
 #define DDR_PHY_MR22_ODTD_CA_MASK                              0x00000020U
@@ -10970,9 +10970,9 @@
 /*
 * ODT CS override.
 */
-#undef DDR_PHY_MR22_ODTE_CS_DEFVAL 
-#undef DDR_PHY_MR22_ODTE_CS_SHIFT 
-#undef DDR_PHY_MR22_ODTE_CS_MASK 
+#undef DDR_PHY_MR22_ODTE_CS_DEFVAL
+#undef DDR_PHY_MR22_ODTE_CS_SHIFT
+#undef DDR_PHY_MR22_ODTE_CS_MASK
 #define DDR_PHY_MR22_ODTE_CS_DEFVAL                            0x00000000
 #define DDR_PHY_MR22_ODTE_CS_SHIFT                             4
 #define DDR_PHY_MR22_ODTE_CS_MASK                              0x00000010U
@@ -10980,9 +10980,9 @@
 /*
 * ODT CK override.
 */
-#undef DDR_PHY_MR22_ODTE_CK_DEFVAL 
-#undef DDR_PHY_MR22_ODTE_CK_SHIFT 
-#undef DDR_PHY_MR22_ODTE_CK_MASK 
+#undef DDR_PHY_MR22_ODTE_CK_DEFVAL
+#undef DDR_PHY_MR22_ODTE_CK_SHIFT
+#undef DDR_PHY_MR22_ODTE_CK_MASK
 #define DDR_PHY_MR22_ODTE_CK_DEFVAL                            0x00000000
 #define DDR_PHY_MR22_ODTE_CK_SHIFT                             3
 #define DDR_PHY_MR22_ODTE_CK_MASK                              0x00000008U
@@ -10990,9 +10990,9 @@
 /*
 * Controller ODT value for VOH calibration.
 */
-#undef DDR_PHY_MR22_CODT_DEFVAL 
-#undef DDR_PHY_MR22_CODT_SHIFT 
-#undef DDR_PHY_MR22_CODT_MASK 
+#undef DDR_PHY_MR22_CODT_DEFVAL
+#undef DDR_PHY_MR22_CODT_SHIFT
+#undef DDR_PHY_MR22_CODT_MASK
 #define DDR_PHY_MR22_CODT_DEFVAL                               0x00000000
 #define DDR_PHY_MR22_CODT_SHIFT                                0
 #define DDR_PHY_MR22_CODT_MASK                                 0x00000007U
@@ -11000,9 +11000,9 @@
 /*
 * Refresh During Training
 */
-#undef DDR_PHY_DTCR0_RFSHDT_DEFVAL 
-#undef DDR_PHY_DTCR0_RFSHDT_SHIFT 
-#undef DDR_PHY_DTCR0_RFSHDT_MASK 
+#undef DDR_PHY_DTCR0_RFSHDT_DEFVAL
+#undef DDR_PHY_DTCR0_RFSHDT_SHIFT
+#undef DDR_PHY_DTCR0_RFSHDT_MASK
 #define DDR_PHY_DTCR0_RFSHDT_DEFVAL                            0x800091C7
 #define DDR_PHY_DTCR0_RFSHDT_SHIFT                             28
 #define DDR_PHY_DTCR0_RFSHDT_MASK                              0xF0000000U
@@ -11010,9 +11010,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DTCR0_RESERVED_27_26_DEFVAL 
-#undef DDR_PHY_DTCR0_RESERVED_27_26_SHIFT 
-#undef DDR_PHY_DTCR0_RESERVED_27_26_MASK 
+#undef DDR_PHY_DTCR0_RESERVED_27_26_DEFVAL
+#undef DDR_PHY_DTCR0_RESERVED_27_26_SHIFT
+#undef DDR_PHY_DTCR0_RESERVED_27_26_MASK
 #define DDR_PHY_DTCR0_RESERVED_27_26_DEFVAL                    0x800091C7
 #define DDR_PHY_DTCR0_RESERVED_27_26_SHIFT                     26
 #define DDR_PHY_DTCR0_RESERVED_27_26_MASK                      0x0C000000U
@@ -11020,9 +11020,9 @@
 /*
 * Data Training Debug Rank Select
 */
-#undef DDR_PHY_DTCR0_DTDRS_DEFVAL 
-#undef DDR_PHY_DTCR0_DTDRS_SHIFT 
-#undef DDR_PHY_DTCR0_DTDRS_MASK 
+#undef DDR_PHY_DTCR0_DTDRS_DEFVAL
+#undef DDR_PHY_DTCR0_DTDRS_SHIFT
+#undef DDR_PHY_DTCR0_DTDRS_MASK
 #define DDR_PHY_DTCR0_DTDRS_DEFVAL                             0x800091C7
 #define DDR_PHY_DTCR0_DTDRS_SHIFT                              24
 #define DDR_PHY_DTCR0_DTDRS_MASK                               0x03000000U
@@ -11030,9 +11030,9 @@
 /*
 * Data Training with Early/Extended Gate
 */
-#undef DDR_PHY_DTCR0_DTEXG_DEFVAL 
-#undef DDR_PHY_DTCR0_DTEXG_SHIFT 
-#undef DDR_PHY_DTCR0_DTEXG_MASK 
+#undef DDR_PHY_DTCR0_DTEXG_DEFVAL
+#undef DDR_PHY_DTCR0_DTEXG_SHIFT
+#undef DDR_PHY_DTCR0_DTEXG_MASK
 #define DDR_PHY_DTCR0_DTEXG_DEFVAL                             0x800091C7
 #define DDR_PHY_DTCR0_DTEXG_SHIFT                              23
 #define DDR_PHY_DTCR0_DTEXG_MASK                               0x00800000U
@@ -11040,9 +11040,9 @@
 /*
 * Data Training Extended Write DQS
 */
-#undef DDR_PHY_DTCR0_DTEXD_DEFVAL 
-#undef DDR_PHY_DTCR0_DTEXD_SHIFT 
-#undef DDR_PHY_DTCR0_DTEXD_MASK 
+#undef DDR_PHY_DTCR0_DTEXD_DEFVAL
+#undef DDR_PHY_DTCR0_DTEXD_SHIFT
+#undef DDR_PHY_DTCR0_DTEXD_MASK
 #define DDR_PHY_DTCR0_DTEXD_DEFVAL                             0x800091C7
 #define DDR_PHY_DTCR0_DTEXD_SHIFT                              22
 #define DDR_PHY_DTCR0_DTEXD_MASK                               0x00400000U
@@ -11050,9 +11050,9 @@
 /*
 * Data Training Debug Step
 */
-#undef DDR_PHY_DTCR0_DTDSTP_DEFVAL 
-#undef DDR_PHY_DTCR0_DTDSTP_SHIFT 
-#undef DDR_PHY_DTCR0_DTDSTP_MASK 
+#undef DDR_PHY_DTCR0_DTDSTP_DEFVAL
+#undef DDR_PHY_DTCR0_DTDSTP_SHIFT
+#undef DDR_PHY_DTCR0_DTDSTP_MASK
 #define DDR_PHY_DTCR0_DTDSTP_DEFVAL                            0x800091C7
 #define DDR_PHY_DTCR0_DTDSTP_SHIFT                             21
 #define DDR_PHY_DTCR0_DTDSTP_MASK                              0x00200000U
@@ -11060,9 +11060,9 @@
 /*
 * Data Training Debug Enable
 */
-#undef DDR_PHY_DTCR0_DTDEN_DEFVAL 
-#undef DDR_PHY_DTCR0_DTDEN_SHIFT 
-#undef DDR_PHY_DTCR0_DTDEN_MASK 
+#undef DDR_PHY_DTCR0_DTDEN_DEFVAL
+#undef DDR_PHY_DTCR0_DTDEN_SHIFT
+#undef DDR_PHY_DTCR0_DTDEN_MASK
 #define DDR_PHY_DTCR0_DTDEN_DEFVAL                             0x800091C7
 #define DDR_PHY_DTCR0_DTDEN_SHIFT                              20
 #define DDR_PHY_DTCR0_DTDEN_MASK                               0x00100000U
@@ -11070,9 +11070,9 @@
 /*
 * Data Training Debug Byte Select
 */
-#undef DDR_PHY_DTCR0_DTDBS_DEFVAL 
-#undef DDR_PHY_DTCR0_DTDBS_SHIFT 
-#undef DDR_PHY_DTCR0_DTDBS_MASK 
+#undef DDR_PHY_DTCR0_DTDBS_DEFVAL
+#undef DDR_PHY_DTCR0_DTDBS_SHIFT
+#undef DDR_PHY_DTCR0_DTDBS_MASK
 #define DDR_PHY_DTCR0_DTDBS_DEFVAL                             0x800091C7
 #define DDR_PHY_DTCR0_DTDBS_SHIFT                              16
 #define DDR_PHY_DTCR0_DTDBS_MASK                               0x000F0000U
@@ -11080,9 +11080,9 @@
 /*
 * Data Training read DBI deskewing configuration
 */
-#undef DDR_PHY_DTCR0_DTRDBITR_DEFVAL 
-#undef DDR_PHY_DTCR0_DTRDBITR_SHIFT 
-#undef DDR_PHY_DTCR0_DTRDBITR_MASK 
+#undef DDR_PHY_DTCR0_DTRDBITR_DEFVAL
+#undef DDR_PHY_DTCR0_DTRDBITR_SHIFT
+#undef DDR_PHY_DTCR0_DTRDBITR_MASK
 #define DDR_PHY_DTCR0_DTRDBITR_DEFVAL                          0x800091C7
 #define DDR_PHY_DTCR0_DTRDBITR_SHIFT                           14
 #define DDR_PHY_DTCR0_DTRDBITR_MASK                            0x0000C000U
@@ -11090,9 +11090,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DTCR0_RESERVED_13_DEFVAL 
-#undef DDR_PHY_DTCR0_RESERVED_13_SHIFT 
-#undef DDR_PHY_DTCR0_RESERVED_13_MASK 
+#undef DDR_PHY_DTCR0_RESERVED_13_DEFVAL
+#undef DDR_PHY_DTCR0_RESERVED_13_SHIFT
+#undef DDR_PHY_DTCR0_RESERVED_13_MASK
 #define DDR_PHY_DTCR0_RESERVED_13_DEFVAL                       0x800091C7
 #define DDR_PHY_DTCR0_RESERVED_13_SHIFT                        13
 #define DDR_PHY_DTCR0_RESERVED_13_MASK                         0x00002000U
@@ -11100,9 +11100,9 @@
 /*
 * Data Training Write Bit Deskew Data Mask
 */
-#undef DDR_PHY_DTCR0_DTWBDDM_DEFVAL 
-#undef DDR_PHY_DTCR0_DTWBDDM_SHIFT 
-#undef DDR_PHY_DTCR0_DTWBDDM_MASK 
+#undef DDR_PHY_DTCR0_DTWBDDM_DEFVAL
+#undef DDR_PHY_DTCR0_DTWBDDM_SHIFT
+#undef DDR_PHY_DTCR0_DTWBDDM_MASK
 #define DDR_PHY_DTCR0_DTWBDDM_DEFVAL                           0x800091C7
 #define DDR_PHY_DTCR0_DTWBDDM_SHIFT                            12
 #define DDR_PHY_DTCR0_DTWBDDM_MASK                             0x00001000U
@@ -11110,9 +11110,9 @@
 /*
 * Refreshes Issued During Entry to Training
 */
-#undef DDR_PHY_DTCR0_RFSHEN_DEFVAL 
-#undef DDR_PHY_DTCR0_RFSHEN_SHIFT 
-#undef DDR_PHY_DTCR0_RFSHEN_MASK 
+#undef DDR_PHY_DTCR0_RFSHEN_DEFVAL
+#undef DDR_PHY_DTCR0_RFSHEN_SHIFT
+#undef DDR_PHY_DTCR0_RFSHEN_MASK
 #define DDR_PHY_DTCR0_RFSHEN_DEFVAL                            0x800091C7
 #define DDR_PHY_DTCR0_RFSHEN_SHIFT                             8
 #define DDR_PHY_DTCR0_RFSHEN_MASK                              0x00000F00U
@@ -11120,9 +11120,9 @@
 /*
 * Data Training Compare Data
 */
-#undef DDR_PHY_DTCR0_DTCMPD_DEFVAL 
-#undef DDR_PHY_DTCR0_DTCMPD_SHIFT 
-#undef DDR_PHY_DTCR0_DTCMPD_MASK 
+#undef DDR_PHY_DTCR0_DTCMPD_DEFVAL
+#undef DDR_PHY_DTCR0_DTCMPD_SHIFT
+#undef DDR_PHY_DTCR0_DTCMPD_MASK
 #define DDR_PHY_DTCR0_DTCMPD_DEFVAL                            0x800091C7
 #define DDR_PHY_DTCR0_DTCMPD_SHIFT                             7
 #define DDR_PHY_DTCR0_DTCMPD_MASK                              0x00000080U
@@ -11130,9 +11130,9 @@
 /*
 * Data Training Using MPR
 */
-#undef DDR_PHY_DTCR0_DTMPR_DEFVAL 
-#undef DDR_PHY_DTCR0_DTMPR_SHIFT 
-#undef DDR_PHY_DTCR0_DTMPR_MASK 
+#undef DDR_PHY_DTCR0_DTMPR_DEFVAL
+#undef DDR_PHY_DTCR0_DTMPR_SHIFT
+#undef DDR_PHY_DTCR0_DTMPR_MASK
 #define DDR_PHY_DTCR0_DTMPR_DEFVAL                             0x800091C7
 #define DDR_PHY_DTCR0_DTMPR_SHIFT                              6
 #define DDR_PHY_DTCR0_DTMPR_MASK                               0x00000040U
@@ -11140,9 +11140,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DTCR0_RESERVED_5_4_DEFVAL 
-#undef DDR_PHY_DTCR0_RESERVED_5_4_SHIFT 
-#undef DDR_PHY_DTCR0_RESERVED_5_4_MASK 
+#undef DDR_PHY_DTCR0_RESERVED_5_4_DEFVAL
+#undef DDR_PHY_DTCR0_RESERVED_5_4_SHIFT
+#undef DDR_PHY_DTCR0_RESERVED_5_4_MASK
 #define DDR_PHY_DTCR0_RESERVED_5_4_DEFVAL                      0x800091C7
 #define DDR_PHY_DTCR0_RESERVED_5_4_SHIFT                       4
 #define DDR_PHY_DTCR0_RESERVED_5_4_MASK                        0x00000030U
@@ -11150,9 +11150,9 @@
 /*
 * Data Training Repeat Number
 */
-#undef DDR_PHY_DTCR0_DTRPTN_DEFVAL 
-#undef DDR_PHY_DTCR0_DTRPTN_SHIFT 
-#undef DDR_PHY_DTCR0_DTRPTN_MASK 
+#undef DDR_PHY_DTCR0_DTRPTN_DEFVAL
+#undef DDR_PHY_DTCR0_DTRPTN_SHIFT
+#undef DDR_PHY_DTCR0_DTRPTN_MASK
 #define DDR_PHY_DTCR0_DTRPTN_DEFVAL                            0x800091C7
 #define DDR_PHY_DTCR0_DTRPTN_SHIFT                             0
 #define DDR_PHY_DTCR0_DTRPTN_MASK                              0x0000000FU
@@ -11160,9 +11160,9 @@
 /*
 * Rank Enable.
 */
-#undef DDR_PHY_DTCR1_RANKEN_RSVD_DEFVAL 
-#undef DDR_PHY_DTCR1_RANKEN_RSVD_SHIFT 
-#undef DDR_PHY_DTCR1_RANKEN_RSVD_MASK 
+#undef DDR_PHY_DTCR1_RANKEN_RSVD_DEFVAL
+#undef DDR_PHY_DTCR1_RANKEN_RSVD_SHIFT
+#undef DDR_PHY_DTCR1_RANKEN_RSVD_MASK
 #define DDR_PHY_DTCR1_RANKEN_RSVD_DEFVAL                       0x00030237
 #define DDR_PHY_DTCR1_RANKEN_RSVD_SHIFT                        18
 #define DDR_PHY_DTCR1_RANKEN_RSVD_MASK                         0xFFFC0000U
@@ -11170,9 +11170,9 @@
 /*
 * Rank Enable.
 */
-#undef DDR_PHY_DTCR1_RANKEN_DEFVAL 
-#undef DDR_PHY_DTCR1_RANKEN_SHIFT 
-#undef DDR_PHY_DTCR1_RANKEN_MASK 
+#undef DDR_PHY_DTCR1_RANKEN_DEFVAL
+#undef DDR_PHY_DTCR1_RANKEN_SHIFT
+#undef DDR_PHY_DTCR1_RANKEN_MASK
 #define DDR_PHY_DTCR1_RANKEN_DEFVAL                            0x00030237
 #define DDR_PHY_DTCR1_RANKEN_SHIFT                             16
 #define DDR_PHY_DTCR1_RANKEN_MASK                              0x00030000U
@@ -11180,9 +11180,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DTCR1_RESERVED_15_14_DEFVAL 
-#undef DDR_PHY_DTCR1_RESERVED_15_14_SHIFT 
-#undef DDR_PHY_DTCR1_RESERVED_15_14_MASK 
+#undef DDR_PHY_DTCR1_RESERVED_15_14_DEFVAL
+#undef DDR_PHY_DTCR1_RESERVED_15_14_SHIFT
+#undef DDR_PHY_DTCR1_RESERVED_15_14_MASK
 #define DDR_PHY_DTCR1_RESERVED_15_14_DEFVAL                    0x00030237
 #define DDR_PHY_DTCR1_RESERVED_15_14_SHIFT                     14
 #define DDR_PHY_DTCR1_RESERVED_15_14_MASK                      0x0000C000U
@@ -11190,9 +11190,9 @@
 /*
 * Data Training Rank
 */
-#undef DDR_PHY_DTCR1_DTRANK_DEFVAL 
-#undef DDR_PHY_DTCR1_DTRANK_SHIFT 
-#undef DDR_PHY_DTCR1_DTRANK_MASK 
+#undef DDR_PHY_DTCR1_DTRANK_DEFVAL
+#undef DDR_PHY_DTCR1_DTRANK_SHIFT
+#undef DDR_PHY_DTCR1_DTRANK_MASK
 #define DDR_PHY_DTCR1_DTRANK_DEFVAL                            0x00030237
 #define DDR_PHY_DTCR1_DTRANK_SHIFT                             12
 #define DDR_PHY_DTCR1_DTRANK_MASK                              0x00003000U
@@ -11200,9 +11200,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DTCR1_RESERVED_11_DEFVAL 
-#undef DDR_PHY_DTCR1_RESERVED_11_SHIFT 
-#undef DDR_PHY_DTCR1_RESERVED_11_MASK 
+#undef DDR_PHY_DTCR1_RESERVED_11_DEFVAL
+#undef DDR_PHY_DTCR1_RESERVED_11_SHIFT
+#undef DDR_PHY_DTCR1_RESERVED_11_MASK
 #define DDR_PHY_DTCR1_RESERVED_11_DEFVAL                       0x00030237
 #define DDR_PHY_DTCR1_RESERVED_11_SHIFT                        11
 #define DDR_PHY_DTCR1_RESERVED_11_MASK                         0x00000800U
@@ -11210,9 +11210,9 @@
 /*
 * Read Leveling Gate Sampling Difference
 */
-#undef DDR_PHY_DTCR1_RDLVLGDIFF_DEFVAL 
-#undef DDR_PHY_DTCR1_RDLVLGDIFF_SHIFT 
-#undef DDR_PHY_DTCR1_RDLVLGDIFF_MASK 
+#undef DDR_PHY_DTCR1_RDLVLGDIFF_DEFVAL
+#undef DDR_PHY_DTCR1_RDLVLGDIFF_SHIFT
+#undef DDR_PHY_DTCR1_RDLVLGDIFF_MASK
 #define DDR_PHY_DTCR1_RDLVLGDIFF_DEFVAL                        0x00030237
 #define DDR_PHY_DTCR1_RDLVLGDIFF_SHIFT                         8
 #define DDR_PHY_DTCR1_RDLVLGDIFF_MASK                          0x00000700U
@@ -11220,9 +11220,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DTCR1_RESERVED_7_DEFVAL 
-#undef DDR_PHY_DTCR1_RESERVED_7_SHIFT 
-#undef DDR_PHY_DTCR1_RESERVED_7_MASK 
+#undef DDR_PHY_DTCR1_RESERVED_7_DEFVAL
+#undef DDR_PHY_DTCR1_RESERVED_7_SHIFT
+#undef DDR_PHY_DTCR1_RESERVED_7_MASK
 #define DDR_PHY_DTCR1_RESERVED_7_DEFVAL                        0x00030237
 #define DDR_PHY_DTCR1_RESERVED_7_SHIFT                         7
 #define DDR_PHY_DTCR1_RESERVED_7_MASK                          0x00000080U
@@ -11230,9 +11230,9 @@
 /*
 * Read Leveling Gate Shift
 */
-#undef DDR_PHY_DTCR1_RDLVLGS_DEFVAL 
-#undef DDR_PHY_DTCR1_RDLVLGS_SHIFT 
-#undef DDR_PHY_DTCR1_RDLVLGS_MASK 
+#undef DDR_PHY_DTCR1_RDLVLGS_DEFVAL
+#undef DDR_PHY_DTCR1_RDLVLGS_SHIFT
+#undef DDR_PHY_DTCR1_RDLVLGS_MASK
 #define DDR_PHY_DTCR1_RDLVLGS_DEFVAL                           0x00030237
 #define DDR_PHY_DTCR1_RDLVLGS_SHIFT                            4
 #define DDR_PHY_DTCR1_RDLVLGS_MASK                             0x00000070U
@@ -11240,9 +11240,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DTCR1_RESERVED_3_DEFVAL 
-#undef DDR_PHY_DTCR1_RESERVED_3_SHIFT 
-#undef DDR_PHY_DTCR1_RESERVED_3_MASK 
+#undef DDR_PHY_DTCR1_RESERVED_3_DEFVAL
+#undef DDR_PHY_DTCR1_RESERVED_3_SHIFT
+#undef DDR_PHY_DTCR1_RESERVED_3_MASK
 #define DDR_PHY_DTCR1_RESERVED_3_DEFVAL                        0x00030237
 #define DDR_PHY_DTCR1_RESERVED_3_SHIFT                         3
 #define DDR_PHY_DTCR1_RESERVED_3_MASK                          0x00000008U
@@ -11250,9 +11250,9 @@
 /*
 * Read Preamble Training enable
 */
-#undef DDR_PHY_DTCR1_RDPRMVL_TRN_DEFVAL 
-#undef DDR_PHY_DTCR1_RDPRMVL_TRN_SHIFT 
-#undef DDR_PHY_DTCR1_RDPRMVL_TRN_MASK 
+#undef DDR_PHY_DTCR1_RDPRMVL_TRN_DEFVAL
+#undef DDR_PHY_DTCR1_RDPRMVL_TRN_SHIFT
+#undef DDR_PHY_DTCR1_RDPRMVL_TRN_MASK
 #define DDR_PHY_DTCR1_RDPRMVL_TRN_DEFVAL                       0x00030237
 #define DDR_PHY_DTCR1_RDPRMVL_TRN_SHIFT                        2
 #define DDR_PHY_DTCR1_RDPRMVL_TRN_MASK                         0x00000004U
@@ -11260,9 +11260,9 @@
 /*
 * Read Leveling Enable
 */
-#undef DDR_PHY_DTCR1_RDLVLEN_DEFVAL 
-#undef DDR_PHY_DTCR1_RDLVLEN_SHIFT 
-#undef DDR_PHY_DTCR1_RDLVLEN_MASK 
+#undef DDR_PHY_DTCR1_RDLVLEN_DEFVAL
+#undef DDR_PHY_DTCR1_RDLVLEN_SHIFT
+#undef DDR_PHY_DTCR1_RDLVLEN_MASK
 #define DDR_PHY_DTCR1_RDLVLEN_DEFVAL                           0x00030237
 #define DDR_PHY_DTCR1_RDLVLEN_SHIFT                            1
 #define DDR_PHY_DTCR1_RDLVLEN_MASK                             0x00000002U
@@ -11270,9 +11270,9 @@
 /*
 * Basic Gate Training Enable
 */
-#undef DDR_PHY_DTCR1_BSTEN_DEFVAL 
-#undef DDR_PHY_DTCR1_BSTEN_SHIFT 
-#undef DDR_PHY_DTCR1_BSTEN_MASK 
+#undef DDR_PHY_DTCR1_BSTEN_DEFVAL
+#undef DDR_PHY_DTCR1_BSTEN_SHIFT
+#undef DDR_PHY_DTCR1_BSTEN_MASK
 #define DDR_PHY_DTCR1_BSTEN_DEFVAL                             0x00030237
 #define DDR_PHY_DTCR1_BSTEN_SHIFT                              0
 #define DDR_PHY_DTCR1_BSTEN_MASK                               0x00000001U
@@ -11280,9 +11280,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_CATR0_RESERVED_31_21_DEFVAL 
-#undef DDR_PHY_CATR0_RESERVED_31_21_SHIFT 
-#undef DDR_PHY_CATR0_RESERVED_31_21_MASK 
+#undef DDR_PHY_CATR0_RESERVED_31_21_DEFVAL
+#undef DDR_PHY_CATR0_RESERVED_31_21_SHIFT
+#undef DDR_PHY_CATR0_RESERVED_31_21_MASK
 #define DDR_PHY_CATR0_RESERVED_31_21_DEFVAL                    0x00141054
 #define DDR_PHY_CATR0_RESERVED_31_21_SHIFT                     21
 #define DDR_PHY_CATR0_RESERVED_31_21_MASK                      0xFFE00000U
@@ -11291,9 +11291,9 @@
 * Minimum time (in terms of number of dram clocks) between two consectuve
     * CA calibration command
 */
-#undef DDR_PHY_CATR0_CACD_DEFVAL 
-#undef DDR_PHY_CATR0_CACD_SHIFT 
-#undef DDR_PHY_CATR0_CACD_MASK 
+#undef DDR_PHY_CATR0_CACD_DEFVAL
+#undef DDR_PHY_CATR0_CACD_SHIFT
+#undef DDR_PHY_CATR0_CACD_MASK
 #define DDR_PHY_CATR0_CACD_DEFVAL                              0x00141054
 #define DDR_PHY_CATR0_CACD_SHIFT                               16
 #define DDR_PHY_CATR0_CACD_MASK                                0x001F0000U
@@ -11301,9 +11301,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_CATR0_RESERVED_15_13_DEFVAL 
-#undef DDR_PHY_CATR0_RESERVED_15_13_SHIFT 
-#undef DDR_PHY_CATR0_RESERVED_15_13_MASK 
+#undef DDR_PHY_CATR0_RESERVED_15_13_DEFVAL
+#undef DDR_PHY_CATR0_RESERVED_15_13_SHIFT
+#undef DDR_PHY_CATR0_RESERVED_15_13_MASK
 #define DDR_PHY_CATR0_RESERVED_15_13_DEFVAL                    0x00141054
 #define DDR_PHY_CATR0_RESERVED_15_13_SHIFT                     13
 #define DDR_PHY_CATR0_RESERVED_15_13_MASK                      0x0000E000U
@@ -11313,9 +11313,9 @@
     * sampling the CA response after Calibration command has been sent to the
     * memory
 */
-#undef DDR_PHY_CATR0_CAADR_DEFVAL 
-#undef DDR_PHY_CATR0_CAADR_SHIFT 
-#undef DDR_PHY_CATR0_CAADR_MASK 
+#undef DDR_PHY_CATR0_CAADR_DEFVAL
+#undef DDR_PHY_CATR0_CAADR_SHIFT
+#undef DDR_PHY_CATR0_CAADR_MASK
 #define DDR_PHY_CATR0_CAADR_DEFVAL                             0x00141054
 #define DDR_PHY_CATR0_CAADR_SHIFT                              8
 #define DDR_PHY_CATR0_CAADR_MASK                               0x00001F00U
@@ -11323,9 +11323,9 @@
 /*
 * CA_1 Response Byte Lane 1
 */
-#undef DDR_PHY_CATR0_CA1BYTE1_DEFVAL 
-#undef DDR_PHY_CATR0_CA1BYTE1_SHIFT 
-#undef DDR_PHY_CATR0_CA1BYTE1_MASK 
+#undef DDR_PHY_CATR0_CA1BYTE1_DEFVAL
+#undef DDR_PHY_CATR0_CA1BYTE1_SHIFT
+#undef DDR_PHY_CATR0_CA1BYTE1_MASK
 #define DDR_PHY_CATR0_CA1BYTE1_DEFVAL                          0x00141054
 #define DDR_PHY_CATR0_CA1BYTE1_SHIFT                           4
 #define DDR_PHY_CATR0_CA1BYTE1_MASK                            0x000000F0U
@@ -11333,9 +11333,9 @@
 /*
 * CA_1 Response Byte Lane 0
 */
-#undef DDR_PHY_CATR0_CA1BYTE0_DEFVAL 
-#undef DDR_PHY_CATR0_CA1BYTE0_SHIFT 
-#undef DDR_PHY_CATR0_CA1BYTE0_MASK 
+#undef DDR_PHY_CATR0_CA1BYTE0_DEFVAL
+#undef DDR_PHY_CATR0_CA1BYTE0_SHIFT
+#undef DDR_PHY_CATR0_CA1BYTE0_MASK
 #define DDR_PHY_CATR0_CA1BYTE0_DEFVAL                          0x00141054
 #define DDR_PHY_CATR0_CA1BYTE0_SHIFT                           0
 #define DDR_PHY_CATR0_CA1BYTE0_MASK                            0x0000000FU
@@ -11344,9 +11344,9 @@
 * Number of delay taps by which the DQS gate LCDL will be updated when DQS
     *  drift is detected
 */
-#undef DDR_PHY_DQSDR0_DFTDLY_DEFVAL 
-#undef DDR_PHY_DQSDR0_DFTDLY_SHIFT 
-#undef DDR_PHY_DQSDR0_DFTDLY_MASK 
+#undef DDR_PHY_DQSDR0_DFTDLY_DEFVAL
+#undef DDR_PHY_DQSDR0_DFTDLY_SHIFT
+#undef DDR_PHY_DQSDR0_DFTDLY_MASK
 #define DDR_PHY_DQSDR0_DFTDLY_DEFVAL                           0x00088000
 #define DDR_PHY_DQSDR0_DFTDLY_SHIFT                            28
 #define DDR_PHY_DQSDR0_DFTDLY_MASK                             0xF0000000U
@@ -11354,9 +11354,9 @@
 /*
 * Drift Impedance Update
 */
-#undef DDR_PHY_DQSDR0_DFTZQUP_DEFVAL 
-#undef DDR_PHY_DQSDR0_DFTZQUP_SHIFT 
-#undef DDR_PHY_DQSDR0_DFTZQUP_MASK 
+#undef DDR_PHY_DQSDR0_DFTZQUP_DEFVAL
+#undef DDR_PHY_DQSDR0_DFTZQUP_SHIFT
+#undef DDR_PHY_DQSDR0_DFTZQUP_MASK
 #define DDR_PHY_DQSDR0_DFTZQUP_DEFVAL                          0x00088000
 #define DDR_PHY_DQSDR0_DFTZQUP_SHIFT                           27
 #define DDR_PHY_DQSDR0_DFTZQUP_MASK                            0x08000000U
@@ -11364,9 +11364,9 @@
 /*
 * Drift DDL Update
 */
-#undef DDR_PHY_DQSDR0_DFTDDLUP_DEFVAL 
-#undef DDR_PHY_DQSDR0_DFTDDLUP_SHIFT 
-#undef DDR_PHY_DQSDR0_DFTDDLUP_MASK 
+#undef DDR_PHY_DQSDR0_DFTDDLUP_DEFVAL
+#undef DDR_PHY_DQSDR0_DFTDDLUP_SHIFT
+#undef DDR_PHY_DQSDR0_DFTDDLUP_MASK
 #define DDR_PHY_DQSDR0_DFTDDLUP_DEFVAL                         0x00088000
 #define DDR_PHY_DQSDR0_DFTDDLUP_SHIFT                          26
 #define DDR_PHY_DQSDR0_DFTDDLUP_MASK                           0x04000000U
@@ -11374,9 +11374,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DQSDR0_RESERVED_25_22_DEFVAL 
-#undef DDR_PHY_DQSDR0_RESERVED_25_22_SHIFT 
-#undef DDR_PHY_DQSDR0_RESERVED_25_22_MASK 
+#undef DDR_PHY_DQSDR0_RESERVED_25_22_DEFVAL
+#undef DDR_PHY_DQSDR0_RESERVED_25_22_SHIFT
+#undef DDR_PHY_DQSDR0_RESERVED_25_22_MASK
 #define DDR_PHY_DQSDR0_RESERVED_25_22_DEFVAL                   0x00088000
 #define DDR_PHY_DQSDR0_RESERVED_25_22_SHIFT                    22
 #define DDR_PHY_DQSDR0_RESERVED_25_22_MASK                     0x03C00000U
@@ -11384,9 +11384,9 @@
 /*
 * Drift Read Spacing
 */
-#undef DDR_PHY_DQSDR0_DFTRDSPC_DEFVAL 
-#undef DDR_PHY_DQSDR0_DFTRDSPC_SHIFT 
-#undef DDR_PHY_DQSDR0_DFTRDSPC_MASK 
+#undef DDR_PHY_DQSDR0_DFTRDSPC_DEFVAL
+#undef DDR_PHY_DQSDR0_DFTRDSPC_SHIFT
+#undef DDR_PHY_DQSDR0_DFTRDSPC_MASK
 #define DDR_PHY_DQSDR0_DFTRDSPC_DEFVAL                         0x00088000
 #define DDR_PHY_DQSDR0_DFTRDSPC_SHIFT                          20
 #define DDR_PHY_DQSDR0_DFTRDSPC_MASK                           0x00300000U
@@ -11394,9 +11394,9 @@
 /*
 * Drift Back-to-Back Reads
 */
-#undef DDR_PHY_DQSDR0_DFTB2BRD_DEFVAL 
-#undef DDR_PHY_DQSDR0_DFTB2BRD_SHIFT 
-#undef DDR_PHY_DQSDR0_DFTB2BRD_MASK 
+#undef DDR_PHY_DQSDR0_DFTB2BRD_DEFVAL
+#undef DDR_PHY_DQSDR0_DFTB2BRD_SHIFT
+#undef DDR_PHY_DQSDR0_DFTB2BRD_MASK
 #define DDR_PHY_DQSDR0_DFTB2BRD_DEFVAL                         0x00088000
 #define DDR_PHY_DQSDR0_DFTB2BRD_SHIFT                          16
 #define DDR_PHY_DQSDR0_DFTB2BRD_MASK                           0x000F0000U
@@ -11404,9 +11404,9 @@
 /*
 * Drift Idle Reads
 */
-#undef DDR_PHY_DQSDR0_DFTIDLRD_DEFVAL 
-#undef DDR_PHY_DQSDR0_DFTIDLRD_SHIFT 
-#undef DDR_PHY_DQSDR0_DFTIDLRD_MASK 
+#undef DDR_PHY_DQSDR0_DFTIDLRD_DEFVAL
+#undef DDR_PHY_DQSDR0_DFTIDLRD_SHIFT
+#undef DDR_PHY_DQSDR0_DFTIDLRD_MASK
 #define DDR_PHY_DQSDR0_DFTIDLRD_DEFVAL                         0x00088000
 #define DDR_PHY_DQSDR0_DFTIDLRD_SHIFT                          12
 #define DDR_PHY_DQSDR0_DFTIDLRD_MASK                           0x0000F000U
@@ -11414,9 +11414,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DQSDR0_RESERVED_11_8_DEFVAL 
-#undef DDR_PHY_DQSDR0_RESERVED_11_8_SHIFT 
-#undef DDR_PHY_DQSDR0_RESERVED_11_8_MASK 
+#undef DDR_PHY_DQSDR0_RESERVED_11_8_DEFVAL
+#undef DDR_PHY_DQSDR0_RESERVED_11_8_SHIFT
+#undef DDR_PHY_DQSDR0_RESERVED_11_8_MASK
 #define DDR_PHY_DQSDR0_RESERVED_11_8_DEFVAL                    0x00088000
 #define DDR_PHY_DQSDR0_RESERVED_11_8_SHIFT                     8
 #define DDR_PHY_DQSDR0_RESERVED_11_8_MASK                      0x00000F00U
@@ -11424,9 +11424,9 @@
 /*
 * Gate Pulse Enable
 */
-#undef DDR_PHY_DQSDR0_DFTGPULSE_DEFVAL 
-#undef DDR_PHY_DQSDR0_DFTGPULSE_SHIFT 
-#undef DDR_PHY_DQSDR0_DFTGPULSE_MASK 
+#undef DDR_PHY_DQSDR0_DFTGPULSE_DEFVAL
+#undef DDR_PHY_DQSDR0_DFTGPULSE_SHIFT
+#undef DDR_PHY_DQSDR0_DFTGPULSE_MASK
 #define DDR_PHY_DQSDR0_DFTGPULSE_DEFVAL                        0x00088000
 #define DDR_PHY_DQSDR0_DFTGPULSE_SHIFT                         4
 #define DDR_PHY_DQSDR0_DFTGPULSE_MASK                          0x000000F0U
@@ -11434,9 +11434,9 @@
 /*
 * DQS Drift Update Mode
 */
-#undef DDR_PHY_DQSDR0_DFTUPMODE_DEFVAL 
-#undef DDR_PHY_DQSDR0_DFTUPMODE_SHIFT 
-#undef DDR_PHY_DQSDR0_DFTUPMODE_MASK 
+#undef DDR_PHY_DQSDR0_DFTUPMODE_DEFVAL
+#undef DDR_PHY_DQSDR0_DFTUPMODE_SHIFT
+#undef DDR_PHY_DQSDR0_DFTUPMODE_MASK
 #define DDR_PHY_DQSDR0_DFTUPMODE_DEFVAL                        0x00088000
 #define DDR_PHY_DQSDR0_DFTUPMODE_SHIFT                         2
 #define DDR_PHY_DQSDR0_DFTUPMODE_MASK                          0x0000000CU
@@ -11444,9 +11444,9 @@
 /*
 * DQS Drift Detection Mode
 */
-#undef DDR_PHY_DQSDR0_DFTDTMODE_DEFVAL 
-#undef DDR_PHY_DQSDR0_DFTDTMODE_SHIFT 
-#undef DDR_PHY_DQSDR0_DFTDTMODE_MASK 
+#undef DDR_PHY_DQSDR0_DFTDTMODE_DEFVAL
+#undef DDR_PHY_DQSDR0_DFTDTMODE_SHIFT
+#undef DDR_PHY_DQSDR0_DFTDTMODE_MASK
 #define DDR_PHY_DQSDR0_DFTDTMODE_DEFVAL                        0x00088000
 #define DDR_PHY_DQSDR0_DFTDTMODE_SHIFT                         1
 #define DDR_PHY_DQSDR0_DFTDTMODE_MASK                          0x00000002U
@@ -11454,9 +11454,9 @@
 /*
 * DQS Drift Detection Enable
 */
-#undef DDR_PHY_DQSDR0_DFTDTEN_DEFVAL 
-#undef DDR_PHY_DQSDR0_DFTDTEN_SHIFT 
-#undef DDR_PHY_DQSDR0_DFTDTEN_MASK 
+#undef DDR_PHY_DQSDR0_DFTDTEN_DEFVAL
+#undef DDR_PHY_DQSDR0_DFTDTEN_SHIFT
+#undef DDR_PHY_DQSDR0_DFTDTEN_MASK
 #define DDR_PHY_DQSDR0_DFTDTEN_DEFVAL                          0x00088000
 #define DDR_PHY_DQSDR0_DFTDTEN_SHIFT                           0
 #define DDR_PHY_DQSDR0_DFTDTEN_MASK                            0x00000001U
@@ -11464,19 +11464,19 @@
 /*
 * LFSR seed for pseudo-random BIST patterns
 */
-#undef DDR_PHY_BISTLSR_SEED_DEFVAL 
-#undef DDR_PHY_BISTLSR_SEED_SHIFT 
-#undef DDR_PHY_BISTLSR_SEED_MASK 
-#define DDR_PHY_BISTLSR_SEED_DEFVAL                            
+#undef DDR_PHY_BISTLSR_SEED_DEFVAL
+#undef DDR_PHY_BISTLSR_SEED_SHIFT
+#undef DDR_PHY_BISTLSR_SEED_MASK
+#define DDR_PHY_BISTLSR_SEED_DEFVAL
 #define DDR_PHY_BISTLSR_SEED_SHIFT                             0
 #define DDR_PHY_BISTLSR_SEED_MASK                              0xFFFFFFFFU
 
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_RIOCR5_RESERVED_31_16_DEFVAL 
-#undef DDR_PHY_RIOCR5_RESERVED_31_16_SHIFT 
-#undef DDR_PHY_RIOCR5_RESERVED_31_16_MASK 
+#undef DDR_PHY_RIOCR5_RESERVED_31_16_DEFVAL
+#undef DDR_PHY_RIOCR5_RESERVED_31_16_SHIFT
+#undef DDR_PHY_RIOCR5_RESERVED_31_16_MASK
 #define DDR_PHY_RIOCR5_RESERVED_31_16_DEFVAL                   0x00000005
 #define DDR_PHY_RIOCR5_RESERVED_31_16_SHIFT                    16
 #define DDR_PHY_RIOCR5_RESERVED_31_16_MASK                     0xFFFF0000U
@@ -11484,9 +11484,9 @@
 /*
 * Reserved. Return zeros on reads.
 */
-#undef DDR_PHY_RIOCR5_ODTOEMODE_RSVD_DEFVAL 
-#undef DDR_PHY_RIOCR5_ODTOEMODE_RSVD_SHIFT 
-#undef DDR_PHY_RIOCR5_ODTOEMODE_RSVD_MASK 
+#undef DDR_PHY_RIOCR5_ODTOEMODE_RSVD_DEFVAL
+#undef DDR_PHY_RIOCR5_ODTOEMODE_RSVD_SHIFT
+#undef DDR_PHY_RIOCR5_ODTOEMODE_RSVD_MASK
 #define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_DEFVAL                   0x00000005
 #define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_SHIFT                    4
 #define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_MASK                     0x0000FFF0U
@@ -11494,9 +11494,9 @@
 /*
 * SDRAM On-die Termination Output Enable (OE) Mode Selection.
 */
-#undef DDR_PHY_RIOCR5_ODTOEMODE_DEFVAL 
-#undef DDR_PHY_RIOCR5_ODTOEMODE_SHIFT 
-#undef DDR_PHY_RIOCR5_ODTOEMODE_MASK 
+#undef DDR_PHY_RIOCR5_ODTOEMODE_DEFVAL
+#undef DDR_PHY_RIOCR5_ODTOEMODE_SHIFT
+#undef DDR_PHY_RIOCR5_ODTOEMODE_MASK
 #define DDR_PHY_RIOCR5_ODTOEMODE_DEFVAL                        0x00000005
 #define DDR_PHY_RIOCR5_ODTOEMODE_SHIFT                         0
 #define DDR_PHY_RIOCR5_ODTOEMODE_MASK                          0x0000000FU
@@ -11504,9 +11504,9 @@
 /*
 * Address/Command Slew Rate (D3F I/O Only)
 */
-#undef DDR_PHY_ACIOCR0_ACSR_DEFVAL 
-#undef DDR_PHY_ACIOCR0_ACSR_SHIFT 
-#undef DDR_PHY_ACIOCR0_ACSR_MASK 
+#undef DDR_PHY_ACIOCR0_ACSR_DEFVAL
+#undef DDR_PHY_ACIOCR0_ACSR_SHIFT
+#undef DDR_PHY_ACIOCR0_ACSR_MASK
 #define DDR_PHY_ACIOCR0_ACSR_DEFVAL                            0x30000000
 #define DDR_PHY_ACIOCR0_ACSR_SHIFT                             30
 #define DDR_PHY_ACIOCR0_ACSR_MASK                              0xC0000000U
@@ -11514,9 +11514,9 @@
 /*
 * SDRAM Reset I/O Mode
 */
-#undef DDR_PHY_ACIOCR0_RSTIOM_DEFVAL 
-#undef DDR_PHY_ACIOCR0_RSTIOM_SHIFT 
-#undef DDR_PHY_ACIOCR0_RSTIOM_MASK 
+#undef DDR_PHY_ACIOCR0_RSTIOM_DEFVAL
+#undef DDR_PHY_ACIOCR0_RSTIOM_SHIFT
+#undef DDR_PHY_ACIOCR0_RSTIOM_MASK
 #define DDR_PHY_ACIOCR0_RSTIOM_DEFVAL                          0x30000000
 #define DDR_PHY_ACIOCR0_RSTIOM_SHIFT                           29
 #define DDR_PHY_ACIOCR0_RSTIOM_MASK                            0x20000000U
@@ -11524,9 +11524,9 @@
 /*
 * SDRAM Reset Power Down Receiver
 */
-#undef DDR_PHY_ACIOCR0_RSTPDR_DEFVAL 
-#undef DDR_PHY_ACIOCR0_RSTPDR_SHIFT 
-#undef DDR_PHY_ACIOCR0_RSTPDR_MASK 
+#undef DDR_PHY_ACIOCR0_RSTPDR_DEFVAL
+#undef DDR_PHY_ACIOCR0_RSTPDR_SHIFT
+#undef DDR_PHY_ACIOCR0_RSTPDR_MASK
 #define DDR_PHY_ACIOCR0_RSTPDR_DEFVAL                          0x30000000
 #define DDR_PHY_ACIOCR0_RSTPDR_SHIFT                           28
 #define DDR_PHY_ACIOCR0_RSTPDR_MASK                            0x10000000U
@@ -11534,9 +11534,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_ACIOCR0_RESERVED_27_DEFVAL 
-#undef DDR_PHY_ACIOCR0_RESERVED_27_SHIFT 
-#undef DDR_PHY_ACIOCR0_RESERVED_27_MASK 
+#undef DDR_PHY_ACIOCR0_RESERVED_27_DEFVAL
+#undef DDR_PHY_ACIOCR0_RESERVED_27_SHIFT
+#undef DDR_PHY_ACIOCR0_RESERVED_27_MASK
 #define DDR_PHY_ACIOCR0_RESERVED_27_DEFVAL                     0x30000000
 #define DDR_PHY_ACIOCR0_RESERVED_27_SHIFT                      27
 #define DDR_PHY_ACIOCR0_RESERVED_27_MASK                       0x08000000U
@@ -11544,9 +11544,9 @@
 /*
 * SDRAM Reset On-Die Termination
 */
-#undef DDR_PHY_ACIOCR0_RSTODT_DEFVAL 
-#undef DDR_PHY_ACIOCR0_RSTODT_SHIFT 
-#undef DDR_PHY_ACIOCR0_RSTODT_MASK 
+#undef DDR_PHY_ACIOCR0_RSTODT_DEFVAL
+#undef DDR_PHY_ACIOCR0_RSTODT_SHIFT
+#undef DDR_PHY_ACIOCR0_RSTODT_MASK
 #define DDR_PHY_ACIOCR0_RSTODT_DEFVAL                          0x30000000
 #define DDR_PHY_ACIOCR0_RSTODT_SHIFT                           26
 #define DDR_PHY_ACIOCR0_RSTODT_MASK                            0x04000000U
@@ -11554,9 +11554,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_ACIOCR0_RESERVED_25_10_DEFVAL 
-#undef DDR_PHY_ACIOCR0_RESERVED_25_10_SHIFT 
-#undef DDR_PHY_ACIOCR0_RESERVED_25_10_MASK 
+#undef DDR_PHY_ACIOCR0_RESERVED_25_10_DEFVAL
+#undef DDR_PHY_ACIOCR0_RESERVED_25_10_SHIFT
+#undef DDR_PHY_ACIOCR0_RESERVED_25_10_MASK
 #define DDR_PHY_ACIOCR0_RESERVED_25_10_DEFVAL                  0x30000000
 #define DDR_PHY_ACIOCR0_RESERVED_25_10_SHIFT                   10
 #define DDR_PHY_ACIOCR0_RESERVED_25_10_MASK                    0x03FFFC00U
@@ -11564,9 +11564,9 @@
 /*
 * CK Duty Cycle Correction
 */
-#undef DDR_PHY_ACIOCR0_CKDCC_DEFVAL 
-#undef DDR_PHY_ACIOCR0_CKDCC_SHIFT 
-#undef DDR_PHY_ACIOCR0_CKDCC_MASK 
+#undef DDR_PHY_ACIOCR0_CKDCC_DEFVAL
+#undef DDR_PHY_ACIOCR0_CKDCC_SHIFT
+#undef DDR_PHY_ACIOCR0_CKDCC_MASK
 #define DDR_PHY_ACIOCR0_CKDCC_DEFVAL                           0x30000000
 #define DDR_PHY_ACIOCR0_CKDCC_SHIFT                            6
 #define DDR_PHY_ACIOCR0_CKDCC_MASK                             0x000003C0U
@@ -11574,9 +11574,9 @@
 /*
 * AC Power Down Receiver Mode
 */
-#undef DDR_PHY_ACIOCR0_ACPDRMODE_DEFVAL 
-#undef DDR_PHY_ACIOCR0_ACPDRMODE_SHIFT 
-#undef DDR_PHY_ACIOCR0_ACPDRMODE_MASK 
+#undef DDR_PHY_ACIOCR0_ACPDRMODE_DEFVAL
+#undef DDR_PHY_ACIOCR0_ACPDRMODE_SHIFT
+#undef DDR_PHY_ACIOCR0_ACPDRMODE_MASK
 #define DDR_PHY_ACIOCR0_ACPDRMODE_DEFVAL                       0x30000000
 #define DDR_PHY_ACIOCR0_ACPDRMODE_SHIFT                        4
 #define DDR_PHY_ACIOCR0_ACPDRMODE_MASK                         0x00000030U
@@ -11584,9 +11584,9 @@
 /*
 * AC On-die Termination Mode
 */
-#undef DDR_PHY_ACIOCR0_ACODTMODE_DEFVAL 
-#undef DDR_PHY_ACIOCR0_ACODTMODE_SHIFT 
-#undef DDR_PHY_ACIOCR0_ACODTMODE_MASK 
+#undef DDR_PHY_ACIOCR0_ACODTMODE_DEFVAL
+#undef DDR_PHY_ACIOCR0_ACODTMODE_SHIFT
+#undef DDR_PHY_ACIOCR0_ACODTMODE_MASK
 #define DDR_PHY_ACIOCR0_ACODTMODE_DEFVAL                       0x30000000
 #define DDR_PHY_ACIOCR0_ACODTMODE_SHIFT                        2
 #define DDR_PHY_ACIOCR0_ACODTMODE_MASK                         0x0000000CU
@@ -11594,9 +11594,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_ACIOCR0_RESERVED_1_DEFVAL 
-#undef DDR_PHY_ACIOCR0_RESERVED_1_SHIFT 
-#undef DDR_PHY_ACIOCR0_RESERVED_1_MASK 
+#undef DDR_PHY_ACIOCR0_RESERVED_1_DEFVAL
+#undef DDR_PHY_ACIOCR0_RESERVED_1_SHIFT
+#undef DDR_PHY_ACIOCR0_RESERVED_1_MASK
 #define DDR_PHY_ACIOCR0_RESERVED_1_DEFVAL                      0x30000000
 #define DDR_PHY_ACIOCR0_RESERVED_1_SHIFT                       1
 #define DDR_PHY_ACIOCR0_RESERVED_1_MASK                        0x00000002U
@@ -11604,9 +11604,9 @@
 /*
 * Control delayed or non-delayed clock to CS_N/ODT?CKE AC slices.
 */
-#undef DDR_PHY_ACIOCR0_ACRANKCLKSEL_DEFVAL 
-#undef DDR_PHY_ACIOCR0_ACRANKCLKSEL_SHIFT 
-#undef DDR_PHY_ACIOCR0_ACRANKCLKSEL_MASK 
+#undef DDR_PHY_ACIOCR0_ACRANKCLKSEL_DEFVAL
+#undef DDR_PHY_ACIOCR0_ACRANKCLKSEL_SHIFT
+#undef DDR_PHY_ACIOCR0_ACRANKCLKSEL_MASK
 #define DDR_PHY_ACIOCR0_ACRANKCLKSEL_DEFVAL                    0x30000000
 #define DDR_PHY_ACIOCR0_ACRANKCLKSEL_SHIFT                     0
 #define DDR_PHY_ACIOCR0_ACRANKCLKSEL_MASK                      0x00000001U
@@ -11615,9 +11615,9 @@
 * Clock gating for glue logic inside CLKGEN and glue logic inside CONTROL
     * slice
 */
-#undef DDR_PHY_ACIOCR2_CLKGENCLKGATE_DEFVAL 
-#undef DDR_PHY_ACIOCR2_CLKGENCLKGATE_SHIFT 
-#undef DDR_PHY_ACIOCR2_CLKGENCLKGATE_MASK 
+#undef DDR_PHY_ACIOCR2_CLKGENCLKGATE_DEFVAL
+#undef DDR_PHY_ACIOCR2_CLKGENCLKGATE_SHIFT
+#undef DDR_PHY_ACIOCR2_CLKGENCLKGATE_MASK
 #define DDR_PHY_ACIOCR2_CLKGENCLKGATE_DEFVAL                   0x00000000
 #define DDR_PHY_ACIOCR2_CLKGENCLKGATE_SHIFT                    31
 #define DDR_PHY_ACIOCR2_CLKGENCLKGATE_MASK                     0x80000000U
@@ -11625,9 +11625,9 @@
 /*
 * Clock gating for Output Enable D slices [0]
 */
-#undef DDR_PHY_ACIOCR2_ACOECLKGATE0_DEFVAL 
-#undef DDR_PHY_ACIOCR2_ACOECLKGATE0_SHIFT 
-#undef DDR_PHY_ACIOCR2_ACOECLKGATE0_MASK 
+#undef DDR_PHY_ACIOCR2_ACOECLKGATE0_DEFVAL
+#undef DDR_PHY_ACIOCR2_ACOECLKGATE0_SHIFT
+#undef DDR_PHY_ACIOCR2_ACOECLKGATE0_MASK
 #define DDR_PHY_ACIOCR2_ACOECLKGATE0_DEFVAL                    0x00000000
 #define DDR_PHY_ACIOCR2_ACOECLKGATE0_SHIFT                     30
 #define DDR_PHY_ACIOCR2_ACOECLKGATE0_MASK                      0x40000000U
@@ -11635,9 +11635,9 @@
 /*
 * Clock gating for Power Down Receiver D slices [0]
 */
-#undef DDR_PHY_ACIOCR2_ACPDRCLKGATE0_DEFVAL 
-#undef DDR_PHY_ACIOCR2_ACPDRCLKGATE0_SHIFT 
-#undef DDR_PHY_ACIOCR2_ACPDRCLKGATE0_MASK 
+#undef DDR_PHY_ACIOCR2_ACPDRCLKGATE0_DEFVAL
+#undef DDR_PHY_ACIOCR2_ACPDRCLKGATE0_SHIFT
+#undef DDR_PHY_ACIOCR2_ACPDRCLKGATE0_MASK
 #define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_DEFVAL                   0x00000000
 #define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_SHIFT                    29
 #define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_MASK                     0x20000000U
@@ -11645,9 +11645,9 @@
 /*
 * Clock gating for Termination Enable D slices [0]
 */
-#undef DDR_PHY_ACIOCR2_ACTECLKGATE0_DEFVAL 
-#undef DDR_PHY_ACIOCR2_ACTECLKGATE0_SHIFT 
-#undef DDR_PHY_ACIOCR2_ACTECLKGATE0_MASK 
+#undef DDR_PHY_ACIOCR2_ACTECLKGATE0_DEFVAL
+#undef DDR_PHY_ACIOCR2_ACTECLKGATE0_SHIFT
+#undef DDR_PHY_ACIOCR2_ACTECLKGATE0_MASK
 #define DDR_PHY_ACIOCR2_ACTECLKGATE0_DEFVAL                    0x00000000
 #define DDR_PHY_ACIOCR2_ACTECLKGATE0_SHIFT                     28
 #define DDR_PHY_ACIOCR2_ACTECLKGATE0_MASK                      0x10000000U
@@ -11655,9 +11655,9 @@
 /*
 * Clock gating for CK# D slices [1:0]
 */
-#undef DDR_PHY_ACIOCR2_CKNCLKGATE0_DEFVAL 
-#undef DDR_PHY_ACIOCR2_CKNCLKGATE0_SHIFT 
-#undef DDR_PHY_ACIOCR2_CKNCLKGATE0_MASK 
+#undef DDR_PHY_ACIOCR2_CKNCLKGATE0_DEFVAL
+#undef DDR_PHY_ACIOCR2_CKNCLKGATE0_SHIFT
+#undef DDR_PHY_ACIOCR2_CKNCLKGATE0_MASK
 #define DDR_PHY_ACIOCR2_CKNCLKGATE0_DEFVAL                     0x00000000
 #define DDR_PHY_ACIOCR2_CKNCLKGATE0_SHIFT                      26
 #define DDR_PHY_ACIOCR2_CKNCLKGATE0_MASK                       0x0C000000U
@@ -11665,9 +11665,9 @@
 /*
 * Clock gating for CK D slices [1:0]
 */
-#undef DDR_PHY_ACIOCR2_CKCLKGATE0_DEFVAL 
-#undef DDR_PHY_ACIOCR2_CKCLKGATE0_SHIFT 
-#undef DDR_PHY_ACIOCR2_CKCLKGATE0_MASK 
+#undef DDR_PHY_ACIOCR2_CKCLKGATE0_DEFVAL
+#undef DDR_PHY_ACIOCR2_CKCLKGATE0_SHIFT
+#undef DDR_PHY_ACIOCR2_CKCLKGATE0_MASK
 #define DDR_PHY_ACIOCR2_CKCLKGATE0_DEFVAL                      0x00000000
 #define DDR_PHY_ACIOCR2_CKCLKGATE0_SHIFT                       24
 #define DDR_PHY_ACIOCR2_CKCLKGATE0_MASK                        0x03000000U
@@ -11675,9 +11675,9 @@
 /*
 * Clock gating for AC D slices [23:0]
 */
-#undef DDR_PHY_ACIOCR2_ACCLKGATE0_DEFVAL 
-#undef DDR_PHY_ACIOCR2_ACCLKGATE0_SHIFT 
-#undef DDR_PHY_ACIOCR2_ACCLKGATE0_MASK 
+#undef DDR_PHY_ACIOCR2_ACCLKGATE0_DEFVAL
+#undef DDR_PHY_ACIOCR2_ACCLKGATE0_SHIFT
+#undef DDR_PHY_ACIOCR2_ACCLKGATE0_MASK
 #define DDR_PHY_ACIOCR2_ACCLKGATE0_DEFVAL                      0x00000000
 #define DDR_PHY_ACIOCR2_ACCLKGATE0_SHIFT                       0
 #define DDR_PHY_ACIOCR2_ACCLKGATE0_MASK                        0x00FFFFFFU
@@ -11685,9 +11685,9 @@
 /*
 * SDRAM Parity Output Enable (OE) Mode Selection
 */
-#undef DDR_PHY_ACIOCR3_PAROEMODE_DEFVAL 
-#undef DDR_PHY_ACIOCR3_PAROEMODE_SHIFT 
-#undef DDR_PHY_ACIOCR3_PAROEMODE_MASK 
+#undef DDR_PHY_ACIOCR3_PAROEMODE_DEFVAL
+#undef DDR_PHY_ACIOCR3_PAROEMODE_SHIFT
+#undef DDR_PHY_ACIOCR3_PAROEMODE_MASK
 #define DDR_PHY_ACIOCR3_PAROEMODE_DEFVAL                       0x00000005
 #define DDR_PHY_ACIOCR3_PAROEMODE_SHIFT                        30
 #define DDR_PHY_ACIOCR3_PAROEMODE_MASK                         0xC0000000U
@@ -11695,9 +11695,9 @@
 /*
 * SDRAM Bank Group Output Enable (OE) Mode Selection
 */
-#undef DDR_PHY_ACIOCR3_BGOEMODE_DEFVAL 
-#undef DDR_PHY_ACIOCR3_BGOEMODE_SHIFT 
-#undef DDR_PHY_ACIOCR3_BGOEMODE_MASK 
+#undef DDR_PHY_ACIOCR3_BGOEMODE_DEFVAL
+#undef DDR_PHY_ACIOCR3_BGOEMODE_SHIFT
+#undef DDR_PHY_ACIOCR3_BGOEMODE_MASK
 #define DDR_PHY_ACIOCR3_BGOEMODE_DEFVAL                        0x00000005
 #define DDR_PHY_ACIOCR3_BGOEMODE_SHIFT                         26
 #define DDR_PHY_ACIOCR3_BGOEMODE_MASK                          0x3C000000U
@@ -11705,9 +11705,9 @@
 /*
 * SDRAM Bank Address Output Enable (OE) Mode Selection
 */
-#undef DDR_PHY_ACIOCR3_BAOEMODE_DEFVAL 
-#undef DDR_PHY_ACIOCR3_BAOEMODE_SHIFT 
-#undef DDR_PHY_ACIOCR3_BAOEMODE_MASK 
+#undef DDR_PHY_ACIOCR3_BAOEMODE_DEFVAL
+#undef DDR_PHY_ACIOCR3_BAOEMODE_SHIFT
+#undef DDR_PHY_ACIOCR3_BAOEMODE_MASK
 #define DDR_PHY_ACIOCR3_BAOEMODE_DEFVAL                        0x00000005
 #define DDR_PHY_ACIOCR3_BAOEMODE_SHIFT                         22
 #define DDR_PHY_ACIOCR3_BAOEMODE_MASK                          0x03C00000U
@@ -11715,9 +11715,9 @@
 /*
 * SDRAM A[17] Output Enable (OE) Mode Selection
 */
-#undef DDR_PHY_ACIOCR3_A17OEMODE_DEFVAL 
-#undef DDR_PHY_ACIOCR3_A17OEMODE_SHIFT 
-#undef DDR_PHY_ACIOCR3_A17OEMODE_MASK 
+#undef DDR_PHY_ACIOCR3_A17OEMODE_DEFVAL
+#undef DDR_PHY_ACIOCR3_A17OEMODE_SHIFT
+#undef DDR_PHY_ACIOCR3_A17OEMODE_MASK
 #define DDR_PHY_ACIOCR3_A17OEMODE_DEFVAL                       0x00000005
 #define DDR_PHY_ACIOCR3_A17OEMODE_SHIFT                        20
 #define DDR_PHY_ACIOCR3_A17OEMODE_MASK                         0x00300000U
@@ -11725,9 +11725,9 @@
 /*
 * SDRAM A[16] / RAS_n Output Enable (OE) Mode Selection
 */
-#undef DDR_PHY_ACIOCR3_A16OEMODE_DEFVAL 
-#undef DDR_PHY_ACIOCR3_A16OEMODE_SHIFT 
-#undef DDR_PHY_ACIOCR3_A16OEMODE_MASK 
+#undef DDR_PHY_ACIOCR3_A16OEMODE_DEFVAL
+#undef DDR_PHY_ACIOCR3_A16OEMODE_SHIFT
+#undef DDR_PHY_ACIOCR3_A16OEMODE_MASK
 #define DDR_PHY_ACIOCR3_A16OEMODE_DEFVAL                       0x00000005
 #define DDR_PHY_ACIOCR3_A16OEMODE_SHIFT                        18
 #define DDR_PHY_ACIOCR3_A16OEMODE_MASK                         0x000C0000U
@@ -11735,9 +11735,9 @@
 /*
 * SDRAM ACT_n Output Enable (OE) Mode Selection (DDR4 only)
 */
-#undef DDR_PHY_ACIOCR3_ACTOEMODE_DEFVAL 
-#undef DDR_PHY_ACIOCR3_ACTOEMODE_SHIFT 
-#undef DDR_PHY_ACIOCR3_ACTOEMODE_MASK 
+#undef DDR_PHY_ACIOCR3_ACTOEMODE_DEFVAL
+#undef DDR_PHY_ACIOCR3_ACTOEMODE_SHIFT
+#undef DDR_PHY_ACIOCR3_ACTOEMODE_MASK
 #define DDR_PHY_ACIOCR3_ACTOEMODE_DEFVAL                       0x00000005
 #define DDR_PHY_ACIOCR3_ACTOEMODE_SHIFT                        16
 #define DDR_PHY_ACIOCR3_ACTOEMODE_MASK                         0x00030000U
@@ -11745,9 +11745,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_ACIOCR3_RESERVED_15_8_DEFVAL 
-#undef DDR_PHY_ACIOCR3_RESERVED_15_8_SHIFT 
-#undef DDR_PHY_ACIOCR3_RESERVED_15_8_MASK 
+#undef DDR_PHY_ACIOCR3_RESERVED_15_8_DEFVAL
+#undef DDR_PHY_ACIOCR3_RESERVED_15_8_SHIFT
+#undef DDR_PHY_ACIOCR3_RESERVED_15_8_MASK
 #define DDR_PHY_ACIOCR3_RESERVED_15_8_DEFVAL                   0x00000005
 #define DDR_PHY_ACIOCR3_RESERVED_15_8_SHIFT                    8
 #define DDR_PHY_ACIOCR3_RESERVED_15_8_MASK                     0x0000FF00U
@@ -11755,9 +11755,9 @@
 /*
 * Reserved. Return zeros on reads.
 */
-#undef DDR_PHY_ACIOCR3_CKOEMODE_RSVD_DEFVAL 
-#undef DDR_PHY_ACIOCR3_CKOEMODE_RSVD_SHIFT 
-#undef DDR_PHY_ACIOCR3_CKOEMODE_RSVD_MASK 
+#undef DDR_PHY_ACIOCR3_CKOEMODE_RSVD_DEFVAL
+#undef DDR_PHY_ACIOCR3_CKOEMODE_RSVD_SHIFT
+#undef DDR_PHY_ACIOCR3_CKOEMODE_RSVD_MASK
 #define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_DEFVAL                   0x00000005
 #define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_SHIFT                    4
 #define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_MASK                     0x000000F0U
@@ -11765,9 +11765,9 @@
 /*
 * SDRAM CK Output Enable (OE) Mode Selection.
 */
-#undef DDR_PHY_ACIOCR3_CKOEMODE_DEFVAL 
-#undef DDR_PHY_ACIOCR3_CKOEMODE_SHIFT 
-#undef DDR_PHY_ACIOCR3_CKOEMODE_MASK 
+#undef DDR_PHY_ACIOCR3_CKOEMODE_DEFVAL
+#undef DDR_PHY_ACIOCR3_CKOEMODE_SHIFT
+#undef DDR_PHY_ACIOCR3_CKOEMODE_MASK
 #define DDR_PHY_ACIOCR3_CKOEMODE_DEFVAL                        0x00000005
 #define DDR_PHY_ACIOCR3_CKOEMODE_SHIFT                         0
 #define DDR_PHY_ACIOCR3_CKOEMODE_MASK                          0x0000000FU
@@ -11775,9 +11775,9 @@
 /*
 * Clock gating for AC LB slices and loopback read valid slices
 */
-#undef DDR_PHY_ACIOCR4_LBCLKGATE_DEFVAL 
-#undef DDR_PHY_ACIOCR4_LBCLKGATE_SHIFT 
-#undef DDR_PHY_ACIOCR4_LBCLKGATE_MASK 
+#undef DDR_PHY_ACIOCR4_LBCLKGATE_DEFVAL
+#undef DDR_PHY_ACIOCR4_LBCLKGATE_SHIFT
+#undef DDR_PHY_ACIOCR4_LBCLKGATE_MASK
 #define DDR_PHY_ACIOCR4_LBCLKGATE_DEFVAL                       0x00000000
 #define DDR_PHY_ACIOCR4_LBCLKGATE_SHIFT                        31
 #define DDR_PHY_ACIOCR4_LBCLKGATE_MASK                         0x80000000U
@@ -11785,9 +11785,9 @@
 /*
 * Clock gating for Output Enable D slices [1]
 */
-#undef DDR_PHY_ACIOCR4_ACOECLKGATE1_DEFVAL 
-#undef DDR_PHY_ACIOCR4_ACOECLKGATE1_SHIFT 
-#undef DDR_PHY_ACIOCR4_ACOECLKGATE1_MASK 
+#undef DDR_PHY_ACIOCR4_ACOECLKGATE1_DEFVAL
+#undef DDR_PHY_ACIOCR4_ACOECLKGATE1_SHIFT
+#undef DDR_PHY_ACIOCR4_ACOECLKGATE1_MASK
 #define DDR_PHY_ACIOCR4_ACOECLKGATE1_DEFVAL                    0x00000000
 #define DDR_PHY_ACIOCR4_ACOECLKGATE1_SHIFT                     30
 #define DDR_PHY_ACIOCR4_ACOECLKGATE1_MASK                      0x40000000U
@@ -11795,9 +11795,9 @@
 /*
 * Clock gating for Power Down Receiver D slices [1]
 */
-#undef DDR_PHY_ACIOCR4_ACPDRCLKGATE1_DEFVAL 
-#undef DDR_PHY_ACIOCR4_ACPDRCLKGATE1_SHIFT 
-#undef DDR_PHY_ACIOCR4_ACPDRCLKGATE1_MASK 
+#undef DDR_PHY_ACIOCR4_ACPDRCLKGATE1_DEFVAL
+#undef DDR_PHY_ACIOCR4_ACPDRCLKGATE1_SHIFT
+#undef DDR_PHY_ACIOCR4_ACPDRCLKGATE1_MASK
 #define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_DEFVAL                   0x00000000
 #define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_SHIFT                    29
 #define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_MASK                     0x20000000U
@@ -11805,9 +11805,9 @@
 /*
 * Clock gating for Termination Enable D slices [1]
 */
-#undef DDR_PHY_ACIOCR4_ACTECLKGATE1_DEFVAL 
-#undef DDR_PHY_ACIOCR4_ACTECLKGATE1_SHIFT 
-#undef DDR_PHY_ACIOCR4_ACTECLKGATE1_MASK 
+#undef DDR_PHY_ACIOCR4_ACTECLKGATE1_DEFVAL
+#undef DDR_PHY_ACIOCR4_ACTECLKGATE1_SHIFT
+#undef DDR_PHY_ACIOCR4_ACTECLKGATE1_MASK
 #define DDR_PHY_ACIOCR4_ACTECLKGATE1_DEFVAL                    0x00000000
 #define DDR_PHY_ACIOCR4_ACTECLKGATE1_SHIFT                     28
 #define DDR_PHY_ACIOCR4_ACTECLKGATE1_MASK                      0x10000000U
@@ -11815,9 +11815,9 @@
 /*
 * Clock gating for CK# D slices [3:2]
 */
-#undef DDR_PHY_ACIOCR4_CKNCLKGATE1_DEFVAL 
-#undef DDR_PHY_ACIOCR4_CKNCLKGATE1_SHIFT 
-#undef DDR_PHY_ACIOCR4_CKNCLKGATE1_MASK 
+#undef DDR_PHY_ACIOCR4_CKNCLKGATE1_DEFVAL
+#undef DDR_PHY_ACIOCR4_CKNCLKGATE1_SHIFT
+#undef DDR_PHY_ACIOCR4_CKNCLKGATE1_MASK
 #define DDR_PHY_ACIOCR4_CKNCLKGATE1_DEFVAL                     0x00000000
 #define DDR_PHY_ACIOCR4_CKNCLKGATE1_SHIFT                      26
 #define DDR_PHY_ACIOCR4_CKNCLKGATE1_MASK                       0x0C000000U
@@ -11825,9 +11825,9 @@
 /*
 * Clock gating for CK D slices [3:2]
 */
-#undef DDR_PHY_ACIOCR4_CKCLKGATE1_DEFVAL 
-#undef DDR_PHY_ACIOCR4_CKCLKGATE1_SHIFT 
-#undef DDR_PHY_ACIOCR4_CKCLKGATE1_MASK 
+#undef DDR_PHY_ACIOCR4_CKCLKGATE1_DEFVAL
+#undef DDR_PHY_ACIOCR4_CKCLKGATE1_SHIFT
+#undef DDR_PHY_ACIOCR4_CKCLKGATE1_MASK
 #define DDR_PHY_ACIOCR4_CKCLKGATE1_DEFVAL                      0x00000000
 #define DDR_PHY_ACIOCR4_CKCLKGATE1_SHIFT                       24
 #define DDR_PHY_ACIOCR4_CKCLKGATE1_MASK                        0x03000000U
@@ -11835,9 +11835,9 @@
 /*
 * Clock gating for AC D slices [47:24]
 */
-#undef DDR_PHY_ACIOCR4_ACCLKGATE1_DEFVAL 
-#undef DDR_PHY_ACIOCR4_ACCLKGATE1_SHIFT 
-#undef DDR_PHY_ACIOCR4_ACCLKGATE1_MASK 
+#undef DDR_PHY_ACIOCR4_ACCLKGATE1_DEFVAL
+#undef DDR_PHY_ACIOCR4_ACCLKGATE1_SHIFT
+#undef DDR_PHY_ACIOCR4_ACCLKGATE1_MASK
 #define DDR_PHY_ACIOCR4_ACCLKGATE1_DEFVAL                      0x00000000
 #define DDR_PHY_ACIOCR4_ACCLKGATE1_SHIFT                       0
 #define DDR_PHY_ACIOCR4_ACCLKGATE1_MASK                        0x00FFFFFFU
@@ -11845,9 +11845,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_IOVCR0_RESERVED_31_29_DEFVAL 
-#undef DDR_PHY_IOVCR0_RESERVED_31_29_SHIFT 
-#undef DDR_PHY_IOVCR0_RESERVED_31_29_MASK 
+#undef DDR_PHY_IOVCR0_RESERVED_31_29_DEFVAL
+#undef DDR_PHY_IOVCR0_RESERVED_31_29_SHIFT
+#undef DDR_PHY_IOVCR0_RESERVED_31_29_MASK
 #define DDR_PHY_IOVCR0_RESERVED_31_29_DEFVAL                   0x0F000000
 #define DDR_PHY_IOVCR0_RESERVED_31_29_SHIFT                    29
 #define DDR_PHY_IOVCR0_RESERVED_31_29_MASK                     0xE0000000U
@@ -11855,9 +11855,9 @@
 /*
 * Address/command lane VREF Pad Enable
 */
-#undef DDR_PHY_IOVCR0_ACREFPEN_DEFVAL 
-#undef DDR_PHY_IOVCR0_ACREFPEN_SHIFT 
-#undef DDR_PHY_IOVCR0_ACREFPEN_MASK 
+#undef DDR_PHY_IOVCR0_ACREFPEN_DEFVAL
+#undef DDR_PHY_IOVCR0_ACREFPEN_SHIFT
+#undef DDR_PHY_IOVCR0_ACREFPEN_MASK
 #define DDR_PHY_IOVCR0_ACREFPEN_DEFVAL                         0x0F000000
 #define DDR_PHY_IOVCR0_ACREFPEN_SHIFT                          28
 #define DDR_PHY_IOVCR0_ACREFPEN_MASK                           0x10000000U
@@ -11865,9 +11865,9 @@
 /*
 * Address/command lane Internal VREF Enable
 */
-#undef DDR_PHY_IOVCR0_ACREFEEN_DEFVAL 
-#undef DDR_PHY_IOVCR0_ACREFEEN_SHIFT 
-#undef DDR_PHY_IOVCR0_ACREFEEN_MASK 
+#undef DDR_PHY_IOVCR0_ACREFEEN_DEFVAL
+#undef DDR_PHY_IOVCR0_ACREFEEN_SHIFT
+#undef DDR_PHY_IOVCR0_ACREFEEN_MASK
 #define DDR_PHY_IOVCR0_ACREFEEN_DEFVAL                         0x0F000000
 #define DDR_PHY_IOVCR0_ACREFEEN_SHIFT                          26
 #define DDR_PHY_IOVCR0_ACREFEEN_MASK                           0x0C000000U
@@ -11875,9 +11875,9 @@
 /*
 * Address/command lane Single-End VREF Enable
 */
-#undef DDR_PHY_IOVCR0_ACREFSEN_DEFVAL 
-#undef DDR_PHY_IOVCR0_ACREFSEN_SHIFT 
-#undef DDR_PHY_IOVCR0_ACREFSEN_MASK 
+#undef DDR_PHY_IOVCR0_ACREFSEN_DEFVAL
+#undef DDR_PHY_IOVCR0_ACREFSEN_SHIFT
+#undef DDR_PHY_IOVCR0_ACREFSEN_MASK
 #define DDR_PHY_IOVCR0_ACREFSEN_DEFVAL                         0x0F000000
 #define DDR_PHY_IOVCR0_ACREFSEN_SHIFT                          25
 #define DDR_PHY_IOVCR0_ACREFSEN_MASK                           0x02000000U
@@ -11885,9 +11885,9 @@
 /*
 * Address/command lane Internal VREF Enable
 */
-#undef DDR_PHY_IOVCR0_ACREFIEN_DEFVAL 
-#undef DDR_PHY_IOVCR0_ACREFIEN_SHIFT 
-#undef DDR_PHY_IOVCR0_ACREFIEN_MASK 
+#undef DDR_PHY_IOVCR0_ACREFIEN_DEFVAL
+#undef DDR_PHY_IOVCR0_ACREFIEN_SHIFT
+#undef DDR_PHY_IOVCR0_ACREFIEN_MASK
 #define DDR_PHY_IOVCR0_ACREFIEN_DEFVAL                         0x0F000000
 #define DDR_PHY_IOVCR0_ACREFIEN_SHIFT                          24
 #define DDR_PHY_IOVCR0_ACREFIEN_MASK                           0x01000000U
@@ -11895,9 +11895,9 @@
 /*
 * External VREF generato REFSEL range select
 */
-#undef DDR_PHY_IOVCR0_ACREFESELRANGE_DEFVAL 
-#undef DDR_PHY_IOVCR0_ACREFESELRANGE_SHIFT 
-#undef DDR_PHY_IOVCR0_ACREFESELRANGE_MASK 
+#undef DDR_PHY_IOVCR0_ACREFESELRANGE_DEFVAL
+#undef DDR_PHY_IOVCR0_ACREFESELRANGE_SHIFT
+#undef DDR_PHY_IOVCR0_ACREFESELRANGE_MASK
 #define DDR_PHY_IOVCR0_ACREFESELRANGE_DEFVAL                   0x0F000000
 #define DDR_PHY_IOVCR0_ACREFESELRANGE_SHIFT                    23
 #define DDR_PHY_IOVCR0_ACREFESELRANGE_MASK                     0x00800000U
@@ -11905,9 +11905,9 @@
 /*
 * Address/command lane External VREF Select
 */
-#undef DDR_PHY_IOVCR0_ACREFESEL_DEFVAL 
-#undef DDR_PHY_IOVCR0_ACREFESEL_SHIFT 
-#undef DDR_PHY_IOVCR0_ACREFESEL_MASK 
+#undef DDR_PHY_IOVCR0_ACREFESEL_DEFVAL
+#undef DDR_PHY_IOVCR0_ACREFESEL_SHIFT
+#undef DDR_PHY_IOVCR0_ACREFESEL_MASK
 #define DDR_PHY_IOVCR0_ACREFESEL_DEFVAL                        0x0F000000
 #define DDR_PHY_IOVCR0_ACREFESEL_SHIFT                         16
 #define DDR_PHY_IOVCR0_ACREFESEL_MASK                          0x007F0000U
@@ -11915,9 +11915,9 @@
 /*
 * Single ended VREF generator REFSEL range select
 */
-#undef DDR_PHY_IOVCR0_ACREFSSELRANGE_DEFVAL 
-#undef DDR_PHY_IOVCR0_ACREFSSELRANGE_SHIFT 
-#undef DDR_PHY_IOVCR0_ACREFSSELRANGE_MASK 
+#undef DDR_PHY_IOVCR0_ACREFSSELRANGE_DEFVAL
+#undef DDR_PHY_IOVCR0_ACREFSSELRANGE_SHIFT
+#undef DDR_PHY_IOVCR0_ACREFSSELRANGE_MASK
 #define DDR_PHY_IOVCR0_ACREFSSELRANGE_DEFVAL                   0x0F000000
 #define DDR_PHY_IOVCR0_ACREFSSELRANGE_SHIFT                    15
 #define DDR_PHY_IOVCR0_ACREFSSELRANGE_MASK                     0x00008000U
@@ -11925,9 +11925,9 @@
 /*
 * Address/command lane Single-End VREF Select
 */
-#undef DDR_PHY_IOVCR0_ACREFSSEL_DEFVAL 
-#undef DDR_PHY_IOVCR0_ACREFSSEL_SHIFT 
-#undef DDR_PHY_IOVCR0_ACREFSSEL_MASK 
+#undef DDR_PHY_IOVCR0_ACREFSSEL_DEFVAL
+#undef DDR_PHY_IOVCR0_ACREFSSEL_SHIFT
+#undef DDR_PHY_IOVCR0_ACREFSSEL_MASK
 #define DDR_PHY_IOVCR0_ACREFSSEL_DEFVAL                        0x0F000000
 #define DDR_PHY_IOVCR0_ACREFSSEL_SHIFT                         8
 #define DDR_PHY_IOVCR0_ACREFSSEL_MASK                          0x00007F00U
@@ -11935,9 +11935,9 @@
 /*
 * Internal VREF generator REFSEL ragne select
 */
-#undef DDR_PHY_IOVCR0_ACVREFISELRANGE_DEFVAL 
-#undef DDR_PHY_IOVCR0_ACVREFISELRANGE_SHIFT 
-#undef DDR_PHY_IOVCR0_ACVREFISELRANGE_MASK 
+#undef DDR_PHY_IOVCR0_ACVREFISELRANGE_DEFVAL
+#undef DDR_PHY_IOVCR0_ACVREFISELRANGE_SHIFT
+#undef DDR_PHY_IOVCR0_ACVREFISELRANGE_MASK
 #define DDR_PHY_IOVCR0_ACVREFISELRANGE_DEFVAL                  0x0F000000
 #define DDR_PHY_IOVCR0_ACVREFISELRANGE_SHIFT                   7
 #define DDR_PHY_IOVCR0_ACVREFISELRANGE_MASK                    0x00000080U
@@ -11945,9 +11945,9 @@
 /*
 * REFSEL Control for internal AC IOs
 */
-#undef DDR_PHY_IOVCR0_ACVREFISEL_DEFVAL 
-#undef DDR_PHY_IOVCR0_ACVREFISEL_SHIFT 
-#undef DDR_PHY_IOVCR0_ACVREFISEL_MASK 
+#undef DDR_PHY_IOVCR0_ACVREFISEL_DEFVAL
+#undef DDR_PHY_IOVCR0_ACVREFISEL_SHIFT
+#undef DDR_PHY_IOVCR0_ACVREFISEL_MASK
 #define DDR_PHY_IOVCR0_ACVREFISEL_DEFVAL                       0x0F000000
 #define DDR_PHY_IOVCR0_ACVREFISEL_SHIFT                        0
 #define DDR_PHY_IOVCR0_ACVREFISEL_MASK                         0x0000007FU
@@ -11956,9 +11956,9 @@
 * Number of ctl_clk required to meet (> 150ns) timing requirements during
     * DRAM DQ VREF training
 */
-#undef DDR_PHY_VTCR0_TVREF_DEFVAL 
-#undef DDR_PHY_VTCR0_TVREF_SHIFT 
-#undef DDR_PHY_VTCR0_TVREF_MASK 
+#undef DDR_PHY_VTCR0_TVREF_DEFVAL
+#undef DDR_PHY_VTCR0_TVREF_SHIFT
+#undef DDR_PHY_VTCR0_TVREF_MASK
 #define DDR_PHY_VTCR0_TVREF_DEFVAL                             0x70032019
 #define DDR_PHY_VTCR0_TVREF_SHIFT                              29
 #define DDR_PHY_VTCR0_TVREF_MASK                               0xE0000000U
@@ -11966,9 +11966,9 @@
 /*
 * DRM DQ VREF training Enable
 */
-#undef DDR_PHY_VTCR0_DVEN_DEFVAL 
-#undef DDR_PHY_VTCR0_DVEN_SHIFT 
-#undef DDR_PHY_VTCR0_DVEN_MASK 
+#undef DDR_PHY_VTCR0_DVEN_DEFVAL
+#undef DDR_PHY_VTCR0_DVEN_SHIFT
+#undef DDR_PHY_VTCR0_DVEN_MASK
 #define DDR_PHY_VTCR0_DVEN_DEFVAL                              0x70032019
 #define DDR_PHY_VTCR0_DVEN_SHIFT                               28
 #define DDR_PHY_VTCR0_DVEN_MASK                                0x10000000U
@@ -11976,9 +11976,9 @@
 /*
 * Per Device Addressability Enable
 */
-#undef DDR_PHY_VTCR0_PDAEN_DEFVAL 
-#undef DDR_PHY_VTCR0_PDAEN_SHIFT 
-#undef DDR_PHY_VTCR0_PDAEN_MASK 
+#undef DDR_PHY_VTCR0_PDAEN_DEFVAL
+#undef DDR_PHY_VTCR0_PDAEN_SHIFT
+#undef DDR_PHY_VTCR0_PDAEN_MASK
 #define DDR_PHY_VTCR0_PDAEN_DEFVAL                             0x70032019
 #define DDR_PHY_VTCR0_PDAEN_SHIFT                              27
 #define DDR_PHY_VTCR0_PDAEN_MASK                               0x08000000U
@@ -11986,9 +11986,9 @@
 /*
 * Reserved. Returns zeroes on reads.
 */
-#undef DDR_PHY_VTCR0_RESERVED_26_DEFVAL 
-#undef DDR_PHY_VTCR0_RESERVED_26_SHIFT 
-#undef DDR_PHY_VTCR0_RESERVED_26_MASK 
+#undef DDR_PHY_VTCR0_RESERVED_26_DEFVAL
+#undef DDR_PHY_VTCR0_RESERVED_26_SHIFT
+#undef DDR_PHY_VTCR0_RESERVED_26_MASK
 #define DDR_PHY_VTCR0_RESERVED_26_DEFVAL                       0x70032019
 #define DDR_PHY_VTCR0_RESERVED_26_SHIFT                        26
 #define DDR_PHY_VTCR0_RESERVED_26_MASK                         0x04000000U
@@ -11996,9 +11996,9 @@
 /*
 * VREF Word Count
 */
-#undef DDR_PHY_VTCR0_VWCR_DEFVAL 
-#undef DDR_PHY_VTCR0_VWCR_SHIFT 
-#undef DDR_PHY_VTCR0_VWCR_MASK 
+#undef DDR_PHY_VTCR0_VWCR_DEFVAL
+#undef DDR_PHY_VTCR0_VWCR_SHIFT
+#undef DDR_PHY_VTCR0_VWCR_MASK
 #define DDR_PHY_VTCR0_VWCR_DEFVAL                              0x70032019
 #define DDR_PHY_VTCR0_VWCR_SHIFT                               22
 #define DDR_PHY_VTCR0_VWCR_MASK                                0x03C00000U
@@ -12006,9 +12006,9 @@
 /*
 * DRAM DQ VREF step size used during DRAM VREF training
 */
-#undef DDR_PHY_VTCR0_DVSS_DEFVAL 
-#undef DDR_PHY_VTCR0_DVSS_SHIFT 
-#undef DDR_PHY_VTCR0_DVSS_MASK 
+#undef DDR_PHY_VTCR0_DVSS_DEFVAL
+#undef DDR_PHY_VTCR0_DVSS_SHIFT
+#undef DDR_PHY_VTCR0_DVSS_MASK
 #define DDR_PHY_VTCR0_DVSS_DEFVAL                              0x70032019
 #define DDR_PHY_VTCR0_DVSS_SHIFT                               18
 #define DDR_PHY_VTCR0_DVSS_MASK                                0x003C0000U
@@ -12016,9 +12016,9 @@
 /*
 * Maximum VREF limit value used during DRAM VREF training
 */
-#undef DDR_PHY_VTCR0_DVMAX_DEFVAL 
-#undef DDR_PHY_VTCR0_DVMAX_SHIFT 
-#undef DDR_PHY_VTCR0_DVMAX_MASK 
+#undef DDR_PHY_VTCR0_DVMAX_DEFVAL
+#undef DDR_PHY_VTCR0_DVMAX_SHIFT
+#undef DDR_PHY_VTCR0_DVMAX_MASK
 #define DDR_PHY_VTCR0_DVMAX_DEFVAL                             0x70032019
 #define DDR_PHY_VTCR0_DVMAX_SHIFT                              12
 #define DDR_PHY_VTCR0_DVMAX_MASK                               0x0003F000U
@@ -12026,9 +12026,9 @@
 /*
 * Minimum VREF limit value used during DRAM VREF training
 */
-#undef DDR_PHY_VTCR0_DVMIN_DEFVAL 
-#undef DDR_PHY_VTCR0_DVMIN_SHIFT 
-#undef DDR_PHY_VTCR0_DVMIN_MASK 
+#undef DDR_PHY_VTCR0_DVMIN_DEFVAL
+#undef DDR_PHY_VTCR0_DVMIN_SHIFT
+#undef DDR_PHY_VTCR0_DVMIN_MASK
 #define DDR_PHY_VTCR0_DVMIN_DEFVAL                             0x70032019
 #define DDR_PHY_VTCR0_DVMIN_SHIFT                              6
 #define DDR_PHY_VTCR0_DVMIN_MASK                               0x00000FC0U
@@ -12036,9 +12036,9 @@
 /*
 * Initial DRAM DQ VREF value used during DRAM VREF training
 */
-#undef DDR_PHY_VTCR0_DVINIT_DEFVAL 
-#undef DDR_PHY_VTCR0_DVINIT_SHIFT 
-#undef DDR_PHY_VTCR0_DVINIT_MASK 
+#undef DDR_PHY_VTCR0_DVINIT_DEFVAL
+#undef DDR_PHY_VTCR0_DVINIT_SHIFT
+#undef DDR_PHY_VTCR0_DVINIT_MASK
 #define DDR_PHY_VTCR0_DVINIT_DEFVAL                            0x70032019
 #define DDR_PHY_VTCR0_DVINIT_SHIFT                             0
 #define DDR_PHY_VTCR0_DVINIT_MASK                              0x0000003FU
@@ -12047,9 +12047,9 @@
 * Host VREF step size used during VREF training. The register value of N i
     * ndicates step size of (N+1)
 */
-#undef DDR_PHY_VTCR1_HVSS_DEFVAL 
-#undef DDR_PHY_VTCR1_HVSS_SHIFT 
-#undef DDR_PHY_VTCR1_HVSS_MASK 
+#undef DDR_PHY_VTCR1_HVSS_DEFVAL
+#undef DDR_PHY_VTCR1_HVSS_SHIFT
+#undef DDR_PHY_VTCR1_HVSS_MASK
 #define DDR_PHY_VTCR1_HVSS_DEFVAL                              0x07F00072
 #define DDR_PHY_VTCR1_HVSS_SHIFT                               28
 #define DDR_PHY_VTCR1_HVSS_MASK                                0xF0000000U
@@ -12057,9 +12057,9 @@
 /*
 * Reserved. Returns zeroes on reads.
 */
-#undef DDR_PHY_VTCR1_RESERVED_27_DEFVAL 
-#undef DDR_PHY_VTCR1_RESERVED_27_SHIFT 
-#undef DDR_PHY_VTCR1_RESERVED_27_MASK 
+#undef DDR_PHY_VTCR1_RESERVED_27_DEFVAL
+#undef DDR_PHY_VTCR1_RESERVED_27_SHIFT
+#undef DDR_PHY_VTCR1_RESERVED_27_MASK
 #define DDR_PHY_VTCR1_RESERVED_27_DEFVAL                       0x07F00072
 #define DDR_PHY_VTCR1_RESERVED_27_SHIFT                        27
 #define DDR_PHY_VTCR1_RESERVED_27_MASK                         0x08000000U
@@ -12067,9 +12067,9 @@
 /*
 * Maximum VREF limit value used during DRAM VREF training.
 */
-#undef DDR_PHY_VTCR1_HVMAX_DEFVAL 
-#undef DDR_PHY_VTCR1_HVMAX_SHIFT 
-#undef DDR_PHY_VTCR1_HVMAX_MASK 
+#undef DDR_PHY_VTCR1_HVMAX_DEFVAL
+#undef DDR_PHY_VTCR1_HVMAX_SHIFT
+#undef DDR_PHY_VTCR1_HVMAX_MASK
 #define DDR_PHY_VTCR1_HVMAX_DEFVAL                             0x07F00072
 #define DDR_PHY_VTCR1_HVMAX_SHIFT                              20
 #define DDR_PHY_VTCR1_HVMAX_MASK                               0x07F00000U
@@ -12077,9 +12077,9 @@
 /*
 * Reserved. Returns zeroes on reads.
 */
-#undef DDR_PHY_VTCR1_RESERVED_19_DEFVAL 
-#undef DDR_PHY_VTCR1_RESERVED_19_SHIFT 
-#undef DDR_PHY_VTCR1_RESERVED_19_MASK 
+#undef DDR_PHY_VTCR1_RESERVED_19_DEFVAL
+#undef DDR_PHY_VTCR1_RESERVED_19_SHIFT
+#undef DDR_PHY_VTCR1_RESERVED_19_MASK
 #define DDR_PHY_VTCR1_RESERVED_19_DEFVAL                       0x07F00072
 #define DDR_PHY_VTCR1_RESERVED_19_SHIFT                        19
 #define DDR_PHY_VTCR1_RESERVED_19_MASK                         0x00080000U
@@ -12087,9 +12087,9 @@
 /*
 * Minimum VREF limit value used during DRAM VREF training.
 */
-#undef DDR_PHY_VTCR1_HVMIN_DEFVAL 
-#undef DDR_PHY_VTCR1_HVMIN_SHIFT 
-#undef DDR_PHY_VTCR1_HVMIN_MASK 
+#undef DDR_PHY_VTCR1_HVMIN_DEFVAL
+#undef DDR_PHY_VTCR1_HVMIN_SHIFT
+#undef DDR_PHY_VTCR1_HVMIN_MASK
 #define DDR_PHY_VTCR1_HVMIN_DEFVAL                             0x07F00072
 #define DDR_PHY_VTCR1_HVMIN_SHIFT                              12
 #define DDR_PHY_VTCR1_HVMIN_MASK                               0x0007F000U
@@ -12097,9 +12097,9 @@
 /*
 * Reserved. Returns zeroes on reads.
 */
-#undef DDR_PHY_VTCR1_RESERVED_11_DEFVAL 
-#undef DDR_PHY_VTCR1_RESERVED_11_SHIFT 
-#undef DDR_PHY_VTCR1_RESERVED_11_MASK 
+#undef DDR_PHY_VTCR1_RESERVED_11_DEFVAL
+#undef DDR_PHY_VTCR1_RESERVED_11_SHIFT
+#undef DDR_PHY_VTCR1_RESERVED_11_MASK
 #define DDR_PHY_VTCR1_RESERVED_11_DEFVAL                       0x07F00072
 #define DDR_PHY_VTCR1_RESERVED_11_SHIFT                        11
 #define DDR_PHY_VTCR1_RESERVED_11_MASK                         0x00000800U
@@ -12107,9 +12107,9 @@
 /*
 * Static Host Vref Rank Value
 */
-#undef DDR_PHY_VTCR1_SHRNK_DEFVAL 
-#undef DDR_PHY_VTCR1_SHRNK_SHIFT 
-#undef DDR_PHY_VTCR1_SHRNK_MASK 
+#undef DDR_PHY_VTCR1_SHRNK_DEFVAL
+#undef DDR_PHY_VTCR1_SHRNK_SHIFT
+#undef DDR_PHY_VTCR1_SHRNK_MASK
 #define DDR_PHY_VTCR1_SHRNK_DEFVAL                             0x07F00072
 #define DDR_PHY_VTCR1_SHRNK_SHIFT                              9
 #define DDR_PHY_VTCR1_SHRNK_MASK                               0x00000600U
@@ -12117,9 +12117,9 @@
 /*
 * Static Host Vref Rank Enable
 */
-#undef DDR_PHY_VTCR1_SHREN_DEFVAL 
-#undef DDR_PHY_VTCR1_SHREN_SHIFT 
-#undef DDR_PHY_VTCR1_SHREN_MASK 
+#undef DDR_PHY_VTCR1_SHREN_DEFVAL
+#undef DDR_PHY_VTCR1_SHREN_SHIFT
+#undef DDR_PHY_VTCR1_SHREN_MASK
 #define DDR_PHY_VTCR1_SHREN_DEFVAL                             0x07F00072
 #define DDR_PHY_VTCR1_SHREN_SHIFT                              8
 #define DDR_PHY_VTCR1_SHREN_MASK                               0x00000100U
@@ -12128,9 +12128,9 @@
 * Number of ctl_clk required to meet (> 200ns) VREF Settling timing requir
     * ements during Host IO VREF training
 */
-#undef DDR_PHY_VTCR1_TVREFIO_DEFVAL 
-#undef DDR_PHY_VTCR1_TVREFIO_SHIFT 
-#undef DDR_PHY_VTCR1_TVREFIO_MASK 
+#undef DDR_PHY_VTCR1_TVREFIO_DEFVAL
+#undef DDR_PHY_VTCR1_TVREFIO_SHIFT
+#undef DDR_PHY_VTCR1_TVREFIO_MASK
 #define DDR_PHY_VTCR1_TVREFIO_DEFVAL                           0x07F00072
 #define DDR_PHY_VTCR1_TVREFIO_SHIFT                            5
 #define DDR_PHY_VTCR1_TVREFIO_MASK                             0x000000E0U
@@ -12138,9 +12138,9 @@
 /*
 * Eye LCDL Offset value for VREF training
 */
-#undef DDR_PHY_VTCR1_EOFF_DEFVAL 
-#undef DDR_PHY_VTCR1_EOFF_SHIFT 
-#undef DDR_PHY_VTCR1_EOFF_MASK 
+#undef DDR_PHY_VTCR1_EOFF_DEFVAL
+#undef DDR_PHY_VTCR1_EOFF_SHIFT
+#undef DDR_PHY_VTCR1_EOFF_MASK
 #define DDR_PHY_VTCR1_EOFF_DEFVAL                              0x07F00072
 #define DDR_PHY_VTCR1_EOFF_SHIFT                               3
 #define DDR_PHY_VTCR1_EOFF_MASK                                0x00000018U
@@ -12148,9 +12148,9 @@
 /*
 * Number of LCDL Eye points for which VREF training is repeated
 */
-#undef DDR_PHY_VTCR1_ENUM_DEFVAL 
-#undef DDR_PHY_VTCR1_ENUM_SHIFT 
-#undef DDR_PHY_VTCR1_ENUM_MASK 
+#undef DDR_PHY_VTCR1_ENUM_DEFVAL
+#undef DDR_PHY_VTCR1_ENUM_SHIFT
+#undef DDR_PHY_VTCR1_ENUM_MASK
 #define DDR_PHY_VTCR1_ENUM_DEFVAL                              0x07F00072
 #define DDR_PHY_VTCR1_ENUM_SHIFT                               2
 #define DDR_PHY_VTCR1_ENUM_MASK                                0x00000004U
@@ -12158,9 +12158,9 @@
 /*
 * HOST (IO) internal VREF training Enable
 */
-#undef DDR_PHY_VTCR1_HVEN_DEFVAL 
-#undef DDR_PHY_VTCR1_HVEN_SHIFT 
-#undef DDR_PHY_VTCR1_HVEN_MASK 
+#undef DDR_PHY_VTCR1_HVEN_DEFVAL
+#undef DDR_PHY_VTCR1_HVEN_SHIFT
+#undef DDR_PHY_VTCR1_HVEN_MASK
 #define DDR_PHY_VTCR1_HVEN_DEFVAL                              0x07F00072
 #define DDR_PHY_VTCR1_HVEN_SHIFT                               1
 #define DDR_PHY_VTCR1_HVEN_MASK                                0x00000002U
@@ -12168,9 +12168,9 @@
 /*
 * Host IO Type Control
 */
-#undef DDR_PHY_VTCR1_HVIO_DEFVAL 
-#undef DDR_PHY_VTCR1_HVIO_SHIFT 
-#undef DDR_PHY_VTCR1_HVIO_MASK 
+#undef DDR_PHY_VTCR1_HVIO_DEFVAL
+#undef DDR_PHY_VTCR1_HVIO_SHIFT
+#undef DDR_PHY_VTCR1_HVIO_MASK
 #define DDR_PHY_VTCR1_HVIO_DEFVAL                              0x07F00072
 #define DDR_PHY_VTCR1_HVIO_SHIFT                               0
 #define DDR_PHY_VTCR1_HVIO_MASK                                0x00000001U
@@ -12178,9 +12178,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_ACBDLR1_RESERVED_31_30_DEFVAL 
-#undef DDR_PHY_ACBDLR1_RESERVED_31_30_SHIFT 
-#undef DDR_PHY_ACBDLR1_RESERVED_31_30_MASK 
+#undef DDR_PHY_ACBDLR1_RESERVED_31_30_DEFVAL
+#undef DDR_PHY_ACBDLR1_RESERVED_31_30_SHIFT
+#undef DDR_PHY_ACBDLR1_RESERVED_31_30_MASK
 #define DDR_PHY_ACBDLR1_RESERVED_31_30_DEFVAL                  0x00000000
 #define DDR_PHY_ACBDLR1_RESERVED_31_30_SHIFT                   30
 #define DDR_PHY_ACBDLR1_RESERVED_31_30_MASK                    0xC0000000U
@@ -12188,9 +12188,9 @@
 /*
 * Delay select for the BDL on Parity.
 */
-#undef DDR_PHY_ACBDLR1_PARBD_DEFVAL 
-#undef DDR_PHY_ACBDLR1_PARBD_SHIFT 
-#undef DDR_PHY_ACBDLR1_PARBD_MASK 
+#undef DDR_PHY_ACBDLR1_PARBD_DEFVAL
+#undef DDR_PHY_ACBDLR1_PARBD_SHIFT
+#undef DDR_PHY_ACBDLR1_PARBD_MASK
 #define DDR_PHY_ACBDLR1_PARBD_DEFVAL                           0x00000000
 #define DDR_PHY_ACBDLR1_PARBD_SHIFT                            24
 #define DDR_PHY_ACBDLR1_PARBD_MASK                             0x3F000000U
@@ -12198,9 +12198,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_ACBDLR1_RESERVED_23_22_DEFVAL 
-#undef DDR_PHY_ACBDLR1_RESERVED_23_22_SHIFT 
-#undef DDR_PHY_ACBDLR1_RESERVED_23_22_MASK 
+#undef DDR_PHY_ACBDLR1_RESERVED_23_22_DEFVAL
+#undef DDR_PHY_ACBDLR1_RESERVED_23_22_SHIFT
+#undef DDR_PHY_ACBDLR1_RESERVED_23_22_MASK
 #define DDR_PHY_ACBDLR1_RESERVED_23_22_DEFVAL                  0x00000000
 #define DDR_PHY_ACBDLR1_RESERVED_23_22_SHIFT                   22
 #define DDR_PHY_ACBDLR1_RESERVED_23_22_MASK                    0x00C00000U
@@ -12209,9 +12209,9 @@
 * Delay select for the BDL on Address A[16]. In DDR3 mode this pin is conn
     * ected to WE.
 */
-#undef DDR_PHY_ACBDLR1_A16BD_DEFVAL 
-#undef DDR_PHY_ACBDLR1_A16BD_SHIFT 
-#undef DDR_PHY_ACBDLR1_A16BD_MASK 
+#undef DDR_PHY_ACBDLR1_A16BD_DEFVAL
+#undef DDR_PHY_ACBDLR1_A16BD_SHIFT
+#undef DDR_PHY_ACBDLR1_A16BD_MASK
 #define DDR_PHY_ACBDLR1_A16BD_DEFVAL                           0x00000000
 #define DDR_PHY_ACBDLR1_A16BD_SHIFT                            16
 #define DDR_PHY_ACBDLR1_A16BD_MASK                             0x003F0000U
@@ -12219,9 +12219,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_ACBDLR1_RESERVED_15_14_DEFVAL 
-#undef DDR_PHY_ACBDLR1_RESERVED_15_14_SHIFT 
-#undef DDR_PHY_ACBDLR1_RESERVED_15_14_MASK 
+#undef DDR_PHY_ACBDLR1_RESERVED_15_14_DEFVAL
+#undef DDR_PHY_ACBDLR1_RESERVED_15_14_SHIFT
+#undef DDR_PHY_ACBDLR1_RESERVED_15_14_MASK
 #define DDR_PHY_ACBDLR1_RESERVED_15_14_DEFVAL                  0x00000000
 #define DDR_PHY_ACBDLR1_RESERVED_15_14_SHIFT                   14
 #define DDR_PHY_ACBDLR1_RESERVED_15_14_MASK                    0x0000C000U
@@ -12230,9 +12230,9 @@
 * Delay select for the BDL on Address A[17]. When not in DDR4 modemode thi
     * s pin is connected to CAS.
 */
-#undef DDR_PHY_ACBDLR1_A17BD_DEFVAL 
-#undef DDR_PHY_ACBDLR1_A17BD_SHIFT 
-#undef DDR_PHY_ACBDLR1_A17BD_MASK 
+#undef DDR_PHY_ACBDLR1_A17BD_DEFVAL
+#undef DDR_PHY_ACBDLR1_A17BD_SHIFT
+#undef DDR_PHY_ACBDLR1_A17BD_MASK
 #define DDR_PHY_ACBDLR1_A17BD_DEFVAL                           0x00000000
 #define DDR_PHY_ACBDLR1_A17BD_SHIFT                            8
 #define DDR_PHY_ACBDLR1_A17BD_MASK                             0x00003F00U
@@ -12240,9 +12240,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_ACBDLR1_RESERVED_7_6_DEFVAL 
-#undef DDR_PHY_ACBDLR1_RESERVED_7_6_SHIFT 
-#undef DDR_PHY_ACBDLR1_RESERVED_7_6_MASK 
+#undef DDR_PHY_ACBDLR1_RESERVED_7_6_DEFVAL
+#undef DDR_PHY_ACBDLR1_RESERVED_7_6_SHIFT
+#undef DDR_PHY_ACBDLR1_RESERVED_7_6_MASK
 #define DDR_PHY_ACBDLR1_RESERVED_7_6_DEFVAL                    0x00000000
 #define DDR_PHY_ACBDLR1_RESERVED_7_6_SHIFT                     6
 #define DDR_PHY_ACBDLR1_RESERVED_7_6_MASK                      0x000000C0U
@@ -12250,9 +12250,9 @@
 /*
 * Delay select for the BDL on ACTN.
 */
-#undef DDR_PHY_ACBDLR1_ACTBD_DEFVAL 
-#undef DDR_PHY_ACBDLR1_ACTBD_SHIFT 
-#undef DDR_PHY_ACBDLR1_ACTBD_MASK 
+#undef DDR_PHY_ACBDLR1_ACTBD_DEFVAL
+#undef DDR_PHY_ACBDLR1_ACTBD_SHIFT
+#undef DDR_PHY_ACBDLR1_ACTBD_MASK
 #define DDR_PHY_ACBDLR1_ACTBD_DEFVAL                           0x00000000
 #define DDR_PHY_ACBDLR1_ACTBD_SHIFT                            0
 #define DDR_PHY_ACBDLR1_ACTBD_MASK                             0x0000003FU
@@ -12260,9 +12260,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_ACBDLR2_RESERVED_31_30_DEFVAL 
-#undef DDR_PHY_ACBDLR2_RESERVED_31_30_SHIFT 
-#undef DDR_PHY_ACBDLR2_RESERVED_31_30_MASK 
+#undef DDR_PHY_ACBDLR2_RESERVED_31_30_DEFVAL
+#undef DDR_PHY_ACBDLR2_RESERVED_31_30_SHIFT
+#undef DDR_PHY_ACBDLR2_RESERVED_31_30_MASK
 #define DDR_PHY_ACBDLR2_RESERVED_31_30_DEFVAL                  0x00000000
 #define DDR_PHY_ACBDLR2_RESERVED_31_30_SHIFT                   30
 #define DDR_PHY_ACBDLR2_RESERVED_31_30_MASK                    0xC0000000U
@@ -12270,9 +12270,9 @@
 /*
 * Delay select for the BDL on BG[1].
 */
-#undef DDR_PHY_ACBDLR2_BG1BD_DEFVAL 
-#undef DDR_PHY_ACBDLR2_BG1BD_SHIFT 
-#undef DDR_PHY_ACBDLR2_BG1BD_MASK 
+#undef DDR_PHY_ACBDLR2_BG1BD_DEFVAL
+#undef DDR_PHY_ACBDLR2_BG1BD_SHIFT
+#undef DDR_PHY_ACBDLR2_BG1BD_MASK
 #define DDR_PHY_ACBDLR2_BG1BD_DEFVAL                           0x00000000
 #define DDR_PHY_ACBDLR2_BG1BD_SHIFT                            24
 #define DDR_PHY_ACBDLR2_BG1BD_MASK                             0x3F000000U
@@ -12280,9 +12280,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_ACBDLR2_RESERVED_23_22_DEFVAL 
-#undef DDR_PHY_ACBDLR2_RESERVED_23_22_SHIFT 
-#undef DDR_PHY_ACBDLR2_RESERVED_23_22_MASK 
+#undef DDR_PHY_ACBDLR2_RESERVED_23_22_DEFVAL
+#undef DDR_PHY_ACBDLR2_RESERVED_23_22_SHIFT
+#undef DDR_PHY_ACBDLR2_RESERVED_23_22_MASK
 #define DDR_PHY_ACBDLR2_RESERVED_23_22_DEFVAL                  0x00000000
 #define DDR_PHY_ACBDLR2_RESERVED_23_22_SHIFT                   22
 #define DDR_PHY_ACBDLR2_RESERVED_23_22_MASK                    0x00C00000U
@@ -12290,9 +12290,9 @@
 /*
 * Delay select for the BDL on BG[0].
 */
-#undef DDR_PHY_ACBDLR2_BG0BD_DEFVAL 
-#undef DDR_PHY_ACBDLR2_BG0BD_SHIFT 
-#undef DDR_PHY_ACBDLR2_BG0BD_MASK 
+#undef DDR_PHY_ACBDLR2_BG0BD_DEFVAL
+#undef DDR_PHY_ACBDLR2_BG0BD_SHIFT
+#undef DDR_PHY_ACBDLR2_BG0BD_MASK
 #define DDR_PHY_ACBDLR2_BG0BD_DEFVAL                           0x00000000
 #define DDR_PHY_ACBDLR2_BG0BD_SHIFT                            16
 #define DDR_PHY_ACBDLR2_BG0BD_MASK                             0x003F0000U
@@ -12300,9 +12300,9 @@
 /*
 * Reser.ved Return zeroes on reads.
 */
-#undef DDR_PHY_ACBDLR2_RESERVED_15_14_DEFVAL 
-#undef DDR_PHY_ACBDLR2_RESERVED_15_14_SHIFT 
-#undef DDR_PHY_ACBDLR2_RESERVED_15_14_MASK 
+#undef DDR_PHY_ACBDLR2_RESERVED_15_14_DEFVAL
+#undef DDR_PHY_ACBDLR2_RESERVED_15_14_SHIFT
+#undef DDR_PHY_ACBDLR2_RESERVED_15_14_MASK
 #define DDR_PHY_ACBDLR2_RESERVED_15_14_DEFVAL                  0x00000000
 #define DDR_PHY_ACBDLR2_RESERVED_15_14_SHIFT                   14
 #define DDR_PHY_ACBDLR2_RESERVED_15_14_MASK                    0x0000C000U
@@ -12310,9 +12310,9 @@
 /*
 * Delay select for the BDL on BA[1].
 */
-#undef DDR_PHY_ACBDLR2_BA1BD_DEFVAL 
-#undef DDR_PHY_ACBDLR2_BA1BD_SHIFT 
-#undef DDR_PHY_ACBDLR2_BA1BD_MASK 
+#undef DDR_PHY_ACBDLR2_BA1BD_DEFVAL
+#undef DDR_PHY_ACBDLR2_BA1BD_SHIFT
+#undef DDR_PHY_ACBDLR2_BA1BD_MASK
 #define DDR_PHY_ACBDLR2_BA1BD_DEFVAL                           0x00000000
 #define DDR_PHY_ACBDLR2_BA1BD_SHIFT                            8
 #define DDR_PHY_ACBDLR2_BA1BD_MASK                             0x00003F00U
@@ -12320,9 +12320,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_ACBDLR2_RESERVED_7_6_DEFVAL 
-#undef DDR_PHY_ACBDLR2_RESERVED_7_6_SHIFT 
-#undef DDR_PHY_ACBDLR2_RESERVED_7_6_MASK 
+#undef DDR_PHY_ACBDLR2_RESERVED_7_6_DEFVAL
+#undef DDR_PHY_ACBDLR2_RESERVED_7_6_SHIFT
+#undef DDR_PHY_ACBDLR2_RESERVED_7_6_MASK
 #define DDR_PHY_ACBDLR2_RESERVED_7_6_DEFVAL                    0x00000000
 #define DDR_PHY_ACBDLR2_RESERVED_7_6_SHIFT                     6
 #define DDR_PHY_ACBDLR2_RESERVED_7_6_MASK                      0x000000C0U
@@ -12330,9 +12330,9 @@
 /*
 * Delay select for the BDL on BA[0].
 */
-#undef DDR_PHY_ACBDLR2_BA0BD_DEFVAL 
-#undef DDR_PHY_ACBDLR2_BA0BD_SHIFT 
-#undef DDR_PHY_ACBDLR2_BA0BD_MASK 
+#undef DDR_PHY_ACBDLR2_BA0BD_DEFVAL
+#undef DDR_PHY_ACBDLR2_BA0BD_SHIFT
+#undef DDR_PHY_ACBDLR2_BA0BD_MASK
 #define DDR_PHY_ACBDLR2_BA0BD_DEFVAL                           0x00000000
 #define DDR_PHY_ACBDLR2_BA0BD_SHIFT                            0
 #define DDR_PHY_ACBDLR2_BA0BD_MASK                             0x0000003FU
@@ -12340,9 +12340,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_ACBDLR6_RESERVED_31_30_DEFVAL 
-#undef DDR_PHY_ACBDLR6_RESERVED_31_30_SHIFT 
-#undef DDR_PHY_ACBDLR6_RESERVED_31_30_MASK 
+#undef DDR_PHY_ACBDLR6_RESERVED_31_30_DEFVAL
+#undef DDR_PHY_ACBDLR6_RESERVED_31_30_SHIFT
+#undef DDR_PHY_ACBDLR6_RESERVED_31_30_MASK
 #define DDR_PHY_ACBDLR6_RESERVED_31_30_DEFVAL                  0x00000000
 #define DDR_PHY_ACBDLR6_RESERVED_31_30_SHIFT                   30
 #define DDR_PHY_ACBDLR6_RESERVED_31_30_MASK                    0xC0000000U
@@ -12350,9 +12350,9 @@
 /*
 * Delay select for the BDL on Address A[3].
 */
-#undef DDR_PHY_ACBDLR6_A03BD_DEFVAL 
-#undef DDR_PHY_ACBDLR6_A03BD_SHIFT 
-#undef DDR_PHY_ACBDLR6_A03BD_MASK 
+#undef DDR_PHY_ACBDLR6_A03BD_DEFVAL
+#undef DDR_PHY_ACBDLR6_A03BD_SHIFT
+#undef DDR_PHY_ACBDLR6_A03BD_MASK
 #define DDR_PHY_ACBDLR6_A03BD_DEFVAL                           0x00000000
 #define DDR_PHY_ACBDLR6_A03BD_SHIFT                            24
 #define DDR_PHY_ACBDLR6_A03BD_MASK                             0x3F000000U
@@ -12360,9 +12360,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_ACBDLR6_RESERVED_23_22_DEFVAL 
-#undef DDR_PHY_ACBDLR6_RESERVED_23_22_SHIFT 
-#undef DDR_PHY_ACBDLR6_RESERVED_23_22_MASK 
+#undef DDR_PHY_ACBDLR6_RESERVED_23_22_DEFVAL
+#undef DDR_PHY_ACBDLR6_RESERVED_23_22_SHIFT
+#undef DDR_PHY_ACBDLR6_RESERVED_23_22_MASK
 #define DDR_PHY_ACBDLR6_RESERVED_23_22_DEFVAL                  0x00000000
 #define DDR_PHY_ACBDLR6_RESERVED_23_22_SHIFT                   22
 #define DDR_PHY_ACBDLR6_RESERVED_23_22_MASK                    0x00C00000U
@@ -12370,9 +12370,9 @@
 /*
 * Delay select for the BDL on Address A[2].
 */
-#undef DDR_PHY_ACBDLR6_A02BD_DEFVAL 
-#undef DDR_PHY_ACBDLR6_A02BD_SHIFT 
-#undef DDR_PHY_ACBDLR6_A02BD_MASK 
+#undef DDR_PHY_ACBDLR6_A02BD_DEFVAL
+#undef DDR_PHY_ACBDLR6_A02BD_SHIFT
+#undef DDR_PHY_ACBDLR6_A02BD_MASK
 #define DDR_PHY_ACBDLR6_A02BD_DEFVAL                           0x00000000
 #define DDR_PHY_ACBDLR6_A02BD_SHIFT                            16
 #define DDR_PHY_ACBDLR6_A02BD_MASK                             0x003F0000U
@@ -12380,9 +12380,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_ACBDLR6_RESERVED_15_14_DEFVAL 
-#undef DDR_PHY_ACBDLR6_RESERVED_15_14_SHIFT 
-#undef DDR_PHY_ACBDLR6_RESERVED_15_14_MASK 
+#undef DDR_PHY_ACBDLR6_RESERVED_15_14_DEFVAL
+#undef DDR_PHY_ACBDLR6_RESERVED_15_14_SHIFT
+#undef DDR_PHY_ACBDLR6_RESERVED_15_14_MASK
 #define DDR_PHY_ACBDLR6_RESERVED_15_14_DEFVAL                  0x00000000
 #define DDR_PHY_ACBDLR6_RESERVED_15_14_SHIFT                   14
 #define DDR_PHY_ACBDLR6_RESERVED_15_14_MASK                    0x0000C000U
@@ -12390,9 +12390,9 @@
 /*
 * Delay select for the BDL on Address A[1].
 */
-#undef DDR_PHY_ACBDLR6_A01BD_DEFVAL 
-#undef DDR_PHY_ACBDLR6_A01BD_SHIFT 
-#undef DDR_PHY_ACBDLR6_A01BD_MASK 
+#undef DDR_PHY_ACBDLR6_A01BD_DEFVAL
+#undef DDR_PHY_ACBDLR6_A01BD_SHIFT
+#undef DDR_PHY_ACBDLR6_A01BD_MASK
 #define DDR_PHY_ACBDLR6_A01BD_DEFVAL                           0x00000000
 #define DDR_PHY_ACBDLR6_A01BD_SHIFT                            8
 #define DDR_PHY_ACBDLR6_A01BD_MASK                             0x00003F00U
@@ -12400,9 +12400,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_ACBDLR6_RESERVED_7_6_DEFVAL 
-#undef DDR_PHY_ACBDLR6_RESERVED_7_6_SHIFT 
-#undef DDR_PHY_ACBDLR6_RESERVED_7_6_MASK 
+#undef DDR_PHY_ACBDLR6_RESERVED_7_6_DEFVAL
+#undef DDR_PHY_ACBDLR6_RESERVED_7_6_SHIFT
+#undef DDR_PHY_ACBDLR6_RESERVED_7_6_MASK
 #define DDR_PHY_ACBDLR6_RESERVED_7_6_DEFVAL                    0x00000000
 #define DDR_PHY_ACBDLR6_RESERVED_7_6_SHIFT                     6
 #define DDR_PHY_ACBDLR6_RESERVED_7_6_MASK                      0x000000C0U
@@ -12410,9 +12410,9 @@
 /*
 * Delay select for the BDL on Address A[0].
 */
-#undef DDR_PHY_ACBDLR6_A00BD_DEFVAL 
-#undef DDR_PHY_ACBDLR6_A00BD_SHIFT 
-#undef DDR_PHY_ACBDLR6_A00BD_MASK 
+#undef DDR_PHY_ACBDLR6_A00BD_DEFVAL
+#undef DDR_PHY_ACBDLR6_A00BD_SHIFT
+#undef DDR_PHY_ACBDLR6_A00BD_MASK
 #define DDR_PHY_ACBDLR6_A00BD_DEFVAL                           0x00000000
 #define DDR_PHY_ACBDLR6_A00BD_SHIFT                            0
 #define DDR_PHY_ACBDLR6_A00BD_MASK                             0x0000003FU
@@ -12420,9 +12420,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_ACBDLR7_RESERVED_31_30_DEFVAL 
-#undef DDR_PHY_ACBDLR7_RESERVED_31_30_SHIFT 
-#undef DDR_PHY_ACBDLR7_RESERVED_31_30_MASK 
+#undef DDR_PHY_ACBDLR7_RESERVED_31_30_DEFVAL
+#undef DDR_PHY_ACBDLR7_RESERVED_31_30_SHIFT
+#undef DDR_PHY_ACBDLR7_RESERVED_31_30_MASK
 #define DDR_PHY_ACBDLR7_RESERVED_31_30_DEFVAL                  0x00000000
 #define DDR_PHY_ACBDLR7_RESERVED_31_30_SHIFT                   30
 #define DDR_PHY_ACBDLR7_RESERVED_31_30_MASK                    0xC0000000U
@@ -12430,9 +12430,9 @@
 /*
 * Delay select for the BDL on Address A[7].
 */
-#undef DDR_PHY_ACBDLR7_A07BD_DEFVAL 
-#undef DDR_PHY_ACBDLR7_A07BD_SHIFT 
-#undef DDR_PHY_ACBDLR7_A07BD_MASK 
+#undef DDR_PHY_ACBDLR7_A07BD_DEFVAL
+#undef DDR_PHY_ACBDLR7_A07BD_SHIFT
+#undef DDR_PHY_ACBDLR7_A07BD_MASK
 #define DDR_PHY_ACBDLR7_A07BD_DEFVAL                           0x00000000
 #define DDR_PHY_ACBDLR7_A07BD_SHIFT                            24
 #define DDR_PHY_ACBDLR7_A07BD_MASK                             0x3F000000U
@@ -12440,9 +12440,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_ACBDLR7_RESERVED_23_22_DEFVAL 
-#undef DDR_PHY_ACBDLR7_RESERVED_23_22_SHIFT 
-#undef DDR_PHY_ACBDLR7_RESERVED_23_22_MASK 
+#undef DDR_PHY_ACBDLR7_RESERVED_23_22_DEFVAL
+#undef DDR_PHY_ACBDLR7_RESERVED_23_22_SHIFT
+#undef DDR_PHY_ACBDLR7_RESERVED_23_22_MASK
 #define DDR_PHY_ACBDLR7_RESERVED_23_22_DEFVAL                  0x00000000
 #define DDR_PHY_ACBDLR7_RESERVED_23_22_SHIFT                   22
 #define DDR_PHY_ACBDLR7_RESERVED_23_22_MASK                    0x00C00000U
@@ -12450,9 +12450,9 @@
 /*
 * Delay select for the BDL on Address A[6].
 */
-#undef DDR_PHY_ACBDLR7_A06BD_DEFVAL 
-#undef DDR_PHY_ACBDLR7_A06BD_SHIFT 
-#undef DDR_PHY_ACBDLR7_A06BD_MASK 
+#undef DDR_PHY_ACBDLR7_A06BD_DEFVAL
+#undef DDR_PHY_ACBDLR7_A06BD_SHIFT
+#undef DDR_PHY_ACBDLR7_A06BD_MASK
 #define DDR_PHY_ACBDLR7_A06BD_DEFVAL                           0x00000000
 #define DDR_PHY_ACBDLR7_A06BD_SHIFT                            16
 #define DDR_PHY_ACBDLR7_A06BD_MASK                             0x003F0000U
@@ -12460,9 +12460,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_ACBDLR7_RESERVED_15_14_DEFVAL 
-#undef DDR_PHY_ACBDLR7_RESERVED_15_14_SHIFT 
-#undef DDR_PHY_ACBDLR7_RESERVED_15_14_MASK 
+#undef DDR_PHY_ACBDLR7_RESERVED_15_14_DEFVAL
+#undef DDR_PHY_ACBDLR7_RESERVED_15_14_SHIFT
+#undef DDR_PHY_ACBDLR7_RESERVED_15_14_MASK
 #define DDR_PHY_ACBDLR7_RESERVED_15_14_DEFVAL                  0x00000000
 #define DDR_PHY_ACBDLR7_RESERVED_15_14_SHIFT                   14
 #define DDR_PHY_ACBDLR7_RESERVED_15_14_MASK                    0x0000C000U
@@ -12470,9 +12470,9 @@
 /*
 * Delay select for the BDL on Address A[5].
 */
-#undef DDR_PHY_ACBDLR7_A05BD_DEFVAL 
-#undef DDR_PHY_ACBDLR7_A05BD_SHIFT 
-#undef DDR_PHY_ACBDLR7_A05BD_MASK 
+#undef DDR_PHY_ACBDLR7_A05BD_DEFVAL
+#undef DDR_PHY_ACBDLR7_A05BD_SHIFT
+#undef DDR_PHY_ACBDLR7_A05BD_MASK
 #define DDR_PHY_ACBDLR7_A05BD_DEFVAL                           0x00000000
 #define DDR_PHY_ACBDLR7_A05BD_SHIFT                            8
 #define DDR_PHY_ACBDLR7_A05BD_MASK                             0x00003F00U
@@ -12480,9 +12480,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_ACBDLR7_RESERVED_7_6_DEFVAL 
-#undef DDR_PHY_ACBDLR7_RESERVED_7_6_SHIFT 
-#undef DDR_PHY_ACBDLR7_RESERVED_7_6_MASK 
+#undef DDR_PHY_ACBDLR7_RESERVED_7_6_DEFVAL
+#undef DDR_PHY_ACBDLR7_RESERVED_7_6_SHIFT
+#undef DDR_PHY_ACBDLR7_RESERVED_7_6_MASK
 #define DDR_PHY_ACBDLR7_RESERVED_7_6_DEFVAL                    0x00000000
 #define DDR_PHY_ACBDLR7_RESERVED_7_6_SHIFT                     6
 #define DDR_PHY_ACBDLR7_RESERVED_7_6_MASK                      0x000000C0U
@@ -12490,9 +12490,9 @@
 /*
 * Delay select for the BDL on Address A[4].
 */
-#undef DDR_PHY_ACBDLR7_A04BD_DEFVAL 
-#undef DDR_PHY_ACBDLR7_A04BD_SHIFT 
-#undef DDR_PHY_ACBDLR7_A04BD_MASK 
+#undef DDR_PHY_ACBDLR7_A04BD_DEFVAL
+#undef DDR_PHY_ACBDLR7_A04BD_SHIFT
+#undef DDR_PHY_ACBDLR7_A04BD_MASK
 #define DDR_PHY_ACBDLR7_A04BD_DEFVAL                           0x00000000
 #define DDR_PHY_ACBDLR7_A04BD_SHIFT                            0
 #define DDR_PHY_ACBDLR7_A04BD_MASK                             0x0000003FU
@@ -12500,9 +12500,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_ACBDLR8_RESERVED_31_30_DEFVAL 
-#undef DDR_PHY_ACBDLR8_RESERVED_31_30_SHIFT 
-#undef DDR_PHY_ACBDLR8_RESERVED_31_30_MASK 
+#undef DDR_PHY_ACBDLR8_RESERVED_31_30_DEFVAL
+#undef DDR_PHY_ACBDLR8_RESERVED_31_30_SHIFT
+#undef DDR_PHY_ACBDLR8_RESERVED_31_30_MASK
 #define DDR_PHY_ACBDLR8_RESERVED_31_30_DEFVAL                  0x00000000
 #define DDR_PHY_ACBDLR8_RESERVED_31_30_SHIFT                   30
 #define DDR_PHY_ACBDLR8_RESERVED_31_30_MASK                    0xC0000000U
@@ -12510,9 +12510,9 @@
 /*
 * Delay select for the BDL on Address A[11].
 */
-#undef DDR_PHY_ACBDLR8_A11BD_DEFVAL 
-#undef DDR_PHY_ACBDLR8_A11BD_SHIFT 
-#undef DDR_PHY_ACBDLR8_A11BD_MASK 
+#undef DDR_PHY_ACBDLR8_A11BD_DEFVAL
+#undef DDR_PHY_ACBDLR8_A11BD_SHIFT
+#undef DDR_PHY_ACBDLR8_A11BD_MASK
 #define DDR_PHY_ACBDLR8_A11BD_DEFVAL                           0x00000000
 #define DDR_PHY_ACBDLR8_A11BD_SHIFT                            24
 #define DDR_PHY_ACBDLR8_A11BD_MASK                             0x3F000000U
@@ -12520,9 +12520,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_ACBDLR8_RESERVED_23_22_DEFVAL 
-#undef DDR_PHY_ACBDLR8_RESERVED_23_22_SHIFT 
-#undef DDR_PHY_ACBDLR8_RESERVED_23_22_MASK 
+#undef DDR_PHY_ACBDLR8_RESERVED_23_22_DEFVAL
+#undef DDR_PHY_ACBDLR8_RESERVED_23_22_SHIFT
+#undef DDR_PHY_ACBDLR8_RESERVED_23_22_MASK
 #define DDR_PHY_ACBDLR8_RESERVED_23_22_DEFVAL                  0x00000000
 #define DDR_PHY_ACBDLR8_RESERVED_23_22_SHIFT                   22
 #define DDR_PHY_ACBDLR8_RESERVED_23_22_MASK                    0x00C00000U
@@ -12530,9 +12530,9 @@
 /*
 * Delay select for the BDL on Address A[10].
 */
-#undef DDR_PHY_ACBDLR8_A10BD_DEFVAL 
-#undef DDR_PHY_ACBDLR8_A10BD_SHIFT 
-#undef DDR_PHY_ACBDLR8_A10BD_MASK 
+#undef DDR_PHY_ACBDLR8_A10BD_DEFVAL
+#undef DDR_PHY_ACBDLR8_A10BD_SHIFT
+#undef DDR_PHY_ACBDLR8_A10BD_MASK
 #define DDR_PHY_ACBDLR8_A10BD_DEFVAL                           0x00000000
 #define DDR_PHY_ACBDLR8_A10BD_SHIFT                            16
 #define DDR_PHY_ACBDLR8_A10BD_MASK                             0x003F0000U
@@ -12540,9 +12540,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_ACBDLR8_RESERVED_15_14_DEFVAL 
-#undef DDR_PHY_ACBDLR8_RESERVED_15_14_SHIFT 
-#undef DDR_PHY_ACBDLR8_RESERVED_15_14_MASK 
+#undef DDR_PHY_ACBDLR8_RESERVED_15_14_DEFVAL
+#undef DDR_PHY_ACBDLR8_RESERVED_15_14_SHIFT
+#undef DDR_PHY_ACBDLR8_RESERVED_15_14_MASK
 #define DDR_PHY_ACBDLR8_RESERVED_15_14_DEFVAL                  0x00000000
 #define DDR_PHY_ACBDLR8_RESERVED_15_14_SHIFT                   14
 #define DDR_PHY_ACBDLR8_RESERVED_15_14_MASK                    0x0000C000U
@@ -12550,9 +12550,9 @@
 /*
 * Delay select for the BDL on Address A[9].
 */
-#undef DDR_PHY_ACBDLR8_A09BD_DEFVAL 
-#undef DDR_PHY_ACBDLR8_A09BD_SHIFT 
-#undef DDR_PHY_ACBDLR8_A09BD_MASK 
+#undef DDR_PHY_ACBDLR8_A09BD_DEFVAL
+#undef DDR_PHY_ACBDLR8_A09BD_SHIFT
+#undef DDR_PHY_ACBDLR8_A09BD_MASK
 #define DDR_PHY_ACBDLR8_A09BD_DEFVAL                           0x00000000
 #define DDR_PHY_ACBDLR8_A09BD_SHIFT                            8
 #define DDR_PHY_ACBDLR8_A09BD_MASK                             0x00003F00U
@@ -12560,9 +12560,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_ACBDLR8_RESERVED_7_6_DEFVAL 
-#undef DDR_PHY_ACBDLR8_RESERVED_7_6_SHIFT 
-#undef DDR_PHY_ACBDLR8_RESERVED_7_6_MASK 
+#undef DDR_PHY_ACBDLR8_RESERVED_7_6_DEFVAL
+#undef DDR_PHY_ACBDLR8_RESERVED_7_6_SHIFT
+#undef DDR_PHY_ACBDLR8_RESERVED_7_6_MASK
 #define DDR_PHY_ACBDLR8_RESERVED_7_6_DEFVAL                    0x00000000
 #define DDR_PHY_ACBDLR8_RESERVED_7_6_SHIFT                     6
 #define DDR_PHY_ACBDLR8_RESERVED_7_6_MASK                      0x000000C0U
@@ -12570,9 +12570,9 @@
 /*
 * Delay select for the BDL on Address A[8].
 */
-#undef DDR_PHY_ACBDLR8_A08BD_DEFVAL 
-#undef DDR_PHY_ACBDLR8_A08BD_SHIFT 
-#undef DDR_PHY_ACBDLR8_A08BD_MASK 
+#undef DDR_PHY_ACBDLR8_A08BD_DEFVAL
+#undef DDR_PHY_ACBDLR8_A08BD_SHIFT
+#undef DDR_PHY_ACBDLR8_A08BD_MASK
 #define DDR_PHY_ACBDLR8_A08BD_DEFVAL                           0x00000000
 #define DDR_PHY_ACBDLR8_A08BD_SHIFT                            0
 #define DDR_PHY_ACBDLR8_A08BD_MASK                             0x0000003FU
@@ -12580,9 +12580,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_ACBDLR9_RESERVED_31_30_DEFVAL 
-#undef DDR_PHY_ACBDLR9_RESERVED_31_30_SHIFT 
-#undef DDR_PHY_ACBDLR9_RESERVED_31_30_MASK 
+#undef DDR_PHY_ACBDLR9_RESERVED_31_30_DEFVAL
+#undef DDR_PHY_ACBDLR9_RESERVED_31_30_SHIFT
+#undef DDR_PHY_ACBDLR9_RESERVED_31_30_MASK
 #define DDR_PHY_ACBDLR9_RESERVED_31_30_DEFVAL                  0x00000000
 #define DDR_PHY_ACBDLR9_RESERVED_31_30_SHIFT                   30
 #define DDR_PHY_ACBDLR9_RESERVED_31_30_MASK                    0xC0000000U
@@ -12590,9 +12590,9 @@
 /*
 * Delay select for the BDL on Address A[15].
 */
-#undef DDR_PHY_ACBDLR9_A15BD_DEFVAL 
-#undef DDR_PHY_ACBDLR9_A15BD_SHIFT 
-#undef DDR_PHY_ACBDLR9_A15BD_MASK 
+#undef DDR_PHY_ACBDLR9_A15BD_DEFVAL
+#undef DDR_PHY_ACBDLR9_A15BD_SHIFT
+#undef DDR_PHY_ACBDLR9_A15BD_MASK
 #define DDR_PHY_ACBDLR9_A15BD_DEFVAL                           0x00000000
 #define DDR_PHY_ACBDLR9_A15BD_SHIFT                            24
 #define DDR_PHY_ACBDLR9_A15BD_MASK                             0x3F000000U
@@ -12600,9 +12600,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_ACBDLR9_RESERVED_23_22_DEFVAL 
-#undef DDR_PHY_ACBDLR9_RESERVED_23_22_SHIFT 
-#undef DDR_PHY_ACBDLR9_RESERVED_23_22_MASK 
+#undef DDR_PHY_ACBDLR9_RESERVED_23_22_DEFVAL
+#undef DDR_PHY_ACBDLR9_RESERVED_23_22_SHIFT
+#undef DDR_PHY_ACBDLR9_RESERVED_23_22_MASK
 #define DDR_PHY_ACBDLR9_RESERVED_23_22_DEFVAL                  0x00000000
 #define DDR_PHY_ACBDLR9_RESERVED_23_22_SHIFT                   22
 #define DDR_PHY_ACBDLR9_RESERVED_23_22_MASK                    0x00C00000U
@@ -12610,9 +12610,9 @@
 /*
 * Delay select for the BDL on Address A[14].
 */
-#undef DDR_PHY_ACBDLR9_A14BD_DEFVAL 
-#undef DDR_PHY_ACBDLR9_A14BD_SHIFT 
-#undef DDR_PHY_ACBDLR9_A14BD_MASK 
+#undef DDR_PHY_ACBDLR9_A14BD_DEFVAL
+#undef DDR_PHY_ACBDLR9_A14BD_SHIFT
+#undef DDR_PHY_ACBDLR9_A14BD_MASK
 #define DDR_PHY_ACBDLR9_A14BD_DEFVAL                           0x00000000
 #define DDR_PHY_ACBDLR9_A14BD_SHIFT                            16
 #define DDR_PHY_ACBDLR9_A14BD_MASK                             0x003F0000U
@@ -12620,9 +12620,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_ACBDLR9_RESERVED_15_14_DEFVAL 
-#undef DDR_PHY_ACBDLR9_RESERVED_15_14_SHIFT 
-#undef DDR_PHY_ACBDLR9_RESERVED_15_14_MASK 
+#undef DDR_PHY_ACBDLR9_RESERVED_15_14_DEFVAL
+#undef DDR_PHY_ACBDLR9_RESERVED_15_14_SHIFT
+#undef DDR_PHY_ACBDLR9_RESERVED_15_14_MASK
 #define DDR_PHY_ACBDLR9_RESERVED_15_14_DEFVAL                  0x00000000
 #define DDR_PHY_ACBDLR9_RESERVED_15_14_SHIFT                   14
 #define DDR_PHY_ACBDLR9_RESERVED_15_14_MASK                    0x0000C000U
@@ -12630,9 +12630,9 @@
 /*
 * Delay select for the BDL on Address A[13].
 */
-#undef DDR_PHY_ACBDLR9_A13BD_DEFVAL 
-#undef DDR_PHY_ACBDLR9_A13BD_SHIFT 
-#undef DDR_PHY_ACBDLR9_A13BD_MASK 
+#undef DDR_PHY_ACBDLR9_A13BD_DEFVAL
+#undef DDR_PHY_ACBDLR9_A13BD_SHIFT
+#undef DDR_PHY_ACBDLR9_A13BD_MASK
 #define DDR_PHY_ACBDLR9_A13BD_DEFVAL                           0x00000000
 #define DDR_PHY_ACBDLR9_A13BD_SHIFT                            8
 #define DDR_PHY_ACBDLR9_A13BD_MASK                             0x00003F00U
@@ -12640,9 +12640,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_ACBDLR9_RESERVED_7_6_DEFVAL 
-#undef DDR_PHY_ACBDLR9_RESERVED_7_6_SHIFT 
-#undef DDR_PHY_ACBDLR9_RESERVED_7_6_MASK 
+#undef DDR_PHY_ACBDLR9_RESERVED_7_6_DEFVAL
+#undef DDR_PHY_ACBDLR9_RESERVED_7_6_SHIFT
+#undef DDR_PHY_ACBDLR9_RESERVED_7_6_MASK
 #define DDR_PHY_ACBDLR9_RESERVED_7_6_DEFVAL                    0x00000000
 #define DDR_PHY_ACBDLR9_RESERVED_7_6_SHIFT                     6
 #define DDR_PHY_ACBDLR9_RESERVED_7_6_MASK                      0x000000C0U
@@ -12650,9 +12650,9 @@
 /*
 * Delay select for the BDL on Address A[12].
 */
-#undef DDR_PHY_ACBDLR9_A12BD_DEFVAL 
-#undef DDR_PHY_ACBDLR9_A12BD_SHIFT 
-#undef DDR_PHY_ACBDLR9_A12BD_MASK 
+#undef DDR_PHY_ACBDLR9_A12BD_DEFVAL
+#undef DDR_PHY_ACBDLR9_A12BD_SHIFT
+#undef DDR_PHY_ACBDLR9_A12BD_MASK
 #define DDR_PHY_ACBDLR9_A12BD_DEFVAL                           0x00000000
 #define DDR_PHY_ACBDLR9_A12BD_SHIFT                            0
 #define DDR_PHY_ACBDLR9_A12BD_MASK                             0x0000003FU
@@ -12660,9 +12660,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_ZQCR_RESERVED_31_26_DEFVAL 
-#undef DDR_PHY_ZQCR_RESERVED_31_26_SHIFT 
-#undef DDR_PHY_ZQCR_RESERVED_31_26_MASK 
+#undef DDR_PHY_ZQCR_RESERVED_31_26_DEFVAL
+#undef DDR_PHY_ZQCR_RESERVED_31_26_SHIFT
+#undef DDR_PHY_ZQCR_RESERVED_31_26_MASK
 #define DDR_PHY_ZQCR_RESERVED_31_26_DEFVAL                     0x008A2858
 #define DDR_PHY_ZQCR_RESERVED_31_26_SHIFT                      26
 #define DDR_PHY_ZQCR_RESERVED_31_26_MASK                       0xFC000000U
@@ -12670,9 +12670,9 @@
 /*
 * ZQ VREF Range
 */
-#undef DDR_PHY_ZQCR_ZQREFISELRANGE_DEFVAL 
-#undef DDR_PHY_ZQCR_ZQREFISELRANGE_SHIFT 
-#undef DDR_PHY_ZQCR_ZQREFISELRANGE_MASK 
+#undef DDR_PHY_ZQCR_ZQREFISELRANGE_DEFVAL
+#undef DDR_PHY_ZQCR_ZQREFISELRANGE_SHIFT
+#undef DDR_PHY_ZQCR_ZQREFISELRANGE_MASK
 #define DDR_PHY_ZQCR_ZQREFISELRANGE_DEFVAL                     0x008A2858
 #define DDR_PHY_ZQCR_ZQREFISELRANGE_SHIFT                      25
 #define DDR_PHY_ZQCR_ZQREFISELRANGE_MASK                       0x02000000U
@@ -12680,9 +12680,9 @@
 /*
 * Programmable Wait for Frequency B
 */
-#undef DDR_PHY_ZQCR_PGWAIT_FRQB_DEFVAL 
-#undef DDR_PHY_ZQCR_PGWAIT_FRQB_SHIFT 
-#undef DDR_PHY_ZQCR_PGWAIT_FRQB_MASK 
+#undef DDR_PHY_ZQCR_PGWAIT_FRQB_DEFVAL
+#undef DDR_PHY_ZQCR_PGWAIT_FRQB_SHIFT
+#undef DDR_PHY_ZQCR_PGWAIT_FRQB_MASK
 #define DDR_PHY_ZQCR_PGWAIT_FRQB_DEFVAL                        0x008A2858
 #define DDR_PHY_ZQCR_PGWAIT_FRQB_SHIFT                         19
 #define DDR_PHY_ZQCR_PGWAIT_FRQB_MASK                          0x01F80000U
@@ -12690,9 +12690,9 @@
 /*
 * Programmable Wait for Frequency A
 */
-#undef DDR_PHY_ZQCR_PGWAIT_FRQA_DEFVAL 
-#undef DDR_PHY_ZQCR_PGWAIT_FRQA_SHIFT 
-#undef DDR_PHY_ZQCR_PGWAIT_FRQA_MASK 
+#undef DDR_PHY_ZQCR_PGWAIT_FRQA_DEFVAL
+#undef DDR_PHY_ZQCR_PGWAIT_FRQA_SHIFT
+#undef DDR_PHY_ZQCR_PGWAIT_FRQA_MASK
 #define DDR_PHY_ZQCR_PGWAIT_FRQA_DEFVAL                        0x008A2858
 #define DDR_PHY_ZQCR_PGWAIT_FRQA_SHIFT                         13
 #define DDR_PHY_ZQCR_PGWAIT_FRQA_MASK                          0x0007E000U
@@ -12700,9 +12700,9 @@
 /*
 * ZQ VREF Pad Enable
 */
-#undef DDR_PHY_ZQCR_ZQREFPEN_DEFVAL 
-#undef DDR_PHY_ZQCR_ZQREFPEN_SHIFT 
-#undef DDR_PHY_ZQCR_ZQREFPEN_MASK 
+#undef DDR_PHY_ZQCR_ZQREFPEN_DEFVAL
+#undef DDR_PHY_ZQCR_ZQREFPEN_SHIFT
+#undef DDR_PHY_ZQCR_ZQREFPEN_MASK
 #define DDR_PHY_ZQCR_ZQREFPEN_DEFVAL                           0x008A2858
 #define DDR_PHY_ZQCR_ZQREFPEN_SHIFT                            12
 #define DDR_PHY_ZQCR_ZQREFPEN_MASK                             0x00001000U
@@ -12710,9 +12710,9 @@
 /*
 * ZQ Internal VREF Enable
 */
-#undef DDR_PHY_ZQCR_ZQREFIEN_DEFVAL 
-#undef DDR_PHY_ZQCR_ZQREFIEN_SHIFT 
-#undef DDR_PHY_ZQCR_ZQREFIEN_MASK 
+#undef DDR_PHY_ZQCR_ZQREFIEN_DEFVAL
+#undef DDR_PHY_ZQCR_ZQREFIEN_SHIFT
+#undef DDR_PHY_ZQCR_ZQREFIEN_MASK
 #define DDR_PHY_ZQCR_ZQREFIEN_DEFVAL                           0x008A2858
 #define DDR_PHY_ZQCR_ZQREFIEN_SHIFT                            11
 #define DDR_PHY_ZQCR_ZQREFIEN_MASK                             0x00000800U
@@ -12720,9 +12720,9 @@
 /*
 * Choice of termination mode
 */
-#undef DDR_PHY_ZQCR_ODT_MODE_DEFVAL 
-#undef DDR_PHY_ZQCR_ODT_MODE_SHIFT 
-#undef DDR_PHY_ZQCR_ODT_MODE_MASK 
+#undef DDR_PHY_ZQCR_ODT_MODE_DEFVAL
+#undef DDR_PHY_ZQCR_ODT_MODE_SHIFT
+#undef DDR_PHY_ZQCR_ODT_MODE_MASK
 #define DDR_PHY_ZQCR_ODT_MODE_DEFVAL                           0x008A2858
 #define DDR_PHY_ZQCR_ODT_MODE_SHIFT                            9
 #define DDR_PHY_ZQCR_ODT_MODE_MASK                             0x00000600U
@@ -12730,9 +12730,9 @@
 /*
 * Force ZCAL VT update
 */
-#undef DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_DEFVAL 
-#undef DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_SHIFT 
-#undef DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_MASK 
+#undef DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_DEFVAL
+#undef DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_SHIFT
+#undef DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_MASK
 #define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_DEFVAL               0x008A2858
 #define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_SHIFT                8
 #define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_MASK                 0x00000100U
@@ -12740,9 +12740,9 @@
 /*
 * IO VT Drift Limit
 */
-#undef DDR_PHY_ZQCR_IODLMT_DEFVAL 
-#undef DDR_PHY_ZQCR_IODLMT_SHIFT 
-#undef DDR_PHY_ZQCR_IODLMT_MASK 
+#undef DDR_PHY_ZQCR_IODLMT_DEFVAL
+#undef DDR_PHY_ZQCR_IODLMT_SHIFT
+#undef DDR_PHY_ZQCR_IODLMT_MASK
 #define DDR_PHY_ZQCR_IODLMT_DEFVAL                             0x008A2858
 #define DDR_PHY_ZQCR_IODLMT_SHIFT                              5
 #define DDR_PHY_ZQCR_IODLMT_MASK                               0x000000E0U
@@ -12750,9 +12750,9 @@
 /*
 * Averaging algorithm enable, if set, enables averaging algorithm
 */
-#undef DDR_PHY_ZQCR_AVGEN_DEFVAL 
-#undef DDR_PHY_ZQCR_AVGEN_SHIFT 
-#undef DDR_PHY_ZQCR_AVGEN_MASK 
+#undef DDR_PHY_ZQCR_AVGEN_DEFVAL
+#undef DDR_PHY_ZQCR_AVGEN_SHIFT
+#undef DDR_PHY_ZQCR_AVGEN_MASK
 #define DDR_PHY_ZQCR_AVGEN_DEFVAL                              0x008A2858
 #define DDR_PHY_ZQCR_AVGEN_SHIFT                               4
 #define DDR_PHY_ZQCR_AVGEN_MASK                                0x00000010U
@@ -12760,9 +12760,9 @@
 /*
 * Maximum number of averaging rounds to be used by averaging algorithm
 */
-#undef DDR_PHY_ZQCR_AVGMAX_DEFVAL 
-#undef DDR_PHY_ZQCR_AVGMAX_SHIFT 
-#undef DDR_PHY_ZQCR_AVGMAX_MASK 
+#undef DDR_PHY_ZQCR_AVGMAX_DEFVAL
+#undef DDR_PHY_ZQCR_AVGMAX_SHIFT
+#undef DDR_PHY_ZQCR_AVGMAX_MASK
 #define DDR_PHY_ZQCR_AVGMAX_DEFVAL                             0x008A2858
 #define DDR_PHY_ZQCR_AVGMAX_SHIFT                              2
 #define DDR_PHY_ZQCR_AVGMAX_MASK                               0x0000000CU
@@ -12770,9 +12770,9 @@
 /*
 * ZQ Calibration Type
 */
-#undef DDR_PHY_ZQCR_ZCALT_DEFVAL 
-#undef DDR_PHY_ZQCR_ZCALT_SHIFT 
-#undef DDR_PHY_ZQCR_ZCALT_MASK 
+#undef DDR_PHY_ZQCR_ZCALT_DEFVAL
+#undef DDR_PHY_ZQCR_ZCALT_SHIFT
+#undef DDR_PHY_ZQCR_ZCALT_MASK
 #define DDR_PHY_ZQCR_ZCALT_DEFVAL                              0x008A2858
 #define DDR_PHY_ZQCR_ZCALT_SHIFT                               1
 #define DDR_PHY_ZQCR_ZCALT_MASK                                0x00000002U
@@ -12780,9 +12780,9 @@
 /*
 * ZQ Power Down
 */
-#undef DDR_PHY_ZQCR_ZQPD_DEFVAL 
-#undef DDR_PHY_ZQCR_ZQPD_SHIFT 
-#undef DDR_PHY_ZQCR_ZQPD_MASK 
+#undef DDR_PHY_ZQCR_ZQPD_DEFVAL
+#undef DDR_PHY_ZQCR_ZQPD_SHIFT
+#undef DDR_PHY_ZQCR_ZQPD_MASK
 #define DDR_PHY_ZQCR_ZQPD_DEFVAL                               0x008A2858
 #define DDR_PHY_ZQCR_ZQPD_SHIFT                                0
 #define DDR_PHY_ZQCR_ZQPD_MASK                                 0x00000001U
@@ -12790,9 +12790,9 @@
 /*
 * Pull-down drive strength ZCTRL over-ride enable
 */
-#undef DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_DEFVAL 
-#undef DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_SHIFT 
-#undef DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_MASK 
+#undef DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_DEFVAL
+#undef DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_SHIFT
+#undef DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_MASK
 #define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_DEFVAL                      0x000077BB
 #define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_SHIFT                       31
 #define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_MASK                        0x80000000U
@@ -12800,9 +12800,9 @@
 /*
 * Pull-up drive strength ZCTRL over-ride enable
 */
-#undef DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_DEFVAL 
-#undef DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_SHIFT 
-#undef DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_MASK 
+#undef DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_DEFVAL
+#undef DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_SHIFT
+#undef DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_MASK
 #define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_DEFVAL                      0x000077BB
 #define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_SHIFT                       30
 #define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_MASK                        0x40000000U
@@ -12810,9 +12810,9 @@
 /*
 * Pull-down termination ZCTRL over-ride enable
 */
-#undef DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_DEFVAL 
-#undef DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_SHIFT 
-#undef DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_MASK 
+#undef DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_DEFVAL
+#undef DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_SHIFT
+#undef DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_MASK
 #define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_DEFVAL                      0x000077BB
 #define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_SHIFT                       29
 #define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_MASK                        0x20000000U
@@ -12820,9 +12820,9 @@
 /*
 * Pull-up termination ZCTRL over-ride enable
 */
-#undef DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_DEFVAL 
-#undef DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_SHIFT 
-#undef DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_MASK 
+#undef DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_DEFVAL
+#undef DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_SHIFT
+#undef DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_MASK
 #define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_DEFVAL                      0x000077BB
 #define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_SHIFT                       28
 #define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_MASK                        0x10000000U
@@ -12830,9 +12830,9 @@
 /*
 * Calibration segment bypass
 */
-#undef DDR_PHY_ZQ0PR0_ZSEGBYP_DEFVAL 
-#undef DDR_PHY_ZQ0PR0_ZSEGBYP_SHIFT 
-#undef DDR_PHY_ZQ0PR0_ZSEGBYP_MASK 
+#undef DDR_PHY_ZQ0PR0_ZSEGBYP_DEFVAL
+#undef DDR_PHY_ZQ0PR0_ZSEGBYP_SHIFT
+#undef DDR_PHY_ZQ0PR0_ZSEGBYP_MASK
 #define DDR_PHY_ZQ0PR0_ZSEGBYP_DEFVAL                          0x000077BB
 #define DDR_PHY_ZQ0PR0_ZSEGBYP_SHIFT                           27
 #define DDR_PHY_ZQ0PR0_ZSEGBYP_MASK                            0x08000000U
@@ -12841,9 +12841,9 @@
 * VREF latch mode controls the mode in which the ZLE pin of the PVREF cell
     *  is driven by the PUB
 */
-#undef DDR_PHY_ZQ0PR0_ZLE_MODE_DEFVAL 
-#undef DDR_PHY_ZQ0PR0_ZLE_MODE_SHIFT 
-#undef DDR_PHY_ZQ0PR0_ZLE_MODE_MASK 
+#undef DDR_PHY_ZQ0PR0_ZLE_MODE_DEFVAL
+#undef DDR_PHY_ZQ0PR0_ZLE_MODE_SHIFT
+#undef DDR_PHY_ZQ0PR0_ZLE_MODE_MASK
 #define DDR_PHY_ZQ0PR0_ZLE_MODE_DEFVAL                         0x000077BB
 #define DDR_PHY_ZQ0PR0_ZLE_MODE_SHIFT                          25
 #define DDR_PHY_ZQ0PR0_ZLE_MODE_MASK                           0x06000000U
@@ -12851,9 +12851,9 @@
 /*
 * Termination adjustment
 */
-#undef DDR_PHY_ZQ0PR0_ODT_ADJUST_DEFVAL 
-#undef DDR_PHY_ZQ0PR0_ODT_ADJUST_SHIFT 
-#undef DDR_PHY_ZQ0PR0_ODT_ADJUST_MASK 
+#undef DDR_PHY_ZQ0PR0_ODT_ADJUST_DEFVAL
+#undef DDR_PHY_ZQ0PR0_ODT_ADJUST_SHIFT
+#undef DDR_PHY_ZQ0PR0_ODT_ADJUST_MASK
 #define DDR_PHY_ZQ0PR0_ODT_ADJUST_DEFVAL                       0x000077BB
 #define DDR_PHY_ZQ0PR0_ODT_ADJUST_SHIFT                        22
 #define DDR_PHY_ZQ0PR0_ODT_ADJUST_MASK                         0x01C00000U
@@ -12861,9 +12861,9 @@
 /*
 * Pulldown drive strength adjustment
 */
-#undef DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_DEFVAL 
-#undef DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_SHIFT 
-#undef DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_MASK 
+#undef DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_DEFVAL
+#undef DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_SHIFT
+#undef DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_MASK
 #define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_DEFVAL                    0x000077BB
 #define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_SHIFT                     19
 #define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_MASK                      0x00380000U
@@ -12871,9 +12871,9 @@
 /*
 * Pullup drive strength adjustment
 */
-#undef DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_DEFVAL 
-#undef DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_SHIFT 
-#undef DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_MASK 
+#undef DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_DEFVAL
+#undef DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_SHIFT
+#undef DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_MASK
 #define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_DEFVAL                    0x000077BB
 #define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_SHIFT                     16
 #define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_MASK                      0x00070000U
@@ -12881,9 +12881,9 @@
 /*
 * DRAM Impedance Divide Ratio
 */
-#undef DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_DEFVAL 
-#undef DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_SHIFT 
-#undef DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_MASK 
+#undef DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_DEFVAL
+#undef DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_SHIFT
+#undef DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_MASK
 #define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_DEFVAL                   0x000077BB
 #define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_SHIFT                    12
 #define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_MASK                     0x0000F000U
@@ -12891,9 +12891,9 @@
 /*
 * HOST Impedance Divide Ratio
 */
-#undef DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_DEFVAL 
-#undef DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_SHIFT 
-#undef DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_MASK 
+#undef DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_DEFVAL
+#undef DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_SHIFT
+#undef DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_MASK
 #define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_DEFVAL                   0x000077BB
 #define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_SHIFT                    8
 #define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_MASK                     0x00000F00U
@@ -12902,9 +12902,9 @@
 * Impedance Divide Ratio (pulldown drive calibration during asymmetric dri
     * ve strength calibration)
 */
-#undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_DEFVAL 
-#undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_SHIFT 
-#undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_MASK 
+#undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_DEFVAL
+#undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_SHIFT
+#undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_MASK
 #define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_DEFVAL                0x000077BB
 #define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_SHIFT                 4
 #define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_MASK                  0x000000F0U
@@ -12913,9 +12913,9 @@
 * Impedance Divide Ratio (pullup drive calibration during asymmetric drive
     *  strength calibration)
 */
-#undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_DEFVAL 
-#undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_SHIFT 
-#undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_MASK 
+#undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_DEFVAL
+#undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_SHIFT
+#undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_MASK
 #define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_DEFVAL                0x000077BB
 #define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_SHIFT                 0
 #define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_MASK                  0x0000000FU
@@ -12923,9 +12923,9 @@
 /*
 * Reserved. Return zeros on reads.
 */
-#undef DDR_PHY_ZQ0OR0_RESERVED_31_26_DEFVAL 
-#undef DDR_PHY_ZQ0OR0_RESERVED_31_26_SHIFT 
-#undef DDR_PHY_ZQ0OR0_RESERVED_31_26_MASK 
+#undef DDR_PHY_ZQ0OR0_RESERVED_31_26_DEFVAL
+#undef DDR_PHY_ZQ0OR0_RESERVED_31_26_SHIFT
+#undef DDR_PHY_ZQ0OR0_RESERVED_31_26_MASK
 #define DDR_PHY_ZQ0OR0_RESERVED_31_26_DEFVAL                   0x00000000
 #define DDR_PHY_ZQ0OR0_RESERVED_31_26_SHIFT                    26
 #define DDR_PHY_ZQ0OR0_RESERVED_31_26_MASK                     0xFC000000U
@@ -12933,9 +12933,9 @@
 /*
 * Override value for the pull-up output impedance
 */
-#undef DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_DEFVAL 
-#undef DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_SHIFT 
-#undef DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_MASK 
+#undef DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_DEFVAL
+#undef DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_SHIFT
+#undef DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_MASK
 #define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_DEFVAL                0x00000000
 #define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_SHIFT                 16
 #define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_MASK                  0x03FF0000U
@@ -12943,9 +12943,9 @@
 /*
 * Reserved. Return zeros on reads.
 */
-#undef DDR_PHY_ZQ0OR0_RESERVED_15_10_DEFVAL 
-#undef DDR_PHY_ZQ0OR0_RESERVED_15_10_SHIFT 
-#undef DDR_PHY_ZQ0OR0_RESERVED_15_10_MASK 
+#undef DDR_PHY_ZQ0OR0_RESERVED_15_10_DEFVAL
+#undef DDR_PHY_ZQ0OR0_RESERVED_15_10_SHIFT
+#undef DDR_PHY_ZQ0OR0_RESERVED_15_10_MASK
 #define DDR_PHY_ZQ0OR0_RESERVED_15_10_DEFVAL                   0x00000000
 #define DDR_PHY_ZQ0OR0_RESERVED_15_10_SHIFT                    10
 #define DDR_PHY_ZQ0OR0_RESERVED_15_10_MASK                     0x0000FC00U
@@ -12953,9 +12953,9 @@
 /*
 * Override value for the pull-down output impedance
 */
-#undef DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_DEFVAL 
-#undef DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_SHIFT 
-#undef DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_MASK 
+#undef DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_DEFVAL
+#undef DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_SHIFT
+#undef DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_MASK
 #define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_DEFVAL                0x00000000
 #define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_SHIFT                 0
 #define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_MASK                  0x000003FFU
@@ -12963,9 +12963,9 @@
 /*
 * Reserved. Return zeros on reads.
 */
-#undef DDR_PHY_ZQ0OR1_RESERVED_31_26_DEFVAL 
-#undef DDR_PHY_ZQ0OR1_RESERVED_31_26_SHIFT 
-#undef DDR_PHY_ZQ0OR1_RESERVED_31_26_MASK 
+#undef DDR_PHY_ZQ0OR1_RESERVED_31_26_DEFVAL
+#undef DDR_PHY_ZQ0OR1_RESERVED_31_26_SHIFT
+#undef DDR_PHY_ZQ0OR1_RESERVED_31_26_MASK
 #define DDR_PHY_ZQ0OR1_RESERVED_31_26_DEFVAL                   0x00000000
 #define DDR_PHY_ZQ0OR1_RESERVED_31_26_SHIFT                    26
 #define DDR_PHY_ZQ0OR1_RESERVED_31_26_MASK                     0xFC000000U
@@ -12973,9 +12973,9 @@
 /*
 * Override value for the pull-up termination
 */
-#undef DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_DEFVAL 
-#undef DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_SHIFT 
-#undef DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_MASK 
+#undef DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_DEFVAL
+#undef DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_SHIFT
+#undef DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_MASK
 #define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_DEFVAL                0x00000000
 #define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_SHIFT                 16
 #define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_MASK                  0x03FF0000U
@@ -12983,9 +12983,9 @@
 /*
 * Reserved. Return zeros on reads.
 */
-#undef DDR_PHY_ZQ0OR1_RESERVED_15_10_DEFVAL 
-#undef DDR_PHY_ZQ0OR1_RESERVED_15_10_SHIFT 
-#undef DDR_PHY_ZQ0OR1_RESERVED_15_10_MASK 
+#undef DDR_PHY_ZQ0OR1_RESERVED_15_10_DEFVAL
+#undef DDR_PHY_ZQ0OR1_RESERVED_15_10_SHIFT
+#undef DDR_PHY_ZQ0OR1_RESERVED_15_10_MASK
 #define DDR_PHY_ZQ0OR1_RESERVED_15_10_DEFVAL                   0x00000000
 #define DDR_PHY_ZQ0OR1_RESERVED_15_10_SHIFT                    10
 #define DDR_PHY_ZQ0OR1_RESERVED_15_10_MASK                     0x0000FC00U
@@ -12993,9 +12993,9 @@
 /*
 * Override value for the pull-down termination
 */
-#undef DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_DEFVAL 
-#undef DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_SHIFT 
-#undef DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_MASK 
+#undef DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_DEFVAL
+#undef DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_SHIFT
+#undef DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_MASK
 #define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_DEFVAL                0x00000000
 #define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_SHIFT                 0
 #define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_MASK                  0x000003FFU
@@ -13003,9 +13003,9 @@
 /*
 * Pull-down drive strength ZCTRL over-ride enable
 */
-#undef DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_DEFVAL 
-#undef DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_SHIFT 
-#undef DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_MASK 
+#undef DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_DEFVAL
+#undef DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_SHIFT
+#undef DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_MASK
 #define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_DEFVAL                      0x000077BB
 #define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_SHIFT                       31
 #define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_MASK                        0x80000000U
@@ -13013,9 +13013,9 @@
 /*
 * Pull-up drive strength ZCTRL over-ride enable
 */
-#undef DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_DEFVAL 
-#undef DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_SHIFT 
-#undef DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_MASK 
+#undef DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_DEFVAL
+#undef DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_SHIFT
+#undef DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_MASK
 #define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_DEFVAL                      0x000077BB
 #define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_SHIFT                       30
 #define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_MASK                        0x40000000U
@@ -13023,9 +13023,9 @@
 /*
 * Pull-down termination ZCTRL over-ride enable
 */
-#undef DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_DEFVAL 
-#undef DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_SHIFT 
-#undef DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_MASK 
+#undef DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_DEFVAL
+#undef DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_SHIFT
+#undef DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_MASK
 #define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_DEFVAL                      0x000077BB
 #define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_SHIFT                       29
 #define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_MASK                        0x20000000U
@@ -13033,9 +13033,9 @@
 /*
 * Pull-up termination ZCTRL over-ride enable
 */
-#undef DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_DEFVAL 
-#undef DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_SHIFT 
-#undef DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_MASK 
+#undef DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_DEFVAL
+#undef DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_SHIFT
+#undef DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_MASK
 #define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_DEFVAL                      0x000077BB
 #define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_SHIFT                       28
 #define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_MASK                        0x10000000U
@@ -13043,9 +13043,9 @@
 /*
 * Calibration segment bypass
 */
-#undef DDR_PHY_ZQ1PR0_ZSEGBYP_DEFVAL 
-#undef DDR_PHY_ZQ1PR0_ZSEGBYP_SHIFT 
-#undef DDR_PHY_ZQ1PR0_ZSEGBYP_MASK 
+#undef DDR_PHY_ZQ1PR0_ZSEGBYP_DEFVAL
+#undef DDR_PHY_ZQ1PR0_ZSEGBYP_SHIFT
+#undef DDR_PHY_ZQ1PR0_ZSEGBYP_MASK
 #define DDR_PHY_ZQ1PR0_ZSEGBYP_DEFVAL                          0x000077BB
 #define DDR_PHY_ZQ1PR0_ZSEGBYP_SHIFT                           27
 #define DDR_PHY_ZQ1PR0_ZSEGBYP_MASK                            0x08000000U
@@ -13054,9 +13054,9 @@
 * VREF latch mode controls the mode in which the ZLE pin of the PVREF cell
     *  is driven by the PUB
 */
-#undef DDR_PHY_ZQ1PR0_ZLE_MODE_DEFVAL 
-#undef DDR_PHY_ZQ1PR0_ZLE_MODE_SHIFT 
-#undef DDR_PHY_ZQ1PR0_ZLE_MODE_MASK 
+#undef DDR_PHY_ZQ1PR0_ZLE_MODE_DEFVAL
+#undef DDR_PHY_ZQ1PR0_ZLE_MODE_SHIFT
+#undef DDR_PHY_ZQ1PR0_ZLE_MODE_MASK
 #define DDR_PHY_ZQ1PR0_ZLE_MODE_DEFVAL                         0x000077BB
 #define DDR_PHY_ZQ1PR0_ZLE_MODE_SHIFT                          25
 #define DDR_PHY_ZQ1PR0_ZLE_MODE_MASK                           0x06000000U
@@ -13064,9 +13064,9 @@
 /*
 * Termination adjustment
 */
-#undef DDR_PHY_ZQ1PR0_ODT_ADJUST_DEFVAL 
-#undef DDR_PHY_ZQ1PR0_ODT_ADJUST_SHIFT 
-#undef DDR_PHY_ZQ1PR0_ODT_ADJUST_MASK 
+#undef DDR_PHY_ZQ1PR0_ODT_ADJUST_DEFVAL
+#undef DDR_PHY_ZQ1PR0_ODT_ADJUST_SHIFT
+#undef DDR_PHY_ZQ1PR0_ODT_ADJUST_MASK
 #define DDR_PHY_ZQ1PR0_ODT_ADJUST_DEFVAL                       0x000077BB
 #define DDR_PHY_ZQ1PR0_ODT_ADJUST_SHIFT                        22
 #define DDR_PHY_ZQ1PR0_ODT_ADJUST_MASK                         0x01C00000U
@@ -13074,9 +13074,9 @@
 /*
 * Pulldown drive strength adjustment
 */
-#undef DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_DEFVAL 
-#undef DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_SHIFT 
-#undef DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_MASK 
+#undef DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_DEFVAL
+#undef DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_SHIFT
+#undef DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_MASK
 #define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_DEFVAL                    0x000077BB
 #define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_SHIFT                     19
 #define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_MASK                      0x00380000U
@@ -13084,9 +13084,9 @@
 /*
 * Pullup drive strength adjustment
 */
-#undef DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_DEFVAL 
-#undef DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_SHIFT 
-#undef DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_MASK 
+#undef DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_DEFVAL
+#undef DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_SHIFT
+#undef DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_MASK
 #define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_DEFVAL                    0x000077BB
 #define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_SHIFT                     16
 #define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_MASK                      0x00070000U
@@ -13094,9 +13094,9 @@
 /*
 * DRAM Impedance Divide Ratio
 */
-#undef DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_DEFVAL 
-#undef DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_SHIFT 
-#undef DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_MASK 
+#undef DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_DEFVAL
+#undef DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_SHIFT
+#undef DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_MASK
 #define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_DEFVAL                   0x000077BB
 #define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_SHIFT                    12
 #define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_MASK                     0x0000F000U
@@ -13104,9 +13104,9 @@
 /*
 * HOST Impedance Divide Ratio
 */
-#undef DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_DEFVAL 
-#undef DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_SHIFT 
-#undef DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_MASK 
+#undef DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_DEFVAL
+#undef DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_SHIFT
+#undef DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_MASK
 #define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_DEFVAL                   0x000077BB
 #define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_SHIFT                    8
 #define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_MASK                     0x00000F00U
@@ -13115,9 +13115,9 @@
 * Impedance Divide Ratio (pulldown drive calibration during asymmetric dri
     * ve strength calibration)
 */
-#undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_DEFVAL 
-#undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_SHIFT 
-#undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_MASK 
+#undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_DEFVAL
+#undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_SHIFT
+#undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_MASK
 #define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_DEFVAL                0x000077BB
 #define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_SHIFT                 4
 #define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_MASK                  0x000000F0U
@@ -13126,9 +13126,9 @@
 * Impedance Divide Ratio (pullup drive calibration during asymmetric drive
     *  strength calibration)
 */
-#undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_DEFVAL 
-#undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_SHIFT 
-#undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_MASK 
+#undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_DEFVAL
+#undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_SHIFT
+#undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_MASK
 #define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_DEFVAL                0x000077BB
 #define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_SHIFT                 0
 #define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_MASK                  0x0000000FU
@@ -13136,9 +13136,9 @@
 /*
 * Calibration Bypass
 */
-#undef DDR_PHY_DX0GCR0_CALBYP_DEFVAL 
-#undef DDR_PHY_DX0GCR0_CALBYP_SHIFT 
-#undef DDR_PHY_DX0GCR0_CALBYP_MASK 
+#undef DDR_PHY_DX0GCR0_CALBYP_DEFVAL
+#undef DDR_PHY_DX0GCR0_CALBYP_SHIFT
+#undef DDR_PHY_DX0GCR0_CALBYP_MASK
 #define DDR_PHY_DX0GCR0_CALBYP_DEFVAL                          0x40200204
 #define DDR_PHY_DX0GCR0_CALBYP_SHIFT                           31
 #define DDR_PHY_DX0GCR0_CALBYP_MASK                            0x80000000U
@@ -13146,9 +13146,9 @@
 /*
 * Master Delay Line Enable
 */
-#undef DDR_PHY_DX0GCR0_MDLEN_DEFVAL 
-#undef DDR_PHY_DX0GCR0_MDLEN_SHIFT 
-#undef DDR_PHY_DX0GCR0_MDLEN_MASK 
+#undef DDR_PHY_DX0GCR0_MDLEN_DEFVAL
+#undef DDR_PHY_DX0GCR0_MDLEN_SHIFT
+#undef DDR_PHY_DX0GCR0_MDLEN_MASK
 #define DDR_PHY_DX0GCR0_MDLEN_DEFVAL                           0x40200204
 #define DDR_PHY_DX0GCR0_MDLEN_SHIFT                            30
 #define DDR_PHY_DX0GCR0_MDLEN_MASK                             0x40000000U
@@ -13156,9 +13156,9 @@
 /*
 * Configurable ODT(TE) Phase Shift
 */
-#undef DDR_PHY_DX0GCR0_CODTSHFT_DEFVAL 
-#undef DDR_PHY_DX0GCR0_CODTSHFT_SHIFT 
-#undef DDR_PHY_DX0GCR0_CODTSHFT_MASK 
+#undef DDR_PHY_DX0GCR0_CODTSHFT_DEFVAL
+#undef DDR_PHY_DX0GCR0_CODTSHFT_SHIFT
+#undef DDR_PHY_DX0GCR0_CODTSHFT_MASK
 #define DDR_PHY_DX0GCR0_CODTSHFT_DEFVAL                        0x40200204
 #define DDR_PHY_DX0GCR0_CODTSHFT_SHIFT                         28
 #define DDR_PHY_DX0GCR0_CODTSHFT_MASK                          0x30000000U
@@ -13166,9 +13166,9 @@
 /*
 * DQS Duty Cycle Correction
 */
-#undef DDR_PHY_DX0GCR0_DQSDCC_DEFVAL 
-#undef DDR_PHY_DX0GCR0_DQSDCC_SHIFT 
-#undef DDR_PHY_DX0GCR0_DQSDCC_MASK 
+#undef DDR_PHY_DX0GCR0_DQSDCC_DEFVAL
+#undef DDR_PHY_DX0GCR0_DQSDCC_SHIFT
+#undef DDR_PHY_DX0GCR0_DQSDCC_MASK
 #define DDR_PHY_DX0GCR0_DQSDCC_DEFVAL                          0x40200204
 #define DDR_PHY_DX0GCR0_DQSDCC_SHIFT                           24
 #define DDR_PHY_DX0GCR0_DQSDCC_MASK                            0x0F000000U
@@ -13177,9 +13177,9 @@
 * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
     *  input for the respective bypte lane of the PHY
 */
-#undef DDR_PHY_DX0GCR0_RDDLY_DEFVAL 
-#undef DDR_PHY_DX0GCR0_RDDLY_SHIFT 
-#undef DDR_PHY_DX0GCR0_RDDLY_MASK 
+#undef DDR_PHY_DX0GCR0_RDDLY_DEFVAL
+#undef DDR_PHY_DX0GCR0_RDDLY_SHIFT
+#undef DDR_PHY_DX0GCR0_RDDLY_MASK
 #define DDR_PHY_DX0GCR0_RDDLY_DEFVAL                           0x40200204
 #define DDR_PHY_DX0GCR0_RDDLY_SHIFT                            20
 #define DDR_PHY_DX0GCR0_RDDLY_MASK                             0x00F00000U
@@ -13187,9 +13187,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX0GCR0_RESERVED_19_14_DEFVAL 
-#undef DDR_PHY_DX0GCR0_RESERVED_19_14_SHIFT 
-#undef DDR_PHY_DX0GCR0_RESERVED_19_14_MASK 
+#undef DDR_PHY_DX0GCR0_RESERVED_19_14_DEFVAL
+#undef DDR_PHY_DX0GCR0_RESERVED_19_14_SHIFT
+#undef DDR_PHY_DX0GCR0_RESERVED_19_14_MASK
 #define DDR_PHY_DX0GCR0_RESERVED_19_14_DEFVAL                  0x40200204
 #define DDR_PHY_DX0GCR0_RESERVED_19_14_SHIFT                   14
 #define DDR_PHY_DX0GCR0_RESERVED_19_14_MASK                    0x000FC000U
@@ -13197,9 +13197,9 @@
 /*
 * DQSNSE Power Down Receiver
 */
-#undef DDR_PHY_DX0GCR0_DQSNSEPDR_DEFVAL 
-#undef DDR_PHY_DX0GCR0_DQSNSEPDR_SHIFT 
-#undef DDR_PHY_DX0GCR0_DQSNSEPDR_MASK 
+#undef DDR_PHY_DX0GCR0_DQSNSEPDR_DEFVAL
+#undef DDR_PHY_DX0GCR0_DQSNSEPDR_SHIFT
+#undef DDR_PHY_DX0GCR0_DQSNSEPDR_MASK
 #define DDR_PHY_DX0GCR0_DQSNSEPDR_DEFVAL                       0x40200204
 #define DDR_PHY_DX0GCR0_DQSNSEPDR_SHIFT                        13
 #define DDR_PHY_DX0GCR0_DQSNSEPDR_MASK                         0x00002000U
@@ -13207,9 +13207,9 @@
 /*
 * DQSSE Power Down Receiver
 */
-#undef DDR_PHY_DX0GCR0_DQSSEPDR_DEFVAL 
-#undef DDR_PHY_DX0GCR0_DQSSEPDR_SHIFT 
-#undef DDR_PHY_DX0GCR0_DQSSEPDR_MASK 
+#undef DDR_PHY_DX0GCR0_DQSSEPDR_DEFVAL
+#undef DDR_PHY_DX0GCR0_DQSSEPDR_SHIFT
+#undef DDR_PHY_DX0GCR0_DQSSEPDR_MASK
 #define DDR_PHY_DX0GCR0_DQSSEPDR_DEFVAL                        0x40200204
 #define DDR_PHY_DX0GCR0_DQSSEPDR_SHIFT                         12
 #define DDR_PHY_DX0GCR0_DQSSEPDR_MASK                          0x00001000U
@@ -13217,9 +13217,9 @@
 /*
 * RTT On Additive Latency
 */
-#undef DDR_PHY_DX0GCR0_RTTOAL_DEFVAL 
-#undef DDR_PHY_DX0GCR0_RTTOAL_SHIFT 
-#undef DDR_PHY_DX0GCR0_RTTOAL_MASK 
+#undef DDR_PHY_DX0GCR0_RTTOAL_DEFVAL
+#undef DDR_PHY_DX0GCR0_RTTOAL_SHIFT
+#undef DDR_PHY_DX0GCR0_RTTOAL_MASK
 #define DDR_PHY_DX0GCR0_RTTOAL_DEFVAL                          0x40200204
 #define DDR_PHY_DX0GCR0_RTTOAL_SHIFT                           11
 #define DDR_PHY_DX0GCR0_RTTOAL_MASK                            0x00000800U
@@ -13227,9 +13227,9 @@
 /*
 * RTT Output Hold
 */
-#undef DDR_PHY_DX0GCR0_RTTOH_DEFVAL 
-#undef DDR_PHY_DX0GCR0_RTTOH_SHIFT 
-#undef DDR_PHY_DX0GCR0_RTTOH_MASK 
+#undef DDR_PHY_DX0GCR0_RTTOH_DEFVAL
+#undef DDR_PHY_DX0GCR0_RTTOH_SHIFT
+#undef DDR_PHY_DX0GCR0_RTTOH_MASK
 #define DDR_PHY_DX0GCR0_RTTOH_DEFVAL                           0x40200204
 #define DDR_PHY_DX0GCR0_RTTOH_SHIFT                            9
 #define DDR_PHY_DX0GCR0_RTTOH_MASK                             0x00000600U
@@ -13237,9 +13237,9 @@
 /*
 * Configurable PDR Phase Shift
 */
-#undef DDR_PHY_DX0GCR0_CPDRSHFT_DEFVAL 
-#undef DDR_PHY_DX0GCR0_CPDRSHFT_SHIFT 
-#undef DDR_PHY_DX0GCR0_CPDRSHFT_MASK 
+#undef DDR_PHY_DX0GCR0_CPDRSHFT_DEFVAL
+#undef DDR_PHY_DX0GCR0_CPDRSHFT_SHIFT
+#undef DDR_PHY_DX0GCR0_CPDRSHFT_MASK
 #define DDR_PHY_DX0GCR0_CPDRSHFT_DEFVAL                        0x40200204
 #define DDR_PHY_DX0GCR0_CPDRSHFT_SHIFT                         7
 #define DDR_PHY_DX0GCR0_CPDRSHFT_MASK                          0x00000180U
@@ -13247,9 +13247,9 @@
 /*
 * DQSR Power Down
 */
-#undef DDR_PHY_DX0GCR0_DQSRPD_DEFVAL 
-#undef DDR_PHY_DX0GCR0_DQSRPD_SHIFT 
-#undef DDR_PHY_DX0GCR0_DQSRPD_MASK 
+#undef DDR_PHY_DX0GCR0_DQSRPD_DEFVAL
+#undef DDR_PHY_DX0GCR0_DQSRPD_SHIFT
+#undef DDR_PHY_DX0GCR0_DQSRPD_MASK
 #define DDR_PHY_DX0GCR0_DQSRPD_DEFVAL                          0x40200204
 #define DDR_PHY_DX0GCR0_DQSRPD_SHIFT                           6
 #define DDR_PHY_DX0GCR0_DQSRPD_MASK                            0x00000040U
@@ -13257,9 +13257,9 @@
 /*
 * DQSG Power Down Receiver
 */
-#undef DDR_PHY_DX0GCR0_DQSGPDR_DEFVAL 
-#undef DDR_PHY_DX0GCR0_DQSGPDR_SHIFT 
-#undef DDR_PHY_DX0GCR0_DQSGPDR_MASK 
+#undef DDR_PHY_DX0GCR0_DQSGPDR_DEFVAL
+#undef DDR_PHY_DX0GCR0_DQSGPDR_SHIFT
+#undef DDR_PHY_DX0GCR0_DQSGPDR_MASK
 #define DDR_PHY_DX0GCR0_DQSGPDR_DEFVAL                         0x40200204
 #define DDR_PHY_DX0GCR0_DQSGPDR_SHIFT                          5
 #define DDR_PHY_DX0GCR0_DQSGPDR_MASK                           0x00000020U
@@ -13267,9 +13267,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX0GCR0_RESERVED_4_DEFVAL 
-#undef DDR_PHY_DX0GCR0_RESERVED_4_SHIFT 
-#undef DDR_PHY_DX0GCR0_RESERVED_4_MASK 
+#undef DDR_PHY_DX0GCR0_RESERVED_4_DEFVAL
+#undef DDR_PHY_DX0GCR0_RESERVED_4_SHIFT
+#undef DDR_PHY_DX0GCR0_RESERVED_4_MASK
 #define DDR_PHY_DX0GCR0_RESERVED_4_DEFVAL                      0x40200204
 #define DDR_PHY_DX0GCR0_RESERVED_4_SHIFT                       4
 #define DDR_PHY_DX0GCR0_RESERVED_4_MASK                        0x00000010U
@@ -13277,9 +13277,9 @@
 /*
 * DQSG On-Die Termination
 */
-#undef DDR_PHY_DX0GCR0_DQSGODT_DEFVAL 
-#undef DDR_PHY_DX0GCR0_DQSGODT_SHIFT 
-#undef DDR_PHY_DX0GCR0_DQSGODT_MASK 
+#undef DDR_PHY_DX0GCR0_DQSGODT_DEFVAL
+#undef DDR_PHY_DX0GCR0_DQSGODT_SHIFT
+#undef DDR_PHY_DX0GCR0_DQSGODT_MASK
 #define DDR_PHY_DX0GCR0_DQSGODT_DEFVAL                         0x40200204
 #define DDR_PHY_DX0GCR0_DQSGODT_SHIFT                          3
 #define DDR_PHY_DX0GCR0_DQSGODT_MASK                           0x00000008U
@@ -13287,9 +13287,9 @@
 /*
 * DQSG Output Enable
 */
-#undef DDR_PHY_DX0GCR0_DQSGOE_DEFVAL 
-#undef DDR_PHY_DX0GCR0_DQSGOE_SHIFT 
-#undef DDR_PHY_DX0GCR0_DQSGOE_MASK 
+#undef DDR_PHY_DX0GCR0_DQSGOE_DEFVAL
+#undef DDR_PHY_DX0GCR0_DQSGOE_SHIFT
+#undef DDR_PHY_DX0GCR0_DQSGOE_MASK
 #define DDR_PHY_DX0GCR0_DQSGOE_DEFVAL                          0x40200204
 #define DDR_PHY_DX0GCR0_DQSGOE_SHIFT                           2
 #define DDR_PHY_DX0GCR0_DQSGOE_MASK                            0x00000004U
@@ -13297,9 +13297,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX0GCR0_RESERVED_1_0_DEFVAL 
-#undef DDR_PHY_DX0GCR0_RESERVED_1_0_SHIFT 
-#undef DDR_PHY_DX0GCR0_RESERVED_1_0_MASK 
+#undef DDR_PHY_DX0GCR0_RESERVED_1_0_DEFVAL
+#undef DDR_PHY_DX0GCR0_RESERVED_1_0_SHIFT
+#undef DDR_PHY_DX0GCR0_RESERVED_1_0_MASK
 #define DDR_PHY_DX0GCR0_RESERVED_1_0_DEFVAL                    0x40200204
 #define DDR_PHY_DX0GCR0_RESERVED_1_0_SHIFT                     0
 #define DDR_PHY_DX0GCR0_RESERVED_1_0_MASK                      0x00000003U
@@ -13307,9 +13307,9 @@
 /*
 * Byte lane VREF IOM (Used only by D4MU IOs)
 */
-#undef DDR_PHY_DX0GCR4_RESERVED_31_29_DEFVAL 
-#undef DDR_PHY_DX0GCR4_RESERVED_31_29_SHIFT 
-#undef DDR_PHY_DX0GCR4_RESERVED_31_29_MASK 
+#undef DDR_PHY_DX0GCR4_RESERVED_31_29_DEFVAL
+#undef DDR_PHY_DX0GCR4_RESERVED_31_29_SHIFT
+#undef DDR_PHY_DX0GCR4_RESERVED_31_29_MASK
 #define DDR_PHY_DX0GCR4_RESERVED_31_29_DEFVAL                  0x0E00003C
 #define DDR_PHY_DX0GCR4_RESERVED_31_29_SHIFT                   29
 #define DDR_PHY_DX0GCR4_RESERVED_31_29_MASK                    0xE0000000U
@@ -13317,9 +13317,9 @@
 /*
 * Byte Lane VREF Pad Enable
 */
-#undef DDR_PHY_DX0GCR4_DXREFPEN_DEFVAL 
-#undef DDR_PHY_DX0GCR4_DXREFPEN_SHIFT 
-#undef DDR_PHY_DX0GCR4_DXREFPEN_MASK 
+#undef DDR_PHY_DX0GCR4_DXREFPEN_DEFVAL
+#undef DDR_PHY_DX0GCR4_DXREFPEN_SHIFT
+#undef DDR_PHY_DX0GCR4_DXREFPEN_MASK
 #define DDR_PHY_DX0GCR4_DXREFPEN_DEFVAL                        0x0E00003C
 #define DDR_PHY_DX0GCR4_DXREFPEN_SHIFT                         28
 #define DDR_PHY_DX0GCR4_DXREFPEN_MASK                          0x10000000U
@@ -13327,9 +13327,9 @@
 /*
 * Byte Lane Internal VREF Enable
 */
-#undef DDR_PHY_DX0GCR4_DXREFEEN_DEFVAL 
-#undef DDR_PHY_DX0GCR4_DXREFEEN_SHIFT 
-#undef DDR_PHY_DX0GCR4_DXREFEEN_MASK 
+#undef DDR_PHY_DX0GCR4_DXREFEEN_DEFVAL
+#undef DDR_PHY_DX0GCR4_DXREFEEN_SHIFT
+#undef DDR_PHY_DX0GCR4_DXREFEEN_MASK
 #define DDR_PHY_DX0GCR4_DXREFEEN_DEFVAL                        0x0E00003C
 #define DDR_PHY_DX0GCR4_DXREFEEN_SHIFT                         26
 #define DDR_PHY_DX0GCR4_DXREFEEN_MASK                          0x0C000000U
@@ -13337,9 +13337,9 @@
 /*
 * Byte Lane Single-End VREF Enable
 */
-#undef DDR_PHY_DX0GCR4_DXREFSEN_DEFVAL 
-#undef DDR_PHY_DX0GCR4_DXREFSEN_SHIFT 
-#undef DDR_PHY_DX0GCR4_DXREFSEN_MASK 
+#undef DDR_PHY_DX0GCR4_DXREFSEN_DEFVAL
+#undef DDR_PHY_DX0GCR4_DXREFSEN_SHIFT
+#undef DDR_PHY_DX0GCR4_DXREFSEN_MASK
 #define DDR_PHY_DX0GCR4_DXREFSEN_DEFVAL                        0x0E00003C
 #define DDR_PHY_DX0GCR4_DXREFSEN_SHIFT                         25
 #define DDR_PHY_DX0GCR4_DXREFSEN_MASK                          0x02000000U
@@ -13347,9 +13347,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX0GCR4_RESERVED_24_DEFVAL 
-#undef DDR_PHY_DX0GCR4_RESERVED_24_SHIFT 
-#undef DDR_PHY_DX0GCR4_RESERVED_24_MASK 
+#undef DDR_PHY_DX0GCR4_RESERVED_24_DEFVAL
+#undef DDR_PHY_DX0GCR4_RESERVED_24_SHIFT
+#undef DDR_PHY_DX0GCR4_RESERVED_24_MASK
 #define DDR_PHY_DX0GCR4_RESERVED_24_DEFVAL                     0x0E00003C
 #define DDR_PHY_DX0GCR4_RESERVED_24_SHIFT                      24
 #define DDR_PHY_DX0GCR4_RESERVED_24_MASK                       0x01000000U
@@ -13357,9 +13357,9 @@
 /*
 * External VREF generator REFSEL range select
 */
-#undef DDR_PHY_DX0GCR4_DXREFESELRANGE_DEFVAL 
-#undef DDR_PHY_DX0GCR4_DXREFESELRANGE_SHIFT 
-#undef DDR_PHY_DX0GCR4_DXREFESELRANGE_MASK 
+#undef DDR_PHY_DX0GCR4_DXREFESELRANGE_DEFVAL
+#undef DDR_PHY_DX0GCR4_DXREFESELRANGE_SHIFT
+#undef DDR_PHY_DX0GCR4_DXREFESELRANGE_MASK
 #define DDR_PHY_DX0GCR4_DXREFESELRANGE_DEFVAL                  0x0E00003C
 #define DDR_PHY_DX0GCR4_DXREFESELRANGE_SHIFT                   23
 #define DDR_PHY_DX0GCR4_DXREFESELRANGE_MASK                    0x00800000U
@@ -13367,9 +13367,9 @@
 /*
 * Byte Lane External VREF Select
 */
-#undef DDR_PHY_DX0GCR4_DXREFESEL_DEFVAL 
-#undef DDR_PHY_DX0GCR4_DXREFESEL_SHIFT 
-#undef DDR_PHY_DX0GCR4_DXREFESEL_MASK 
+#undef DDR_PHY_DX0GCR4_DXREFESEL_DEFVAL
+#undef DDR_PHY_DX0GCR4_DXREFESEL_SHIFT
+#undef DDR_PHY_DX0GCR4_DXREFESEL_MASK
 #define DDR_PHY_DX0GCR4_DXREFESEL_DEFVAL                       0x0E00003C
 #define DDR_PHY_DX0GCR4_DXREFESEL_SHIFT                        16
 #define DDR_PHY_DX0GCR4_DXREFESEL_MASK                         0x007F0000U
@@ -13377,9 +13377,9 @@
 /*
 * Single ended VREF generator REFSEL range select
 */
-#undef DDR_PHY_DX0GCR4_DXREFSSELRANGE_DEFVAL 
-#undef DDR_PHY_DX0GCR4_DXREFSSELRANGE_SHIFT 
-#undef DDR_PHY_DX0GCR4_DXREFSSELRANGE_MASK 
+#undef DDR_PHY_DX0GCR4_DXREFSSELRANGE_DEFVAL
+#undef DDR_PHY_DX0GCR4_DXREFSSELRANGE_SHIFT
+#undef DDR_PHY_DX0GCR4_DXREFSSELRANGE_MASK
 #define DDR_PHY_DX0GCR4_DXREFSSELRANGE_DEFVAL                  0x0E00003C
 #define DDR_PHY_DX0GCR4_DXREFSSELRANGE_SHIFT                   15
 #define DDR_PHY_DX0GCR4_DXREFSSELRANGE_MASK                    0x00008000U
@@ -13387,9 +13387,9 @@
 /*
 * Byte Lane Single-End VREF Select
 */
-#undef DDR_PHY_DX0GCR4_DXREFSSEL_DEFVAL 
-#undef DDR_PHY_DX0GCR4_DXREFSSEL_SHIFT 
-#undef DDR_PHY_DX0GCR4_DXREFSSEL_MASK 
+#undef DDR_PHY_DX0GCR4_DXREFSSEL_DEFVAL
+#undef DDR_PHY_DX0GCR4_DXREFSSEL_SHIFT
+#undef DDR_PHY_DX0GCR4_DXREFSSEL_MASK
 #define DDR_PHY_DX0GCR4_DXREFSSEL_DEFVAL                       0x0E00003C
 #define DDR_PHY_DX0GCR4_DXREFSSEL_SHIFT                        8
 #define DDR_PHY_DX0GCR4_DXREFSSEL_MASK                         0x00007F00U
@@ -13397,9 +13397,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX0GCR4_RESERVED_7_6_DEFVAL 
-#undef DDR_PHY_DX0GCR4_RESERVED_7_6_SHIFT 
-#undef DDR_PHY_DX0GCR4_RESERVED_7_6_MASK 
+#undef DDR_PHY_DX0GCR4_RESERVED_7_6_DEFVAL
+#undef DDR_PHY_DX0GCR4_RESERVED_7_6_SHIFT
+#undef DDR_PHY_DX0GCR4_RESERVED_7_6_MASK
 #define DDR_PHY_DX0GCR4_RESERVED_7_6_DEFVAL                    0x0E00003C
 #define DDR_PHY_DX0GCR4_RESERVED_7_6_SHIFT                     6
 #define DDR_PHY_DX0GCR4_RESERVED_7_6_MASK                      0x000000C0U
@@ -13407,9 +13407,9 @@
 /*
 * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
 */
-#undef DDR_PHY_DX0GCR4_DXREFIEN_DEFVAL 
-#undef DDR_PHY_DX0GCR4_DXREFIEN_SHIFT 
-#undef DDR_PHY_DX0GCR4_DXREFIEN_MASK 
+#undef DDR_PHY_DX0GCR4_DXREFIEN_DEFVAL
+#undef DDR_PHY_DX0GCR4_DXREFIEN_SHIFT
+#undef DDR_PHY_DX0GCR4_DXREFIEN_MASK
 #define DDR_PHY_DX0GCR4_DXREFIEN_DEFVAL                        0x0E00003C
 #define DDR_PHY_DX0GCR4_DXREFIEN_SHIFT                         2
 #define DDR_PHY_DX0GCR4_DXREFIEN_MASK                          0x0000003CU
@@ -13417,9 +13417,9 @@
 /*
 * VRMON control for DQ IO (Single Ended) buffers of a byte lane.
 */
-#undef DDR_PHY_DX0GCR4_DXREFIMON_DEFVAL 
-#undef DDR_PHY_DX0GCR4_DXREFIMON_SHIFT 
-#undef DDR_PHY_DX0GCR4_DXREFIMON_MASK 
+#undef DDR_PHY_DX0GCR4_DXREFIMON_DEFVAL
+#undef DDR_PHY_DX0GCR4_DXREFIMON_SHIFT
+#undef DDR_PHY_DX0GCR4_DXREFIMON_MASK
 #define DDR_PHY_DX0GCR4_DXREFIMON_DEFVAL                       0x0E00003C
 #define DDR_PHY_DX0GCR4_DXREFIMON_SHIFT                        0
 #define DDR_PHY_DX0GCR4_DXREFIMON_MASK                         0x00000003U
@@ -13427,9 +13427,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX0GCR5_RESERVED_31_DEFVAL 
-#undef DDR_PHY_DX0GCR5_RESERVED_31_SHIFT 
-#undef DDR_PHY_DX0GCR5_RESERVED_31_MASK 
+#undef DDR_PHY_DX0GCR5_RESERVED_31_DEFVAL
+#undef DDR_PHY_DX0GCR5_RESERVED_31_SHIFT
+#undef DDR_PHY_DX0GCR5_RESERVED_31_MASK
 #define DDR_PHY_DX0GCR5_RESERVED_31_DEFVAL                     0x09090909
 #define DDR_PHY_DX0GCR5_RESERVED_31_SHIFT                      31
 #define DDR_PHY_DX0GCR5_RESERVED_31_MASK                       0x80000000U
@@ -13437,9 +13437,9 @@
 /*
 * Byte Lane internal VREF Select for Rank 3
 */
-#undef DDR_PHY_DX0GCR5_DXREFISELR3_DEFVAL 
-#undef DDR_PHY_DX0GCR5_DXREFISELR3_SHIFT 
-#undef DDR_PHY_DX0GCR5_DXREFISELR3_MASK 
+#undef DDR_PHY_DX0GCR5_DXREFISELR3_DEFVAL
+#undef DDR_PHY_DX0GCR5_DXREFISELR3_SHIFT
+#undef DDR_PHY_DX0GCR5_DXREFISELR3_MASK
 #define DDR_PHY_DX0GCR5_DXREFISELR3_DEFVAL                     0x09090909
 #define DDR_PHY_DX0GCR5_DXREFISELR3_SHIFT                      24
 #define DDR_PHY_DX0GCR5_DXREFISELR3_MASK                       0x7F000000U
@@ -13447,9 +13447,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX0GCR5_RESERVED_23_DEFVAL 
-#undef DDR_PHY_DX0GCR5_RESERVED_23_SHIFT 
-#undef DDR_PHY_DX0GCR5_RESERVED_23_MASK 
+#undef DDR_PHY_DX0GCR5_RESERVED_23_DEFVAL
+#undef DDR_PHY_DX0GCR5_RESERVED_23_SHIFT
+#undef DDR_PHY_DX0GCR5_RESERVED_23_MASK
 #define DDR_PHY_DX0GCR5_RESERVED_23_DEFVAL                     0x09090909
 #define DDR_PHY_DX0GCR5_RESERVED_23_SHIFT                      23
 #define DDR_PHY_DX0GCR5_RESERVED_23_MASK                       0x00800000U
@@ -13457,9 +13457,9 @@
 /*
 * Byte Lane internal VREF Select for Rank 2
 */
-#undef DDR_PHY_DX0GCR5_DXREFISELR2_DEFVAL 
-#undef DDR_PHY_DX0GCR5_DXREFISELR2_SHIFT 
-#undef DDR_PHY_DX0GCR5_DXREFISELR2_MASK 
+#undef DDR_PHY_DX0GCR5_DXREFISELR2_DEFVAL
+#undef DDR_PHY_DX0GCR5_DXREFISELR2_SHIFT
+#undef DDR_PHY_DX0GCR5_DXREFISELR2_MASK
 #define DDR_PHY_DX0GCR5_DXREFISELR2_DEFVAL                     0x09090909
 #define DDR_PHY_DX0GCR5_DXREFISELR2_SHIFT                      16
 #define DDR_PHY_DX0GCR5_DXREFISELR2_MASK                       0x007F0000U
@@ -13467,9 +13467,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX0GCR5_RESERVED_15_DEFVAL 
-#undef DDR_PHY_DX0GCR5_RESERVED_15_SHIFT 
-#undef DDR_PHY_DX0GCR5_RESERVED_15_MASK 
+#undef DDR_PHY_DX0GCR5_RESERVED_15_DEFVAL
+#undef DDR_PHY_DX0GCR5_RESERVED_15_SHIFT
+#undef DDR_PHY_DX0GCR5_RESERVED_15_MASK
 #define DDR_PHY_DX0GCR5_RESERVED_15_DEFVAL                     0x09090909
 #define DDR_PHY_DX0GCR5_RESERVED_15_SHIFT                      15
 #define DDR_PHY_DX0GCR5_RESERVED_15_MASK                       0x00008000U
@@ -13477,9 +13477,9 @@
 /*
 * Byte Lane internal VREF Select for Rank 1
 */
-#undef DDR_PHY_DX0GCR5_DXREFISELR1_DEFVAL 
-#undef DDR_PHY_DX0GCR5_DXREFISELR1_SHIFT 
-#undef DDR_PHY_DX0GCR5_DXREFISELR1_MASK 
+#undef DDR_PHY_DX0GCR5_DXREFISELR1_DEFVAL
+#undef DDR_PHY_DX0GCR5_DXREFISELR1_SHIFT
+#undef DDR_PHY_DX0GCR5_DXREFISELR1_MASK
 #define DDR_PHY_DX0GCR5_DXREFISELR1_DEFVAL                     0x09090909
 #define DDR_PHY_DX0GCR5_DXREFISELR1_SHIFT                      8
 #define DDR_PHY_DX0GCR5_DXREFISELR1_MASK                       0x00007F00U
@@ -13487,9 +13487,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX0GCR5_RESERVED_7_DEFVAL 
-#undef DDR_PHY_DX0GCR5_RESERVED_7_SHIFT 
-#undef DDR_PHY_DX0GCR5_RESERVED_7_MASK 
+#undef DDR_PHY_DX0GCR5_RESERVED_7_DEFVAL
+#undef DDR_PHY_DX0GCR5_RESERVED_7_SHIFT
+#undef DDR_PHY_DX0GCR5_RESERVED_7_MASK
 #define DDR_PHY_DX0GCR5_RESERVED_7_DEFVAL                      0x09090909
 #define DDR_PHY_DX0GCR5_RESERVED_7_SHIFT                       7
 #define DDR_PHY_DX0GCR5_RESERVED_7_MASK                        0x00000080U
@@ -13497,9 +13497,9 @@
 /*
 * Byte Lane internal VREF Select for Rank 0
 */
-#undef DDR_PHY_DX0GCR5_DXREFISELR0_DEFVAL 
-#undef DDR_PHY_DX0GCR5_DXREFISELR0_SHIFT 
-#undef DDR_PHY_DX0GCR5_DXREFISELR0_MASK 
+#undef DDR_PHY_DX0GCR5_DXREFISELR0_DEFVAL
+#undef DDR_PHY_DX0GCR5_DXREFISELR0_SHIFT
+#undef DDR_PHY_DX0GCR5_DXREFISELR0_MASK
 #define DDR_PHY_DX0GCR5_DXREFISELR0_DEFVAL                     0x09090909
 #define DDR_PHY_DX0GCR5_DXREFISELR0_SHIFT                      0
 #define DDR_PHY_DX0GCR5_DXREFISELR0_MASK                       0x0000007FU
@@ -13507,9 +13507,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX0GCR6_RESERVED_31_30_DEFVAL 
-#undef DDR_PHY_DX0GCR6_RESERVED_31_30_SHIFT 
-#undef DDR_PHY_DX0GCR6_RESERVED_31_30_MASK 
+#undef DDR_PHY_DX0GCR6_RESERVED_31_30_DEFVAL
+#undef DDR_PHY_DX0GCR6_RESERVED_31_30_SHIFT
+#undef DDR_PHY_DX0GCR6_RESERVED_31_30_MASK
 #define DDR_PHY_DX0GCR6_RESERVED_31_30_DEFVAL                  0x09090909
 #define DDR_PHY_DX0GCR6_RESERVED_31_30_SHIFT                   30
 #define DDR_PHY_DX0GCR6_RESERVED_31_30_MASK                    0xC0000000U
@@ -13517,9 +13517,9 @@
 /*
 * DRAM DQ VREF Select for Rank3
 */
-#undef DDR_PHY_DX0GCR6_DXDQVREFR3_DEFVAL 
-#undef DDR_PHY_DX0GCR6_DXDQVREFR3_SHIFT 
-#undef DDR_PHY_DX0GCR6_DXDQVREFR3_MASK 
+#undef DDR_PHY_DX0GCR6_DXDQVREFR3_DEFVAL
+#undef DDR_PHY_DX0GCR6_DXDQVREFR3_SHIFT
+#undef DDR_PHY_DX0GCR6_DXDQVREFR3_MASK
 #define DDR_PHY_DX0GCR6_DXDQVREFR3_DEFVAL                      0x09090909
 #define DDR_PHY_DX0GCR6_DXDQVREFR3_SHIFT                       24
 #define DDR_PHY_DX0GCR6_DXDQVREFR3_MASK                        0x3F000000U
@@ -13527,9 +13527,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX0GCR6_RESERVED_23_22_DEFVAL 
-#undef DDR_PHY_DX0GCR6_RESERVED_23_22_SHIFT 
-#undef DDR_PHY_DX0GCR6_RESERVED_23_22_MASK 
+#undef DDR_PHY_DX0GCR6_RESERVED_23_22_DEFVAL
+#undef DDR_PHY_DX0GCR6_RESERVED_23_22_SHIFT
+#undef DDR_PHY_DX0GCR6_RESERVED_23_22_MASK
 #define DDR_PHY_DX0GCR6_RESERVED_23_22_DEFVAL                  0x09090909
 #define DDR_PHY_DX0GCR6_RESERVED_23_22_SHIFT                   22
 #define DDR_PHY_DX0GCR6_RESERVED_23_22_MASK                    0x00C00000U
@@ -13537,9 +13537,9 @@
 /*
 * DRAM DQ VREF Select for Rank2
 */
-#undef DDR_PHY_DX0GCR6_DXDQVREFR2_DEFVAL 
-#undef DDR_PHY_DX0GCR6_DXDQVREFR2_SHIFT 
-#undef DDR_PHY_DX0GCR6_DXDQVREFR2_MASK 
+#undef DDR_PHY_DX0GCR6_DXDQVREFR2_DEFVAL
+#undef DDR_PHY_DX0GCR6_DXDQVREFR2_SHIFT
+#undef DDR_PHY_DX0GCR6_DXDQVREFR2_MASK
 #define DDR_PHY_DX0GCR6_DXDQVREFR2_DEFVAL                      0x09090909
 #define DDR_PHY_DX0GCR6_DXDQVREFR2_SHIFT                       16
 #define DDR_PHY_DX0GCR6_DXDQVREFR2_MASK                        0x003F0000U
@@ -13547,9 +13547,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX0GCR6_RESERVED_15_14_DEFVAL 
-#undef DDR_PHY_DX0GCR6_RESERVED_15_14_SHIFT 
-#undef DDR_PHY_DX0GCR6_RESERVED_15_14_MASK 
+#undef DDR_PHY_DX0GCR6_RESERVED_15_14_DEFVAL
+#undef DDR_PHY_DX0GCR6_RESERVED_15_14_SHIFT
+#undef DDR_PHY_DX0GCR6_RESERVED_15_14_MASK
 #define DDR_PHY_DX0GCR6_RESERVED_15_14_DEFVAL                  0x09090909
 #define DDR_PHY_DX0GCR6_RESERVED_15_14_SHIFT                   14
 #define DDR_PHY_DX0GCR6_RESERVED_15_14_MASK                    0x0000C000U
@@ -13557,9 +13557,9 @@
 /*
 * DRAM DQ VREF Select for Rank1
 */
-#undef DDR_PHY_DX0GCR6_DXDQVREFR1_DEFVAL 
-#undef DDR_PHY_DX0GCR6_DXDQVREFR1_SHIFT 
-#undef DDR_PHY_DX0GCR6_DXDQVREFR1_MASK 
+#undef DDR_PHY_DX0GCR6_DXDQVREFR1_DEFVAL
+#undef DDR_PHY_DX0GCR6_DXDQVREFR1_SHIFT
+#undef DDR_PHY_DX0GCR6_DXDQVREFR1_MASK
 #define DDR_PHY_DX0GCR6_DXDQVREFR1_DEFVAL                      0x09090909
 #define DDR_PHY_DX0GCR6_DXDQVREFR1_SHIFT                       8
 #define DDR_PHY_DX0GCR6_DXDQVREFR1_MASK                        0x00003F00U
@@ -13567,9 +13567,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX0GCR6_RESERVED_7_6_DEFVAL 
-#undef DDR_PHY_DX0GCR6_RESERVED_7_6_SHIFT 
-#undef DDR_PHY_DX0GCR6_RESERVED_7_6_MASK 
+#undef DDR_PHY_DX0GCR6_RESERVED_7_6_DEFVAL
+#undef DDR_PHY_DX0GCR6_RESERVED_7_6_SHIFT
+#undef DDR_PHY_DX0GCR6_RESERVED_7_6_MASK
 #define DDR_PHY_DX0GCR6_RESERVED_7_6_DEFVAL                    0x09090909
 #define DDR_PHY_DX0GCR6_RESERVED_7_6_SHIFT                     6
 #define DDR_PHY_DX0GCR6_RESERVED_7_6_MASK                      0x000000C0U
@@ -13577,9 +13577,9 @@
 /*
 * DRAM DQ VREF Select for Rank0
 */
-#undef DDR_PHY_DX0GCR6_DXDQVREFR0_DEFVAL 
-#undef DDR_PHY_DX0GCR6_DXDQVREFR0_SHIFT 
-#undef DDR_PHY_DX0GCR6_DXDQVREFR0_MASK 
+#undef DDR_PHY_DX0GCR6_DXDQVREFR0_DEFVAL
+#undef DDR_PHY_DX0GCR6_DXDQVREFR0_SHIFT
+#undef DDR_PHY_DX0GCR6_DXDQVREFR0_MASK
 #define DDR_PHY_DX0GCR6_DXDQVREFR0_DEFVAL                      0x09090909
 #define DDR_PHY_DX0GCR6_DXDQVREFR0_SHIFT                       0
 #define DDR_PHY_DX0GCR6_DXDQVREFR0_MASK                        0x0000003FU
@@ -13587,9 +13587,9 @@
 /*
 * Calibration Bypass
 */
-#undef DDR_PHY_DX1GCR0_CALBYP_DEFVAL 
-#undef DDR_PHY_DX1GCR0_CALBYP_SHIFT 
-#undef DDR_PHY_DX1GCR0_CALBYP_MASK 
+#undef DDR_PHY_DX1GCR0_CALBYP_DEFVAL
+#undef DDR_PHY_DX1GCR0_CALBYP_SHIFT
+#undef DDR_PHY_DX1GCR0_CALBYP_MASK
 #define DDR_PHY_DX1GCR0_CALBYP_DEFVAL                          0x40200204
 #define DDR_PHY_DX1GCR0_CALBYP_SHIFT                           31
 #define DDR_PHY_DX1GCR0_CALBYP_MASK                            0x80000000U
@@ -13597,9 +13597,9 @@
 /*
 * Master Delay Line Enable
 */
-#undef DDR_PHY_DX1GCR0_MDLEN_DEFVAL 
-#undef DDR_PHY_DX1GCR0_MDLEN_SHIFT 
-#undef DDR_PHY_DX1GCR0_MDLEN_MASK 
+#undef DDR_PHY_DX1GCR0_MDLEN_DEFVAL
+#undef DDR_PHY_DX1GCR0_MDLEN_SHIFT
+#undef DDR_PHY_DX1GCR0_MDLEN_MASK
 #define DDR_PHY_DX1GCR0_MDLEN_DEFVAL                           0x40200204
 #define DDR_PHY_DX1GCR0_MDLEN_SHIFT                            30
 #define DDR_PHY_DX1GCR0_MDLEN_MASK                             0x40000000U
@@ -13607,9 +13607,9 @@
 /*
 * Configurable ODT(TE) Phase Shift
 */
-#undef DDR_PHY_DX1GCR0_CODTSHFT_DEFVAL 
-#undef DDR_PHY_DX1GCR0_CODTSHFT_SHIFT 
-#undef DDR_PHY_DX1GCR0_CODTSHFT_MASK 
+#undef DDR_PHY_DX1GCR0_CODTSHFT_DEFVAL
+#undef DDR_PHY_DX1GCR0_CODTSHFT_SHIFT
+#undef DDR_PHY_DX1GCR0_CODTSHFT_MASK
 #define DDR_PHY_DX1GCR0_CODTSHFT_DEFVAL                        0x40200204
 #define DDR_PHY_DX1GCR0_CODTSHFT_SHIFT                         28
 #define DDR_PHY_DX1GCR0_CODTSHFT_MASK                          0x30000000U
@@ -13617,9 +13617,9 @@
 /*
 * DQS Duty Cycle Correction
 */
-#undef DDR_PHY_DX1GCR0_DQSDCC_DEFVAL 
-#undef DDR_PHY_DX1GCR0_DQSDCC_SHIFT 
-#undef DDR_PHY_DX1GCR0_DQSDCC_MASK 
+#undef DDR_PHY_DX1GCR0_DQSDCC_DEFVAL
+#undef DDR_PHY_DX1GCR0_DQSDCC_SHIFT
+#undef DDR_PHY_DX1GCR0_DQSDCC_MASK
 #define DDR_PHY_DX1GCR0_DQSDCC_DEFVAL                          0x40200204
 #define DDR_PHY_DX1GCR0_DQSDCC_SHIFT                           24
 #define DDR_PHY_DX1GCR0_DQSDCC_MASK                            0x0F000000U
@@ -13628,9 +13628,9 @@
 * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
     *  input for the respective bypte lane of the PHY
 */
-#undef DDR_PHY_DX1GCR0_RDDLY_DEFVAL 
-#undef DDR_PHY_DX1GCR0_RDDLY_SHIFT 
-#undef DDR_PHY_DX1GCR0_RDDLY_MASK 
+#undef DDR_PHY_DX1GCR0_RDDLY_DEFVAL
+#undef DDR_PHY_DX1GCR0_RDDLY_SHIFT
+#undef DDR_PHY_DX1GCR0_RDDLY_MASK
 #define DDR_PHY_DX1GCR0_RDDLY_DEFVAL                           0x40200204
 #define DDR_PHY_DX1GCR0_RDDLY_SHIFT                            20
 #define DDR_PHY_DX1GCR0_RDDLY_MASK                             0x00F00000U
@@ -13638,9 +13638,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX1GCR0_RESERVED_19_14_DEFVAL 
-#undef DDR_PHY_DX1GCR0_RESERVED_19_14_SHIFT 
-#undef DDR_PHY_DX1GCR0_RESERVED_19_14_MASK 
+#undef DDR_PHY_DX1GCR0_RESERVED_19_14_DEFVAL
+#undef DDR_PHY_DX1GCR0_RESERVED_19_14_SHIFT
+#undef DDR_PHY_DX1GCR0_RESERVED_19_14_MASK
 #define DDR_PHY_DX1GCR0_RESERVED_19_14_DEFVAL                  0x40200204
 #define DDR_PHY_DX1GCR0_RESERVED_19_14_SHIFT                   14
 #define DDR_PHY_DX1GCR0_RESERVED_19_14_MASK                    0x000FC000U
@@ -13648,9 +13648,9 @@
 /*
 * DQSNSE Power Down Receiver
 */
-#undef DDR_PHY_DX1GCR0_DQSNSEPDR_DEFVAL 
-#undef DDR_PHY_DX1GCR0_DQSNSEPDR_SHIFT 
-#undef DDR_PHY_DX1GCR0_DQSNSEPDR_MASK 
+#undef DDR_PHY_DX1GCR0_DQSNSEPDR_DEFVAL
+#undef DDR_PHY_DX1GCR0_DQSNSEPDR_SHIFT
+#undef DDR_PHY_DX1GCR0_DQSNSEPDR_MASK
 #define DDR_PHY_DX1GCR0_DQSNSEPDR_DEFVAL                       0x40200204
 #define DDR_PHY_DX1GCR0_DQSNSEPDR_SHIFT                        13
 #define DDR_PHY_DX1GCR0_DQSNSEPDR_MASK                         0x00002000U
@@ -13658,9 +13658,9 @@
 /*
 * DQSSE Power Down Receiver
 */
-#undef DDR_PHY_DX1GCR0_DQSSEPDR_DEFVAL 
-#undef DDR_PHY_DX1GCR0_DQSSEPDR_SHIFT 
-#undef DDR_PHY_DX1GCR0_DQSSEPDR_MASK 
+#undef DDR_PHY_DX1GCR0_DQSSEPDR_DEFVAL
+#undef DDR_PHY_DX1GCR0_DQSSEPDR_SHIFT
+#undef DDR_PHY_DX1GCR0_DQSSEPDR_MASK
 #define DDR_PHY_DX1GCR0_DQSSEPDR_DEFVAL                        0x40200204
 #define DDR_PHY_DX1GCR0_DQSSEPDR_SHIFT                         12
 #define DDR_PHY_DX1GCR0_DQSSEPDR_MASK                          0x00001000U
@@ -13668,9 +13668,9 @@
 /*
 * RTT On Additive Latency
 */
-#undef DDR_PHY_DX1GCR0_RTTOAL_DEFVAL 
-#undef DDR_PHY_DX1GCR0_RTTOAL_SHIFT 
-#undef DDR_PHY_DX1GCR0_RTTOAL_MASK 
+#undef DDR_PHY_DX1GCR0_RTTOAL_DEFVAL
+#undef DDR_PHY_DX1GCR0_RTTOAL_SHIFT
+#undef DDR_PHY_DX1GCR0_RTTOAL_MASK
 #define DDR_PHY_DX1GCR0_RTTOAL_DEFVAL                          0x40200204
 #define DDR_PHY_DX1GCR0_RTTOAL_SHIFT                           11
 #define DDR_PHY_DX1GCR0_RTTOAL_MASK                            0x00000800U
@@ -13678,9 +13678,9 @@
 /*
 * RTT Output Hold
 */
-#undef DDR_PHY_DX1GCR0_RTTOH_DEFVAL 
-#undef DDR_PHY_DX1GCR0_RTTOH_SHIFT 
-#undef DDR_PHY_DX1GCR0_RTTOH_MASK 
+#undef DDR_PHY_DX1GCR0_RTTOH_DEFVAL
+#undef DDR_PHY_DX1GCR0_RTTOH_SHIFT
+#undef DDR_PHY_DX1GCR0_RTTOH_MASK
 #define DDR_PHY_DX1GCR0_RTTOH_DEFVAL                           0x40200204
 #define DDR_PHY_DX1GCR0_RTTOH_SHIFT                            9
 #define DDR_PHY_DX1GCR0_RTTOH_MASK                             0x00000600U
@@ -13688,9 +13688,9 @@
 /*
 * Configurable PDR Phase Shift
 */
-#undef DDR_PHY_DX1GCR0_CPDRSHFT_DEFVAL 
-#undef DDR_PHY_DX1GCR0_CPDRSHFT_SHIFT 
-#undef DDR_PHY_DX1GCR0_CPDRSHFT_MASK 
+#undef DDR_PHY_DX1GCR0_CPDRSHFT_DEFVAL
+#undef DDR_PHY_DX1GCR0_CPDRSHFT_SHIFT
+#undef DDR_PHY_DX1GCR0_CPDRSHFT_MASK
 #define DDR_PHY_DX1GCR0_CPDRSHFT_DEFVAL                        0x40200204
 #define DDR_PHY_DX1GCR0_CPDRSHFT_SHIFT                         7
 #define DDR_PHY_DX1GCR0_CPDRSHFT_MASK                          0x00000180U
@@ -13698,9 +13698,9 @@
 /*
 * DQSR Power Down
 */
-#undef DDR_PHY_DX1GCR0_DQSRPD_DEFVAL 
-#undef DDR_PHY_DX1GCR0_DQSRPD_SHIFT 
-#undef DDR_PHY_DX1GCR0_DQSRPD_MASK 
+#undef DDR_PHY_DX1GCR0_DQSRPD_DEFVAL
+#undef DDR_PHY_DX1GCR0_DQSRPD_SHIFT
+#undef DDR_PHY_DX1GCR0_DQSRPD_MASK
 #define DDR_PHY_DX1GCR0_DQSRPD_DEFVAL                          0x40200204
 #define DDR_PHY_DX1GCR0_DQSRPD_SHIFT                           6
 #define DDR_PHY_DX1GCR0_DQSRPD_MASK                            0x00000040U
@@ -13708,9 +13708,9 @@
 /*
 * DQSG Power Down Receiver
 */
-#undef DDR_PHY_DX1GCR0_DQSGPDR_DEFVAL 
-#undef DDR_PHY_DX1GCR0_DQSGPDR_SHIFT 
-#undef DDR_PHY_DX1GCR0_DQSGPDR_MASK 
+#undef DDR_PHY_DX1GCR0_DQSGPDR_DEFVAL
+#undef DDR_PHY_DX1GCR0_DQSGPDR_SHIFT
+#undef DDR_PHY_DX1GCR0_DQSGPDR_MASK
 #define DDR_PHY_DX1GCR0_DQSGPDR_DEFVAL                         0x40200204
 #define DDR_PHY_DX1GCR0_DQSGPDR_SHIFT                          5
 #define DDR_PHY_DX1GCR0_DQSGPDR_MASK                           0x00000020U
@@ -13718,9 +13718,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX1GCR0_RESERVED_4_DEFVAL 
-#undef DDR_PHY_DX1GCR0_RESERVED_4_SHIFT 
-#undef DDR_PHY_DX1GCR0_RESERVED_4_MASK 
+#undef DDR_PHY_DX1GCR0_RESERVED_4_DEFVAL
+#undef DDR_PHY_DX1GCR0_RESERVED_4_SHIFT
+#undef DDR_PHY_DX1GCR0_RESERVED_4_MASK
 #define DDR_PHY_DX1GCR0_RESERVED_4_DEFVAL                      0x40200204
 #define DDR_PHY_DX1GCR0_RESERVED_4_SHIFT                       4
 #define DDR_PHY_DX1GCR0_RESERVED_4_MASK                        0x00000010U
@@ -13728,9 +13728,9 @@
 /*
 * DQSG On-Die Termination
 */
-#undef DDR_PHY_DX1GCR0_DQSGODT_DEFVAL 
-#undef DDR_PHY_DX1GCR0_DQSGODT_SHIFT 
-#undef DDR_PHY_DX1GCR0_DQSGODT_MASK 
+#undef DDR_PHY_DX1GCR0_DQSGODT_DEFVAL
+#undef DDR_PHY_DX1GCR0_DQSGODT_SHIFT
+#undef DDR_PHY_DX1GCR0_DQSGODT_MASK
 #define DDR_PHY_DX1GCR0_DQSGODT_DEFVAL                         0x40200204
 #define DDR_PHY_DX1GCR0_DQSGODT_SHIFT                          3
 #define DDR_PHY_DX1GCR0_DQSGODT_MASK                           0x00000008U
@@ -13738,9 +13738,9 @@
 /*
 * DQSG Output Enable
 */
-#undef DDR_PHY_DX1GCR0_DQSGOE_DEFVAL 
-#undef DDR_PHY_DX1GCR0_DQSGOE_SHIFT 
-#undef DDR_PHY_DX1GCR0_DQSGOE_MASK 
+#undef DDR_PHY_DX1GCR0_DQSGOE_DEFVAL
+#undef DDR_PHY_DX1GCR0_DQSGOE_SHIFT
+#undef DDR_PHY_DX1GCR0_DQSGOE_MASK
 #define DDR_PHY_DX1GCR0_DQSGOE_DEFVAL                          0x40200204
 #define DDR_PHY_DX1GCR0_DQSGOE_SHIFT                           2
 #define DDR_PHY_DX1GCR0_DQSGOE_MASK                            0x00000004U
@@ -13748,9 +13748,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX1GCR0_RESERVED_1_0_DEFVAL 
-#undef DDR_PHY_DX1GCR0_RESERVED_1_0_SHIFT 
-#undef DDR_PHY_DX1GCR0_RESERVED_1_0_MASK 
+#undef DDR_PHY_DX1GCR0_RESERVED_1_0_DEFVAL
+#undef DDR_PHY_DX1GCR0_RESERVED_1_0_SHIFT
+#undef DDR_PHY_DX1GCR0_RESERVED_1_0_MASK
 #define DDR_PHY_DX1GCR0_RESERVED_1_0_DEFVAL                    0x40200204
 #define DDR_PHY_DX1GCR0_RESERVED_1_0_SHIFT                     0
 #define DDR_PHY_DX1GCR0_RESERVED_1_0_MASK                      0x00000003U
@@ -13758,9 +13758,9 @@
 /*
 * Byte lane VREF IOM (Used only by D4MU IOs)
 */
-#undef DDR_PHY_DX1GCR4_RESERVED_31_29_DEFVAL 
-#undef DDR_PHY_DX1GCR4_RESERVED_31_29_SHIFT 
-#undef DDR_PHY_DX1GCR4_RESERVED_31_29_MASK 
+#undef DDR_PHY_DX1GCR4_RESERVED_31_29_DEFVAL
+#undef DDR_PHY_DX1GCR4_RESERVED_31_29_SHIFT
+#undef DDR_PHY_DX1GCR4_RESERVED_31_29_MASK
 #define DDR_PHY_DX1GCR4_RESERVED_31_29_DEFVAL                  0x0E00003C
 #define DDR_PHY_DX1GCR4_RESERVED_31_29_SHIFT                   29
 #define DDR_PHY_DX1GCR4_RESERVED_31_29_MASK                    0xE0000000U
@@ -13768,9 +13768,9 @@
 /*
 * Byte Lane VREF Pad Enable
 */
-#undef DDR_PHY_DX1GCR4_DXREFPEN_DEFVAL 
-#undef DDR_PHY_DX1GCR4_DXREFPEN_SHIFT 
-#undef DDR_PHY_DX1GCR4_DXREFPEN_MASK 
+#undef DDR_PHY_DX1GCR4_DXREFPEN_DEFVAL
+#undef DDR_PHY_DX1GCR4_DXREFPEN_SHIFT
+#undef DDR_PHY_DX1GCR4_DXREFPEN_MASK
 #define DDR_PHY_DX1GCR4_DXREFPEN_DEFVAL                        0x0E00003C
 #define DDR_PHY_DX1GCR4_DXREFPEN_SHIFT                         28
 #define DDR_PHY_DX1GCR4_DXREFPEN_MASK                          0x10000000U
@@ -13778,9 +13778,9 @@
 /*
 * Byte Lane Internal VREF Enable
 */
-#undef DDR_PHY_DX1GCR4_DXREFEEN_DEFVAL 
-#undef DDR_PHY_DX1GCR4_DXREFEEN_SHIFT 
-#undef DDR_PHY_DX1GCR4_DXREFEEN_MASK 
+#undef DDR_PHY_DX1GCR4_DXREFEEN_DEFVAL
+#undef DDR_PHY_DX1GCR4_DXREFEEN_SHIFT
+#undef DDR_PHY_DX1GCR4_DXREFEEN_MASK
 #define DDR_PHY_DX1GCR4_DXREFEEN_DEFVAL                        0x0E00003C
 #define DDR_PHY_DX1GCR4_DXREFEEN_SHIFT                         26
 #define DDR_PHY_DX1GCR4_DXREFEEN_MASK                          0x0C000000U
@@ -13788,9 +13788,9 @@
 /*
 * Byte Lane Single-End VREF Enable
 */
-#undef DDR_PHY_DX1GCR4_DXREFSEN_DEFVAL 
-#undef DDR_PHY_DX1GCR4_DXREFSEN_SHIFT 
-#undef DDR_PHY_DX1GCR4_DXREFSEN_MASK 
+#undef DDR_PHY_DX1GCR4_DXREFSEN_DEFVAL
+#undef DDR_PHY_DX1GCR4_DXREFSEN_SHIFT
+#undef DDR_PHY_DX1GCR4_DXREFSEN_MASK
 #define DDR_PHY_DX1GCR4_DXREFSEN_DEFVAL                        0x0E00003C
 #define DDR_PHY_DX1GCR4_DXREFSEN_SHIFT                         25
 #define DDR_PHY_DX1GCR4_DXREFSEN_MASK                          0x02000000U
@@ -13798,9 +13798,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX1GCR4_RESERVED_24_DEFVAL 
-#undef DDR_PHY_DX1GCR4_RESERVED_24_SHIFT 
-#undef DDR_PHY_DX1GCR4_RESERVED_24_MASK 
+#undef DDR_PHY_DX1GCR4_RESERVED_24_DEFVAL
+#undef DDR_PHY_DX1GCR4_RESERVED_24_SHIFT
+#undef DDR_PHY_DX1GCR4_RESERVED_24_MASK
 #define DDR_PHY_DX1GCR4_RESERVED_24_DEFVAL                     0x0E00003C
 #define DDR_PHY_DX1GCR4_RESERVED_24_SHIFT                      24
 #define DDR_PHY_DX1GCR4_RESERVED_24_MASK                       0x01000000U
@@ -13808,9 +13808,9 @@
 /*
 * External VREF generator REFSEL range select
 */
-#undef DDR_PHY_DX1GCR4_DXREFESELRANGE_DEFVAL 
-#undef DDR_PHY_DX1GCR4_DXREFESELRANGE_SHIFT 
-#undef DDR_PHY_DX1GCR4_DXREFESELRANGE_MASK 
+#undef DDR_PHY_DX1GCR4_DXREFESELRANGE_DEFVAL
+#undef DDR_PHY_DX1GCR4_DXREFESELRANGE_SHIFT
+#undef DDR_PHY_DX1GCR4_DXREFESELRANGE_MASK
 #define DDR_PHY_DX1GCR4_DXREFESELRANGE_DEFVAL                  0x0E00003C
 #define DDR_PHY_DX1GCR4_DXREFESELRANGE_SHIFT                   23
 #define DDR_PHY_DX1GCR4_DXREFESELRANGE_MASK                    0x00800000U
@@ -13818,9 +13818,9 @@
 /*
 * Byte Lane External VREF Select
 */
-#undef DDR_PHY_DX1GCR4_DXREFESEL_DEFVAL 
-#undef DDR_PHY_DX1GCR4_DXREFESEL_SHIFT 
-#undef DDR_PHY_DX1GCR4_DXREFESEL_MASK 
+#undef DDR_PHY_DX1GCR4_DXREFESEL_DEFVAL
+#undef DDR_PHY_DX1GCR4_DXREFESEL_SHIFT
+#undef DDR_PHY_DX1GCR4_DXREFESEL_MASK
 #define DDR_PHY_DX1GCR4_DXREFESEL_DEFVAL                       0x0E00003C
 #define DDR_PHY_DX1GCR4_DXREFESEL_SHIFT                        16
 #define DDR_PHY_DX1GCR4_DXREFESEL_MASK                         0x007F0000U
@@ -13828,9 +13828,9 @@
 /*
 * Single ended VREF generator REFSEL range select
 */
-#undef DDR_PHY_DX1GCR4_DXREFSSELRANGE_DEFVAL 
-#undef DDR_PHY_DX1GCR4_DXREFSSELRANGE_SHIFT 
-#undef DDR_PHY_DX1GCR4_DXREFSSELRANGE_MASK 
+#undef DDR_PHY_DX1GCR4_DXREFSSELRANGE_DEFVAL
+#undef DDR_PHY_DX1GCR4_DXREFSSELRANGE_SHIFT
+#undef DDR_PHY_DX1GCR4_DXREFSSELRANGE_MASK
 #define DDR_PHY_DX1GCR4_DXREFSSELRANGE_DEFVAL                  0x0E00003C
 #define DDR_PHY_DX1GCR4_DXREFSSELRANGE_SHIFT                   15
 #define DDR_PHY_DX1GCR4_DXREFSSELRANGE_MASK                    0x00008000U
@@ -13838,9 +13838,9 @@
 /*
 * Byte Lane Single-End VREF Select
 */
-#undef DDR_PHY_DX1GCR4_DXREFSSEL_DEFVAL 
-#undef DDR_PHY_DX1GCR4_DXREFSSEL_SHIFT 
-#undef DDR_PHY_DX1GCR4_DXREFSSEL_MASK 
+#undef DDR_PHY_DX1GCR4_DXREFSSEL_DEFVAL
+#undef DDR_PHY_DX1GCR4_DXREFSSEL_SHIFT
+#undef DDR_PHY_DX1GCR4_DXREFSSEL_MASK
 #define DDR_PHY_DX1GCR4_DXREFSSEL_DEFVAL                       0x0E00003C
 #define DDR_PHY_DX1GCR4_DXREFSSEL_SHIFT                        8
 #define DDR_PHY_DX1GCR4_DXREFSSEL_MASK                         0x00007F00U
@@ -13848,9 +13848,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX1GCR4_RESERVED_7_6_DEFVAL 
-#undef DDR_PHY_DX1GCR4_RESERVED_7_6_SHIFT 
-#undef DDR_PHY_DX1GCR4_RESERVED_7_6_MASK 
+#undef DDR_PHY_DX1GCR4_RESERVED_7_6_DEFVAL
+#undef DDR_PHY_DX1GCR4_RESERVED_7_6_SHIFT
+#undef DDR_PHY_DX1GCR4_RESERVED_7_6_MASK
 #define DDR_PHY_DX1GCR4_RESERVED_7_6_DEFVAL                    0x0E00003C
 #define DDR_PHY_DX1GCR4_RESERVED_7_6_SHIFT                     6
 #define DDR_PHY_DX1GCR4_RESERVED_7_6_MASK                      0x000000C0U
@@ -13858,9 +13858,9 @@
 /*
 * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
 */
-#undef DDR_PHY_DX1GCR4_DXREFIEN_DEFVAL 
-#undef DDR_PHY_DX1GCR4_DXREFIEN_SHIFT 
-#undef DDR_PHY_DX1GCR4_DXREFIEN_MASK 
+#undef DDR_PHY_DX1GCR4_DXREFIEN_DEFVAL
+#undef DDR_PHY_DX1GCR4_DXREFIEN_SHIFT
+#undef DDR_PHY_DX1GCR4_DXREFIEN_MASK
 #define DDR_PHY_DX1GCR4_DXREFIEN_DEFVAL                        0x0E00003C
 #define DDR_PHY_DX1GCR4_DXREFIEN_SHIFT                         2
 #define DDR_PHY_DX1GCR4_DXREFIEN_MASK                          0x0000003CU
@@ -13868,9 +13868,9 @@
 /*
 * VRMON control for DQ IO (Single Ended) buffers of a byte lane.
 */
-#undef DDR_PHY_DX1GCR4_DXREFIMON_DEFVAL 
-#undef DDR_PHY_DX1GCR4_DXREFIMON_SHIFT 
-#undef DDR_PHY_DX1GCR4_DXREFIMON_MASK 
+#undef DDR_PHY_DX1GCR4_DXREFIMON_DEFVAL
+#undef DDR_PHY_DX1GCR4_DXREFIMON_SHIFT
+#undef DDR_PHY_DX1GCR4_DXREFIMON_MASK
 #define DDR_PHY_DX1GCR4_DXREFIMON_DEFVAL                       0x0E00003C
 #define DDR_PHY_DX1GCR4_DXREFIMON_SHIFT                        0
 #define DDR_PHY_DX1GCR4_DXREFIMON_MASK                         0x00000003U
@@ -13878,9 +13878,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX1GCR5_RESERVED_31_DEFVAL 
-#undef DDR_PHY_DX1GCR5_RESERVED_31_SHIFT 
-#undef DDR_PHY_DX1GCR5_RESERVED_31_MASK 
+#undef DDR_PHY_DX1GCR5_RESERVED_31_DEFVAL
+#undef DDR_PHY_DX1GCR5_RESERVED_31_SHIFT
+#undef DDR_PHY_DX1GCR5_RESERVED_31_MASK
 #define DDR_PHY_DX1GCR5_RESERVED_31_DEFVAL                     0x09090909
 #define DDR_PHY_DX1GCR5_RESERVED_31_SHIFT                      31
 #define DDR_PHY_DX1GCR5_RESERVED_31_MASK                       0x80000000U
@@ -13888,9 +13888,9 @@
 /*
 * Byte Lane internal VREF Select for Rank 3
 */
-#undef DDR_PHY_DX1GCR5_DXREFISELR3_DEFVAL 
-#undef DDR_PHY_DX1GCR5_DXREFISELR3_SHIFT 
-#undef DDR_PHY_DX1GCR5_DXREFISELR3_MASK 
+#undef DDR_PHY_DX1GCR5_DXREFISELR3_DEFVAL
+#undef DDR_PHY_DX1GCR5_DXREFISELR3_SHIFT
+#undef DDR_PHY_DX1GCR5_DXREFISELR3_MASK
 #define DDR_PHY_DX1GCR5_DXREFISELR3_DEFVAL                     0x09090909
 #define DDR_PHY_DX1GCR5_DXREFISELR3_SHIFT                      24
 #define DDR_PHY_DX1GCR5_DXREFISELR3_MASK                       0x7F000000U
@@ -13898,9 +13898,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX1GCR5_RESERVED_23_DEFVAL 
-#undef DDR_PHY_DX1GCR5_RESERVED_23_SHIFT 
-#undef DDR_PHY_DX1GCR5_RESERVED_23_MASK 
+#undef DDR_PHY_DX1GCR5_RESERVED_23_DEFVAL
+#undef DDR_PHY_DX1GCR5_RESERVED_23_SHIFT
+#undef DDR_PHY_DX1GCR5_RESERVED_23_MASK
 #define DDR_PHY_DX1GCR5_RESERVED_23_DEFVAL                     0x09090909
 #define DDR_PHY_DX1GCR5_RESERVED_23_SHIFT                      23
 #define DDR_PHY_DX1GCR5_RESERVED_23_MASK                       0x00800000U
@@ -13908,9 +13908,9 @@
 /*
 * Byte Lane internal VREF Select for Rank 2
 */
-#undef DDR_PHY_DX1GCR5_DXREFISELR2_DEFVAL 
-#undef DDR_PHY_DX1GCR5_DXREFISELR2_SHIFT 
-#undef DDR_PHY_DX1GCR5_DXREFISELR2_MASK 
+#undef DDR_PHY_DX1GCR5_DXREFISELR2_DEFVAL
+#undef DDR_PHY_DX1GCR5_DXREFISELR2_SHIFT
+#undef DDR_PHY_DX1GCR5_DXREFISELR2_MASK
 #define DDR_PHY_DX1GCR5_DXREFISELR2_DEFVAL                     0x09090909
 #define DDR_PHY_DX1GCR5_DXREFISELR2_SHIFT                      16
 #define DDR_PHY_DX1GCR5_DXREFISELR2_MASK                       0x007F0000U
@@ -13918,9 +13918,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX1GCR5_RESERVED_15_DEFVAL 
-#undef DDR_PHY_DX1GCR5_RESERVED_15_SHIFT 
-#undef DDR_PHY_DX1GCR5_RESERVED_15_MASK 
+#undef DDR_PHY_DX1GCR5_RESERVED_15_DEFVAL
+#undef DDR_PHY_DX1GCR5_RESERVED_15_SHIFT
+#undef DDR_PHY_DX1GCR5_RESERVED_15_MASK
 #define DDR_PHY_DX1GCR5_RESERVED_15_DEFVAL                     0x09090909
 #define DDR_PHY_DX1GCR5_RESERVED_15_SHIFT                      15
 #define DDR_PHY_DX1GCR5_RESERVED_15_MASK                       0x00008000U
@@ -13928,9 +13928,9 @@
 /*
 * Byte Lane internal VREF Select for Rank 1
 */
-#undef DDR_PHY_DX1GCR5_DXREFISELR1_DEFVAL 
-#undef DDR_PHY_DX1GCR5_DXREFISELR1_SHIFT 
-#undef DDR_PHY_DX1GCR5_DXREFISELR1_MASK 
+#undef DDR_PHY_DX1GCR5_DXREFISELR1_DEFVAL
+#undef DDR_PHY_DX1GCR5_DXREFISELR1_SHIFT
+#undef DDR_PHY_DX1GCR5_DXREFISELR1_MASK
 #define DDR_PHY_DX1GCR5_DXREFISELR1_DEFVAL                     0x09090909
 #define DDR_PHY_DX1GCR5_DXREFISELR1_SHIFT                      8
 #define DDR_PHY_DX1GCR5_DXREFISELR1_MASK                       0x00007F00U
@@ -13938,9 +13938,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX1GCR5_RESERVED_7_DEFVAL 
-#undef DDR_PHY_DX1GCR5_RESERVED_7_SHIFT 
-#undef DDR_PHY_DX1GCR5_RESERVED_7_MASK 
+#undef DDR_PHY_DX1GCR5_RESERVED_7_DEFVAL
+#undef DDR_PHY_DX1GCR5_RESERVED_7_SHIFT
+#undef DDR_PHY_DX1GCR5_RESERVED_7_MASK
 #define DDR_PHY_DX1GCR5_RESERVED_7_DEFVAL                      0x09090909
 #define DDR_PHY_DX1GCR5_RESERVED_7_SHIFT                       7
 #define DDR_PHY_DX1GCR5_RESERVED_7_MASK                        0x00000080U
@@ -13948,9 +13948,9 @@
 /*
 * Byte Lane internal VREF Select for Rank 0
 */
-#undef DDR_PHY_DX1GCR5_DXREFISELR0_DEFVAL 
-#undef DDR_PHY_DX1GCR5_DXREFISELR0_SHIFT 
-#undef DDR_PHY_DX1GCR5_DXREFISELR0_MASK 
+#undef DDR_PHY_DX1GCR5_DXREFISELR0_DEFVAL
+#undef DDR_PHY_DX1GCR5_DXREFISELR0_SHIFT
+#undef DDR_PHY_DX1GCR5_DXREFISELR0_MASK
 #define DDR_PHY_DX1GCR5_DXREFISELR0_DEFVAL                     0x09090909
 #define DDR_PHY_DX1GCR5_DXREFISELR0_SHIFT                      0
 #define DDR_PHY_DX1GCR5_DXREFISELR0_MASK                       0x0000007FU
@@ -13958,9 +13958,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX1GCR6_RESERVED_31_30_DEFVAL 
-#undef DDR_PHY_DX1GCR6_RESERVED_31_30_SHIFT 
-#undef DDR_PHY_DX1GCR6_RESERVED_31_30_MASK 
+#undef DDR_PHY_DX1GCR6_RESERVED_31_30_DEFVAL
+#undef DDR_PHY_DX1GCR6_RESERVED_31_30_SHIFT
+#undef DDR_PHY_DX1GCR6_RESERVED_31_30_MASK
 #define DDR_PHY_DX1GCR6_RESERVED_31_30_DEFVAL                  0x09090909
 #define DDR_PHY_DX1GCR6_RESERVED_31_30_SHIFT                   30
 #define DDR_PHY_DX1GCR6_RESERVED_31_30_MASK                    0xC0000000U
@@ -13968,9 +13968,9 @@
 /*
 * DRAM DQ VREF Select for Rank3
 */
-#undef DDR_PHY_DX1GCR6_DXDQVREFR3_DEFVAL 
-#undef DDR_PHY_DX1GCR6_DXDQVREFR3_SHIFT 
-#undef DDR_PHY_DX1GCR6_DXDQVREFR3_MASK 
+#undef DDR_PHY_DX1GCR6_DXDQVREFR3_DEFVAL
+#undef DDR_PHY_DX1GCR6_DXDQVREFR3_SHIFT
+#undef DDR_PHY_DX1GCR6_DXDQVREFR3_MASK
 #define DDR_PHY_DX1GCR6_DXDQVREFR3_DEFVAL                      0x09090909
 #define DDR_PHY_DX1GCR6_DXDQVREFR3_SHIFT                       24
 #define DDR_PHY_DX1GCR6_DXDQVREFR3_MASK                        0x3F000000U
@@ -13978,9 +13978,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX1GCR6_RESERVED_23_22_DEFVAL 
-#undef DDR_PHY_DX1GCR6_RESERVED_23_22_SHIFT 
-#undef DDR_PHY_DX1GCR6_RESERVED_23_22_MASK 
+#undef DDR_PHY_DX1GCR6_RESERVED_23_22_DEFVAL
+#undef DDR_PHY_DX1GCR6_RESERVED_23_22_SHIFT
+#undef DDR_PHY_DX1GCR6_RESERVED_23_22_MASK
 #define DDR_PHY_DX1GCR6_RESERVED_23_22_DEFVAL                  0x09090909
 #define DDR_PHY_DX1GCR6_RESERVED_23_22_SHIFT                   22
 #define DDR_PHY_DX1GCR6_RESERVED_23_22_MASK                    0x00C00000U
@@ -13988,9 +13988,9 @@
 /*
 * DRAM DQ VREF Select for Rank2
 */
-#undef DDR_PHY_DX1GCR6_DXDQVREFR2_DEFVAL 
-#undef DDR_PHY_DX1GCR6_DXDQVREFR2_SHIFT 
-#undef DDR_PHY_DX1GCR6_DXDQVREFR2_MASK 
+#undef DDR_PHY_DX1GCR6_DXDQVREFR2_DEFVAL
+#undef DDR_PHY_DX1GCR6_DXDQVREFR2_SHIFT
+#undef DDR_PHY_DX1GCR6_DXDQVREFR2_MASK
 #define DDR_PHY_DX1GCR6_DXDQVREFR2_DEFVAL                      0x09090909
 #define DDR_PHY_DX1GCR6_DXDQVREFR2_SHIFT                       16
 #define DDR_PHY_DX1GCR6_DXDQVREFR2_MASK                        0x003F0000U
@@ -13998,9 +13998,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX1GCR6_RESERVED_15_14_DEFVAL 
-#undef DDR_PHY_DX1GCR6_RESERVED_15_14_SHIFT 
-#undef DDR_PHY_DX1GCR6_RESERVED_15_14_MASK 
+#undef DDR_PHY_DX1GCR6_RESERVED_15_14_DEFVAL
+#undef DDR_PHY_DX1GCR6_RESERVED_15_14_SHIFT
+#undef DDR_PHY_DX1GCR6_RESERVED_15_14_MASK
 #define DDR_PHY_DX1GCR6_RESERVED_15_14_DEFVAL                  0x09090909
 #define DDR_PHY_DX1GCR6_RESERVED_15_14_SHIFT                   14
 #define DDR_PHY_DX1GCR6_RESERVED_15_14_MASK                    0x0000C000U
@@ -14008,9 +14008,9 @@
 /*
 * DRAM DQ VREF Select for Rank1
 */
-#undef DDR_PHY_DX1GCR6_DXDQVREFR1_DEFVAL 
-#undef DDR_PHY_DX1GCR6_DXDQVREFR1_SHIFT 
-#undef DDR_PHY_DX1GCR6_DXDQVREFR1_MASK 
+#undef DDR_PHY_DX1GCR6_DXDQVREFR1_DEFVAL
+#undef DDR_PHY_DX1GCR6_DXDQVREFR1_SHIFT
+#undef DDR_PHY_DX1GCR6_DXDQVREFR1_MASK
 #define DDR_PHY_DX1GCR6_DXDQVREFR1_DEFVAL                      0x09090909
 #define DDR_PHY_DX1GCR6_DXDQVREFR1_SHIFT                       8
 #define DDR_PHY_DX1GCR6_DXDQVREFR1_MASK                        0x00003F00U
@@ -14018,9 +14018,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX1GCR6_RESERVED_7_6_DEFVAL 
-#undef DDR_PHY_DX1GCR6_RESERVED_7_6_SHIFT 
-#undef DDR_PHY_DX1GCR6_RESERVED_7_6_MASK 
+#undef DDR_PHY_DX1GCR6_RESERVED_7_6_DEFVAL
+#undef DDR_PHY_DX1GCR6_RESERVED_7_6_SHIFT
+#undef DDR_PHY_DX1GCR6_RESERVED_7_6_MASK
 #define DDR_PHY_DX1GCR6_RESERVED_7_6_DEFVAL                    0x09090909
 #define DDR_PHY_DX1GCR6_RESERVED_7_6_SHIFT                     6
 #define DDR_PHY_DX1GCR6_RESERVED_7_6_MASK                      0x000000C0U
@@ -14028,9 +14028,9 @@
 /*
 * DRAM DQ VREF Select for Rank0
 */
-#undef DDR_PHY_DX1GCR6_DXDQVREFR0_DEFVAL 
-#undef DDR_PHY_DX1GCR6_DXDQVREFR0_SHIFT 
-#undef DDR_PHY_DX1GCR6_DXDQVREFR0_MASK 
+#undef DDR_PHY_DX1GCR6_DXDQVREFR0_DEFVAL
+#undef DDR_PHY_DX1GCR6_DXDQVREFR0_SHIFT
+#undef DDR_PHY_DX1GCR6_DXDQVREFR0_MASK
 #define DDR_PHY_DX1GCR6_DXDQVREFR0_DEFVAL                      0x09090909
 #define DDR_PHY_DX1GCR6_DXDQVREFR0_SHIFT                       0
 #define DDR_PHY_DX1GCR6_DXDQVREFR0_MASK                        0x0000003FU
@@ -14038,9 +14038,9 @@
 /*
 * Calibration Bypass
 */
-#undef DDR_PHY_DX2GCR0_CALBYP_DEFVAL 
-#undef DDR_PHY_DX2GCR0_CALBYP_SHIFT 
-#undef DDR_PHY_DX2GCR0_CALBYP_MASK 
+#undef DDR_PHY_DX2GCR0_CALBYP_DEFVAL
+#undef DDR_PHY_DX2GCR0_CALBYP_SHIFT
+#undef DDR_PHY_DX2GCR0_CALBYP_MASK
 #define DDR_PHY_DX2GCR0_CALBYP_DEFVAL                          0x40200204
 #define DDR_PHY_DX2GCR0_CALBYP_SHIFT                           31
 #define DDR_PHY_DX2GCR0_CALBYP_MASK                            0x80000000U
@@ -14048,9 +14048,9 @@
 /*
 * Master Delay Line Enable
 */
-#undef DDR_PHY_DX2GCR0_MDLEN_DEFVAL 
-#undef DDR_PHY_DX2GCR0_MDLEN_SHIFT 
-#undef DDR_PHY_DX2GCR0_MDLEN_MASK 
+#undef DDR_PHY_DX2GCR0_MDLEN_DEFVAL
+#undef DDR_PHY_DX2GCR0_MDLEN_SHIFT
+#undef DDR_PHY_DX2GCR0_MDLEN_MASK
 #define DDR_PHY_DX2GCR0_MDLEN_DEFVAL                           0x40200204
 #define DDR_PHY_DX2GCR0_MDLEN_SHIFT                            30
 #define DDR_PHY_DX2GCR0_MDLEN_MASK                             0x40000000U
@@ -14058,9 +14058,9 @@
 /*
 * Configurable ODT(TE) Phase Shift
 */
-#undef DDR_PHY_DX2GCR0_CODTSHFT_DEFVAL 
-#undef DDR_PHY_DX2GCR0_CODTSHFT_SHIFT 
-#undef DDR_PHY_DX2GCR0_CODTSHFT_MASK 
+#undef DDR_PHY_DX2GCR0_CODTSHFT_DEFVAL
+#undef DDR_PHY_DX2GCR0_CODTSHFT_SHIFT
+#undef DDR_PHY_DX2GCR0_CODTSHFT_MASK
 #define DDR_PHY_DX2GCR0_CODTSHFT_DEFVAL                        0x40200204
 #define DDR_PHY_DX2GCR0_CODTSHFT_SHIFT                         28
 #define DDR_PHY_DX2GCR0_CODTSHFT_MASK                          0x30000000U
@@ -14068,9 +14068,9 @@
 /*
 * DQS Duty Cycle Correction
 */
-#undef DDR_PHY_DX2GCR0_DQSDCC_DEFVAL 
-#undef DDR_PHY_DX2GCR0_DQSDCC_SHIFT 
-#undef DDR_PHY_DX2GCR0_DQSDCC_MASK 
+#undef DDR_PHY_DX2GCR0_DQSDCC_DEFVAL
+#undef DDR_PHY_DX2GCR0_DQSDCC_SHIFT
+#undef DDR_PHY_DX2GCR0_DQSDCC_MASK
 #define DDR_PHY_DX2GCR0_DQSDCC_DEFVAL                          0x40200204
 #define DDR_PHY_DX2GCR0_DQSDCC_SHIFT                           24
 #define DDR_PHY_DX2GCR0_DQSDCC_MASK                            0x0F000000U
@@ -14079,9 +14079,9 @@
 * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
     *  input for the respective bypte lane of the PHY
 */
-#undef DDR_PHY_DX2GCR0_RDDLY_DEFVAL 
-#undef DDR_PHY_DX2GCR0_RDDLY_SHIFT 
-#undef DDR_PHY_DX2GCR0_RDDLY_MASK 
+#undef DDR_PHY_DX2GCR0_RDDLY_DEFVAL
+#undef DDR_PHY_DX2GCR0_RDDLY_SHIFT
+#undef DDR_PHY_DX2GCR0_RDDLY_MASK
 #define DDR_PHY_DX2GCR0_RDDLY_DEFVAL                           0x40200204
 #define DDR_PHY_DX2GCR0_RDDLY_SHIFT                            20
 #define DDR_PHY_DX2GCR0_RDDLY_MASK                             0x00F00000U
@@ -14089,9 +14089,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX2GCR0_RESERVED_19_14_DEFVAL 
-#undef DDR_PHY_DX2GCR0_RESERVED_19_14_SHIFT 
-#undef DDR_PHY_DX2GCR0_RESERVED_19_14_MASK 
+#undef DDR_PHY_DX2GCR0_RESERVED_19_14_DEFVAL
+#undef DDR_PHY_DX2GCR0_RESERVED_19_14_SHIFT
+#undef DDR_PHY_DX2GCR0_RESERVED_19_14_MASK
 #define DDR_PHY_DX2GCR0_RESERVED_19_14_DEFVAL                  0x40200204
 #define DDR_PHY_DX2GCR0_RESERVED_19_14_SHIFT                   14
 #define DDR_PHY_DX2GCR0_RESERVED_19_14_MASK                    0x000FC000U
@@ -14099,9 +14099,9 @@
 /*
 * DQSNSE Power Down Receiver
 */
-#undef DDR_PHY_DX2GCR0_DQSNSEPDR_DEFVAL 
-#undef DDR_PHY_DX2GCR0_DQSNSEPDR_SHIFT 
-#undef DDR_PHY_DX2GCR0_DQSNSEPDR_MASK 
+#undef DDR_PHY_DX2GCR0_DQSNSEPDR_DEFVAL
+#undef DDR_PHY_DX2GCR0_DQSNSEPDR_SHIFT
+#undef DDR_PHY_DX2GCR0_DQSNSEPDR_MASK
 #define DDR_PHY_DX2GCR0_DQSNSEPDR_DEFVAL                       0x40200204
 #define DDR_PHY_DX2GCR0_DQSNSEPDR_SHIFT                        13
 #define DDR_PHY_DX2GCR0_DQSNSEPDR_MASK                         0x00002000U
@@ -14109,9 +14109,9 @@
 /*
 * DQSSE Power Down Receiver
 */
-#undef DDR_PHY_DX2GCR0_DQSSEPDR_DEFVAL 
-#undef DDR_PHY_DX2GCR0_DQSSEPDR_SHIFT 
-#undef DDR_PHY_DX2GCR0_DQSSEPDR_MASK 
+#undef DDR_PHY_DX2GCR0_DQSSEPDR_DEFVAL
+#undef DDR_PHY_DX2GCR0_DQSSEPDR_SHIFT
+#undef DDR_PHY_DX2GCR0_DQSSEPDR_MASK
 #define DDR_PHY_DX2GCR0_DQSSEPDR_DEFVAL                        0x40200204
 #define DDR_PHY_DX2GCR0_DQSSEPDR_SHIFT                         12
 #define DDR_PHY_DX2GCR0_DQSSEPDR_MASK                          0x00001000U
@@ -14119,9 +14119,9 @@
 /*
 * RTT On Additive Latency
 */
-#undef DDR_PHY_DX2GCR0_RTTOAL_DEFVAL 
-#undef DDR_PHY_DX2GCR0_RTTOAL_SHIFT 
-#undef DDR_PHY_DX2GCR0_RTTOAL_MASK 
+#undef DDR_PHY_DX2GCR0_RTTOAL_DEFVAL
+#undef DDR_PHY_DX2GCR0_RTTOAL_SHIFT
+#undef DDR_PHY_DX2GCR0_RTTOAL_MASK
 #define DDR_PHY_DX2GCR0_RTTOAL_DEFVAL                          0x40200204
 #define DDR_PHY_DX2GCR0_RTTOAL_SHIFT                           11
 #define DDR_PHY_DX2GCR0_RTTOAL_MASK                            0x00000800U
@@ -14129,9 +14129,9 @@
 /*
 * RTT Output Hold
 */
-#undef DDR_PHY_DX2GCR0_RTTOH_DEFVAL 
-#undef DDR_PHY_DX2GCR0_RTTOH_SHIFT 
-#undef DDR_PHY_DX2GCR0_RTTOH_MASK 
+#undef DDR_PHY_DX2GCR0_RTTOH_DEFVAL
+#undef DDR_PHY_DX2GCR0_RTTOH_SHIFT
+#undef DDR_PHY_DX2GCR0_RTTOH_MASK
 #define DDR_PHY_DX2GCR0_RTTOH_DEFVAL                           0x40200204
 #define DDR_PHY_DX2GCR0_RTTOH_SHIFT                            9
 #define DDR_PHY_DX2GCR0_RTTOH_MASK                             0x00000600U
@@ -14139,9 +14139,9 @@
 /*
 * Configurable PDR Phase Shift
 */
-#undef DDR_PHY_DX2GCR0_CPDRSHFT_DEFVAL 
-#undef DDR_PHY_DX2GCR0_CPDRSHFT_SHIFT 
-#undef DDR_PHY_DX2GCR0_CPDRSHFT_MASK 
+#undef DDR_PHY_DX2GCR0_CPDRSHFT_DEFVAL
+#undef DDR_PHY_DX2GCR0_CPDRSHFT_SHIFT
+#undef DDR_PHY_DX2GCR0_CPDRSHFT_MASK
 #define DDR_PHY_DX2GCR0_CPDRSHFT_DEFVAL                        0x40200204
 #define DDR_PHY_DX2GCR0_CPDRSHFT_SHIFT                         7
 #define DDR_PHY_DX2GCR0_CPDRSHFT_MASK                          0x00000180U
@@ -14149,9 +14149,9 @@
 /*
 * DQSR Power Down
 */
-#undef DDR_PHY_DX2GCR0_DQSRPD_DEFVAL 
-#undef DDR_PHY_DX2GCR0_DQSRPD_SHIFT 
-#undef DDR_PHY_DX2GCR0_DQSRPD_MASK 
+#undef DDR_PHY_DX2GCR0_DQSRPD_DEFVAL
+#undef DDR_PHY_DX2GCR0_DQSRPD_SHIFT
+#undef DDR_PHY_DX2GCR0_DQSRPD_MASK
 #define DDR_PHY_DX2GCR0_DQSRPD_DEFVAL                          0x40200204
 #define DDR_PHY_DX2GCR0_DQSRPD_SHIFT                           6
 #define DDR_PHY_DX2GCR0_DQSRPD_MASK                            0x00000040U
@@ -14159,9 +14159,9 @@
 /*
 * DQSG Power Down Receiver
 */
-#undef DDR_PHY_DX2GCR0_DQSGPDR_DEFVAL 
-#undef DDR_PHY_DX2GCR0_DQSGPDR_SHIFT 
-#undef DDR_PHY_DX2GCR0_DQSGPDR_MASK 
+#undef DDR_PHY_DX2GCR0_DQSGPDR_DEFVAL
+#undef DDR_PHY_DX2GCR0_DQSGPDR_SHIFT
+#undef DDR_PHY_DX2GCR0_DQSGPDR_MASK
 #define DDR_PHY_DX2GCR0_DQSGPDR_DEFVAL                         0x40200204
 #define DDR_PHY_DX2GCR0_DQSGPDR_SHIFT                          5
 #define DDR_PHY_DX2GCR0_DQSGPDR_MASK                           0x00000020U
@@ -14169,9 +14169,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX2GCR0_RESERVED_4_DEFVAL 
-#undef DDR_PHY_DX2GCR0_RESERVED_4_SHIFT 
-#undef DDR_PHY_DX2GCR0_RESERVED_4_MASK 
+#undef DDR_PHY_DX2GCR0_RESERVED_4_DEFVAL
+#undef DDR_PHY_DX2GCR0_RESERVED_4_SHIFT
+#undef DDR_PHY_DX2GCR0_RESERVED_4_MASK
 #define DDR_PHY_DX2GCR0_RESERVED_4_DEFVAL                      0x40200204
 #define DDR_PHY_DX2GCR0_RESERVED_4_SHIFT                       4
 #define DDR_PHY_DX2GCR0_RESERVED_4_MASK                        0x00000010U
@@ -14179,9 +14179,9 @@
 /*
 * DQSG On-Die Termination
 */
-#undef DDR_PHY_DX2GCR0_DQSGODT_DEFVAL 
-#undef DDR_PHY_DX2GCR0_DQSGODT_SHIFT 
-#undef DDR_PHY_DX2GCR0_DQSGODT_MASK 
+#undef DDR_PHY_DX2GCR0_DQSGODT_DEFVAL
+#undef DDR_PHY_DX2GCR0_DQSGODT_SHIFT
+#undef DDR_PHY_DX2GCR0_DQSGODT_MASK
 #define DDR_PHY_DX2GCR0_DQSGODT_DEFVAL                         0x40200204
 #define DDR_PHY_DX2GCR0_DQSGODT_SHIFT                          3
 #define DDR_PHY_DX2GCR0_DQSGODT_MASK                           0x00000008U
@@ -14189,9 +14189,9 @@
 /*
 * DQSG Output Enable
 */
-#undef DDR_PHY_DX2GCR0_DQSGOE_DEFVAL 
-#undef DDR_PHY_DX2GCR0_DQSGOE_SHIFT 
-#undef DDR_PHY_DX2GCR0_DQSGOE_MASK 
+#undef DDR_PHY_DX2GCR0_DQSGOE_DEFVAL
+#undef DDR_PHY_DX2GCR0_DQSGOE_SHIFT
+#undef DDR_PHY_DX2GCR0_DQSGOE_MASK
 #define DDR_PHY_DX2GCR0_DQSGOE_DEFVAL                          0x40200204
 #define DDR_PHY_DX2GCR0_DQSGOE_SHIFT                           2
 #define DDR_PHY_DX2GCR0_DQSGOE_MASK                            0x00000004U
@@ -14199,9 +14199,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX2GCR0_RESERVED_1_0_DEFVAL 
-#undef DDR_PHY_DX2GCR0_RESERVED_1_0_SHIFT 
-#undef DDR_PHY_DX2GCR0_RESERVED_1_0_MASK 
+#undef DDR_PHY_DX2GCR0_RESERVED_1_0_DEFVAL
+#undef DDR_PHY_DX2GCR0_RESERVED_1_0_SHIFT
+#undef DDR_PHY_DX2GCR0_RESERVED_1_0_MASK
 #define DDR_PHY_DX2GCR0_RESERVED_1_0_DEFVAL                    0x40200204
 #define DDR_PHY_DX2GCR0_RESERVED_1_0_SHIFT                     0
 #define DDR_PHY_DX2GCR0_RESERVED_1_0_MASK                      0x00000003U
@@ -14209,9 +14209,9 @@
 /*
 * Enables the PDR mode for DQ[7:0]
 */
-#undef DDR_PHY_DX2GCR1_DXPDRMODE_DEFVAL 
-#undef DDR_PHY_DX2GCR1_DXPDRMODE_SHIFT 
-#undef DDR_PHY_DX2GCR1_DXPDRMODE_MASK 
+#undef DDR_PHY_DX2GCR1_DXPDRMODE_DEFVAL
+#undef DDR_PHY_DX2GCR1_DXPDRMODE_SHIFT
+#undef DDR_PHY_DX2GCR1_DXPDRMODE_MASK
 #define DDR_PHY_DX2GCR1_DXPDRMODE_DEFVAL                       0x00007FFF
 #define DDR_PHY_DX2GCR1_DXPDRMODE_SHIFT                        16
 #define DDR_PHY_DX2GCR1_DXPDRMODE_MASK                         0xFFFF0000U
@@ -14219,9 +14219,9 @@
 /*
 * Reserved. Returns zeroes on reads.
 */
-#undef DDR_PHY_DX2GCR1_RESERVED_15_DEFVAL 
-#undef DDR_PHY_DX2GCR1_RESERVED_15_SHIFT 
-#undef DDR_PHY_DX2GCR1_RESERVED_15_MASK 
+#undef DDR_PHY_DX2GCR1_RESERVED_15_DEFVAL
+#undef DDR_PHY_DX2GCR1_RESERVED_15_SHIFT
+#undef DDR_PHY_DX2GCR1_RESERVED_15_MASK
 #define DDR_PHY_DX2GCR1_RESERVED_15_DEFVAL                     0x00007FFF
 #define DDR_PHY_DX2GCR1_RESERVED_15_SHIFT                      15
 #define DDR_PHY_DX2GCR1_RESERVED_15_MASK                       0x00008000U
@@ -14229,9 +14229,9 @@
 /*
 * Select the delayed or non-delayed read data strobe #
 */
-#undef DDR_PHY_DX2GCR1_QSNSEL_DEFVAL 
-#undef DDR_PHY_DX2GCR1_QSNSEL_SHIFT 
-#undef DDR_PHY_DX2GCR1_QSNSEL_MASK 
+#undef DDR_PHY_DX2GCR1_QSNSEL_DEFVAL
+#undef DDR_PHY_DX2GCR1_QSNSEL_SHIFT
+#undef DDR_PHY_DX2GCR1_QSNSEL_MASK
 #define DDR_PHY_DX2GCR1_QSNSEL_DEFVAL                          0x00007FFF
 #define DDR_PHY_DX2GCR1_QSNSEL_SHIFT                           14
 #define DDR_PHY_DX2GCR1_QSNSEL_MASK                            0x00004000U
@@ -14239,9 +14239,9 @@
 /*
 * Select the delayed or non-delayed read data strobe
 */
-#undef DDR_PHY_DX2GCR1_QSSEL_DEFVAL 
-#undef DDR_PHY_DX2GCR1_QSSEL_SHIFT 
-#undef DDR_PHY_DX2GCR1_QSSEL_MASK 
+#undef DDR_PHY_DX2GCR1_QSSEL_DEFVAL
+#undef DDR_PHY_DX2GCR1_QSSEL_SHIFT
+#undef DDR_PHY_DX2GCR1_QSSEL_MASK
 #define DDR_PHY_DX2GCR1_QSSEL_DEFVAL                           0x00007FFF
 #define DDR_PHY_DX2GCR1_QSSEL_SHIFT                            13
 #define DDR_PHY_DX2GCR1_QSSEL_MASK                             0x00002000U
@@ -14249,9 +14249,9 @@
 /*
 * Enables Read Data Strobe in a byte lane
 */
-#undef DDR_PHY_DX2GCR1_OEEN_DEFVAL 
-#undef DDR_PHY_DX2GCR1_OEEN_SHIFT 
-#undef DDR_PHY_DX2GCR1_OEEN_MASK 
+#undef DDR_PHY_DX2GCR1_OEEN_DEFVAL
+#undef DDR_PHY_DX2GCR1_OEEN_SHIFT
+#undef DDR_PHY_DX2GCR1_OEEN_MASK
 #define DDR_PHY_DX2GCR1_OEEN_DEFVAL                            0x00007FFF
 #define DDR_PHY_DX2GCR1_OEEN_SHIFT                             12
 #define DDR_PHY_DX2GCR1_OEEN_MASK                              0x00001000U
@@ -14259,9 +14259,9 @@
 /*
 * Enables PDR in a byte lane
 */
-#undef DDR_PHY_DX2GCR1_PDREN_DEFVAL 
-#undef DDR_PHY_DX2GCR1_PDREN_SHIFT 
-#undef DDR_PHY_DX2GCR1_PDREN_MASK 
+#undef DDR_PHY_DX2GCR1_PDREN_DEFVAL
+#undef DDR_PHY_DX2GCR1_PDREN_SHIFT
+#undef DDR_PHY_DX2GCR1_PDREN_MASK
 #define DDR_PHY_DX2GCR1_PDREN_DEFVAL                           0x00007FFF
 #define DDR_PHY_DX2GCR1_PDREN_SHIFT                            11
 #define DDR_PHY_DX2GCR1_PDREN_MASK                             0x00000800U
@@ -14269,9 +14269,9 @@
 /*
 * Enables ODT/TE in a byte lane
 */
-#undef DDR_PHY_DX2GCR1_TEEN_DEFVAL 
-#undef DDR_PHY_DX2GCR1_TEEN_SHIFT 
-#undef DDR_PHY_DX2GCR1_TEEN_MASK 
+#undef DDR_PHY_DX2GCR1_TEEN_DEFVAL
+#undef DDR_PHY_DX2GCR1_TEEN_SHIFT
+#undef DDR_PHY_DX2GCR1_TEEN_MASK
 #define DDR_PHY_DX2GCR1_TEEN_DEFVAL                            0x00007FFF
 #define DDR_PHY_DX2GCR1_TEEN_SHIFT                             10
 #define DDR_PHY_DX2GCR1_TEEN_MASK                              0x00000400U
@@ -14279,9 +14279,9 @@
 /*
 * Enables Write Data strobe in a byte lane
 */
-#undef DDR_PHY_DX2GCR1_DSEN_DEFVAL 
-#undef DDR_PHY_DX2GCR1_DSEN_SHIFT 
-#undef DDR_PHY_DX2GCR1_DSEN_MASK 
+#undef DDR_PHY_DX2GCR1_DSEN_DEFVAL
+#undef DDR_PHY_DX2GCR1_DSEN_SHIFT
+#undef DDR_PHY_DX2GCR1_DSEN_MASK
 #define DDR_PHY_DX2GCR1_DSEN_DEFVAL                            0x00007FFF
 #define DDR_PHY_DX2GCR1_DSEN_SHIFT                             9
 #define DDR_PHY_DX2GCR1_DSEN_MASK                              0x00000200U
@@ -14289,9 +14289,9 @@
 /*
 * Enables DM pin in a byte lane
 */
-#undef DDR_PHY_DX2GCR1_DMEN_DEFVAL 
-#undef DDR_PHY_DX2GCR1_DMEN_SHIFT 
-#undef DDR_PHY_DX2GCR1_DMEN_MASK 
+#undef DDR_PHY_DX2GCR1_DMEN_DEFVAL
+#undef DDR_PHY_DX2GCR1_DMEN_SHIFT
+#undef DDR_PHY_DX2GCR1_DMEN_MASK
 #define DDR_PHY_DX2GCR1_DMEN_DEFVAL                            0x00007FFF
 #define DDR_PHY_DX2GCR1_DMEN_SHIFT                             8
 #define DDR_PHY_DX2GCR1_DMEN_MASK                              0x00000100U
@@ -14299,9 +14299,9 @@
 /*
 * Enables DQ corresponding to each bit in a byte
 */
-#undef DDR_PHY_DX2GCR1_DQEN_DEFVAL 
-#undef DDR_PHY_DX2GCR1_DQEN_SHIFT 
-#undef DDR_PHY_DX2GCR1_DQEN_MASK 
+#undef DDR_PHY_DX2GCR1_DQEN_DEFVAL
+#undef DDR_PHY_DX2GCR1_DQEN_SHIFT
+#undef DDR_PHY_DX2GCR1_DQEN_MASK
 #define DDR_PHY_DX2GCR1_DQEN_DEFVAL                            0x00007FFF
 #define DDR_PHY_DX2GCR1_DQEN_SHIFT                             0
 #define DDR_PHY_DX2GCR1_DQEN_MASK                              0x000000FFU
@@ -14309,9 +14309,9 @@
 /*
 * Byte lane VREF IOM (Used only by D4MU IOs)
 */
-#undef DDR_PHY_DX2GCR4_RESERVED_31_29_DEFVAL 
-#undef DDR_PHY_DX2GCR4_RESERVED_31_29_SHIFT 
-#undef DDR_PHY_DX2GCR4_RESERVED_31_29_MASK 
+#undef DDR_PHY_DX2GCR4_RESERVED_31_29_DEFVAL
+#undef DDR_PHY_DX2GCR4_RESERVED_31_29_SHIFT
+#undef DDR_PHY_DX2GCR4_RESERVED_31_29_MASK
 #define DDR_PHY_DX2GCR4_RESERVED_31_29_DEFVAL                  0x0E00003C
 #define DDR_PHY_DX2GCR4_RESERVED_31_29_SHIFT                   29
 #define DDR_PHY_DX2GCR4_RESERVED_31_29_MASK                    0xE0000000U
@@ -14319,9 +14319,9 @@
 /*
 * Byte Lane VREF Pad Enable
 */
-#undef DDR_PHY_DX2GCR4_DXREFPEN_DEFVAL 
-#undef DDR_PHY_DX2GCR4_DXREFPEN_SHIFT 
-#undef DDR_PHY_DX2GCR4_DXREFPEN_MASK 
+#undef DDR_PHY_DX2GCR4_DXREFPEN_DEFVAL
+#undef DDR_PHY_DX2GCR4_DXREFPEN_SHIFT
+#undef DDR_PHY_DX2GCR4_DXREFPEN_MASK
 #define DDR_PHY_DX2GCR4_DXREFPEN_DEFVAL                        0x0E00003C
 #define DDR_PHY_DX2GCR4_DXREFPEN_SHIFT                         28
 #define DDR_PHY_DX2GCR4_DXREFPEN_MASK                          0x10000000U
@@ -14329,9 +14329,9 @@
 /*
 * Byte Lane Internal VREF Enable
 */
-#undef DDR_PHY_DX2GCR4_DXREFEEN_DEFVAL 
-#undef DDR_PHY_DX2GCR4_DXREFEEN_SHIFT 
-#undef DDR_PHY_DX2GCR4_DXREFEEN_MASK 
+#undef DDR_PHY_DX2GCR4_DXREFEEN_DEFVAL
+#undef DDR_PHY_DX2GCR4_DXREFEEN_SHIFT
+#undef DDR_PHY_DX2GCR4_DXREFEEN_MASK
 #define DDR_PHY_DX2GCR4_DXREFEEN_DEFVAL                        0x0E00003C
 #define DDR_PHY_DX2GCR4_DXREFEEN_SHIFT                         26
 #define DDR_PHY_DX2GCR4_DXREFEEN_MASK                          0x0C000000U
@@ -14339,9 +14339,9 @@
 /*
 * Byte Lane Single-End VREF Enable
 */
-#undef DDR_PHY_DX2GCR4_DXREFSEN_DEFVAL 
-#undef DDR_PHY_DX2GCR4_DXREFSEN_SHIFT 
-#undef DDR_PHY_DX2GCR4_DXREFSEN_MASK 
+#undef DDR_PHY_DX2GCR4_DXREFSEN_DEFVAL
+#undef DDR_PHY_DX2GCR4_DXREFSEN_SHIFT
+#undef DDR_PHY_DX2GCR4_DXREFSEN_MASK
 #define DDR_PHY_DX2GCR4_DXREFSEN_DEFVAL                        0x0E00003C
 #define DDR_PHY_DX2GCR4_DXREFSEN_SHIFT                         25
 #define DDR_PHY_DX2GCR4_DXREFSEN_MASK                          0x02000000U
@@ -14349,9 +14349,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX2GCR4_RESERVED_24_DEFVAL 
-#undef DDR_PHY_DX2GCR4_RESERVED_24_SHIFT 
-#undef DDR_PHY_DX2GCR4_RESERVED_24_MASK 
+#undef DDR_PHY_DX2GCR4_RESERVED_24_DEFVAL
+#undef DDR_PHY_DX2GCR4_RESERVED_24_SHIFT
+#undef DDR_PHY_DX2GCR4_RESERVED_24_MASK
 #define DDR_PHY_DX2GCR4_RESERVED_24_DEFVAL                     0x0E00003C
 #define DDR_PHY_DX2GCR4_RESERVED_24_SHIFT                      24
 #define DDR_PHY_DX2GCR4_RESERVED_24_MASK                       0x01000000U
@@ -14359,9 +14359,9 @@
 /*
 * External VREF generator REFSEL range select
 */
-#undef DDR_PHY_DX2GCR4_DXREFESELRANGE_DEFVAL 
-#undef DDR_PHY_DX2GCR4_DXREFESELRANGE_SHIFT 
-#undef DDR_PHY_DX2GCR4_DXREFESELRANGE_MASK 
+#undef DDR_PHY_DX2GCR4_DXREFESELRANGE_DEFVAL
+#undef DDR_PHY_DX2GCR4_DXREFESELRANGE_SHIFT
+#undef DDR_PHY_DX2GCR4_DXREFESELRANGE_MASK
 #define DDR_PHY_DX2GCR4_DXREFESELRANGE_DEFVAL                  0x0E00003C
 #define DDR_PHY_DX2GCR4_DXREFESELRANGE_SHIFT                   23
 #define DDR_PHY_DX2GCR4_DXREFESELRANGE_MASK                    0x00800000U
@@ -14369,9 +14369,9 @@
 /*
 * Byte Lane External VREF Select
 */
-#undef DDR_PHY_DX2GCR4_DXREFESEL_DEFVAL 
-#undef DDR_PHY_DX2GCR4_DXREFESEL_SHIFT 
-#undef DDR_PHY_DX2GCR4_DXREFESEL_MASK 
+#undef DDR_PHY_DX2GCR4_DXREFESEL_DEFVAL
+#undef DDR_PHY_DX2GCR4_DXREFESEL_SHIFT
+#undef DDR_PHY_DX2GCR4_DXREFESEL_MASK
 #define DDR_PHY_DX2GCR4_DXREFESEL_DEFVAL                       0x0E00003C
 #define DDR_PHY_DX2GCR4_DXREFESEL_SHIFT                        16
 #define DDR_PHY_DX2GCR4_DXREFESEL_MASK                         0x007F0000U
@@ -14379,9 +14379,9 @@
 /*
 * Single ended VREF generator REFSEL range select
 */
-#undef DDR_PHY_DX2GCR4_DXREFSSELRANGE_DEFVAL 
-#undef DDR_PHY_DX2GCR4_DXREFSSELRANGE_SHIFT 
-#undef DDR_PHY_DX2GCR4_DXREFSSELRANGE_MASK 
+#undef DDR_PHY_DX2GCR4_DXREFSSELRANGE_DEFVAL
+#undef DDR_PHY_DX2GCR4_DXREFSSELRANGE_SHIFT
+#undef DDR_PHY_DX2GCR4_DXREFSSELRANGE_MASK
 #define DDR_PHY_DX2GCR4_DXREFSSELRANGE_DEFVAL                  0x0E00003C
 #define DDR_PHY_DX2GCR4_DXREFSSELRANGE_SHIFT                   15
 #define DDR_PHY_DX2GCR4_DXREFSSELRANGE_MASK                    0x00008000U
@@ -14389,9 +14389,9 @@
 /*
 * Byte Lane Single-End VREF Select
 */
-#undef DDR_PHY_DX2GCR4_DXREFSSEL_DEFVAL 
-#undef DDR_PHY_DX2GCR4_DXREFSSEL_SHIFT 
-#undef DDR_PHY_DX2GCR4_DXREFSSEL_MASK 
+#undef DDR_PHY_DX2GCR4_DXREFSSEL_DEFVAL
+#undef DDR_PHY_DX2GCR4_DXREFSSEL_SHIFT
+#undef DDR_PHY_DX2GCR4_DXREFSSEL_MASK
 #define DDR_PHY_DX2GCR4_DXREFSSEL_DEFVAL                       0x0E00003C
 #define DDR_PHY_DX2GCR4_DXREFSSEL_SHIFT                        8
 #define DDR_PHY_DX2GCR4_DXREFSSEL_MASK                         0x00007F00U
@@ -14399,9 +14399,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX2GCR4_RESERVED_7_6_DEFVAL 
-#undef DDR_PHY_DX2GCR4_RESERVED_7_6_SHIFT 
-#undef DDR_PHY_DX2GCR4_RESERVED_7_6_MASK 
+#undef DDR_PHY_DX2GCR4_RESERVED_7_6_DEFVAL
+#undef DDR_PHY_DX2GCR4_RESERVED_7_6_SHIFT
+#undef DDR_PHY_DX2GCR4_RESERVED_7_6_MASK
 #define DDR_PHY_DX2GCR4_RESERVED_7_6_DEFVAL                    0x0E00003C
 #define DDR_PHY_DX2GCR4_RESERVED_7_6_SHIFT                     6
 #define DDR_PHY_DX2GCR4_RESERVED_7_6_MASK                      0x000000C0U
@@ -14409,9 +14409,9 @@
 /*
 * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
 */
-#undef DDR_PHY_DX2GCR4_DXREFIEN_DEFVAL 
-#undef DDR_PHY_DX2GCR4_DXREFIEN_SHIFT 
-#undef DDR_PHY_DX2GCR4_DXREFIEN_MASK 
+#undef DDR_PHY_DX2GCR4_DXREFIEN_DEFVAL
+#undef DDR_PHY_DX2GCR4_DXREFIEN_SHIFT
+#undef DDR_PHY_DX2GCR4_DXREFIEN_MASK
 #define DDR_PHY_DX2GCR4_DXREFIEN_DEFVAL                        0x0E00003C
 #define DDR_PHY_DX2GCR4_DXREFIEN_SHIFT                         2
 #define DDR_PHY_DX2GCR4_DXREFIEN_MASK                          0x0000003CU
@@ -14419,9 +14419,9 @@
 /*
 * VRMON control for DQ IO (Single Ended) buffers of a byte lane.
 */
-#undef DDR_PHY_DX2GCR4_DXREFIMON_DEFVAL 
-#undef DDR_PHY_DX2GCR4_DXREFIMON_SHIFT 
-#undef DDR_PHY_DX2GCR4_DXREFIMON_MASK 
+#undef DDR_PHY_DX2GCR4_DXREFIMON_DEFVAL
+#undef DDR_PHY_DX2GCR4_DXREFIMON_SHIFT
+#undef DDR_PHY_DX2GCR4_DXREFIMON_MASK
 #define DDR_PHY_DX2GCR4_DXREFIMON_DEFVAL                       0x0E00003C
 #define DDR_PHY_DX2GCR4_DXREFIMON_SHIFT                        0
 #define DDR_PHY_DX2GCR4_DXREFIMON_MASK                         0x00000003U
@@ -14429,9 +14429,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX2GCR5_RESERVED_31_DEFVAL 
-#undef DDR_PHY_DX2GCR5_RESERVED_31_SHIFT 
-#undef DDR_PHY_DX2GCR5_RESERVED_31_MASK 
+#undef DDR_PHY_DX2GCR5_RESERVED_31_DEFVAL
+#undef DDR_PHY_DX2GCR5_RESERVED_31_SHIFT
+#undef DDR_PHY_DX2GCR5_RESERVED_31_MASK
 #define DDR_PHY_DX2GCR5_RESERVED_31_DEFVAL                     0x09090909
 #define DDR_PHY_DX2GCR5_RESERVED_31_SHIFT                      31
 #define DDR_PHY_DX2GCR5_RESERVED_31_MASK                       0x80000000U
@@ -14439,9 +14439,9 @@
 /*
 * Byte Lane internal VREF Select for Rank 3
 */
-#undef DDR_PHY_DX2GCR5_DXREFISELR3_DEFVAL 
-#undef DDR_PHY_DX2GCR5_DXREFISELR3_SHIFT 
-#undef DDR_PHY_DX2GCR5_DXREFISELR3_MASK 
+#undef DDR_PHY_DX2GCR5_DXREFISELR3_DEFVAL
+#undef DDR_PHY_DX2GCR5_DXREFISELR3_SHIFT
+#undef DDR_PHY_DX2GCR5_DXREFISELR3_MASK
 #define DDR_PHY_DX2GCR5_DXREFISELR3_DEFVAL                     0x09090909
 #define DDR_PHY_DX2GCR5_DXREFISELR3_SHIFT                      24
 #define DDR_PHY_DX2GCR5_DXREFISELR3_MASK                       0x7F000000U
@@ -14449,9 +14449,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX2GCR5_RESERVED_23_DEFVAL 
-#undef DDR_PHY_DX2GCR5_RESERVED_23_SHIFT 
-#undef DDR_PHY_DX2GCR5_RESERVED_23_MASK 
+#undef DDR_PHY_DX2GCR5_RESERVED_23_DEFVAL
+#undef DDR_PHY_DX2GCR5_RESERVED_23_SHIFT
+#undef DDR_PHY_DX2GCR5_RESERVED_23_MASK
 #define DDR_PHY_DX2GCR5_RESERVED_23_DEFVAL                     0x09090909
 #define DDR_PHY_DX2GCR5_RESERVED_23_SHIFT                      23
 #define DDR_PHY_DX2GCR5_RESERVED_23_MASK                       0x00800000U
@@ -14459,9 +14459,9 @@
 /*
 * Byte Lane internal VREF Select for Rank 2
 */
-#undef DDR_PHY_DX2GCR5_DXREFISELR2_DEFVAL 
-#undef DDR_PHY_DX2GCR5_DXREFISELR2_SHIFT 
-#undef DDR_PHY_DX2GCR5_DXREFISELR2_MASK 
+#undef DDR_PHY_DX2GCR5_DXREFISELR2_DEFVAL
+#undef DDR_PHY_DX2GCR5_DXREFISELR2_SHIFT
+#undef DDR_PHY_DX2GCR5_DXREFISELR2_MASK
 #define DDR_PHY_DX2GCR5_DXREFISELR2_DEFVAL                     0x09090909
 #define DDR_PHY_DX2GCR5_DXREFISELR2_SHIFT                      16
 #define DDR_PHY_DX2GCR5_DXREFISELR2_MASK                       0x007F0000U
@@ -14469,9 +14469,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX2GCR5_RESERVED_15_DEFVAL 
-#undef DDR_PHY_DX2GCR5_RESERVED_15_SHIFT 
-#undef DDR_PHY_DX2GCR5_RESERVED_15_MASK 
+#undef DDR_PHY_DX2GCR5_RESERVED_15_DEFVAL
+#undef DDR_PHY_DX2GCR5_RESERVED_15_SHIFT
+#undef DDR_PHY_DX2GCR5_RESERVED_15_MASK
 #define DDR_PHY_DX2GCR5_RESERVED_15_DEFVAL                     0x09090909
 #define DDR_PHY_DX2GCR5_RESERVED_15_SHIFT                      15
 #define DDR_PHY_DX2GCR5_RESERVED_15_MASK                       0x00008000U
@@ -14479,9 +14479,9 @@
 /*
 * Byte Lane internal VREF Select for Rank 1
 */
-#undef DDR_PHY_DX2GCR5_DXREFISELR1_DEFVAL 
-#undef DDR_PHY_DX2GCR5_DXREFISELR1_SHIFT 
-#undef DDR_PHY_DX2GCR5_DXREFISELR1_MASK 
+#undef DDR_PHY_DX2GCR5_DXREFISELR1_DEFVAL
+#undef DDR_PHY_DX2GCR5_DXREFISELR1_SHIFT
+#undef DDR_PHY_DX2GCR5_DXREFISELR1_MASK
 #define DDR_PHY_DX2GCR5_DXREFISELR1_DEFVAL                     0x09090909
 #define DDR_PHY_DX2GCR5_DXREFISELR1_SHIFT                      8
 #define DDR_PHY_DX2GCR5_DXREFISELR1_MASK                       0x00007F00U
@@ -14489,9 +14489,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX2GCR5_RESERVED_7_DEFVAL 
-#undef DDR_PHY_DX2GCR5_RESERVED_7_SHIFT 
-#undef DDR_PHY_DX2GCR5_RESERVED_7_MASK 
+#undef DDR_PHY_DX2GCR5_RESERVED_7_DEFVAL
+#undef DDR_PHY_DX2GCR5_RESERVED_7_SHIFT
+#undef DDR_PHY_DX2GCR5_RESERVED_7_MASK
 #define DDR_PHY_DX2GCR5_RESERVED_7_DEFVAL                      0x09090909
 #define DDR_PHY_DX2GCR5_RESERVED_7_SHIFT                       7
 #define DDR_PHY_DX2GCR5_RESERVED_7_MASK                        0x00000080U
@@ -14499,9 +14499,9 @@
 /*
 * Byte Lane internal VREF Select for Rank 0
 */
-#undef DDR_PHY_DX2GCR5_DXREFISELR0_DEFVAL 
-#undef DDR_PHY_DX2GCR5_DXREFISELR0_SHIFT 
-#undef DDR_PHY_DX2GCR5_DXREFISELR0_MASK 
+#undef DDR_PHY_DX2GCR5_DXREFISELR0_DEFVAL
+#undef DDR_PHY_DX2GCR5_DXREFISELR0_SHIFT
+#undef DDR_PHY_DX2GCR5_DXREFISELR0_MASK
 #define DDR_PHY_DX2GCR5_DXREFISELR0_DEFVAL                     0x09090909
 #define DDR_PHY_DX2GCR5_DXREFISELR0_SHIFT                      0
 #define DDR_PHY_DX2GCR5_DXREFISELR0_MASK                       0x0000007FU
@@ -14509,9 +14509,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX2GCR6_RESERVED_31_30_DEFVAL 
-#undef DDR_PHY_DX2GCR6_RESERVED_31_30_SHIFT 
-#undef DDR_PHY_DX2GCR6_RESERVED_31_30_MASK 
+#undef DDR_PHY_DX2GCR6_RESERVED_31_30_DEFVAL
+#undef DDR_PHY_DX2GCR6_RESERVED_31_30_SHIFT
+#undef DDR_PHY_DX2GCR6_RESERVED_31_30_MASK
 #define DDR_PHY_DX2GCR6_RESERVED_31_30_DEFVAL                  0x09090909
 #define DDR_PHY_DX2GCR6_RESERVED_31_30_SHIFT                   30
 #define DDR_PHY_DX2GCR6_RESERVED_31_30_MASK                    0xC0000000U
@@ -14519,9 +14519,9 @@
 /*
 * DRAM DQ VREF Select for Rank3
 */
-#undef DDR_PHY_DX2GCR6_DXDQVREFR3_DEFVAL 
-#undef DDR_PHY_DX2GCR6_DXDQVREFR3_SHIFT 
-#undef DDR_PHY_DX2GCR6_DXDQVREFR3_MASK 
+#undef DDR_PHY_DX2GCR6_DXDQVREFR3_DEFVAL
+#undef DDR_PHY_DX2GCR6_DXDQVREFR3_SHIFT
+#undef DDR_PHY_DX2GCR6_DXDQVREFR3_MASK
 #define DDR_PHY_DX2GCR6_DXDQVREFR3_DEFVAL                      0x09090909
 #define DDR_PHY_DX2GCR6_DXDQVREFR3_SHIFT                       24
 #define DDR_PHY_DX2GCR6_DXDQVREFR3_MASK                        0x3F000000U
@@ -14529,9 +14529,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX2GCR6_RESERVED_23_22_DEFVAL 
-#undef DDR_PHY_DX2GCR6_RESERVED_23_22_SHIFT 
-#undef DDR_PHY_DX2GCR6_RESERVED_23_22_MASK 
+#undef DDR_PHY_DX2GCR6_RESERVED_23_22_DEFVAL
+#undef DDR_PHY_DX2GCR6_RESERVED_23_22_SHIFT
+#undef DDR_PHY_DX2GCR6_RESERVED_23_22_MASK
 #define DDR_PHY_DX2GCR6_RESERVED_23_22_DEFVAL                  0x09090909
 #define DDR_PHY_DX2GCR6_RESERVED_23_22_SHIFT                   22
 #define DDR_PHY_DX2GCR6_RESERVED_23_22_MASK                    0x00C00000U
@@ -14539,9 +14539,9 @@
 /*
 * DRAM DQ VREF Select for Rank2
 */
-#undef DDR_PHY_DX2GCR6_DXDQVREFR2_DEFVAL 
-#undef DDR_PHY_DX2GCR6_DXDQVREFR2_SHIFT 
-#undef DDR_PHY_DX2GCR6_DXDQVREFR2_MASK 
+#undef DDR_PHY_DX2GCR6_DXDQVREFR2_DEFVAL
+#undef DDR_PHY_DX2GCR6_DXDQVREFR2_SHIFT
+#undef DDR_PHY_DX2GCR6_DXDQVREFR2_MASK
 #define DDR_PHY_DX2GCR6_DXDQVREFR2_DEFVAL                      0x09090909
 #define DDR_PHY_DX2GCR6_DXDQVREFR2_SHIFT                       16
 #define DDR_PHY_DX2GCR6_DXDQVREFR2_MASK                        0x003F0000U
@@ -14549,9 +14549,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX2GCR6_RESERVED_15_14_DEFVAL 
-#undef DDR_PHY_DX2GCR6_RESERVED_15_14_SHIFT 
-#undef DDR_PHY_DX2GCR6_RESERVED_15_14_MASK 
+#undef DDR_PHY_DX2GCR6_RESERVED_15_14_DEFVAL
+#undef DDR_PHY_DX2GCR6_RESERVED_15_14_SHIFT
+#undef DDR_PHY_DX2GCR6_RESERVED_15_14_MASK
 #define DDR_PHY_DX2GCR6_RESERVED_15_14_DEFVAL                  0x09090909
 #define DDR_PHY_DX2GCR6_RESERVED_15_14_SHIFT                   14
 #define DDR_PHY_DX2GCR6_RESERVED_15_14_MASK                    0x0000C000U
@@ -14559,9 +14559,9 @@
 /*
 * DRAM DQ VREF Select for Rank1
 */
-#undef DDR_PHY_DX2GCR6_DXDQVREFR1_DEFVAL 
-#undef DDR_PHY_DX2GCR6_DXDQVREFR1_SHIFT 
-#undef DDR_PHY_DX2GCR6_DXDQVREFR1_MASK 
+#undef DDR_PHY_DX2GCR6_DXDQVREFR1_DEFVAL
+#undef DDR_PHY_DX2GCR6_DXDQVREFR1_SHIFT
+#undef DDR_PHY_DX2GCR6_DXDQVREFR1_MASK
 #define DDR_PHY_DX2GCR6_DXDQVREFR1_DEFVAL                      0x09090909
 #define DDR_PHY_DX2GCR6_DXDQVREFR1_SHIFT                       8
 #define DDR_PHY_DX2GCR6_DXDQVREFR1_MASK                        0x00003F00U
@@ -14569,9 +14569,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX2GCR6_RESERVED_7_6_DEFVAL 
-#undef DDR_PHY_DX2GCR6_RESERVED_7_6_SHIFT 
-#undef DDR_PHY_DX2GCR6_RESERVED_7_6_MASK 
+#undef DDR_PHY_DX2GCR6_RESERVED_7_6_DEFVAL
+#undef DDR_PHY_DX2GCR6_RESERVED_7_6_SHIFT
+#undef DDR_PHY_DX2GCR6_RESERVED_7_6_MASK
 #define DDR_PHY_DX2GCR6_RESERVED_7_6_DEFVAL                    0x09090909
 #define DDR_PHY_DX2GCR6_RESERVED_7_6_SHIFT                     6
 #define DDR_PHY_DX2GCR6_RESERVED_7_6_MASK                      0x000000C0U
@@ -14579,9 +14579,9 @@
 /*
 * DRAM DQ VREF Select for Rank0
 */
-#undef DDR_PHY_DX2GCR6_DXDQVREFR0_DEFVAL 
-#undef DDR_PHY_DX2GCR6_DXDQVREFR0_SHIFT 
-#undef DDR_PHY_DX2GCR6_DXDQVREFR0_MASK 
+#undef DDR_PHY_DX2GCR6_DXDQVREFR0_DEFVAL
+#undef DDR_PHY_DX2GCR6_DXDQVREFR0_SHIFT
+#undef DDR_PHY_DX2GCR6_DXDQVREFR0_MASK
 #define DDR_PHY_DX2GCR6_DXDQVREFR0_DEFVAL                      0x09090909
 #define DDR_PHY_DX2GCR6_DXDQVREFR0_SHIFT                       0
 #define DDR_PHY_DX2GCR6_DXDQVREFR0_MASK                        0x0000003FU
@@ -14589,9 +14589,9 @@
 /*
 * Calibration Bypass
 */
-#undef DDR_PHY_DX3GCR0_CALBYP_DEFVAL 
-#undef DDR_PHY_DX3GCR0_CALBYP_SHIFT 
-#undef DDR_PHY_DX3GCR0_CALBYP_MASK 
+#undef DDR_PHY_DX3GCR0_CALBYP_DEFVAL
+#undef DDR_PHY_DX3GCR0_CALBYP_SHIFT
+#undef DDR_PHY_DX3GCR0_CALBYP_MASK
 #define DDR_PHY_DX3GCR0_CALBYP_DEFVAL                          0x40200204
 #define DDR_PHY_DX3GCR0_CALBYP_SHIFT                           31
 #define DDR_PHY_DX3GCR0_CALBYP_MASK                            0x80000000U
@@ -14599,9 +14599,9 @@
 /*
 * Master Delay Line Enable
 */
-#undef DDR_PHY_DX3GCR0_MDLEN_DEFVAL 
-#undef DDR_PHY_DX3GCR0_MDLEN_SHIFT 
-#undef DDR_PHY_DX3GCR0_MDLEN_MASK 
+#undef DDR_PHY_DX3GCR0_MDLEN_DEFVAL
+#undef DDR_PHY_DX3GCR0_MDLEN_SHIFT
+#undef DDR_PHY_DX3GCR0_MDLEN_MASK
 #define DDR_PHY_DX3GCR0_MDLEN_DEFVAL                           0x40200204
 #define DDR_PHY_DX3GCR0_MDLEN_SHIFT                            30
 #define DDR_PHY_DX3GCR0_MDLEN_MASK                             0x40000000U
@@ -14609,9 +14609,9 @@
 /*
 * Configurable ODT(TE) Phase Shift
 */
-#undef DDR_PHY_DX3GCR0_CODTSHFT_DEFVAL 
-#undef DDR_PHY_DX3GCR0_CODTSHFT_SHIFT 
-#undef DDR_PHY_DX3GCR0_CODTSHFT_MASK 
+#undef DDR_PHY_DX3GCR0_CODTSHFT_DEFVAL
+#undef DDR_PHY_DX3GCR0_CODTSHFT_SHIFT
+#undef DDR_PHY_DX3GCR0_CODTSHFT_MASK
 #define DDR_PHY_DX3GCR0_CODTSHFT_DEFVAL                        0x40200204
 #define DDR_PHY_DX3GCR0_CODTSHFT_SHIFT                         28
 #define DDR_PHY_DX3GCR0_CODTSHFT_MASK                          0x30000000U
@@ -14619,9 +14619,9 @@
 /*
 * DQS Duty Cycle Correction
 */
-#undef DDR_PHY_DX3GCR0_DQSDCC_DEFVAL 
-#undef DDR_PHY_DX3GCR0_DQSDCC_SHIFT 
-#undef DDR_PHY_DX3GCR0_DQSDCC_MASK 
+#undef DDR_PHY_DX3GCR0_DQSDCC_DEFVAL
+#undef DDR_PHY_DX3GCR0_DQSDCC_SHIFT
+#undef DDR_PHY_DX3GCR0_DQSDCC_MASK
 #define DDR_PHY_DX3GCR0_DQSDCC_DEFVAL                          0x40200204
 #define DDR_PHY_DX3GCR0_DQSDCC_SHIFT                           24
 #define DDR_PHY_DX3GCR0_DQSDCC_MASK                            0x0F000000U
@@ -14630,9 +14630,9 @@
 * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
     *  input for the respective bypte lane of the PHY
 */
-#undef DDR_PHY_DX3GCR0_RDDLY_DEFVAL 
-#undef DDR_PHY_DX3GCR0_RDDLY_SHIFT 
-#undef DDR_PHY_DX3GCR0_RDDLY_MASK 
+#undef DDR_PHY_DX3GCR0_RDDLY_DEFVAL
+#undef DDR_PHY_DX3GCR0_RDDLY_SHIFT
+#undef DDR_PHY_DX3GCR0_RDDLY_MASK
 #define DDR_PHY_DX3GCR0_RDDLY_DEFVAL                           0x40200204
 #define DDR_PHY_DX3GCR0_RDDLY_SHIFT                            20
 #define DDR_PHY_DX3GCR0_RDDLY_MASK                             0x00F00000U
@@ -14640,9 +14640,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX3GCR0_RESERVED_19_14_DEFVAL 
-#undef DDR_PHY_DX3GCR0_RESERVED_19_14_SHIFT 
-#undef DDR_PHY_DX3GCR0_RESERVED_19_14_MASK 
+#undef DDR_PHY_DX3GCR0_RESERVED_19_14_DEFVAL
+#undef DDR_PHY_DX3GCR0_RESERVED_19_14_SHIFT
+#undef DDR_PHY_DX3GCR0_RESERVED_19_14_MASK
 #define DDR_PHY_DX3GCR0_RESERVED_19_14_DEFVAL                  0x40200204
 #define DDR_PHY_DX3GCR0_RESERVED_19_14_SHIFT                   14
 #define DDR_PHY_DX3GCR0_RESERVED_19_14_MASK                    0x000FC000U
@@ -14650,9 +14650,9 @@
 /*
 * DQSNSE Power Down Receiver
 */
-#undef DDR_PHY_DX3GCR0_DQSNSEPDR_DEFVAL 
-#undef DDR_PHY_DX3GCR0_DQSNSEPDR_SHIFT 
-#undef DDR_PHY_DX3GCR0_DQSNSEPDR_MASK 
+#undef DDR_PHY_DX3GCR0_DQSNSEPDR_DEFVAL
+#undef DDR_PHY_DX3GCR0_DQSNSEPDR_SHIFT
+#undef DDR_PHY_DX3GCR0_DQSNSEPDR_MASK
 #define DDR_PHY_DX3GCR0_DQSNSEPDR_DEFVAL                       0x40200204
 #define DDR_PHY_DX3GCR0_DQSNSEPDR_SHIFT                        13
 #define DDR_PHY_DX3GCR0_DQSNSEPDR_MASK                         0x00002000U
@@ -14660,9 +14660,9 @@
 /*
 * DQSSE Power Down Receiver
 */
-#undef DDR_PHY_DX3GCR0_DQSSEPDR_DEFVAL 
-#undef DDR_PHY_DX3GCR0_DQSSEPDR_SHIFT 
-#undef DDR_PHY_DX3GCR0_DQSSEPDR_MASK 
+#undef DDR_PHY_DX3GCR0_DQSSEPDR_DEFVAL
+#undef DDR_PHY_DX3GCR0_DQSSEPDR_SHIFT
+#undef DDR_PHY_DX3GCR0_DQSSEPDR_MASK
 #define DDR_PHY_DX3GCR0_DQSSEPDR_DEFVAL                        0x40200204
 #define DDR_PHY_DX3GCR0_DQSSEPDR_SHIFT                         12
 #define DDR_PHY_DX3GCR0_DQSSEPDR_MASK                          0x00001000U
@@ -14670,9 +14670,9 @@
 /*
 * RTT On Additive Latency
 */
-#undef DDR_PHY_DX3GCR0_RTTOAL_DEFVAL 
-#undef DDR_PHY_DX3GCR0_RTTOAL_SHIFT 
-#undef DDR_PHY_DX3GCR0_RTTOAL_MASK 
+#undef DDR_PHY_DX3GCR0_RTTOAL_DEFVAL
+#undef DDR_PHY_DX3GCR0_RTTOAL_SHIFT
+#undef DDR_PHY_DX3GCR0_RTTOAL_MASK
 #define DDR_PHY_DX3GCR0_RTTOAL_DEFVAL                          0x40200204
 #define DDR_PHY_DX3GCR0_RTTOAL_SHIFT                           11
 #define DDR_PHY_DX3GCR0_RTTOAL_MASK                            0x00000800U
@@ -14680,9 +14680,9 @@
 /*
 * RTT Output Hold
 */
-#undef DDR_PHY_DX3GCR0_RTTOH_DEFVAL 
-#undef DDR_PHY_DX3GCR0_RTTOH_SHIFT 
-#undef DDR_PHY_DX3GCR0_RTTOH_MASK 
+#undef DDR_PHY_DX3GCR0_RTTOH_DEFVAL
+#undef DDR_PHY_DX3GCR0_RTTOH_SHIFT
+#undef DDR_PHY_DX3GCR0_RTTOH_MASK
 #define DDR_PHY_DX3GCR0_RTTOH_DEFVAL                           0x40200204
 #define DDR_PHY_DX3GCR0_RTTOH_SHIFT                            9
 #define DDR_PHY_DX3GCR0_RTTOH_MASK                             0x00000600U
@@ -14690,9 +14690,9 @@
 /*
 * Configurable PDR Phase Shift
 */
-#undef DDR_PHY_DX3GCR0_CPDRSHFT_DEFVAL 
-#undef DDR_PHY_DX3GCR0_CPDRSHFT_SHIFT 
-#undef DDR_PHY_DX3GCR0_CPDRSHFT_MASK 
+#undef DDR_PHY_DX3GCR0_CPDRSHFT_DEFVAL
+#undef DDR_PHY_DX3GCR0_CPDRSHFT_SHIFT
+#undef DDR_PHY_DX3GCR0_CPDRSHFT_MASK
 #define DDR_PHY_DX3GCR0_CPDRSHFT_DEFVAL                        0x40200204
 #define DDR_PHY_DX3GCR0_CPDRSHFT_SHIFT                         7
 #define DDR_PHY_DX3GCR0_CPDRSHFT_MASK                          0x00000180U
@@ -14700,9 +14700,9 @@
 /*
 * DQSR Power Down
 */
-#undef DDR_PHY_DX3GCR0_DQSRPD_DEFVAL 
-#undef DDR_PHY_DX3GCR0_DQSRPD_SHIFT 
-#undef DDR_PHY_DX3GCR0_DQSRPD_MASK 
+#undef DDR_PHY_DX3GCR0_DQSRPD_DEFVAL
+#undef DDR_PHY_DX3GCR0_DQSRPD_SHIFT
+#undef DDR_PHY_DX3GCR0_DQSRPD_MASK
 #define DDR_PHY_DX3GCR0_DQSRPD_DEFVAL                          0x40200204
 #define DDR_PHY_DX3GCR0_DQSRPD_SHIFT                           6
 #define DDR_PHY_DX3GCR0_DQSRPD_MASK                            0x00000040U
@@ -14710,9 +14710,9 @@
 /*
 * DQSG Power Down Receiver
 */
-#undef DDR_PHY_DX3GCR0_DQSGPDR_DEFVAL 
-#undef DDR_PHY_DX3GCR0_DQSGPDR_SHIFT 
-#undef DDR_PHY_DX3GCR0_DQSGPDR_MASK 
+#undef DDR_PHY_DX3GCR0_DQSGPDR_DEFVAL
+#undef DDR_PHY_DX3GCR0_DQSGPDR_SHIFT
+#undef DDR_PHY_DX3GCR0_DQSGPDR_MASK
 #define DDR_PHY_DX3GCR0_DQSGPDR_DEFVAL                         0x40200204
 #define DDR_PHY_DX3GCR0_DQSGPDR_SHIFT                          5
 #define DDR_PHY_DX3GCR0_DQSGPDR_MASK                           0x00000020U
@@ -14720,9 +14720,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX3GCR0_RESERVED_4_DEFVAL 
-#undef DDR_PHY_DX3GCR0_RESERVED_4_SHIFT 
-#undef DDR_PHY_DX3GCR0_RESERVED_4_MASK 
+#undef DDR_PHY_DX3GCR0_RESERVED_4_DEFVAL
+#undef DDR_PHY_DX3GCR0_RESERVED_4_SHIFT
+#undef DDR_PHY_DX3GCR0_RESERVED_4_MASK
 #define DDR_PHY_DX3GCR0_RESERVED_4_DEFVAL                      0x40200204
 #define DDR_PHY_DX3GCR0_RESERVED_4_SHIFT                       4
 #define DDR_PHY_DX3GCR0_RESERVED_4_MASK                        0x00000010U
@@ -14730,9 +14730,9 @@
 /*
 * DQSG On-Die Termination
 */
-#undef DDR_PHY_DX3GCR0_DQSGODT_DEFVAL 
-#undef DDR_PHY_DX3GCR0_DQSGODT_SHIFT 
-#undef DDR_PHY_DX3GCR0_DQSGODT_MASK 
+#undef DDR_PHY_DX3GCR0_DQSGODT_DEFVAL
+#undef DDR_PHY_DX3GCR0_DQSGODT_SHIFT
+#undef DDR_PHY_DX3GCR0_DQSGODT_MASK
 #define DDR_PHY_DX3GCR0_DQSGODT_DEFVAL                         0x40200204
 #define DDR_PHY_DX3GCR0_DQSGODT_SHIFT                          3
 #define DDR_PHY_DX3GCR0_DQSGODT_MASK                           0x00000008U
@@ -14740,9 +14740,9 @@
 /*
 * DQSG Output Enable
 */
-#undef DDR_PHY_DX3GCR0_DQSGOE_DEFVAL 
-#undef DDR_PHY_DX3GCR0_DQSGOE_SHIFT 
-#undef DDR_PHY_DX3GCR0_DQSGOE_MASK 
+#undef DDR_PHY_DX3GCR0_DQSGOE_DEFVAL
+#undef DDR_PHY_DX3GCR0_DQSGOE_SHIFT
+#undef DDR_PHY_DX3GCR0_DQSGOE_MASK
 #define DDR_PHY_DX3GCR0_DQSGOE_DEFVAL                          0x40200204
 #define DDR_PHY_DX3GCR0_DQSGOE_SHIFT                           2
 #define DDR_PHY_DX3GCR0_DQSGOE_MASK                            0x00000004U
@@ -14750,9 +14750,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX3GCR0_RESERVED_1_0_DEFVAL 
-#undef DDR_PHY_DX3GCR0_RESERVED_1_0_SHIFT 
-#undef DDR_PHY_DX3GCR0_RESERVED_1_0_MASK 
+#undef DDR_PHY_DX3GCR0_RESERVED_1_0_DEFVAL
+#undef DDR_PHY_DX3GCR0_RESERVED_1_0_SHIFT
+#undef DDR_PHY_DX3GCR0_RESERVED_1_0_MASK
 #define DDR_PHY_DX3GCR0_RESERVED_1_0_DEFVAL                    0x40200204
 #define DDR_PHY_DX3GCR0_RESERVED_1_0_SHIFT                     0
 #define DDR_PHY_DX3GCR0_RESERVED_1_0_MASK                      0x00000003U
@@ -14760,9 +14760,9 @@
 /*
 * Enables the PDR mode for DQ[7:0]
 */
-#undef DDR_PHY_DX3GCR1_DXPDRMODE_DEFVAL 
-#undef DDR_PHY_DX3GCR1_DXPDRMODE_SHIFT 
-#undef DDR_PHY_DX3GCR1_DXPDRMODE_MASK 
+#undef DDR_PHY_DX3GCR1_DXPDRMODE_DEFVAL
+#undef DDR_PHY_DX3GCR1_DXPDRMODE_SHIFT
+#undef DDR_PHY_DX3GCR1_DXPDRMODE_MASK
 #define DDR_PHY_DX3GCR1_DXPDRMODE_DEFVAL                       0x00007FFF
 #define DDR_PHY_DX3GCR1_DXPDRMODE_SHIFT                        16
 #define DDR_PHY_DX3GCR1_DXPDRMODE_MASK                         0xFFFF0000U
@@ -14770,9 +14770,9 @@
 /*
 * Reserved. Returns zeroes on reads.
 */
-#undef DDR_PHY_DX3GCR1_RESERVED_15_DEFVAL 
-#undef DDR_PHY_DX3GCR1_RESERVED_15_SHIFT 
-#undef DDR_PHY_DX3GCR1_RESERVED_15_MASK 
+#undef DDR_PHY_DX3GCR1_RESERVED_15_DEFVAL
+#undef DDR_PHY_DX3GCR1_RESERVED_15_SHIFT
+#undef DDR_PHY_DX3GCR1_RESERVED_15_MASK
 #define DDR_PHY_DX3GCR1_RESERVED_15_DEFVAL                     0x00007FFF
 #define DDR_PHY_DX3GCR1_RESERVED_15_SHIFT                      15
 #define DDR_PHY_DX3GCR1_RESERVED_15_MASK                       0x00008000U
@@ -14780,9 +14780,9 @@
 /*
 * Select the delayed or non-delayed read data strobe #
 */
-#undef DDR_PHY_DX3GCR1_QSNSEL_DEFVAL 
-#undef DDR_PHY_DX3GCR1_QSNSEL_SHIFT 
-#undef DDR_PHY_DX3GCR1_QSNSEL_MASK 
+#undef DDR_PHY_DX3GCR1_QSNSEL_DEFVAL
+#undef DDR_PHY_DX3GCR1_QSNSEL_SHIFT
+#undef DDR_PHY_DX3GCR1_QSNSEL_MASK
 #define DDR_PHY_DX3GCR1_QSNSEL_DEFVAL                          0x00007FFF
 #define DDR_PHY_DX3GCR1_QSNSEL_SHIFT                           14
 #define DDR_PHY_DX3GCR1_QSNSEL_MASK                            0x00004000U
@@ -14790,9 +14790,9 @@
 /*
 * Select the delayed or non-delayed read data strobe
 */
-#undef DDR_PHY_DX3GCR1_QSSEL_DEFVAL 
-#undef DDR_PHY_DX3GCR1_QSSEL_SHIFT 
-#undef DDR_PHY_DX3GCR1_QSSEL_MASK 
+#undef DDR_PHY_DX3GCR1_QSSEL_DEFVAL
+#undef DDR_PHY_DX3GCR1_QSSEL_SHIFT
+#undef DDR_PHY_DX3GCR1_QSSEL_MASK
 #define DDR_PHY_DX3GCR1_QSSEL_DEFVAL                           0x00007FFF
 #define DDR_PHY_DX3GCR1_QSSEL_SHIFT                            13
 #define DDR_PHY_DX3GCR1_QSSEL_MASK                             0x00002000U
@@ -14800,9 +14800,9 @@
 /*
 * Enables Read Data Strobe in a byte lane
 */
-#undef DDR_PHY_DX3GCR1_OEEN_DEFVAL 
-#undef DDR_PHY_DX3GCR1_OEEN_SHIFT 
-#undef DDR_PHY_DX3GCR1_OEEN_MASK 
+#undef DDR_PHY_DX3GCR1_OEEN_DEFVAL
+#undef DDR_PHY_DX3GCR1_OEEN_SHIFT
+#undef DDR_PHY_DX3GCR1_OEEN_MASK
 #define DDR_PHY_DX3GCR1_OEEN_DEFVAL                            0x00007FFF
 #define DDR_PHY_DX3GCR1_OEEN_SHIFT                             12
 #define DDR_PHY_DX3GCR1_OEEN_MASK                              0x00001000U
@@ -14810,9 +14810,9 @@
 /*
 * Enables PDR in a byte lane
 */
-#undef DDR_PHY_DX3GCR1_PDREN_DEFVAL 
-#undef DDR_PHY_DX3GCR1_PDREN_SHIFT 
-#undef DDR_PHY_DX3GCR1_PDREN_MASK 
+#undef DDR_PHY_DX3GCR1_PDREN_DEFVAL
+#undef DDR_PHY_DX3GCR1_PDREN_SHIFT
+#undef DDR_PHY_DX3GCR1_PDREN_MASK
 #define DDR_PHY_DX3GCR1_PDREN_DEFVAL                           0x00007FFF
 #define DDR_PHY_DX3GCR1_PDREN_SHIFT                            11
 #define DDR_PHY_DX3GCR1_PDREN_MASK                             0x00000800U
@@ -14820,9 +14820,9 @@
 /*
 * Enables ODT/TE in a byte lane
 */
-#undef DDR_PHY_DX3GCR1_TEEN_DEFVAL 
-#undef DDR_PHY_DX3GCR1_TEEN_SHIFT 
-#undef DDR_PHY_DX3GCR1_TEEN_MASK 
+#undef DDR_PHY_DX3GCR1_TEEN_DEFVAL
+#undef DDR_PHY_DX3GCR1_TEEN_SHIFT
+#undef DDR_PHY_DX3GCR1_TEEN_MASK
 #define DDR_PHY_DX3GCR1_TEEN_DEFVAL                            0x00007FFF
 #define DDR_PHY_DX3GCR1_TEEN_SHIFT                             10
 #define DDR_PHY_DX3GCR1_TEEN_MASK                              0x00000400U
@@ -14830,9 +14830,9 @@
 /*
 * Enables Write Data strobe in a byte lane
 */
-#undef DDR_PHY_DX3GCR1_DSEN_DEFVAL 
-#undef DDR_PHY_DX3GCR1_DSEN_SHIFT 
-#undef DDR_PHY_DX3GCR1_DSEN_MASK 
+#undef DDR_PHY_DX3GCR1_DSEN_DEFVAL
+#undef DDR_PHY_DX3GCR1_DSEN_SHIFT
+#undef DDR_PHY_DX3GCR1_DSEN_MASK
 #define DDR_PHY_DX3GCR1_DSEN_DEFVAL                            0x00007FFF
 #define DDR_PHY_DX3GCR1_DSEN_SHIFT                             9
 #define DDR_PHY_DX3GCR1_DSEN_MASK                              0x00000200U
@@ -14840,9 +14840,9 @@
 /*
 * Enables DM pin in a byte lane
 */
-#undef DDR_PHY_DX3GCR1_DMEN_DEFVAL 
-#undef DDR_PHY_DX3GCR1_DMEN_SHIFT 
-#undef DDR_PHY_DX3GCR1_DMEN_MASK 
+#undef DDR_PHY_DX3GCR1_DMEN_DEFVAL
+#undef DDR_PHY_DX3GCR1_DMEN_SHIFT
+#undef DDR_PHY_DX3GCR1_DMEN_MASK
 #define DDR_PHY_DX3GCR1_DMEN_DEFVAL                            0x00007FFF
 #define DDR_PHY_DX3GCR1_DMEN_SHIFT                             8
 #define DDR_PHY_DX3GCR1_DMEN_MASK                              0x00000100U
@@ -14850,9 +14850,9 @@
 /*
 * Enables DQ corresponding to each bit in a byte
 */
-#undef DDR_PHY_DX3GCR1_DQEN_DEFVAL 
-#undef DDR_PHY_DX3GCR1_DQEN_SHIFT 
-#undef DDR_PHY_DX3GCR1_DQEN_MASK 
+#undef DDR_PHY_DX3GCR1_DQEN_DEFVAL
+#undef DDR_PHY_DX3GCR1_DQEN_SHIFT
+#undef DDR_PHY_DX3GCR1_DQEN_MASK
 #define DDR_PHY_DX3GCR1_DQEN_DEFVAL                            0x00007FFF
 #define DDR_PHY_DX3GCR1_DQEN_SHIFT                             0
 #define DDR_PHY_DX3GCR1_DQEN_MASK                              0x000000FFU
@@ -14860,9 +14860,9 @@
 /*
 * Byte lane VREF IOM (Used only by D4MU IOs)
 */
-#undef DDR_PHY_DX3GCR4_RESERVED_31_29_DEFVAL 
-#undef DDR_PHY_DX3GCR4_RESERVED_31_29_SHIFT 
-#undef DDR_PHY_DX3GCR4_RESERVED_31_29_MASK 
+#undef DDR_PHY_DX3GCR4_RESERVED_31_29_DEFVAL
+#undef DDR_PHY_DX3GCR4_RESERVED_31_29_SHIFT
+#undef DDR_PHY_DX3GCR4_RESERVED_31_29_MASK
 #define DDR_PHY_DX3GCR4_RESERVED_31_29_DEFVAL                  0x0E00003C
 #define DDR_PHY_DX3GCR4_RESERVED_31_29_SHIFT                   29
 #define DDR_PHY_DX3GCR4_RESERVED_31_29_MASK                    0xE0000000U
@@ -14870,9 +14870,9 @@
 /*
 * Byte Lane VREF Pad Enable
 */
-#undef DDR_PHY_DX3GCR4_DXREFPEN_DEFVAL 
-#undef DDR_PHY_DX3GCR4_DXREFPEN_SHIFT 
-#undef DDR_PHY_DX3GCR4_DXREFPEN_MASK 
+#undef DDR_PHY_DX3GCR4_DXREFPEN_DEFVAL
+#undef DDR_PHY_DX3GCR4_DXREFPEN_SHIFT
+#undef DDR_PHY_DX3GCR4_DXREFPEN_MASK
 #define DDR_PHY_DX3GCR4_DXREFPEN_DEFVAL                        0x0E00003C
 #define DDR_PHY_DX3GCR4_DXREFPEN_SHIFT                         28
 #define DDR_PHY_DX3GCR4_DXREFPEN_MASK                          0x10000000U
@@ -14880,9 +14880,9 @@
 /*
 * Byte Lane Internal VREF Enable
 */
-#undef DDR_PHY_DX3GCR4_DXREFEEN_DEFVAL 
-#undef DDR_PHY_DX3GCR4_DXREFEEN_SHIFT 
-#undef DDR_PHY_DX3GCR4_DXREFEEN_MASK 
+#undef DDR_PHY_DX3GCR4_DXREFEEN_DEFVAL
+#undef DDR_PHY_DX3GCR4_DXREFEEN_SHIFT
+#undef DDR_PHY_DX3GCR4_DXREFEEN_MASK
 #define DDR_PHY_DX3GCR4_DXREFEEN_DEFVAL                        0x0E00003C
 #define DDR_PHY_DX3GCR4_DXREFEEN_SHIFT                         26
 #define DDR_PHY_DX3GCR4_DXREFEEN_MASK                          0x0C000000U
@@ -14890,9 +14890,9 @@
 /*
 * Byte Lane Single-End VREF Enable
 */
-#undef DDR_PHY_DX3GCR4_DXREFSEN_DEFVAL 
-#undef DDR_PHY_DX3GCR4_DXREFSEN_SHIFT 
-#undef DDR_PHY_DX3GCR4_DXREFSEN_MASK 
+#undef DDR_PHY_DX3GCR4_DXREFSEN_DEFVAL
+#undef DDR_PHY_DX3GCR4_DXREFSEN_SHIFT
+#undef DDR_PHY_DX3GCR4_DXREFSEN_MASK
 #define DDR_PHY_DX3GCR4_DXREFSEN_DEFVAL                        0x0E00003C
 #define DDR_PHY_DX3GCR4_DXREFSEN_SHIFT                         25
 #define DDR_PHY_DX3GCR4_DXREFSEN_MASK                          0x02000000U
@@ -14900,9 +14900,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX3GCR4_RESERVED_24_DEFVAL 
-#undef DDR_PHY_DX3GCR4_RESERVED_24_SHIFT 
-#undef DDR_PHY_DX3GCR4_RESERVED_24_MASK 
+#undef DDR_PHY_DX3GCR4_RESERVED_24_DEFVAL
+#undef DDR_PHY_DX3GCR4_RESERVED_24_SHIFT
+#undef DDR_PHY_DX3GCR4_RESERVED_24_MASK
 #define DDR_PHY_DX3GCR4_RESERVED_24_DEFVAL                     0x0E00003C
 #define DDR_PHY_DX3GCR4_RESERVED_24_SHIFT                      24
 #define DDR_PHY_DX3GCR4_RESERVED_24_MASK                       0x01000000U
@@ -14910,9 +14910,9 @@
 /*
 * External VREF generator REFSEL range select
 */
-#undef DDR_PHY_DX3GCR4_DXREFESELRANGE_DEFVAL 
-#undef DDR_PHY_DX3GCR4_DXREFESELRANGE_SHIFT 
-#undef DDR_PHY_DX3GCR4_DXREFESELRANGE_MASK 
+#undef DDR_PHY_DX3GCR4_DXREFESELRANGE_DEFVAL
+#undef DDR_PHY_DX3GCR4_DXREFESELRANGE_SHIFT
+#undef DDR_PHY_DX3GCR4_DXREFESELRANGE_MASK
 #define DDR_PHY_DX3GCR4_DXREFESELRANGE_DEFVAL                  0x0E00003C
 #define DDR_PHY_DX3GCR4_DXREFESELRANGE_SHIFT                   23
 #define DDR_PHY_DX3GCR4_DXREFESELRANGE_MASK                    0x00800000U
@@ -14920,9 +14920,9 @@
 /*
 * Byte Lane External VREF Select
 */
-#undef DDR_PHY_DX3GCR4_DXREFESEL_DEFVAL 
-#undef DDR_PHY_DX3GCR4_DXREFESEL_SHIFT 
-#undef DDR_PHY_DX3GCR4_DXREFESEL_MASK 
+#undef DDR_PHY_DX3GCR4_DXREFESEL_DEFVAL
+#undef DDR_PHY_DX3GCR4_DXREFESEL_SHIFT
+#undef DDR_PHY_DX3GCR4_DXREFESEL_MASK
 #define DDR_PHY_DX3GCR4_DXREFESEL_DEFVAL                       0x0E00003C
 #define DDR_PHY_DX3GCR4_DXREFESEL_SHIFT                        16
 #define DDR_PHY_DX3GCR4_DXREFESEL_MASK                         0x007F0000U
@@ -14930,9 +14930,9 @@
 /*
 * Single ended VREF generator REFSEL range select
 */
-#undef DDR_PHY_DX3GCR4_DXREFSSELRANGE_DEFVAL 
-#undef DDR_PHY_DX3GCR4_DXREFSSELRANGE_SHIFT 
-#undef DDR_PHY_DX3GCR4_DXREFSSELRANGE_MASK 
+#undef DDR_PHY_DX3GCR4_DXREFSSELRANGE_DEFVAL
+#undef DDR_PHY_DX3GCR4_DXREFSSELRANGE_SHIFT
+#undef DDR_PHY_DX3GCR4_DXREFSSELRANGE_MASK
 #define DDR_PHY_DX3GCR4_DXREFSSELRANGE_DEFVAL                  0x0E00003C
 #define DDR_PHY_DX3GCR4_DXREFSSELRANGE_SHIFT                   15
 #define DDR_PHY_DX3GCR4_DXREFSSELRANGE_MASK                    0x00008000U
@@ -14940,9 +14940,9 @@
 /*
 * Byte Lane Single-End VREF Select
 */
-#undef DDR_PHY_DX3GCR4_DXREFSSEL_DEFVAL 
-#undef DDR_PHY_DX3GCR4_DXREFSSEL_SHIFT 
-#undef DDR_PHY_DX3GCR4_DXREFSSEL_MASK 
+#undef DDR_PHY_DX3GCR4_DXREFSSEL_DEFVAL
+#undef DDR_PHY_DX3GCR4_DXREFSSEL_SHIFT
+#undef DDR_PHY_DX3GCR4_DXREFSSEL_MASK
 #define DDR_PHY_DX3GCR4_DXREFSSEL_DEFVAL                       0x0E00003C
 #define DDR_PHY_DX3GCR4_DXREFSSEL_SHIFT                        8
 #define DDR_PHY_DX3GCR4_DXREFSSEL_MASK                         0x00007F00U
@@ -14950,9 +14950,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX3GCR4_RESERVED_7_6_DEFVAL 
-#undef DDR_PHY_DX3GCR4_RESERVED_7_6_SHIFT 
-#undef DDR_PHY_DX3GCR4_RESERVED_7_6_MASK 
+#undef DDR_PHY_DX3GCR4_RESERVED_7_6_DEFVAL
+#undef DDR_PHY_DX3GCR4_RESERVED_7_6_SHIFT
+#undef DDR_PHY_DX3GCR4_RESERVED_7_6_MASK
 #define DDR_PHY_DX3GCR4_RESERVED_7_6_DEFVAL                    0x0E00003C
 #define DDR_PHY_DX3GCR4_RESERVED_7_6_SHIFT                     6
 #define DDR_PHY_DX3GCR4_RESERVED_7_6_MASK                      0x000000C0U
@@ -14960,9 +14960,9 @@
 /*
 * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
 */
-#undef DDR_PHY_DX3GCR4_DXREFIEN_DEFVAL 
-#undef DDR_PHY_DX3GCR4_DXREFIEN_SHIFT 
-#undef DDR_PHY_DX3GCR4_DXREFIEN_MASK 
+#undef DDR_PHY_DX3GCR4_DXREFIEN_DEFVAL
+#undef DDR_PHY_DX3GCR4_DXREFIEN_SHIFT
+#undef DDR_PHY_DX3GCR4_DXREFIEN_MASK
 #define DDR_PHY_DX3GCR4_DXREFIEN_DEFVAL                        0x0E00003C
 #define DDR_PHY_DX3GCR4_DXREFIEN_SHIFT                         2
 #define DDR_PHY_DX3GCR4_DXREFIEN_MASK                          0x0000003CU
@@ -14970,9 +14970,9 @@
 /*
 * VRMON control for DQ IO (Single Ended) buffers of a byte lane.
 */
-#undef DDR_PHY_DX3GCR4_DXREFIMON_DEFVAL 
-#undef DDR_PHY_DX3GCR4_DXREFIMON_SHIFT 
-#undef DDR_PHY_DX3GCR4_DXREFIMON_MASK 
+#undef DDR_PHY_DX3GCR4_DXREFIMON_DEFVAL
+#undef DDR_PHY_DX3GCR4_DXREFIMON_SHIFT
+#undef DDR_PHY_DX3GCR4_DXREFIMON_MASK
 #define DDR_PHY_DX3GCR4_DXREFIMON_DEFVAL                       0x0E00003C
 #define DDR_PHY_DX3GCR4_DXREFIMON_SHIFT                        0
 #define DDR_PHY_DX3GCR4_DXREFIMON_MASK                         0x00000003U
@@ -14980,9 +14980,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX3GCR5_RESERVED_31_DEFVAL 
-#undef DDR_PHY_DX3GCR5_RESERVED_31_SHIFT 
-#undef DDR_PHY_DX3GCR5_RESERVED_31_MASK 
+#undef DDR_PHY_DX3GCR5_RESERVED_31_DEFVAL
+#undef DDR_PHY_DX3GCR5_RESERVED_31_SHIFT
+#undef DDR_PHY_DX3GCR5_RESERVED_31_MASK
 #define DDR_PHY_DX3GCR5_RESERVED_31_DEFVAL                     0x09090909
 #define DDR_PHY_DX3GCR5_RESERVED_31_SHIFT                      31
 #define DDR_PHY_DX3GCR5_RESERVED_31_MASK                       0x80000000U
@@ -14990,9 +14990,9 @@
 /*
 * Byte Lane internal VREF Select for Rank 3
 */
-#undef DDR_PHY_DX3GCR5_DXREFISELR3_DEFVAL 
-#undef DDR_PHY_DX3GCR5_DXREFISELR3_SHIFT 
-#undef DDR_PHY_DX3GCR5_DXREFISELR3_MASK 
+#undef DDR_PHY_DX3GCR5_DXREFISELR3_DEFVAL
+#undef DDR_PHY_DX3GCR5_DXREFISELR3_SHIFT
+#undef DDR_PHY_DX3GCR5_DXREFISELR3_MASK
 #define DDR_PHY_DX3GCR5_DXREFISELR3_DEFVAL                     0x09090909
 #define DDR_PHY_DX3GCR5_DXREFISELR3_SHIFT                      24
 #define DDR_PHY_DX3GCR5_DXREFISELR3_MASK                       0x7F000000U
@@ -15000,9 +15000,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX3GCR5_RESERVED_23_DEFVAL 
-#undef DDR_PHY_DX3GCR5_RESERVED_23_SHIFT 
-#undef DDR_PHY_DX3GCR5_RESERVED_23_MASK 
+#undef DDR_PHY_DX3GCR5_RESERVED_23_DEFVAL
+#undef DDR_PHY_DX3GCR5_RESERVED_23_SHIFT
+#undef DDR_PHY_DX3GCR5_RESERVED_23_MASK
 #define DDR_PHY_DX3GCR5_RESERVED_23_DEFVAL                     0x09090909
 #define DDR_PHY_DX3GCR5_RESERVED_23_SHIFT                      23
 #define DDR_PHY_DX3GCR5_RESERVED_23_MASK                       0x00800000U
@@ -15010,9 +15010,9 @@
 /*
 * Byte Lane internal VREF Select for Rank 2
 */
-#undef DDR_PHY_DX3GCR5_DXREFISELR2_DEFVAL 
-#undef DDR_PHY_DX3GCR5_DXREFISELR2_SHIFT 
-#undef DDR_PHY_DX3GCR5_DXREFISELR2_MASK 
+#undef DDR_PHY_DX3GCR5_DXREFISELR2_DEFVAL
+#undef DDR_PHY_DX3GCR5_DXREFISELR2_SHIFT
+#undef DDR_PHY_DX3GCR5_DXREFISELR2_MASK
 #define DDR_PHY_DX3GCR5_DXREFISELR2_DEFVAL                     0x09090909
 #define DDR_PHY_DX3GCR5_DXREFISELR2_SHIFT                      16
 #define DDR_PHY_DX3GCR5_DXREFISELR2_MASK                       0x007F0000U
@@ -15020,9 +15020,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX3GCR5_RESERVED_15_DEFVAL 
-#undef DDR_PHY_DX3GCR5_RESERVED_15_SHIFT 
-#undef DDR_PHY_DX3GCR5_RESERVED_15_MASK 
+#undef DDR_PHY_DX3GCR5_RESERVED_15_DEFVAL
+#undef DDR_PHY_DX3GCR5_RESERVED_15_SHIFT
+#undef DDR_PHY_DX3GCR5_RESERVED_15_MASK
 #define DDR_PHY_DX3GCR5_RESERVED_15_DEFVAL                     0x09090909
 #define DDR_PHY_DX3GCR5_RESERVED_15_SHIFT                      15
 #define DDR_PHY_DX3GCR5_RESERVED_15_MASK                       0x00008000U
@@ -15030,9 +15030,9 @@
 /*
 * Byte Lane internal VREF Select for Rank 1
 */
-#undef DDR_PHY_DX3GCR5_DXREFISELR1_DEFVAL 
-#undef DDR_PHY_DX3GCR5_DXREFISELR1_SHIFT 
-#undef DDR_PHY_DX3GCR5_DXREFISELR1_MASK 
+#undef DDR_PHY_DX3GCR5_DXREFISELR1_DEFVAL
+#undef DDR_PHY_DX3GCR5_DXREFISELR1_SHIFT
+#undef DDR_PHY_DX3GCR5_DXREFISELR1_MASK
 #define DDR_PHY_DX3GCR5_DXREFISELR1_DEFVAL                     0x09090909
 #define DDR_PHY_DX3GCR5_DXREFISELR1_SHIFT                      8
 #define DDR_PHY_DX3GCR5_DXREFISELR1_MASK                       0x00007F00U
@@ -15040,9 +15040,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX3GCR5_RESERVED_7_DEFVAL 
-#undef DDR_PHY_DX3GCR5_RESERVED_7_SHIFT 
-#undef DDR_PHY_DX3GCR5_RESERVED_7_MASK 
+#undef DDR_PHY_DX3GCR5_RESERVED_7_DEFVAL
+#undef DDR_PHY_DX3GCR5_RESERVED_7_SHIFT
+#undef DDR_PHY_DX3GCR5_RESERVED_7_MASK
 #define DDR_PHY_DX3GCR5_RESERVED_7_DEFVAL                      0x09090909
 #define DDR_PHY_DX3GCR5_RESERVED_7_SHIFT                       7
 #define DDR_PHY_DX3GCR5_RESERVED_7_MASK                        0x00000080U
@@ -15050,9 +15050,9 @@
 /*
 * Byte Lane internal VREF Select for Rank 0
 */
-#undef DDR_PHY_DX3GCR5_DXREFISELR0_DEFVAL 
-#undef DDR_PHY_DX3GCR5_DXREFISELR0_SHIFT 
-#undef DDR_PHY_DX3GCR5_DXREFISELR0_MASK 
+#undef DDR_PHY_DX3GCR5_DXREFISELR0_DEFVAL
+#undef DDR_PHY_DX3GCR5_DXREFISELR0_SHIFT
+#undef DDR_PHY_DX3GCR5_DXREFISELR0_MASK
 #define DDR_PHY_DX3GCR5_DXREFISELR0_DEFVAL                     0x09090909
 #define DDR_PHY_DX3GCR5_DXREFISELR0_SHIFT                      0
 #define DDR_PHY_DX3GCR5_DXREFISELR0_MASK                       0x0000007FU
@@ -15060,9 +15060,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX3GCR6_RESERVED_31_30_DEFVAL 
-#undef DDR_PHY_DX3GCR6_RESERVED_31_30_SHIFT 
-#undef DDR_PHY_DX3GCR6_RESERVED_31_30_MASK 
+#undef DDR_PHY_DX3GCR6_RESERVED_31_30_DEFVAL
+#undef DDR_PHY_DX3GCR6_RESERVED_31_30_SHIFT
+#undef DDR_PHY_DX3GCR6_RESERVED_31_30_MASK
 #define DDR_PHY_DX3GCR6_RESERVED_31_30_DEFVAL                  0x09090909
 #define DDR_PHY_DX3GCR6_RESERVED_31_30_SHIFT                   30
 #define DDR_PHY_DX3GCR6_RESERVED_31_30_MASK                    0xC0000000U
@@ -15070,9 +15070,9 @@
 /*
 * DRAM DQ VREF Select for Rank3
 */
-#undef DDR_PHY_DX3GCR6_DXDQVREFR3_DEFVAL 
-#undef DDR_PHY_DX3GCR6_DXDQVREFR3_SHIFT 
-#undef DDR_PHY_DX3GCR6_DXDQVREFR3_MASK 
+#undef DDR_PHY_DX3GCR6_DXDQVREFR3_DEFVAL
+#undef DDR_PHY_DX3GCR6_DXDQVREFR3_SHIFT
+#undef DDR_PHY_DX3GCR6_DXDQVREFR3_MASK
 #define DDR_PHY_DX3GCR6_DXDQVREFR3_DEFVAL                      0x09090909
 #define DDR_PHY_DX3GCR6_DXDQVREFR3_SHIFT                       24
 #define DDR_PHY_DX3GCR6_DXDQVREFR3_MASK                        0x3F000000U
@@ -15080,9 +15080,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX3GCR6_RESERVED_23_22_DEFVAL 
-#undef DDR_PHY_DX3GCR6_RESERVED_23_22_SHIFT 
-#undef DDR_PHY_DX3GCR6_RESERVED_23_22_MASK 
+#undef DDR_PHY_DX3GCR6_RESERVED_23_22_DEFVAL
+#undef DDR_PHY_DX3GCR6_RESERVED_23_22_SHIFT
+#undef DDR_PHY_DX3GCR6_RESERVED_23_22_MASK
 #define DDR_PHY_DX3GCR6_RESERVED_23_22_DEFVAL                  0x09090909
 #define DDR_PHY_DX3GCR6_RESERVED_23_22_SHIFT                   22
 #define DDR_PHY_DX3GCR6_RESERVED_23_22_MASK                    0x00C00000U
@@ -15090,9 +15090,9 @@
 /*
 * DRAM DQ VREF Select for Rank2
 */
-#undef DDR_PHY_DX3GCR6_DXDQVREFR2_DEFVAL 
-#undef DDR_PHY_DX3GCR6_DXDQVREFR2_SHIFT 
-#undef DDR_PHY_DX3GCR6_DXDQVREFR2_MASK 
+#undef DDR_PHY_DX3GCR6_DXDQVREFR2_DEFVAL
+#undef DDR_PHY_DX3GCR6_DXDQVREFR2_SHIFT
+#undef DDR_PHY_DX3GCR6_DXDQVREFR2_MASK
 #define DDR_PHY_DX3GCR6_DXDQVREFR2_DEFVAL                      0x09090909
 #define DDR_PHY_DX3GCR6_DXDQVREFR2_SHIFT                       16
 #define DDR_PHY_DX3GCR6_DXDQVREFR2_MASK                        0x003F0000U
@@ -15100,9 +15100,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX3GCR6_RESERVED_15_14_DEFVAL 
-#undef DDR_PHY_DX3GCR6_RESERVED_15_14_SHIFT 
-#undef DDR_PHY_DX3GCR6_RESERVED_15_14_MASK 
+#undef DDR_PHY_DX3GCR6_RESERVED_15_14_DEFVAL
+#undef DDR_PHY_DX3GCR6_RESERVED_15_14_SHIFT
+#undef DDR_PHY_DX3GCR6_RESERVED_15_14_MASK
 #define DDR_PHY_DX3GCR6_RESERVED_15_14_DEFVAL                  0x09090909
 #define DDR_PHY_DX3GCR6_RESERVED_15_14_SHIFT                   14
 #define DDR_PHY_DX3GCR6_RESERVED_15_14_MASK                    0x0000C000U
@@ -15110,9 +15110,9 @@
 /*
 * DRAM DQ VREF Select for Rank1
 */
-#undef DDR_PHY_DX3GCR6_DXDQVREFR1_DEFVAL 
-#undef DDR_PHY_DX3GCR6_DXDQVREFR1_SHIFT 
-#undef DDR_PHY_DX3GCR6_DXDQVREFR1_MASK 
+#undef DDR_PHY_DX3GCR6_DXDQVREFR1_DEFVAL
+#undef DDR_PHY_DX3GCR6_DXDQVREFR1_SHIFT
+#undef DDR_PHY_DX3GCR6_DXDQVREFR1_MASK
 #define DDR_PHY_DX3GCR6_DXDQVREFR1_DEFVAL                      0x09090909
 #define DDR_PHY_DX3GCR6_DXDQVREFR1_SHIFT                       8
 #define DDR_PHY_DX3GCR6_DXDQVREFR1_MASK                        0x00003F00U
@@ -15120,9 +15120,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX3GCR6_RESERVED_7_6_DEFVAL 
-#undef DDR_PHY_DX3GCR6_RESERVED_7_6_SHIFT 
-#undef DDR_PHY_DX3GCR6_RESERVED_7_6_MASK 
+#undef DDR_PHY_DX3GCR6_RESERVED_7_6_DEFVAL
+#undef DDR_PHY_DX3GCR6_RESERVED_7_6_SHIFT
+#undef DDR_PHY_DX3GCR6_RESERVED_7_6_MASK
 #define DDR_PHY_DX3GCR6_RESERVED_7_6_DEFVAL                    0x09090909
 #define DDR_PHY_DX3GCR6_RESERVED_7_6_SHIFT                     6
 #define DDR_PHY_DX3GCR6_RESERVED_7_6_MASK                      0x000000C0U
@@ -15130,9 +15130,9 @@
 /*
 * DRAM DQ VREF Select for Rank0
 */
-#undef DDR_PHY_DX3GCR6_DXDQVREFR0_DEFVAL 
-#undef DDR_PHY_DX3GCR6_DXDQVREFR0_SHIFT 
-#undef DDR_PHY_DX3GCR6_DXDQVREFR0_MASK 
+#undef DDR_PHY_DX3GCR6_DXDQVREFR0_DEFVAL
+#undef DDR_PHY_DX3GCR6_DXDQVREFR0_SHIFT
+#undef DDR_PHY_DX3GCR6_DXDQVREFR0_MASK
 #define DDR_PHY_DX3GCR6_DXDQVREFR0_DEFVAL                      0x09090909
 #define DDR_PHY_DX3GCR6_DXDQVREFR0_SHIFT                       0
 #define DDR_PHY_DX3GCR6_DXDQVREFR0_MASK                        0x0000003FU
@@ -15140,9 +15140,9 @@
 /*
 * Calibration Bypass
 */
-#undef DDR_PHY_DX4GCR0_CALBYP_DEFVAL 
-#undef DDR_PHY_DX4GCR0_CALBYP_SHIFT 
-#undef DDR_PHY_DX4GCR0_CALBYP_MASK 
+#undef DDR_PHY_DX4GCR0_CALBYP_DEFVAL
+#undef DDR_PHY_DX4GCR0_CALBYP_SHIFT
+#undef DDR_PHY_DX4GCR0_CALBYP_MASK
 #define DDR_PHY_DX4GCR0_CALBYP_DEFVAL                          0x40200204
 #define DDR_PHY_DX4GCR0_CALBYP_SHIFT                           31
 #define DDR_PHY_DX4GCR0_CALBYP_MASK                            0x80000000U
@@ -15150,9 +15150,9 @@
 /*
 * Master Delay Line Enable
 */
-#undef DDR_PHY_DX4GCR0_MDLEN_DEFVAL 
-#undef DDR_PHY_DX4GCR0_MDLEN_SHIFT 
-#undef DDR_PHY_DX4GCR0_MDLEN_MASK 
+#undef DDR_PHY_DX4GCR0_MDLEN_DEFVAL
+#undef DDR_PHY_DX4GCR0_MDLEN_SHIFT
+#undef DDR_PHY_DX4GCR0_MDLEN_MASK
 #define DDR_PHY_DX4GCR0_MDLEN_DEFVAL                           0x40200204
 #define DDR_PHY_DX4GCR0_MDLEN_SHIFT                            30
 #define DDR_PHY_DX4GCR0_MDLEN_MASK                             0x40000000U
@@ -15160,9 +15160,9 @@
 /*
 * Configurable ODT(TE) Phase Shift
 */
-#undef DDR_PHY_DX4GCR0_CODTSHFT_DEFVAL 
-#undef DDR_PHY_DX4GCR0_CODTSHFT_SHIFT 
-#undef DDR_PHY_DX4GCR0_CODTSHFT_MASK 
+#undef DDR_PHY_DX4GCR0_CODTSHFT_DEFVAL
+#undef DDR_PHY_DX4GCR0_CODTSHFT_SHIFT
+#undef DDR_PHY_DX4GCR0_CODTSHFT_MASK
 #define DDR_PHY_DX4GCR0_CODTSHFT_DEFVAL                        0x40200204
 #define DDR_PHY_DX4GCR0_CODTSHFT_SHIFT                         28
 #define DDR_PHY_DX4GCR0_CODTSHFT_MASK                          0x30000000U
@@ -15170,9 +15170,9 @@
 /*
 * DQS Duty Cycle Correction
 */
-#undef DDR_PHY_DX4GCR0_DQSDCC_DEFVAL 
-#undef DDR_PHY_DX4GCR0_DQSDCC_SHIFT 
-#undef DDR_PHY_DX4GCR0_DQSDCC_MASK 
+#undef DDR_PHY_DX4GCR0_DQSDCC_DEFVAL
+#undef DDR_PHY_DX4GCR0_DQSDCC_SHIFT
+#undef DDR_PHY_DX4GCR0_DQSDCC_MASK
 #define DDR_PHY_DX4GCR0_DQSDCC_DEFVAL                          0x40200204
 #define DDR_PHY_DX4GCR0_DQSDCC_SHIFT                           24
 #define DDR_PHY_DX4GCR0_DQSDCC_MASK                            0x0F000000U
@@ -15181,9 +15181,9 @@
 * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
     *  input for the respective bypte lane of the PHY
 */
-#undef DDR_PHY_DX4GCR0_RDDLY_DEFVAL 
-#undef DDR_PHY_DX4GCR0_RDDLY_SHIFT 
-#undef DDR_PHY_DX4GCR0_RDDLY_MASK 
+#undef DDR_PHY_DX4GCR0_RDDLY_DEFVAL
+#undef DDR_PHY_DX4GCR0_RDDLY_SHIFT
+#undef DDR_PHY_DX4GCR0_RDDLY_MASK
 #define DDR_PHY_DX4GCR0_RDDLY_DEFVAL                           0x40200204
 #define DDR_PHY_DX4GCR0_RDDLY_SHIFT                            20
 #define DDR_PHY_DX4GCR0_RDDLY_MASK                             0x00F00000U
@@ -15191,9 +15191,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX4GCR0_RESERVED_19_14_DEFVAL 
-#undef DDR_PHY_DX4GCR0_RESERVED_19_14_SHIFT 
-#undef DDR_PHY_DX4GCR0_RESERVED_19_14_MASK 
+#undef DDR_PHY_DX4GCR0_RESERVED_19_14_DEFVAL
+#undef DDR_PHY_DX4GCR0_RESERVED_19_14_SHIFT
+#undef DDR_PHY_DX4GCR0_RESERVED_19_14_MASK
 #define DDR_PHY_DX4GCR0_RESERVED_19_14_DEFVAL                  0x40200204
 #define DDR_PHY_DX4GCR0_RESERVED_19_14_SHIFT                   14
 #define DDR_PHY_DX4GCR0_RESERVED_19_14_MASK                    0x000FC000U
@@ -15201,9 +15201,9 @@
 /*
 * DQSNSE Power Down Receiver
 */
-#undef DDR_PHY_DX4GCR0_DQSNSEPDR_DEFVAL 
-#undef DDR_PHY_DX4GCR0_DQSNSEPDR_SHIFT 
-#undef DDR_PHY_DX4GCR0_DQSNSEPDR_MASK 
+#undef DDR_PHY_DX4GCR0_DQSNSEPDR_DEFVAL
+#undef DDR_PHY_DX4GCR0_DQSNSEPDR_SHIFT
+#undef DDR_PHY_DX4GCR0_DQSNSEPDR_MASK
 #define DDR_PHY_DX4GCR0_DQSNSEPDR_DEFVAL                       0x40200204
 #define DDR_PHY_DX4GCR0_DQSNSEPDR_SHIFT                        13
 #define DDR_PHY_DX4GCR0_DQSNSEPDR_MASK                         0x00002000U
@@ -15211,9 +15211,9 @@
 /*
 * DQSSE Power Down Receiver
 */
-#undef DDR_PHY_DX4GCR0_DQSSEPDR_DEFVAL 
-#undef DDR_PHY_DX4GCR0_DQSSEPDR_SHIFT 
-#undef DDR_PHY_DX4GCR0_DQSSEPDR_MASK 
+#undef DDR_PHY_DX4GCR0_DQSSEPDR_DEFVAL
+#undef DDR_PHY_DX4GCR0_DQSSEPDR_SHIFT
+#undef DDR_PHY_DX4GCR0_DQSSEPDR_MASK
 #define DDR_PHY_DX4GCR0_DQSSEPDR_DEFVAL                        0x40200204
 #define DDR_PHY_DX4GCR0_DQSSEPDR_SHIFT                         12
 #define DDR_PHY_DX4GCR0_DQSSEPDR_MASK                          0x00001000U
@@ -15221,9 +15221,9 @@
 /*
 * RTT On Additive Latency
 */
-#undef DDR_PHY_DX4GCR0_RTTOAL_DEFVAL 
-#undef DDR_PHY_DX4GCR0_RTTOAL_SHIFT 
-#undef DDR_PHY_DX4GCR0_RTTOAL_MASK 
+#undef DDR_PHY_DX4GCR0_RTTOAL_DEFVAL
+#undef DDR_PHY_DX4GCR0_RTTOAL_SHIFT
+#undef DDR_PHY_DX4GCR0_RTTOAL_MASK
 #define DDR_PHY_DX4GCR0_RTTOAL_DEFVAL                          0x40200204
 #define DDR_PHY_DX4GCR0_RTTOAL_SHIFT                           11
 #define DDR_PHY_DX4GCR0_RTTOAL_MASK                            0x00000800U
@@ -15231,9 +15231,9 @@
 /*
 * RTT Output Hold
 */
-#undef DDR_PHY_DX4GCR0_RTTOH_DEFVAL 
-#undef DDR_PHY_DX4GCR0_RTTOH_SHIFT 
-#undef DDR_PHY_DX4GCR0_RTTOH_MASK 
+#undef DDR_PHY_DX4GCR0_RTTOH_DEFVAL
+#undef DDR_PHY_DX4GCR0_RTTOH_SHIFT
+#undef DDR_PHY_DX4GCR0_RTTOH_MASK
 #define DDR_PHY_DX4GCR0_RTTOH_DEFVAL                           0x40200204
 #define DDR_PHY_DX4GCR0_RTTOH_SHIFT                            9
 #define DDR_PHY_DX4GCR0_RTTOH_MASK                             0x00000600U
@@ -15241,9 +15241,9 @@
 /*
 * Configurable PDR Phase Shift
 */
-#undef DDR_PHY_DX4GCR0_CPDRSHFT_DEFVAL 
-#undef DDR_PHY_DX4GCR0_CPDRSHFT_SHIFT 
-#undef DDR_PHY_DX4GCR0_CPDRSHFT_MASK 
+#undef DDR_PHY_DX4GCR0_CPDRSHFT_DEFVAL
+#undef DDR_PHY_DX4GCR0_CPDRSHFT_SHIFT
+#undef DDR_PHY_DX4GCR0_CPDRSHFT_MASK
 #define DDR_PHY_DX4GCR0_CPDRSHFT_DEFVAL                        0x40200204
 #define DDR_PHY_DX4GCR0_CPDRSHFT_SHIFT                         7
 #define DDR_PHY_DX4GCR0_CPDRSHFT_MASK                          0x00000180U
@@ -15251,9 +15251,9 @@
 /*
 * DQSR Power Down
 */
-#undef DDR_PHY_DX4GCR0_DQSRPD_DEFVAL 
-#undef DDR_PHY_DX4GCR0_DQSRPD_SHIFT 
-#undef DDR_PHY_DX4GCR0_DQSRPD_MASK 
+#undef DDR_PHY_DX4GCR0_DQSRPD_DEFVAL
+#undef DDR_PHY_DX4GCR0_DQSRPD_SHIFT
+#undef DDR_PHY_DX4GCR0_DQSRPD_MASK
 #define DDR_PHY_DX4GCR0_DQSRPD_DEFVAL                          0x40200204
 #define DDR_PHY_DX4GCR0_DQSRPD_SHIFT                           6
 #define DDR_PHY_DX4GCR0_DQSRPD_MASK                            0x00000040U
@@ -15261,9 +15261,9 @@
 /*
 * DQSG Power Down Receiver
 */
-#undef DDR_PHY_DX4GCR0_DQSGPDR_DEFVAL 
-#undef DDR_PHY_DX4GCR0_DQSGPDR_SHIFT 
-#undef DDR_PHY_DX4GCR0_DQSGPDR_MASK 
+#undef DDR_PHY_DX4GCR0_DQSGPDR_DEFVAL
+#undef DDR_PHY_DX4GCR0_DQSGPDR_SHIFT
+#undef DDR_PHY_DX4GCR0_DQSGPDR_MASK
 #define DDR_PHY_DX4GCR0_DQSGPDR_DEFVAL                         0x40200204
 #define DDR_PHY_DX4GCR0_DQSGPDR_SHIFT                          5
 #define DDR_PHY_DX4GCR0_DQSGPDR_MASK                           0x00000020U
@@ -15271,9 +15271,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX4GCR0_RESERVED_4_DEFVAL 
-#undef DDR_PHY_DX4GCR0_RESERVED_4_SHIFT 
-#undef DDR_PHY_DX4GCR0_RESERVED_4_MASK 
+#undef DDR_PHY_DX4GCR0_RESERVED_4_DEFVAL
+#undef DDR_PHY_DX4GCR0_RESERVED_4_SHIFT
+#undef DDR_PHY_DX4GCR0_RESERVED_4_MASK
 #define DDR_PHY_DX4GCR0_RESERVED_4_DEFVAL                      0x40200204
 #define DDR_PHY_DX4GCR0_RESERVED_4_SHIFT                       4
 #define DDR_PHY_DX4GCR0_RESERVED_4_MASK                        0x00000010U
@@ -15281,9 +15281,9 @@
 /*
 * DQSG On-Die Termination
 */
-#undef DDR_PHY_DX4GCR0_DQSGODT_DEFVAL 
-#undef DDR_PHY_DX4GCR0_DQSGODT_SHIFT 
-#undef DDR_PHY_DX4GCR0_DQSGODT_MASK 
+#undef DDR_PHY_DX4GCR0_DQSGODT_DEFVAL
+#undef DDR_PHY_DX4GCR0_DQSGODT_SHIFT
+#undef DDR_PHY_DX4GCR0_DQSGODT_MASK
 #define DDR_PHY_DX4GCR0_DQSGODT_DEFVAL                         0x40200204
 #define DDR_PHY_DX4GCR0_DQSGODT_SHIFT                          3
 #define DDR_PHY_DX4GCR0_DQSGODT_MASK                           0x00000008U
@@ -15291,9 +15291,9 @@
 /*
 * DQSG Output Enable
 */
-#undef DDR_PHY_DX4GCR0_DQSGOE_DEFVAL 
-#undef DDR_PHY_DX4GCR0_DQSGOE_SHIFT 
-#undef DDR_PHY_DX4GCR0_DQSGOE_MASK 
+#undef DDR_PHY_DX4GCR0_DQSGOE_DEFVAL
+#undef DDR_PHY_DX4GCR0_DQSGOE_SHIFT
+#undef DDR_PHY_DX4GCR0_DQSGOE_MASK
 #define DDR_PHY_DX4GCR0_DQSGOE_DEFVAL                          0x40200204
 #define DDR_PHY_DX4GCR0_DQSGOE_SHIFT                           2
 #define DDR_PHY_DX4GCR0_DQSGOE_MASK                            0x00000004U
@@ -15301,9 +15301,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX4GCR0_RESERVED_1_0_DEFVAL 
-#undef DDR_PHY_DX4GCR0_RESERVED_1_0_SHIFT 
-#undef DDR_PHY_DX4GCR0_RESERVED_1_0_MASK 
+#undef DDR_PHY_DX4GCR0_RESERVED_1_0_DEFVAL
+#undef DDR_PHY_DX4GCR0_RESERVED_1_0_SHIFT
+#undef DDR_PHY_DX4GCR0_RESERVED_1_0_MASK
 #define DDR_PHY_DX4GCR0_RESERVED_1_0_DEFVAL                    0x40200204
 #define DDR_PHY_DX4GCR0_RESERVED_1_0_SHIFT                     0
 #define DDR_PHY_DX4GCR0_RESERVED_1_0_MASK                      0x00000003U
@@ -15311,9 +15311,9 @@
 /*
 * Enables the PDR mode for DQ[7:0]
 */
-#undef DDR_PHY_DX4GCR1_DXPDRMODE_DEFVAL 
-#undef DDR_PHY_DX4GCR1_DXPDRMODE_SHIFT 
-#undef DDR_PHY_DX4GCR1_DXPDRMODE_MASK 
+#undef DDR_PHY_DX4GCR1_DXPDRMODE_DEFVAL
+#undef DDR_PHY_DX4GCR1_DXPDRMODE_SHIFT
+#undef DDR_PHY_DX4GCR1_DXPDRMODE_MASK
 #define DDR_PHY_DX4GCR1_DXPDRMODE_DEFVAL                       0x00007FFF
 #define DDR_PHY_DX4GCR1_DXPDRMODE_SHIFT                        16
 #define DDR_PHY_DX4GCR1_DXPDRMODE_MASK                         0xFFFF0000U
@@ -15321,9 +15321,9 @@
 /*
 * Reserved. Returns zeroes on reads.
 */
-#undef DDR_PHY_DX4GCR1_RESERVED_15_DEFVAL 
-#undef DDR_PHY_DX4GCR1_RESERVED_15_SHIFT 
-#undef DDR_PHY_DX4GCR1_RESERVED_15_MASK 
+#undef DDR_PHY_DX4GCR1_RESERVED_15_DEFVAL
+#undef DDR_PHY_DX4GCR1_RESERVED_15_SHIFT
+#undef DDR_PHY_DX4GCR1_RESERVED_15_MASK
 #define DDR_PHY_DX4GCR1_RESERVED_15_DEFVAL                     0x00007FFF
 #define DDR_PHY_DX4GCR1_RESERVED_15_SHIFT                      15
 #define DDR_PHY_DX4GCR1_RESERVED_15_MASK                       0x00008000U
@@ -15331,9 +15331,9 @@
 /*
 * Select the delayed or non-delayed read data strobe #
 */
-#undef DDR_PHY_DX4GCR1_QSNSEL_DEFVAL 
-#undef DDR_PHY_DX4GCR1_QSNSEL_SHIFT 
-#undef DDR_PHY_DX4GCR1_QSNSEL_MASK 
+#undef DDR_PHY_DX4GCR1_QSNSEL_DEFVAL
+#undef DDR_PHY_DX4GCR1_QSNSEL_SHIFT
+#undef DDR_PHY_DX4GCR1_QSNSEL_MASK
 #define DDR_PHY_DX4GCR1_QSNSEL_DEFVAL                          0x00007FFF
 #define DDR_PHY_DX4GCR1_QSNSEL_SHIFT                           14
 #define DDR_PHY_DX4GCR1_QSNSEL_MASK                            0x00004000U
@@ -15341,9 +15341,9 @@
 /*
 * Select the delayed or non-delayed read data strobe
 */
-#undef DDR_PHY_DX4GCR1_QSSEL_DEFVAL 
-#undef DDR_PHY_DX4GCR1_QSSEL_SHIFT 
-#undef DDR_PHY_DX4GCR1_QSSEL_MASK 
+#undef DDR_PHY_DX4GCR1_QSSEL_DEFVAL
+#undef DDR_PHY_DX4GCR1_QSSEL_SHIFT
+#undef DDR_PHY_DX4GCR1_QSSEL_MASK
 #define DDR_PHY_DX4GCR1_QSSEL_DEFVAL                           0x00007FFF
 #define DDR_PHY_DX4GCR1_QSSEL_SHIFT                            13
 #define DDR_PHY_DX4GCR1_QSSEL_MASK                             0x00002000U
@@ -15351,9 +15351,9 @@
 /*
 * Enables Read Data Strobe in a byte lane
 */
-#undef DDR_PHY_DX4GCR1_OEEN_DEFVAL 
-#undef DDR_PHY_DX4GCR1_OEEN_SHIFT 
-#undef DDR_PHY_DX4GCR1_OEEN_MASK 
+#undef DDR_PHY_DX4GCR1_OEEN_DEFVAL
+#undef DDR_PHY_DX4GCR1_OEEN_SHIFT
+#undef DDR_PHY_DX4GCR1_OEEN_MASK
 #define DDR_PHY_DX4GCR1_OEEN_DEFVAL                            0x00007FFF
 #define DDR_PHY_DX4GCR1_OEEN_SHIFT                             12
 #define DDR_PHY_DX4GCR1_OEEN_MASK                              0x00001000U
@@ -15361,9 +15361,9 @@
 /*
 * Enables PDR in a byte lane
 */
-#undef DDR_PHY_DX4GCR1_PDREN_DEFVAL 
-#undef DDR_PHY_DX4GCR1_PDREN_SHIFT 
-#undef DDR_PHY_DX4GCR1_PDREN_MASK 
+#undef DDR_PHY_DX4GCR1_PDREN_DEFVAL
+#undef DDR_PHY_DX4GCR1_PDREN_SHIFT
+#undef DDR_PHY_DX4GCR1_PDREN_MASK
 #define DDR_PHY_DX4GCR1_PDREN_DEFVAL                           0x00007FFF
 #define DDR_PHY_DX4GCR1_PDREN_SHIFT                            11
 #define DDR_PHY_DX4GCR1_PDREN_MASK                             0x00000800U
@@ -15371,9 +15371,9 @@
 /*
 * Enables ODT/TE in a byte lane
 */
-#undef DDR_PHY_DX4GCR1_TEEN_DEFVAL 
-#undef DDR_PHY_DX4GCR1_TEEN_SHIFT 
-#undef DDR_PHY_DX4GCR1_TEEN_MASK 
+#undef DDR_PHY_DX4GCR1_TEEN_DEFVAL
+#undef DDR_PHY_DX4GCR1_TEEN_SHIFT
+#undef DDR_PHY_DX4GCR1_TEEN_MASK
 #define DDR_PHY_DX4GCR1_TEEN_DEFVAL                            0x00007FFF
 #define DDR_PHY_DX4GCR1_TEEN_SHIFT                             10
 #define DDR_PHY_DX4GCR1_TEEN_MASK                              0x00000400U
@@ -15381,9 +15381,9 @@
 /*
 * Enables Write Data strobe in a byte lane
 */
-#undef DDR_PHY_DX4GCR1_DSEN_DEFVAL 
-#undef DDR_PHY_DX4GCR1_DSEN_SHIFT 
-#undef DDR_PHY_DX4GCR1_DSEN_MASK 
+#undef DDR_PHY_DX4GCR1_DSEN_DEFVAL
+#undef DDR_PHY_DX4GCR1_DSEN_SHIFT
+#undef DDR_PHY_DX4GCR1_DSEN_MASK
 #define DDR_PHY_DX4GCR1_DSEN_DEFVAL                            0x00007FFF
 #define DDR_PHY_DX4GCR1_DSEN_SHIFT                             9
 #define DDR_PHY_DX4GCR1_DSEN_MASK                              0x00000200U
@@ -15391,9 +15391,9 @@
 /*
 * Enables DM pin in a byte lane
 */
-#undef DDR_PHY_DX4GCR1_DMEN_DEFVAL 
-#undef DDR_PHY_DX4GCR1_DMEN_SHIFT 
-#undef DDR_PHY_DX4GCR1_DMEN_MASK 
+#undef DDR_PHY_DX4GCR1_DMEN_DEFVAL
+#undef DDR_PHY_DX4GCR1_DMEN_SHIFT
+#undef DDR_PHY_DX4GCR1_DMEN_MASK
 #define DDR_PHY_DX4GCR1_DMEN_DEFVAL                            0x00007FFF
 #define DDR_PHY_DX4GCR1_DMEN_SHIFT                             8
 #define DDR_PHY_DX4GCR1_DMEN_MASK                              0x00000100U
@@ -15401,9 +15401,9 @@
 /*
 * Enables DQ corresponding to each bit in a byte
 */
-#undef DDR_PHY_DX4GCR1_DQEN_DEFVAL 
-#undef DDR_PHY_DX4GCR1_DQEN_SHIFT 
-#undef DDR_PHY_DX4GCR1_DQEN_MASK 
+#undef DDR_PHY_DX4GCR1_DQEN_DEFVAL
+#undef DDR_PHY_DX4GCR1_DQEN_SHIFT
+#undef DDR_PHY_DX4GCR1_DQEN_MASK
 #define DDR_PHY_DX4GCR1_DQEN_DEFVAL                            0x00007FFF
 #define DDR_PHY_DX4GCR1_DQEN_SHIFT                             0
 #define DDR_PHY_DX4GCR1_DQEN_MASK                              0x000000FFU
@@ -15411,9 +15411,9 @@
 /*
 * Byte lane VREF IOM (Used only by D4MU IOs)
 */
-#undef DDR_PHY_DX4GCR4_RESERVED_31_29_DEFVAL 
-#undef DDR_PHY_DX4GCR4_RESERVED_31_29_SHIFT 
-#undef DDR_PHY_DX4GCR4_RESERVED_31_29_MASK 
+#undef DDR_PHY_DX4GCR4_RESERVED_31_29_DEFVAL
+#undef DDR_PHY_DX4GCR4_RESERVED_31_29_SHIFT
+#undef DDR_PHY_DX4GCR4_RESERVED_31_29_MASK
 #define DDR_PHY_DX4GCR4_RESERVED_31_29_DEFVAL                  0x0E00003C
 #define DDR_PHY_DX4GCR4_RESERVED_31_29_SHIFT                   29
 #define DDR_PHY_DX4GCR4_RESERVED_31_29_MASK                    0xE0000000U
@@ -15421,9 +15421,9 @@
 /*
 * Byte Lane VREF Pad Enable
 */
-#undef DDR_PHY_DX4GCR4_DXREFPEN_DEFVAL 
-#undef DDR_PHY_DX4GCR4_DXREFPEN_SHIFT 
-#undef DDR_PHY_DX4GCR4_DXREFPEN_MASK 
+#undef DDR_PHY_DX4GCR4_DXREFPEN_DEFVAL
+#undef DDR_PHY_DX4GCR4_DXREFPEN_SHIFT
+#undef DDR_PHY_DX4GCR4_DXREFPEN_MASK
 #define DDR_PHY_DX4GCR4_DXREFPEN_DEFVAL                        0x0E00003C
 #define DDR_PHY_DX4GCR4_DXREFPEN_SHIFT                         28
 #define DDR_PHY_DX4GCR4_DXREFPEN_MASK                          0x10000000U
@@ -15431,9 +15431,9 @@
 /*
 * Byte Lane Internal VREF Enable
 */
-#undef DDR_PHY_DX4GCR4_DXREFEEN_DEFVAL 
-#undef DDR_PHY_DX4GCR4_DXREFEEN_SHIFT 
-#undef DDR_PHY_DX4GCR4_DXREFEEN_MASK 
+#undef DDR_PHY_DX4GCR4_DXREFEEN_DEFVAL
+#undef DDR_PHY_DX4GCR4_DXREFEEN_SHIFT
+#undef DDR_PHY_DX4GCR4_DXREFEEN_MASK
 #define DDR_PHY_DX4GCR4_DXREFEEN_DEFVAL                        0x0E00003C
 #define DDR_PHY_DX4GCR4_DXREFEEN_SHIFT                         26
 #define DDR_PHY_DX4GCR4_DXREFEEN_MASK                          0x0C000000U
@@ -15441,9 +15441,9 @@
 /*
 * Byte Lane Single-End VREF Enable
 */
-#undef DDR_PHY_DX4GCR4_DXREFSEN_DEFVAL 
-#undef DDR_PHY_DX4GCR4_DXREFSEN_SHIFT 
-#undef DDR_PHY_DX4GCR4_DXREFSEN_MASK 
+#undef DDR_PHY_DX4GCR4_DXREFSEN_DEFVAL
+#undef DDR_PHY_DX4GCR4_DXREFSEN_SHIFT
+#undef DDR_PHY_DX4GCR4_DXREFSEN_MASK
 #define DDR_PHY_DX4GCR4_DXREFSEN_DEFVAL                        0x0E00003C
 #define DDR_PHY_DX4GCR4_DXREFSEN_SHIFT                         25
 #define DDR_PHY_DX4GCR4_DXREFSEN_MASK                          0x02000000U
@@ -15451,9 +15451,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX4GCR4_RESERVED_24_DEFVAL 
-#undef DDR_PHY_DX4GCR4_RESERVED_24_SHIFT 
-#undef DDR_PHY_DX4GCR4_RESERVED_24_MASK 
+#undef DDR_PHY_DX4GCR4_RESERVED_24_DEFVAL
+#undef DDR_PHY_DX4GCR4_RESERVED_24_SHIFT
+#undef DDR_PHY_DX4GCR4_RESERVED_24_MASK
 #define DDR_PHY_DX4GCR4_RESERVED_24_DEFVAL                     0x0E00003C
 #define DDR_PHY_DX4GCR4_RESERVED_24_SHIFT                      24
 #define DDR_PHY_DX4GCR4_RESERVED_24_MASK                       0x01000000U
@@ -15461,9 +15461,9 @@
 /*
 * External VREF generator REFSEL range select
 */
-#undef DDR_PHY_DX4GCR4_DXREFESELRANGE_DEFVAL 
-#undef DDR_PHY_DX4GCR4_DXREFESELRANGE_SHIFT 
-#undef DDR_PHY_DX4GCR4_DXREFESELRANGE_MASK 
+#undef DDR_PHY_DX4GCR4_DXREFESELRANGE_DEFVAL
+#undef DDR_PHY_DX4GCR4_DXREFESELRANGE_SHIFT
+#undef DDR_PHY_DX4GCR4_DXREFESELRANGE_MASK
 #define DDR_PHY_DX4GCR4_DXREFESELRANGE_DEFVAL                  0x0E00003C
 #define DDR_PHY_DX4GCR4_DXREFESELRANGE_SHIFT                   23
 #define DDR_PHY_DX4GCR4_DXREFESELRANGE_MASK                    0x00800000U
@@ -15471,9 +15471,9 @@
 /*
 * Byte Lane External VREF Select
 */
-#undef DDR_PHY_DX4GCR4_DXREFESEL_DEFVAL 
-#undef DDR_PHY_DX4GCR4_DXREFESEL_SHIFT 
-#undef DDR_PHY_DX4GCR4_DXREFESEL_MASK 
+#undef DDR_PHY_DX4GCR4_DXREFESEL_DEFVAL
+#undef DDR_PHY_DX4GCR4_DXREFESEL_SHIFT
+#undef DDR_PHY_DX4GCR4_DXREFESEL_MASK
 #define DDR_PHY_DX4GCR4_DXREFESEL_DEFVAL                       0x0E00003C
 #define DDR_PHY_DX4GCR4_DXREFESEL_SHIFT                        16
 #define DDR_PHY_DX4GCR4_DXREFESEL_MASK                         0x007F0000U
@@ -15481,9 +15481,9 @@
 /*
 * Single ended VREF generator REFSEL range select
 */
-#undef DDR_PHY_DX4GCR4_DXREFSSELRANGE_DEFVAL 
-#undef DDR_PHY_DX4GCR4_DXREFSSELRANGE_SHIFT 
-#undef DDR_PHY_DX4GCR4_DXREFSSELRANGE_MASK 
+#undef DDR_PHY_DX4GCR4_DXREFSSELRANGE_DEFVAL
+#undef DDR_PHY_DX4GCR4_DXREFSSELRANGE_SHIFT
+#undef DDR_PHY_DX4GCR4_DXREFSSELRANGE_MASK
 #define DDR_PHY_DX4GCR4_DXREFSSELRANGE_DEFVAL                  0x0E00003C
 #define DDR_PHY_DX4GCR4_DXREFSSELRANGE_SHIFT                   15
 #define DDR_PHY_DX4GCR4_DXREFSSELRANGE_MASK                    0x00008000U
@@ -15491,9 +15491,9 @@
 /*
 * Byte Lane Single-End VREF Select
 */
-#undef DDR_PHY_DX4GCR4_DXREFSSEL_DEFVAL 
-#undef DDR_PHY_DX4GCR4_DXREFSSEL_SHIFT 
-#undef DDR_PHY_DX4GCR4_DXREFSSEL_MASK 
+#undef DDR_PHY_DX4GCR4_DXREFSSEL_DEFVAL
+#undef DDR_PHY_DX4GCR4_DXREFSSEL_SHIFT
+#undef DDR_PHY_DX4GCR4_DXREFSSEL_MASK
 #define DDR_PHY_DX4GCR4_DXREFSSEL_DEFVAL                       0x0E00003C
 #define DDR_PHY_DX4GCR4_DXREFSSEL_SHIFT                        8
 #define DDR_PHY_DX4GCR4_DXREFSSEL_MASK                         0x00007F00U
@@ -15501,9 +15501,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX4GCR4_RESERVED_7_6_DEFVAL 
-#undef DDR_PHY_DX4GCR4_RESERVED_7_6_SHIFT 
-#undef DDR_PHY_DX4GCR4_RESERVED_7_6_MASK 
+#undef DDR_PHY_DX4GCR4_RESERVED_7_6_DEFVAL
+#undef DDR_PHY_DX4GCR4_RESERVED_7_6_SHIFT
+#undef DDR_PHY_DX4GCR4_RESERVED_7_6_MASK
 #define DDR_PHY_DX4GCR4_RESERVED_7_6_DEFVAL                    0x0E00003C
 #define DDR_PHY_DX4GCR4_RESERVED_7_6_SHIFT                     6
 #define DDR_PHY_DX4GCR4_RESERVED_7_6_MASK                      0x000000C0U
@@ -15511,9 +15511,9 @@
 /*
 * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
 */
-#undef DDR_PHY_DX4GCR4_DXREFIEN_DEFVAL 
-#undef DDR_PHY_DX4GCR4_DXREFIEN_SHIFT 
-#undef DDR_PHY_DX4GCR4_DXREFIEN_MASK 
+#undef DDR_PHY_DX4GCR4_DXREFIEN_DEFVAL
+#undef DDR_PHY_DX4GCR4_DXREFIEN_SHIFT
+#undef DDR_PHY_DX4GCR4_DXREFIEN_MASK
 #define DDR_PHY_DX4GCR4_DXREFIEN_DEFVAL                        0x0E00003C
 #define DDR_PHY_DX4GCR4_DXREFIEN_SHIFT                         2
 #define DDR_PHY_DX4GCR4_DXREFIEN_MASK                          0x0000003CU
@@ -15521,9 +15521,9 @@
 /*
 * VRMON control for DQ IO (Single Ended) buffers of a byte lane.
 */
-#undef DDR_PHY_DX4GCR4_DXREFIMON_DEFVAL 
-#undef DDR_PHY_DX4GCR4_DXREFIMON_SHIFT 
-#undef DDR_PHY_DX4GCR4_DXREFIMON_MASK 
+#undef DDR_PHY_DX4GCR4_DXREFIMON_DEFVAL
+#undef DDR_PHY_DX4GCR4_DXREFIMON_SHIFT
+#undef DDR_PHY_DX4GCR4_DXREFIMON_MASK
 #define DDR_PHY_DX4GCR4_DXREFIMON_DEFVAL                       0x0E00003C
 #define DDR_PHY_DX4GCR4_DXREFIMON_SHIFT                        0
 #define DDR_PHY_DX4GCR4_DXREFIMON_MASK                         0x00000003U
@@ -15531,9 +15531,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX4GCR5_RESERVED_31_DEFVAL 
-#undef DDR_PHY_DX4GCR5_RESERVED_31_SHIFT 
-#undef DDR_PHY_DX4GCR5_RESERVED_31_MASK 
+#undef DDR_PHY_DX4GCR5_RESERVED_31_DEFVAL
+#undef DDR_PHY_DX4GCR5_RESERVED_31_SHIFT
+#undef DDR_PHY_DX4GCR5_RESERVED_31_MASK
 #define DDR_PHY_DX4GCR5_RESERVED_31_DEFVAL                     0x09090909
 #define DDR_PHY_DX4GCR5_RESERVED_31_SHIFT                      31
 #define DDR_PHY_DX4GCR5_RESERVED_31_MASK                       0x80000000U
@@ -15541,9 +15541,9 @@
 /*
 * Byte Lane internal VREF Select for Rank 3
 */
-#undef DDR_PHY_DX4GCR5_DXREFISELR3_DEFVAL 
-#undef DDR_PHY_DX4GCR5_DXREFISELR3_SHIFT 
-#undef DDR_PHY_DX4GCR5_DXREFISELR3_MASK 
+#undef DDR_PHY_DX4GCR5_DXREFISELR3_DEFVAL
+#undef DDR_PHY_DX4GCR5_DXREFISELR3_SHIFT
+#undef DDR_PHY_DX4GCR5_DXREFISELR3_MASK
 #define DDR_PHY_DX4GCR5_DXREFISELR3_DEFVAL                     0x09090909
 #define DDR_PHY_DX4GCR5_DXREFISELR3_SHIFT                      24
 #define DDR_PHY_DX4GCR5_DXREFISELR3_MASK                       0x7F000000U
@@ -15551,9 +15551,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX4GCR5_RESERVED_23_DEFVAL 
-#undef DDR_PHY_DX4GCR5_RESERVED_23_SHIFT 
-#undef DDR_PHY_DX4GCR5_RESERVED_23_MASK 
+#undef DDR_PHY_DX4GCR5_RESERVED_23_DEFVAL
+#undef DDR_PHY_DX4GCR5_RESERVED_23_SHIFT
+#undef DDR_PHY_DX4GCR5_RESERVED_23_MASK
 #define DDR_PHY_DX4GCR5_RESERVED_23_DEFVAL                     0x09090909
 #define DDR_PHY_DX4GCR5_RESERVED_23_SHIFT                      23
 #define DDR_PHY_DX4GCR5_RESERVED_23_MASK                       0x00800000U
@@ -15561,9 +15561,9 @@
 /*
 * Byte Lane internal VREF Select for Rank 2
 */
-#undef DDR_PHY_DX4GCR5_DXREFISELR2_DEFVAL 
-#undef DDR_PHY_DX4GCR5_DXREFISELR2_SHIFT 
-#undef DDR_PHY_DX4GCR5_DXREFISELR2_MASK 
+#undef DDR_PHY_DX4GCR5_DXREFISELR2_DEFVAL
+#undef DDR_PHY_DX4GCR5_DXREFISELR2_SHIFT
+#undef DDR_PHY_DX4GCR5_DXREFISELR2_MASK
 #define DDR_PHY_DX4GCR5_DXREFISELR2_DEFVAL                     0x09090909
 #define DDR_PHY_DX4GCR5_DXREFISELR2_SHIFT                      16
 #define DDR_PHY_DX4GCR5_DXREFISELR2_MASK                       0x007F0000U
@@ -15571,9 +15571,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX4GCR5_RESERVED_15_DEFVAL 
-#undef DDR_PHY_DX4GCR5_RESERVED_15_SHIFT 
-#undef DDR_PHY_DX4GCR5_RESERVED_15_MASK 
+#undef DDR_PHY_DX4GCR5_RESERVED_15_DEFVAL
+#undef DDR_PHY_DX4GCR5_RESERVED_15_SHIFT
+#undef DDR_PHY_DX4GCR5_RESERVED_15_MASK
 #define DDR_PHY_DX4GCR5_RESERVED_15_DEFVAL                     0x09090909
 #define DDR_PHY_DX4GCR5_RESERVED_15_SHIFT                      15
 #define DDR_PHY_DX4GCR5_RESERVED_15_MASK                       0x00008000U
@@ -15581,9 +15581,9 @@
 /*
 * Byte Lane internal VREF Select for Rank 1
 */
-#undef DDR_PHY_DX4GCR5_DXREFISELR1_DEFVAL 
-#undef DDR_PHY_DX4GCR5_DXREFISELR1_SHIFT 
-#undef DDR_PHY_DX4GCR5_DXREFISELR1_MASK 
+#undef DDR_PHY_DX4GCR5_DXREFISELR1_DEFVAL
+#undef DDR_PHY_DX4GCR5_DXREFISELR1_SHIFT
+#undef DDR_PHY_DX4GCR5_DXREFISELR1_MASK
 #define DDR_PHY_DX4GCR5_DXREFISELR1_DEFVAL                     0x09090909
 #define DDR_PHY_DX4GCR5_DXREFISELR1_SHIFT                      8
 #define DDR_PHY_DX4GCR5_DXREFISELR1_MASK                       0x00007F00U
@@ -15591,9 +15591,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX4GCR5_RESERVED_7_DEFVAL 
-#undef DDR_PHY_DX4GCR5_RESERVED_7_SHIFT 
-#undef DDR_PHY_DX4GCR5_RESERVED_7_MASK 
+#undef DDR_PHY_DX4GCR5_RESERVED_7_DEFVAL
+#undef DDR_PHY_DX4GCR5_RESERVED_7_SHIFT
+#undef DDR_PHY_DX4GCR5_RESERVED_7_MASK
 #define DDR_PHY_DX4GCR5_RESERVED_7_DEFVAL                      0x09090909
 #define DDR_PHY_DX4GCR5_RESERVED_7_SHIFT                       7
 #define DDR_PHY_DX4GCR5_RESERVED_7_MASK                        0x00000080U
@@ -15601,9 +15601,9 @@
 /*
 * Byte Lane internal VREF Select for Rank 0
 */
-#undef DDR_PHY_DX4GCR5_DXREFISELR0_DEFVAL 
-#undef DDR_PHY_DX4GCR5_DXREFISELR0_SHIFT 
-#undef DDR_PHY_DX4GCR5_DXREFISELR0_MASK 
+#undef DDR_PHY_DX4GCR5_DXREFISELR0_DEFVAL
+#undef DDR_PHY_DX4GCR5_DXREFISELR0_SHIFT
+#undef DDR_PHY_DX4GCR5_DXREFISELR0_MASK
 #define DDR_PHY_DX4GCR5_DXREFISELR0_DEFVAL                     0x09090909
 #define DDR_PHY_DX4GCR5_DXREFISELR0_SHIFT                      0
 #define DDR_PHY_DX4GCR5_DXREFISELR0_MASK                       0x0000007FU
@@ -15611,9 +15611,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX4GCR6_RESERVED_31_30_DEFVAL 
-#undef DDR_PHY_DX4GCR6_RESERVED_31_30_SHIFT 
-#undef DDR_PHY_DX4GCR6_RESERVED_31_30_MASK 
+#undef DDR_PHY_DX4GCR6_RESERVED_31_30_DEFVAL
+#undef DDR_PHY_DX4GCR6_RESERVED_31_30_SHIFT
+#undef DDR_PHY_DX4GCR6_RESERVED_31_30_MASK
 #define DDR_PHY_DX4GCR6_RESERVED_31_30_DEFVAL                  0x09090909
 #define DDR_PHY_DX4GCR6_RESERVED_31_30_SHIFT                   30
 #define DDR_PHY_DX4GCR6_RESERVED_31_30_MASK                    0xC0000000U
@@ -15621,9 +15621,9 @@
 /*
 * DRAM DQ VREF Select for Rank3
 */
-#undef DDR_PHY_DX4GCR6_DXDQVREFR3_DEFVAL 
-#undef DDR_PHY_DX4GCR6_DXDQVREFR3_SHIFT 
-#undef DDR_PHY_DX4GCR6_DXDQVREFR3_MASK 
+#undef DDR_PHY_DX4GCR6_DXDQVREFR3_DEFVAL
+#undef DDR_PHY_DX4GCR6_DXDQVREFR3_SHIFT
+#undef DDR_PHY_DX4GCR6_DXDQVREFR3_MASK
 #define DDR_PHY_DX4GCR6_DXDQVREFR3_DEFVAL                      0x09090909
 #define DDR_PHY_DX4GCR6_DXDQVREFR3_SHIFT                       24
 #define DDR_PHY_DX4GCR6_DXDQVREFR3_MASK                        0x3F000000U
@@ -15631,9 +15631,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX4GCR6_RESERVED_23_22_DEFVAL 
-#undef DDR_PHY_DX4GCR6_RESERVED_23_22_SHIFT 
-#undef DDR_PHY_DX4GCR6_RESERVED_23_22_MASK 
+#undef DDR_PHY_DX4GCR6_RESERVED_23_22_DEFVAL
+#undef DDR_PHY_DX4GCR6_RESERVED_23_22_SHIFT
+#undef DDR_PHY_DX4GCR6_RESERVED_23_22_MASK
 #define DDR_PHY_DX4GCR6_RESERVED_23_22_DEFVAL                  0x09090909
 #define DDR_PHY_DX4GCR6_RESERVED_23_22_SHIFT                   22
 #define DDR_PHY_DX4GCR6_RESERVED_23_22_MASK                    0x00C00000U
@@ -15641,9 +15641,9 @@
 /*
 * DRAM DQ VREF Select for Rank2
 */
-#undef DDR_PHY_DX4GCR6_DXDQVREFR2_DEFVAL 
-#undef DDR_PHY_DX4GCR6_DXDQVREFR2_SHIFT 
-#undef DDR_PHY_DX4GCR6_DXDQVREFR2_MASK 
+#undef DDR_PHY_DX4GCR6_DXDQVREFR2_DEFVAL
+#undef DDR_PHY_DX4GCR6_DXDQVREFR2_SHIFT
+#undef DDR_PHY_DX4GCR6_DXDQVREFR2_MASK
 #define DDR_PHY_DX4GCR6_DXDQVREFR2_DEFVAL                      0x09090909
 #define DDR_PHY_DX4GCR6_DXDQVREFR2_SHIFT                       16
 #define DDR_PHY_DX4GCR6_DXDQVREFR2_MASK                        0x003F0000U
@@ -15651,9 +15651,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX4GCR6_RESERVED_15_14_DEFVAL 
-#undef DDR_PHY_DX4GCR6_RESERVED_15_14_SHIFT 
-#undef DDR_PHY_DX4GCR6_RESERVED_15_14_MASK 
+#undef DDR_PHY_DX4GCR6_RESERVED_15_14_DEFVAL
+#undef DDR_PHY_DX4GCR6_RESERVED_15_14_SHIFT
+#undef DDR_PHY_DX4GCR6_RESERVED_15_14_MASK
 #define DDR_PHY_DX4GCR6_RESERVED_15_14_DEFVAL                  0x09090909
 #define DDR_PHY_DX4GCR6_RESERVED_15_14_SHIFT                   14
 #define DDR_PHY_DX4GCR6_RESERVED_15_14_MASK                    0x0000C000U
@@ -15661,9 +15661,9 @@
 /*
 * DRAM DQ VREF Select for Rank1
 */
-#undef DDR_PHY_DX4GCR6_DXDQVREFR1_DEFVAL 
-#undef DDR_PHY_DX4GCR6_DXDQVREFR1_SHIFT 
-#undef DDR_PHY_DX4GCR6_DXDQVREFR1_MASK 
+#undef DDR_PHY_DX4GCR6_DXDQVREFR1_DEFVAL
+#undef DDR_PHY_DX4GCR6_DXDQVREFR1_SHIFT
+#undef DDR_PHY_DX4GCR6_DXDQVREFR1_MASK
 #define DDR_PHY_DX4GCR6_DXDQVREFR1_DEFVAL                      0x09090909
 #define DDR_PHY_DX4GCR6_DXDQVREFR1_SHIFT                       8
 #define DDR_PHY_DX4GCR6_DXDQVREFR1_MASK                        0x00003F00U
@@ -15671,9 +15671,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX4GCR6_RESERVED_7_6_DEFVAL 
-#undef DDR_PHY_DX4GCR6_RESERVED_7_6_SHIFT 
-#undef DDR_PHY_DX4GCR6_RESERVED_7_6_MASK 
+#undef DDR_PHY_DX4GCR6_RESERVED_7_6_DEFVAL
+#undef DDR_PHY_DX4GCR6_RESERVED_7_6_SHIFT
+#undef DDR_PHY_DX4GCR6_RESERVED_7_6_MASK
 #define DDR_PHY_DX4GCR6_RESERVED_7_6_DEFVAL                    0x09090909
 #define DDR_PHY_DX4GCR6_RESERVED_7_6_SHIFT                     6
 #define DDR_PHY_DX4GCR6_RESERVED_7_6_MASK                      0x000000C0U
@@ -15681,9 +15681,9 @@
 /*
 * DRAM DQ VREF Select for Rank0
 */
-#undef DDR_PHY_DX4GCR6_DXDQVREFR0_DEFVAL 
-#undef DDR_PHY_DX4GCR6_DXDQVREFR0_SHIFT 
-#undef DDR_PHY_DX4GCR6_DXDQVREFR0_MASK 
+#undef DDR_PHY_DX4GCR6_DXDQVREFR0_DEFVAL
+#undef DDR_PHY_DX4GCR6_DXDQVREFR0_SHIFT
+#undef DDR_PHY_DX4GCR6_DXDQVREFR0_MASK
 #define DDR_PHY_DX4GCR6_DXDQVREFR0_DEFVAL                      0x09090909
 #define DDR_PHY_DX4GCR6_DXDQVREFR0_SHIFT                       0
 #define DDR_PHY_DX4GCR6_DXDQVREFR0_MASK                        0x0000003FU
@@ -15691,9 +15691,9 @@
 /*
 * Calibration Bypass
 */
-#undef DDR_PHY_DX5GCR0_CALBYP_DEFVAL 
-#undef DDR_PHY_DX5GCR0_CALBYP_SHIFT 
-#undef DDR_PHY_DX5GCR0_CALBYP_MASK 
+#undef DDR_PHY_DX5GCR0_CALBYP_DEFVAL
+#undef DDR_PHY_DX5GCR0_CALBYP_SHIFT
+#undef DDR_PHY_DX5GCR0_CALBYP_MASK
 #define DDR_PHY_DX5GCR0_CALBYP_DEFVAL                          0x40200204
 #define DDR_PHY_DX5GCR0_CALBYP_SHIFT                           31
 #define DDR_PHY_DX5GCR0_CALBYP_MASK                            0x80000000U
@@ -15701,9 +15701,9 @@
 /*
 * Master Delay Line Enable
 */
-#undef DDR_PHY_DX5GCR0_MDLEN_DEFVAL 
-#undef DDR_PHY_DX5GCR0_MDLEN_SHIFT 
-#undef DDR_PHY_DX5GCR0_MDLEN_MASK 
+#undef DDR_PHY_DX5GCR0_MDLEN_DEFVAL
+#undef DDR_PHY_DX5GCR0_MDLEN_SHIFT
+#undef DDR_PHY_DX5GCR0_MDLEN_MASK
 #define DDR_PHY_DX5GCR0_MDLEN_DEFVAL                           0x40200204
 #define DDR_PHY_DX5GCR0_MDLEN_SHIFT                            30
 #define DDR_PHY_DX5GCR0_MDLEN_MASK                             0x40000000U
@@ -15711,9 +15711,9 @@
 /*
 * Configurable ODT(TE) Phase Shift
 */
-#undef DDR_PHY_DX5GCR0_CODTSHFT_DEFVAL 
-#undef DDR_PHY_DX5GCR0_CODTSHFT_SHIFT 
-#undef DDR_PHY_DX5GCR0_CODTSHFT_MASK 
+#undef DDR_PHY_DX5GCR0_CODTSHFT_DEFVAL
+#undef DDR_PHY_DX5GCR0_CODTSHFT_SHIFT
+#undef DDR_PHY_DX5GCR0_CODTSHFT_MASK
 #define DDR_PHY_DX5GCR0_CODTSHFT_DEFVAL                        0x40200204
 #define DDR_PHY_DX5GCR0_CODTSHFT_SHIFT                         28
 #define DDR_PHY_DX5GCR0_CODTSHFT_MASK                          0x30000000U
@@ -15721,9 +15721,9 @@
 /*
 * DQS Duty Cycle Correction
 */
-#undef DDR_PHY_DX5GCR0_DQSDCC_DEFVAL 
-#undef DDR_PHY_DX5GCR0_DQSDCC_SHIFT 
-#undef DDR_PHY_DX5GCR0_DQSDCC_MASK 
+#undef DDR_PHY_DX5GCR0_DQSDCC_DEFVAL
+#undef DDR_PHY_DX5GCR0_DQSDCC_SHIFT
+#undef DDR_PHY_DX5GCR0_DQSDCC_MASK
 #define DDR_PHY_DX5GCR0_DQSDCC_DEFVAL                          0x40200204
 #define DDR_PHY_DX5GCR0_DQSDCC_SHIFT                           24
 #define DDR_PHY_DX5GCR0_DQSDCC_MASK                            0x0F000000U
@@ -15732,9 +15732,9 @@
 * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
     *  input for the respective bypte lane of the PHY
 */
-#undef DDR_PHY_DX5GCR0_RDDLY_DEFVAL 
-#undef DDR_PHY_DX5GCR0_RDDLY_SHIFT 
-#undef DDR_PHY_DX5GCR0_RDDLY_MASK 
+#undef DDR_PHY_DX5GCR0_RDDLY_DEFVAL
+#undef DDR_PHY_DX5GCR0_RDDLY_SHIFT
+#undef DDR_PHY_DX5GCR0_RDDLY_MASK
 #define DDR_PHY_DX5GCR0_RDDLY_DEFVAL                           0x40200204
 #define DDR_PHY_DX5GCR0_RDDLY_SHIFT                            20
 #define DDR_PHY_DX5GCR0_RDDLY_MASK                             0x00F00000U
@@ -15742,9 +15742,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX5GCR0_RESERVED_19_14_DEFVAL 
-#undef DDR_PHY_DX5GCR0_RESERVED_19_14_SHIFT 
-#undef DDR_PHY_DX5GCR0_RESERVED_19_14_MASK 
+#undef DDR_PHY_DX5GCR0_RESERVED_19_14_DEFVAL
+#undef DDR_PHY_DX5GCR0_RESERVED_19_14_SHIFT
+#undef DDR_PHY_DX5GCR0_RESERVED_19_14_MASK
 #define DDR_PHY_DX5GCR0_RESERVED_19_14_DEFVAL                  0x40200204
 #define DDR_PHY_DX5GCR0_RESERVED_19_14_SHIFT                   14
 #define DDR_PHY_DX5GCR0_RESERVED_19_14_MASK                    0x000FC000U
@@ -15752,9 +15752,9 @@
 /*
 * DQSNSE Power Down Receiver
 */
-#undef DDR_PHY_DX5GCR0_DQSNSEPDR_DEFVAL 
-#undef DDR_PHY_DX5GCR0_DQSNSEPDR_SHIFT 
-#undef DDR_PHY_DX5GCR0_DQSNSEPDR_MASK 
+#undef DDR_PHY_DX5GCR0_DQSNSEPDR_DEFVAL
+#undef DDR_PHY_DX5GCR0_DQSNSEPDR_SHIFT
+#undef DDR_PHY_DX5GCR0_DQSNSEPDR_MASK
 #define DDR_PHY_DX5GCR0_DQSNSEPDR_DEFVAL                       0x40200204
 #define DDR_PHY_DX5GCR0_DQSNSEPDR_SHIFT                        13
 #define DDR_PHY_DX5GCR0_DQSNSEPDR_MASK                         0x00002000U
@@ -15762,9 +15762,9 @@
 /*
 * DQSSE Power Down Receiver
 */
-#undef DDR_PHY_DX5GCR0_DQSSEPDR_DEFVAL 
-#undef DDR_PHY_DX5GCR0_DQSSEPDR_SHIFT 
-#undef DDR_PHY_DX5GCR0_DQSSEPDR_MASK 
+#undef DDR_PHY_DX5GCR0_DQSSEPDR_DEFVAL
+#undef DDR_PHY_DX5GCR0_DQSSEPDR_SHIFT
+#undef DDR_PHY_DX5GCR0_DQSSEPDR_MASK
 #define DDR_PHY_DX5GCR0_DQSSEPDR_DEFVAL                        0x40200204
 #define DDR_PHY_DX5GCR0_DQSSEPDR_SHIFT                         12
 #define DDR_PHY_DX5GCR0_DQSSEPDR_MASK                          0x00001000U
@@ -15772,9 +15772,9 @@
 /*
 * RTT On Additive Latency
 */
-#undef DDR_PHY_DX5GCR0_RTTOAL_DEFVAL 
-#undef DDR_PHY_DX5GCR0_RTTOAL_SHIFT 
-#undef DDR_PHY_DX5GCR0_RTTOAL_MASK 
+#undef DDR_PHY_DX5GCR0_RTTOAL_DEFVAL
+#undef DDR_PHY_DX5GCR0_RTTOAL_SHIFT
+#undef DDR_PHY_DX5GCR0_RTTOAL_MASK
 #define DDR_PHY_DX5GCR0_RTTOAL_DEFVAL                          0x40200204
 #define DDR_PHY_DX5GCR0_RTTOAL_SHIFT                           11
 #define DDR_PHY_DX5GCR0_RTTOAL_MASK                            0x00000800U
@@ -15782,9 +15782,9 @@
 /*
 * RTT Output Hold
 */
-#undef DDR_PHY_DX5GCR0_RTTOH_DEFVAL 
-#undef DDR_PHY_DX5GCR0_RTTOH_SHIFT 
-#undef DDR_PHY_DX5GCR0_RTTOH_MASK 
+#undef DDR_PHY_DX5GCR0_RTTOH_DEFVAL
+#undef DDR_PHY_DX5GCR0_RTTOH_SHIFT
+#undef DDR_PHY_DX5GCR0_RTTOH_MASK
 #define DDR_PHY_DX5GCR0_RTTOH_DEFVAL                           0x40200204
 #define DDR_PHY_DX5GCR0_RTTOH_SHIFT                            9
 #define DDR_PHY_DX5GCR0_RTTOH_MASK                             0x00000600U
@@ -15792,9 +15792,9 @@
 /*
 * Configurable PDR Phase Shift
 */
-#undef DDR_PHY_DX5GCR0_CPDRSHFT_DEFVAL 
-#undef DDR_PHY_DX5GCR0_CPDRSHFT_SHIFT 
-#undef DDR_PHY_DX5GCR0_CPDRSHFT_MASK 
+#undef DDR_PHY_DX5GCR0_CPDRSHFT_DEFVAL
+#undef DDR_PHY_DX5GCR0_CPDRSHFT_SHIFT
+#undef DDR_PHY_DX5GCR0_CPDRSHFT_MASK
 #define DDR_PHY_DX5GCR0_CPDRSHFT_DEFVAL                        0x40200204
 #define DDR_PHY_DX5GCR0_CPDRSHFT_SHIFT                         7
 #define DDR_PHY_DX5GCR0_CPDRSHFT_MASK                          0x00000180U
@@ -15802,9 +15802,9 @@
 /*
 * DQSR Power Down
 */
-#undef DDR_PHY_DX5GCR0_DQSRPD_DEFVAL 
-#undef DDR_PHY_DX5GCR0_DQSRPD_SHIFT 
-#undef DDR_PHY_DX5GCR0_DQSRPD_MASK 
+#undef DDR_PHY_DX5GCR0_DQSRPD_DEFVAL
+#undef DDR_PHY_DX5GCR0_DQSRPD_SHIFT
+#undef DDR_PHY_DX5GCR0_DQSRPD_MASK
 #define DDR_PHY_DX5GCR0_DQSRPD_DEFVAL                          0x40200204
 #define DDR_PHY_DX5GCR0_DQSRPD_SHIFT                           6
 #define DDR_PHY_DX5GCR0_DQSRPD_MASK                            0x00000040U
@@ -15812,9 +15812,9 @@
 /*
 * DQSG Power Down Receiver
 */
-#undef DDR_PHY_DX5GCR0_DQSGPDR_DEFVAL 
-#undef DDR_PHY_DX5GCR0_DQSGPDR_SHIFT 
-#undef DDR_PHY_DX5GCR0_DQSGPDR_MASK 
+#undef DDR_PHY_DX5GCR0_DQSGPDR_DEFVAL
+#undef DDR_PHY_DX5GCR0_DQSGPDR_SHIFT
+#undef DDR_PHY_DX5GCR0_DQSGPDR_MASK
 #define DDR_PHY_DX5GCR0_DQSGPDR_DEFVAL                         0x40200204
 #define DDR_PHY_DX5GCR0_DQSGPDR_SHIFT                          5
 #define DDR_PHY_DX5GCR0_DQSGPDR_MASK                           0x00000020U
@@ -15822,9 +15822,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX5GCR0_RESERVED_4_DEFVAL 
-#undef DDR_PHY_DX5GCR0_RESERVED_4_SHIFT 
-#undef DDR_PHY_DX5GCR0_RESERVED_4_MASK 
+#undef DDR_PHY_DX5GCR0_RESERVED_4_DEFVAL
+#undef DDR_PHY_DX5GCR0_RESERVED_4_SHIFT
+#undef DDR_PHY_DX5GCR0_RESERVED_4_MASK
 #define DDR_PHY_DX5GCR0_RESERVED_4_DEFVAL                      0x40200204
 #define DDR_PHY_DX5GCR0_RESERVED_4_SHIFT                       4
 #define DDR_PHY_DX5GCR0_RESERVED_4_MASK                        0x00000010U
@@ -15832,9 +15832,9 @@
 /*
 * DQSG On-Die Termination
 */
-#undef DDR_PHY_DX5GCR0_DQSGODT_DEFVAL 
-#undef DDR_PHY_DX5GCR0_DQSGODT_SHIFT 
-#undef DDR_PHY_DX5GCR0_DQSGODT_MASK 
+#undef DDR_PHY_DX5GCR0_DQSGODT_DEFVAL
+#undef DDR_PHY_DX5GCR0_DQSGODT_SHIFT
+#undef DDR_PHY_DX5GCR0_DQSGODT_MASK
 #define DDR_PHY_DX5GCR0_DQSGODT_DEFVAL                         0x40200204
 #define DDR_PHY_DX5GCR0_DQSGODT_SHIFT                          3
 #define DDR_PHY_DX5GCR0_DQSGODT_MASK                           0x00000008U
@@ -15842,9 +15842,9 @@
 /*
 * DQSG Output Enable
 */
-#undef DDR_PHY_DX5GCR0_DQSGOE_DEFVAL 
-#undef DDR_PHY_DX5GCR0_DQSGOE_SHIFT 
-#undef DDR_PHY_DX5GCR0_DQSGOE_MASK 
+#undef DDR_PHY_DX5GCR0_DQSGOE_DEFVAL
+#undef DDR_PHY_DX5GCR0_DQSGOE_SHIFT
+#undef DDR_PHY_DX5GCR0_DQSGOE_MASK
 #define DDR_PHY_DX5GCR0_DQSGOE_DEFVAL                          0x40200204
 #define DDR_PHY_DX5GCR0_DQSGOE_SHIFT                           2
 #define DDR_PHY_DX5GCR0_DQSGOE_MASK                            0x00000004U
@@ -15852,9 +15852,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX5GCR0_RESERVED_1_0_DEFVAL 
-#undef DDR_PHY_DX5GCR0_RESERVED_1_0_SHIFT 
-#undef DDR_PHY_DX5GCR0_RESERVED_1_0_MASK 
+#undef DDR_PHY_DX5GCR0_RESERVED_1_0_DEFVAL
+#undef DDR_PHY_DX5GCR0_RESERVED_1_0_SHIFT
+#undef DDR_PHY_DX5GCR0_RESERVED_1_0_MASK
 #define DDR_PHY_DX5GCR0_RESERVED_1_0_DEFVAL                    0x40200204
 #define DDR_PHY_DX5GCR0_RESERVED_1_0_SHIFT                     0
 #define DDR_PHY_DX5GCR0_RESERVED_1_0_MASK                      0x00000003U
@@ -15862,9 +15862,9 @@
 /*
 * Enables the PDR mode for DQ[7:0]
 */
-#undef DDR_PHY_DX5GCR1_DXPDRMODE_DEFVAL 
-#undef DDR_PHY_DX5GCR1_DXPDRMODE_SHIFT 
-#undef DDR_PHY_DX5GCR1_DXPDRMODE_MASK 
+#undef DDR_PHY_DX5GCR1_DXPDRMODE_DEFVAL
+#undef DDR_PHY_DX5GCR1_DXPDRMODE_SHIFT
+#undef DDR_PHY_DX5GCR1_DXPDRMODE_MASK
 #define DDR_PHY_DX5GCR1_DXPDRMODE_DEFVAL                       0x00007FFF
 #define DDR_PHY_DX5GCR1_DXPDRMODE_SHIFT                        16
 #define DDR_PHY_DX5GCR1_DXPDRMODE_MASK                         0xFFFF0000U
@@ -15872,9 +15872,9 @@
 /*
 * Reserved. Returns zeroes on reads.
 */
-#undef DDR_PHY_DX5GCR1_RESERVED_15_DEFVAL 
-#undef DDR_PHY_DX5GCR1_RESERVED_15_SHIFT 
-#undef DDR_PHY_DX5GCR1_RESERVED_15_MASK 
+#undef DDR_PHY_DX5GCR1_RESERVED_15_DEFVAL
+#undef DDR_PHY_DX5GCR1_RESERVED_15_SHIFT
+#undef DDR_PHY_DX5GCR1_RESERVED_15_MASK
 #define DDR_PHY_DX5GCR1_RESERVED_15_DEFVAL                     0x00007FFF
 #define DDR_PHY_DX5GCR1_RESERVED_15_SHIFT                      15
 #define DDR_PHY_DX5GCR1_RESERVED_15_MASK                       0x00008000U
@@ -15882,9 +15882,9 @@
 /*
 * Select the delayed or non-delayed read data strobe #
 */
-#undef DDR_PHY_DX5GCR1_QSNSEL_DEFVAL 
-#undef DDR_PHY_DX5GCR1_QSNSEL_SHIFT 
-#undef DDR_PHY_DX5GCR1_QSNSEL_MASK 
+#undef DDR_PHY_DX5GCR1_QSNSEL_DEFVAL
+#undef DDR_PHY_DX5GCR1_QSNSEL_SHIFT
+#undef DDR_PHY_DX5GCR1_QSNSEL_MASK
 #define DDR_PHY_DX5GCR1_QSNSEL_DEFVAL                          0x00007FFF
 #define DDR_PHY_DX5GCR1_QSNSEL_SHIFT                           14
 #define DDR_PHY_DX5GCR1_QSNSEL_MASK                            0x00004000U
@@ -15892,9 +15892,9 @@
 /*
 * Select the delayed or non-delayed read data strobe
 */
-#undef DDR_PHY_DX5GCR1_QSSEL_DEFVAL 
-#undef DDR_PHY_DX5GCR1_QSSEL_SHIFT 
-#undef DDR_PHY_DX5GCR1_QSSEL_MASK 
+#undef DDR_PHY_DX5GCR1_QSSEL_DEFVAL
+#undef DDR_PHY_DX5GCR1_QSSEL_SHIFT
+#undef DDR_PHY_DX5GCR1_QSSEL_MASK
 #define DDR_PHY_DX5GCR1_QSSEL_DEFVAL                           0x00007FFF
 #define DDR_PHY_DX5GCR1_QSSEL_SHIFT                            13
 #define DDR_PHY_DX5GCR1_QSSEL_MASK                             0x00002000U
@@ -15902,9 +15902,9 @@
 /*
 * Enables Read Data Strobe in a byte lane
 */
-#undef DDR_PHY_DX5GCR1_OEEN_DEFVAL 
-#undef DDR_PHY_DX5GCR1_OEEN_SHIFT 
-#undef DDR_PHY_DX5GCR1_OEEN_MASK 
+#undef DDR_PHY_DX5GCR1_OEEN_DEFVAL
+#undef DDR_PHY_DX5GCR1_OEEN_SHIFT
+#undef DDR_PHY_DX5GCR1_OEEN_MASK
 #define DDR_PHY_DX5GCR1_OEEN_DEFVAL                            0x00007FFF
 #define DDR_PHY_DX5GCR1_OEEN_SHIFT                             12
 #define DDR_PHY_DX5GCR1_OEEN_MASK                              0x00001000U
@@ -15912,9 +15912,9 @@
 /*
 * Enables PDR in a byte lane
 */
-#undef DDR_PHY_DX5GCR1_PDREN_DEFVAL 
-#undef DDR_PHY_DX5GCR1_PDREN_SHIFT 
-#undef DDR_PHY_DX5GCR1_PDREN_MASK 
+#undef DDR_PHY_DX5GCR1_PDREN_DEFVAL
+#undef DDR_PHY_DX5GCR1_PDREN_SHIFT
+#undef DDR_PHY_DX5GCR1_PDREN_MASK
 #define DDR_PHY_DX5GCR1_PDREN_DEFVAL                           0x00007FFF
 #define DDR_PHY_DX5GCR1_PDREN_SHIFT                            11
 #define DDR_PHY_DX5GCR1_PDREN_MASK                             0x00000800U
@@ -15922,9 +15922,9 @@
 /*
 * Enables ODT/TE in a byte lane
 */
-#undef DDR_PHY_DX5GCR1_TEEN_DEFVAL 
-#undef DDR_PHY_DX5GCR1_TEEN_SHIFT 
-#undef DDR_PHY_DX5GCR1_TEEN_MASK 
+#undef DDR_PHY_DX5GCR1_TEEN_DEFVAL
+#undef DDR_PHY_DX5GCR1_TEEN_SHIFT
+#undef DDR_PHY_DX5GCR1_TEEN_MASK
 #define DDR_PHY_DX5GCR1_TEEN_DEFVAL                            0x00007FFF
 #define DDR_PHY_DX5GCR1_TEEN_SHIFT                             10
 #define DDR_PHY_DX5GCR1_TEEN_MASK                              0x00000400U
@@ -15932,9 +15932,9 @@
 /*
 * Enables Write Data strobe in a byte lane
 */
-#undef DDR_PHY_DX5GCR1_DSEN_DEFVAL 
-#undef DDR_PHY_DX5GCR1_DSEN_SHIFT 
-#undef DDR_PHY_DX5GCR1_DSEN_MASK 
+#undef DDR_PHY_DX5GCR1_DSEN_DEFVAL
+#undef DDR_PHY_DX5GCR1_DSEN_SHIFT
+#undef DDR_PHY_DX5GCR1_DSEN_MASK
 #define DDR_PHY_DX5GCR1_DSEN_DEFVAL                            0x00007FFF
 #define DDR_PHY_DX5GCR1_DSEN_SHIFT                             9
 #define DDR_PHY_DX5GCR1_DSEN_MASK                              0x00000200U
@@ -15942,9 +15942,9 @@
 /*
 * Enables DM pin in a byte lane
 */
-#undef DDR_PHY_DX5GCR1_DMEN_DEFVAL 
-#undef DDR_PHY_DX5GCR1_DMEN_SHIFT 
-#undef DDR_PHY_DX5GCR1_DMEN_MASK 
+#undef DDR_PHY_DX5GCR1_DMEN_DEFVAL
+#undef DDR_PHY_DX5GCR1_DMEN_SHIFT
+#undef DDR_PHY_DX5GCR1_DMEN_MASK
 #define DDR_PHY_DX5GCR1_DMEN_DEFVAL                            0x00007FFF
 #define DDR_PHY_DX5GCR1_DMEN_SHIFT                             8
 #define DDR_PHY_DX5GCR1_DMEN_MASK                              0x00000100U
@@ -15952,9 +15952,9 @@
 /*
 * Enables DQ corresponding to each bit in a byte
 */
-#undef DDR_PHY_DX5GCR1_DQEN_DEFVAL 
-#undef DDR_PHY_DX5GCR1_DQEN_SHIFT 
-#undef DDR_PHY_DX5GCR1_DQEN_MASK 
+#undef DDR_PHY_DX5GCR1_DQEN_DEFVAL
+#undef DDR_PHY_DX5GCR1_DQEN_SHIFT
+#undef DDR_PHY_DX5GCR1_DQEN_MASK
 #define DDR_PHY_DX5GCR1_DQEN_DEFVAL                            0x00007FFF
 #define DDR_PHY_DX5GCR1_DQEN_SHIFT                             0
 #define DDR_PHY_DX5GCR1_DQEN_MASK                              0x000000FFU
@@ -15962,9 +15962,9 @@
 /*
 * Byte lane VREF IOM (Used only by D4MU IOs)
 */
-#undef DDR_PHY_DX5GCR4_RESERVED_31_29_DEFVAL 
-#undef DDR_PHY_DX5GCR4_RESERVED_31_29_SHIFT 
-#undef DDR_PHY_DX5GCR4_RESERVED_31_29_MASK 
+#undef DDR_PHY_DX5GCR4_RESERVED_31_29_DEFVAL
+#undef DDR_PHY_DX5GCR4_RESERVED_31_29_SHIFT
+#undef DDR_PHY_DX5GCR4_RESERVED_31_29_MASK
 #define DDR_PHY_DX5GCR4_RESERVED_31_29_DEFVAL                  0x0E00003C
 #define DDR_PHY_DX5GCR4_RESERVED_31_29_SHIFT                   29
 #define DDR_PHY_DX5GCR4_RESERVED_31_29_MASK                    0xE0000000U
@@ -15972,9 +15972,9 @@
 /*
 * Byte Lane VREF Pad Enable
 */
-#undef DDR_PHY_DX5GCR4_DXREFPEN_DEFVAL 
-#undef DDR_PHY_DX5GCR4_DXREFPEN_SHIFT 
-#undef DDR_PHY_DX5GCR4_DXREFPEN_MASK 
+#undef DDR_PHY_DX5GCR4_DXREFPEN_DEFVAL
+#undef DDR_PHY_DX5GCR4_DXREFPEN_SHIFT
+#undef DDR_PHY_DX5GCR4_DXREFPEN_MASK
 #define DDR_PHY_DX5GCR4_DXREFPEN_DEFVAL                        0x0E00003C
 #define DDR_PHY_DX5GCR4_DXREFPEN_SHIFT                         28
 #define DDR_PHY_DX5GCR4_DXREFPEN_MASK                          0x10000000U
@@ -15982,9 +15982,9 @@
 /*
 * Byte Lane Internal VREF Enable
 */
-#undef DDR_PHY_DX5GCR4_DXREFEEN_DEFVAL 
-#undef DDR_PHY_DX5GCR4_DXREFEEN_SHIFT 
-#undef DDR_PHY_DX5GCR4_DXREFEEN_MASK 
+#undef DDR_PHY_DX5GCR4_DXREFEEN_DEFVAL
+#undef DDR_PHY_DX5GCR4_DXREFEEN_SHIFT
+#undef DDR_PHY_DX5GCR4_DXREFEEN_MASK
 #define DDR_PHY_DX5GCR4_DXREFEEN_DEFVAL                        0x0E00003C
 #define DDR_PHY_DX5GCR4_DXREFEEN_SHIFT                         26
 #define DDR_PHY_DX5GCR4_DXREFEEN_MASK                          0x0C000000U
@@ -15992,9 +15992,9 @@
 /*
 * Byte Lane Single-End VREF Enable
 */
-#undef DDR_PHY_DX5GCR4_DXREFSEN_DEFVAL 
-#undef DDR_PHY_DX5GCR4_DXREFSEN_SHIFT 
-#undef DDR_PHY_DX5GCR4_DXREFSEN_MASK 
+#undef DDR_PHY_DX5GCR4_DXREFSEN_DEFVAL
+#undef DDR_PHY_DX5GCR4_DXREFSEN_SHIFT
+#undef DDR_PHY_DX5GCR4_DXREFSEN_MASK
 #define DDR_PHY_DX5GCR4_DXREFSEN_DEFVAL                        0x0E00003C
 #define DDR_PHY_DX5GCR4_DXREFSEN_SHIFT                         25
 #define DDR_PHY_DX5GCR4_DXREFSEN_MASK                          0x02000000U
@@ -16002,9 +16002,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX5GCR4_RESERVED_24_DEFVAL 
-#undef DDR_PHY_DX5GCR4_RESERVED_24_SHIFT 
-#undef DDR_PHY_DX5GCR4_RESERVED_24_MASK 
+#undef DDR_PHY_DX5GCR4_RESERVED_24_DEFVAL
+#undef DDR_PHY_DX5GCR4_RESERVED_24_SHIFT
+#undef DDR_PHY_DX5GCR4_RESERVED_24_MASK
 #define DDR_PHY_DX5GCR4_RESERVED_24_DEFVAL                     0x0E00003C
 #define DDR_PHY_DX5GCR4_RESERVED_24_SHIFT                      24
 #define DDR_PHY_DX5GCR4_RESERVED_24_MASK                       0x01000000U
@@ -16012,9 +16012,9 @@
 /*
 * External VREF generator REFSEL range select
 */
-#undef DDR_PHY_DX5GCR4_DXREFESELRANGE_DEFVAL 
-#undef DDR_PHY_DX5GCR4_DXREFESELRANGE_SHIFT 
-#undef DDR_PHY_DX5GCR4_DXREFESELRANGE_MASK 
+#undef DDR_PHY_DX5GCR4_DXREFESELRANGE_DEFVAL
+#undef DDR_PHY_DX5GCR4_DXREFESELRANGE_SHIFT
+#undef DDR_PHY_DX5GCR4_DXREFESELRANGE_MASK
 #define DDR_PHY_DX5GCR4_DXREFESELRANGE_DEFVAL                  0x0E00003C
 #define DDR_PHY_DX5GCR4_DXREFESELRANGE_SHIFT                   23
 #define DDR_PHY_DX5GCR4_DXREFESELRANGE_MASK                    0x00800000U
@@ -16022,9 +16022,9 @@
 /*
 * Byte Lane External VREF Select
 */
-#undef DDR_PHY_DX5GCR4_DXREFESEL_DEFVAL 
-#undef DDR_PHY_DX5GCR4_DXREFESEL_SHIFT 
-#undef DDR_PHY_DX5GCR4_DXREFESEL_MASK 
+#undef DDR_PHY_DX5GCR4_DXREFESEL_DEFVAL
+#undef DDR_PHY_DX5GCR4_DXREFESEL_SHIFT
+#undef DDR_PHY_DX5GCR4_DXREFESEL_MASK
 #define DDR_PHY_DX5GCR4_DXREFESEL_DEFVAL                       0x0E00003C
 #define DDR_PHY_DX5GCR4_DXREFESEL_SHIFT                        16
 #define DDR_PHY_DX5GCR4_DXREFESEL_MASK                         0x007F0000U
@@ -16032,9 +16032,9 @@
 /*
 * Single ended VREF generator REFSEL range select
 */
-#undef DDR_PHY_DX5GCR4_DXREFSSELRANGE_DEFVAL 
-#undef DDR_PHY_DX5GCR4_DXREFSSELRANGE_SHIFT 
-#undef DDR_PHY_DX5GCR4_DXREFSSELRANGE_MASK 
+#undef DDR_PHY_DX5GCR4_DXREFSSELRANGE_DEFVAL
+#undef DDR_PHY_DX5GCR4_DXREFSSELRANGE_SHIFT
+#undef DDR_PHY_DX5GCR4_DXREFSSELRANGE_MASK
 #define DDR_PHY_DX5GCR4_DXREFSSELRANGE_DEFVAL                  0x0E00003C
 #define DDR_PHY_DX5GCR4_DXREFSSELRANGE_SHIFT                   15
 #define DDR_PHY_DX5GCR4_DXREFSSELRANGE_MASK                    0x00008000U
@@ -16042,9 +16042,9 @@
 /*
 * Byte Lane Single-End VREF Select
 */
-#undef DDR_PHY_DX5GCR4_DXREFSSEL_DEFVAL 
-#undef DDR_PHY_DX5GCR4_DXREFSSEL_SHIFT 
-#undef DDR_PHY_DX5GCR4_DXREFSSEL_MASK 
+#undef DDR_PHY_DX5GCR4_DXREFSSEL_DEFVAL
+#undef DDR_PHY_DX5GCR4_DXREFSSEL_SHIFT
+#undef DDR_PHY_DX5GCR4_DXREFSSEL_MASK
 #define DDR_PHY_DX5GCR4_DXREFSSEL_DEFVAL                       0x0E00003C
 #define DDR_PHY_DX5GCR4_DXREFSSEL_SHIFT                        8
 #define DDR_PHY_DX5GCR4_DXREFSSEL_MASK                         0x00007F00U
@@ -16052,9 +16052,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX5GCR4_RESERVED_7_6_DEFVAL 
-#undef DDR_PHY_DX5GCR4_RESERVED_7_6_SHIFT 
-#undef DDR_PHY_DX5GCR4_RESERVED_7_6_MASK 
+#undef DDR_PHY_DX5GCR4_RESERVED_7_6_DEFVAL
+#undef DDR_PHY_DX5GCR4_RESERVED_7_6_SHIFT
+#undef DDR_PHY_DX5GCR4_RESERVED_7_6_MASK
 #define DDR_PHY_DX5GCR4_RESERVED_7_6_DEFVAL                    0x0E00003C
 #define DDR_PHY_DX5GCR4_RESERVED_7_6_SHIFT                     6
 #define DDR_PHY_DX5GCR4_RESERVED_7_6_MASK                      0x000000C0U
@@ -16062,9 +16062,9 @@
 /*
 * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
 */
-#undef DDR_PHY_DX5GCR4_DXREFIEN_DEFVAL 
-#undef DDR_PHY_DX5GCR4_DXREFIEN_SHIFT 
-#undef DDR_PHY_DX5GCR4_DXREFIEN_MASK 
+#undef DDR_PHY_DX5GCR4_DXREFIEN_DEFVAL
+#undef DDR_PHY_DX5GCR4_DXREFIEN_SHIFT
+#undef DDR_PHY_DX5GCR4_DXREFIEN_MASK
 #define DDR_PHY_DX5GCR4_DXREFIEN_DEFVAL                        0x0E00003C
 #define DDR_PHY_DX5GCR4_DXREFIEN_SHIFT                         2
 #define DDR_PHY_DX5GCR4_DXREFIEN_MASK                          0x0000003CU
@@ -16072,9 +16072,9 @@
 /*
 * VRMON control for DQ IO (Single Ended) buffers of a byte lane.
 */
-#undef DDR_PHY_DX5GCR4_DXREFIMON_DEFVAL 
-#undef DDR_PHY_DX5GCR4_DXREFIMON_SHIFT 
-#undef DDR_PHY_DX5GCR4_DXREFIMON_MASK 
+#undef DDR_PHY_DX5GCR4_DXREFIMON_DEFVAL
+#undef DDR_PHY_DX5GCR4_DXREFIMON_SHIFT
+#undef DDR_PHY_DX5GCR4_DXREFIMON_MASK
 #define DDR_PHY_DX5GCR4_DXREFIMON_DEFVAL                       0x0E00003C
 #define DDR_PHY_DX5GCR4_DXREFIMON_SHIFT                        0
 #define DDR_PHY_DX5GCR4_DXREFIMON_MASK                         0x00000003U
@@ -16082,9 +16082,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX5GCR5_RESERVED_31_DEFVAL 
-#undef DDR_PHY_DX5GCR5_RESERVED_31_SHIFT 
-#undef DDR_PHY_DX5GCR5_RESERVED_31_MASK 
+#undef DDR_PHY_DX5GCR5_RESERVED_31_DEFVAL
+#undef DDR_PHY_DX5GCR5_RESERVED_31_SHIFT
+#undef DDR_PHY_DX5GCR5_RESERVED_31_MASK
 #define DDR_PHY_DX5GCR5_RESERVED_31_DEFVAL                     0x09090909
 #define DDR_PHY_DX5GCR5_RESERVED_31_SHIFT                      31
 #define DDR_PHY_DX5GCR5_RESERVED_31_MASK                       0x80000000U
@@ -16092,9 +16092,9 @@
 /*
 * Byte Lane internal VREF Select for Rank 3
 */
-#undef DDR_PHY_DX5GCR5_DXREFISELR3_DEFVAL 
-#undef DDR_PHY_DX5GCR5_DXREFISELR3_SHIFT 
-#undef DDR_PHY_DX5GCR5_DXREFISELR3_MASK 
+#undef DDR_PHY_DX5GCR5_DXREFISELR3_DEFVAL
+#undef DDR_PHY_DX5GCR5_DXREFISELR3_SHIFT
+#undef DDR_PHY_DX5GCR5_DXREFISELR3_MASK
 #define DDR_PHY_DX5GCR5_DXREFISELR3_DEFVAL                     0x09090909
 #define DDR_PHY_DX5GCR5_DXREFISELR3_SHIFT                      24
 #define DDR_PHY_DX5GCR5_DXREFISELR3_MASK                       0x7F000000U
@@ -16102,9 +16102,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX5GCR5_RESERVED_23_DEFVAL 
-#undef DDR_PHY_DX5GCR5_RESERVED_23_SHIFT 
-#undef DDR_PHY_DX5GCR5_RESERVED_23_MASK 
+#undef DDR_PHY_DX5GCR5_RESERVED_23_DEFVAL
+#undef DDR_PHY_DX5GCR5_RESERVED_23_SHIFT
+#undef DDR_PHY_DX5GCR5_RESERVED_23_MASK
 #define DDR_PHY_DX5GCR5_RESERVED_23_DEFVAL                     0x09090909
 #define DDR_PHY_DX5GCR5_RESERVED_23_SHIFT                      23
 #define DDR_PHY_DX5GCR5_RESERVED_23_MASK                       0x00800000U
@@ -16112,9 +16112,9 @@
 /*
 * Byte Lane internal VREF Select for Rank 2
 */
-#undef DDR_PHY_DX5GCR5_DXREFISELR2_DEFVAL 
-#undef DDR_PHY_DX5GCR5_DXREFISELR2_SHIFT 
-#undef DDR_PHY_DX5GCR5_DXREFISELR2_MASK 
+#undef DDR_PHY_DX5GCR5_DXREFISELR2_DEFVAL
+#undef DDR_PHY_DX5GCR5_DXREFISELR2_SHIFT
+#undef DDR_PHY_DX5GCR5_DXREFISELR2_MASK
 #define DDR_PHY_DX5GCR5_DXREFISELR2_DEFVAL                     0x09090909
 #define DDR_PHY_DX5GCR5_DXREFISELR2_SHIFT                      16
 #define DDR_PHY_DX5GCR5_DXREFISELR2_MASK                       0x007F0000U
@@ -16122,9 +16122,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX5GCR5_RESERVED_15_DEFVAL 
-#undef DDR_PHY_DX5GCR5_RESERVED_15_SHIFT 
-#undef DDR_PHY_DX5GCR5_RESERVED_15_MASK 
+#undef DDR_PHY_DX5GCR5_RESERVED_15_DEFVAL
+#undef DDR_PHY_DX5GCR5_RESERVED_15_SHIFT
+#undef DDR_PHY_DX5GCR5_RESERVED_15_MASK
 #define DDR_PHY_DX5GCR5_RESERVED_15_DEFVAL                     0x09090909
 #define DDR_PHY_DX5GCR5_RESERVED_15_SHIFT                      15
 #define DDR_PHY_DX5GCR5_RESERVED_15_MASK                       0x00008000U
@@ -16132,9 +16132,9 @@
 /*
 * Byte Lane internal VREF Select for Rank 1
 */
-#undef DDR_PHY_DX5GCR5_DXREFISELR1_DEFVAL 
-#undef DDR_PHY_DX5GCR5_DXREFISELR1_SHIFT 
-#undef DDR_PHY_DX5GCR5_DXREFISELR1_MASK 
+#undef DDR_PHY_DX5GCR5_DXREFISELR1_DEFVAL
+#undef DDR_PHY_DX5GCR5_DXREFISELR1_SHIFT
+#undef DDR_PHY_DX5GCR5_DXREFISELR1_MASK
 #define DDR_PHY_DX5GCR5_DXREFISELR1_DEFVAL                     0x09090909
 #define DDR_PHY_DX5GCR5_DXREFISELR1_SHIFT                      8
 #define DDR_PHY_DX5GCR5_DXREFISELR1_MASK                       0x00007F00U
@@ -16142,9 +16142,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX5GCR5_RESERVED_7_DEFVAL 
-#undef DDR_PHY_DX5GCR5_RESERVED_7_SHIFT 
-#undef DDR_PHY_DX5GCR5_RESERVED_7_MASK 
+#undef DDR_PHY_DX5GCR5_RESERVED_7_DEFVAL
+#undef DDR_PHY_DX5GCR5_RESERVED_7_SHIFT
+#undef DDR_PHY_DX5GCR5_RESERVED_7_MASK
 #define DDR_PHY_DX5GCR5_RESERVED_7_DEFVAL                      0x09090909
 #define DDR_PHY_DX5GCR5_RESERVED_7_SHIFT                       7
 #define DDR_PHY_DX5GCR5_RESERVED_7_MASK                        0x00000080U
@@ -16152,9 +16152,9 @@
 /*
 * Byte Lane internal VREF Select for Rank 0
 */
-#undef DDR_PHY_DX5GCR5_DXREFISELR0_DEFVAL 
-#undef DDR_PHY_DX5GCR5_DXREFISELR0_SHIFT 
-#undef DDR_PHY_DX5GCR5_DXREFISELR0_MASK 
+#undef DDR_PHY_DX5GCR5_DXREFISELR0_DEFVAL
+#undef DDR_PHY_DX5GCR5_DXREFISELR0_SHIFT
+#undef DDR_PHY_DX5GCR5_DXREFISELR0_MASK
 #define DDR_PHY_DX5GCR5_DXREFISELR0_DEFVAL                     0x09090909
 #define DDR_PHY_DX5GCR5_DXREFISELR0_SHIFT                      0
 #define DDR_PHY_DX5GCR5_DXREFISELR0_MASK                       0x0000007FU
@@ -16162,9 +16162,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX5GCR6_RESERVED_31_30_DEFVAL 
-#undef DDR_PHY_DX5GCR6_RESERVED_31_30_SHIFT 
-#undef DDR_PHY_DX5GCR6_RESERVED_31_30_MASK 
+#undef DDR_PHY_DX5GCR6_RESERVED_31_30_DEFVAL
+#undef DDR_PHY_DX5GCR6_RESERVED_31_30_SHIFT
+#undef DDR_PHY_DX5GCR6_RESERVED_31_30_MASK
 #define DDR_PHY_DX5GCR6_RESERVED_31_30_DEFVAL                  0x09090909
 #define DDR_PHY_DX5GCR6_RESERVED_31_30_SHIFT                   30
 #define DDR_PHY_DX5GCR6_RESERVED_31_30_MASK                    0xC0000000U
@@ -16172,9 +16172,9 @@
 /*
 * DRAM DQ VREF Select for Rank3
 */
-#undef DDR_PHY_DX5GCR6_DXDQVREFR3_DEFVAL 
-#undef DDR_PHY_DX5GCR6_DXDQVREFR3_SHIFT 
-#undef DDR_PHY_DX5GCR6_DXDQVREFR3_MASK 
+#undef DDR_PHY_DX5GCR6_DXDQVREFR3_DEFVAL
+#undef DDR_PHY_DX5GCR6_DXDQVREFR3_SHIFT
+#undef DDR_PHY_DX5GCR6_DXDQVREFR3_MASK
 #define DDR_PHY_DX5GCR6_DXDQVREFR3_DEFVAL                      0x09090909
 #define DDR_PHY_DX5GCR6_DXDQVREFR3_SHIFT                       24
 #define DDR_PHY_DX5GCR6_DXDQVREFR3_MASK                        0x3F000000U
@@ -16182,9 +16182,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX5GCR6_RESERVED_23_22_DEFVAL 
-#undef DDR_PHY_DX5GCR6_RESERVED_23_22_SHIFT 
-#undef DDR_PHY_DX5GCR6_RESERVED_23_22_MASK 
+#undef DDR_PHY_DX5GCR6_RESERVED_23_22_DEFVAL
+#undef DDR_PHY_DX5GCR6_RESERVED_23_22_SHIFT
+#undef DDR_PHY_DX5GCR6_RESERVED_23_22_MASK
 #define DDR_PHY_DX5GCR6_RESERVED_23_22_DEFVAL                  0x09090909
 #define DDR_PHY_DX5GCR6_RESERVED_23_22_SHIFT                   22
 #define DDR_PHY_DX5GCR6_RESERVED_23_22_MASK                    0x00C00000U
@@ -16192,9 +16192,9 @@
 /*
 * DRAM DQ VREF Select for Rank2
 */
-#undef DDR_PHY_DX5GCR6_DXDQVREFR2_DEFVAL 
-#undef DDR_PHY_DX5GCR6_DXDQVREFR2_SHIFT 
-#undef DDR_PHY_DX5GCR6_DXDQVREFR2_MASK 
+#undef DDR_PHY_DX5GCR6_DXDQVREFR2_DEFVAL
+#undef DDR_PHY_DX5GCR6_DXDQVREFR2_SHIFT
+#undef DDR_PHY_DX5GCR6_DXDQVREFR2_MASK
 #define DDR_PHY_DX5GCR6_DXDQVREFR2_DEFVAL                      0x09090909
 #define DDR_PHY_DX5GCR6_DXDQVREFR2_SHIFT                       16
 #define DDR_PHY_DX5GCR6_DXDQVREFR2_MASK                        0x003F0000U
@@ -16202,9 +16202,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX5GCR6_RESERVED_15_14_DEFVAL 
-#undef DDR_PHY_DX5GCR6_RESERVED_15_14_SHIFT 
-#undef DDR_PHY_DX5GCR6_RESERVED_15_14_MASK 
+#undef DDR_PHY_DX5GCR6_RESERVED_15_14_DEFVAL
+#undef DDR_PHY_DX5GCR6_RESERVED_15_14_SHIFT
+#undef DDR_PHY_DX5GCR6_RESERVED_15_14_MASK
 #define DDR_PHY_DX5GCR6_RESERVED_15_14_DEFVAL                  0x09090909
 #define DDR_PHY_DX5GCR6_RESERVED_15_14_SHIFT                   14
 #define DDR_PHY_DX5GCR6_RESERVED_15_14_MASK                    0x0000C000U
@@ -16212,9 +16212,9 @@
 /*
 * DRAM DQ VREF Select for Rank1
 */
-#undef DDR_PHY_DX5GCR6_DXDQVREFR1_DEFVAL 
-#undef DDR_PHY_DX5GCR6_DXDQVREFR1_SHIFT 
-#undef DDR_PHY_DX5GCR6_DXDQVREFR1_MASK 
+#undef DDR_PHY_DX5GCR6_DXDQVREFR1_DEFVAL
+#undef DDR_PHY_DX5GCR6_DXDQVREFR1_SHIFT
+#undef DDR_PHY_DX5GCR6_DXDQVREFR1_MASK
 #define DDR_PHY_DX5GCR6_DXDQVREFR1_DEFVAL                      0x09090909
 #define DDR_PHY_DX5GCR6_DXDQVREFR1_SHIFT                       8
 #define DDR_PHY_DX5GCR6_DXDQVREFR1_MASK                        0x00003F00U
@@ -16222,9 +16222,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX5GCR6_RESERVED_7_6_DEFVAL 
-#undef DDR_PHY_DX5GCR6_RESERVED_7_6_SHIFT 
-#undef DDR_PHY_DX5GCR6_RESERVED_7_6_MASK 
+#undef DDR_PHY_DX5GCR6_RESERVED_7_6_DEFVAL
+#undef DDR_PHY_DX5GCR6_RESERVED_7_6_SHIFT
+#undef DDR_PHY_DX5GCR6_RESERVED_7_6_MASK
 #define DDR_PHY_DX5GCR6_RESERVED_7_6_DEFVAL                    0x09090909
 #define DDR_PHY_DX5GCR6_RESERVED_7_6_SHIFT                     6
 #define DDR_PHY_DX5GCR6_RESERVED_7_6_MASK                      0x000000C0U
@@ -16232,9 +16232,9 @@
 /*
 * DRAM DQ VREF Select for Rank0
 */
-#undef DDR_PHY_DX5GCR6_DXDQVREFR0_DEFVAL 
-#undef DDR_PHY_DX5GCR6_DXDQVREFR0_SHIFT 
-#undef DDR_PHY_DX5GCR6_DXDQVREFR0_MASK 
+#undef DDR_PHY_DX5GCR6_DXDQVREFR0_DEFVAL
+#undef DDR_PHY_DX5GCR6_DXDQVREFR0_SHIFT
+#undef DDR_PHY_DX5GCR6_DXDQVREFR0_MASK
 #define DDR_PHY_DX5GCR6_DXDQVREFR0_DEFVAL                      0x09090909
 #define DDR_PHY_DX5GCR6_DXDQVREFR0_SHIFT                       0
 #define DDR_PHY_DX5GCR6_DXDQVREFR0_MASK                        0x0000003FU
@@ -16242,9 +16242,9 @@
 /*
 * Calibration Bypass
 */
-#undef DDR_PHY_DX6GCR0_CALBYP_DEFVAL 
-#undef DDR_PHY_DX6GCR0_CALBYP_SHIFT 
-#undef DDR_PHY_DX6GCR0_CALBYP_MASK 
+#undef DDR_PHY_DX6GCR0_CALBYP_DEFVAL
+#undef DDR_PHY_DX6GCR0_CALBYP_SHIFT
+#undef DDR_PHY_DX6GCR0_CALBYP_MASK
 #define DDR_PHY_DX6GCR0_CALBYP_DEFVAL                          0x40200204
 #define DDR_PHY_DX6GCR0_CALBYP_SHIFT                           31
 #define DDR_PHY_DX6GCR0_CALBYP_MASK                            0x80000000U
@@ -16252,9 +16252,9 @@
 /*
 * Master Delay Line Enable
 */
-#undef DDR_PHY_DX6GCR0_MDLEN_DEFVAL 
-#undef DDR_PHY_DX6GCR0_MDLEN_SHIFT 
-#undef DDR_PHY_DX6GCR0_MDLEN_MASK 
+#undef DDR_PHY_DX6GCR0_MDLEN_DEFVAL
+#undef DDR_PHY_DX6GCR0_MDLEN_SHIFT
+#undef DDR_PHY_DX6GCR0_MDLEN_MASK
 #define DDR_PHY_DX6GCR0_MDLEN_DEFVAL                           0x40200204
 #define DDR_PHY_DX6GCR0_MDLEN_SHIFT                            30
 #define DDR_PHY_DX6GCR0_MDLEN_MASK                             0x40000000U
@@ -16262,9 +16262,9 @@
 /*
 * Configurable ODT(TE) Phase Shift
 */
-#undef DDR_PHY_DX6GCR0_CODTSHFT_DEFVAL 
-#undef DDR_PHY_DX6GCR0_CODTSHFT_SHIFT 
-#undef DDR_PHY_DX6GCR0_CODTSHFT_MASK 
+#undef DDR_PHY_DX6GCR0_CODTSHFT_DEFVAL
+#undef DDR_PHY_DX6GCR0_CODTSHFT_SHIFT
+#undef DDR_PHY_DX6GCR0_CODTSHFT_MASK
 #define DDR_PHY_DX6GCR0_CODTSHFT_DEFVAL                        0x40200204
 #define DDR_PHY_DX6GCR0_CODTSHFT_SHIFT                         28
 #define DDR_PHY_DX6GCR0_CODTSHFT_MASK                          0x30000000U
@@ -16272,9 +16272,9 @@
 /*
 * DQS Duty Cycle Correction
 */
-#undef DDR_PHY_DX6GCR0_DQSDCC_DEFVAL 
-#undef DDR_PHY_DX6GCR0_DQSDCC_SHIFT 
-#undef DDR_PHY_DX6GCR0_DQSDCC_MASK 
+#undef DDR_PHY_DX6GCR0_DQSDCC_DEFVAL
+#undef DDR_PHY_DX6GCR0_DQSDCC_SHIFT
+#undef DDR_PHY_DX6GCR0_DQSDCC_MASK
 #define DDR_PHY_DX6GCR0_DQSDCC_DEFVAL                          0x40200204
 #define DDR_PHY_DX6GCR0_DQSDCC_SHIFT                           24
 #define DDR_PHY_DX6GCR0_DQSDCC_MASK                            0x0F000000U
@@ -16283,9 +16283,9 @@
 * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
     *  input for the respective bypte lane of the PHY
 */
-#undef DDR_PHY_DX6GCR0_RDDLY_DEFVAL 
-#undef DDR_PHY_DX6GCR0_RDDLY_SHIFT 
-#undef DDR_PHY_DX6GCR0_RDDLY_MASK 
+#undef DDR_PHY_DX6GCR0_RDDLY_DEFVAL
+#undef DDR_PHY_DX6GCR0_RDDLY_SHIFT
+#undef DDR_PHY_DX6GCR0_RDDLY_MASK
 #define DDR_PHY_DX6GCR0_RDDLY_DEFVAL                           0x40200204
 #define DDR_PHY_DX6GCR0_RDDLY_SHIFT                            20
 #define DDR_PHY_DX6GCR0_RDDLY_MASK                             0x00F00000U
@@ -16293,9 +16293,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX6GCR0_RESERVED_19_14_DEFVAL 
-#undef DDR_PHY_DX6GCR0_RESERVED_19_14_SHIFT 
-#undef DDR_PHY_DX6GCR0_RESERVED_19_14_MASK 
+#undef DDR_PHY_DX6GCR0_RESERVED_19_14_DEFVAL
+#undef DDR_PHY_DX6GCR0_RESERVED_19_14_SHIFT
+#undef DDR_PHY_DX6GCR0_RESERVED_19_14_MASK
 #define DDR_PHY_DX6GCR0_RESERVED_19_14_DEFVAL                  0x40200204
 #define DDR_PHY_DX6GCR0_RESERVED_19_14_SHIFT                   14
 #define DDR_PHY_DX6GCR0_RESERVED_19_14_MASK                    0x000FC000U
@@ -16303,9 +16303,9 @@
 /*
 * DQSNSE Power Down Receiver
 */
-#undef DDR_PHY_DX6GCR0_DQSNSEPDR_DEFVAL 
-#undef DDR_PHY_DX6GCR0_DQSNSEPDR_SHIFT 
-#undef DDR_PHY_DX6GCR0_DQSNSEPDR_MASK 
+#undef DDR_PHY_DX6GCR0_DQSNSEPDR_DEFVAL
+#undef DDR_PHY_DX6GCR0_DQSNSEPDR_SHIFT
+#undef DDR_PHY_DX6GCR0_DQSNSEPDR_MASK
 #define DDR_PHY_DX6GCR0_DQSNSEPDR_DEFVAL                       0x40200204
 #define DDR_PHY_DX6GCR0_DQSNSEPDR_SHIFT                        13
 #define DDR_PHY_DX6GCR0_DQSNSEPDR_MASK                         0x00002000U
@@ -16313,9 +16313,9 @@
 /*
 * DQSSE Power Down Receiver
 */
-#undef DDR_PHY_DX6GCR0_DQSSEPDR_DEFVAL 
-#undef DDR_PHY_DX6GCR0_DQSSEPDR_SHIFT 
-#undef DDR_PHY_DX6GCR0_DQSSEPDR_MASK 
+#undef DDR_PHY_DX6GCR0_DQSSEPDR_DEFVAL
+#undef DDR_PHY_DX6GCR0_DQSSEPDR_SHIFT
+#undef DDR_PHY_DX6GCR0_DQSSEPDR_MASK
 #define DDR_PHY_DX6GCR0_DQSSEPDR_DEFVAL                        0x40200204
 #define DDR_PHY_DX6GCR0_DQSSEPDR_SHIFT                         12
 #define DDR_PHY_DX6GCR0_DQSSEPDR_MASK                          0x00001000U
@@ -16323,9 +16323,9 @@
 /*
 * RTT On Additive Latency
 */
-#undef DDR_PHY_DX6GCR0_RTTOAL_DEFVAL 
-#undef DDR_PHY_DX6GCR0_RTTOAL_SHIFT 
-#undef DDR_PHY_DX6GCR0_RTTOAL_MASK 
+#undef DDR_PHY_DX6GCR0_RTTOAL_DEFVAL
+#undef DDR_PHY_DX6GCR0_RTTOAL_SHIFT
+#undef DDR_PHY_DX6GCR0_RTTOAL_MASK
 #define DDR_PHY_DX6GCR0_RTTOAL_DEFVAL                          0x40200204
 #define DDR_PHY_DX6GCR0_RTTOAL_SHIFT                           11
 #define DDR_PHY_DX6GCR0_RTTOAL_MASK                            0x00000800U
@@ -16333,9 +16333,9 @@
 /*
 * RTT Output Hold
 */
-#undef DDR_PHY_DX6GCR0_RTTOH_DEFVAL 
-#undef DDR_PHY_DX6GCR0_RTTOH_SHIFT 
-#undef DDR_PHY_DX6GCR0_RTTOH_MASK 
+#undef DDR_PHY_DX6GCR0_RTTOH_DEFVAL
+#undef DDR_PHY_DX6GCR0_RTTOH_SHIFT
+#undef DDR_PHY_DX6GCR0_RTTOH_MASK
 #define DDR_PHY_DX6GCR0_RTTOH_DEFVAL                           0x40200204
 #define DDR_PHY_DX6GCR0_RTTOH_SHIFT                            9
 #define DDR_PHY_DX6GCR0_RTTOH_MASK                             0x00000600U
@@ -16343,9 +16343,9 @@
 /*
 * Configurable PDR Phase Shift
 */
-#undef DDR_PHY_DX6GCR0_CPDRSHFT_DEFVAL 
-#undef DDR_PHY_DX6GCR0_CPDRSHFT_SHIFT 
-#undef DDR_PHY_DX6GCR0_CPDRSHFT_MASK 
+#undef DDR_PHY_DX6GCR0_CPDRSHFT_DEFVAL
+#undef DDR_PHY_DX6GCR0_CPDRSHFT_SHIFT
+#undef DDR_PHY_DX6GCR0_CPDRSHFT_MASK
 #define DDR_PHY_DX6GCR0_CPDRSHFT_DEFVAL                        0x40200204
 #define DDR_PHY_DX6GCR0_CPDRSHFT_SHIFT                         7
 #define DDR_PHY_DX6GCR0_CPDRSHFT_MASK                          0x00000180U
@@ -16353,9 +16353,9 @@
 /*
 * DQSR Power Down
 */
-#undef DDR_PHY_DX6GCR0_DQSRPD_DEFVAL 
-#undef DDR_PHY_DX6GCR0_DQSRPD_SHIFT 
-#undef DDR_PHY_DX6GCR0_DQSRPD_MASK 
+#undef DDR_PHY_DX6GCR0_DQSRPD_DEFVAL
+#undef DDR_PHY_DX6GCR0_DQSRPD_SHIFT
+#undef DDR_PHY_DX6GCR0_DQSRPD_MASK
 #define DDR_PHY_DX6GCR0_DQSRPD_DEFVAL                          0x40200204
 #define DDR_PHY_DX6GCR0_DQSRPD_SHIFT                           6
 #define DDR_PHY_DX6GCR0_DQSRPD_MASK                            0x00000040U
@@ -16363,9 +16363,9 @@
 /*
 * DQSG Power Down Receiver
 */
-#undef DDR_PHY_DX6GCR0_DQSGPDR_DEFVAL 
-#undef DDR_PHY_DX6GCR0_DQSGPDR_SHIFT 
-#undef DDR_PHY_DX6GCR0_DQSGPDR_MASK 
+#undef DDR_PHY_DX6GCR0_DQSGPDR_DEFVAL
+#undef DDR_PHY_DX6GCR0_DQSGPDR_SHIFT
+#undef DDR_PHY_DX6GCR0_DQSGPDR_MASK
 #define DDR_PHY_DX6GCR0_DQSGPDR_DEFVAL                         0x40200204
 #define DDR_PHY_DX6GCR0_DQSGPDR_SHIFT                          5
 #define DDR_PHY_DX6GCR0_DQSGPDR_MASK                           0x00000020U
@@ -16373,9 +16373,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX6GCR0_RESERVED_4_DEFVAL 
-#undef DDR_PHY_DX6GCR0_RESERVED_4_SHIFT 
-#undef DDR_PHY_DX6GCR0_RESERVED_4_MASK 
+#undef DDR_PHY_DX6GCR0_RESERVED_4_DEFVAL
+#undef DDR_PHY_DX6GCR0_RESERVED_4_SHIFT
+#undef DDR_PHY_DX6GCR0_RESERVED_4_MASK
 #define DDR_PHY_DX6GCR0_RESERVED_4_DEFVAL                      0x40200204
 #define DDR_PHY_DX6GCR0_RESERVED_4_SHIFT                       4
 #define DDR_PHY_DX6GCR0_RESERVED_4_MASK                        0x00000010U
@@ -16383,9 +16383,9 @@
 /*
 * DQSG On-Die Termination
 */
-#undef DDR_PHY_DX6GCR0_DQSGODT_DEFVAL 
-#undef DDR_PHY_DX6GCR0_DQSGODT_SHIFT 
-#undef DDR_PHY_DX6GCR0_DQSGODT_MASK 
+#undef DDR_PHY_DX6GCR0_DQSGODT_DEFVAL
+#undef DDR_PHY_DX6GCR0_DQSGODT_SHIFT
+#undef DDR_PHY_DX6GCR0_DQSGODT_MASK
 #define DDR_PHY_DX6GCR0_DQSGODT_DEFVAL                         0x40200204
 #define DDR_PHY_DX6GCR0_DQSGODT_SHIFT                          3
 #define DDR_PHY_DX6GCR0_DQSGODT_MASK                           0x00000008U
@@ -16393,9 +16393,9 @@
 /*
 * DQSG Output Enable
 */
-#undef DDR_PHY_DX6GCR0_DQSGOE_DEFVAL 
-#undef DDR_PHY_DX6GCR0_DQSGOE_SHIFT 
-#undef DDR_PHY_DX6GCR0_DQSGOE_MASK 
+#undef DDR_PHY_DX6GCR0_DQSGOE_DEFVAL
+#undef DDR_PHY_DX6GCR0_DQSGOE_SHIFT
+#undef DDR_PHY_DX6GCR0_DQSGOE_MASK
 #define DDR_PHY_DX6GCR0_DQSGOE_DEFVAL                          0x40200204
 #define DDR_PHY_DX6GCR0_DQSGOE_SHIFT                           2
 #define DDR_PHY_DX6GCR0_DQSGOE_MASK                            0x00000004U
@@ -16403,9 +16403,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX6GCR0_RESERVED_1_0_DEFVAL 
-#undef DDR_PHY_DX6GCR0_RESERVED_1_0_SHIFT 
-#undef DDR_PHY_DX6GCR0_RESERVED_1_0_MASK 
+#undef DDR_PHY_DX6GCR0_RESERVED_1_0_DEFVAL
+#undef DDR_PHY_DX6GCR0_RESERVED_1_0_SHIFT
+#undef DDR_PHY_DX6GCR0_RESERVED_1_0_MASK
 #define DDR_PHY_DX6GCR0_RESERVED_1_0_DEFVAL                    0x40200204
 #define DDR_PHY_DX6GCR0_RESERVED_1_0_SHIFT                     0
 #define DDR_PHY_DX6GCR0_RESERVED_1_0_MASK                      0x00000003U
@@ -16413,9 +16413,9 @@
 /*
 * Enables the PDR mode for DQ[7:0]
 */
-#undef DDR_PHY_DX6GCR1_DXPDRMODE_DEFVAL 
-#undef DDR_PHY_DX6GCR1_DXPDRMODE_SHIFT 
-#undef DDR_PHY_DX6GCR1_DXPDRMODE_MASK 
+#undef DDR_PHY_DX6GCR1_DXPDRMODE_DEFVAL
+#undef DDR_PHY_DX6GCR1_DXPDRMODE_SHIFT
+#undef DDR_PHY_DX6GCR1_DXPDRMODE_MASK
 #define DDR_PHY_DX6GCR1_DXPDRMODE_DEFVAL                       0x00007FFF
 #define DDR_PHY_DX6GCR1_DXPDRMODE_SHIFT                        16
 #define DDR_PHY_DX6GCR1_DXPDRMODE_MASK                         0xFFFF0000U
@@ -16423,9 +16423,9 @@
 /*
 * Reserved. Returns zeroes on reads.
 */
-#undef DDR_PHY_DX6GCR1_RESERVED_15_DEFVAL 
-#undef DDR_PHY_DX6GCR1_RESERVED_15_SHIFT 
-#undef DDR_PHY_DX6GCR1_RESERVED_15_MASK 
+#undef DDR_PHY_DX6GCR1_RESERVED_15_DEFVAL
+#undef DDR_PHY_DX6GCR1_RESERVED_15_SHIFT
+#undef DDR_PHY_DX6GCR1_RESERVED_15_MASK
 #define DDR_PHY_DX6GCR1_RESERVED_15_DEFVAL                     0x00007FFF
 #define DDR_PHY_DX6GCR1_RESERVED_15_SHIFT                      15
 #define DDR_PHY_DX6GCR1_RESERVED_15_MASK                       0x00008000U
@@ -16433,9 +16433,9 @@
 /*
 * Select the delayed or non-delayed read data strobe #
 */
-#undef DDR_PHY_DX6GCR1_QSNSEL_DEFVAL 
-#undef DDR_PHY_DX6GCR1_QSNSEL_SHIFT 
-#undef DDR_PHY_DX6GCR1_QSNSEL_MASK 
+#undef DDR_PHY_DX6GCR1_QSNSEL_DEFVAL
+#undef DDR_PHY_DX6GCR1_QSNSEL_SHIFT
+#undef DDR_PHY_DX6GCR1_QSNSEL_MASK
 #define DDR_PHY_DX6GCR1_QSNSEL_DEFVAL                          0x00007FFF
 #define DDR_PHY_DX6GCR1_QSNSEL_SHIFT                           14
 #define DDR_PHY_DX6GCR1_QSNSEL_MASK                            0x00004000U
@@ -16443,9 +16443,9 @@
 /*
 * Select the delayed or non-delayed read data strobe
 */
-#undef DDR_PHY_DX6GCR1_QSSEL_DEFVAL 
-#undef DDR_PHY_DX6GCR1_QSSEL_SHIFT 
-#undef DDR_PHY_DX6GCR1_QSSEL_MASK 
+#undef DDR_PHY_DX6GCR1_QSSEL_DEFVAL
+#undef DDR_PHY_DX6GCR1_QSSEL_SHIFT
+#undef DDR_PHY_DX6GCR1_QSSEL_MASK
 #define DDR_PHY_DX6GCR1_QSSEL_DEFVAL                           0x00007FFF
 #define DDR_PHY_DX6GCR1_QSSEL_SHIFT                            13
 #define DDR_PHY_DX6GCR1_QSSEL_MASK                             0x00002000U
@@ -16453,9 +16453,9 @@
 /*
 * Enables Read Data Strobe in a byte lane
 */
-#undef DDR_PHY_DX6GCR1_OEEN_DEFVAL 
-#undef DDR_PHY_DX6GCR1_OEEN_SHIFT 
-#undef DDR_PHY_DX6GCR1_OEEN_MASK 
+#undef DDR_PHY_DX6GCR1_OEEN_DEFVAL
+#undef DDR_PHY_DX6GCR1_OEEN_SHIFT
+#undef DDR_PHY_DX6GCR1_OEEN_MASK
 #define DDR_PHY_DX6GCR1_OEEN_DEFVAL                            0x00007FFF
 #define DDR_PHY_DX6GCR1_OEEN_SHIFT                             12
 #define DDR_PHY_DX6GCR1_OEEN_MASK                              0x00001000U
@@ -16463,9 +16463,9 @@
 /*
 * Enables PDR in a byte lane
 */
-#undef DDR_PHY_DX6GCR1_PDREN_DEFVAL 
-#undef DDR_PHY_DX6GCR1_PDREN_SHIFT 
-#undef DDR_PHY_DX6GCR1_PDREN_MASK 
+#undef DDR_PHY_DX6GCR1_PDREN_DEFVAL
+#undef DDR_PHY_DX6GCR1_PDREN_SHIFT
+#undef DDR_PHY_DX6GCR1_PDREN_MASK
 #define DDR_PHY_DX6GCR1_PDREN_DEFVAL                           0x00007FFF
 #define DDR_PHY_DX6GCR1_PDREN_SHIFT                            11
 #define DDR_PHY_DX6GCR1_PDREN_MASK                             0x00000800U
@@ -16473,9 +16473,9 @@
 /*
 * Enables ODT/TE in a byte lane
 */
-#undef DDR_PHY_DX6GCR1_TEEN_DEFVAL 
-#undef DDR_PHY_DX6GCR1_TEEN_SHIFT 
-#undef DDR_PHY_DX6GCR1_TEEN_MASK 
+#undef DDR_PHY_DX6GCR1_TEEN_DEFVAL
+#undef DDR_PHY_DX6GCR1_TEEN_SHIFT
+#undef DDR_PHY_DX6GCR1_TEEN_MASK
 #define DDR_PHY_DX6GCR1_TEEN_DEFVAL                            0x00007FFF
 #define DDR_PHY_DX6GCR1_TEEN_SHIFT                             10
 #define DDR_PHY_DX6GCR1_TEEN_MASK                              0x00000400U
@@ -16483,9 +16483,9 @@
 /*
 * Enables Write Data strobe in a byte lane
 */
-#undef DDR_PHY_DX6GCR1_DSEN_DEFVAL 
-#undef DDR_PHY_DX6GCR1_DSEN_SHIFT 
-#undef DDR_PHY_DX6GCR1_DSEN_MASK 
+#undef DDR_PHY_DX6GCR1_DSEN_DEFVAL
+#undef DDR_PHY_DX6GCR1_DSEN_SHIFT
+#undef DDR_PHY_DX6GCR1_DSEN_MASK
 #define DDR_PHY_DX6GCR1_DSEN_DEFVAL                            0x00007FFF
 #define DDR_PHY_DX6GCR1_DSEN_SHIFT                             9
 #define DDR_PHY_DX6GCR1_DSEN_MASK                              0x00000200U
@@ -16493,9 +16493,9 @@
 /*
 * Enables DM pin in a byte lane
 */
-#undef DDR_PHY_DX6GCR1_DMEN_DEFVAL 
-#undef DDR_PHY_DX6GCR1_DMEN_SHIFT 
-#undef DDR_PHY_DX6GCR1_DMEN_MASK 
+#undef DDR_PHY_DX6GCR1_DMEN_DEFVAL
+#undef DDR_PHY_DX6GCR1_DMEN_SHIFT
+#undef DDR_PHY_DX6GCR1_DMEN_MASK
 #define DDR_PHY_DX6GCR1_DMEN_DEFVAL                            0x00007FFF
 #define DDR_PHY_DX6GCR1_DMEN_SHIFT                             8
 #define DDR_PHY_DX6GCR1_DMEN_MASK                              0x00000100U
@@ -16503,9 +16503,9 @@
 /*
 * Enables DQ corresponding to each bit in a byte
 */
-#undef DDR_PHY_DX6GCR1_DQEN_DEFVAL 
-#undef DDR_PHY_DX6GCR1_DQEN_SHIFT 
-#undef DDR_PHY_DX6GCR1_DQEN_MASK 
+#undef DDR_PHY_DX6GCR1_DQEN_DEFVAL
+#undef DDR_PHY_DX6GCR1_DQEN_SHIFT
+#undef DDR_PHY_DX6GCR1_DQEN_MASK
 #define DDR_PHY_DX6GCR1_DQEN_DEFVAL                            0x00007FFF
 #define DDR_PHY_DX6GCR1_DQEN_SHIFT                             0
 #define DDR_PHY_DX6GCR1_DQEN_MASK                              0x000000FFU
@@ -16513,9 +16513,9 @@
 /*
 * Byte lane VREF IOM (Used only by D4MU IOs)
 */
-#undef DDR_PHY_DX6GCR4_RESERVED_31_29_DEFVAL 
-#undef DDR_PHY_DX6GCR4_RESERVED_31_29_SHIFT 
-#undef DDR_PHY_DX6GCR4_RESERVED_31_29_MASK 
+#undef DDR_PHY_DX6GCR4_RESERVED_31_29_DEFVAL
+#undef DDR_PHY_DX6GCR4_RESERVED_31_29_SHIFT
+#undef DDR_PHY_DX6GCR4_RESERVED_31_29_MASK
 #define DDR_PHY_DX6GCR4_RESERVED_31_29_DEFVAL                  0x0E00003C
 #define DDR_PHY_DX6GCR4_RESERVED_31_29_SHIFT                   29
 #define DDR_PHY_DX6GCR4_RESERVED_31_29_MASK                    0xE0000000U
@@ -16523,9 +16523,9 @@
 /*
 * Byte Lane VREF Pad Enable
 */
-#undef DDR_PHY_DX6GCR4_DXREFPEN_DEFVAL 
-#undef DDR_PHY_DX6GCR4_DXREFPEN_SHIFT 
-#undef DDR_PHY_DX6GCR4_DXREFPEN_MASK 
+#undef DDR_PHY_DX6GCR4_DXREFPEN_DEFVAL
+#undef DDR_PHY_DX6GCR4_DXREFPEN_SHIFT
+#undef DDR_PHY_DX6GCR4_DXREFPEN_MASK
 #define DDR_PHY_DX6GCR4_DXREFPEN_DEFVAL                        0x0E00003C
 #define DDR_PHY_DX6GCR4_DXREFPEN_SHIFT                         28
 #define DDR_PHY_DX6GCR4_DXREFPEN_MASK                          0x10000000U
@@ -16533,9 +16533,9 @@
 /*
 * Byte Lane Internal VREF Enable
 */
-#undef DDR_PHY_DX6GCR4_DXREFEEN_DEFVAL 
-#undef DDR_PHY_DX6GCR4_DXREFEEN_SHIFT 
-#undef DDR_PHY_DX6GCR4_DXREFEEN_MASK 
+#undef DDR_PHY_DX6GCR4_DXREFEEN_DEFVAL
+#undef DDR_PHY_DX6GCR4_DXREFEEN_SHIFT
+#undef DDR_PHY_DX6GCR4_DXREFEEN_MASK
 #define DDR_PHY_DX6GCR4_DXREFEEN_DEFVAL                        0x0E00003C
 #define DDR_PHY_DX6GCR4_DXREFEEN_SHIFT                         26
 #define DDR_PHY_DX6GCR4_DXREFEEN_MASK                          0x0C000000U
@@ -16543,9 +16543,9 @@
 /*
 * Byte Lane Single-End VREF Enable
 */
-#undef DDR_PHY_DX6GCR4_DXREFSEN_DEFVAL 
-#undef DDR_PHY_DX6GCR4_DXREFSEN_SHIFT 
-#undef DDR_PHY_DX6GCR4_DXREFSEN_MASK 
+#undef DDR_PHY_DX6GCR4_DXREFSEN_DEFVAL
+#undef DDR_PHY_DX6GCR4_DXREFSEN_SHIFT
+#undef DDR_PHY_DX6GCR4_DXREFSEN_MASK
 #define DDR_PHY_DX6GCR4_DXREFSEN_DEFVAL                        0x0E00003C
 #define DDR_PHY_DX6GCR4_DXREFSEN_SHIFT                         25
 #define DDR_PHY_DX6GCR4_DXREFSEN_MASK                          0x02000000U
@@ -16553,9 +16553,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX6GCR4_RESERVED_24_DEFVAL 
-#undef DDR_PHY_DX6GCR4_RESERVED_24_SHIFT 
-#undef DDR_PHY_DX6GCR4_RESERVED_24_MASK 
+#undef DDR_PHY_DX6GCR4_RESERVED_24_DEFVAL
+#undef DDR_PHY_DX6GCR4_RESERVED_24_SHIFT
+#undef DDR_PHY_DX6GCR4_RESERVED_24_MASK
 #define DDR_PHY_DX6GCR4_RESERVED_24_DEFVAL                     0x0E00003C
 #define DDR_PHY_DX6GCR4_RESERVED_24_SHIFT                      24
 #define DDR_PHY_DX6GCR4_RESERVED_24_MASK                       0x01000000U
@@ -16563,9 +16563,9 @@
 /*
 * External VREF generator REFSEL range select
 */
-#undef DDR_PHY_DX6GCR4_DXREFESELRANGE_DEFVAL 
-#undef DDR_PHY_DX6GCR4_DXREFESELRANGE_SHIFT 
-#undef DDR_PHY_DX6GCR4_DXREFESELRANGE_MASK 
+#undef DDR_PHY_DX6GCR4_DXREFESELRANGE_DEFVAL
+#undef DDR_PHY_DX6GCR4_DXREFESELRANGE_SHIFT
+#undef DDR_PHY_DX6GCR4_DXREFESELRANGE_MASK
 #define DDR_PHY_DX6GCR4_DXREFESELRANGE_DEFVAL                  0x0E00003C
 #define DDR_PHY_DX6GCR4_DXREFESELRANGE_SHIFT                   23
 #define DDR_PHY_DX6GCR4_DXREFESELRANGE_MASK                    0x00800000U
@@ -16573,9 +16573,9 @@
 /*
 * Byte Lane External VREF Select
 */
-#undef DDR_PHY_DX6GCR4_DXREFESEL_DEFVAL 
-#undef DDR_PHY_DX6GCR4_DXREFESEL_SHIFT 
-#undef DDR_PHY_DX6GCR4_DXREFESEL_MASK 
+#undef DDR_PHY_DX6GCR4_DXREFESEL_DEFVAL
+#undef DDR_PHY_DX6GCR4_DXREFESEL_SHIFT
+#undef DDR_PHY_DX6GCR4_DXREFESEL_MASK
 #define DDR_PHY_DX6GCR4_DXREFESEL_DEFVAL                       0x0E00003C
 #define DDR_PHY_DX6GCR4_DXREFESEL_SHIFT                        16
 #define DDR_PHY_DX6GCR4_DXREFESEL_MASK                         0x007F0000U
@@ -16583,9 +16583,9 @@
 /*
 * Single ended VREF generator REFSEL range select
 */
-#undef DDR_PHY_DX6GCR4_DXREFSSELRANGE_DEFVAL 
-#undef DDR_PHY_DX6GCR4_DXREFSSELRANGE_SHIFT 
-#undef DDR_PHY_DX6GCR4_DXREFSSELRANGE_MASK 
+#undef DDR_PHY_DX6GCR4_DXREFSSELRANGE_DEFVAL
+#undef DDR_PHY_DX6GCR4_DXREFSSELRANGE_SHIFT
+#undef DDR_PHY_DX6GCR4_DXREFSSELRANGE_MASK
 #define DDR_PHY_DX6GCR4_DXREFSSELRANGE_DEFVAL                  0x0E00003C
 #define DDR_PHY_DX6GCR4_DXREFSSELRANGE_SHIFT                   15
 #define DDR_PHY_DX6GCR4_DXREFSSELRANGE_MASK                    0x00008000U
@@ -16593,9 +16593,9 @@
 /*
 * Byte Lane Single-End VREF Select
 */
-#undef DDR_PHY_DX6GCR4_DXREFSSEL_DEFVAL 
-#undef DDR_PHY_DX6GCR4_DXREFSSEL_SHIFT 
-#undef DDR_PHY_DX6GCR4_DXREFSSEL_MASK 
+#undef DDR_PHY_DX6GCR4_DXREFSSEL_DEFVAL
+#undef DDR_PHY_DX6GCR4_DXREFSSEL_SHIFT
+#undef DDR_PHY_DX6GCR4_DXREFSSEL_MASK
 #define DDR_PHY_DX6GCR4_DXREFSSEL_DEFVAL                       0x0E00003C
 #define DDR_PHY_DX6GCR4_DXREFSSEL_SHIFT                        8
 #define DDR_PHY_DX6GCR4_DXREFSSEL_MASK                         0x00007F00U
@@ -16603,9 +16603,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX6GCR4_RESERVED_7_6_DEFVAL 
-#undef DDR_PHY_DX6GCR4_RESERVED_7_6_SHIFT 
-#undef DDR_PHY_DX6GCR4_RESERVED_7_6_MASK 
+#undef DDR_PHY_DX6GCR4_RESERVED_7_6_DEFVAL
+#undef DDR_PHY_DX6GCR4_RESERVED_7_6_SHIFT
+#undef DDR_PHY_DX6GCR4_RESERVED_7_6_MASK
 #define DDR_PHY_DX6GCR4_RESERVED_7_6_DEFVAL                    0x0E00003C
 #define DDR_PHY_DX6GCR4_RESERVED_7_6_SHIFT                     6
 #define DDR_PHY_DX6GCR4_RESERVED_7_6_MASK                      0x000000C0U
@@ -16613,9 +16613,9 @@
 /*
 * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
 */
-#undef DDR_PHY_DX6GCR4_DXREFIEN_DEFVAL 
-#undef DDR_PHY_DX6GCR4_DXREFIEN_SHIFT 
-#undef DDR_PHY_DX6GCR4_DXREFIEN_MASK 
+#undef DDR_PHY_DX6GCR4_DXREFIEN_DEFVAL
+#undef DDR_PHY_DX6GCR4_DXREFIEN_SHIFT
+#undef DDR_PHY_DX6GCR4_DXREFIEN_MASK
 #define DDR_PHY_DX6GCR4_DXREFIEN_DEFVAL                        0x0E00003C
 #define DDR_PHY_DX6GCR4_DXREFIEN_SHIFT                         2
 #define DDR_PHY_DX6GCR4_DXREFIEN_MASK                          0x0000003CU
@@ -16623,9 +16623,9 @@
 /*
 * VRMON control for DQ IO (Single Ended) buffers of a byte lane.
 */
-#undef DDR_PHY_DX6GCR4_DXREFIMON_DEFVAL 
-#undef DDR_PHY_DX6GCR4_DXREFIMON_SHIFT 
-#undef DDR_PHY_DX6GCR4_DXREFIMON_MASK 
+#undef DDR_PHY_DX6GCR4_DXREFIMON_DEFVAL
+#undef DDR_PHY_DX6GCR4_DXREFIMON_SHIFT
+#undef DDR_PHY_DX6GCR4_DXREFIMON_MASK
 #define DDR_PHY_DX6GCR4_DXREFIMON_DEFVAL                       0x0E00003C
 #define DDR_PHY_DX6GCR4_DXREFIMON_SHIFT                        0
 #define DDR_PHY_DX6GCR4_DXREFIMON_MASK                         0x00000003U
@@ -16633,9 +16633,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX6GCR5_RESERVED_31_DEFVAL 
-#undef DDR_PHY_DX6GCR5_RESERVED_31_SHIFT 
-#undef DDR_PHY_DX6GCR5_RESERVED_31_MASK 
+#undef DDR_PHY_DX6GCR5_RESERVED_31_DEFVAL
+#undef DDR_PHY_DX6GCR5_RESERVED_31_SHIFT
+#undef DDR_PHY_DX6GCR5_RESERVED_31_MASK
 #define DDR_PHY_DX6GCR5_RESERVED_31_DEFVAL                     0x09090909
 #define DDR_PHY_DX6GCR5_RESERVED_31_SHIFT                      31
 #define DDR_PHY_DX6GCR5_RESERVED_31_MASK                       0x80000000U
@@ -16643,9 +16643,9 @@
 /*
 * Byte Lane internal VREF Select for Rank 3
 */
-#undef DDR_PHY_DX6GCR5_DXREFISELR3_DEFVAL 
-#undef DDR_PHY_DX6GCR5_DXREFISELR3_SHIFT 
-#undef DDR_PHY_DX6GCR5_DXREFISELR3_MASK 
+#undef DDR_PHY_DX6GCR5_DXREFISELR3_DEFVAL
+#undef DDR_PHY_DX6GCR5_DXREFISELR3_SHIFT
+#undef DDR_PHY_DX6GCR5_DXREFISELR3_MASK
 #define DDR_PHY_DX6GCR5_DXREFISELR3_DEFVAL                     0x09090909
 #define DDR_PHY_DX6GCR5_DXREFISELR3_SHIFT                      24
 #define DDR_PHY_DX6GCR5_DXREFISELR3_MASK                       0x7F000000U
@@ -16653,9 +16653,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX6GCR5_RESERVED_23_DEFVAL 
-#undef DDR_PHY_DX6GCR5_RESERVED_23_SHIFT 
-#undef DDR_PHY_DX6GCR5_RESERVED_23_MASK 
+#undef DDR_PHY_DX6GCR5_RESERVED_23_DEFVAL
+#undef DDR_PHY_DX6GCR5_RESERVED_23_SHIFT
+#undef DDR_PHY_DX6GCR5_RESERVED_23_MASK
 #define DDR_PHY_DX6GCR5_RESERVED_23_DEFVAL                     0x09090909
 #define DDR_PHY_DX6GCR5_RESERVED_23_SHIFT                      23
 #define DDR_PHY_DX6GCR5_RESERVED_23_MASK                       0x00800000U
@@ -16663,9 +16663,9 @@
 /*
 * Byte Lane internal VREF Select for Rank 2
 */
-#undef DDR_PHY_DX6GCR5_DXREFISELR2_DEFVAL 
-#undef DDR_PHY_DX6GCR5_DXREFISELR2_SHIFT 
-#undef DDR_PHY_DX6GCR5_DXREFISELR2_MASK 
+#undef DDR_PHY_DX6GCR5_DXREFISELR2_DEFVAL
+#undef DDR_PHY_DX6GCR5_DXREFISELR2_SHIFT
+#undef DDR_PHY_DX6GCR5_DXREFISELR2_MASK
 #define DDR_PHY_DX6GCR5_DXREFISELR2_DEFVAL                     0x09090909
 #define DDR_PHY_DX6GCR5_DXREFISELR2_SHIFT                      16
 #define DDR_PHY_DX6GCR5_DXREFISELR2_MASK                       0x007F0000U
@@ -16673,9 +16673,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX6GCR5_RESERVED_15_DEFVAL 
-#undef DDR_PHY_DX6GCR5_RESERVED_15_SHIFT 
-#undef DDR_PHY_DX6GCR5_RESERVED_15_MASK 
+#undef DDR_PHY_DX6GCR5_RESERVED_15_DEFVAL
+#undef DDR_PHY_DX6GCR5_RESERVED_15_SHIFT
+#undef DDR_PHY_DX6GCR5_RESERVED_15_MASK
 #define DDR_PHY_DX6GCR5_RESERVED_15_DEFVAL                     0x09090909
 #define DDR_PHY_DX6GCR5_RESERVED_15_SHIFT                      15
 #define DDR_PHY_DX6GCR5_RESERVED_15_MASK                       0x00008000U
@@ -16683,9 +16683,9 @@
 /*
 * Byte Lane internal VREF Select for Rank 1
 */
-#undef DDR_PHY_DX6GCR5_DXREFISELR1_DEFVAL 
-#undef DDR_PHY_DX6GCR5_DXREFISELR1_SHIFT 
-#undef DDR_PHY_DX6GCR5_DXREFISELR1_MASK 
+#undef DDR_PHY_DX6GCR5_DXREFISELR1_DEFVAL
+#undef DDR_PHY_DX6GCR5_DXREFISELR1_SHIFT
+#undef DDR_PHY_DX6GCR5_DXREFISELR1_MASK
 #define DDR_PHY_DX6GCR5_DXREFISELR1_DEFVAL                     0x09090909
 #define DDR_PHY_DX6GCR5_DXREFISELR1_SHIFT                      8
 #define DDR_PHY_DX6GCR5_DXREFISELR1_MASK                       0x00007F00U
@@ -16693,9 +16693,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX6GCR5_RESERVED_7_DEFVAL 
-#undef DDR_PHY_DX6GCR5_RESERVED_7_SHIFT 
-#undef DDR_PHY_DX6GCR5_RESERVED_7_MASK 
+#undef DDR_PHY_DX6GCR5_RESERVED_7_DEFVAL
+#undef DDR_PHY_DX6GCR5_RESERVED_7_SHIFT
+#undef DDR_PHY_DX6GCR5_RESERVED_7_MASK
 #define DDR_PHY_DX6GCR5_RESERVED_7_DEFVAL                      0x09090909
 #define DDR_PHY_DX6GCR5_RESERVED_7_SHIFT                       7
 #define DDR_PHY_DX6GCR5_RESERVED_7_MASK                        0x00000080U
@@ -16703,9 +16703,9 @@
 /*
 * Byte Lane internal VREF Select for Rank 0
 */
-#undef DDR_PHY_DX6GCR5_DXREFISELR0_DEFVAL 
-#undef DDR_PHY_DX6GCR5_DXREFISELR0_SHIFT 
-#undef DDR_PHY_DX6GCR5_DXREFISELR0_MASK 
+#undef DDR_PHY_DX6GCR5_DXREFISELR0_DEFVAL
+#undef DDR_PHY_DX6GCR5_DXREFISELR0_SHIFT
+#undef DDR_PHY_DX6GCR5_DXREFISELR0_MASK
 #define DDR_PHY_DX6GCR5_DXREFISELR0_DEFVAL                     0x09090909
 #define DDR_PHY_DX6GCR5_DXREFISELR0_SHIFT                      0
 #define DDR_PHY_DX6GCR5_DXREFISELR0_MASK                       0x0000007FU
@@ -16713,9 +16713,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX6GCR6_RESERVED_31_30_DEFVAL 
-#undef DDR_PHY_DX6GCR6_RESERVED_31_30_SHIFT 
-#undef DDR_PHY_DX6GCR6_RESERVED_31_30_MASK 
+#undef DDR_PHY_DX6GCR6_RESERVED_31_30_DEFVAL
+#undef DDR_PHY_DX6GCR6_RESERVED_31_30_SHIFT
+#undef DDR_PHY_DX6GCR6_RESERVED_31_30_MASK
 #define DDR_PHY_DX6GCR6_RESERVED_31_30_DEFVAL                  0x09090909
 #define DDR_PHY_DX6GCR6_RESERVED_31_30_SHIFT                   30
 #define DDR_PHY_DX6GCR6_RESERVED_31_30_MASK                    0xC0000000U
@@ -16723,9 +16723,9 @@
 /*
 * DRAM DQ VREF Select for Rank3
 */
-#undef DDR_PHY_DX6GCR6_DXDQVREFR3_DEFVAL 
-#undef DDR_PHY_DX6GCR6_DXDQVREFR3_SHIFT 
-#undef DDR_PHY_DX6GCR6_DXDQVREFR3_MASK 
+#undef DDR_PHY_DX6GCR6_DXDQVREFR3_DEFVAL
+#undef DDR_PHY_DX6GCR6_DXDQVREFR3_SHIFT
+#undef DDR_PHY_DX6GCR6_DXDQVREFR3_MASK
 #define DDR_PHY_DX6GCR6_DXDQVREFR3_DEFVAL                      0x09090909
 #define DDR_PHY_DX6GCR6_DXDQVREFR3_SHIFT                       24
 #define DDR_PHY_DX6GCR6_DXDQVREFR3_MASK                        0x3F000000U
@@ -16733,9 +16733,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX6GCR6_RESERVED_23_22_DEFVAL 
-#undef DDR_PHY_DX6GCR6_RESERVED_23_22_SHIFT 
-#undef DDR_PHY_DX6GCR6_RESERVED_23_22_MASK 
+#undef DDR_PHY_DX6GCR6_RESERVED_23_22_DEFVAL
+#undef DDR_PHY_DX6GCR6_RESERVED_23_22_SHIFT
+#undef DDR_PHY_DX6GCR6_RESERVED_23_22_MASK
 #define DDR_PHY_DX6GCR6_RESERVED_23_22_DEFVAL                  0x09090909
 #define DDR_PHY_DX6GCR6_RESERVED_23_22_SHIFT                   22
 #define DDR_PHY_DX6GCR6_RESERVED_23_22_MASK                    0x00C00000U
@@ -16743,9 +16743,9 @@
 /*
 * DRAM DQ VREF Select for Rank2
 */
-#undef DDR_PHY_DX6GCR6_DXDQVREFR2_DEFVAL 
-#undef DDR_PHY_DX6GCR6_DXDQVREFR2_SHIFT 
-#undef DDR_PHY_DX6GCR6_DXDQVREFR2_MASK 
+#undef DDR_PHY_DX6GCR6_DXDQVREFR2_DEFVAL
+#undef DDR_PHY_DX6GCR6_DXDQVREFR2_SHIFT
+#undef DDR_PHY_DX6GCR6_DXDQVREFR2_MASK
 #define DDR_PHY_DX6GCR6_DXDQVREFR2_DEFVAL                      0x09090909
 #define DDR_PHY_DX6GCR6_DXDQVREFR2_SHIFT                       16
 #define DDR_PHY_DX6GCR6_DXDQVREFR2_MASK                        0x003F0000U
@@ -16753,9 +16753,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX6GCR6_RESERVED_15_14_DEFVAL 
-#undef DDR_PHY_DX6GCR6_RESERVED_15_14_SHIFT 
-#undef DDR_PHY_DX6GCR6_RESERVED_15_14_MASK 
+#undef DDR_PHY_DX6GCR6_RESERVED_15_14_DEFVAL
+#undef DDR_PHY_DX6GCR6_RESERVED_15_14_SHIFT
+#undef DDR_PHY_DX6GCR6_RESERVED_15_14_MASK
 #define DDR_PHY_DX6GCR6_RESERVED_15_14_DEFVAL                  0x09090909
 #define DDR_PHY_DX6GCR6_RESERVED_15_14_SHIFT                   14
 #define DDR_PHY_DX6GCR6_RESERVED_15_14_MASK                    0x0000C000U
@@ -16763,9 +16763,9 @@
 /*
 * DRAM DQ VREF Select for Rank1
 */
-#undef DDR_PHY_DX6GCR6_DXDQVREFR1_DEFVAL 
-#undef DDR_PHY_DX6GCR6_DXDQVREFR1_SHIFT 
-#undef DDR_PHY_DX6GCR6_DXDQVREFR1_MASK 
+#undef DDR_PHY_DX6GCR6_DXDQVREFR1_DEFVAL
+#undef DDR_PHY_DX6GCR6_DXDQVREFR1_SHIFT
+#undef DDR_PHY_DX6GCR6_DXDQVREFR1_MASK
 #define DDR_PHY_DX6GCR6_DXDQVREFR1_DEFVAL                      0x09090909
 #define DDR_PHY_DX6GCR6_DXDQVREFR1_SHIFT                       8
 #define DDR_PHY_DX6GCR6_DXDQVREFR1_MASK                        0x00003F00U
@@ -16773,9 +16773,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX6GCR6_RESERVED_7_6_DEFVAL 
-#undef DDR_PHY_DX6GCR6_RESERVED_7_6_SHIFT 
-#undef DDR_PHY_DX6GCR6_RESERVED_7_6_MASK 
+#undef DDR_PHY_DX6GCR6_RESERVED_7_6_DEFVAL
+#undef DDR_PHY_DX6GCR6_RESERVED_7_6_SHIFT
+#undef DDR_PHY_DX6GCR6_RESERVED_7_6_MASK
 #define DDR_PHY_DX6GCR6_RESERVED_7_6_DEFVAL                    0x09090909
 #define DDR_PHY_DX6GCR6_RESERVED_7_6_SHIFT                     6
 #define DDR_PHY_DX6GCR6_RESERVED_7_6_MASK                      0x000000C0U
@@ -16783,9 +16783,9 @@
 /*
 * DRAM DQ VREF Select for Rank0
 */
-#undef DDR_PHY_DX6GCR6_DXDQVREFR0_DEFVAL 
-#undef DDR_PHY_DX6GCR6_DXDQVREFR0_SHIFT 
-#undef DDR_PHY_DX6GCR6_DXDQVREFR0_MASK 
+#undef DDR_PHY_DX6GCR6_DXDQVREFR0_DEFVAL
+#undef DDR_PHY_DX6GCR6_DXDQVREFR0_SHIFT
+#undef DDR_PHY_DX6GCR6_DXDQVREFR0_MASK
 #define DDR_PHY_DX6GCR6_DXDQVREFR0_DEFVAL                      0x09090909
 #define DDR_PHY_DX6GCR6_DXDQVREFR0_SHIFT                       0
 #define DDR_PHY_DX6GCR6_DXDQVREFR0_MASK                        0x0000003FU
@@ -16793,9 +16793,9 @@
 /*
 * Calibration Bypass
 */
-#undef DDR_PHY_DX7GCR0_CALBYP_DEFVAL 
-#undef DDR_PHY_DX7GCR0_CALBYP_SHIFT 
-#undef DDR_PHY_DX7GCR0_CALBYP_MASK 
+#undef DDR_PHY_DX7GCR0_CALBYP_DEFVAL
+#undef DDR_PHY_DX7GCR0_CALBYP_SHIFT
+#undef DDR_PHY_DX7GCR0_CALBYP_MASK
 #define DDR_PHY_DX7GCR0_CALBYP_DEFVAL                          0x40200204
 #define DDR_PHY_DX7GCR0_CALBYP_SHIFT                           31
 #define DDR_PHY_DX7GCR0_CALBYP_MASK                            0x80000000U
@@ -16803,9 +16803,9 @@
 /*
 * Master Delay Line Enable
 */
-#undef DDR_PHY_DX7GCR0_MDLEN_DEFVAL 
-#undef DDR_PHY_DX7GCR0_MDLEN_SHIFT 
-#undef DDR_PHY_DX7GCR0_MDLEN_MASK 
+#undef DDR_PHY_DX7GCR0_MDLEN_DEFVAL
+#undef DDR_PHY_DX7GCR0_MDLEN_SHIFT
+#undef DDR_PHY_DX7GCR0_MDLEN_MASK
 #define DDR_PHY_DX7GCR0_MDLEN_DEFVAL                           0x40200204
 #define DDR_PHY_DX7GCR0_MDLEN_SHIFT                            30
 #define DDR_PHY_DX7GCR0_MDLEN_MASK                             0x40000000U
@@ -16813,9 +16813,9 @@
 /*
 * Configurable ODT(TE) Phase Shift
 */
-#undef DDR_PHY_DX7GCR0_CODTSHFT_DEFVAL 
-#undef DDR_PHY_DX7GCR0_CODTSHFT_SHIFT 
-#undef DDR_PHY_DX7GCR0_CODTSHFT_MASK 
+#undef DDR_PHY_DX7GCR0_CODTSHFT_DEFVAL
+#undef DDR_PHY_DX7GCR0_CODTSHFT_SHIFT
+#undef DDR_PHY_DX7GCR0_CODTSHFT_MASK
 #define DDR_PHY_DX7GCR0_CODTSHFT_DEFVAL                        0x40200204
 #define DDR_PHY_DX7GCR0_CODTSHFT_SHIFT                         28
 #define DDR_PHY_DX7GCR0_CODTSHFT_MASK                          0x30000000U
@@ -16823,9 +16823,9 @@
 /*
 * DQS Duty Cycle Correction
 */
-#undef DDR_PHY_DX7GCR0_DQSDCC_DEFVAL 
-#undef DDR_PHY_DX7GCR0_DQSDCC_SHIFT 
-#undef DDR_PHY_DX7GCR0_DQSDCC_MASK 
+#undef DDR_PHY_DX7GCR0_DQSDCC_DEFVAL
+#undef DDR_PHY_DX7GCR0_DQSDCC_SHIFT
+#undef DDR_PHY_DX7GCR0_DQSDCC_MASK
 #define DDR_PHY_DX7GCR0_DQSDCC_DEFVAL                          0x40200204
 #define DDR_PHY_DX7GCR0_DQSDCC_SHIFT                           24
 #define DDR_PHY_DX7GCR0_DQSDCC_MASK                            0x0F000000U
@@ -16834,9 +16834,9 @@
 * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
     *  input for the respective bypte lane of the PHY
 */
-#undef DDR_PHY_DX7GCR0_RDDLY_DEFVAL 
-#undef DDR_PHY_DX7GCR0_RDDLY_SHIFT 
-#undef DDR_PHY_DX7GCR0_RDDLY_MASK 
+#undef DDR_PHY_DX7GCR0_RDDLY_DEFVAL
+#undef DDR_PHY_DX7GCR0_RDDLY_SHIFT
+#undef DDR_PHY_DX7GCR0_RDDLY_MASK
 #define DDR_PHY_DX7GCR0_RDDLY_DEFVAL                           0x40200204
 #define DDR_PHY_DX7GCR0_RDDLY_SHIFT                            20
 #define DDR_PHY_DX7GCR0_RDDLY_MASK                             0x00F00000U
@@ -16844,9 +16844,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX7GCR0_RESERVED_19_14_DEFVAL 
-#undef DDR_PHY_DX7GCR0_RESERVED_19_14_SHIFT 
-#undef DDR_PHY_DX7GCR0_RESERVED_19_14_MASK 
+#undef DDR_PHY_DX7GCR0_RESERVED_19_14_DEFVAL
+#undef DDR_PHY_DX7GCR0_RESERVED_19_14_SHIFT
+#undef DDR_PHY_DX7GCR0_RESERVED_19_14_MASK
 #define DDR_PHY_DX7GCR0_RESERVED_19_14_DEFVAL                  0x40200204
 #define DDR_PHY_DX7GCR0_RESERVED_19_14_SHIFT                   14
 #define DDR_PHY_DX7GCR0_RESERVED_19_14_MASK                    0x000FC000U
@@ -16854,9 +16854,9 @@
 /*
 * DQSNSE Power Down Receiver
 */
-#undef DDR_PHY_DX7GCR0_DQSNSEPDR_DEFVAL 
-#undef DDR_PHY_DX7GCR0_DQSNSEPDR_SHIFT 
-#undef DDR_PHY_DX7GCR0_DQSNSEPDR_MASK 
+#undef DDR_PHY_DX7GCR0_DQSNSEPDR_DEFVAL
+#undef DDR_PHY_DX7GCR0_DQSNSEPDR_SHIFT
+#undef DDR_PHY_DX7GCR0_DQSNSEPDR_MASK
 #define DDR_PHY_DX7GCR0_DQSNSEPDR_DEFVAL                       0x40200204
 #define DDR_PHY_DX7GCR0_DQSNSEPDR_SHIFT                        13
 #define DDR_PHY_DX7GCR0_DQSNSEPDR_MASK                         0x00002000U
@@ -16864,9 +16864,9 @@
 /*
 * DQSSE Power Down Receiver
 */
-#undef DDR_PHY_DX7GCR0_DQSSEPDR_DEFVAL 
-#undef DDR_PHY_DX7GCR0_DQSSEPDR_SHIFT 
-#undef DDR_PHY_DX7GCR0_DQSSEPDR_MASK 
+#undef DDR_PHY_DX7GCR0_DQSSEPDR_DEFVAL
+#undef DDR_PHY_DX7GCR0_DQSSEPDR_SHIFT
+#undef DDR_PHY_DX7GCR0_DQSSEPDR_MASK
 #define DDR_PHY_DX7GCR0_DQSSEPDR_DEFVAL                        0x40200204
 #define DDR_PHY_DX7GCR0_DQSSEPDR_SHIFT                         12
 #define DDR_PHY_DX7GCR0_DQSSEPDR_MASK                          0x00001000U
@@ -16874,9 +16874,9 @@
 /*
 * RTT On Additive Latency
 */
-#undef DDR_PHY_DX7GCR0_RTTOAL_DEFVAL 
-#undef DDR_PHY_DX7GCR0_RTTOAL_SHIFT 
-#undef DDR_PHY_DX7GCR0_RTTOAL_MASK 
+#undef DDR_PHY_DX7GCR0_RTTOAL_DEFVAL
+#undef DDR_PHY_DX7GCR0_RTTOAL_SHIFT
+#undef DDR_PHY_DX7GCR0_RTTOAL_MASK
 #define DDR_PHY_DX7GCR0_RTTOAL_DEFVAL                          0x40200204
 #define DDR_PHY_DX7GCR0_RTTOAL_SHIFT                           11
 #define DDR_PHY_DX7GCR0_RTTOAL_MASK                            0x00000800U
@@ -16884,9 +16884,9 @@
 /*
 * RTT Output Hold
 */
-#undef DDR_PHY_DX7GCR0_RTTOH_DEFVAL 
-#undef DDR_PHY_DX7GCR0_RTTOH_SHIFT 
-#undef DDR_PHY_DX7GCR0_RTTOH_MASK 
+#undef DDR_PHY_DX7GCR0_RTTOH_DEFVAL
+#undef DDR_PHY_DX7GCR0_RTTOH_SHIFT
+#undef DDR_PHY_DX7GCR0_RTTOH_MASK
 #define DDR_PHY_DX7GCR0_RTTOH_DEFVAL                           0x40200204
 #define DDR_PHY_DX7GCR0_RTTOH_SHIFT                            9
 #define DDR_PHY_DX7GCR0_RTTOH_MASK                             0x00000600U
@@ -16894,9 +16894,9 @@
 /*
 * Configurable PDR Phase Shift
 */
-#undef DDR_PHY_DX7GCR0_CPDRSHFT_DEFVAL 
-#undef DDR_PHY_DX7GCR0_CPDRSHFT_SHIFT 
-#undef DDR_PHY_DX7GCR0_CPDRSHFT_MASK 
+#undef DDR_PHY_DX7GCR0_CPDRSHFT_DEFVAL
+#undef DDR_PHY_DX7GCR0_CPDRSHFT_SHIFT
+#undef DDR_PHY_DX7GCR0_CPDRSHFT_MASK
 #define DDR_PHY_DX7GCR0_CPDRSHFT_DEFVAL                        0x40200204
 #define DDR_PHY_DX7GCR0_CPDRSHFT_SHIFT                         7
 #define DDR_PHY_DX7GCR0_CPDRSHFT_MASK                          0x00000180U
@@ -16904,9 +16904,9 @@
 /*
 * DQSR Power Down
 */
-#undef DDR_PHY_DX7GCR0_DQSRPD_DEFVAL 
-#undef DDR_PHY_DX7GCR0_DQSRPD_SHIFT 
-#undef DDR_PHY_DX7GCR0_DQSRPD_MASK 
+#undef DDR_PHY_DX7GCR0_DQSRPD_DEFVAL
+#undef DDR_PHY_DX7GCR0_DQSRPD_SHIFT
+#undef DDR_PHY_DX7GCR0_DQSRPD_MASK
 #define DDR_PHY_DX7GCR0_DQSRPD_DEFVAL                          0x40200204
 #define DDR_PHY_DX7GCR0_DQSRPD_SHIFT                           6
 #define DDR_PHY_DX7GCR0_DQSRPD_MASK                            0x00000040U
@@ -16914,9 +16914,9 @@
 /*
 * DQSG Power Down Receiver
 */
-#undef DDR_PHY_DX7GCR0_DQSGPDR_DEFVAL 
-#undef DDR_PHY_DX7GCR0_DQSGPDR_SHIFT 
-#undef DDR_PHY_DX7GCR0_DQSGPDR_MASK 
+#undef DDR_PHY_DX7GCR0_DQSGPDR_DEFVAL
+#undef DDR_PHY_DX7GCR0_DQSGPDR_SHIFT
+#undef DDR_PHY_DX7GCR0_DQSGPDR_MASK
 #define DDR_PHY_DX7GCR0_DQSGPDR_DEFVAL                         0x40200204
 #define DDR_PHY_DX7GCR0_DQSGPDR_SHIFT                          5
 #define DDR_PHY_DX7GCR0_DQSGPDR_MASK                           0x00000020U
@@ -16924,9 +16924,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX7GCR0_RESERVED_4_DEFVAL 
-#undef DDR_PHY_DX7GCR0_RESERVED_4_SHIFT 
-#undef DDR_PHY_DX7GCR0_RESERVED_4_MASK 
+#undef DDR_PHY_DX7GCR0_RESERVED_4_DEFVAL
+#undef DDR_PHY_DX7GCR0_RESERVED_4_SHIFT
+#undef DDR_PHY_DX7GCR0_RESERVED_4_MASK
 #define DDR_PHY_DX7GCR0_RESERVED_4_DEFVAL                      0x40200204
 #define DDR_PHY_DX7GCR0_RESERVED_4_SHIFT                       4
 #define DDR_PHY_DX7GCR0_RESERVED_4_MASK                        0x00000010U
@@ -16934,9 +16934,9 @@
 /*
 * DQSG On-Die Termination
 */
-#undef DDR_PHY_DX7GCR0_DQSGODT_DEFVAL 
-#undef DDR_PHY_DX7GCR0_DQSGODT_SHIFT 
-#undef DDR_PHY_DX7GCR0_DQSGODT_MASK 
+#undef DDR_PHY_DX7GCR0_DQSGODT_DEFVAL
+#undef DDR_PHY_DX7GCR0_DQSGODT_SHIFT
+#undef DDR_PHY_DX7GCR0_DQSGODT_MASK
 #define DDR_PHY_DX7GCR0_DQSGODT_DEFVAL                         0x40200204
 #define DDR_PHY_DX7GCR0_DQSGODT_SHIFT                          3
 #define DDR_PHY_DX7GCR0_DQSGODT_MASK                           0x00000008U
@@ -16944,9 +16944,9 @@
 /*
 * DQSG Output Enable
 */
-#undef DDR_PHY_DX7GCR0_DQSGOE_DEFVAL 
-#undef DDR_PHY_DX7GCR0_DQSGOE_SHIFT 
-#undef DDR_PHY_DX7GCR0_DQSGOE_MASK 
+#undef DDR_PHY_DX7GCR0_DQSGOE_DEFVAL
+#undef DDR_PHY_DX7GCR0_DQSGOE_SHIFT
+#undef DDR_PHY_DX7GCR0_DQSGOE_MASK
 #define DDR_PHY_DX7GCR0_DQSGOE_DEFVAL                          0x40200204
 #define DDR_PHY_DX7GCR0_DQSGOE_SHIFT                           2
 #define DDR_PHY_DX7GCR0_DQSGOE_MASK                            0x00000004U
@@ -16954,9 +16954,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX7GCR0_RESERVED_1_0_DEFVAL 
-#undef DDR_PHY_DX7GCR0_RESERVED_1_0_SHIFT 
-#undef DDR_PHY_DX7GCR0_RESERVED_1_0_MASK 
+#undef DDR_PHY_DX7GCR0_RESERVED_1_0_DEFVAL
+#undef DDR_PHY_DX7GCR0_RESERVED_1_0_SHIFT
+#undef DDR_PHY_DX7GCR0_RESERVED_1_0_MASK
 #define DDR_PHY_DX7GCR0_RESERVED_1_0_DEFVAL                    0x40200204
 #define DDR_PHY_DX7GCR0_RESERVED_1_0_SHIFT                     0
 #define DDR_PHY_DX7GCR0_RESERVED_1_0_MASK                      0x00000003U
@@ -16964,9 +16964,9 @@
 /*
 * Enables the PDR mode for DQ[7:0]
 */
-#undef DDR_PHY_DX7GCR1_DXPDRMODE_DEFVAL 
-#undef DDR_PHY_DX7GCR1_DXPDRMODE_SHIFT 
-#undef DDR_PHY_DX7GCR1_DXPDRMODE_MASK 
+#undef DDR_PHY_DX7GCR1_DXPDRMODE_DEFVAL
+#undef DDR_PHY_DX7GCR1_DXPDRMODE_SHIFT
+#undef DDR_PHY_DX7GCR1_DXPDRMODE_MASK
 #define DDR_PHY_DX7GCR1_DXPDRMODE_DEFVAL                       0x00007FFF
 #define DDR_PHY_DX7GCR1_DXPDRMODE_SHIFT                        16
 #define DDR_PHY_DX7GCR1_DXPDRMODE_MASK                         0xFFFF0000U
@@ -16974,9 +16974,9 @@
 /*
 * Reserved. Returns zeroes on reads.
 */
-#undef DDR_PHY_DX7GCR1_RESERVED_15_DEFVAL 
-#undef DDR_PHY_DX7GCR1_RESERVED_15_SHIFT 
-#undef DDR_PHY_DX7GCR1_RESERVED_15_MASK 
+#undef DDR_PHY_DX7GCR1_RESERVED_15_DEFVAL
+#undef DDR_PHY_DX7GCR1_RESERVED_15_SHIFT
+#undef DDR_PHY_DX7GCR1_RESERVED_15_MASK
 #define DDR_PHY_DX7GCR1_RESERVED_15_DEFVAL                     0x00007FFF
 #define DDR_PHY_DX7GCR1_RESERVED_15_SHIFT                      15
 #define DDR_PHY_DX7GCR1_RESERVED_15_MASK                       0x00008000U
@@ -16984,9 +16984,9 @@
 /*
 * Select the delayed or non-delayed read data strobe #
 */
-#undef DDR_PHY_DX7GCR1_QSNSEL_DEFVAL 
-#undef DDR_PHY_DX7GCR1_QSNSEL_SHIFT 
-#undef DDR_PHY_DX7GCR1_QSNSEL_MASK 
+#undef DDR_PHY_DX7GCR1_QSNSEL_DEFVAL
+#undef DDR_PHY_DX7GCR1_QSNSEL_SHIFT
+#undef DDR_PHY_DX7GCR1_QSNSEL_MASK
 #define DDR_PHY_DX7GCR1_QSNSEL_DEFVAL                          0x00007FFF
 #define DDR_PHY_DX7GCR1_QSNSEL_SHIFT                           14
 #define DDR_PHY_DX7GCR1_QSNSEL_MASK                            0x00004000U
@@ -16994,9 +16994,9 @@
 /*
 * Select the delayed or non-delayed read data strobe
 */
-#undef DDR_PHY_DX7GCR1_QSSEL_DEFVAL 
-#undef DDR_PHY_DX7GCR1_QSSEL_SHIFT 
-#undef DDR_PHY_DX7GCR1_QSSEL_MASK 
+#undef DDR_PHY_DX7GCR1_QSSEL_DEFVAL
+#undef DDR_PHY_DX7GCR1_QSSEL_SHIFT
+#undef DDR_PHY_DX7GCR1_QSSEL_MASK
 #define DDR_PHY_DX7GCR1_QSSEL_DEFVAL                           0x00007FFF
 #define DDR_PHY_DX7GCR1_QSSEL_SHIFT                            13
 #define DDR_PHY_DX7GCR1_QSSEL_MASK                             0x00002000U
@@ -17004,9 +17004,9 @@
 /*
 * Enables Read Data Strobe in a byte lane
 */
-#undef DDR_PHY_DX7GCR1_OEEN_DEFVAL 
-#undef DDR_PHY_DX7GCR1_OEEN_SHIFT 
-#undef DDR_PHY_DX7GCR1_OEEN_MASK 
+#undef DDR_PHY_DX7GCR1_OEEN_DEFVAL
+#undef DDR_PHY_DX7GCR1_OEEN_SHIFT
+#undef DDR_PHY_DX7GCR1_OEEN_MASK
 #define DDR_PHY_DX7GCR1_OEEN_DEFVAL                            0x00007FFF
 #define DDR_PHY_DX7GCR1_OEEN_SHIFT                             12
 #define DDR_PHY_DX7GCR1_OEEN_MASK                              0x00001000U
@@ -17014,9 +17014,9 @@
 /*
 * Enables PDR in a byte lane
 */
-#undef DDR_PHY_DX7GCR1_PDREN_DEFVAL 
-#undef DDR_PHY_DX7GCR1_PDREN_SHIFT 
-#undef DDR_PHY_DX7GCR1_PDREN_MASK 
+#undef DDR_PHY_DX7GCR1_PDREN_DEFVAL
+#undef DDR_PHY_DX7GCR1_PDREN_SHIFT
+#undef DDR_PHY_DX7GCR1_PDREN_MASK
 #define DDR_PHY_DX7GCR1_PDREN_DEFVAL                           0x00007FFF
 #define DDR_PHY_DX7GCR1_PDREN_SHIFT                            11
 #define DDR_PHY_DX7GCR1_PDREN_MASK                             0x00000800U
@@ -17024,9 +17024,9 @@
 /*
 * Enables ODT/TE in a byte lane
 */
-#undef DDR_PHY_DX7GCR1_TEEN_DEFVAL 
-#undef DDR_PHY_DX7GCR1_TEEN_SHIFT 
-#undef DDR_PHY_DX7GCR1_TEEN_MASK 
+#undef DDR_PHY_DX7GCR1_TEEN_DEFVAL
+#undef DDR_PHY_DX7GCR1_TEEN_SHIFT
+#undef DDR_PHY_DX7GCR1_TEEN_MASK
 #define DDR_PHY_DX7GCR1_TEEN_DEFVAL                            0x00007FFF
 #define DDR_PHY_DX7GCR1_TEEN_SHIFT                             10
 #define DDR_PHY_DX7GCR1_TEEN_MASK                              0x00000400U
@@ -17034,9 +17034,9 @@
 /*
 * Enables Write Data strobe in a byte lane
 */
-#undef DDR_PHY_DX7GCR1_DSEN_DEFVAL 
-#undef DDR_PHY_DX7GCR1_DSEN_SHIFT 
-#undef DDR_PHY_DX7GCR1_DSEN_MASK 
+#undef DDR_PHY_DX7GCR1_DSEN_DEFVAL
+#undef DDR_PHY_DX7GCR1_DSEN_SHIFT
+#undef DDR_PHY_DX7GCR1_DSEN_MASK
 #define DDR_PHY_DX7GCR1_DSEN_DEFVAL                            0x00007FFF
 #define DDR_PHY_DX7GCR1_DSEN_SHIFT                             9
 #define DDR_PHY_DX7GCR1_DSEN_MASK                              0x00000200U
@@ -17044,9 +17044,9 @@
 /*
 * Enables DM pin in a byte lane
 */
-#undef DDR_PHY_DX7GCR1_DMEN_DEFVAL 
-#undef DDR_PHY_DX7GCR1_DMEN_SHIFT 
-#undef DDR_PHY_DX7GCR1_DMEN_MASK 
+#undef DDR_PHY_DX7GCR1_DMEN_DEFVAL
+#undef DDR_PHY_DX7GCR1_DMEN_SHIFT
+#undef DDR_PHY_DX7GCR1_DMEN_MASK
 #define DDR_PHY_DX7GCR1_DMEN_DEFVAL                            0x00007FFF
 #define DDR_PHY_DX7GCR1_DMEN_SHIFT                             8
 #define DDR_PHY_DX7GCR1_DMEN_MASK                              0x00000100U
@@ -17054,9 +17054,9 @@
 /*
 * Enables DQ corresponding to each bit in a byte
 */
-#undef DDR_PHY_DX7GCR1_DQEN_DEFVAL 
-#undef DDR_PHY_DX7GCR1_DQEN_SHIFT 
-#undef DDR_PHY_DX7GCR1_DQEN_MASK 
+#undef DDR_PHY_DX7GCR1_DQEN_DEFVAL
+#undef DDR_PHY_DX7GCR1_DQEN_SHIFT
+#undef DDR_PHY_DX7GCR1_DQEN_MASK
 #define DDR_PHY_DX7GCR1_DQEN_DEFVAL                            0x00007FFF
 #define DDR_PHY_DX7GCR1_DQEN_SHIFT                             0
 #define DDR_PHY_DX7GCR1_DQEN_MASK                              0x000000FFU
@@ -17064,9 +17064,9 @@
 /*
 * Byte lane VREF IOM (Used only by D4MU IOs)
 */
-#undef DDR_PHY_DX7GCR4_RESERVED_31_29_DEFVAL 
-#undef DDR_PHY_DX7GCR4_RESERVED_31_29_SHIFT 
-#undef DDR_PHY_DX7GCR4_RESERVED_31_29_MASK 
+#undef DDR_PHY_DX7GCR4_RESERVED_31_29_DEFVAL
+#undef DDR_PHY_DX7GCR4_RESERVED_31_29_SHIFT
+#undef DDR_PHY_DX7GCR4_RESERVED_31_29_MASK
 #define DDR_PHY_DX7GCR4_RESERVED_31_29_DEFVAL                  0x0E00003C
 #define DDR_PHY_DX7GCR4_RESERVED_31_29_SHIFT                   29
 #define DDR_PHY_DX7GCR4_RESERVED_31_29_MASK                    0xE0000000U
@@ -17074,9 +17074,9 @@
 /*
 * Byte Lane VREF Pad Enable
 */
-#undef DDR_PHY_DX7GCR4_DXREFPEN_DEFVAL 
-#undef DDR_PHY_DX7GCR4_DXREFPEN_SHIFT 
-#undef DDR_PHY_DX7GCR4_DXREFPEN_MASK 
+#undef DDR_PHY_DX7GCR4_DXREFPEN_DEFVAL
+#undef DDR_PHY_DX7GCR4_DXREFPEN_SHIFT
+#undef DDR_PHY_DX7GCR4_DXREFPEN_MASK
 #define DDR_PHY_DX7GCR4_DXREFPEN_DEFVAL                        0x0E00003C
 #define DDR_PHY_DX7GCR4_DXREFPEN_SHIFT                         28
 #define DDR_PHY_DX7GCR4_DXREFPEN_MASK                          0x10000000U
@@ -17084,9 +17084,9 @@
 /*
 * Byte Lane Internal VREF Enable
 */
-#undef DDR_PHY_DX7GCR4_DXREFEEN_DEFVAL 
-#undef DDR_PHY_DX7GCR4_DXREFEEN_SHIFT 
-#undef DDR_PHY_DX7GCR4_DXREFEEN_MASK 
+#undef DDR_PHY_DX7GCR4_DXREFEEN_DEFVAL
+#undef DDR_PHY_DX7GCR4_DXREFEEN_SHIFT
+#undef DDR_PHY_DX7GCR4_DXREFEEN_MASK
 #define DDR_PHY_DX7GCR4_DXREFEEN_DEFVAL                        0x0E00003C
 #define DDR_PHY_DX7GCR4_DXREFEEN_SHIFT                         26
 #define DDR_PHY_DX7GCR4_DXREFEEN_MASK                          0x0C000000U
@@ -17094,9 +17094,9 @@
 /*
 * Byte Lane Single-End VREF Enable
 */
-#undef DDR_PHY_DX7GCR4_DXREFSEN_DEFVAL 
-#undef DDR_PHY_DX7GCR4_DXREFSEN_SHIFT 
-#undef DDR_PHY_DX7GCR4_DXREFSEN_MASK 
+#undef DDR_PHY_DX7GCR4_DXREFSEN_DEFVAL
+#undef DDR_PHY_DX7GCR4_DXREFSEN_SHIFT
+#undef DDR_PHY_DX7GCR4_DXREFSEN_MASK
 #define DDR_PHY_DX7GCR4_DXREFSEN_DEFVAL                        0x0E00003C
 #define DDR_PHY_DX7GCR4_DXREFSEN_SHIFT                         25
 #define DDR_PHY_DX7GCR4_DXREFSEN_MASK                          0x02000000U
@@ -17104,9 +17104,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX7GCR4_RESERVED_24_DEFVAL 
-#undef DDR_PHY_DX7GCR4_RESERVED_24_SHIFT 
-#undef DDR_PHY_DX7GCR4_RESERVED_24_MASK 
+#undef DDR_PHY_DX7GCR4_RESERVED_24_DEFVAL
+#undef DDR_PHY_DX7GCR4_RESERVED_24_SHIFT
+#undef DDR_PHY_DX7GCR4_RESERVED_24_MASK
 #define DDR_PHY_DX7GCR4_RESERVED_24_DEFVAL                     0x0E00003C
 #define DDR_PHY_DX7GCR4_RESERVED_24_SHIFT                      24
 #define DDR_PHY_DX7GCR4_RESERVED_24_MASK                       0x01000000U
@@ -17114,9 +17114,9 @@
 /*
 * External VREF generator REFSEL range select
 */
-#undef DDR_PHY_DX7GCR4_DXREFESELRANGE_DEFVAL 
-#undef DDR_PHY_DX7GCR4_DXREFESELRANGE_SHIFT 
-#undef DDR_PHY_DX7GCR4_DXREFESELRANGE_MASK 
+#undef DDR_PHY_DX7GCR4_DXREFESELRANGE_DEFVAL
+#undef DDR_PHY_DX7GCR4_DXREFESELRANGE_SHIFT
+#undef DDR_PHY_DX7GCR4_DXREFESELRANGE_MASK
 #define DDR_PHY_DX7GCR4_DXREFESELRANGE_DEFVAL                  0x0E00003C
 #define DDR_PHY_DX7GCR4_DXREFESELRANGE_SHIFT                   23
 #define DDR_PHY_DX7GCR4_DXREFESELRANGE_MASK                    0x00800000U
@@ -17124,9 +17124,9 @@
 /*
 * Byte Lane External VREF Select
 */
-#undef DDR_PHY_DX7GCR4_DXREFESEL_DEFVAL 
-#undef DDR_PHY_DX7GCR4_DXREFESEL_SHIFT 
-#undef DDR_PHY_DX7GCR4_DXREFESEL_MASK 
+#undef DDR_PHY_DX7GCR4_DXREFESEL_DEFVAL
+#undef DDR_PHY_DX7GCR4_DXREFESEL_SHIFT
+#undef DDR_PHY_DX7GCR4_DXREFESEL_MASK
 #define DDR_PHY_DX7GCR4_DXREFESEL_DEFVAL                       0x0E00003C
 #define DDR_PHY_DX7GCR4_DXREFESEL_SHIFT                        16
 #define DDR_PHY_DX7GCR4_DXREFESEL_MASK                         0x007F0000U
@@ -17134,9 +17134,9 @@
 /*
 * Single ended VREF generator REFSEL range select
 */
-#undef DDR_PHY_DX7GCR4_DXREFSSELRANGE_DEFVAL 
-#undef DDR_PHY_DX7GCR4_DXREFSSELRANGE_SHIFT 
-#undef DDR_PHY_DX7GCR4_DXREFSSELRANGE_MASK 
+#undef DDR_PHY_DX7GCR4_DXREFSSELRANGE_DEFVAL
+#undef DDR_PHY_DX7GCR4_DXREFSSELRANGE_SHIFT
+#undef DDR_PHY_DX7GCR4_DXREFSSELRANGE_MASK
 #define DDR_PHY_DX7GCR4_DXREFSSELRANGE_DEFVAL                  0x0E00003C
 #define DDR_PHY_DX7GCR4_DXREFSSELRANGE_SHIFT                   15
 #define DDR_PHY_DX7GCR4_DXREFSSELRANGE_MASK                    0x00008000U
@@ -17144,9 +17144,9 @@
 /*
 * Byte Lane Single-End VREF Select
 */
-#undef DDR_PHY_DX7GCR4_DXREFSSEL_DEFVAL 
-#undef DDR_PHY_DX7GCR4_DXREFSSEL_SHIFT 
-#undef DDR_PHY_DX7GCR4_DXREFSSEL_MASK 
+#undef DDR_PHY_DX7GCR4_DXREFSSEL_DEFVAL
+#undef DDR_PHY_DX7GCR4_DXREFSSEL_SHIFT
+#undef DDR_PHY_DX7GCR4_DXREFSSEL_MASK
 #define DDR_PHY_DX7GCR4_DXREFSSEL_DEFVAL                       0x0E00003C
 #define DDR_PHY_DX7GCR4_DXREFSSEL_SHIFT                        8
 #define DDR_PHY_DX7GCR4_DXREFSSEL_MASK                         0x00007F00U
@@ -17154,9 +17154,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX7GCR4_RESERVED_7_6_DEFVAL 
-#undef DDR_PHY_DX7GCR4_RESERVED_7_6_SHIFT 
-#undef DDR_PHY_DX7GCR4_RESERVED_7_6_MASK 
+#undef DDR_PHY_DX7GCR4_RESERVED_7_6_DEFVAL
+#undef DDR_PHY_DX7GCR4_RESERVED_7_6_SHIFT
+#undef DDR_PHY_DX7GCR4_RESERVED_7_6_MASK
 #define DDR_PHY_DX7GCR4_RESERVED_7_6_DEFVAL                    0x0E00003C
 #define DDR_PHY_DX7GCR4_RESERVED_7_6_SHIFT                     6
 #define DDR_PHY_DX7GCR4_RESERVED_7_6_MASK                      0x000000C0U
@@ -17164,9 +17164,9 @@
 /*
 * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
 */
-#undef DDR_PHY_DX7GCR4_DXREFIEN_DEFVAL 
-#undef DDR_PHY_DX7GCR4_DXREFIEN_SHIFT 
-#undef DDR_PHY_DX7GCR4_DXREFIEN_MASK 
+#undef DDR_PHY_DX7GCR4_DXREFIEN_DEFVAL
+#undef DDR_PHY_DX7GCR4_DXREFIEN_SHIFT
+#undef DDR_PHY_DX7GCR4_DXREFIEN_MASK
 #define DDR_PHY_DX7GCR4_DXREFIEN_DEFVAL                        0x0E00003C
 #define DDR_PHY_DX7GCR4_DXREFIEN_SHIFT                         2
 #define DDR_PHY_DX7GCR4_DXREFIEN_MASK                          0x0000003CU
@@ -17174,9 +17174,9 @@
 /*
 * VRMON control for DQ IO (Single Ended) buffers of a byte lane.
 */
-#undef DDR_PHY_DX7GCR4_DXREFIMON_DEFVAL 
-#undef DDR_PHY_DX7GCR4_DXREFIMON_SHIFT 
-#undef DDR_PHY_DX7GCR4_DXREFIMON_MASK 
+#undef DDR_PHY_DX7GCR4_DXREFIMON_DEFVAL
+#undef DDR_PHY_DX7GCR4_DXREFIMON_SHIFT
+#undef DDR_PHY_DX7GCR4_DXREFIMON_MASK
 #define DDR_PHY_DX7GCR4_DXREFIMON_DEFVAL                       0x0E00003C
 #define DDR_PHY_DX7GCR4_DXREFIMON_SHIFT                        0
 #define DDR_PHY_DX7GCR4_DXREFIMON_MASK                         0x00000003U
@@ -17184,9 +17184,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX7GCR5_RESERVED_31_DEFVAL 
-#undef DDR_PHY_DX7GCR5_RESERVED_31_SHIFT 
-#undef DDR_PHY_DX7GCR5_RESERVED_31_MASK 
+#undef DDR_PHY_DX7GCR5_RESERVED_31_DEFVAL
+#undef DDR_PHY_DX7GCR5_RESERVED_31_SHIFT
+#undef DDR_PHY_DX7GCR5_RESERVED_31_MASK
 #define DDR_PHY_DX7GCR5_RESERVED_31_DEFVAL                     0x09090909
 #define DDR_PHY_DX7GCR5_RESERVED_31_SHIFT                      31
 #define DDR_PHY_DX7GCR5_RESERVED_31_MASK                       0x80000000U
@@ -17194,9 +17194,9 @@
 /*
 * Byte Lane internal VREF Select for Rank 3
 */
-#undef DDR_PHY_DX7GCR5_DXREFISELR3_DEFVAL 
-#undef DDR_PHY_DX7GCR5_DXREFISELR3_SHIFT 
-#undef DDR_PHY_DX7GCR5_DXREFISELR3_MASK 
+#undef DDR_PHY_DX7GCR5_DXREFISELR3_DEFVAL
+#undef DDR_PHY_DX7GCR5_DXREFISELR3_SHIFT
+#undef DDR_PHY_DX7GCR5_DXREFISELR3_MASK
 #define DDR_PHY_DX7GCR5_DXREFISELR3_DEFVAL                     0x09090909
 #define DDR_PHY_DX7GCR5_DXREFISELR3_SHIFT                      24
 #define DDR_PHY_DX7GCR5_DXREFISELR3_MASK                       0x7F000000U
@@ -17204,9 +17204,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX7GCR5_RESERVED_23_DEFVAL 
-#undef DDR_PHY_DX7GCR5_RESERVED_23_SHIFT 
-#undef DDR_PHY_DX7GCR5_RESERVED_23_MASK 
+#undef DDR_PHY_DX7GCR5_RESERVED_23_DEFVAL
+#undef DDR_PHY_DX7GCR5_RESERVED_23_SHIFT
+#undef DDR_PHY_DX7GCR5_RESERVED_23_MASK
 #define DDR_PHY_DX7GCR5_RESERVED_23_DEFVAL                     0x09090909
 #define DDR_PHY_DX7GCR5_RESERVED_23_SHIFT                      23
 #define DDR_PHY_DX7GCR5_RESERVED_23_MASK                       0x00800000U
@@ -17214,9 +17214,9 @@
 /*
 * Byte Lane internal VREF Select for Rank 2
 */
-#undef DDR_PHY_DX7GCR5_DXREFISELR2_DEFVAL 
-#undef DDR_PHY_DX7GCR5_DXREFISELR2_SHIFT 
-#undef DDR_PHY_DX7GCR5_DXREFISELR2_MASK 
+#undef DDR_PHY_DX7GCR5_DXREFISELR2_DEFVAL
+#undef DDR_PHY_DX7GCR5_DXREFISELR2_SHIFT
+#undef DDR_PHY_DX7GCR5_DXREFISELR2_MASK
 #define DDR_PHY_DX7GCR5_DXREFISELR2_DEFVAL                     0x09090909
 #define DDR_PHY_DX7GCR5_DXREFISELR2_SHIFT                      16
 #define DDR_PHY_DX7GCR5_DXREFISELR2_MASK                       0x007F0000U
@@ -17224,9 +17224,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX7GCR5_RESERVED_15_DEFVAL 
-#undef DDR_PHY_DX7GCR5_RESERVED_15_SHIFT 
-#undef DDR_PHY_DX7GCR5_RESERVED_15_MASK 
+#undef DDR_PHY_DX7GCR5_RESERVED_15_DEFVAL
+#undef DDR_PHY_DX7GCR5_RESERVED_15_SHIFT
+#undef DDR_PHY_DX7GCR5_RESERVED_15_MASK
 #define DDR_PHY_DX7GCR5_RESERVED_15_DEFVAL                     0x09090909
 #define DDR_PHY_DX7GCR5_RESERVED_15_SHIFT                      15
 #define DDR_PHY_DX7GCR5_RESERVED_15_MASK                       0x00008000U
@@ -17234,9 +17234,9 @@
 /*
 * Byte Lane internal VREF Select for Rank 1
 */
-#undef DDR_PHY_DX7GCR5_DXREFISELR1_DEFVAL 
-#undef DDR_PHY_DX7GCR5_DXREFISELR1_SHIFT 
-#undef DDR_PHY_DX7GCR5_DXREFISELR1_MASK 
+#undef DDR_PHY_DX7GCR5_DXREFISELR1_DEFVAL
+#undef DDR_PHY_DX7GCR5_DXREFISELR1_SHIFT
+#undef DDR_PHY_DX7GCR5_DXREFISELR1_MASK
 #define DDR_PHY_DX7GCR5_DXREFISELR1_DEFVAL                     0x09090909
 #define DDR_PHY_DX7GCR5_DXREFISELR1_SHIFT                      8
 #define DDR_PHY_DX7GCR5_DXREFISELR1_MASK                       0x00007F00U
@@ -17244,9 +17244,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX7GCR5_RESERVED_7_DEFVAL 
-#undef DDR_PHY_DX7GCR5_RESERVED_7_SHIFT 
-#undef DDR_PHY_DX7GCR5_RESERVED_7_MASK 
+#undef DDR_PHY_DX7GCR5_RESERVED_7_DEFVAL
+#undef DDR_PHY_DX7GCR5_RESERVED_7_SHIFT
+#undef DDR_PHY_DX7GCR5_RESERVED_7_MASK
 #define DDR_PHY_DX7GCR5_RESERVED_7_DEFVAL                      0x09090909
 #define DDR_PHY_DX7GCR5_RESERVED_7_SHIFT                       7
 #define DDR_PHY_DX7GCR5_RESERVED_7_MASK                        0x00000080U
@@ -17254,9 +17254,9 @@
 /*
 * Byte Lane internal VREF Select for Rank 0
 */
-#undef DDR_PHY_DX7GCR5_DXREFISELR0_DEFVAL 
-#undef DDR_PHY_DX7GCR5_DXREFISELR0_SHIFT 
-#undef DDR_PHY_DX7GCR5_DXREFISELR0_MASK 
+#undef DDR_PHY_DX7GCR5_DXREFISELR0_DEFVAL
+#undef DDR_PHY_DX7GCR5_DXREFISELR0_SHIFT
+#undef DDR_PHY_DX7GCR5_DXREFISELR0_MASK
 #define DDR_PHY_DX7GCR5_DXREFISELR0_DEFVAL                     0x09090909
 #define DDR_PHY_DX7GCR5_DXREFISELR0_SHIFT                      0
 #define DDR_PHY_DX7GCR5_DXREFISELR0_MASK                       0x0000007FU
@@ -17264,9 +17264,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX7GCR6_RESERVED_31_30_DEFVAL 
-#undef DDR_PHY_DX7GCR6_RESERVED_31_30_SHIFT 
-#undef DDR_PHY_DX7GCR6_RESERVED_31_30_MASK 
+#undef DDR_PHY_DX7GCR6_RESERVED_31_30_DEFVAL
+#undef DDR_PHY_DX7GCR6_RESERVED_31_30_SHIFT
+#undef DDR_PHY_DX7GCR6_RESERVED_31_30_MASK
 #define DDR_PHY_DX7GCR6_RESERVED_31_30_DEFVAL                  0x09090909
 #define DDR_PHY_DX7GCR6_RESERVED_31_30_SHIFT                   30
 #define DDR_PHY_DX7GCR6_RESERVED_31_30_MASK                    0xC0000000U
@@ -17274,9 +17274,9 @@
 /*
 * DRAM DQ VREF Select for Rank3
 */
-#undef DDR_PHY_DX7GCR6_DXDQVREFR3_DEFVAL 
-#undef DDR_PHY_DX7GCR6_DXDQVREFR3_SHIFT 
-#undef DDR_PHY_DX7GCR6_DXDQVREFR3_MASK 
+#undef DDR_PHY_DX7GCR6_DXDQVREFR3_DEFVAL
+#undef DDR_PHY_DX7GCR6_DXDQVREFR3_SHIFT
+#undef DDR_PHY_DX7GCR6_DXDQVREFR3_MASK
 #define DDR_PHY_DX7GCR6_DXDQVREFR3_DEFVAL                      0x09090909
 #define DDR_PHY_DX7GCR6_DXDQVREFR3_SHIFT                       24
 #define DDR_PHY_DX7GCR6_DXDQVREFR3_MASK                        0x3F000000U
@@ -17284,9 +17284,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX7GCR6_RESERVED_23_22_DEFVAL 
-#undef DDR_PHY_DX7GCR6_RESERVED_23_22_SHIFT 
-#undef DDR_PHY_DX7GCR6_RESERVED_23_22_MASK 
+#undef DDR_PHY_DX7GCR6_RESERVED_23_22_DEFVAL
+#undef DDR_PHY_DX7GCR6_RESERVED_23_22_SHIFT
+#undef DDR_PHY_DX7GCR6_RESERVED_23_22_MASK
 #define DDR_PHY_DX7GCR6_RESERVED_23_22_DEFVAL                  0x09090909
 #define DDR_PHY_DX7GCR6_RESERVED_23_22_SHIFT                   22
 #define DDR_PHY_DX7GCR6_RESERVED_23_22_MASK                    0x00C00000U
@@ -17294,9 +17294,9 @@
 /*
 * DRAM DQ VREF Select for Rank2
 */
-#undef DDR_PHY_DX7GCR6_DXDQVREFR2_DEFVAL 
-#undef DDR_PHY_DX7GCR6_DXDQVREFR2_SHIFT 
-#undef DDR_PHY_DX7GCR6_DXDQVREFR2_MASK 
+#undef DDR_PHY_DX7GCR6_DXDQVREFR2_DEFVAL
+#undef DDR_PHY_DX7GCR6_DXDQVREFR2_SHIFT
+#undef DDR_PHY_DX7GCR6_DXDQVREFR2_MASK
 #define DDR_PHY_DX7GCR6_DXDQVREFR2_DEFVAL                      0x09090909
 #define DDR_PHY_DX7GCR6_DXDQVREFR2_SHIFT                       16
 #define DDR_PHY_DX7GCR6_DXDQVREFR2_MASK                        0x003F0000U
@@ -17304,9 +17304,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX7GCR6_RESERVED_15_14_DEFVAL 
-#undef DDR_PHY_DX7GCR6_RESERVED_15_14_SHIFT 
-#undef DDR_PHY_DX7GCR6_RESERVED_15_14_MASK 
+#undef DDR_PHY_DX7GCR6_RESERVED_15_14_DEFVAL
+#undef DDR_PHY_DX7GCR6_RESERVED_15_14_SHIFT
+#undef DDR_PHY_DX7GCR6_RESERVED_15_14_MASK
 #define DDR_PHY_DX7GCR6_RESERVED_15_14_DEFVAL                  0x09090909
 #define DDR_PHY_DX7GCR6_RESERVED_15_14_SHIFT                   14
 #define DDR_PHY_DX7GCR6_RESERVED_15_14_MASK                    0x0000C000U
@@ -17314,9 +17314,9 @@
 /*
 * DRAM DQ VREF Select for Rank1
 */
-#undef DDR_PHY_DX7GCR6_DXDQVREFR1_DEFVAL 
-#undef DDR_PHY_DX7GCR6_DXDQVREFR1_SHIFT 
-#undef DDR_PHY_DX7GCR6_DXDQVREFR1_MASK 
+#undef DDR_PHY_DX7GCR6_DXDQVREFR1_DEFVAL
+#undef DDR_PHY_DX7GCR6_DXDQVREFR1_SHIFT
+#undef DDR_PHY_DX7GCR6_DXDQVREFR1_MASK
 #define DDR_PHY_DX7GCR6_DXDQVREFR1_DEFVAL                      0x09090909
 #define DDR_PHY_DX7GCR6_DXDQVREFR1_SHIFT                       8
 #define DDR_PHY_DX7GCR6_DXDQVREFR1_MASK                        0x00003F00U
@@ -17324,9 +17324,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX7GCR6_RESERVED_7_6_DEFVAL 
-#undef DDR_PHY_DX7GCR6_RESERVED_7_6_SHIFT 
-#undef DDR_PHY_DX7GCR6_RESERVED_7_6_MASK 
+#undef DDR_PHY_DX7GCR6_RESERVED_7_6_DEFVAL
+#undef DDR_PHY_DX7GCR6_RESERVED_7_6_SHIFT
+#undef DDR_PHY_DX7GCR6_RESERVED_7_6_MASK
 #define DDR_PHY_DX7GCR6_RESERVED_7_6_DEFVAL                    0x09090909
 #define DDR_PHY_DX7GCR6_RESERVED_7_6_SHIFT                     6
 #define DDR_PHY_DX7GCR6_RESERVED_7_6_MASK                      0x000000C0U
@@ -17334,9 +17334,9 @@
 /*
 * DRAM DQ VREF Select for Rank0
 */
-#undef DDR_PHY_DX7GCR6_DXDQVREFR0_DEFVAL 
-#undef DDR_PHY_DX7GCR6_DXDQVREFR0_SHIFT 
-#undef DDR_PHY_DX7GCR6_DXDQVREFR0_MASK 
+#undef DDR_PHY_DX7GCR6_DXDQVREFR0_DEFVAL
+#undef DDR_PHY_DX7GCR6_DXDQVREFR0_SHIFT
+#undef DDR_PHY_DX7GCR6_DXDQVREFR0_MASK
 #define DDR_PHY_DX7GCR6_DXDQVREFR0_DEFVAL                      0x09090909
 #define DDR_PHY_DX7GCR6_DXDQVREFR0_SHIFT                       0
 #define DDR_PHY_DX7GCR6_DXDQVREFR0_MASK                        0x0000003FU
@@ -17344,9 +17344,9 @@
 /*
 * Calibration Bypass
 */
-#undef DDR_PHY_DX8GCR0_CALBYP_DEFVAL 
-#undef DDR_PHY_DX8GCR0_CALBYP_SHIFT 
-#undef DDR_PHY_DX8GCR0_CALBYP_MASK 
+#undef DDR_PHY_DX8GCR0_CALBYP_DEFVAL
+#undef DDR_PHY_DX8GCR0_CALBYP_SHIFT
+#undef DDR_PHY_DX8GCR0_CALBYP_MASK
 #define DDR_PHY_DX8GCR0_CALBYP_DEFVAL                          0x40200204
 #define DDR_PHY_DX8GCR0_CALBYP_SHIFT                           31
 #define DDR_PHY_DX8GCR0_CALBYP_MASK                            0x80000000U
@@ -17354,9 +17354,9 @@
 /*
 * Master Delay Line Enable
 */
-#undef DDR_PHY_DX8GCR0_MDLEN_DEFVAL 
-#undef DDR_PHY_DX8GCR0_MDLEN_SHIFT 
-#undef DDR_PHY_DX8GCR0_MDLEN_MASK 
+#undef DDR_PHY_DX8GCR0_MDLEN_DEFVAL
+#undef DDR_PHY_DX8GCR0_MDLEN_SHIFT
+#undef DDR_PHY_DX8GCR0_MDLEN_MASK
 #define DDR_PHY_DX8GCR0_MDLEN_DEFVAL                           0x40200204
 #define DDR_PHY_DX8GCR0_MDLEN_SHIFT                            30
 #define DDR_PHY_DX8GCR0_MDLEN_MASK                             0x40000000U
@@ -17364,9 +17364,9 @@
 /*
 * Configurable ODT(TE) Phase Shift
 */
-#undef DDR_PHY_DX8GCR0_CODTSHFT_DEFVAL 
-#undef DDR_PHY_DX8GCR0_CODTSHFT_SHIFT 
-#undef DDR_PHY_DX8GCR0_CODTSHFT_MASK 
+#undef DDR_PHY_DX8GCR0_CODTSHFT_DEFVAL
+#undef DDR_PHY_DX8GCR0_CODTSHFT_SHIFT
+#undef DDR_PHY_DX8GCR0_CODTSHFT_MASK
 #define DDR_PHY_DX8GCR0_CODTSHFT_DEFVAL                        0x40200204
 #define DDR_PHY_DX8GCR0_CODTSHFT_SHIFT                         28
 #define DDR_PHY_DX8GCR0_CODTSHFT_MASK                          0x30000000U
@@ -17374,9 +17374,9 @@
 /*
 * DQS Duty Cycle Correction
 */
-#undef DDR_PHY_DX8GCR0_DQSDCC_DEFVAL 
-#undef DDR_PHY_DX8GCR0_DQSDCC_SHIFT 
-#undef DDR_PHY_DX8GCR0_DQSDCC_MASK 
+#undef DDR_PHY_DX8GCR0_DQSDCC_DEFVAL
+#undef DDR_PHY_DX8GCR0_DQSDCC_SHIFT
+#undef DDR_PHY_DX8GCR0_DQSDCC_MASK
 #define DDR_PHY_DX8GCR0_DQSDCC_DEFVAL                          0x40200204
 #define DDR_PHY_DX8GCR0_DQSDCC_SHIFT                           24
 #define DDR_PHY_DX8GCR0_DQSDCC_MASK                            0x0F000000U
@@ -17385,9 +17385,9 @@
 * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
     *  input for the respective bypte lane of the PHY
 */
-#undef DDR_PHY_DX8GCR0_RDDLY_DEFVAL 
-#undef DDR_PHY_DX8GCR0_RDDLY_SHIFT 
-#undef DDR_PHY_DX8GCR0_RDDLY_MASK 
+#undef DDR_PHY_DX8GCR0_RDDLY_DEFVAL
+#undef DDR_PHY_DX8GCR0_RDDLY_SHIFT
+#undef DDR_PHY_DX8GCR0_RDDLY_MASK
 #define DDR_PHY_DX8GCR0_RDDLY_DEFVAL                           0x40200204
 #define DDR_PHY_DX8GCR0_RDDLY_SHIFT                            20
 #define DDR_PHY_DX8GCR0_RDDLY_MASK                             0x00F00000U
@@ -17395,9 +17395,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8GCR0_RESERVED_19_14_DEFVAL 
-#undef DDR_PHY_DX8GCR0_RESERVED_19_14_SHIFT 
-#undef DDR_PHY_DX8GCR0_RESERVED_19_14_MASK 
+#undef DDR_PHY_DX8GCR0_RESERVED_19_14_DEFVAL
+#undef DDR_PHY_DX8GCR0_RESERVED_19_14_SHIFT
+#undef DDR_PHY_DX8GCR0_RESERVED_19_14_MASK
 #define DDR_PHY_DX8GCR0_RESERVED_19_14_DEFVAL                  0x40200204
 #define DDR_PHY_DX8GCR0_RESERVED_19_14_SHIFT                   14
 #define DDR_PHY_DX8GCR0_RESERVED_19_14_MASK                    0x000FC000U
@@ -17405,9 +17405,9 @@
 /*
 * DQSNSE Power Down Receiver
 */
-#undef DDR_PHY_DX8GCR0_DQSNSEPDR_DEFVAL 
-#undef DDR_PHY_DX8GCR0_DQSNSEPDR_SHIFT 
-#undef DDR_PHY_DX8GCR0_DQSNSEPDR_MASK 
+#undef DDR_PHY_DX8GCR0_DQSNSEPDR_DEFVAL
+#undef DDR_PHY_DX8GCR0_DQSNSEPDR_SHIFT
+#undef DDR_PHY_DX8GCR0_DQSNSEPDR_MASK
 #define DDR_PHY_DX8GCR0_DQSNSEPDR_DEFVAL                       0x40200204
 #define DDR_PHY_DX8GCR0_DQSNSEPDR_SHIFT                        13
 #define DDR_PHY_DX8GCR0_DQSNSEPDR_MASK                         0x00002000U
@@ -17415,9 +17415,9 @@
 /*
 * DQSSE Power Down Receiver
 */
-#undef DDR_PHY_DX8GCR0_DQSSEPDR_DEFVAL 
-#undef DDR_PHY_DX8GCR0_DQSSEPDR_SHIFT 
-#undef DDR_PHY_DX8GCR0_DQSSEPDR_MASK 
+#undef DDR_PHY_DX8GCR0_DQSSEPDR_DEFVAL
+#undef DDR_PHY_DX8GCR0_DQSSEPDR_SHIFT
+#undef DDR_PHY_DX8GCR0_DQSSEPDR_MASK
 #define DDR_PHY_DX8GCR0_DQSSEPDR_DEFVAL                        0x40200204
 #define DDR_PHY_DX8GCR0_DQSSEPDR_SHIFT                         12
 #define DDR_PHY_DX8GCR0_DQSSEPDR_MASK                          0x00001000U
@@ -17425,9 +17425,9 @@
 /*
 * RTT On Additive Latency
 */
-#undef DDR_PHY_DX8GCR0_RTTOAL_DEFVAL 
-#undef DDR_PHY_DX8GCR0_RTTOAL_SHIFT 
-#undef DDR_PHY_DX8GCR0_RTTOAL_MASK 
+#undef DDR_PHY_DX8GCR0_RTTOAL_DEFVAL
+#undef DDR_PHY_DX8GCR0_RTTOAL_SHIFT
+#undef DDR_PHY_DX8GCR0_RTTOAL_MASK
 #define DDR_PHY_DX8GCR0_RTTOAL_DEFVAL                          0x40200204
 #define DDR_PHY_DX8GCR0_RTTOAL_SHIFT                           11
 #define DDR_PHY_DX8GCR0_RTTOAL_MASK                            0x00000800U
@@ -17435,9 +17435,9 @@
 /*
 * RTT Output Hold
 */
-#undef DDR_PHY_DX8GCR0_RTTOH_DEFVAL 
-#undef DDR_PHY_DX8GCR0_RTTOH_SHIFT 
-#undef DDR_PHY_DX8GCR0_RTTOH_MASK 
+#undef DDR_PHY_DX8GCR0_RTTOH_DEFVAL
+#undef DDR_PHY_DX8GCR0_RTTOH_SHIFT
+#undef DDR_PHY_DX8GCR0_RTTOH_MASK
 #define DDR_PHY_DX8GCR0_RTTOH_DEFVAL                           0x40200204
 #define DDR_PHY_DX8GCR0_RTTOH_SHIFT                            9
 #define DDR_PHY_DX8GCR0_RTTOH_MASK                             0x00000600U
@@ -17445,9 +17445,9 @@
 /*
 * Configurable PDR Phase Shift
 */
-#undef DDR_PHY_DX8GCR0_CPDRSHFT_DEFVAL 
-#undef DDR_PHY_DX8GCR0_CPDRSHFT_SHIFT 
-#undef DDR_PHY_DX8GCR0_CPDRSHFT_MASK 
+#undef DDR_PHY_DX8GCR0_CPDRSHFT_DEFVAL
+#undef DDR_PHY_DX8GCR0_CPDRSHFT_SHIFT
+#undef DDR_PHY_DX8GCR0_CPDRSHFT_MASK
 #define DDR_PHY_DX8GCR0_CPDRSHFT_DEFVAL                        0x40200204
 #define DDR_PHY_DX8GCR0_CPDRSHFT_SHIFT                         7
 #define DDR_PHY_DX8GCR0_CPDRSHFT_MASK                          0x00000180U
@@ -17455,9 +17455,9 @@
 /*
 * DQSR Power Down
 */
-#undef DDR_PHY_DX8GCR0_DQSRPD_DEFVAL 
-#undef DDR_PHY_DX8GCR0_DQSRPD_SHIFT 
-#undef DDR_PHY_DX8GCR0_DQSRPD_MASK 
+#undef DDR_PHY_DX8GCR0_DQSRPD_DEFVAL
+#undef DDR_PHY_DX8GCR0_DQSRPD_SHIFT
+#undef DDR_PHY_DX8GCR0_DQSRPD_MASK
 #define DDR_PHY_DX8GCR0_DQSRPD_DEFVAL                          0x40200204
 #define DDR_PHY_DX8GCR0_DQSRPD_SHIFT                           6
 #define DDR_PHY_DX8GCR0_DQSRPD_MASK                            0x00000040U
@@ -17465,9 +17465,9 @@
 /*
 * DQSG Power Down Receiver
 */
-#undef DDR_PHY_DX8GCR0_DQSGPDR_DEFVAL 
-#undef DDR_PHY_DX8GCR0_DQSGPDR_SHIFT 
-#undef DDR_PHY_DX8GCR0_DQSGPDR_MASK 
+#undef DDR_PHY_DX8GCR0_DQSGPDR_DEFVAL
+#undef DDR_PHY_DX8GCR0_DQSGPDR_SHIFT
+#undef DDR_PHY_DX8GCR0_DQSGPDR_MASK
 #define DDR_PHY_DX8GCR0_DQSGPDR_DEFVAL                         0x40200204
 #define DDR_PHY_DX8GCR0_DQSGPDR_SHIFT                          5
 #define DDR_PHY_DX8GCR0_DQSGPDR_MASK                           0x00000020U
@@ -17475,9 +17475,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8GCR0_RESERVED_4_DEFVAL 
-#undef DDR_PHY_DX8GCR0_RESERVED_4_SHIFT 
-#undef DDR_PHY_DX8GCR0_RESERVED_4_MASK 
+#undef DDR_PHY_DX8GCR0_RESERVED_4_DEFVAL
+#undef DDR_PHY_DX8GCR0_RESERVED_4_SHIFT
+#undef DDR_PHY_DX8GCR0_RESERVED_4_MASK
 #define DDR_PHY_DX8GCR0_RESERVED_4_DEFVAL                      0x40200204
 #define DDR_PHY_DX8GCR0_RESERVED_4_SHIFT                       4
 #define DDR_PHY_DX8GCR0_RESERVED_4_MASK                        0x00000010U
@@ -17485,9 +17485,9 @@
 /*
 * DQSG On-Die Termination
 */
-#undef DDR_PHY_DX8GCR0_DQSGODT_DEFVAL 
-#undef DDR_PHY_DX8GCR0_DQSGODT_SHIFT 
-#undef DDR_PHY_DX8GCR0_DQSGODT_MASK 
+#undef DDR_PHY_DX8GCR0_DQSGODT_DEFVAL
+#undef DDR_PHY_DX8GCR0_DQSGODT_SHIFT
+#undef DDR_PHY_DX8GCR0_DQSGODT_MASK
 #define DDR_PHY_DX8GCR0_DQSGODT_DEFVAL                         0x40200204
 #define DDR_PHY_DX8GCR0_DQSGODT_SHIFT                          3
 #define DDR_PHY_DX8GCR0_DQSGODT_MASK                           0x00000008U
@@ -17495,9 +17495,9 @@
 /*
 * DQSG Output Enable
 */
-#undef DDR_PHY_DX8GCR0_DQSGOE_DEFVAL 
-#undef DDR_PHY_DX8GCR0_DQSGOE_SHIFT 
-#undef DDR_PHY_DX8GCR0_DQSGOE_MASK 
+#undef DDR_PHY_DX8GCR0_DQSGOE_DEFVAL
+#undef DDR_PHY_DX8GCR0_DQSGOE_SHIFT
+#undef DDR_PHY_DX8GCR0_DQSGOE_MASK
 #define DDR_PHY_DX8GCR0_DQSGOE_DEFVAL                          0x40200204
 #define DDR_PHY_DX8GCR0_DQSGOE_SHIFT                           2
 #define DDR_PHY_DX8GCR0_DQSGOE_MASK                            0x00000004U
@@ -17505,9 +17505,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8GCR0_RESERVED_1_0_DEFVAL 
-#undef DDR_PHY_DX8GCR0_RESERVED_1_0_SHIFT 
-#undef DDR_PHY_DX8GCR0_RESERVED_1_0_MASK 
+#undef DDR_PHY_DX8GCR0_RESERVED_1_0_DEFVAL
+#undef DDR_PHY_DX8GCR0_RESERVED_1_0_SHIFT
+#undef DDR_PHY_DX8GCR0_RESERVED_1_0_MASK
 #define DDR_PHY_DX8GCR0_RESERVED_1_0_DEFVAL                    0x40200204
 #define DDR_PHY_DX8GCR0_RESERVED_1_0_SHIFT                     0
 #define DDR_PHY_DX8GCR0_RESERVED_1_0_MASK                      0x00000003U
@@ -17515,9 +17515,9 @@
 /*
 * Enables the PDR mode for DQ[7:0]
 */
-#undef DDR_PHY_DX8GCR1_DXPDRMODE_DEFVAL 
-#undef DDR_PHY_DX8GCR1_DXPDRMODE_SHIFT 
-#undef DDR_PHY_DX8GCR1_DXPDRMODE_MASK 
+#undef DDR_PHY_DX8GCR1_DXPDRMODE_DEFVAL
+#undef DDR_PHY_DX8GCR1_DXPDRMODE_SHIFT
+#undef DDR_PHY_DX8GCR1_DXPDRMODE_MASK
 #define DDR_PHY_DX8GCR1_DXPDRMODE_DEFVAL                       0x00007FFF
 #define DDR_PHY_DX8GCR1_DXPDRMODE_SHIFT                        16
 #define DDR_PHY_DX8GCR1_DXPDRMODE_MASK                         0xFFFF0000U
@@ -17525,9 +17525,9 @@
 /*
 * Reserved. Returns zeroes on reads.
 */
-#undef DDR_PHY_DX8GCR1_RESERVED_15_DEFVAL 
-#undef DDR_PHY_DX8GCR1_RESERVED_15_SHIFT 
-#undef DDR_PHY_DX8GCR1_RESERVED_15_MASK 
+#undef DDR_PHY_DX8GCR1_RESERVED_15_DEFVAL
+#undef DDR_PHY_DX8GCR1_RESERVED_15_SHIFT
+#undef DDR_PHY_DX8GCR1_RESERVED_15_MASK
 #define DDR_PHY_DX8GCR1_RESERVED_15_DEFVAL                     0x00007FFF
 #define DDR_PHY_DX8GCR1_RESERVED_15_SHIFT                      15
 #define DDR_PHY_DX8GCR1_RESERVED_15_MASK                       0x00008000U
@@ -17535,9 +17535,9 @@
 /*
 * Select the delayed or non-delayed read data strobe #
 */
-#undef DDR_PHY_DX8GCR1_QSNSEL_DEFVAL 
-#undef DDR_PHY_DX8GCR1_QSNSEL_SHIFT 
-#undef DDR_PHY_DX8GCR1_QSNSEL_MASK 
+#undef DDR_PHY_DX8GCR1_QSNSEL_DEFVAL
+#undef DDR_PHY_DX8GCR1_QSNSEL_SHIFT
+#undef DDR_PHY_DX8GCR1_QSNSEL_MASK
 #define DDR_PHY_DX8GCR1_QSNSEL_DEFVAL                          0x00007FFF
 #define DDR_PHY_DX8GCR1_QSNSEL_SHIFT                           14
 #define DDR_PHY_DX8GCR1_QSNSEL_MASK                            0x00004000U
@@ -17545,9 +17545,9 @@
 /*
 * Select the delayed or non-delayed read data strobe
 */
-#undef DDR_PHY_DX8GCR1_QSSEL_DEFVAL 
-#undef DDR_PHY_DX8GCR1_QSSEL_SHIFT 
-#undef DDR_PHY_DX8GCR1_QSSEL_MASK 
+#undef DDR_PHY_DX8GCR1_QSSEL_DEFVAL
+#undef DDR_PHY_DX8GCR1_QSSEL_SHIFT
+#undef DDR_PHY_DX8GCR1_QSSEL_MASK
 #define DDR_PHY_DX8GCR1_QSSEL_DEFVAL                           0x00007FFF
 #define DDR_PHY_DX8GCR1_QSSEL_SHIFT                            13
 #define DDR_PHY_DX8GCR1_QSSEL_MASK                             0x00002000U
@@ -17555,9 +17555,9 @@
 /*
 * Enables Read Data Strobe in a byte lane
 */
-#undef DDR_PHY_DX8GCR1_OEEN_DEFVAL 
-#undef DDR_PHY_DX8GCR1_OEEN_SHIFT 
-#undef DDR_PHY_DX8GCR1_OEEN_MASK 
+#undef DDR_PHY_DX8GCR1_OEEN_DEFVAL
+#undef DDR_PHY_DX8GCR1_OEEN_SHIFT
+#undef DDR_PHY_DX8GCR1_OEEN_MASK
 #define DDR_PHY_DX8GCR1_OEEN_DEFVAL                            0x00007FFF
 #define DDR_PHY_DX8GCR1_OEEN_SHIFT                             12
 #define DDR_PHY_DX8GCR1_OEEN_MASK                              0x00001000U
@@ -17565,9 +17565,9 @@
 /*
 * Enables PDR in a byte lane
 */
-#undef DDR_PHY_DX8GCR1_PDREN_DEFVAL 
-#undef DDR_PHY_DX8GCR1_PDREN_SHIFT 
-#undef DDR_PHY_DX8GCR1_PDREN_MASK 
+#undef DDR_PHY_DX8GCR1_PDREN_DEFVAL
+#undef DDR_PHY_DX8GCR1_PDREN_SHIFT
+#undef DDR_PHY_DX8GCR1_PDREN_MASK
 #define DDR_PHY_DX8GCR1_PDREN_DEFVAL                           0x00007FFF
 #define DDR_PHY_DX8GCR1_PDREN_SHIFT                            11
 #define DDR_PHY_DX8GCR1_PDREN_MASK                             0x00000800U
@@ -17575,9 +17575,9 @@
 /*
 * Enables ODT/TE in a byte lane
 */
-#undef DDR_PHY_DX8GCR1_TEEN_DEFVAL 
-#undef DDR_PHY_DX8GCR1_TEEN_SHIFT 
-#undef DDR_PHY_DX8GCR1_TEEN_MASK 
+#undef DDR_PHY_DX8GCR1_TEEN_DEFVAL
+#undef DDR_PHY_DX8GCR1_TEEN_SHIFT
+#undef DDR_PHY_DX8GCR1_TEEN_MASK
 #define DDR_PHY_DX8GCR1_TEEN_DEFVAL                            0x00007FFF
 #define DDR_PHY_DX8GCR1_TEEN_SHIFT                             10
 #define DDR_PHY_DX8GCR1_TEEN_MASK                              0x00000400U
@@ -17585,9 +17585,9 @@
 /*
 * Enables Write Data strobe in a byte lane
 */
-#undef DDR_PHY_DX8GCR1_DSEN_DEFVAL 
-#undef DDR_PHY_DX8GCR1_DSEN_SHIFT 
-#undef DDR_PHY_DX8GCR1_DSEN_MASK 
+#undef DDR_PHY_DX8GCR1_DSEN_DEFVAL
+#undef DDR_PHY_DX8GCR1_DSEN_SHIFT
+#undef DDR_PHY_DX8GCR1_DSEN_MASK
 #define DDR_PHY_DX8GCR1_DSEN_DEFVAL                            0x00007FFF
 #define DDR_PHY_DX8GCR1_DSEN_SHIFT                             9
 #define DDR_PHY_DX8GCR1_DSEN_MASK                              0x00000200U
@@ -17595,9 +17595,9 @@
 /*
 * Enables DM pin in a byte lane
 */
-#undef DDR_PHY_DX8GCR1_DMEN_DEFVAL 
-#undef DDR_PHY_DX8GCR1_DMEN_SHIFT 
-#undef DDR_PHY_DX8GCR1_DMEN_MASK 
+#undef DDR_PHY_DX8GCR1_DMEN_DEFVAL
+#undef DDR_PHY_DX8GCR1_DMEN_SHIFT
+#undef DDR_PHY_DX8GCR1_DMEN_MASK
 #define DDR_PHY_DX8GCR1_DMEN_DEFVAL                            0x00007FFF
 #define DDR_PHY_DX8GCR1_DMEN_SHIFT                             8
 #define DDR_PHY_DX8GCR1_DMEN_MASK                              0x00000100U
@@ -17605,9 +17605,9 @@
 /*
 * Enables DQ corresponding to each bit in a byte
 */
-#undef DDR_PHY_DX8GCR1_DQEN_DEFVAL 
-#undef DDR_PHY_DX8GCR1_DQEN_SHIFT 
-#undef DDR_PHY_DX8GCR1_DQEN_MASK 
+#undef DDR_PHY_DX8GCR1_DQEN_DEFVAL
+#undef DDR_PHY_DX8GCR1_DQEN_SHIFT
+#undef DDR_PHY_DX8GCR1_DQEN_MASK
 #define DDR_PHY_DX8GCR1_DQEN_DEFVAL                            0x00007FFF
 #define DDR_PHY_DX8GCR1_DQEN_SHIFT                             0
 #define DDR_PHY_DX8GCR1_DQEN_MASK                              0x000000FFU
@@ -17615,9 +17615,9 @@
 /*
 * Byte lane VREF IOM (Used only by D4MU IOs)
 */
-#undef DDR_PHY_DX8GCR4_RESERVED_31_29_DEFVAL 
-#undef DDR_PHY_DX8GCR4_RESERVED_31_29_SHIFT 
-#undef DDR_PHY_DX8GCR4_RESERVED_31_29_MASK 
+#undef DDR_PHY_DX8GCR4_RESERVED_31_29_DEFVAL
+#undef DDR_PHY_DX8GCR4_RESERVED_31_29_SHIFT
+#undef DDR_PHY_DX8GCR4_RESERVED_31_29_MASK
 #define DDR_PHY_DX8GCR4_RESERVED_31_29_DEFVAL                  0x0E00003C
 #define DDR_PHY_DX8GCR4_RESERVED_31_29_SHIFT                   29
 #define DDR_PHY_DX8GCR4_RESERVED_31_29_MASK                    0xE0000000U
@@ -17625,9 +17625,9 @@
 /*
 * Byte Lane VREF Pad Enable
 */
-#undef DDR_PHY_DX8GCR4_DXREFPEN_DEFVAL 
-#undef DDR_PHY_DX8GCR4_DXREFPEN_SHIFT 
-#undef DDR_PHY_DX8GCR4_DXREFPEN_MASK 
+#undef DDR_PHY_DX8GCR4_DXREFPEN_DEFVAL
+#undef DDR_PHY_DX8GCR4_DXREFPEN_SHIFT
+#undef DDR_PHY_DX8GCR4_DXREFPEN_MASK
 #define DDR_PHY_DX8GCR4_DXREFPEN_DEFVAL                        0x0E00003C
 #define DDR_PHY_DX8GCR4_DXREFPEN_SHIFT                         28
 #define DDR_PHY_DX8GCR4_DXREFPEN_MASK                          0x10000000U
@@ -17635,9 +17635,9 @@
 /*
 * Byte Lane Internal VREF Enable
 */
-#undef DDR_PHY_DX8GCR4_DXREFEEN_DEFVAL 
-#undef DDR_PHY_DX8GCR4_DXREFEEN_SHIFT 
-#undef DDR_PHY_DX8GCR4_DXREFEEN_MASK 
+#undef DDR_PHY_DX8GCR4_DXREFEEN_DEFVAL
+#undef DDR_PHY_DX8GCR4_DXREFEEN_SHIFT
+#undef DDR_PHY_DX8GCR4_DXREFEEN_MASK
 #define DDR_PHY_DX8GCR4_DXREFEEN_DEFVAL                        0x0E00003C
 #define DDR_PHY_DX8GCR4_DXREFEEN_SHIFT                         26
 #define DDR_PHY_DX8GCR4_DXREFEEN_MASK                          0x0C000000U
@@ -17645,9 +17645,9 @@
 /*
 * Byte Lane Single-End VREF Enable
 */
-#undef DDR_PHY_DX8GCR4_DXREFSEN_DEFVAL 
-#undef DDR_PHY_DX8GCR4_DXREFSEN_SHIFT 
-#undef DDR_PHY_DX8GCR4_DXREFSEN_MASK 
+#undef DDR_PHY_DX8GCR4_DXREFSEN_DEFVAL
+#undef DDR_PHY_DX8GCR4_DXREFSEN_SHIFT
+#undef DDR_PHY_DX8GCR4_DXREFSEN_MASK
 #define DDR_PHY_DX8GCR4_DXREFSEN_DEFVAL                        0x0E00003C
 #define DDR_PHY_DX8GCR4_DXREFSEN_SHIFT                         25
 #define DDR_PHY_DX8GCR4_DXREFSEN_MASK                          0x02000000U
@@ -17655,9 +17655,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX8GCR4_RESERVED_24_DEFVAL 
-#undef DDR_PHY_DX8GCR4_RESERVED_24_SHIFT 
-#undef DDR_PHY_DX8GCR4_RESERVED_24_MASK 
+#undef DDR_PHY_DX8GCR4_RESERVED_24_DEFVAL
+#undef DDR_PHY_DX8GCR4_RESERVED_24_SHIFT
+#undef DDR_PHY_DX8GCR4_RESERVED_24_MASK
 #define DDR_PHY_DX8GCR4_RESERVED_24_DEFVAL                     0x0E00003C
 #define DDR_PHY_DX8GCR4_RESERVED_24_SHIFT                      24
 #define DDR_PHY_DX8GCR4_RESERVED_24_MASK                       0x01000000U
@@ -17665,9 +17665,9 @@
 /*
 * External VREF generator REFSEL range select
 */
-#undef DDR_PHY_DX8GCR4_DXREFESELRANGE_DEFVAL 
-#undef DDR_PHY_DX8GCR4_DXREFESELRANGE_SHIFT 
-#undef DDR_PHY_DX8GCR4_DXREFESELRANGE_MASK 
+#undef DDR_PHY_DX8GCR4_DXREFESELRANGE_DEFVAL
+#undef DDR_PHY_DX8GCR4_DXREFESELRANGE_SHIFT
+#undef DDR_PHY_DX8GCR4_DXREFESELRANGE_MASK
 #define DDR_PHY_DX8GCR4_DXREFESELRANGE_DEFVAL                  0x0E00003C
 #define DDR_PHY_DX8GCR4_DXREFESELRANGE_SHIFT                   23
 #define DDR_PHY_DX8GCR4_DXREFESELRANGE_MASK                    0x00800000U
@@ -17675,9 +17675,9 @@
 /*
 * Byte Lane External VREF Select
 */
-#undef DDR_PHY_DX8GCR4_DXREFESEL_DEFVAL 
-#undef DDR_PHY_DX8GCR4_DXREFESEL_SHIFT 
-#undef DDR_PHY_DX8GCR4_DXREFESEL_MASK 
+#undef DDR_PHY_DX8GCR4_DXREFESEL_DEFVAL
+#undef DDR_PHY_DX8GCR4_DXREFESEL_SHIFT
+#undef DDR_PHY_DX8GCR4_DXREFESEL_MASK
 #define DDR_PHY_DX8GCR4_DXREFESEL_DEFVAL                       0x0E00003C
 #define DDR_PHY_DX8GCR4_DXREFESEL_SHIFT                        16
 #define DDR_PHY_DX8GCR4_DXREFESEL_MASK                         0x007F0000U
@@ -17685,9 +17685,9 @@
 /*
 * Single ended VREF generator REFSEL range select
 */
-#undef DDR_PHY_DX8GCR4_DXREFSSELRANGE_DEFVAL 
-#undef DDR_PHY_DX8GCR4_DXREFSSELRANGE_SHIFT 
-#undef DDR_PHY_DX8GCR4_DXREFSSELRANGE_MASK 
+#undef DDR_PHY_DX8GCR4_DXREFSSELRANGE_DEFVAL
+#undef DDR_PHY_DX8GCR4_DXREFSSELRANGE_SHIFT
+#undef DDR_PHY_DX8GCR4_DXREFSSELRANGE_MASK
 #define DDR_PHY_DX8GCR4_DXREFSSELRANGE_DEFVAL                  0x0E00003C
 #define DDR_PHY_DX8GCR4_DXREFSSELRANGE_SHIFT                   15
 #define DDR_PHY_DX8GCR4_DXREFSSELRANGE_MASK                    0x00008000U
@@ -17695,9 +17695,9 @@
 /*
 * Byte Lane Single-End VREF Select
 */
-#undef DDR_PHY_DX8GCR4_DXREFSSEL_DEFVAL 
-#undef DDR_PHY_DX8GCR4_DXREFSSEL_SHIFT 
-#undef DDR_PHY_DX8GCR4_DXREFSSEL_MASK 
+#undef DDR_PHY_DX8GCR4_DXREFSSEL_DEFVAL
+#undef DDR_PHY_DX8GCR4_DXREFSSEL_SHIFT
+#undef DDR_PHY_DX8GCR4_DXREFSSEL_MASK
 #define DDR_PHY_DX8GCR4_DXREFSSEL_DEFVAL                       0x0E00003C
 #define DDR_PHY_DX8GCR4_DXREFSSEL_SHIFT                        8
 #define DDR_PHY_DX8GCR4_DXREFSSEL_MASK                         0x00007F00U
@@ -17705,9 +17705,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX8GCR4_RESERVED_7_6_DEFVAL 
-#undef DDR_PHY_DX8GCR4_RESERVED_7_6_SHIFT 
-#undef DDR_PHY_DX8GCR4_RESERVED_7_6_MASK 
+#undef DDR_PHY_DX8GCR4_RESERVED_7_6_DEFVAL
+#undef DDR_PHY_DX8GCR4_RESERVED_7_6_SHIFT
+#undef DDR_PHY_DX8GCR4_RESERVED_7_6_MASK
 #define DDR_PHY_DX8GCR4_RESERVED_7_6_DEFVAL                    0x0E00003C
 #define DDR_PHY_DX8GCR4_RESERVED_7_6_SHIFT                     6
 #define DDR_PHY_DX8GCR4_RESERVED_7_6_MASK                      0x000000C0U
@@ -17715,9 +17715,9 @@
 /*
 * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
 */
-#undef DDR_PHY_DX8GCR4_DXREFIEN_DEFVAL 
-#undef DDR_PHY_DX8GCR4_DXREFIEN_SHIFT 
-#undef DDR_PHY_DX8GCR4_DXREFIEN_MASK 
+#undef DDR_PHY_DX8GCR4_DXREFIEN_DEFVAL
+#undef DDR_PHY_DX8GCR4_DXREFIEN_SHIFT
+#undef DDR_PHY_DX8GCR4_DXREFIEN_MASK
 #define DDR_PHY_DX8GCR4_DXREFIEN_DEFVAL                        0x0E00003C
 #define DDR_PHY_DX8GCR4_DXREFIEN_SHIFT                         2
 #define DDR_PHY_DX8GCR4_DXREFIEN_MASK                          0x0000003CU
@@ -17725,9 +17725,9 @@
 /*
 * VRMON control for DQ IO (Single Ended) buffers of a byte lane.
 */
-#undef DDR_PHY_DX8GCR4_DXREFIMON_DEFVAL 
-#undef DDR_PHY_DX8GCR4_DXREFIMON_SHIFT 
-#undef DDR_PHY_DX8GCR4_DXREFIMON_MASK 
+#undef DDR_PHY_DX8GCR4_DXREFIMON_DEFVAL
+#undef DDR_PHY_DX8GCR4_DXREFIMON_SHIFT
+#undef DDR_PHY_DX8GCR4_DXREFIMON_MASK
 #define DDR_PHY_DX8GCR4_DXREFIMON_DEFVAL                       0x0E00003C
 #define DDR_PHY_DX8GCR4_DXREFIMON_SHIFT                        0
 #define DDR_PHY_DX8GCR4_DXREFIMON_MASK                         0x00000003U
@@ -17735,9 +17735,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX8GCR5_RESERVED_31_DEFVAL 
-#undef DDR_PHY_DX8GCR5_RESERVED_31_SHIFT 
-#undef DDR_PHY_DX8GCR5_RESERVED_31_MASK 
+#undef DDR_PHY_DX8GCR5_RESERVED_31_DEFVAL
+#undef DDR_PHY_DX8GCR5_RESERVED_31_SHIFT
+#undef DDR_PHY_DX8GCR5_RESERVED_31_MASK
 #define DDR_PHY_DX8GCR5_RESERVED_31_DEFVAL                     0x09090909
 #define DDR_PHY_DX8GCR5_RESERVED_31_SHIFT                      31
 #define DDR_PHY_DX8GCR5_RESERVED_31_MASK                       0x80000000U
@@ -17745,9 +17745,9 @@
 /*
 * Byte Lane internal VREF Select for Rank 3
 */
-#undef DDR_PHY_DX8GCR5_DXREFISELR3_DEFVAL 
-#undef DDR_PHY_DX8GCR5_DXREFISELR3_SHIFT 
-#undef DDR_PHY_DX8GCR5_DXREFISELR3_MASK 
+#undef DDR_PHY_DX8GCR5_DXREFISELR3_DEFVAL
+#undef DDR_PHY_DX8GCR5_DXREFISELR3_SHIFT
+#undef DDR_PHY_DX8GCR5_DXREFISELR3_MASK
 #define DDR_PHY_DX8GCR5_DXREFISELR3_DEFVAL                     0x09090909
 #define DDR_PHY_DX8GCR5_DXREFISELR3_SHIFT                      24
 #define DDR_PHY_DX8GCR5_DXREFISELR3_MASK                       0x7F000000U
@@ -17755,9 +17755,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX8GCR5_RESERVED_23_DEFVAL 
-#undef DDR_PHY_DX8GCR5_RESERVED_23_SHIFT 
-#undef DDR_PHY_DX8GCR5_RESERVED_23_MASK 
+#undef DDR_PHY_DX8GCR5_RESERVED_23_DEFVAL
+#undef DDR_PHY_DX8GCR5_RESERVED_23_SHIFT
+#undef DDR_PHY_DX8GCR5_RESERVED_23_MASK
 #define DDR_PHY_DX8GCR5_RESERVED_23_DEFVAL                     0x09090909
 #define DDR_PHY_DX8GCR5_RESERVED_23_SHIFT                      23
 #define DDR_PHY_DX8GCR5_RESERVED_23_MASK                       0x00800000U
@@ -17765,9 +17765,9 @@
 /*
 * Byte Lane internal VREF Select for Rank 2
 */
-#undef DDR_PHY_DX8GCR5_DXREFISELR2_DEFVAL 
-#undef DDR_PHY_DX8GCR5_DXREFISELR2_SHIFT 
-#undef DDR_PHY_DX8GCR5_DXREFISELR2_MASK 
+#undef DDR_PHY_DX8GCR5_DXREFISELR2_DEFVAL
+#undef DDR_PHY_DX8GCR5_DXREFISELR2_SHIFT
+#undef DDR_PHY_DX8GCR5_DXREFISELR2_MASK
 #define DDR_PHY_DX8GCR5_DXREFISELR2_DEFVAL                     0x09090909
 #define DDR_PHY_DX8GCR5_DXREFISELR2_SHIFT                      16
 #define DDR_PHY_DX8GCR5_DXREFISELR2_MASK                       0x007F0000U
@@ -17775,9 +17775,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX8GCR5_RESERVED_15_DEFVAL 
-#undef DDR_PHY_DX8GCR5_RESERVED_15_SHIFT 
-#undef DDR_PHY_DX8GCR5_RESERVED_15_MASK 
+#undef DDR_PHY_DX8GCR5_RESERVED_15_DEFVAL
+#undef DDR_PHY_DX8GCR5_RESERVED_15_SHIFT
+#undef DDR_PHY_DX8GCR5_RESERVED_15_MASK
 #define DDR_PHY_DX8GCR5_RESERVED_15_DEFVAL                     0x09090909
 #define DDR_PHY_DX8GCR5_RESERVED_15_SHIFT                      15
 #define DDR_PHY_DX8GCR5_RESERVED_15_MASK                       0x00008000U
@@ -17785,9 +17785,9 @@
 /*
 * Byte Lane internal VREF Select for Rank 1
 */
-#undef DDR_PHY_DX8GCR5_DXREFISELR1_DEFVAL 
-#undef DDR_PHY_DX8GCR5_DXREFISELR1_SHIFT 
-#undef DDR_PHY_DX8GCR5_DXREFISELR1_MASK 
+#undef DDR_PHY_DX8GCR5_DXREFISELR1_DEFVAL
+#undef DDR_PHY_DX8GCR5_DXREFISELR1_SHIFT
+#undef DDR_PHY_DX8GCR5_DXREFISELR1_MASK
 #define DDR_PHY_DX8GCR5_DXREFISELR1_DEFVAL                     0x09090909
 #define DDR_PHY_DX8GCR5_DXREFISELR1_SHIFT                      8
 #define DDR_PHY_DX8GCR5_DXREFISELR1_MASK                       0x00007F00U
@@ -17795,9 +17795,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX8GCR5_RESERVED_7_DEFVAL 
-#undef DDR_PHY_DX8GCR5_RESERVED_7_SHIFT 
-#undef DDR_PHY_DX8GCR5_RESERVED_7_MASK 
+#undef DDR_PHY_DX8GCR5_RESERVED_7_DEFVAL
+#undef DDR_PHY_DX8GCR5_RESERVED_7_SHIFT
+#undef DDR_PHY_DX8GCR5_RESERVED_7_MASK
 #define DDR_PHY_DX8GCR5_RESERVED_7_DEFVAL                      0x09090909
 #define DDR_PHY_DX8GCR5_RESERVED_7_SHIFT                       7
 #define DDR_PHY_DX8GCR5_RESERVED_7_MASK                        0x00000080U
@@ -17805,9 +17805,9 @@
 /*
 * Byte Lane internal VREF Select for Rank 0
 */
-#undef DDR_PHY_DX8GCR5_DXREFISELR0_DEFVAL 
-#undef DDR_PHY_DX8GCR5_DXREFISELR0_SHIFT 
-#undef DDR_PHY_DX8GCR5_DXREFISELR0_MASK 
+#undef DDR_PHY_DX8GCR5_DXREFISELR0_DEFVAL
+#undef DDR_PHY_DX8GCR5_DXREFISELR0_SHIFT
+#undef DDR_PHY_DX8GCR5_DXREFISELR0_MASK
 #define DDR_PHY_DX8GCR5_DXREFISELR0_DEFVAL                     0x09090909
 #define DDR_PHY_DX8GCR5_DXREFISELR0_SHIFT                      0
 #define DDR_PHY_DX8GCR5_DXREFISELR0_MASK                       0x0000007FU
@@ -17815,9 +17815,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX8GCR6_RESERVED_31_30_DEFVAL 
-#undef DDR_PHY_DX8GCR6_RESERVED_31_30_SHIFT 
-#undef DDR_PHY_DX8GCR6_RESERVED_31_30_MASK 
+#undef DDR_PHY_DX8GCR6_RESERVED_31_30_DEFVAL
+#undef DDR_PHY_DX8GCR6_RESERVED_31_30_SHIFT
+#undef DDR_PHY_DX8GCR6_RESERVED_31_30_MASK
 #define DDR_PHY_DX8GCR6_RESERVED_31_30_DEFVAL                  0x09090909
 #define DDR_PHY_DX8GCR6_RESERVED_31_30_SHIFT                   30
 #define DDR_PHY_DX8GCR6_RESERVED_31_30_MASK                    0xC0000000U
@@ -17825,9 +17825,9 @@
 /*
 * DRAM DQ VREF Select for Rank3
 */
-#undef DDR_PHY_DX8GCR6_DXDQVREFR3_DEFVAL 
-#undef DDR_PHY_DX8GCR6_DXDQVREFR3_SHIFT 
-#undef DDR_PHY_DX8GCR6_DXDQVREFR3_MASK 
+#undef DDR_PHY_DX8GCR6_DXDQVREFR3_DEFVAL
+#undef DDR_PHY_DX8GCR6_DXDQVREFR3_SHIFT
+#undef DDR_PHY_DX8GCR6_DXDQVREFR3_MASK
 #define DDR_PHY_DX8GCR6_DXDQVREFR3_DEFVAL                      0x09090909
 #define DDR_PHY_DX8GCR6_DXDQVREFR3_SHIFT                       24
 #define DDR_PHY_DX8GCR6_DXDQVREFR3_MASK                        0x3F000000U
@@ -17835,9 +17835,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX8GCR6_RESERVED_23_22_DEFVAL 
-#undef DDR_PHY_DX8GCR6_RESERVED_23_22_SHIFT 
-#undef DDR_PHY_DX8GCR6_RESERVED_23_22_MASK 
+#undef DDR_PHY_DX8GCR6_RESERVED_23_22_DEFVAL
+#undef DDR_PHY_DX8GCR6_RESERVED_23_22_SHIFT
+#undef DDR_PHY_DX8GCR6_RESERVED_23_22_MASK
 #define DDR_PHY_DX8GCR6_RESERVED_23_22_DEFVAL                  0x09090909
 #define DDR_PHY_DX8GCR6_RESERVED_23_22_SHIFT                   22
 #define DDR_PHY_DX8GCR6_RESERVED_23_22_MASK                    0x00C00000U
@@ -17845,9 +17845,9 @@
 /*
 * DRAM DQ VREF Select for Rank2
 */
-#undef DDR_PHY_DX8GCR6_DXDQVREFR2_DEFVAL 
-#undef DDR_PHY_DX8GCR6_DXDQVREFR2_SHIFT 
-#undef DDR_PHY_DX8GCR6_DXDQVREFR2_MASK 
+#undef DDR_PHY_DX8GCR6_DXDQVREFR2_DEFVAL
+#undef DDR_PHY_DX8GCR6_DXDQVREFR2_SHIFT
+#undef DDR_PHY_DX8GCR6_DXDQVREFR2_MASK
 #define DDR_PHY_DX8GCR6_DXDQVREFR2_DEFVAL                      0x09090909
 #define DDR_PHY_DX8GCR6_DXDQVREFR2_SHIFT                       16
 #define DDR_PHY_DX8GCR6_DXDQVREFR2_MASK                        0x003F0000U
@@ -17855,9 +17855,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX8GCR6_RESERVED_15_14_DEFVAL 
-#undef DDR_PHY_DX8GCR6_RESERVED_15_14_SHIFT 
-#undef DDR_PHY_DX8GCR6_RESERVED_15_14_MASK 
+#undef DDR_PHY_DX8GCR6_RESERVED_15_14_DEFVAL
+#undef DDR_PHY_DX8GCR6_RESERVED_15_14_SHIFT
+#undef DDR_PHY_DX8GCR6_RESERVED_15_14_MASK
 #define DDR_PHY_DX8GCR6_RESERVED_15_14_DEFVAL                  0x09090909
 #define DDR_PHY_DX8GCR6_RESERVED_15_14_SHIFT                   14
 #define DDR_PHY_DX8GCR6_RESERVED_15_14_MASK                    0x0000C000U
@@ -17865,9 +17865,9 @@
 /*
 * DRAM DQ VREF Select for Rank1
 */
-#undef DDR_PHY_DX8GCR6_DXDQVREFR1_DEFVAL 
-#undef DDR_PHY_DX8GCR6_DXDQVREFR1_SHIFT 
-#undef DDR_PHY_DX8GCR6_DXDQVREFR1_MASK 
+#undef DDR_PHY_DX8GCR6_DXDQVREFR1_DEFVAL
+#undef DDR_PHY_DX8GCR6_DXDQVREFR1_SHIFT
+#undef DDR_PHY_DX8GCR6_DXDQVREFR1_MASK
 #define DDR_PHY_DX8GCR6_DXDQVREFR1_DEFVAL                      0x09090909
 #define DDR_PHY_DX8GCR6_DXDQVREFR1_SHIFT                       8
 #define DDR_PHY_DX8GCR6_DXDQVREFR1_MASK                        0x00003F00U
@@ -17875,9 +17875,9 @@
 /*
 * Reserved. Returns zeros on reads.
 */
-#undef DDR_PHY_DX8GCR6_RESERVED_7_6_DEFVAL 
-#undef DDR_PHY_DX8GCR6_RESERVED_7_6_SHIFT 
-#undef DDR_PHY_DX8GCR6_RESERVED_7_6_MASK 
+#undef DDR_PHY_DX8GCR6_RESERVED_7_6_DEFVAL
+#undef DDR_PHY_DX8GCR6_RESERVED_7_6_SHIFT
+#undef DDR_PHY_DX8GCR6_RESERVED_7_6_MASK
 #define DDR_PHY_DX8GCR6_RESERVED_7_6_DEFVAL                    0x09090909
 #define DDR_PHY_DX8GCR6_RESERVED_7_6_SHIFT                     6
 #define DDR_PHY_DX8GCR6_RESERVED_7_6_MASK                      0x000000C0U
@@ -17885,9 +17885,9 @@
 /*
 * DRAM DQ VREF Select for Rank0
 */
-#undef DDR_PHY_DX8GCR6_DXDQVREFR0_DEFVAL 
-#undef DDR_PHY_DX8GCR6_DXDQVREFR0_SHIFT 
-#undef DDR_PHY_DX8GCR6_DXDQVREFR0_MASK 
+#undef DDR_PHY_DX8GCR6_DXDQVREFR0_DEFVAL
+#undef DDR_PHY_DX8GCR6_DXDQVREFR0_SHIFT
+#undef DDR_PHY_DX8GCR6_DXDQVREFR0_MASK
 #define DDR_PHY_DX8GCR6_DXDQVREFR0_DEFVAL                      0x09090909
 #define DDR_PHY_DX8GCR6_DXDQVREFR0_SHIFT                       0
 #define DDR_PHY_DX8GCR6_DXDQVREFR0_MASK                        0x0000003FU
@@ -17895,9 +17895,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SL0OSC_RESERVED_31_30_DEFVAL 
-#undef DDR_PHY_DX8SL0OSC_RESERVED_31_30_SHIFT 
-#undef DDR_PHY_DX8SL0OSC_RESERVED_31_30_MASK 
+#undef DDR_PHY_DX8SL0OSC_RESERVED_31_30_DEFVAL
+#undef DDR_PHY_DX8SL0OSC_RESERVED_31_30_SHIFT
+#undef DDR_PHY_DX8SL0OSC_RESERVED_31_30_MASK
 #define DDR_PHY_DX8SL0OSC_RESERVED_31_30_DEFVAL                0x00019FFE
 #define DDR_PHY_DX8SL0OSC_RESERVED_31_30_SHIFT                 30
 #define DDR_PHY_DX8SL0OSC_RESERVED_31_30_MASK                  0xC0000000U
@@ -17905,9 +17905,9 @@
 /*
 * Enable Clock Gating for DX ddr_clk
 */
-#undef DDR_PHY_DX8SL0OSC_GATEDXRDCLK_DEFVAL 
-#undef DDR_PHY_DX8SL0OSC_GATEDXRDCLK_SHIFT 
-#undef DDR_PHY_DX8SL0OSC_GATEDXRDCLK_MASK 
+#undef DDR_PHY_DX8SL0OSC_GATEDXRDCLK_DEFVAL
+#undef DDR_PHY_DX8SL0OSC_GATEDXRDCLK_SHIFT
+#undef DDR_PHY_DX8SL0OSC_GATEDXRDCLK_MASK
 #define DDR_PHY_DX8SL0OSC_GATEDXRDCLK_DEFVAL                   0x00019FFE
 #define DDR_PHY_DX8SL0OSC_GATEDXRDCLK_SHIFT                    28
 #define DDR_PHY_DX8SL0OSC_GATEDXRDCLK_MASK                     0x30000000U
@@ -17915,9 +17915,9 @@
 /*
 * Enable Clock Gating for DX ctl_rd_clk
 */
-#undef DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_DEFVAL 
-#undef DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_SHIFT 
-#undef DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_MASK 
+#undef DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_DEFVAL
+#undef DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_SHIFT
+#undef DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_MASK
 #define DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_DEFVAL                  0x00019FFE
 #define DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_SHIFT                   26
 #define DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_MASK                    0x0C000000U
@@ -17925,9 +17925,9 @@
 /*
 * Enable Clock Gating for DX ctl_clk
 */
-#undef DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_DEFVAL 
-#undef DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_SHIFT 
-#undef DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_MASK 
+#undef DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_DEFVAL
+#undef DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_SHIFT
+#undef DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_MASK
 #define DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_DEFVAL                  0x00019FFE
 #define DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_SHIFT                   24
 #define DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_MASK                    0x03000000U
@@ -17936,9 +17936,9 @@
 * Selects the level to which clocks will be stalled when clock gating is e
     * nabled.
 */
-#undef DDR_PHY_DX8SL0OSC_CLKLEVEL_DEFVAL 
-#undef DDR_PHY_DX8SL0OSC_CLKLEVEL_SHIFT 
-#undef DDR_PHY_DX8SL0OSC_CLKLEVEL_MASK 
+#undef DDR_PHY_DX8SL0OSC_CLKLEVEL_DEFVAL
+#undef DDR_PHY_DX8SL0OSC_CLKLEVEL_SHIFT
+#undef DDR_PHY_DX8SL0OSC_CLKLEVEL_MASK
 #define DDR_PHY_DX8SL0OSC_CLKLEVEL_DEFVAL                      0x00019FFE
 #define DDR_PHY_DX8SL0OSC_CLKLEVEL_SHIFT                       22
 #define DDR_PHY_DX8SL0OSC_CLKLEVEL_MASK                        0x00C00000U
@@ -17946,9 +17946,9 @@
 /*
 * Loopback Mode
 */
-#undef DDR_PHY_DX8SL0OSC_LBMODE_DEFVAL 
-#undef DDR_PHY_DX8SL0OSC_LBMODE_SHIFT 
-#undef DDR_PHY_DX8SL0OSC_LBMODE_MASK 
+#undef DDR_PHY_DX8SL0OSC_LBMODE_DEFVAL
+#undef DDR_PHY_DX8SL0OSC_LBMODE_SHIFT
+#undef DDR_PHY_DX8SL0OSC_LBMODE_MASK
 #define DDR_PHY_DX8SL0OSC_LBMODE_DEFVAL                        0x00019FFE
 #define DDR_PHY_DX8SL0OSC_LBMODE_SHIFT                         21
 #define DDR_PHY_DX8SL0OSC_LBMODE_MASK                          0x00200000U
@@ -17956,9 +17956,9 @@
 /*
 * Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
 */
-#undef DDR_PHY_DX8SL0OSC_LBGSDQS_DEFVAL 
-#undef DDR_PHY_DX8SL0OSC_LBGSDQS_SHIFT 
-#undef DDR_PHY_DX8SL0OSC_LBGSDQS_MASK 
+#undef DDR_PHY_DX8SL0OSC_LBGSDQS_DEFVAL
+#undef DDR_PHY_DX8SL0OSC_LBGSDQS_SHIFT
+#undef DDR_PHY_DX8SL0OSC_LBGSDQS_MASK
 #define DDR_PHY_DX8SL0OSC_LBGSDQS_DEFVAL                       0x00019FFE
 #define DDR_PHY_DX8SL0OSC_LBGSDQS_SHIFT                        20
 #define DDR_PHY_DX8SL0OSC_LBGSDQS_MASK                         0x00100000U
@@ -17966,9 +17966,9 @@
 /*
 * Loopback DQS Gating
 */
-#undef DDR_PHY_DX8SL0OSC_LBGDQS_DEFVAL 
-#undef DDR_PHY_DX8SL0OSC_LBGDQS_SHIFT 
-#undef DDR_PHY_DX8SL0OSC_LBGDQS_MASK 
+#undef DDR_PHY_DX8SL0OSC_LBGDQS_DEFVAL
+#undef DDR_PHY_DX8SL0OSC_LBGDQS_SHIFT
+#undef DDR_PHY_DX8SL0OSC_LBGDQS_MASK
 #define DDR_PHY_DX8SL0OSC_LBGDQS_DEFVAL                        0x00019FFE
 #define DDR_PHY_DX8SL0OSC_LBGDQS_SHIFT                         18
 #define DDR_PHY_DX8SL0OSC_LBGDQS_MASK                          0x000C0000U
@@ -17976,9 +17976,9 @@
 /*
 * Loopback DQS Shift
 */
-#undef DDR_PHY_DX8SL0OSC_LBDQSS_DEFVAL 
-#undef DDR_PHY_DX8SL0OSC_LBDQSS_SHIFT 
-#undef DDR_PHY_DX8SL0OSC_LBDQSS_MASK 
+#undef DDR_PHY_DX8SL0OSC_LBDQSS_DEFVAL
+#undef DDR_PHY_DX8SL0OSC_LBDQSS_SHIFT
+#undef DDR_PHY_DX8SL0OSC_LBDQSS_MASK
 #define DDR_PHY_DX8SL0OSC_LBDQSS_DEFVAL                        0x00019FFE
 #define DDR_PHY_DX8SL0OSC_LBDQSS_SHIFT                         17
 #define DDR_PHY_DX8SL0OSC_LBDQSS_MASK                          0x00020000U
@@ -17986,9 +17986,9 @@
 /*
 * PHY High-Speed Reset
 */
-#undef DDR_PHY_DX8SL0OSC_PHYHRST_DEFVAL 
-#undef DDR_PHY_DX8SL0OSC_PHYHRST_SHIFT 
-#undef DDR_PHY_DX8SL0OSC_PHYHRST_MASK 
+#undef DDR_PHY_DX8SL0OSC_PHYHRST_DEFVAL
+#undef DDR_PHY_DX8SL0OSC_PHYHRST_SHIFT
+#undef DDR_PHY_DX8SL0OSC_PHYHRST_MASK
 #define DDR_PHY_DX8SL0OSC_PHYHRST_DEFVAL                       0x00019FFE
 #define DDR_PHY_DX8SL0OSC_PHYHRST_SHIFT                        16
 #define DDR_PHY_DX8SL0OSC_PHYHRST_MASK                         0x00010000U
@@ -17996,9 +17996,9 @@
 /*
 * PHY FIFO Reset
 */
-#undef DDR_PHY_DX8SL0OSC_PHYFRST_DEFVAL 
-#undef DDR_PHY_DX8SL0OSC_PHYFRST_SHIFT 
-#undef DDR_PHY_DX8SL0OSC_PHYFRST_MASK 
+#undef DDR_PHY_DX8SL0OSC_PHYFRST_DEFVAL
+#undef DDR_PHY_DX8SL0OSC_PHYFRST_SHIFT
+#undef DDR_PHY_DX8SL0OSC_PHYFRST_MASK
 #define DDR_PHY_DX8SL0OSC_PHYFRST_DEFVAL                       0x00019FFE
 #define DDR_PHY_DX8SL0OSC_PHYFRST_SHIFT                        15
 #define DDR_PHY_DX8SL0OSC_PHYFRST_MASK                         0x00008000U
@@ -18006,9 +18006,9 @@
 /*
 * Delay Line Test Start
 */
-#undef DDR_PHY_DX8SL0OSC_DLTST_DEFVAL 
-#undef DDR_PHY_DX8SL0OSC_DLTST_SHIFT 
-#undef DDR_PHY_DX8SL0OSC_DLTST_MASK 
+#undef DDR_PHY_DX8SL0OSC_DLTST_DEFVAL
+#undef DDR_PHY_DX8SL0OSC_DLTST_SHIFT
+#undef DDR_PHY_DX8SL0OSC_DLTST_MASK
 #define DDR_PHY_DX8SL0OSC_DLTST_DEFVAL                         0x00019FFE
 #define DDR_PHY_DX8SL0OSC_DLTST_SHIFT                          14
 #define DDR_PHY_DX8SL0OSC_DLTST_MASK                           0x00004000U
@@ -18016,9 +18016,9 @@
 /*
 * Delay Line Test Mode
 */
-#undef DDR_PHY_DX8SL0OSC_DLTMODE_DEFVAL 
-#undef DDR_PHY_DX8SL0OSC_DLTMODE_SHIFT 
-#undef DDR_PHY_DX8SL0OSC_DLTMODE_MASK 
+#undef DDR_PHY_DX8SL0OSC_DLTMODE_DEFVAL
+#undef DDR_PHY_DX8SL0OSC_DLTMODE_SHIFT
+#undef DDR_PHY_DX8SL0OSC_DLTMODE_MASK
 #define DDR_PHY_DX8SL0OSC_DLTMODE_DEFVAL                       0x00019FFE
 #define DDR_PHY_DX8SL0OSC_DLTMODE_SHIFT                        13
 #define DDR_PHY_DX8SL0OSC_DLTMODE_MASK                         0x00002000U
@@ -18026,9 +18026,9 @@
 /*
 * Reserved. Caution, do not write to this register field.
 */
-#undef DDR_PHY_DX8SL0OSC_RESERVED_12_11_DEFVAL 
-#undef DDR_PHY_DX8SL0OSC_RESERVED_12_11_SHIFT 
-#undef DDR_PHY_DX8SL0OSC_RESERVED_12_11_MASK 
+#undef DDR_PHY_DX8SL0OSC_RESERVED_12_11_DEFVAL
+#undef DDR_PHY_DX8SL0OSC_RESERVED_12_11_SHIFT
+#undef DDR_PHY_DX8SL0OSC_RESERVED_12_11_MASK
 #define DDR_PHY_DX8SL0OSC_RESERVED_12_11_DEFVAL                0x00019FFE
 #define DDR_PHY_DX8SL0OSC_RESERVED_12_11_SHIFT                 11
 #define DDR_PHY_DX8SL0OSC_RESERVED_12_11_MASK                  0x00001800U
@@ -18036,9 +18036,9 @@
 /*
 * Oscillator Mode Write-Data Delay Line Select
 */
-#undef DDR_PHY_DX8SL0OSC_OSCWDDL_DEFVAL 
-#undef DDR_PHY_DX8SL0OSC_OSCWDDL_SHIFT 
-#undef DDR_PHY_DX8SL0OSC_OSCWDDL_MASK 
+#undef DDR_PHY_DX8SL0OSC_OSCWDDL_DEFVAL
+#undef DDR_PHY_DX8SL0OSC_OSCWDDL_SHIFT
+#undef DDR_PHY_DX8SL0OSC_OSCWDDL_MASK
 #define DDR_PHY_DX8SL0OSC_OSCWDDL_DEFVAL                       0x00019FFE
 #define DDR_PHY_DX8SL0OSC_OSCWDDL_SHIFT                        9
 #define DDR_PHY_DX8SL0OSC_OSCWDDL_MASK                         0x00000600U
@@ -18046,9 +18046,9 @@
 /*
 * Reserved. Caution, do not write to this register field.
 */
-#undef DDR_PHY_DX8SL0OSC_RESERVED_8_7_DEFVAL 
-#undef DDR_PHY_DX8SL0OSC_RESERVED_8_7_SHIFT 
-#undef DDR_PHY_DX8SL0OSC_RESERVED_8_7_MASK 
+#undef DDR_PHY_DX8SL0OSC_RESERVED_8_7_DEFVAL
+#undef DDR_PHY_DX8SL0OSC_RESERVED_8_7_SHIFT
+#undef DDR_PHY_DX8SL0OSC_RESERVED_8_7_MASK
 #define DDR_PHY_DX8SL0OSC_RESERVED_8_7_DEFVAL                  0x00019FFE
 #define DDR_PHY_DX8SL0OSC_RESERVED_8_7_SHIFT                   7
 #define DDR_PHY_DX8SL0OSC_RESERVED_8_7_MASK                    0x00000180U
@@ -18056,9 +18056,9 @@
 /*
 * Oscillator Mode Write-Leveling Delay Line Select
 */
-#undef DDR_PHY_DX8SL0OSC_OSCWDL_DEFVAL 
-#undef DDR_PHY_DX8SL0OSC_OSCWDL_SHIFT 
-#undef DDR_PHY_DX8SL0OSC_OSCWDL_MASK 
+#undef DDR_PHY_DX8SL0OSC_OSCWDL_DEFVAL
+#undef DDR_PHY_DX8SL0OSC_OSCWDL_SHIFT
+#undef DDR_PHY_DX8SL0OSC_OSCWDL_MASK
 #define DDR_PHY_DX8SL0OSC_OSCWDL_DEFVAL                        0x00019FFE
 #define DDR_PHY_DX8SL0OSC_OSCWDL_SHIFT                         5
 #define DDR_PHY_DX8SL0OSC_OSCWDL_MASK                          0x00000060U
@@ -18066,9 +18066,9 @@
 /*
 * Oscillator Mode Division
 */
-#undef DDR_PHY_DX8SL0OSC_OSCDIV_DEFVAL 
-#undef DDR_PHY_DX8SL0OSC_OSCDIV_SHIFT 
-#undef DDR_PHY_DX8SL0OSC_OSCDIV_MASK 
+#undef DDR_PHY_DX8SL0OSC_OSCDIV_DEFVAL
+#undef DDR_PHY_DX8SL0OSC_OSCDIV_SHIFT
+#undef DDR_PHY_DX8SL0OSC_OSCDIV_MASK
 #define DDR_PHY_DX8SL0OSC_OSCDIV_DEFVAL                        0x00019FFE
 #define DDR_PHY_DX8SL0OSC_OSCDIV_SHIFT                         1
 #define DDR_PHY_DX8SL0OSC_OSCDIV_MASK                          0x0000001EU
@@ -18076,9 +18076,9 @@
 /*
 * Oscillator Enable
 */
-#undef DDR_PHY_DX8SL0OSC_OSCEN_DEFVAL 
-#undef DDR_PHY_DX8SL0OSC_OSCEN_SHIFT 
-#undef DDR_PHY_DX8SL0OSC_OSCEN_MASK 
+#undef DDR_PHY_DX8SL0OSC_OSCEN_DEFVAL
+#undef DDR_PHY_DX8SL0OSC_OSCEN_SHIFT
+#undef DDR_PHY_DX8SL0OSC_OSCEN_MASK
 #define DDR_PHY_DX8SL0OSC_OSCEN_DEFVAL                         0x00019FFE
 #define DDR_PHY_DX8SL0OSC_OSCEN_SHIFT                          0
 #define DDR_PHY_DX8SL0OSC_OSCEN_MASK                           0x00000001U
@@ -18086,9 +18086,9 @@
 /*
 * PLL Bypass
 */
-#undef DDR_PHY_DX8SL0PLLCR0_PLLBYP_DEFVAL 
-#undef DDR_PHY_DX8SL0PLLCR0_PLLBYP_SHIFT 
-#undef DDR_PHY_DX8SL0PLLCR0_PLLBYP_MASK 
+#undef DDR_PHY_DX8SL0PLLCR0_PLLBYP_DEFVAL
+#undef DDR_PHY_DX8SL0PLLCR0_PLLBYP_SHIFT
+#undef DDR_PHY_DX8SL0PLLCR0_PLLBYP_MASK
 #define DDR_PHY_DX8SL0PLLCR0_PLLBYP_DEFVAL                     0x001C0000
 #define DDR_PHY_DX8SL0PLLCR0_PLLBYP_SHIFT                      31
 #define DDR_PHY_DX8SL0PLLCR0_PLLBYP_MASK                       0x80000000U
@@ -18096,9 +18096,9 @@
 /*
 * PLL Reset
 */
-#undef DDR_PHY_DX8SL0PLLCR0_PLLRST_DEFVAL 
-#undef DDR_PHY_DX8SL0PLLCR0_PLLRST_SHIFT 
-#undef DDR_PHY_DX8SL0PLLCR0_PLLRST_MASK 
+#undef DDR_PHY_DX8SL0PLLCR0_PLLRST_DEFVAL
+#undef DDR_PHY_DX8SL0PLLCR0_PLLRST_SHIFT
+#undef DDR_PHY_DX8SL0PLLCR0_PLLRST_MASK
 #define DDR_PHY_DX8SL0PLLCR0_PLLRST_DEFVAL                     0x001C0000
 #define DDR_PHY_DX8SL0PLLCR0_PLLRST_SHIFT                      30
 #define DDR_PHY_DX8SL0PLLCR0_PLLRST_MASK                       0x40000000U
@@ -18106,9 +18106,9 @@
 /*
 * PLL Power Down
 */
-#undef DDR_PHY_DX8SL0PLLCR0_PLLPD_DEFVAL 
-#undef DDR_PHY_DX8SL0PLLCR0_PLLPD_SHIFT 
-#undef DDR_PHY_DX8SL0PLLCR0_PLLPD_MASK 
+#undef DDR_PHY_DX8SL0PLLCR0_PLLPD_DEFVAL
+#undef DDR_PHY_DX8SL0PLLCR0_PLLPD_SHIFT
+#undef DDR_PHY_DX8SL0PLLCR0_PLLPD_MASK
 #define DDR_PHY_DX8SL0PLLCR0_PLLPD_DEFVAL                      0x001C0000
 #define DDR_PHY_DX8SL0PLLCR0_PLLPD_SHIFT                       29
 #define DDR_PHY_DX8SL0PLLCR0_PLLPD_MASK                        0x20000000U
@@ -18116,9 +18116,9 @@
 /*
 * Reference Stop Mode
 */
-#undef DDR_PHY_DX8SL0PLLCR0_RSTOPM_DEFVAL 
-#undef DDR_PHY_DX8SL0PLLCR0_RSTOPM_SHIFT 
-#undef DDR_PHY_DX8SL0PLLCR0_RSTOPM_MASK 
+#undef DDR_PHY_DX8SL0PLLCR0_RSTOPM_DEFVAL
+#undef DDR_PHY_DX8SL0PLLCR0_RSTOPM_SHIFT
+#undef DDR_PHY_DX8SL0PLLCR0_RSTOPM_MASK
 #define DDR_PHY_DX8SL0PLLCR0_RSTOPM_DEFVAL                     0x001C0000
 #define DDR_PHY_DX8SL0PLLCR0_RSTOPM_SHIFT                      28
 #define DDR_PHY_DX8SL0PLLCR0_RSTOPM_MASK                       0x10000000U
@@ -18126,9 +18126,9 @@
 /*
 * PLL Frequency Select
 */
-#undef DDR_PHY_DX8SL0PLLCR0_FRQSEL_DEFVAL 
-#undef DDR_PHY_DX8SL0PLLCR0_FRQSEL_SHIFT 
-#undef DDR_PHY_DX8SL0PLLCR0_FRQSEL_MASK 
+#undef DDR_PHY_DX8SL0PLLCR0_FRQSEL_DEFVAL
+#undef DDR_PHY_DX8SL0PLLCR0_FRQSEL_SHIFT
+#undef DDR_PHY_DX8SL0PLLCR0_FRQSEL_MASK
 #define DDR_PHY_DX8SL0PLLCR0_FRQSEL_DEFVAL                     0x001C0000
 #define DDR_PHY_DX8SL0PLLCR0_FRQSEL_SHIFT                      24
 #define DDR_PHY_DX8SL0PLLCR0_FRQSEL_MASK                       0x0F000000U
@@ -18136,9 +18136,9 @@
 /*
 * Relock Mode
 */
-#undef DDR_PHY_DX8SL0PLLCR0_RLOCKM_DEFVAL 
-#undef DDR_PHY_DX8SL0PLLCR0_RLOCKM_SHIFT 
-#undef DDR_PHY_DX8SL0PLLCR0_RLOCKM_MASK 
+#undef DDR_PHY_DX8SL0PLLCR0_RLOCKM_DEFVAL
+#undef DDR_PHY_DX8SL0PLLCR0_RLOCKM_SHIFT
+#undef DDR_PHY_DX8SL0PLLCR0_RLOCKM_MASK
 #define DDR_PHY_DX8SL0PLLCR0_RLOCKM_DEFVAL                     0x001C0000
 #define DDR_PHY_DX8SL0PLLCR0_RLOCKM_SHIFT                      23
 #define DDR_PHY_DX8SL0PLLCR0_RLOCKM_MASK                       0x00800000U
@@ -18146,9 +18146,9 @@
 /*
 * Charge Pump Proportional Current Control
 */
-#undef DDR_PHY_DX8SL0PLLCR0_CPPC_DEFVAL 
-#undef DDR_PHY_DX8SL0PLLCR0_CPPC_SHIFT 
-#undef DDR_PHY_DX8SL0PLLCR0_CPPC_MASK 
+#undef DDR_PHY_DX8SL0PLLCR0_CPPC_DEFVAL
+#undef DDR_PHY_DX8SL0PLLCR0_CPPC_SHIFT
+#undef DDR_PHY_DX8SL0PLLCR0_CPPC_MASK
 #define DDR_PHY_DX8SL0PLLCR0_CPPC_DEFVAL                       0x001C0000
 #define DDR_PHY_DX8SL0PLLCR0_CPPC_SHIFT                        17
 #define DDR_PHY_DX8SL0PLLCR0_CPPC_MASK                         0x007E0000U
@@ -18156,9 +18156,9 @@
 /*
 * Charge Pump Integrating Current Control
 */
-#undef DDR_PHY_DX8SL0PLLCR0_CPIC_DEFVAL 
-#undef DDR_PHY_DX8SL0PLLCR0_CPIC_SHIFT 
-#undef DDR_PHY_DX8SL0PLLCR0_CPIC_MASK 
+#undef DDR_PHY_DX8SL0PLLCR0_CPIC_DEFVAL
+#undef DDR_PHY_DX8SL0PLLCR0_CPIC_SHIFT
+#undef DDR_PHY_DX8SL0PLLCR0_CPIC_MASK
 #define DDR_PHY_DX8SL0PLLCR0_CPIC_DEFVAL                       0x001C0000
 #define DDR_PHY_DX8SL0PLLCR0_CPIC_SHIFT                        13
 #define DDR_PHY_DX8SL0PLLCR0_CPIC_MASK                         0x0001E000U
@@ -18166,9 +18166,9 @@
 /*
 * Gear Shift
 */
-#undef DDR_PHY_DX8SL0PLLCR0_GSHIFT_DEFVAL 
-#undef DDR_PHY_DX8SL0PLLCR0_GSHIFT_SHIFT 
-#undef DDR_PHY_DX8SL0PLLCR0_GSHIFT_MASK 
+#undef DDR_PHY_DX8SL0PLLCR0_GSHIFT_DEFVAL
+#undef DDR_PHY_DX8SL0PLLCR0_GSHIFT_SHIFT
+#undef DDR_PHY_DX8SL0PLLCR0_GSHIFT_MASK
 #define DDR_PHY_DX8SL0PLLCR0_GSHIFT_DEFVAL                     0x001C0000
 #define DDR_PHY_DX8SL0PLLCR0_GSHIFT_SHIFT                      12
 #define DDR_PHY_DX8SL0PLLCR0_GSHIFT_MASK                       0x00001000U
@@ -18176,9 +18176,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_DEFVAL 
-#undef DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_SHIFT 
-#undef DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_MASK 
+#undef DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_DEFVAL
+#undef DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_SHIFT
+#undef DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_MASK
 #define DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_DEFVAL              0x001C0000
 #define DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_SHIFT               9
 #define DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_MASK                0x00000E00U
@@ -18186,9 +18186,9 @@
 /*
 * Analog Test Enable (ATOEN)
 */
-#undef DDR_PHY_DX8SL0PLLCR0_ATOEN_DEFVAL 
-#undef DDR_PHY_DX8SL0PLLCR0_ATOEN_SHIFT 
-#undef DDR_PHY_DX8SL0PLLCR0_ATOEN_MASK 
+#undef DDR_PHY_DX8SL0PLLCR0_ATOEN_DEFVAL
+#undef DDR_PHY_DX8SL0PLLCR0_ATOEN_SHIFT
+#undef DDR_PHY_DX8SL0PLLCR0_ATOEN_MASK
 #define DDR_PHY_DX8SL0PLLCR0_ATOEN_DEFVAL                      0x001C0000
 #define DDR_PHY_DX8SL0PLLCR0_ATOEN_SHIFT                       8
 #define DDR_PHY_DX8SL0PLLCR0_ATOEN_MASK                        0x00000100U
@@ -18196,9 +18196,9 @@
 /*
 * Analog Test Control
 */
-#undef DDR_PHY_DX8SL0PLLCR0_ATC_DEFVAL 
-#undef DDR_PHY_DX8SL0PLLCR0_ATC_SHIFT 
-#undef DDR_PHY_DX8SL0PLLCR0_ATC_MASK 
+#undef DDR_PHY_DX8SL0PLLCR0_ATC_DEFVAL
+#undef DDR_PHY_DX8SL0PLLCR0_ATC_SHIFT
+#undef DDR_PHY_DX8SL0PLLCR0_ATC_MASK
 #define DDR_PHY_DX8SL0PLLCR0_ATC_DEFVAL                        0x001C0000
 #define DDR_PHY_DX8SL0PLLCR0_ATC_SHIFT                         4
 #define DDR_PHY_DX8SL0PLLCR0_ATC_MASK                          0x000000F0U
@@ -18206,9 +18206,9 @@
 /*
 * Digital Test Control
 */
-#undef DDR_PHY_DX8SL0PLLCR0_DTC_DEFVAL 
-#undef DDR_PHY_DX8SL0PLLCR0_DTC_SHIFT 
-#undef DDR_PHY_DX8SL0PLLCR0_DTC_MASK 
+#undef DDR_PHY_DX8SL0PLLCR0_DTC_DEFVAL
+#undef DDR_PHY_DX8SL0PLLCR0_DTC_SHIFT
+#undef DDR_PHY_DX8SL0PLLCR0_DTC_MASK
 #define DDR_PHY_DX8SL0PLLCR0_DTC_DEFVAL                        0x001C0000
 #define DDR_PHY_DX8SL0PLLCR0_DTC_SHIFT                         0
 #define DDR_PHY_DX8SL0PLLCR0_DTC_MASK                          0x0000000FU
@@ -18216,9 +18216,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_DEFVAL 
-#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_SHIFT 
-#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_MASK 
+#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_DEFVAL
+#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_SHIFT
+#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_MASK
 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_DEFVAL             0x01264000
 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_SHIFT              25
 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_MASK               0xFE000000U
@@ -18226,9 +18226,9 @@
 /*
 * Read Path Rise-to-Rise Mode
 */
-#undef DDR_PHY_DX8SL0DQSCTL_RRRMODE_DEFVAL 
-#undef DDR_PHY_DX8SL0DQSCTL_RRRMODE_SHIFT 
-#undef DDR_PHY_DX8SL0DQSCTL_RRRMODE_MASK 
+#undef DDR_PHY_DX8SL0DQSCTL_RRRMODE_DEFVAL
+#undef DDR_PHY_DX8SL0DQSCTL_RRRMODE_SHIFT
+#undef DDR_PHY_DX8SL0DQSCTL_RRRMODE_MASK
 #define DDR_PHY_DX8SL0DQSCTL_RRRMODE_DEFVAL                    0x01264000
 #define DDR_PHY_DX8SL0DQSCTL_RRRMODE_SHIFT                     24
 #define DDR_PHY_DX8SL0DQSCTL_RRRMODE_MASK                      0x01000000U
@@ -18236,9 +18236,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_DEFVAL 
-#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_SHIFT 
-#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_MASK 
+#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_DEFVAL
+#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_SHIFT
+#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_MASK
 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_DEFVAL             0x01264000
 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_SHIFT              22
 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_MASK               0x00C00000U
@@ -18246,9 +18246,9 @@
 /*
 * Write Path Rise-to-Rise Mode
 */
-#undef DDR_PHY_DX8SL0DQSCTL_WRRMODE_DEFVAL 
-#undef DDR_PHY_DX8SL0DQSCTL_WRRMODE_SHIFT 
-#undef DDR_PHY_DX8SL0DQSCTL_WRRMODE_MASK 
+#undef DDR_PHY_DX8SL0DQSCTL_WRRMODE_DEFVAL
+#undef DDR_PHY_DX8SL0DQSCTL_WRRMODE_SHIFT
+#undef DDR_PHY_DX8SL0DQSCTL_WRRMODE_MASK
 #define DDR_PHY_DX8SL0DQSCTL_WRRMODE_DEFVAL                    0x01264000
 #define DDR_PHY_DX8SL0DQSCTL_WRRMODE_SHIFT                     21
 #define DDR_PHY_DX8SL0DQSCTL_WRRMODE_MASK                      0x00200000U
@@ -18256,9 +18256,9 @@
 /*
 * DQS Gate Extension
 */
-#undef DDR_PHY_DX8SL0DQSCTL_DQSGX_DEFVAL 
-#undef DDR_PHY_DX8SL0DQSCTL_DQSGX_SHIFT 
-#undef DDR_PHY_DX8SL0DQSCTL_DQSGX_MASK 
+#undef DDR_PHY_DX8SL0DQSCTL_DQSGX_DEFVAL
+#undef DDR_PHY_DX8SL0DQSCTL_DQSGX_SHIFT
+#undef DDR_PHY_DX8SL0DQSCTL_DQSGX_MASK
 #define DDR_PHY_DX8SL0DQSCTL_DQSGX_DEFVAL                      0x01264000
 #define DDR_PHY_DX8SL0DQSCTL_DQSGX_SHIFT                       19
 #define DDR_PHY_DX8SL0DQSCTL_DQSGX_MASK                        0x00180000U
@@ -18266,9 +18266,9 @@
 /*
 * Low Power PLL Power Down
 */
-#undef DDR_PHY_DX8SL0DQSCTL_LPPLLPD_DEFVAL 
-#undef DDR_PHY_DX8SL0DQSCTL_LPPLLPD_SHIFT 
-#undef DDR_PHY_DX8SL0DQSCTL_LPPLLPD_MASK 
+#undef DDR_PHY_DX8SL0DQSCTL_LPPLLPD_DEFVAL
+#undef DDR_PHY_DX8SL0DQSCTL_LPPLLPD_SHIFT
+#undef DDR_PHY_DX8SL0DQSCTL_LPPLLPD_MASK
 #define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_DEFVAL                    0x01264000
 #define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_SHIFT                     18
 #define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_MASK                      0x00040000U
@@ -18276,9 +18276,9 @@
 /*
 * Low Power I/O Power Down
 */
-#undef DDR_PHY_DX8SL0DQSCTL_LPIOPD_DEFVAL 
-#undef DDR_PHY_DX8SL0DQSCTL_LPIOPD_SHIFT 
-#undef DDR_PHY_DX8SL0DQSCTL_LPIOPD_MASK 
+#undef DDR_PHY_DX8SL0DQSCTL_LPIOPD_DEFVAL
+#undef DDR_PHY_DX8SL0DQSCTL_LPIOPD_SHIFT
+#undef DDR_PHY_DX8SL0DQSCTL_LPIOPD_MASK
 #define DDR_PHY_DX8SL0DQSCTL_LPIOPD_DEFVAL                     0x01264000
 #define DDR_PHY_DX8SL0DQSCTL_LPIOPD_SHIFT                      17
 #define DDR_PHY_DX8SL0DQSCTL_LPIOPD_MASK                       0x00020000U
@@ -18286,9 +18286,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_DEFVAL 
-#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_SHIFT 
-#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_MASK 
+#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_DEFVAL
+#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_SHIFT
+#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_MASK
 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_DEFVAL             0x01264000
 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_SHIFT              15
 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_MASK               0x00018000U
@@ -18296,9 +18296,9 @@
 /*
 * QS Counter Enable
 */
-#undef DDR_PHY_DX8SL0DQSCTL_QSCNTEN_DEFVAL 
-#undef DDR_PHY_DX8SL0DQSCTL_QSCNTEN_SHIFT 
-#undef DDR_PHY_DX8SL0DQSCTL_QSCNTEN_MASK 
+#undef DDR_PHY_DX8SL0DQSCTL_QSCNTEN_DEFVAL
+#undef DDR_PHY_DX8SL0DQSCTL_QSCNTEN_SHIFT
+#undef DDR_PHY_DX8SL0DQSCTL_QSCNTEN_MASK
 #define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_DEFVAL                    0x01264000
 #define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_SHIFT                     14
 #define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_MASK                      0x00004000U
@@ -18306,9 +18306,9 @@
 /*
 * Unused DQ I/O Mode
 */
-#undef DDR_PHY_DX8SL0DQSCTL_UDQIOM_DEFVAL 
-#undef DDR_PHY_DX8SL0DQSCTL_UDQIOM_SHIFT 
-#undef DDR_PHY_DX8SL0DQSCTL_UDQIOM_MASK 
+#undef DDR_PHY_DX8SL0DQSCTL_UDQIOM_DEFVAL
+#undef DDR_PHY_DX8SL0DQSCTL_UDQIOM_SHIFT
+#undef DDR_PHY_DX8SL0DQSCTL_UDQIOM_MASK
 #define DDR_PHY_DX8SL0DQSCTL_UDQIOM_DEFVAL                     0x01264000
 #define DDR_PHY_DX8SL0DQSCTL_UDQIOM_SHIFT                      13
 #define DDR_PHY_DX8SL0DQSCTL_UDQIOM_MASK                       0x00002000U
@@ -18316,9 +18316,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_DEFVAL 
-#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_SHIFT 
-#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_MASK 
+#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_DEFVAL
+#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_SHIFT
+#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_MASK
 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_DEFVAL             0x01264000
 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_SHIFT              10
 #define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_MASK               0x00001C00U
@@ -18326,9 +18326,9 @@
 /*
 * Data Slew Rate
 */
-#undef DDR_PHY_DX8SL0DQSCTL_DXSR_DEFVAL 
-#undef DDR_PHY_DX8SL0DQSCTL_DXSR_SHIFT 
-#undef DDR_PHY_DX8SL0DQSCTL_DXSR_MASK 
+#undef DDR_PHY_DX8SL0DQSCTL_DXSR_DEFVAL
+#undef DDR_PHY_DX8SL0DQSCTL_DXSR_SHIFT
+#undef DDR_PHY_DX8SL0DQSCTL_DXSR_MASK
 #define DDR_PHY_DX8SL0DQSCTL_DXSR_DEFVAL                       0x01264000
 #define DDR_PHY_DX8SL0DQSCTL_DXSR_SHIFT                        8
 #define DDR_PHY_DX8SL0DQSCTL_DXSR_MASK                         0x00000300U
@@ -18336,9 +18336,9 @@
 /*
 * DQS_N Resistor
 */
-#undef DDR_PHY_DX8SL0DQSCTL_DQSNRES_DEFVAL 
-#undef DDR_PHY_DX8SL0DQSCTL_DQSNRES_SHIFT 
-#undef DDR_PHY_DX8SL0DQSCTL_DQSNRES_MASK 
+#undef DDR_PHY_DX8SL0DQSCTL_DQSNRES_DEFVAL
+#undef DDR_PHY_DX8SL0DQSCTL_DQSNRES_SHIFT
+#undef DDR_PHY_DX8SL0DQSCTL_DQSNRES_MASK
 #define DDR_PHY_DX8SL0DQSCTL_DQSNRES_DEFVAL                    0x01264000
 #define DDR_PHY_DX8SL0DQSCTL_DQSNRES_SHIFT                     4
 #define DDR_PHY_DX8SL0DQSCTL_DQSNRES_MASK                      0x000000F0U
@@ -18346,9 +18346,9 @@
 /*
 * DQS Resistor
 */
-#undef DDR_PHY_DX8SL0DQSCTL_DQSRES_DEFVAL 
-#undef DDR_PHY_DX8SL0DQSCTL_DQSRES_SHIFT 
-#undef DDR_PHY_DX8SL0DQSCTL_DQSRES_MASK 
+#undef DDR_PHY_DX8SL0DQSCTL_DQSRES_DEFVAL
+#undef DDR_PHY_DX8SL0DQSCTL_DQSRES_SHIFT
+#undef DDR_PHY_DX8SL0DQSCTL_DQSRES_MASK
 #define DDR_PHY_DX8SL0DQSCTL_DQSRES_DEFVAL                     0x01264000
 #define DDR_PHY_DX8SL0DQSCTL_DQSRES_SHIFT                      0
 #define DDR_PHY_DX8SL0DQSCTL_DQSRES_MASK                       0x0000000FU
@@ -18356,9 +18356,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_DEFVAL 
-#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_SHIFT 
-#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_MASK 
+#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_DEFVAL
+#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_SHIFT
+#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_MASK
 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_DEFVAL             0x00141800
 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_SHIFT              24
 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_MASK               0xFF000000U
@@ -18366,9 +18366,9 @@
 /*
 * Configurable Read Data Enable
 */
-#undef DDR_PHY_DX8SL0DXCTL2_CRDEN_DEFVAL 
-#undef DDR_PHY_DX8SL0DXCTL2_CRDEN_SHIFT 
-#undef DDR_PHY_DX8SL0DXCTL2_CRDEN_MASK 
+#undef DDR_PHY_DX8SL0DXCTL2_CRDEN_DEFVAL
+#undef DDR_PHY_DX8SL0DXCTL2_CRDEN_SHIFT
+#undef DDR_PHY_DX8SL0DXCTL2_CRDEN_MASK
 #define DDR_PHY_DX8SL0DXCTL2_CRDEN_DEFVAL                      0x00141800
 #define DDR_PHY_DX8SL0DXCTL2_CRDEN_SHIFT                       23
 #define DDR_PHY_DX8SL0DXCTL2_CRDEN_MASK                        0x00800000U
@@ -18376,9 +18376,9 @@
 /*
 * OX Extension during Post-amble
 */
-#undef DDR_PHY_DX8SL0DXCTL2_POSOEX_DEFVAL 
-#undef DDR_PHY_DX8SL0DXCTL2_POSOEX_SHIFT 
-#undef DDR_PHY_DX8SL0DXCTL2_POSOEX_MASK 
+#undef DDR_PHY_DX8SL0DXCTL2_POSOEX_DEFVAL
+#undef DDR_PHY_DX8SL0DXCTL2_POSOEX_SHIFT
+#undef DDR_PHY_DX8SL0DXCTL2_POSOEX_MASK
 #define DDR_PHY_DX8SL0DXCTL2_POSOEX_DEFVAL                     0x00141800
 #define DDR_PHY_DX8SL0DXCTL2_POSOEX_SHIFT                      20
 #define DDR_PHY_DX8SL0DXCTL2_POSOEX_MASK                       0x00700000U
@@ -18386,9 +18386,9 @@
 /*
 * OE Extension during Pre-amble
 */
-#undef DDR_PHY_DX8SL0DXCTL2_PREOEX_DEFVAL 
-#undef DDR_PHY_DX8SL0DXCTL2_PREOEX_SHIFT 
-#undef DDR_PHY_DX8SL0DXCTL2_PREOEX_MASK 
+#undef DDR_PHY_DX8SL0DXCTL2_PREOEX_DEFVAL
+#undef DDR_PHY_DX8SL0DXCTL2_PREOEX_SHIFT
+#undef DDR_PHY_DX8SL0DXCTL2_PREOEX_MASK
 #define DDR_PHY_DX8SL0DXCTL2_PREOEX_DEFVAL                     0x00141800
 #define DDR_PHY_DX8SL0DXCTL2_PREOEX_SHIFT                      18
 #define DDR_PHY_DX8SL0DXCTL2_PREOEX_MASK                       0x000C0000U
@@ -18396,9 +18396,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_17_DEFVAL 
-#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_17_SHIFT 
-#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_17_MASK 
+#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_17_DEFVAL
+#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_17_SHIFT
+#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_17_MASK
 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_17_DEFVAL                0x00141800
 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_17_SHIFT                 17
 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_17_MASK                  0x00020000U
@@ -18406,9 +18406,9 @@
 /*
 * I/O Assisted Gate Select
 */
-#undef DDR_PHY_DX8SL0DXCTL2_IOAG_DEFVAL 
-#undef DDR_PHY_DX8SL0DXCTL2_IOAG_SHIFT 
-#undef DDR_PHY_DX8SL0DXCTL2_IOAG_MASK 
+#undef DDR_PHY_DX8SL0DXCTL2_IOAG_DEFVAL
+#undef DDR_PHY_DX8SL0DXCTL2_IOAG_SHIFT
+#undef DDR_PHY_DX8SL0DXCTL2_IOAG_MASK
 #define DDR_PHY_DX8SL0DXCTL2_IOAG_DEFVAL                       0x00141800
 #define DDR_PHY_DX8SL0DXCTL2_IOAG_SHIFT                        16
 #define DDR_PHY_DX8SL0DXCTL2_IOAG_MASK                         0x00010000U
@@ -18416,9 +18416,9 @@
 /*
 * I/O Loopback Select
 */
-#undef DDR_PHY_DX8SL0DXCTL2_IOLB_DEFVAL 
-#undef DDR_PHY_DX8SL0DXCTL2_IOLB_SHIFT 
-#undef DDR_PHY_DX8SL0DXCTL2_IOLB_MASK 
+#undef DDR_PHY_DX8SL0DXCTL2_IOLB_DEFVAL
+#undef DDR_PHY_DX8SL0DXCTL2_IOLB_SHIFT
+#undef DDR_PHY_DX8SL0DXCTL2_IOLB_MASK
 #define DDR_PHY_DX8SL0DXCTL2_IOLB_DEFVAL                       0x00141800
 #define DDR_PHY_DX8SL0DXCTL2_IOLB_SHIFT                        15
 #define DDR_PHY_DX8SL0DXCTL2_IOLB_MASK                         0x00008000U
@@ -18426,9 +18426,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_DEFVAL 
-#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_SHIFT 
-#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_MASK 
+#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_DEFVAL
+#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_SHIFT
+#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_MASK
 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_DEFVAL             0x00141800
 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_SHIFT              13
 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_MASK               0x00006000U
@@ -18436,9 +18436,9 @@
 /*
 * Low Power Wakeup Threshold
 */
-#undef DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_DEFVAL 
-#undef DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_SHIFT 
-#undef DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_MASK 
+#undef DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_DEFVAL
+#undef DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_SHIFT
+#undef DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_MASK
 #define DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_DEFVAL             0x00141800
 #define DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_SHIFT              9
 #define DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_MASK               0x00001E00U
@@ -18446,9 +18446,9 @@
 /*
 * Read Data Bus Inversion Enable
 */
-#undef DDR_PHY_DX8SL0DXCTL2_RDBI_DEFVAL 
-#undef DDR_PHY_DX8SL0DXCTL2_RDBI_SHIFT 
-#undef DDR_PHY_DX8SL0DXCTL2_RDBI_MASK 
+#undef DDR_PHY_DX8SL0DXCTL2_RDBI_DEFVAL
+#undef DDR_PHY_DX8SL0DXCTL2_RDBI_SHIFT
+#undef DDR_PHY_DX8SL0DXCTL2_RDBI_MASK
 #define DDR_PHY_DX8SL0DXCTL2_RDBI_DEFVAL                       0x00141800
 #define DDR_PHY_DX8SL0DXCTL2_RDBI_SHIFT                        8
 #define DDR_PHY_DX8SL0DXCTL2_RDBI_MASK                         0x00000100U
@@ -18456,9 +18456,9 @@
 /*
 * Write Data Bus Inversion Enable
 */
-#undef DDR_PHY_DX8SL0DXCTL2_WDBI_DEFVAL 
-#undef DDR_PHY_DX8SL0DXCTL2_WDBI_SHIFT 
-#undef DDR_PHY_DX8SL0DXCTL2_WDBI_MASK 
+#undef DDR_PHY_DX8SL0DXCTL2_WDBI_DEFVAL
+#undef DDR_PHY_DX8SL0DXCTL2_WDBI_SHIFT
+#undef DDR_PHY_DX8SL0DXCTL2_WDBI_MASK
 #define DDR_PHY_DX8SL0DXCTL2_WDBI_DEFVAL                       0x00141800
 #define DDR_PHY_DX8SL0DXCTL2_WDBI_SHIFT                        7
 #define DDR_PHY_DX8SL0DXCTL2_WDBI_MASK                         0x00000080U
@@ -18466,9 +18466,9 @@
 /*
 * PUB Read FIFO Bypass
 */
-#undef DDR_PHY_DX8SL0DXCTL2_PRFBYP_DEFVAL 
-#undef DDR_PHY_DX8SL0DXCTL2_PRFBYP_SHIFT 
-#undef DDR_PHY_DX8SL0DXCTL2_PRFBYP_MASK 
+#undef DDR_PHY_DX8SL0DXCTL2_PRFBYP_DEFVAL
+#undef DDR_PHY_DX8SL0DXCTL2_PRFBYP_SHIFT
+#undef DDR_PHY_DX8SL0DXCTL2_PRFBYP_MASK
 #define DDR_PHY_DX8SL0DXCTL2_PRFBYP_DEFVAL                     0x00141800
 #define DDR_PHY_DX8SL0DXCTL2_PRFBYP_SHIFT                      6
 #define DDR_PHY_DX8SL0DXCTL2_PRFBYP_MASK                       0x00000040U
@@ -18476,9 +18476,9 @@
 /*
 * DATX8 Receive FIFO Read Mode
 */
-#undef DDR_PHY_DX8SL0DXCTL2_RDMODE_DEFVAL 
-#undef DDR_PHY_DX8SL0DXCTL2_RDMODE_SHIFT 
-#undef DDR_PHY_DX8SL0DXCTL2_RDMODE_MASK 
+#undef DDR_PHY_DX8SL0DXCTL2_RDMODE_DEFVAL
+#undef DDR_PHY_DX8SL0DXCTL2_RDMODE_SHIFT
+#undef DDR_PHY_DX8SL0DXCTL2_RDMODE_MASK
 #define DDR_PHY_DX8SL0DXCTL2_RDMODE_DEFVAL                     0x00141800
 #define DDR_PHY_DX8SL0DXCTL2_RDMODE_SHIFT                      4
 #define DDR_PHY_DX8SL0DXCTL2_RDMODE_MASK                       0x00000030U
@@ -18486,9 +18486,9 @@
 /*
 * Disables the Read FIFO Reset
 */
-#undef DDR_PHY_DX8SL0DXCTL2_DISRST_DEFVAL 
-#undef DDR_PHY_DX8SL0DXCTL2_DISRST_SHIFT 
-#undef DDR_PHY_DX8SL0DXCTL2_DISRST_MASK 
+#undef DDR_PHY_DX8SL0DXCTL2_DISRST_DEFVAL
+#undef DDR_PHY_DX8SL0DXCTL2_DISRST_SHIFT
+#undef DDR_PHY_DX8SL0DXCTL2_DISRST_MASK
 #define DDR_PHY_DX8SL0DXCTL2_DISRST_DEFVAL                     0x00141800
 #define DDR_PHY_DX8SL0DXCTL2_DISRST_SHIFT                      3
 #define DDR_PHY_DX8SL0DXCTL2_DISRST_MASK                       0x00000008U
@@ -18496,9 +18496,9 @@
 /*
 * Read DQS Gate I/O Loopback
 */
-#undef DDR_PHY_DX8SL0DXCTL2_DQSGLB_DEFVAL 
-#undef DDR_PHY_DX8SL0DXCTL2_DQSGLB_SHIFT 
-#undef DDR_PHY_DX8SL0DXCTL2_DQSGLB_MASK 
+#undef DDR_PHY_DX8SL0DXCTL2_DQSGLB_DEFVAL
+#undef DDR_PHY_DX8SL0DXCTL2_DQSGLB_SHIFT
+#undef DDR_PHY_DX8SL0DXCTL2_DQSGLB_MASK
 #define DDR_PHY_DX8SL0DXCTL2_DQSGLB_DEFVAL                     0x00141800
 #define DDR_PHY_DX8SL0DXCTL2_DQSGLB_SHIFT                      1
 #define DDR_PHY_DX8SL0DXCTL2_DQSGLB_MASK                       0x00000006U
@@ -18506,9 +18506,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_0_DEFVAL 
-#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_0_SHIFT 
-#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_0_MASK 
+#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_0_DEFVAL
+#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_0_SHIFT
+#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_0_MASK
 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_0_DEFVAL                 0x00141800
 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_0_SHIFT                  0
 #define DDR_PHY_DX8SL0DXCTL2_RESERVED_0_MASK                   0x00000001U
@@ -18516,9 +18516,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SL0IOCR_RESERVED_31_DEFVAL 
-#undef DDR_PHY_DX8SL0IOCR_RESERVED_31_SHIFT 
-#undef DDR_PHY_DX8SL0IOCR_RESERVED_31_MASK 
+#undef DDR_PHY_DX8SL0IOCR_RESERVED_31_DEFVAL
+#undef DDR_PHY_DX8SL0IOCR_RESERVED_31_SHIFT
+#undef DDR_PHY_DX8SL0IOCR_RESERVED_31_MASK
 #define DDR_PHY_DX8SL0IOCR_RESERVED_31_DEFVAL                  0x00000000
 #define DDR_PHY_DX8SL0IOCR_RESERVED_31_SHIFT                   31
 #define DDR_PHY_DX8SL0IOCR_RESERVED_31_MASK                    0x80000000U
@@ -18526,9 +18526,9 @@
 /*
 * PVREF_DAC REFSEL range select
 */
-#undef DDR_PHY_DX8SL0IOCR_DXDACRANGE_DEFVAL 
-#undef DDR_PHY_DX8SL0IOCR_DXDACRANGE_SHIFT 
-#undef DDR_PHY_DX8SL0IOCR_DXDACRANGE_MASK 
+#undef DDR_PHY_DX8SL0IOCR_DXDACRANGE_DEFVAL
+#undef DDR_PHY_DX8SL0IOCR_DXDACRANGE_SHIFT
+#undef DDR_PHY_DX8SL0IOCR_DXDACRANGE_MASK
 #define DDR_PHY_DX8SL0IOCR_DXDACRANGE_DEFVAL                   0x00000000
 #define DDR_PHY_DX8SL0IOCR_DXDACRANGE_SHIFT                    28
 #define DDR_PHY_DX8SL0IOCR_DXDACRANGE_MASK                     0x70000000U
@@ -18536,9 +18536,9 @@
 /*
 * IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
 */
-#undef DDR_PHY_DX8SL0IOCR_DXVREFIOM_DEFVAL 
-#undef DDR_PHY_DX8SL0IOCR_DXVREFIOM_SHIFT 
-#undef DDR_PHY_DX8SL0IOCR_DXVREFIOM_MASK 
+#undef DDR_PHY_DX8SL0IOCR_DXVREFIOM_DEFVAL
+#undef DDR_PHY_DX8SL0IOCR_DXVREFIOM_SHIFT
+#undef DDR_PHY_DX8SL0IOCR_DXVREFIOM_MASK
 #define DDR_PHY_DX8SL0IOCR_DXVREFIOM_DEFVAL                    0x00000000
 #define DDR_PHY_DX8SL0IOCR_DXVREFIOM_SHIFT                     25
 #define DDR_PHY_DX8SL0IOCR_DXVREFIOM_MASK                      0x0E000000U
@@ -18546,9 +18546,9 @@
 /*
 * DX IO Mode
 */
-#undef DDR_PHY_DX8SL0IOCR_DXIOM_DEFVAL 
-#undef DDR_PHY_DX8SL0IOCR_DXIOM_SHIFT 
-#undef DDR_PHY_DX8SL0IOCR_DXIOM_MASK 
+#undef DDR_PHY_DX8SL0IOCR_DXIOM_DEFVAL
+#undef DDR_PHY_DX8SL0IOCR_DXIOM_SHIFT
+#undef DDR_PHY_DX8SL0IOCR_DXIOM_MASK
 #define DDR_PHY_DX8SL0IOCR_DXIOM_DEFVAL                        0x00000000
 #define DDR_PHY_DX8SL0IOCR_DXIOM_SHIFT                         22
 #define DDR_PHY_DX8SL0IOCR_DXIOM_MASK                          0x01C00000U
@@ -18556,9 +18556,9 @@
 /*
 * DX IO Transmitter Mode
 */
-#undef DDR_PHY_DX8SL0IOCR_DXTXM_DEFVAL 
-#undef DDR_PHY_DX8SL0IOCR_DXTXM_SHIFT 
-#undef DDR_PHY_DX8SL0IOCR_DXTXM_MASK 
+#undef DDR_PHY_DX8SL0IOCR_DXTXM_DEFVAL
+#undef DDR_PHY_DX8SL0IOCR_DXTXM_SHIFT
+#undef DDR_PHY_DX8SL0IOCR_DXTXM_MASK
 #define DDR_PHY_DX8SL0IOCR_DXTXM_DEFVAL                        0x00000000
 #define DDR_PHY_DX8SL0IOCR_DXTXM_SHIFT                         11
 #define DDR_PHY_DX8SL0IOCR_DXTXM_MASK                          0x003FF800U
@@ -18566,9 +18566,9 @@
 /*
 * DX IO Receiver Mode
 */
-#undef DDR_PHY_DX8SL0IOCR_DXRXM_DEFVAL 
-#undef DDR_PHY_DX8SL0IOCR_DXRXM_SHIFT 
-#undef DDR_PHY_DX8SL0IOCR_DXRXM_MASK 
+#undef DDR_PHY_DX8SL0IOCR_DXRXM_DEFVAL
+#undef DDR_PHY_DX8SL0IOCR_DXRXM_SHIFT
+#undef DDR_PHY_DX8SL0IOCR_DXRXM_MASK
 #define DDR_PHY_DX8SL0IOCR_DXRXM_DEFVAL                        0x00000000
 #define DDR_PHY_DX8SL0IOCR_DXRXM_SHIFT                         0
 #define DDR_PHY_DX8SL0IOCR_DXRXM_MASK                          0x000007FFU
@@ -18576,9 +18576,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SL1OSC_RESERVED_31_30_DEFVAL 
-#undef DDR_PHY_DX8SL1OSC_RESERVED_31_30_SHIFT 
-#undef DDR_PHY_DX8SL1OSC_RESERVED_31_30_MASK 
+#undef DDR_PHY_DX8SL1OSC_RESERVED_31_30_DEFVAL
+#undef DDR_PHY_DX8SL1OSC_RESERVED_31_30_SHIFT
+#undef DDR_PHY_DX8SL1OSC_RESERVED_31_30_MASK
 #define DDR_PHY_DX8SL1OSC_RESERVED_31_30_DEFVAL                0x00019FFE
 #define DDR_PHY_DX8SL1OSC_RESERVED_31_30_SHIFT                 30
 #define DDR_PHY_DX8SL1OSC_RESERVED_31_30_MASK                  0xC0000000U
@@ -18586,9 +18586,9 @@
 /*
 * Enable Clock Gating for DX ddr_clk
 */
-#undef DDR_PHY_DX8SL1OSC_GATEDXRDCLK_DEFVAL 
-#undef DDR_PHY_DX8SL1OSC_GATEDXRDCLK_SHIFT 
-#undef DDR_PHY_DX8SL1OSC_GATEDXRDCLK_MASK 
+#undef DDR_PHY_DX8SL1OSC_GATEDXRDCLK_DEFVAL
+#undef DDR_PHY_DX8SL1OSC_GATEDXRDCLK_SHIFT
+#undef DDR_PHY_DX8SL1OSC_GATEDXRDCLK_MASK
 #define DDR_PHY_DX8SL1OSC_GATEDXRDCLK_DEFVAL                   0x00019FFE
 #define DDR_PHY_DX8SL1OSC_GATEDXRDCLK_SHIFT                    28
 #define DDR_PHY_DX8SL1OSC_GATEDXRDCLK_MASK                     0x30000000U
@@ -18596,9 +18596,9 @@
 /*
 * Enable Clock Gating for DX ctl_rd_clk
 */
-#undef DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_DEFVAL 
-#undef DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_SHIFT 
-#undef DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_MASK 
+#undef DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_DEFVAL
+#undef DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_SHIFT
+#undef DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_MASK
 #define DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_DEFVAL                  0x00019FFE
 #define DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_SHIFT                   26
 #define DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_MASK                    0x0C000000U
@@ -18606,9 +18606,9 @@
 /*
 * Enable Clock Gating for DX ctl_clk
 */
-#undef DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_DEFVAL 
-#undef DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_SHIFT 
-#undef DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_MASK 
+#undef DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_DEFVAL
+#undef DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_SHIFT
+#undef DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_MASK
 #define DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_DEFVAL                  0x00019FFE
 #define DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_SHIFT                   24
 #define DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_MASK                    0x03000000U
@@ -18617,9 +18617,9 @@
 * Selects the level to which clocks will be stalled when clock gating is e
     * nabled.
 */
-#undef DDR_PHY_DX8SL1OSC_CLKLEVEL_DEFVAL 
-#undef DDR_PHY_DX8SL1OSC_CLKLEVEL_SHIFT 
-#undef DDR_PHY_DX8SL1OSC_CLKLEVEL_MASK 
+#undef DDR_PHY_DX8SL1OSC_CLKLEVEL_DEFVAL
+#undef DDR_PHY_DX8SL1OSC_CLKLEVEL_SHIFT
+#undef DDR_PHY_DX8SL1OSC_CLKLEVEL_MASK
 #define DDR_PHY_DX8SL1OSC_CLKLEVEL_DEFVAL                      0x00019FFE
 #define DDR_PHY_DX8SL1OSC_CLKLEVEL_SHIFT                       22
 #define DDR_PHY_DX8SL1OSC_CLKLEVEL_MASK                        0x00C00000U
@@ -18627,9 +18627,9 @@
 /*
 * Loopback Mode
 */
-#undef DDR_PHY_DX8SL1OSC_LBMODE_DEFVAL 
-#undef DDR_PHY_DX8SL1OSC_LBMODE_SHIFT 
-#undef DDR_PHY_DX8SL1OSC_LBMODE_MASK 
+#undef DDR_PHY_DX8SL1OSC_LBMODE_DEFVAL
+#undef DDR_PHY_DX8SL1OSC_LBMODE_SHIFT
+#undef DDR_PHY_DX8SL1OSC_LBMODE_MASK
 #define DDR_PHY_DX8SL1OSC_LBMODE_DEFVAL                        0x00019FFE
 #define DDR_PHY_DX8SL1OSC_LBMODE_SHIFT                         21
 #define DDR_PHY_DX8SL1OSC_LBMODE_MASK                          0x00200000U
@@ -18637,9 +18637,9 @@
 /*
 * Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
 */
-#undef DDR_PHY_DX8SL1OSC_LBGSDQS_DEFVAL 
-#undef DDR_PHY_DX8SL1OSC_LBGSDQS_SHIFT 
-#undef DDR_PHY_DX8SL1OSC_LBGSDQS_MASK 
+#undef DDR_PHY_DX8SL1OSC_LBGSDQS_DEFVAL
+#undef DDR_PHY_DX8SL1OSC_LBGSDQS_SHIFT
+#undef DDR_PHY_DX8SL1OSC_LBGSDQS_MASK
 #define DDR_PHY_DX8SL1OSC_LBGSDQS_DEFVAL                       0x00019FFE
 #define DDR_PHY_DX8SL1OSC_LBGSDQS_SHIFT                        20
 #define DDR_PHY_DX8SL1OSC_LBGSDQS_MASK                         0x00100000U
@@ -18647,9 +18647,9 @@
 /*
 * Loopback DQS Gating
 */
-#undef DDR_PHY_DX8SL1OSC_LBGDQS_DEFVAL 
-#undef DDR_PHY_DX8SL1OSC_LBGDQS_SHIFT 
-#undef DDR_PHY_DX8SL1OSC_LBGDQS_MASK 
+#undef DDR_PHY_DX8SL1OSC_LBGDQS_DEFVAL
+#undef DDR_PHY_DX8SL1OSC_LBGDQS_SHIFT
+#undef DDR_PHY_DX8SL1OSC_LBGDQS_MASK
 #define DDR_PHY_DX8SL1OSC_LBGDQS_DEFVAL                        0x00019FFE
 #define DDR_PHY_DX8SL1OSC_LBGDQS_SHIFT                         18
 #define DDR_PHY_DX8SL1OSC_LBGDQS_MASK                          0x000C0000U
@@ -18657,9 +18657,9 @@
 /*
 * Loopback DQS Shift
 */
-#undef DDR_PHY_DX8SL1OSC_LBDQSS_DEFVAL 
-#undef DDR_PHY_DX8SL1OSC_LBDQSS_SHIFT 
-#undef DDR_PHY_DX8SL1OSC_LBDQSS_MASK 
+#undef DDR_PHY_DX8SL1OSC_LBDQSS_DEFVAL
+#undef DDR_PHY_DX8SL1OSC_LBDQSS_SHIFT
+#undef DDR_PHY_DX8SL1OSC_LBDQSS_MASK
 #define DDR_PHY_DX8SL1OSC_LBDQSS_DEFVAL                        0x00019FFE
 #define DDR_PHY_DX8SL1OSC_LBDQSS_SHIFT                         17
 #define DDR_PHY_DX8SL1OSC_LBDQSS_MASK                          0x00020000U
@@ -18667,9 +18667,9 @@
 /*
 * PHY High-Speed Reset
 */
-#undef DDR_PHY_DX8SL1OSC_PHYHRST_DEFVAL 
-#undef DDR_PHY_DX8SL1OSC_PHYHRST_SHIFT 
-#undef DDR_PHY_DX8SL1OSC_PHYHRST_MASK 
+#undef DDR_PHY_DX8SL1OSC_PHYHRST_DEFVAL
+#undef DDR_PHY_DX8SL1OSC_PHYHRST_SHIFT
+#undef DDR_PHY_DX8SL1OSC_PHYHRST_MASK
 #define DDR_PHY_DX8SL1OSC_PHYHRST_DEFVAL                       0x00019FFE
 #define DDR_PHY_DX8SL1OSC_PHYHRST_SHIFT                        16
 #define DDR_PHY_DX8SL1OSC_PHYHRST_MASK                         0x00010000U
@@ -18677,9 +18677,9 @@
 /*
 * PHY FIFO Reset
 */
-#undef DDR_PHY_DX8SL1OSC_PHYFRST_DEFVAL 
-#undef DDR_PHY_DX8SL1OSC_PHYFRST_SHIFT 
-#undef DDR_PHY_DX8SL1OSC_PHYFRST_MASK 
+#undef DDR_PHY_DX8SL1OSC_PHYFRST_DEFVAL
+#undef DDR_PHY_DX8SL1OSC_PHYFRST_SHIFT
+#undef DDR_PHY_DX8SL1OSC_PHYFRST_MASK
 #define DDR_PHY_DX8SL1OSC_PHYFRST_DEFVAL                       0x00019FFE
 #define DDR_PHY_DX8SL1OSC_PHYFRST_SHIFT                        15
 #define DDR_PHY_DX8SL1OSC_PHYFRST_MASK                         0x00008000U
@@ -18687,9 +18687,9 @@
 /*
 * Delay Line Test Start
 */
-#undef DDR_PHY_DX8SL1OSC_DLTST_DEFVAL 
-#undef DDR_PHY_DX8SL1OSC_DLTST_SHIFT 
-#undef DDR_PHY_DX8SL1OSC_DLTST_MASK 
+#undef DDR_PHY_DX8SL1OSC_DLTST_DEFVAL
+#undef DDR_PHY_DX8SL1OSC_DLTST_SHIFT
+#undef DDR_PHY_DX8SL1OSC_DLTST_MASK
 #define DDR_PHY_DX8SL1OSC_DLTST_DEFVAL                         0x00019FFE
 #define DDR_PHY_DX8SL1OSC_DLTST_SHIFT                          14
 #define DDR_PHY_DX8SL1OSC_DLTST_MASK                           0x00004000U
@@ -18697,9 +18697,9 @@
 /*
 * Delay Line Test Mode
 */
-#undef DDR_PHY_DX8SL1OSC_DLTMODE_DEFVAL 
-#undef DDR_PHY_DX8SL1OSC_DLTMODE_SHIFT 
-#undef DDR_PHY_DX8SL1OSC_DLTMODE_MASK 
+#undef DDR_PHY_DX8SL1OSC_DLTMODE_DEFVAL
+#undef DDR_PHY_DX8SL1OSC_DLTMODE_SHIFT
+#undef DDR_PHY_DX8SL1OSC_DLTMODE_MASK
 #define DDR_PHY_DX8SL1OSC_DLTMODE_DEFVAL                       0x00019FFE
 #define DDR_PHY_DX8SL1OSC_DLTMODE_SHIFT                        13
 #define DDR_PHY_DX8SL1OSC_DLTMODE_MASK                         0x00002000U
@@ -18707,9 +18707,9 @@
 /*
 * Reserved. Caution, do not write to this register field.
 */
-#undef DDR_PHY_DX8SL1OSC_RESERVED_12_11_DEFVAL 
-#undef DDR_PHY_DX8SL1OSC_RESERVED_12_11_SHIFT 
-#undef DDR_PHY_DX8SL1OSC_RESERVED_12_11_MASK 
+#undef DDR_PHY_DX8SL1OSC_RESERVED_12_11_DEFVAL
+#undef DDR_PHY_DX8SL1OSC_RESERVED_12_11_SHIFT
+#undef DDR_PHY_DX8SL1OSC_RESERVED_12_11_MASK
 #define DDR_PHY_DX8SL1OSC_RESERVED_12_11_DEFVAL                0x00019FFE
 #define DDR_PHY_DX8SL1OSC_RESERVED_12_11_SHIFT                 11
 #define DDR_PHY_DX8SL1OSC_RESERVED_12_11_MASK                  0x00001800U
@@ -18717,9 +18717,9 @@
 /*
 * Oscillator Mode Write-Data Delay Line Select
 */
-#undef DDR_PHY_DX8SL1OSC_OSCWDDL_DEFVAL 
-#undef DDR_PHY_DX8SL1OSC_OSCWDDL_SHIFT 
-#undef DDR_PHY_DX8SL1OSC_OSCWDDL_MASK 
+#undef DDR_PHY_DX8SL1OSC_OSCWDDL_DEFVAL
+#undef DDR_PHY_DX8SL1OSC_OSCWDDL_SHIFT
+#undef DDR_PHY_DX8SL1OSC_OSCWDDL_MASK
 #define DDR_PHY_DX8SL1OSC_OSCWDDL_DEFVAL                       0x00019FFE
 #define DDR_PHY_DX8SL1OSC_OSCWDDL_SHIFT                        9
 #define DDR_PHY_DX8SL1OSC_OSCWDDL_MASK                         0x00000600U
@@ -18727,9 +18727,9 @@
 /*
 * Reserved. Caution, do not write to this register field.
 */
-#undef DDR_PHY_DX8SL1OSC_RESERVED_8_7_DEFVAL 
-#undef DDR_PHY_DX8SL1OSC_RESERVED_8_7_SHIFT 
-#undef DDR_PHY_DX8SL1OSC_RESERVED_8_7_MASK 
+#undef DDR_PHY_DX8SL1OSC_RESERVED_8_7_DEFVAL
+#undef DDR_PHY_DX8SL1OSC_RESERVED_8_7_SHIFT
+#undef DDR_PHY_DX8SL1OSC_RESERVED_8_7_MASK
 #define DDR_PHY_DX8SL1OSC_RESERVED_8_7_DEFVAL                  0x00019FFE
 #define DDR_PHY_DX8SL1OSC_RESERVED_8_7_SHIFT                   7
 #define DDR_PHY_DX8SL1OSC_RESERVED_8_7_MASK                    0x00000180U
@@ -18737,9 +18737,9 @@
 /*
 * Oscillator Mode Write-Leveling Delay Line Select
 */
-#undef DDR_PHY_DX8SL1OSC_OSCWDL_DEFVAL 
-#undef DDR_PHY_DX8SL1OSC_OSCWDL_SHIFT 
-#undef DDR_PHY_DX8SL1OSC_OSCWDL_MASK 
+#undef DDR_PHY_DX8SL1OSC_OSCWDL_DEFVAL
+#undef DDR_PHY_DX8SL1OSC_OSCWDL_SHIFT
+#undef DDR_PHY_DX8SL1OSC_OSCWDL_MASK
 #define DDR_PHY_DX8SL1OSC_OSCWDL_DEFVAL                        0x00019FFE
 #define DDR_PHY_DX8SL1OSC_OSCWDL_SHIFT                         5
 #define DDR_PHY_DX8SL1OSC_OSCWDL_MASK                          0x00000060U
@@ -18747,9 +18747,9 @@
 /*
 * Oscillator Mode Division
 */
-#undef DDR_PHY_DX8SL1OSC_OSCDIV_DEFVAL 
-#undef DDR_PHY_DX8SL1OSC_OSCDIV_SHIFT 
-#undef DDR_PHY_DX8SL1OSC_OSCDIV_MASK 
+#undef DDR_PHY_DX8SL1OSC_OSCDIV_DEFVAL
+#undef DDR_PHY_DX8SL1OSC_OSCDIV_SHIFT
+#undef DDR_PHY_DX8SL1OSC_OSCDIV_MASK
 #define DDR_PHY_DX8SL1OSC_OSCDIV_DEFVAL                        0x00019FFE
 #define DDR_PHY_DX8SL1OSC_OSCDIV_SHIFT                         1
 #define DDR_PHY_DX8SL1OSC_OSCDIV_MASK                          0x0000001EU
@@ -18757,9 +18757,9 @@
 /*
 * Oscillator Enable
 */
-#undef DDR_PHY_DX8SL1OSC_OSCEN_DEFVAL 
-#undef DDR_PHY_DX8SL1OSC_OSCEN_SHIFT 
-#undef DDR_PHY_DX8SL1OSC_OSCEN_MASK 
+#undef DDR_PHY_DX8SL1OSC_OSCEN_DEFVAL
+#undef DDR_PHY_DX8SL1OSC_OSCEN_SHIFT
+#undef DDR_PHY_DX8SL1OSC_OSCEN_MASK
 #define DDR_PHY_DX8SL1OSC_OSCEN_DEFVAL                         0x00019FFE
 #define DDR_PHY_DX8SL1OSC_OSCEN_SHIFT                          0
 #define DDR_PHY_DX8SL1OSC_OSCEN_MASK                           0x00000001U
@@ -18767,9 +18767,9 @@
 /*
 * PLL Bypass
 */
-#undef DDR_PHY_DX8SL1PLLCR0_PLLBYP_DEFVAL 
-#undef DDR_PHY_DX8SL1PLLCR0_PLLBYP_SHIFT 
-#undef DDR_PHY_DX8SL1PLLCR0_PLLBYP_MASK 
+#undef DDR_PHY_DX8SL1PLLCR0_PLLBYP_DEFVAL
+#undef DDR_PHY_DX8SL1PLLCR0_PLLBYP_SHIFT
+#undef DDR_PHY_DX8SL1PLLCR0_PLLBYP_MASK
 #define DDR_PHY_DX8SL1PLLCR0_PLLBYP_DEFVAL                     0x001C0000
 #define DDR_PHY_DX8SL1PLLCR0_PLLBYP_SHIFT                      31
 #define DDR_PHY_DX8SL1PLLCR0_PLLBYP_MASK                       0x80000000U
@@ -18777,9 +18777,9 @@
 /*
 * PLL Reset
 */
-#undef DDR_PHY_DX8SL1PLLCR0_PLLRST_DEFVAL 
-#undef DDR_PHY_DX8SL1PLLCR0_PLLRST_SHIFT 
-#undef DDR_PHY_DX8SL1PLLCR0_PLLRST_MASK 
+#undef DDR_PHY_DX8SL1PLLCR0_PLLRST_DEFVAL
+#undef DDR_PHY_DX8SL1PLLCR0_PLLRST_SHIFT
+#undef DDR_PHY_DX8SL1PLLCR0_PLLRST_MASK
 #define DDR_PHY_DX8SL1PLLCR0_PLLRST_DEFVAL                     0x001C0000
 #define DDR_PHY_DX8SL1PLLCR0_PLLRST_SHIFT                      30
 #define DDR_PHY_DX8SL1PLLCR0_PLLRST_MASK                       0x40000000U
@@ -18787,9 +18787,9 @@
 /*
 * PLL Power Down
 */
-#undef DDR_PHY_DX8SL1PLLCR0_PLLPD_DEFVAL 
-#undef DDR_PHY_DX8SL1PLLCR0_PLLPD_SHIFT 
-#undef DDR_PHY_DX8SL1PLLCR0_PLLPD_MASK 
+#undef DDR_PHY_DX8SL1PLLCR0_PLLPD_DEFVAL
+#undef DDR_PHY_DX8SL1PLLCR0_PLLPD_SHIFT
+#undef DDR_PHY_DX8SL1PLLCR0_PLLPD_MASK
 #define DDR_PHY_DX8SL1PLLCR0_PLLPD_DEFVAL                      0x001C0000
 #define DDR_PHY_DX8SL1PLLCR0_PLLPD_SHIFT                       29
 #define DDR_PHY_DX8SL1PLLCR0_PLLPD_MASK                        0x20000000U
@@ -18797,9 +18797,9 @@
 /*
 * Reference Stop Mode
 */
-#undef DDR_PHY_DX8SL1PLLCR0_RSTOPM_DEFVAL 
-#undef DDR_PHY_DX8SL1PLLCR0_RSTOPM_SHIFT 
-#undef DDR_PHY_DX8SL1PLLCR0_RSTOPM_MASK 
+#undef DDR_PHY_DX8SL1PLLCR0_RSTOPM_DEFVAL
+#undef DDR_PHY_DX8SL1PLLCR0_RSTOPM_SHIFT
+#undef DDR_PHY_DX8SL1PLLCR0_RSTOPM_MASK
 #define DDR_PHY_DX8SL1PLLCR0_RSTOPM_DEFVAL                     0x001C0000
 #define DDR_PHY_DX8SL1PLLCR0_RSTOPM_SHIFT                      28
 #define DDR_PHY_DX8SL1PLLCR0_RSTOPM_MASK                       0x10000000U
@@ -18807,9 +18807,9 @@
 /*
 * PLL Frequency Select
 */
-#undef DDR_PHY_DX8SL1PLLCR0_FRQSEL_DEFVAL 
-#undef DDR_PHY_DX8SL1PLLCR0_FRQSEL_SHIFT 
-#undef DDR_PHY_DX8SL1PLLCR0_FRQSEL_MASK 
+#undef DDR_PHY_DX8SL1PLLCR0_FRQSEL_DEFVAL
+#undef DDR_PHY_DX8SL1PLLCR0_FRQSEL_SHIFT
+#undef DDR_PHY_DX8SL1PLLCR0_FRQSEL_MASK
 #define DDR_PHY_DX8SL1PLLCR0_FRQSEL_DEFVAL                     0x001C0000
 #define DDR_PHY_DX8SL1PLLCR0_FRQSEL_SHIFT                      24
 #define DDR_PHY_DX8SL1PLLCR0_FRQSEL_MASK                       0x0F000000U
@@ -18817,9 +18817,9 @@
 /*
 * Relock Mode
 */
-#undef DDR_PHY_DX8SL1PLLCR0_RLOCKM_DEFVAL 
-#undef DDR_PHY_DX8SL1PLLCR0_RLOCKM_SHIFT 
-#undef DDR_PHY_DX8SL1PLLCR0_RLOCKM_MASK 
+#undef DDR_PHY_DX8SL1PLLCR0_RLOCKM_DEFVAL
+#undef DDR_PHY_DX8SL1PLLCR0_RLOCKM_SHIFT
+#undef DDR_PHY_DX8SL1PLLCR0_RLOCKM_MASK
 #define DDR_PHY_DX8SL1PLLCR0_RLOCKM_DEFVAL                     0x001C0000
 #define DDR_PHY_DX8SL1PLLCR0_RLOCKM_SHIFT                      23
 #define DDR_PHY_DX8SL1PLLCR0_RLOCKM_MASK                       0x00800000U
@@ -18827,9 +18827,9 @@
 /*
 * Charge Pump Proportional Current Control
 */
-#undef DDR_PHY_DX8SL1PLLCR0_CPPC_DEFVAL 
-#undef DDR_PHY_DX8SL1PLLCR0_CPPC_SHIFT 
-#undef DDR_PHY_DX8SL1PLLCR0_CPPC_MASK 
+#undef DDR_PHY_DX8SL1PLLCR0_CPPC_DEFVAL
+#undef DDR_PHY_DX8SL1PLLCR0_CPPC_SHIFT
+#undef DDR_PHY_DX8SL1PLLCR0_CPPC_MASK
 #define DDR_PHY_DX8SL1PLLCR0_CPPC_DEFVAL                       0x001C0000
 #define DDR_PHY_DX8SL1PLLCR0_CPPC_SHIFT                        17
 #define DDR_PHY_DX8SL1PLLCR0_CPPC_MASK                         0x007E0000U
@@ -18837,9 +18837,9 @@
 /*
 * Charge Pump Integrating Current Control
 */
-#undef DDR_PHY_DX8SL1PLLCR0_CPIC_DEFVAL 
-#undef DDR_PHY_DX8SL1PLLCR0_CPIC_SHIFT 
-#undef DDR_PHY_DX8SL1PLLCR0_CPIC_MASK 
+#undef DDR_PHY_DX8SL1PLLCR0_CPIC_DEFVAL
+#undef DDR_PHY_DX8SL1PLLCR0_CPIC_SHIFT
+#undef DDR_PHY_DX8SL1PLLCR0_CPIC_MASK
 #define DDR_PHY_DX8SL1PLLCR0_CPIC_DEFVAL                       0x001C0000
 #define DDR_PHY_DX8SL1PLLCR0_CPIC_SHIFT                        13
 #define DDR_PHY_DX8SL1PLLCR0_CPIC_MASK                         0x0001E000U
@@ -18847,9 +18847,9 @@
 /*
 * Gear Shift
 */
-#undef DDR_PHY_DX8SL1PLLCR0_GSHIFT_DEFVAL 
-#undef DDR_PHY_DX8SL1PLLCR0_GSHIFT_SHIFT 
-#undef DDR_PHY_DX8SL1PLLCR0_GSHIFT_MASK 
+#undef DDR_PHY_DX8SL1PLLCR0_GSHIFT_DEFVAL
+#undef DDR_PHY_DX8SL1PLLCR0_GSHIFT_SHIFT
+#undef DDR_PHY_DX8SL1PLLCR0_GSHIFT_MASK
 #define DDR_PHY_DX8SL1PLLCR0_GSHIFT_DEFVAL                     0x001C0000
 #define DDR_PHY_DX8SL1PLLCR0_GSHIFT_SHIFT                      12
 #define DDR_PHY_DX8SL1PLLCR0_GSHIFT_MASK                       0x00001000U
@@ -18857,9 +18857,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9_DEFVAL 
-#undef DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9_SHIFT 
-#undef DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9_MASK 
+#undef DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9_DEFVAL
+#undef DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9_SHIFT
+#undef DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9_MASK
 #define DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9_DEFVAL              0x001C0000
 #define DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9_SHIFT               9
 #define DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9_MASK                0x00000E00U
@@ -18867,9 +18867,9 @@
 /*
 * Analog Test Enable (ATOEN)
 */
-#undef DDR_PHY_DX8SL1PLLCR0_ATOEN_DEFVAL 
-#undef DDR_PHY_DX8SL1PLLCR0_ATOEN_SHIFT 
-#undef DDR_PHY_DX8SL1PLLCR0_ATOEN_MASK 
+#undef DDR_PHY_DX8SL1PLLCR0_ATOEN_DEFVAL
+#undef DDR_PHY_DX8SL1PLLCR0_ATOEN_SHIFT
+#undef DDR_PHY_DX8SL1PLLCR0_ATOEN_MASK
 #define DDR_PHY_DX8SL1PLLCR0_ATOEN_DEFVAL                      0x001C0000
 #define DDR_PHY_DX8SL1PLLCR0_ATOEN_SHIFT                       8
 #define DDR_PHY_DX8SL1PLLCR0_ATOEN_MASK                        0x00000100U
@@ -18877,9 +18877,9 @@
 /*
 * Analog Test Control
 */
-#undef DDR_PHY_DX8SL1PLLCR0_ATC_DEFVAL 
-#undef DDR_PHY_DX8SL1PLLCR0_ATC_SHIFT 
-#undef DDR_PHY_DX8SL1PLLCR0_ATC_MASK 
+#undef DDR_PHY_DX8SL1PLLCR0_ATC_DEFVAL
+#undef DDR_PHY_DX8SL1PLLCR0_ATC_SHIFT
+#undef DDR_PHY_DX8SL1PLLCR0_ATC_MASK
 #define DDR_PHY_DX8SL1PLLCR0_ATC_DEFVAL                        0x001C0000
 #define DDR_PHY_DX8SL1PLLCR0_ATC_SHIFT                         4
 #define DDR_PHY_DX8SL1PLLCR0_ATC_MASK                          0x000000F0U
@@ -18887,9 +18887,9 @@
 /*
 * Digital Test Control
 */
-#undef DDR_PHY_DX8SL1PLLCR0_DTC_DEFVAL 
-#undef DDR_PHY_DX8SL1PLLCR0_DTC_SHIFT 
-#undef DDR_PHY_DX8SL1PLLCR0_DTC_MASK 
+#undef DDR_PHY_DX8SL1PLLCR0_DTC_DEFVAL
+#undef DDR_PHY_DX8SL1PLLCR0_DTC_SHIFT
+#undef DDR_PHY_DX8SL1PLLCR0_DTC_MASK
 #define DDR_PHY_DX8SL1PLLCR0_DTC_DEFVAL                        0x001C0000
 #define DDR_PHY_DX8SL1PLLCR0_DTC_SHIFT                         0
 #define DDR_PHY_DX8SL1PLLCR0_DTC_MASK                          0x0000000FU
@@ -18897,9 +18897,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_DEFVAL 
-#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_SHIFT 
-#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_MASK 
+#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_DEFVAL
+#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_SHIFT
+#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_MASK
 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_DEFVAL             0x01264000
 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_SHIFT              25
 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_MASK               0xFE000000U
@@ -18907,9 +18907,9 @@
 /*
 * Read Path Rise-to-Rise Mode
 */
-#undef DDR_PHY_DX8SL1DQSCTL_RRRMODE_DEFVAL 
-#undef DDR_PHY_DX8SL1DQSCTL_RRRMODE_SHIFT 
-#undef DDR_PHY_DX8SL1DQSCTL_RRRMODE_MASK 
+#undef DDR_PHY_DX8SL1DQSCTL_RRRMODE_DEFVAL
+#undef DDR_PHY_DX8SL1DQSCTL_RRRMODE_SHIFT
+#undef DDR_PHY_DX8SL1DQSCTL_RRRMODE_MASK
 #define DDR_PHY_DX8SL1DQSCTL_RRRMODE_DEFVAL                    0x01264000
 #define DDR_PHY_DX8SL1DQSCTL_RRRMODE_SHIFT                     24
 #define DDR_PHY_DX8SL1DQSCTL_RRRMODE_MASK                      0x01000000U
@@ -18917,9 +18917,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_DEFVAL 
-#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_SHIFT 
-#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_MASK 
+#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_DEFVAL
+#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_SHIFT
+#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_MASK
 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_DEFVAL             0x01264000
 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_SHIFT              22
 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_MASK               0x00C00000U
@@ -18927,9 +18927,9 @@
 /*
 * Write Path Rise-to-Rise Mode
 */
-#undef DDR_PHY_DX8SL1DQSCTL_WRRMODE_DEFVAL 
-#undef DDR_PHY_DX8SL1DQSCTL_WRRMODE_SHIFT 
-#undef DDR_PHY_DX8SL1DQSCTL_WRRMODE_MASK 
+#undef DDR_PHY_DX8SL1DQSCTL_WRRMODE_DEFVAL
+#undef DDR_PHY_DX8SL1DQSCTL_WRRMODE_SHIFT
+#undef DDR_PHY_DX8SL1DQSCTL_WRRMODE_MASK
 #define DDR_PHY_DX8SL1DQSCTL_WRRMODE_DEFVAL                    0x01264000
 #define DDR_PHY_DX8SL1DQSCTL_WRRMODE_SHIFT                     21
 #define DDR_PHY_DX8SL1DQSCTL_WRRMODE_MASK                      0x00200000U
@@ -18937,9 +18937,9 @@
 /*
 * DQS Gate Extension
 */
-#undef DDR_PHY_DX8SL1DQSCTL_DQSGX_DEFVAL 
-#undef DDR_PHY_DX8SL1DQSCTL_DQSGX_SHIFT 
-#undef DDR_PHY_DX8SL1DQSCTL_DQSGX_MASK 
+#undef DDR_PHY_DX8SL1DQSCTL_DQSGX_DEFVAL
+#undef DDR_PHY_DX8SL1DQSCTL_DQSGX_SHIFT
+#undef DDR_PHY_DX8SL1DQSCTL_DQSGX_MASK
 #define DDR_PHY_DX8SL1DQSCTL_DQSGX_DEFVAL                      0x01264000
 #define DDR_PHY_DX8SL1DQSCTL_DQSGX_SHIFT                       19
 #define DDR_PHY_DX8SL1DQSCTL_DQSGX_MASK                        0x00180000U
@@ -18947,9 +18947,9 @@
 /*
 * Low Power PLL Power Down
 */
-#undef DDR_PHY_DX8SL1DQSCTL_LPPLLPD_DEFVAL 
-#undef DDR_PHY_DX8SL1DQSCTL_LPPLLPD_SHIFT 
-#undef DDR_PHY_DX8SL1DQSCTL_LPPLLPD_MASK 
+#undef DDR_PHY_DX8SL1DQSCTL_LPPLLPD_DEFVAL
+#undef DDR_PHY_DX8SL1DQSCTL_LPPLLPD_SHIFT
+#undef DDR_PHY_DX8SL1DQSCTL_LPPLLPD_MASK
 #define DDR_PHY_DX8SL1DQSCTL_LPPLLPD_DEFVAL                    0x01264000
 #define DDR_PHY_DX8SL1DQSCTL_LPPLLPD_SHIFT                     18
 #define DDR_PHY_DX8SL1DQSCTL_LPPLLPD_MASK                      0x00040000U
@@ -18957,9 +18957,9 @@
 /*
 * Low Power I/O Power Down
 */
-#undef DDR_PHY_DX8SL1DQSCTL_LPIOPD_DEFVAL 
-#undef DDR_PHY_DX8SL1DQSCTL_LPIOPD_SHIFT 
-#undef DDR_PHY_DX8SL1DQSCTL_LPIOPD_MASK 
+#undef DDR_PHY_DX8SL1DQSCTL_LPIOPD_DEFVAL
+#undef DDR_PHY_DX8SL1DQSCTL_LPIOPD_SHIFT
+#undef DDR_PHY_DX8SL1DQSCTL_LPIOPD_MASK
 #define DDR_PHY_DX8SL1DQSCTL_LPIOPD_DEFVAL                     0x01264000
 #define DDR_PHY_DX8SL1DQSCTL_LPIOPD_SHIFT                      17
 #define DDR_PHY_DX8SL1DQSCTL_LPIOPD_MASK                       0x00020000U
@@ -18967,9 +18967,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_DEFVAL 
-#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_SHIFT 
-#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_MASK 
+#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_DEFVAL
+#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_SHIFT
+#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_MASK
 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_DEFVAL             0x01264000
 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_SHIFT              15
 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_MASK               0x00018000U
@@ -18977,9 +18977,9 @@
 /*
 * QS Counter Enable
 */
-#undef DDR_PHY_DX8SL1DQSCTL_QSCNTEN_DEFVAL 
-#undef DDR_PHY_DX8SL1DQSCTL_QSCNTEN_SHIFT 
-#undef DDR_PHY_DX8SL1DQSCTL_QSCNTEN_MASK 
+#undef DDR_PHY_DX8SL1DQSCTL_QSCNTEN_DEFVAL
+#undef DDR_PHY_DX8SL1DQSCTL_QSCNTEN_SHIFT
+#undef DDR_PHY_DX8SL1DQSCTL_QSCNTEN_MASK
 #define DDR_PHY_DX8SL1DQSCTL_QSCNTEN_DEFVAL                    0x01264000
 #define DDR_PHY_DX8SL1DQSCTL_QSCNTEN_SHIFT                     14
 #define DDR_PHY_DX8SL1DQSCTL_QSCNTEN_MASK                      0x00004000U
@@ -18987,9 +18987,9 @@
 /*
 * Unused DQ I/O Mode
 */
-#undef DDR_PHY_DX8SL1DQSCTL_UDQIOM_DEFVAL 
-#undef DDR_PHY_DX8SL1DQSCTL_UDQIOM_SHIFT 
-#undef DDR_PHY_DX8SL1DQSCTL_UDQIOM_MASK 
+#undef DDR_PHY_DX8SL1DQSCTL_UDQIOM_DEFVAL
+#undef DDR_PHY_DX8SL1DQSCTL_UDQIOM_SHIFT
+#undef DDR_PHY_DX8SL1DQSCTL_UDQIOM_MASK
 #define DDR_PHY_DX8SL1DQSCTL_UDQIOM_DEFVAL                     0x01264000
 #define DDR_PHY_DX8SL1DQSCTL_UDQIOM_SHIFT                      13
 #define DDR_PHY_DX8SL1DQSCTL_UDQIOM_MASK                       0x00002000U
@@ -18997,9 +18997,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_DEFVAL 
-#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_SHIFT 
-#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_MASK 
+#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_DEFVAL
+#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_SHIFT
+#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_MASK
 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_DEFVAL             0x01264000
 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_SHIFT              10
 #define DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_MASK               0x00001C00U
@@ -19007,9 +19007,9 @@
 /*
 * Data Slew Rate
 */
-#undef DDR_PHY_DX8SL1DQSCTL_DXSR_DEFVAL 
-#undef DDR_PHY_DX8SL1DQSCTL_DXSR_SHIFT 
-#undef DDR_PHY_DX8SL1DQSCTL_DXSR_MASK 
+#undef DDR_PHY_DX8SL1DQSCTL_DXSR_DEFVAL
+#undef DDR_PHY_DX8SL1DQSCTL_DXSR_SHIFT
+#undef DDR_PHY_DX8SL1DQSCTL_DXSR_MASK
 #define DDR_PHY_DX8SL1DQSCTL_DXSR_DEFVAL                       0x01264000
 #define DDR_PHY_DX8SL1DQSCTL_DXSR_SHIFT                        8
 #define DDR_PHY_DX8SL1DQSCTL_DXSR_MASK                         0x00000300U
@@ -19017,9 +19017,9 @@
 /*
 * DQS_N Resistor
 */
-#undef DDR_PHY_DX8SL1DQSCTL_DQSNRES_DEFVAL 
-#undef DDR_PHY_DX8SL1DQSCTL_DQSNRES_SHIFT 
-#undef DDR_PHY_DX8SL1DQSCTL_DQSNRES_MASK 
+#undef DDR_PHY_DX8SL1DQSCTL_DQSNRES_DEFVAL
+#undef DDR_PHY_DX8SL1DQSCTL_DQSNRES_SHIFT
+#undef DDR_PHY_DX8SL1DQSCTL_DQSNRES_MASK
 #define DDR_PHY_DX8SL1DQSCTL_DQSNRES_DEFVAL                    0x01264000
 #define DDR_PHY_DX8SL1DQSCTL_DQSNRES_SHIFT                     4
 #define DDR_PHY_DX8SL1DQSCTL_DQSNRES_MASK                      0x000000F0U
@@ -19027,9 +19027,9 @@
 /*
 * DQS Resistor
 */
-#undef DDR_PHY_DX8SL1DQSCTL_DQSRES_DEFVAL 
-#undef DDR_PHY_DX8SL1DQSCTL_DQSRES_SHIFT 
-#undef DDR_PHY_DX8SL1DQSCTL_DQSRES_MASK 
+#undef DDR_PHY_DX8SL1DQSCTL_DQSRES_DEFVAL
+#undef DDR_PHY_DX8SL1DQSCTL_DQSRES_SHIFT
+#undef DDR_PHY_DX8SL1DQSCTL_DQSRES_MASK
 #define DDR_PHY_DX8SL1DQSCTL_DQSRES_DEFVAL                     0x01264000
 #define DDR_PHY_DX8SL1DQSCTL_DQSRES_SHIFT                      0
 #define DDR_PHY_DX8SL1DQSCTL_DQSRES_MASK                       0x0000000FU
@@ -19037,9 +19037,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_DEFVAL 
-#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_SHIFT 
-#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_MASK 
+#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_DEFVAL
+#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_SHIFT
+#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_MASK
 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_DEFVAL             0x00141800
 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_SHIFT              24
 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_MASK               0xFF000000U
@@ -19047,9 +19047,9 @@
 /*
 * Configurable Read Data Enable
 */
-#undef DDR_PHY_DX8SL1DXCTL2_CRDEN_DEFVAL 
-#undef DDR_PHY_DX8SL1DXCTL2_CRDEN_SHIFT 
-#undef DDR_PHY_DX8SL1DXCTL2_CRDEN_MASK 
+#undef DDR_PHY_DX8SL1DXCTL2_CRDEN_DEFVAL
+#undef DDR_PHY_DX8SL1DXCTL2_CRDEN_SHIFT
+#undef DDR_PHY_DX8SL1DXCTL2_CRDEN_MASK
 #define DDR_PHY_DX8SL1DXCTL2_CRDEN_DEFVAL                      0x00141800
 #define DDR_PHY_DX8SL1DXCTL2_CRDEN_SHIFT                       23
 #define DDR_PHY_DX8SL1DXCTL2_CRDEN_MASK                        0x00800000U
@@ -19057,9 +19057,9 @@
 /*
 * OX Extension during Post-amble
 */
-#undef DDR_PHY_DX8SL1DXCTL2_POSOEX_DEFVAL 
-#undef DDR_PHY_DX8SL1DXCTL2_POSOEX_SHIFT 
-#undef DDR_PHY_DX8SL1DXCTL2_POSOEX_MASK 
+#undef DDR_PHY_DX8SL1DXCTL2_POSOEX_DEFVAL
+#undef DDR_PHY_DX8SL1DXCTL2_POSOEX_SHIFT
+#undef DDR_PHY_DX8SL1DXCTL2_POSOEX_MASK
 #define DDR_PHY_DX8SL1DXCTL2_POSOEX_DEFVAL                     0x00141800
 #define DDR_PHY_DX8SL1DXCTL2_POSOEX_SHIFT                      20
 #define DDR_PHY_DX8SL1DXCTL2_POSOEX_MASK                       0x00700000U
@@ -19067,9 +19067,9 @@
 /*
 * OE Extension during Pre-amble
 */
-#undef DDR_PHY_DX8SL1DXCTL2_PREOEX_DEFVAL 
-#undef DDR_PHY_DX8SL1DXCTL2_PREOEX_SHIFT 
-#undef DDR_PHY_DX8SL1DXCTL2_PREOEX_MASK 
+#undef DDR_PHY_DX8SL1DXCTL2_PREOEX_DEFVAL
+#undef DDR_PHY_DX8SL1DXCTL2_PREOEX_SHIFT
+#undef DDR_PHY_DX8SL1DXCTL2_PREOEX_MASK
 #define DDR_PHY_DX8SL1DXCTL2_PREOEX_DEFVAL                     0x00141800
 #define DDR_PHY_DX8SL1DXCTL2_PREOEX_SHIFT                      18
 #define DDR_PHY_DX8SL1DXCTL2_PREOEX_MASK                       0x000C0000U
@@ -19077,9 +19077,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_17_DEFVAL 
-#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_17_SHIFT 
-#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_17_MASK 
+#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_17_DEFVAL
+#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_17_SHIFT
+#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_17_MASK
 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_17_DEFVAL                0x00141800
 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_17_SHIFT                 17
 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_17_MASK                  0x00020000U
@@ -19087,9 +19087,9 @@
 /*
 * I/O Assisted Gate Select
 */
-#undef DDR_PHY_DX8SL1DXCTL2_IOAG_DEFVAL 
-#undef DDR_PHY_DX8SL1DXCTL2_IOAG_SHIFT 
-#undef DDR_PHY_DX8SL1DXCTL2_IOAG_MASK 
+#undef DDR_PHY_DX8SL1DXCTL2_IOAG_DEFVAL
+#undef DDR_PHY_DX8SL1DXCTL2_IOAG_SHIFT
+#undef DDR_PHY_DX8SL1DXCTL2_IOAG_MASK
 #define DDR_PHY_DX8SL1DXCTL2_IOAG_DEFVAL                       0x00141800
 #define DDR_PHY_DX8SL1DXCTL2_IOAG_SHIFT                        16
 #define DDR_PHY_DX8SL1DXCTL2_IOAG_MASK                         0x00010000U
@@ -19097,9 +19097,9 @@
 /*
 * I/O Loopback Select
 */
-#undef DDR_PHY_DX8SL1DXCTL2_IOLB_DEFVAL 
-#undef DDR_PHY_DX8SL1DXCTL2_IOLB_SHIFT 
-#undef DDR_PHY_DX8SL1DXCTL2_IOLB_MASK 
+#undef DDR_PHY_DX8SL1DXCTL2_IOLB_DEFVAL
+#undef DDR_PHY_DX8SL1DXCTL2_IOLB_SHIFT
+#undef DDR_PHY_DX8SL1DXCTL2_IOLB_MASK
 #define DDR_PHY_DX8SL1DXCTL2_IOLB_DEFVAL                       0x00141800
 #define DDR_PHY_DX8SL1DXCTL2_IOLB_SHIFT                        15
 #define DDR_PHY_DX8SL1DXCTL2_IOLB_MASK                         0x00008000U
@@ -19107,9 +19107,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_DEFVAL 
-#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_SHIFT 
-#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_MASK 
+#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_DEFVAL
+#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_SHIFT
+#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_MASK
 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_DEFVAL             0x00141800
 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_SHIFT              13
 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_MASK               0x00006000U
@@ -19117,9 +19117,9 @@
 /*
 * Low Power Wakeup Threshold
 */
-#undef DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_DEFVAL 
-#undef DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_SHIFT 
-#undef DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_MASK 
+#undef DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_DEFVAL
+#undef DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_SHIFT
+#undef DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_MASK
 #define DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_DEFVAL             0x00141800
 #define DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_SHIFT              9
 #define DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_MASK               0x00001E00U
@@ -19127,9 +19127,9 @@
 /*
 * Read Data Bus Inversion Enable
 */
-#undef DDR_PHY_DX8SL1DXCTL2_RDBI_DEFVAL 
-#undef DDR_PHY_DX8SL1DXCTL2_RDBI_SHIFT 
-#undef DDR_PHY_DX8SL1DXCTL2_RDBI_MASK 
+#undef DDR_PHY_DX8SL1DXCTL2_RDBI_DEFVAL
+#undef DDR_PHY_DX8SL1DXCTL2_RDBI_SHIFT
+#undef DDR_PHY_DX8SL1DXCTL2_RDBI_MASK
 #define DDR_PHY_DX8SL1DXCTL2_RDBI_DEFVAL                       0x00141800
 #define DDR_PHY_DX8SL1DXCTL2_RDBI_SHIFT                        8
 #define DDR_PHY_DX8SL1DXCTL2_RDBI_MASK                         0x00000100U
@@ -19137,9 +19137,9 @@
 /*
 * Write Data Bus Inversion Enable
 */
-#undef DDR_PHY_DX8SL1DXCTL2_WDBI_DEFVAL 
-#undef DDR_PHY_DX8SL1DXCTL2_WDBI_SHIFT 
-#undef DDR_PHY_DX8SL1DXCTL2_WDBI_MASK 
+#undef DDR_PHY_DX8SL1DXCTL2_WDBI_DEFVAL
+#undef DDR_PHY_DX8SL1DXCTL2_WDBI_SHIFT
+#undef DDR_PHY_DX8SL1DXCTL2_WDBI_MASK
 #define DDR_PHY_DX8SL1DXCTL2_WDBI_DEFVAL                       0x00141800
 #define DDR_PHY_DX8SL1DXCTL2_WDBI_SHIFT                        7
 #define DDR_PHY_DX8SL1DXCTL2_WDBI_MASK                         0x00000080U
@@ -19147,9 +19147,9 @@
 /*
 * PUB Read FIFO Bypass
 */
-#undef DDR_PHY_DX8SL1DXCTL2_PRFBYP_DEFVAL 
-#undef DDR_PHY_DX8SL1DXCTL2_PRFBYP_SHIFT 
-#undef DDR_PHY_DX8SL1DXCTL2_PRFBYP_MASK 
+#undef DDR_PHY_DX8SL1DXCTL2_PRFBYP_DEFVAL
+#undef DDR_PHY_DX8SL1DXCTL2_PRFBYP_SHIFT
+#undef DDR_PHY_DX8SL1DXCTL2_PRFBYP_MASK
 #define DDR_PHY_DX8SL1DXCTL2_PRFBYP_DEFVAL                     0x00141800
 #define DDR_PHY_DX8SL1DXCTL2_PRFBYP_SHIFT                      6
 #define DDR_PHY_DX8SL1DXCTL2_PRFBYP_MASK                       0x00000040U
@@ -19157,9 +19157,9 @@
 /*
 * DATX8 Receive FIFO Read Mode
 */
-#undef DDR_PHY_DX8SL1DXCTL2_RDMODE_DEFVAL 
-#undef DDR_PHY_DX8SL1DXCTL2_RDMODE_SHIFT 
-#undef DDR_PHY_DX8SL1DXCTL2_RDMODE_MASK 
+#undef DDR_PHY_DX8SL1DXCTL2_RDMODE_DEFVAL
+#undef DDR_PHY_DX8SL1DXCTL2_RDMODE_SHIFT
+#undef DDR_PHY_DX8SL1DXCTL2_RDMODE_MASK
 #define DDR_PHY_DX8SL1DXCTL2_RDMODE_DEFVAL                     0x00141800
 #define DDR_PHY_DX8SL1DXCTL2_RDMODE_SHIFT                      4
 #define DDR_PHY_DX8SL1DXCTL2_RDMODE_MASK                       0x00000030U
@@ -19167,9 +19167,9 @@
 /*
 * Disables the Read FIFO Reset
 */
-#undef DDR_PHY_DX8SL1DXCTL2_DISRST_DEFVAL 
-#undef DDR_PHY_DX8SL1DXCTL2_DISRST_SHIFT 
-#undef DDR_PHY_DX8SL1DXCTL2_DISRST_MASK 
+#undef DDR_PHY_DX8SL1DXCTL2_DISRST_DEFVAL
+#undef DDR_PHY_DX8SL1DXCTL2_DISRST_SHIFT
+#undef DDR_PHY_DX8SL1DXCTL2_DISRST_MASK
 #define DDR_PHY_DX8SL1DXCTL2_DISRST_DEFVAL                     0x00141800
 #define DDR_PHY_DX8SL1DXCTL2_DISRST_SHIFT                      3
 #define DDR_PHY_DX8SL1DXCTL2_DISRST_MASK                       0x00000008U
@@ -19177,9 +19177,9 @@
 /*
 * Read DQS Gate I/O Loopback
 */
-#undef DDR_PHY_DX8SL1DXCTL2_DQSGLB_DEFVAL 
-#undef DDR_PHY_DX8SL1DXCTL2_DQSGLB_SHIFT 
-#undef DDR_PHY_DX8SL1DXCTL2_DQSGLB_MASK 
+#undef DDR_PHY_DX8SL1DXCTL2_DQSGLB_DEFVAL
+#undef DDR_PHY_DX8SL1DXCTL2_DQSGLB_SHIFT
+#undef DDR_PHY_DX8SL1DXCTL2_DQSGLB_MASK
 #define DDR_PHY_DX8SL1DXCTL2_DQSGLB_DEFVAL                     0x00141800
 #define DDR_PHY_DX8SL1DXCTL2_DQSGLB_SHIFT                      1
 #define DDR_PHY_DX8SL1DXCTL2_DQSGLB_MASK                       0x00000006U
@@ -19187,9 +19187,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_0_DEFVAL 
-#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_0_SHIFT 
-#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_0_MASK 
+#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_0_DEFVAL
+#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_0_SHIFT
+#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_0_MASK
 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_0_DEFVAL                 0x00141800
 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_0_SHIFT                  0
 #define DDR_PHY_DX8SL1DXCTL2_RESERVED_0_MASK                   0x00000001U
@@ -19197,9 +19197,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SL1IOCR_RESERVED_31_DEFVAL 
-#undef DDR_PHY_DX8SL1IOCR_RESERVED_31_SHIFT 
-#undef DDR_PHY_DX8SL1IOCR_RESERVED_31_MASK 
+#undef DDR_PHY_DX8SL1IOCR_RESERVED_31_DEFVAL
+#undef DDR_PHY_DX8SL1IOCR_RESERVED_31_SHIFT
+#undef DDR_PHY_DX8SL1IOCR_RESERVED_31_MASK
 #define DDR_PHY_DX8SL1IOCR_RESERVED_31_DEFVAL                  0x00000000
 #define DDR_PHY_DX8SL1IOCR_RESERVED_31_SHIFT                   31
 #define DDR_PHY_DX8SL1IOCR_RESERVED_31_MASK                    0x80000000U
@@ -19207,9 +19207,9 @@
 /*
 * PVREF_DAC REFSEL range select
 */
-#undef DDR_PHY_DX8SL1IOCR_DXDACRANGE_DEFVAL 
-#undef DDR_PHY_DX8SL1IOCR_DXDACRANGE_SHIFT 
-#undef DDR_PHY_DX8SL1IOCR_DXDACRANGE_MASK 
+#undef DDR_PHY_DX8SL1IOCR_DXDACRANGE_DEFVAL
+#undef DDR_PHY_DX8SL1IOCR_DXDACRANGE_SHIFT
+#undef DDR_PHY_DX8SL1IOCR_DXDACRANGE_MASK
 #define DDR_PHY_DX8SL1IOCR_DXDACRANGE_DEFVAL                   0x00000000
 #define DDR_PHY_DX8SL1IOCR_DXDACRANGE_SHIFT                    28
 #define DDR_PHY_DX8SL1IOCR_DXDACRANGE_MASK                     0x70000000U
@@ -19217,9 +19217,9 @@
 /*
 * IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
 */
-#undef DDR_PHY_DX8SL1IOCR_DXVREFIOM_DEFVAL 
-#undef DDR_PHY_DX8SL1IOCR_DXVREFIOM_SHIFT 
-#undef DDR_PHY_DX8SL1IOCR_DXVREFIOM_MASK 
+#undef DDR_PHY_DX8SL1IOCR_DXVREFIOM_DEFVAL
+#undef DDR_PHY_DX8SL1IOCR_DXVREFIOM_SHIFT
+#undef DDR_PHY_DX8SL1IOCR_DXVREFIOM_MASK
 #define DDR_PHY_DX8SL1IOCR_DXVREFIOM_DEFVAL                    0x00000000
 #define DDR_PHY_DX8SL1IOCR_DXVREFIOM_SHIFT                     25
 #define DDR_PHY_DX8SL1IOCR_DXVREFIOM_MASK                      0x0E000000U
@@ -19227,9 +19227,9 @@
 /*
 * DX IO Mode
 */
-#undef DDR_PHY_DX8SL1IOCR_DXIOM_DEFVAL 
-#undef DDR_PHY_DX8SL1IOCR_DXIOM_SHIFT 
-#undef DDR_PHY_DX8SL1IOCR_DXIOM_MASK 
+#undef DDR_PHY_DX8SL1IOCR_DXIOM_DEFVAL
+#undef DDR_PHY_DX8SL1IOCR_DXIOM_SHIFT
+#undef DDR_PHY_DX8SL1IOCR_DXIOM_MASK
 #define DDR_PHY_DX8SL1IOCR_DXIOM_DEFVAL                        0x00000000
 #define DDR_PHY_DX8SL1IOCR_DXIOM_SHIFT                         22
 #define DDR_PHY_DX8SL1IOCR_DXIOM_MASK                          0x01C00000U
@@ -19237,9 +19237,9 @@
 /*
 * DX IO Transmitter Mode
 */
-#undef DDR_PHY_DX8SL1IOCR_DXTXM_DEFVAL 
-#undef DDR_PHY_DX8SL1IOCR_DXTXM_SHIFT 
-#undef DDR_PHY_DX8SL1IOCR_DXTXM_MASK 
+#undef DDR_PHY_DX8SL1IOCR_DXTXM_DEFVAL
+#undef DDR_PHY_DX8SL1IOCR_DXTXM_SHIFT
+#undef DDR_PHY_DX8SL1IOCR_DXTXM_MASK
 #define DDR_PHY_DX8SL1IOCR_DXTXM_DEFVAL                        0x00000000
 #define DDR_PHY_DX8SL1IOCR_DXTXM_SHIFT                         11
 #define DDR_PHY_DX8SL1IOCR_DXTXM_MASK                          0x003FF800U
@@ -19247,9 +19247,9 @@
 /*
 * DX IO Receiver Mode
 */
-#undef DDR_PHY_DX8SL1IOCR_DXRXM_DEFVAL 
-#undef DDR_PHY_DX8SL1IOCR_DXRXM_SHIFT 
-#undef DDR_PHY_DX8SL1IOCR_DXRXM_MASK 
+#undef DDR_PHY_DX8SL1IOCR_DXRXM_DEFVAL
+#undef DDR_PHY_DX8SL1IOCR_DXRXM_SHIFT
+#undef DDR_PHY_DX8SL1IOCR_DXRXM_MASK
 #define DDR_PHY_DX8SL1IOCR_DXRXM_DEFVAL                        0x00000000
 #define DDR_PHY_DX8SL1IOCR_DXRXM_SHIFT                         0
 #define DDR_PHY_DX8SL1IOCR_DXRXM_MASK                          0x000007FFU
@@ -19257,9 +19257,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SL2OSC_RESERVED_31_30_DEFVAL 
-#undef DDR_PHY_DX8SL2OSC_RESERVED_31_30_SHIFT 
-#undef DDR_PHY_DX8SL2OSC_RESERVED_31_30_MASK 
+#undef DDR_PHY_DX8SL2OSC_RESERVED_31_30_DEFVAL
+#undef DDR_PHY_DX8SL2OSC_RESERVED_31_30_SHIFT
+#undef DDR_PHY_DX8SL2OSC_RESERVED_31_30_MASK
 #define DDR_PHY_DX8SL2OSC_RESERVED_31_30_DEFVAL                0x00019FFE
 #define DDR_PHY_DX8SL2OSC_RESERVED_31_30_SHIFT                 30
 #define DDR_PHY_DX8SL2OSC_RESERVED_31_30_MASK                  0xC0000000U
@@ -19267,9 +19267,9 @@
 /*
 * Enable Clock Gating for DX ddr_clk
 */
-#undef DDR_PHY_DX8SL2OSC_GATEDXRDCLK_DEFVAL 
-#undef DDR_PHY_DX8SL2OSC_GATEDXRDCLK_SHIFT 
-#undef DDR_PHY_DX8SL2OSC_GATEDXRDCLK_MASK 
+#undef DDR_PHY_DX8SL2OSC_GATEDXRDCLK_DEFVAL
+#undef DDR_PHY_DX8SL2OSC_GATEDXRDCLK_SHIFT
+#undef DDR_PHY_DX8SL2OSC_GATEDXRDCLK_MASK
 #define DDR_PHY_DX8SL2OSC_GATEDXRDCLK_DEFVAL                   0x00019FFE
 #define DDR_PHY_DX8SL2OSC_GATEDXRDCLK_SHIFT                    28
 #define DDR_PHY_DX8SL2OSC_GATEDXRDCLK_MASK                     0x30000000U
@@ -19277,9 +19277,9 @@
 /*
 * Enable Clock Gating for DX ctl_rd_clk
 */
-#undef DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_DEFVAL 
-#undef DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_SHIFT 
-#undef DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_MASK 
+#undef DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_DEFVAL
+#undef DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_SHIFT
+#undef DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_MASK
 #define DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_DEFVAL                  0x00019FFE
 #define DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_SHIFT                   26
 #define DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_MASK                    0x0C000000U
@@ -19287,9 +19287,9 @@
 /*
 * Enable Clock Gating for DX ctl_clk
 */
-#undef DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_DEFVAL 
-#undef DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_SHIFT 
-#undef DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_MASK 
+#undef DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_DEFVAL
+#undef DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_SHIFT
+#undef DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_MASK
 #define DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_DEFVAL                  0x00019FFE
 #define DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_SHIFT                   24
 #define DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_MASK                    0x03000000U
@@ -19298,9 +19298,9 @@
 * Selects the level to which clocks will be stalled when clock gating is e
     * nabled.
 */
-#undef DDR_PHY_DX8SL2OSC_CLKLEVEL_DEFVAL 
-#undef DDR_PHY_DX8SL2OSC_CLKLEVEL_SHIFT 
-#undef DDR_PHY_DX8SL2OSC_CLKLEVEL_MASK 
+#undef DDR_PHY_DX8SL2OSC_CLKLEVEL_DEFVAL
+#undef DDR_PHY_DX8SL2OSC_CLKLEVEL_SHIFT
+#undef DDR_PHY_DX8SL2OSC_CLKLEVEL_MASK
 #define DDR_PHY_DX8SL2OSC_CLKLEVEL_DEFVAL                      0x00019FFE
 #define DDR_PHY_DX8SL2OSC_CLKLEVEL_SHIFT                       22
 #define DDR_PHY_DX8SL2OSC_CLKLEVEL_MASK                        0x00C00000U
@@ -19308,9 +19308,9 @@
 /*
 * Loopback Mode
 */
-#undef DDR_PHY_DX8SL2OSC_LBMODE_DEFVAL 
-#undef DDR_PHY_DX8SL2OSC_LBMODE_SHIFT 
-#undef DDR_PHY_DX8SL2OSC_LBMODE_MASK 
+#undef DDR_PHY_DX8SL2OSC_LBMODE_DEFVAL
+#undef DDR_PHY_DX8SL2OSC_LBMODE_SHIFT
+#undef DDR_PHY_DX8SL2OSC_LBMODE_MASK
 #define DDR_PHY_DX8SL2OSC_LBMODE_DEFVAL                        0x00019FFE
 #define DDR_PHY_DX8SL2OSC_LBMODE_SHIFT                         21
 #define DDR_PHY_DX8SL2OSC_LBMODE_MASK                          0x00200000U
@@ -19318,9 +19318,9 @@
 /*
 * Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
 */
-#undef DDR_PHY_DX8SL2OSC_LBGSDQS_DEFVAL 
-#undef DDR_PHY_DX8SL2OSC_LBGSDQS_SHIFT 
-#undef DDR_PHY_DX8SL2OSC_LBGSDQS_MASK 
+#undef DDR_PHY_DX8SL2OSC_LBGSDQS_DEFVAL
+#undef DDR_PHY_DX8SL2OSC_LBGSDQS_SHIFT
+#undef DDR_PHY_DX8SL2OSC_LBGSDQS_MASK
 #define DDR_PHY_DX8SL2OSC_LBGSDQS_DEFVAL                       0x00019FFE
 #define DDR_PHY_DX8SL2OSC_LBGSDQS_SHIFT                        20
 #define DDR_PHY_DX8SL2OSC_LBGSDQS_MASK                         0x00100000U
@@ -19328,9 +19328,9 @@
 /*
 * Loopback DQS Gating
 */
-#undef DDR_PHY_DX8SL2OSC_LBGDQS_DEFVAL 
-#undef DDR_PHY_DX8SL2OSC_LBGDQS_SHIFT 
-#undef DDR_PHY_DX8SL2OSC_LBGDQS_MASK 
+#undef DDR_PHY_DX8SL2OSC_LBGDQS_DEFVAL
+#undef DDR_PHY_DX8SL2OSC_LBGDQS_SHIFT
+#undef DDR_PHY_DX8SL2OSC_LBGDQS_MASK
 #define DDR_PHY_DX8SL2OSC_LBGDQS_DEFVAL                        0x00019FFE
 #define DDR_PHY_DX8SL2OSC_LBGDQS_SHIFT                         18
 #define DDR_PHY_DX8SL2OSC_LBGDQS_MASK                          0x000C0000U
@@ -19338,9 +19338,9 @@
 /*
 * Loopback DQS Shift
 */
-#undef DDR_PHY_DX8SL2OSC_LBDQSS_DEFVAL 
-#undef DDR_PHY_DX8SL2OSC_LBDQSS_SHIFT 
-#undef DDR_PHY_DX8SL2OSC_LBDQSS_MASK 
+#undef DDR_PHY_DX8SL2OSC_LBDQSS_DEFVAL
+#undef DDR_PHY_DX8SL2OSC_LBDQSS_SHIFT
+#undef DDR_PHY_DX8SL2OSC_LBDQSS_MASK
 #define DDR_PHY_DX8SL2OSC_LBDQSS_DEFVAL                        0x00019FFE
 #define DDR_PHY_DX8SL2OSC_LBDQSS_SHIFT                         17
 #define DDR_PHY_DX8SL2OSC_LBDQSS_MASK                          0x00020000U
@@ -19348,9 +19348,9 @@
 /*
 * PHY High-Speed Reset
 */
-#undef DDR_PHY_DX8SL2OSC_PHYHRST_DEFVAL 
-#undef DDR_PHY_DX8SL2OSC_PHYHRST_SHIFT 
-#undef DDR_PHY_DX8SL2OSC_PHYHRST_MASK 
+#undef DDR_PHY_DX8SL2OSC_PHYHRST_DEFVAL
+#undef DDR_PHY_DX8SL2OSC_PHYHRST_SHIFT
+#undef DDR_PHY_DX8SL2OSC_PHYHRST_MASK
 #define DDR_PHY_DX8SL2OSC_PHYHRST_DEFVAL                       0x00019FFE
 #define DDR_PHY_DX8SL2OSC_PHYHRST_SHIFT                        16
 #define DDR_PHY_DX8SL2OSC_PHYHRST_MASK                         0x00010000U
@@ -19358,9 +19358,9 @@
 /*
 * PHY FIFO Reset
 */
-#undef DDR_PHY_DX8SL2OSC_PHYFRST_DEFVAL 
-#undef DDR_PHY_DX8SL2OSC_PHYFRST_SHIFT 
-#undef DDR_PHY_DX8SL2OSC_PHYFRST_MASK 
+#undef DDR_PHY_DX8SL2OSC_PHYFRST_DEFVAL
+#undef DDR_PHY_DX8SL2OSC_PHYFRST_SHIFT
+#undef DDR_PHY_DX8SL2OSC_PHYFRST_MASK
 #define DDR_PHY_DX8SL2OSC_PHYFRST_DEFVAL                       0x00019FFE
 #define DDR_PHY_DX8SL2OSC_PHYFRST_SHIFT                        15
 #define DDR_PHY_DX8SL2OSC_PHYFRST_MASK                         0x00008000U
@@ -19368,9 +19368,9 @@
 /*
 * Delay Line Test Start
 */
-#undef DDR_PHY_DX8SL2OSC_DLTST_DEFVAL 
-#undef DDR_PHY_DX8SL2OSC_DLTST_SHIFT 
-#undef DDR_PHY_DX8SL2OSC_DLTST_MASK 
+#undef DDR_PHY_DX8SL2OSC_DLTST_DEFVAL
+#undef DDR_PHY_DX8SL2OSC_DLTST_SHIFT
+#undef DDR_PHY_DX8SL2OSC_DLTST_MASK
 #define DDR_PHY_DX8SL2OSC_DLTST_DEFVAL                         0x00019FFE
 #define DDR_PHY_DX8SL2OSC_DLTST_SHIFT                          14
 #define DDR_PHY_DX8SL2OSC_DLTST_MASK                           0x00004000U
@@ -19378,9 +19378,9 @@
 /*
 * Delay Line Test Mode
 */
-#undef DDR_PHY_DX8SL2OSC_DLTMODE_DEFVAL 
-#undef DDR_PHY_DX8SL2OSC_DLTMODE_SHIFT 
-#undef DDR_PHY_DX8SL2OSC_DLTMODE_MASK 
+#undef DDR_PHY_DX8SL2OSC_DLTMODE_DEFVAL
+#undef DDR_PHY_DX8SL2OSC_DLTMODE_SHIFT
+#undef DDR_PHY_DX8SL2OSC_DLTMODE_MASK
 #define DDR_PHY_DX8SL2OSC_DLTMODE_DEFVAL                       0x00019FFE
 #define DDR_PHY_DX8SL2OSC_DLTMODE_SHIFT                        13
 #define DDR_PHY_DX8SL2OSC_DLTMODE_MASK                         0x00002000U
@@ -19388,9 +19388,9 @@
 /*
 * Reserved. Caution, do not write to this register field.
 */
-#undef DDR_PHY_DX8SL2OSC_RESERVED_12_11_DEFVAL 
-#undef DDR_PHY_DX8SL2OSC_RESERVED_12_11_SHIFT 
-#undef DDR_PHY_DX8SL2OSC_RESERVED_12_11_MASK 
+#undef DDR_PHY_DX8SL2OSC_RESERVED_12_11_DEFVAL
+#undef DDR_PHY_DX8SL2OSC_RESERVED_12_11_SHIFT
+#undef DDR_PHY_DX8SL2OSC_RESERVED_12_11_MASK
 #define DDR_PHY_DX8SL2OSC_RESERVED_12_11_DEFVAL                0x00019FFE
 #define DDR_PHY_DX8SL2OSC_RESERVED_12_11_SHIFT                 11
 #define DDR_PHY_DX8SL2OSC_RESERVED_12_11_MASK                  0x00001800U
@@ -19398,9 +19398,9 @@
 /*
 * Oscillator Mode Write-Data Delay Line Select
 */
-#undef DDR_PHY_DX8SL2OSC_OSCWDDL_DEFVAL 
-#undef DDR_PHY_DX8SL2OSC_OSCWDDL_SHIFT 
-#undef DDR_PHY_DX8SL2OSC_OSCWDDL_MASK 
+#undef DDR_PHY_DX8SL2OSC_OSCWDDL_DEFVAL
+#undef DDR_PHY_DX8SL2OSC_OSCWDDL_SHIFT
+#undef DDR_PHY_DX8SL2OSC_OSCWDDL_MASK
 #define DDR_PHY_DX8SL2OSC_OSCWDDL_DEFVAL                       0x00019FFE
 #define DDR_PHY_DX8SL2OSC_OSCWDDL_SHIFT                        9
 #define DDR_PHY_DX8SL2OSC_OSCWDDL_MASK                         0x00000600U
@@ -19408,9 +19408,9 @@
 /*
 * Reserved. Caution, do not write to this register field.
 */
-#undef DDR_PHY_DX8SL2OSC_RESERVED_8_7_DEFVAL 
-#undef DDR_PHY_DX8SL2OSC_RESERVED_8_7_SHIFT 
-#undef DDR_PHY_DX8SL2OSC_RESERVED_8_7_MASK 
+#undef DDR_PHY_DX8SL2OSC_RESERVED_8_7_DEFVAL
+#undef DDR_PHY_DX8SL2OSC_RESERVED_8_7_SHIFT
+#undef DDR_PHY_DX8SL2OSC_RESERVED_8_7_MASK
 #define DDR_PHY_DX8SL2OSC_RESERVED_8_7_DEFVAL                  0x00019FFE
 #define DDR_PHY_DX8SL2OSC_RESERVED_8_7_SHIFT                   7
 #define DDR_PHY_DX8SL2OSC_RESERVED_8_7_MASK                    0x00000180U
@@ -19418,9 +19418,9 @@
 /*
 * Oscillator Mode Write-Leveling Delay Line Select
 */
-#undef DDR_PHY_DX8SL2OSC_OSCWDL_DEFVAL 
-#undef DDR_PHY_DX8SL2OSC_OSCWDL_SHIFT 
-#undef DDR_PHY_DX8SL2OSC_OSCWDL_MASK 
+#undef DDR_PHY_DX8SL2OSC_OSCWDL_DEFVAL
+#undef DDR_PHY_DX8SL2OSC_OSCWDL_SHIFT
+#undef DDR_PHY_DX8SL2OSC_OSCWDL_MASK
 #define DDR_PHY_DX8SL2OSC_OSCWDL_DEFVAL                        0x00019FFE
 #define DDR_PHY_DX8SL2OSC_OSCWDL_SHIFT                         5
 #define DDR_PHY_DX8SL2OSC_OSCWDL_MASK                          0x00000060U
@@ -19428,9 +19428,9 @@
 /*
 * Oscillator Mode Division
 */
-#undef DDR_PHY_DX8SL2OSC_OSCDIV_DEFVAL 
-#undef DDR_PHY_DX8SL2OSC_OSCDIV_SHIFT 
-#undef DDR_PHY_DX8SL2OSC_OSCDIV_MASK 
+#undef DDR_PHY_DX8SL2OSC_OSCDIV_DEFVAL
+#undef DDR_PHY_DX8SL2OSC_OSCDIV_SHIFT
+#undef DDR_PHY_DX8SL2OSC_OSCDIV_MASK
 #define DDR_PHY_DX8SL2OSC_OSCDIV_DEFVAL                        0x00019FFE
 #define DDR_PHY_DX8SL2OSC_OSCDIV_SHIFT                         1
 #define DDR_PHY_DX8SL2OSC_OSCDIV_MASK                          0x0000001EU
@@ -19438,9 +19438,9 @@
 /*
 * Oscillator Enable
 */
-#undef DDR_PHY_DX8SL2OSC_OSCEN_DEFVAL 
-#undef DDR_PHY_DX8SL2OSC_OSCEN_SHIFT 
-#undef DDR_PHY_DX8SL2OSC_OSCEN_MASK 
+#undef DDR_PHY_DX8SL2OSC_OSCEN_DEFVAL
+#undef DDR_PHY_DX8SL2OSC_OSCEN_SHIFT
+#undef DDR_PHY_DX8SL2OSC_OSCEN_MASK
 #define DDR_PHY_DX8SL2OSC_OSCEN_DEFVAL                         0x00019FFE
 #define DDR_PHY_DX8SL2OSC_OSCEN_SHIFT                          0
 #define DDR_PHY_DX8SL2OSC_OSCEN_MASK                           0x00000001U
@@ -19448,9 +19448,9 @@
 /*
 * PLL Bypass
 */
-#undef DDR_PHY_DX8SL2PLLCR0_PLLBYP_DEFVAL 
-#undef DDR_PHY_DX8SL2PLLCR0_PLLBYP_SHIFT 
-#undef DDR_PHY_DX8SL2PLLCR0_PLLBYP_MASK 
+#undef DDR_PHY_DX8SL2PLLCR0_PLLBYP_DEFVAL
+#undef DDR_PHY_DX8SL2PLLCR0_PLLBYP_SHIFT
+#undef DDR_PHY_DX8SL2PLLCR0_PLLBYP_MASK
 #define DDR_PHY_DX8SL2PLLCR0_PLLBYP_DEFVAL                     0x001C0000
 #define DDR_PHY_DX8SL2PLLCR0_PLLBYP_SHIFT                      31
 #define DDR_PHY_DX8SL2PLLCR0_PLLBYP_MASK                       0x80000000U
@@ -19458,9 +19458,9 @@
 /*
 * PLL Reset
 */
-#undef DDR_PHY_DX8SL2PLLCR0_PLLRST_DEFVAL 
-#undef DDR_PHY_DX8SL2PLLCR0_PLLRST_SHIFT 
-#undef DDR_PHY_DX8SL2PLLCR0_PLLRST_MASK 
+#undef DDR_PHY_DX8SL2PLLCR0_PLLRST_DEFVAL
+#undef DDR_PHY_DX8SL2PLLCR0_PLLRST_SHIFT
+#undef DDR_PHY_DX8SL2PLLCR0_PLLRST_MASK
 #define DDR_PHY_DX8SL2PLLCR0_PLLRST_DEFVAL                     0x001C0000
 #define DDR_PHY_DX8SL2PLLCR0_PLLRST_SHIFT                      30
 #define DDR_PHY_DX8SL2PLLCR0_PLLRST_MASK                       0x40000000U
@@ -19468,9 +19468,9 @@
 /*
 * PLL Power Down
 */
-#undef DDR_PHY_DX8SL2PLLCR0_PLLPD_DEFVAL 
-#undef DDR_PHY_DX8SL2PLLCR0_PLLPD_SHIFT 
-#undef DDR_PHY_DX8SL2PLLCR0_PLLPD_MASK 
+#undef DDR_PHY_DX8SL2PLLCR0_PLLPD_DEFVAL
+#undef DDR_PHY_DX8SL2PLLCR0_PLLPD_SHIFT
+#undef DDR_PHY_DX8SL2PLLCR0_PLLPD_MASK
 #define DDR_PHY_DX8SL2PLLCR0_PLLPD_DEFVAL                      0x001C0000
 #define DDR_PHY_DX8SL2PLLCR0_PLLPD_SHIFT                       29
 #define DDR_PHY_DX8SL2PLLCR0_PLLPD_MASK                        0x20000000U
@@ -19478,9 +19478,9 @@
 /*
 * Reference Stop Mode
 */
-#undef DDR_PHY_DX8SL2PLLCR0_RSTOPM_DEFVAL 
-#undef DDR_PHY_DX8SL2PLLCR0_RSTOPM_SHIFT 
-#undef DDR_PHY_DX8SL2PLLCR0_RSTOPM_MASK 
+#undef DDR_PHY_DX8SL2PLLCR0_RSTOPM_DEFVAL
+#undef DDR_PHY_DX8SL2PLLCR0_RSTOPM_SHIFT
+#undef DDR_PHY_DX8SL2PLLCR0_RSTOPM_MASK
 #define DDR_PHY_DX8SL2PLLCR0_RSTOPM_DEFVAL                     0x001C0000
 #define DDR_PHY_DX8SL2PLLCR0_RSTOPM_SHIFT                      28
 #define DDR_PHY_DX8SL2PLLCR0_RSTOPM_MASK                       0x10000000U
@@ -19488,9 +19488,9 @@
 /*
 * PLL Frequency Select
 */
-#undef DDR_PHY_DX8SL2PLLCR0_FRQSEL_DEFVAL 
-#undef DDR_PHY_DX8SL2PLLCR0_FRQSEL_SHIFT 
-#undef DDR_PHY_DX8SL2PLLCR0_FRQSEL_MASK 
+#undef DDR_PHY_DX8SL2PLLCR0_FRQSEL_DEFVAL
+#undef DDR_PHY_DX8SL2PLLCR0_FRQSEL_SHIFT
+#undef DDR_PHY_DX8SL2PLLCR0_FRQSEL_MASK
 #define DDR_PHY_DX8SL2PLLCR0_FRQSEL_DEFVAL                     0x001C0000
 #define DDR_PHY_DX8SL2PLLCR0_FRQSEL_SHIFT                      24
 #define DDR_PHY_DX8SL2PLLCR0_FRQSEL_MASK                       0x0F000000U
@@ -19498,9 +19498,9 @@
 /*
 * Relock Mode
 */
-#undef DDR_PHY_DX8SL2PLLCR0_RLOCKM_DEFVAL 
-#undef DDR_PHY_DX8SL2PLLCR0_RLOCKM_SHIFT 
-#undef DDR_PHY_DX8SL2PLLCR0_RLOCKM_MASK 
+#undef DDR_PHY_DX8SL2PLLCR0_RLOCKM_DEFVAL
+#undef DDR_PHY_DX8SL2PLLCR0_RLOCKM_SHIFT
+#undef DDR_PHY_DX8SL2PLLCR0_RLOCKM_MASK
 #define DDR_PHY_DX8SL2PLLCR0_RLOCKM_DEFVAL                     0x001C0000
 #define DDR_PHY_DX8SL2PLLCR0_RLOCKM_SHIFT                      23
 #define DDR_PHY_DX8SL2PLLCR0_RLOCKM_MASK                       0x00800000U
@@ -19508,9 +19508,9 @@
 /*
 * Charge Pump Proportional Current Control
 */
-#undef DDR_PHY_DX8SL2PLLCR0_CPPC_DEFVAL 
-#undef DDR_PHY_DX8SL2PLLCR0_CPPC_SHIFT 
-#undef DDR_PHY_DX8SL2PLLCR0_CPPC_MASK 
+#undef DDR_PHY_DX8SL2PLLCR0_CPPC_DEFVAL
+#undef DDR_PHY_DX8SL2PLLCR0_CPPC_SHIFT
+#undef DDR_PHY_DX8SL2PLLCR0_CPPC_MASK
 #define DDR_PHY_DX8SL2PLLCR0_CPPC_DEFVAL                       0x001C0000
 #define DDR_PHY_DX8SL2PLLCR0_CPPC_SHIFT                        17
 #define DDR_PHY_DX8SL2PLLCR0_CPPC_MASK                         0x007E0000U
@@ -19518,9 +19518,9 @@
 /*
 * Charge Pump Integrating Current Control
 */
-#undef DDR_PHY_DX8SL2PLLCR0_CPIC_DEFVAL 
-#undef DDR_PHY_DX8SL2PLLCR0_CPIC_SHIFT 
-#undef DDR_PHY_DX8SL2PLLCR0_CPIC_MASK 
+#undef DDR_PHY_DX8SL2PLLCR0_CPIC_DEFVAL
+#undef DDR_PHY_DX8SL2PLLCR0_CPIC_SHIFT
+#undef DDR_PHY_DX8SL2PLLCR0_CPIC_MASK
 #define DDR_PHY_DX8SL2PLLCR0_CPIC_DEFVAL                       0x001C0000
 #define DDR_PHY_DX8SL2PLLCR0_CPIC_SHIFT                        13
 #define DDR_PHY_DX8SL2PLLCR0_CPIC_MASK                         0x0001E000U
@@ -19528,9 +19528,9 @@
 /*
 * Gear Shift
 */
-#undef DDR_PHY_DX8SL2PLLCR0_GSHIFT_DEFVAL 
-#undef DDR_PHY_DX8SL2PLLCR0_GSHIFT_SHIFT 
-#undef DDR_PHY_DX8SL2PLLCR0_GSHIFT_MASK 
+#undef DDR_PHY_DX8SL2PLLCR0_GSHIFT_DEFVAL
+#undef DDR_PHY_DX8SL2PLLCR0_GSHIFT_SHIFT
+#undef DDR_PHY_DX8SL2PLLCR0_GSHIFT_MASK
 #define DDR_PHY_DX8SL2PLLCR0_GSHIFT_DEFVAL                     0x001C0000
 #define DDR_PHY_DX8SL2PLLCR0_GSHIFT_SHIFT                      12
 #define DDR_PHY_DX8SL2PLLCR0_GSHIFT_MASK                       0x00001000U
@@ -19538,9 +19538,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9_DEFVAL 
-#undef DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9_SHIFT 
-#undef DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9_MASK 
+#undef DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9_DEFVAL
+#undef DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9_SHIFT
+#undef DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9_MASK
 #define DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9_DEFVAL              0x001C0000
 #define DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9_SHIFT               9
 #define DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9_MASK                0x00000E00U
@@ -19548,9 +19548,9 @@
 /*
 * Analog Test Enable (ATOEN)
 */
-#undef DDR_PHY_DX8SL2PLLCR0_ATOEN_DEFVAL 
-#undef DDR_PHY_DX8SL2PLLCR0_ATOEN_SHIFT 
-#undef DDR_PHY_DX8SL2PLLCR0_ATOEN_MASK 
+#undef DDR_PHY_DX8SL2PLLCR0_ATOEN_DEFVAL
+#undef DDR_PHY_DX8SL2PLLCR0_ATOEN_SHIFT
+#undef DDR_PHY_DX8SL2PLLCR0_ATOEN_MASK
 #define DDR_PHY_DX8SL2PLLCR0_ATOEN_DEFVAL                      0x001C0000
 #define DDR_PHY_DX8SL2PLLCR0_ATOEN_SHIFT                       8
 #define DDR_PHY_DX8SL2PLLCR0_ATOEN_MASK                        0x00000100U
@@ -19558,9 +19558,9 @@
 /*
 * Analog Test Control
 */
-#undef DDR_PHY_DX8SL2PLLCR0_ATC_DEFVAL 
-#undef DDR_PHY_DX8SL2PLLCR0_ATC_SHIFT 
-#undef DDR_PHY_DX8SL2PLLCR0_ATC_MASK 
+#undef DDR_PHY_DX8SL2PLLCR0_ATC_DEFVAL
+#undef DDR_PHY_DX8SL2PLLCR0_ATC_SHIFT
+#undef DDR_PHY_DX8SL2PLLCR0_ATC_MASK
 #define DDR_PHY_DX8SL2PLLCR0_ATC_DEFVAL                        0x001C0000
 #define DDR_PHY_DX8SL2PLLCR0_ATC_SHIFT                         4
 #define DDR_PHY_DX8SL2PLLCR0_ATC_MASK                          0x000000F0U
@@ -19568,9 +19568,9 @@
 /*
 * Digital Test Control
 */
-#undef DDR_PHY_DX8SL2PLLCR0_DTC_DEFVAL 
-#undef DDR_PHY_DX8SL2PLLCR0_DTC_SHIFT 
-#undef DDR_PHY_DX8SL2PLLCR0_DTC_MASK 
+#undef DDR_PHY_DX8SL2PLLCR0_DTC_DEFVAL
+#undef DDR_PHY_DX8SL2PLLCR0_DTC_SHIFT
+#undef DDR_PHY_DX8SL2PLLCR0_DTC_MASK
 #define DDR_PHY_DX8SL2PLLCR0_DTC_DEFVAL                        0x001C0000
 #define DDR_PHY_DX8SL2PLLCR0_DTC_SHIFT                         0
 #define DDR_PHY_DX8SL2PLLCR0_DTC_MASK                          0x0000000FU
@@ -19578,9 +19578,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_DEFVAL 
-#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_SHIFT 
-#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_MASK 
+#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_DEFVAL
+#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_SHIFT
+#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_MASK
 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_DEFVAL             0x01264000
 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_SHIFT              25
 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_MASK               0xFE000000U
@@ -19588,9 +19588,9 @@
 /*
 * Read Path Rise-to-Rise Mode
 */
-#undef DDR_PHY_DX8SL2DQSCTL_RRRMODE_DEFVAL 
-#undef DDR_PHY_DX8SL2DQSCTL_RRRMODE_SHIFT 
-#undef DDR_PHY_DX8SL2DQSCTL_RRRMODE_MASK 
+#undef DDR_PHY_DX8SL2DQSCTL_RRRMODE_DEFVAL
+#undef DDR_PHY_DX8SL2DQSCTL_RRRMODE_SHIFT
+#undef DDR_PHY_DX8SL2DQSCTL_RRRMODE_MASK
 #define DDR_PHY_DX8SL2DQSCTL_RRRMODE_DEFVAL                    0x01264000
 #define DDR_PHY_DX8SL2DQSCTL_RRRMODE_SHIFT                     24
 #define DDR_PHY_DX8SL2DQSCTL_RRRMODE_MASK                      0x01000000U
@@ -19598,9 +19598,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_DEFVAL 
-#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_SHIFT 
-#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_MASK 
+#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_DEFVAL
+#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_SHIFT
+#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_MASK
 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_DEFVAL             0x01264000
 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_SHIFT              22
 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_MASK               0x00C00000U
@@ -19608,9 +19608,9 @@
 /*
 * Write Path Rise-to-Rise Mode
 */
-#undef DDR_PHY_DX8SL2DQSCTL_WRRMODE_DEFVAL 
-#undef DDR_PHY_DX8SL2DQSCTL_WRRMODE_SHIFT 
-#undef DDR_PHY_DX8SL2DQSCTL_WRRMODE_MASK 
+#undef DDR_PHY_DX8SL2DQSCTL_WRRMODE_DEFVAL
+#undef DDR_PHY_DX8SL2DQSCTL_WRRMODE_SHIFT
+#undef DDR_PHY_DX8SL2DQSCTL_WRRMODE_MASK
 #define DDR_PHY_DX8SL2DQSCTL_WRRMODE_DEFVAL                    0x01264000
 #define DDR_PHY_DX8SL2DQSCTL_WRRMODE_SHIFT                     21
 #define DDR_PHY_DX8SL2DQSCTL_WRRMODE_MASK                      0x00200000U
@@ -19618,9 +19618,9 @@
 /*
 * DQS Gate Extension
 */
-#undef DDR_PHY_DX8SL2DQSCTL_DQSGX_DEFVAL 
-#undef DDR_PHY_DX8SL2DQSCTL_DQSGX_SHIFT 
-#undef DDR_PHY_DX8SL2DQSCTL_DQSGX_MASK 
+#undef DDR_PHY_DX8SL2DQSCTL_DQSGX_DEFVAL
+#undef DDR_PHY_DX8SL2DQSCTL_DQSGX_SHIFT
+#undef DDR_PHY_DX8SL2DQSCTL_DQSGX_MASK
 #define DDR_PHY_DX8SL2DQSCTL_DQSGX_DEFVAL                      0x01264000
 #define DDR_PHY_DX8SL2DQSCTL_DQSGX_SHIFT                       19
 #define DDR_PHY_DX8SL2DQSCTL_DQSGX_MASK                        0x00180000U
@@ -19628,9 +19628,9 @@
 /*
 * Low Power PLL Power Down
 */
-#undef DDR_PHY_DX8SL2DQSCTL_LPPLLPD_DEFVAL 
-#undef DDR_PHY_DX8SL2DQSCTL_LPPLLPD_SHIFT 
-#undef DDR_PHY_DX8SL2DQSCTL_LPPLLPD_MASK 
+#undef DDR_PHY_DX8SL2DQSCTL_LPPLLPD_DEFVAL
+#undef DDR_PHY_DX8SL2DQSCTL_LPPLLPD_SHIFT
+#undef DDR_PHY_DX8SL2DQSCTL_LPPLLPD_MASK
 #define DDR_PHY_DX8SL2DQSCTL_LPPLLPD_DEFVAL                    0x01264000
 #define DDR_PHY_DX8SL2DQSCTL_LPPLLPD_SHIFT                     18
 #define DDR_PHY_DX8SL2DQSCTL_LPPLLPD_MASK                      0x00040000U
@@ -19638,9 +19638,9 @@
 /*
 * Low Power I/O Power Down
 */
-#undef DDR_PHY_DX8SL2DQSCTL_LPIOPD_DEFVAL 
-#undef DDR_PHY_DX8SL2DQSCTL_LPIOPD_SHIFT 
-#undef DDR_PHY_DX8SL2DQSCTL_LPIOPD_MASK 
+#undef DDR_PHY_DX8SL2DQSCTL_LPIOPD_DEFVAL
+#undef DDR_PHY_DX8SL2DQSCTL_LPIOPD_SHIFT
+#undef DDR_PHY_DX8SL2DQSCTL_LPIOPD_MASK
 #define DDR_PHY_DX8SL2DQSCTL_LPIOPD_DEFVAL                     0x01264000
 #define DDR_PHY_DX8SL2DQSCTL_LPIOPD_SHIFT                      17
 #define DDR_PHY_DX8SL2DQSCTL_LPIOPD_MASK                       0x00020000U
@@ -19648,9 +19648,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_DEFVAL 
-#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_SHIFT 
-#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_MASK 
+#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_DEFVAL
+#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_SHIFT
+#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_MASK
 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_DEFVAL             0x01264000
 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_SHIFT              15
 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_MASK               0x00018000U
@@ -19658,9 +19658,9 @@
 /*
 * QS Counter Enable
 */
-#undef DDR_PHY_DX8SL2DQSCTL_QSCNTEN_DEFVAL 
-#undef DDR_PHY_DX8SL2DQSCTL_QSCNTEN_SHIFT 
-#undef DDR_PHY_DX8SL2DQSCTL_QSCNTEN_MASK 
+#undef DDR_PHY_DX8SL2DQSCTL_QSCNTEN_DEFVAL
+#undef DDR_PHY_DX8SL2DQSCTL_QSCNTEN_SHIFT
+#undef DDR_PHY_DX8SL2DQSCTL_QSCNTEN_MASK
 #define DDR_PHY_DX8SL2DQSCTL_QSCNTEN_DEFVAL                    0x01264000
 #define DDR_PHY_DX8SL2DQSCTL_QSCNTEN_SHIFT                     14
 #define DDR_PHY_DX8SL2DQSCTL_QSCNTEN_MASK                      0x00004000U
@@ -19668,9 +19668,9 @@
 /*
 * Unused DQ I/O Mode
 */
-#undef DDR_PHY_DX8SL2DQSCTL_UDQIOM_DEFVAL 
-#undef DDR_PHY_DX8SL2DQSCTL_UDQIOM_SHIFT 
-#undef DDR_PHY_DX8SL2DQSCTL_UDQIOM_MASK 
+#undef DDR_PHY_DX8SL2DQSCTL_UDQIOM_DEFVAL
+#undef DDR_PHY_DX8SL2DQSCTL_UDQIOM_SHIFT
+#undef DDR_PHY_DX8SL2DQSCTL_UDQIOM_MASK
 #define DDR_PHY_DX8SL2DQSCTL_UDQIOM_DEFVAL                     0x01264000
 #define DDR_PHY_DX8SL2DQSCTL_UDQIOM_SHIFT                      13
 #define DDR_PHY_DX8SL2DQSCTL_UDQIOM_MASK                       0x00002000U
@@ -19678,9 +19678,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_DEFVAL 
-#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_SHIFT 
-#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_MASK 
+#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_DEFVAL
+#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_SHIFT
+#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_MASK
 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_DEFVAL             0x01264000
 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_SHIFT              10
 #define DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_MASK               0x00001C00U
@@ -19688,9 +19688,9 @@
 /*
 * Data Slew Rate
 */
-#undef DDR_PHY_DX8SL2DQSCTL_DXSR_DEFVAL 
-#undef DDR_PHY_DX8SL2DQSCTL_DXSR_SHIFT 
-#undef DDR_PHY_DX8SL2DQSCTL_DXSR_MASK 
+#undef DDR_PHY_DX8SL2DQSCTL_DXSR_DEFVAL
+#undef DDR_PHY_DX8SL2DQSCTL_DXSR_SHIFT
+#undef DDR_PHY_DX8SL2DQSCTL_DXSR_MASK
 #define DDR_PHY_DX8SL2DQSCTL_DXSR_DEFVAL                       0x01264000
 #define DDR_PHY_DX8SL2DQSCTL_DXSR_SHIFT                        8
 #define DDR_PHY_DX8SL2DQSCTL_DXSR_MASK                         0x00000300U
@@ -19698,9 +19698,9 @@
 /*
 * DQS_N Resistor
 */
-#undef DDR_PHY_DX8SL2DQSCTL_DQSNRES_DEFVAL 
-#undef DDR_PHY_DX8SL2DQSCTL_DQSNRES_SHIFT 
-#undef DDR_PHY_DX8SL2DQSCTL_DQSNRES_MASK 
+#undef DDR_PHY_DX8SL2DQSCTL_DQSNRES_DEFVAL
+#undef DDR_PHY_DX8SL2DQSCTL_DQSNRES_SHIFT
+#undef DDR_PHY_DX8SL2DQSCTL_DQSNRES_MASK
 #define DDR_PHY_DX8SL2DQSCTL_DQSNRES_DEFVAL                    0x01264000
 #define DDR_PHY_DX8SL2DQSCTL_DQSNRES_SHIFT                     4
 #define DDR_PHY_DX8SL2DQSCTL_DQSNRES_MASK                      0x000000F0U
@@ -19708,9 +19708,9 @@
 /*
 * DQS Resistor
 */
-#undef DDR_PHY_DX8SL2DQSCTL_DQSRES_DEFVAL 
-#undef DDR_PHY_DX8SL2DQSCTL_DQSRES_SHIFT 
-#undef DDR_PHY_DX8SL2DQSCTL_DQSRES_MASK 
+#undef DDR_PHY_DX8SL2DQSCTL_DQSRES_DEFVAL
+#undef DDR_PHY_DX8SL2DQSCTL_DQSRES_SHIFT
+#undef DDR_PHY_DX8SL2DQSCTL_DQSRES_MASK
 #define DDR_PHY_DX8SL2DQSCTL_DQSRES_DEFVAL                     0x01264000
 #define DDR_PHY_DX8SL2DQSCTL_DQSRES_SHIFT                      0
 #define DDR_PHY_DX8SL2DQSCTL_DQSRES_MASK                       0x0000000FU
@@ -19718,9 +19718,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_DEFVAL 
-#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_SHIFT 
-#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_MASK 
+#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_DEFVAL
+#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_SHIFT
+#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_MASK
 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_DEFVAL             0x00141800
 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_SHIFT              24
 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_MASK               0xFF000000U
@@ -19728,9 +19728,9 @@
 /*
 * Configurable Read Data Enable
 */
-#undef DDR_PHY_DX8SL2DXCTL2_CRDEN_DEFVAL 
-#undef DDR_PHY_DX8SL2DXCTL2_CRDEN_SHIFT 
-#undef DDR_PHY_DX8SL2DXCTL2_CRDEN_MASK 
+#undef DDR_PHY_DX8SL2DXCTL2_CRDEN_DEFVAL
+#undef DDR_PHY_DX8SL2DXCTL2_CRDEN_SHIFT
+#undef DDR_PHY_DX8SL2DXCTL2_CRDEN_MASK
 #define DDR_PHY_DX8SL2DXCTL2_CRDEN_DEFVAL                      0x00141800
 #define DDR_PHY_DX8SL2DXCTL2_CRDEN_SHIFT                       23
 #define DDR_PHY_DX8SL2DXCTL2_CRDEN_MASK                        0x00800000U
@@ -19738,9 +19738,9 @@
 /*
 * OX Extension during Post-amble
 */
-#undef DDR_PHY_DX8SL2DXCTL2_POSOEX_DEFVAL 
-#undef DDR_PHY_DX8SL2DXCTL2_POSOEX_SHIFT 
-#undef DDR_PHY_DX8SL2DXCTL2_POSOEX_MASK 
+#undef DDR_PHY_DX8SL2DXCTL2_POSOEX_DEFVAL
+#undef DDR_PHY_DX8SL2DXCTL2_POSOEX_SHIFT
+#undef DDR_PHY_DX8SL2DXCTL2_POSOEX_MASK
 #define DDR_PHY_DX8SL2DXCTL2_POSOEX_DEFVAL                     0x00141800
 #define DDR_PHY_DX8SL2DXCTL2_POSOEX_SHIFT                      20
 #define DDR_PHY_DX8SL2DXCTL2_POSOEX_MASK                       0x00700000U
@@ -19748,9 +19748,9 @@
 /*
 * OE Extension during Pre-amble
 */
-#undef DDR_PHY_DX8SL2DXCTL2_PREOEX_DEFVAL 
-#undef DDR_PHY_DX8SL2DXCTL2_PREOEX_SHIFT 
-#undef DDR_PHY_DX8SL2DXCTL2_PREOEX_MASK 
+#undef DDR_PHY_DX8SL2DXCTL2_PREOEX_DEFVAL
+#undef DDR_PHY_DX8SL2DXCTL2_PREOEX_SHIFT
+#undef DDR_PHY_DX8SL2DXCTL2_PREOEX_MASK
 #define DDR_PHY_DX8SL2DXCTL2_PREOEX_DEFVAL                     0x00141800
 #define DDR_PHY_DX8SL2DXCTL2_PREOEX_SHIFT                      18
 #define DDR_PHY_DX8SL2DXCTL2_PREOEX_MASK                       0x000C0000U
@@ -19758,9 +19758,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_17_DEFVAL 
-#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_17_SHIFT 
-#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_17_MASK 
+#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_17_DEFVAL
+#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_17_SHIFT
+#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_17_MASK
 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_17_DEFVAL                0x00141800
 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_17_SHIFT                 17
 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_17_MASK                  0x00020000U
@@ -19768,9 +19768,9 @@
 /*
 * I/O Assisted Gate Select
 */
-#undef DDR_PHY_DX8SL2DXCTL2_IOAG_DEFVAL 
-#undef DDR_PHY_DX8SL2DXCTL2_IOAG_SHIFT 
-#undef DDR_PHY_DX8SL2DXCTL2_IOAG_MASK 
+#undef DDR_PHY_DX8SL2DXCTL2_IOAG_DEFVAL
+#undef DDR_PHY_DX8SL2DXCTL2_IOAG_SHIFT
+#undef DDR_PHY_DX8SL2DXCTL2_IOAG_MASK
 #define DDR_PHY_DX8SL2DXCTL2_IOAG_DEFVAL                       0x00141800
 #define DDR_PHY_DX8SL2DXCTL2_IOAG_SHIFT                        16
 #define DDR_PHY_DX8SL2DXCTL2_IOAG_MASK                         0x00010000U
@@ -19778,9 +19778,9 @@
 /*
 * I/O Loopback Select
 */
-#undef DDR_PHY_DX8SL2DXCTL2_IOLB_DEFVAL 
-#undef DDR_PHY_DX8SL2DXCTL2_IOLB_SHIFT 
-#undef DDR_PHY_DX8SL2DXCTL2_IOLB_MASK 
+#undef DDR_PHY_DX8SL2DXCTL2_IOLB_DEFVAL
+#undef DDR_PHY_DX8SL2DXCTL2_IOLB_SHIFT
+#undef DDR_PHY_DX8SL2DXCTL2_IOLB_MASK
 #define DDR_PHY_DX8SL2DXCTL2_IOLB_DEFVAL                       0x00141800
 #define DDR_PHY_DX8SL2DXCTL2_IOLB_SHIFT                        15
 #define DDR_PHY_DX8SL2DXCTL2_IOLB_MASK                         0x00008000U
@@ -19788,9 +19788,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_DEFVAL 
-#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_SHIFT 
-#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_MASK 
+#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_DEFVAL
+#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_SHIFT
+#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_MASK
 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_DEFVAL             0x00141800
 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_SHIFT              13
 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_MASK               0x00006000U
@@ -19798,9 +19798,9 @@
 /*
 * Low Power Wakeup Threshold
 */
-#undef DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_DEFVAL 
-#undef DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_SHIFT 
-#undef DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_MASK 
+#undef DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_DEFVAL
+#undef DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_SHIFT
+#undef DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_MASK
 #define DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_DEFVAL             0x00141800
 #define DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_SHIFT              9
 #define DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_MASK               0x00001E00U
@@ -19808,9 +19808,9 @@
 /*
 * Read Data Bus Inversion Enable
 */
-#undef DDR_PHY_DX8SL2DXCTL2_RDBI_DEFVAL 
-#undef DDR_PHY_DX8SL2DXCTL2_RDBI_SHIFT 
-#undef DDR_PHY_DX8SL2DXCTL2_RDBI_MASK 
+#undef DDR_PHY_DX8SL2DXCTL2_RDBI_DEFVAL
+#undef DDR_PHY_DX8SL2DXCTL2_RDBI_SHIFT
+#undef DDR_PHY_DX8SL2DXCTL2_RDBI_MASK
 #define DDR_PHY_DX8SL2DXCTL2_RDBI_DEFVAL                       0x00141800
 #define DDR_PHY_DX8SL2DXCTL2_RDBI_SHIFT                        8
 #define DDR_PHY_DX8SL2DXCTL2_RDBI_MASK                         0x00000100U
@@ -19818,9 +19818,9 @@
 /*
 * Write Data Bus Inversion Enable
 */
-#undef DDR_PHY_DX8SL2DXCTL2_WDBI_DEFVAL 
-#undef DDR_PHY_DX8SL2DXCTL2_WDBI_SHIFT 
-#undef DDR_PHY_DX8SL2DXCTL2_WDBI_MASK 
+#undef DDR_PHY_DX8SL2DXCTL2_WDBI_DEFVAL
+#undef DDR_PHY_DX8SL2DXCTL2_WDBI_SHIFT
+#undef DDR_PHY_DX8SL2DXCTL2_WDBI_MASK
 #define DDR_PHY_DX8SL2DXCTL2_WDBI_DEFVAL                       0x00141800
 #define DDR_PHY_DX8SL2DXCTL2_WDBI_SHIFT                        7
 #define DDR_PHY_DX8SL2DXCTL2_WDBI_MASK                         0x00000080U
@@ -19828,9 +19828,9 @@
 /*
 * PUB Read FIFO Bypass
 */
-#undef DDR_PHY_DX8SL2DXCTL2_PRFBYP_DEFVAL 
-#undef DDR_PHY_DX8SL2DXCTL2_PRFBYP_SHIFT 
-#undef DDR_PHY_DX8SL2DXCTL2_PRFBYP_MASK 
+#undef DDR_PHY_DX8SL2DXCTL2_PRFBYP_DEFVAL
+#undef DDR_PHY_DX8SL2DXCTL2_PRFBYP_SHIFT
+#undef DDR_PHY_DX8SL2DXCTL2_PRFBYP_MASK
 #define DDR_PHY_DX8SL2DXCTL2_PRFBYP_DEFVAL                     0x00141800
 #define DDR_PHY_DX8SL2DXCTL2_PRFBYP_SHIFT                      6
 #define DDR_PHY_DX8SL2DXCTL2_PRFBYP_MASK                       0x00000040U
@@ -19838,9 +19838,9 @@
 /*
 * DATX8 Receive FIFO Read Mode
 */
-#undef DDR_PHY_DX8SL2DXCTL2_RDMODE_DEFVAL 
-#undef DDR_PHY_DX8SL2DXCTL2_RDMODE_SHIFT 
-#undef DDR_PHY_DX8SL2DXCTL2_RDMODE_MASK 
+#undef DDR_PHY_DX8SL2DXCTL2_RDMODE_DEFVAL
+#undef DDR_PHY_DX8SL2DXCTL2_RDMODE_SHIFT
+#undef DDR_PHY_DX8SL2DXCTL2_RDMODE_MASK
 #define DDR_PHY_DX8SL2DXCTL2_RDMODE_DEFVAL                     0x00141800
 #define DDR_PHY_DX8SL2DXCTL2_RDMODE_SHIFT                      4
 #define DDR_PHY_DX8SL2DXCTL2_RDMODE_MASK                       0x00000030U
@@ -19848,9 +19848,9 @@
 /*
 * Disables the Read FIFO Reset
 */
-#undef DDR_PHY_DX8SL2DXCTL2_DISRST_DEFVAL 
-#undef DDR_PHY_DX8SL2DXCTL2_DISRST_SHIFT 
-#undef DDR_PHY_DX8SL2DXCTL2_DISRST_MASK 
+#undef DDR_PHY_DX8SL2DXCTL2_DISRST_DEFVAL
+#undef DDR_PHY_DX8SL2DXCTL2_DISRST_SHIFT
+#undef DDR_PHY_DX8SL2DXCTL2_DISRST_MASK
 #define DDR_PHY_DX8SL2DXCTL2_DISRST_DEFVAL                     0x00141800
 #define DDR_PHY_DX8SL2DXCTL2_DISRST_SHIFT                      3
 #define DDR_PHY_DX8SL2DXCTL2_DISRST_MASK                       0x00000008U
@@ -19858,9 +19858,9 @@
 /*
 * Read DQS Gate I/O Loopback
 */
-#undef DDR_PHY_DX8SL2DXCTL2_DQSGLB_DEFVAL 
-#undef DDR_PHY_DX8SL2DXCTL2_DQSGLB_SHIFT 
-#undef DDR_PHY_DX8SL2DXCTL2_DQSGLB_MASK 
+#undef DDR_PHY_DX8SL2DXCTL2_DQSGLB_DEFVAL
+#undef DDR_PHY_DX8SL2DXCTL2_DQSGLB_SHIFT
+#undef DDR_PHY_DX8SL2DXCTL2_DQSGLB_MASK
 #define DDR_PHY_DX8SL2DXCTL2_DQSGLB_DEFVAL                     0x00141800
 #define DDR_PHY_DX8SL2DXCTL2_DQSGLB_SHIFT                      1
 #define DDR_PHY_DX8SL2DXCTL2_DQSGLB_MASK                       0x00000006U
@@ -19868,9 +19868,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_0_DEFVAL 
-#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_0_SHIFT 
-#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_0_MASK 
+#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_0_DEFVAL
+#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_0_SHIFT
+#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_0_MASK
 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_0_DEFVAL                 0x00141800
 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_0_SHIFT                  0
 #define DDR_PHY_DX8SL2DXCTL2_RESERVED_0_MASK                   0x00000001U
@@ -19878,9 +19878,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SL2IOCR_RESERVED_31_DEFVAL 
-#undef DDR_PHY_DX8SL2IOCR_RESERVED_31_SHIFT 
-#undef DDR_PHY_DX8SL2IOCR_RESERVED_31_MASK 
+#undef DDR_PHY_DX8SL2IOCR_RESERVED_31_DEFVAL
+#undef DDR_PHY_DX8SL2IOCR_RESERVED_31_SHIFT
+#undef DDR_PHY_DX8SL2IOCR_RESERVED_31_MASK
 #define DDR_PHY_DX8SL2IOCR_RESERVED_31_DEFVAL                  0x00000000
 #define DDR_PHY_DX8SL2IOCR_RESERVED_31_SHIFT                   31
 #define DDR_PHY_DX8SL2IOCR_RESERVED_31_MASK                    0x80000000U
@@ -19888,9 +19888,9 @@
 /*
 * PVREF_DAC REFSEL range select
 */
-#undef DDR_PHY_DX8SL2IOCR_DXDACRANGE_DEFVAL 
-#undef DDR_PHY_DX8SL2IOCR_DXDACRANGE_SHIFT 
-#undef DDR_PHY_DX8SL2IOCR_DXDACRANGE_MASK 
+#undef DDR_PHY_DX8SL2IOCR_DXDACRANGE_DEFVAL
+#undef DDR_PHY_DX8SL2IOCR_DXDACRANGE_SHIFT
+#undef DDR_PHY_DX8SL2IOCR_DXDACRANGE_MASK
 #define DDR_PHY_DX8SL2IOCR_DXDACRANGE_DEFVAL                   0x00000000
 #define DDR_PHY_DX8SL2IOCR_DXDACRANGE_SHIFT                    28
 #define DDR_PHY_DX8SL2IOCR_DXDACRANGE_MASK                     0x70000000U
@@ -19898,9 +19898,9 @@
 /*
 * IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
 */
-#undef DDR_PHY_DX8SL2IOCR_DXVREFIOM_DEFVAL 
-#undef DDR_PHY_DX8SL2IOCR_DXVREFIOM_SHIFT 
-#undef DDR_PHY_DX8SL2IOCR_DXVREFIOM_MASK 
+#undef DDR_PHY_DX8SL2IOCR_DXVREFIOM_DEFVAL
+#undef DDR_PHY_DX8SL2IOCR_DXVREFIOM_SHIFT
+#undef DDR_PHY_DX8SL2IOCR_DXVREFIOM_MASK
 #define DDR_PHY_DX8SL2IOCR_DXVREFIOM_DEFVAL                    0x00000000
 #define DDR_PHY_DX8SL2IOCR_DXVREFIOM_SHIFT                     25
 #define DDR_PHY_DX8SL2IOCR_DXVREFIOM_MASK                      0x0E000000U
@@ -19908,9 +19908,9 @@
 /*
 * DX IO Mode
 */
-#undef DDR_PHY_DX8SL2IOCR_DXIOM_DEFVAL 
-#undef DDR_PHY_DX8SL2IOCR_DXIOM_SHIFT 
-#undef DDR_PHY_DX8SL2IOCR_DXIOM_MASK 
+#undef DDR_PHY_DX8SL2IOCR_DXIOM_DEFVAL
+#undef DDR_PHY_DX8SL2IOCR_DXIOM_SHIFT
+#undef DDR_PHY_DX8SL2IOCR_DXIOM_MASK
 #define DDR_PHY_DX8SL2IOCR_DXIOM_DEFVAL                        0x00000000
 #define DDR_PHY_DX8SL2IOCR_DXIOM_SHIFT                         22
 #define DDR_PHY_DX8SL2IOCR_DXIOM_MASK                          0x01C00000U
@@ -19918,9 +19918,9 @@
 /*
 * DX IO Transmitter Mode
 */
-#undef DDR_PHY_DX8SL2IOCR_DXTXM_DEFVAL 
-#undef DDR_PHY_DX8SL2IOCR_DXTXM_SHIFT 
-#undef DDR_PHY_DX8SL2IOCR_DXTXM_MASK 
+#undef DDR_PHY_DX8SL2IOCR_DXTXM_DEFVAL
+#undef DDR_PHY_DX8SL2IOCR_DXTXM_SHIFT
+#undef DDR_PHY_DX8SL2IOCR_DXTXM_MASK
 #define DDR_PHY_DX8SL2IOCR_DXTXM_DEFVAL                        0x00000000
 #define DDR_PHY_DX8SL2IOCR_DXTXM_SHIFT                         11
 #define DDR_PHY_DX8SL2IOCR_DXTXM_MASK                          0x003FF800U
@@ -19928,9 +19928,9 @@
 /*
 * DX IO Receiver Mode
 */
-#undef DDR_PHY_DX8SL2IOCR_DXRXM_DEFVAL 
-#undef DDR_PHY_DX8SL2IOCR_DXRXM_SHIFT 
-#undef DDR_PHY_DX8SL2IOCR_DXRXM_MASK 
+#undef DDR_PHY_DX8SL2IOCR_DXRXM_DEFVAL
+#undef DDR_PHY_DX8SL2IOCR_DXRXM_SHIFT
+#undef DDR_PHY_DX8SL2IOCR_DXRXM_MASK
 #define DDR_PHY_DX8SL2IOCR_DXRXM_DEFVAL                        0x00000000
 #define DDR_PHY_DX8SL2IOCR_DXRXM_SHIFT                         0
 #define DDR_PHY_DX8SL2IOCR_DXRXM_MASK                          0x000007FFU
@@ -19938,9 +19938,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SL3OSC_RESERVED_31_30_DEFVAL 
-#undef DDR_PHY_DX8SL3OSC_RESERVED_31_30_SHIFT 
-#undef DDR_PHY_DX8SL3OSC_RESERVED_31_30_MASK 
+#undef DDR_PHY_DX8SL3OSC_RESERVED_31_30_DEFVAL
+#undef DDR_PHY_DX8SL3OSC_RESERVED_31_30_SHIFT
+#undef DDR_PHY_DX8SL3OSC_RESERVED_31_30_MASK
 #define DDR_PHY_DX8SL3OSC_RESERVED_31_30_DEFVAL                0x00019FFE
 #define DDR_PHY_DX8SL3OSC_RESERVED_31_30_SHIFT                 30
 #define DDR_PHY_DX8SL3OSC_RESERVED_31_30_MASK                  0xC0000000U
@@ -19948,9 +19948,9 @@
 /*
 * Enable Clock Gating for DX ddr_clk
 */
-#undef DDR_PHY_DX8SL3OSC_GATEDXRDCLK_DEFVAL 
-#undef DDR_PHY_DX8SL3OSC_GATEDXRDCLK_SHIFT 
-#undef DDR_PHY_DX8SL3OSC_GATEDXRDCLK_MASK 
+#undef DDR_PHY_DX8SL3OSC_GATEDXRDCLK_DEFVAL
+#undef DDR_PHY_DX8SL3OSC_GATEDXRDCLK_SHIFT
+#undef DDR_PHY_DX8SL3OSC_GATEDXRDCLK_MASK
 #define DDR_PHY_DX8SL3OSC_GATEDXRDCLK_DEFVAL                   0x00019FFE
 #define DDR_PHY_DX8SL3OSC_GATEDXRDCLK_SHIFT                    28
 #define DDR_PHY_DX8SL3OSC_GATEDXRDCLK_MASK                     0x30000000U
@@ -19958,9 +19958,9 @@
 /*
 * Enable Clock Gating for DX ctl_rd_clk
 */
-#undef DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_DEFVAL 
-#undef DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_SHIFT 
-#undef DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_MASK 
+#undef DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_DEFVAL
+#undef DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_SHIFT
+#undef DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_MASK
 #define DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_DEFVAL                  0x00019FFE
 #define DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_SHIFT                   26
 #define DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_MASK                    0x0C000000U
@@ -19968,9 +19968,9 @@
 /*
 * Enable Clock Gating for DX ctl_clk
 */
-#undef DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_DEFVAL 
-#undef DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_SHIFT 
-#undef DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_MASK 
+#undef DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_DEFVAL
+#undef DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_SHIFT
+#undef DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_MASK
 #define DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_DEFVAL                  0x00019FFE
 #define DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_SHIFT                   24
 #define DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_MASK                    0x03000000U
@@ -19979,9 +19979,9 @@
 * Selects the level to which clocks will be stalled when clock gating is e
     * nabled.
 */
-#undef DDR_PHY_DX8SL3OSC_CLKLEVEL_DEFVAL 
-#undef DDR_PHY_DX8SL3OSC_CLKLEVEL_SHIFT 
-#undef DDR_PHY_DX8SL3OSC_CLKLEVEL_MASK 
+#undef DDR_PHY_DX8SL3OSC_CLKLEVEL_DEFVAL
+#undef DDR_PHY_DX8SL3OSC_CLKLEVEL_SHIFT
+#undef DDR_PHY_DX8SL3OSC_CLKLEVEL_MASK
 #define DDR_PHY_DX8SL3OSC_CLKLEVEL_DEFVAL                      0x00019FFE
 #define DDR_PHY_DX8SL3OSC_CLKLEVEL_SHIFT                       22
 #define DDR_PHY_DX8SL3OSC_CLKLEVEL_MASK                        0x00C00000U
@@ -19989,9 +19989,9 @@
 /*
 * Loopback Mode
 */
-#undef DDR_PHY_DX8SL3OSC_LBMODE_DEFVAL 
-#undef DDR_PHY_DX8SL3OSC_LBMODE_SHIFT 
-#undef DDR_PHY_DX8SL3OSC_LBMODE_MASK 
+#undef DDR_PHY_DX8SL3OSC_LBMODE_DEFVAL
+#undef DDR_PHY_DX8SL3OSC_LBMODE_SHIFT
+#undef DDR_PHY_DX8SL3OSC_LBMODE_MASK
 #define DDR_PHY_DX8SL3OSC_LBMODE_DEFVAL                        0x00019FFE
 #define DDR_PHY_DX8SL3OSC_LBMODE_SHIFT                         21
 #define DDR_PHY_DX8SL3OSC_LBMODE_MASK                          0x00200000U
@@ -19999,9 +19999,9 @@
 /*
 * Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
 */
-#undef DDR_PHY_DX8SL3OSC_LBGSDQS_DEFVAL 
-#undef DDR_PHY_DX8SL3OSC_LBGSDQS_SHIFT 
-#undef DDR_PHY_DX8SL3OSC_LBGSDQS_MASK 
+#undef DDR_PHY_DX8SL3OSC_LBGSDQS_DEFVAL
+#undef DDR_PHY_DX8SL3OSC_LBGSDQS_SHIFT
+#undef DDR_PHY_DX8SL3OSC_LBGSDQS_MASK
 #define DDR_PHY_DX8SL3OSC_LBGSDQS_DEFVAL                       0x00019FFE
 #define DDR_PHY_DX8SL3OSC_LBGSDQS_SHIFT                        20
 #define DDR_PHY_DX8SL3OSC_LBGSDQS_MASK                         0x00100000U
@@ -20009,9 +20009,9 @@
 /*
 * Loopback DQS Gating
 */
-#undef DDR_PHY_DX8SL3OSC_LBGDQS_DEFVAL 
-#undef DDR_PHY_DX8SL3OSC_LBGDQS_SHIFT 
-#undef DDR_PHY_DX8SL3OSC_LBGDQS_MASK 
+#undef DDR_PHY_DX8SL3OSC_LBGDQS_DEFVAL
+#undef DDR_PHY_DX8SL3OSC_LBGDQS_SHIFT
+#undef DDR_PHY_DX8SL3OSC_LBGDQS_MASK
 #define DDR_PHY_DX8SL3OSC_LBGDQS_DEFVAL                        0x00019FFE
 #define DDR_PHY_DX8SL3OSC_LBGDQS_SHIFT                         18
 #define DDR_PHY_DX8SL3OSC_LBGDQS_MASK                          0x000C0000U
@@ -20019,9 +20019,9 @@
 /*
 * Loopback DQS Shift
 */
-#undef DDR_PHY_DX8SL3OSC_LBDQSS_DEFVAL 
-#undef DDR_PHY_DX8SL3OSC_LBDQSS_SHIFT 
-#undef DDR_PHY_DX8SL3OSC_LBDQSS_MASK 
+#undef DDR_PHY_DX8SL3OSC_LBDQSS_DEFVAL
+#undef DDR_PHY_DX8SL3OSC_LBDQSS_SHIFT
+#undef DDR_PHY_DX8SL3OSC_LBDQSS_MASK
 #define DDR_PHY_DX8SL3OSC_LBDQSS_DEFVAL                        0x00019FFE
 #define DDR_PHY_DX8SL3OSC_LBDQSS_SHIFT                         17
 #define DDR_PHY_DX8SL3OSC_LBDQSS_MASK                          0x00020000U
@@ -20029,9 +20029,9 @@
 /*
 * PHY High-Speed Reset
 */
-#undef DDR_PHY_DX8SL3OSC_PHYHRST_DEFVAL 
-#undef DDR_PHY_DX8SL3OSC_PHYHRST_SHIFT 
-#undef DDR_PHY_DX8SL3OSC_PHYHRST_MASK 
+#undef DDR_PHY_DX8SL3OSC_PHYHRST_DEFVAL
+#undef DDR_PHY_DX8SL3OSC_PHYHRST_SHIFT
+#undef DDR_PHY_DX8SL3OSC_PHYHRST_MASK
 #define DDR_PHY_DX8SL3OSC_PHYHRST_DEFVAL                       0x00019FFE
 #define DDR_PHY_DX8SL3OSC_PHYHRST_SHIFT                        16
 #define DDR_PHY_DX8SL3OSC_PHYHRST_MASK                         0x00010000U
@@ -20039,9 +20039,9 @@
 /*
 * PHY FIFO Reset
 */
-#undef DDR_PHY_DX8SL3OSC_PHYFRST_DEFVAL 
-#undef DDR_PHY_DX8SL3OSC_PHYFRST_SHIFT 
-#undef DDR_PHY_DX8SL3OSC_PHYFRST_MASK 
+#undef DDR_PHY_DX8SL3OSC_PHYFRST_DEFVAL
+#undef DDR_PHY_DX8SL3OSC_PHYFRST_SHIFT
+#undef DDR_PHY_DX8SL3OSC_PHYFRST_MASK
 #define DDR_PHY_DX8SL3OSC_PHYFRST_DEFVAL                       0x00019FFE
 #define DDR_PHY_DX8SL3OSC_PHYFRST_SHIFT                        15
 #define DDR_PHY_DX8SL3OSC_PHYFRST_MASK                         0x00008000U
@@ -20049,9 +20049,9 @@
 /*
 * Delay Line Test Start
 */
-#undef DDR_PHY_DX8SL3OSC_DLTST_DEFVAL 
-#undef DDR_PHY_DX8SL3OSC_DLTST_SHIFT 
-#undef DDR_PHY_DX8SL3OSC_DLTST_MASK 
+#undef DDR_PHY_DX8SL3OSC_DLTST_DEFVAL
+#undef DDR_PHY_DX8SL3OSC_DLTST_SHIFT
+#undef DDR_PHY_DX8SL3OSC_DLTST_MASK
 #define DDR_PHY_DX8SL3OSC_DLTST_DEFVAL                         0x00019FFE
 #define DDR_PHY_DX8SL3OSC_DLTST_SHIFT                          14
 #define DDR_PHY_DX8SL3OSC_DLTST_MASK                           0x00004000U
@@ -20059,9 +20059,9 @@
 /*
 * Delay Line Test Mode
 */
-#undef DDR_PHY_DX8SL3OSC_DLTMODE_DEFVAL 
-#undef DDR_PHY_DX8SL3OSC_DLTMODE_SHIFT 
-#undef DDR_PHY_DX8SL3OSC_DLTMODE_MASK 
+#undef DDR_PHY_DX8SL3OSC_DLTMODE_DEFVAL
+#undef DDR_PHY_DX8SL3OSC_DLTMODE_SHIFT
+#undef DDR_PHY_DX8SL3OSC_DLTMODE_MASK
 #define DDR_PHY_DX8SL3OSC_DLTMODE_DEFVAL                       0x00019FFE
 #define DDR_PHY_DX8SL3OSC_DLTMODE_SHIFT                        13
 #define DDR_PHY_DX8SL3OSC_DLTMODE_MASK                         0x00002000U
@@ -20069,9 +20069,9 @@
 /*
 * Reserved. Caution, do not write to this register field.
 */
-#undef DDR_PHY_DX8SL3OSC_RESERVED_12_11_DEFVAL 
-#undef DDR_PHY_DX8SL3OSC_RESERVED_12_11_SHIFT 
-#undef DDR_PHY_DX8SL3OSC_RESERVED_12_11_MASK 
+#undef DDR_PHY_DX8SL3OSC_RESERVED_12_11_DEFVAL
+#undef DDR_PHY_DX8SL3OSC_RESERVED_12_11_SHIFT
+#undef DDR_PHY_DX8SL3OSC_RESERVED_12_11_MASK
 #define DDR_PHY_DX8SL3OSC_RESERVED_12_11_DEFVAL                0x00019FFE
 #define DDR_PHY_DX8SL3OSC_RESERVED_12_11_SHIFT                 11
 #define DDR_PHY_DX8SL3OSC_RESERVED_12_11_MASK                  0x00001800U
@@ -20079,9 +20079,9 @@
 /*
 * Oscillator Mode Write-Data Delay Line Select
 */
-#undef DDR_PHY_DX8SL3OSC_OSCWDDL_DEFVAL 
-#undef DDR_PHY_DX8SL3OSC_OSCWDDL_SHIFT 
-#undef DDR_PHY_DX8SL3OSC_OSCWDDL_MASK 
+#undef DDR_PHY_DX8SL3OSC_OSCWDDL_DEFVAL
+#undef DDR_PHY_DX8SL3OSC_OSCWDDL_SHIFT
+#undef DDR_PHY_DX8SL3OSC_OSCWDDL_MASK
 #define DDR_PHY_DX8SL3OSC_OSCWDDL_DEFVAL                       0x00019FFE
 #define DDR_PHY_DX8SL3OSC_OSCWDDL_SHIFT                        9
 #define DDR_PHY_DX8SL3OSC_OSCWDDL_MASK                         0x00000600U
@@ -20089,9 +20089,9 @@
 /*
 * Reserved. Caution, do not write to this register field.
 */
-#undef DDR_PHY_DX8SL3OSC_RESERVED_8_7_DEFVAL 
-#undef DDR_PHY_DX8SL3OSC_RESERVED_8_7_SHIFT 
-#undef DDR_PHY_DX8SL3OSC_RESERVED_8_7_MASK 
+#undef DDR_PHY_DX8SL3OSC_RESERVED_8_7_DEFVAL
+#undef DDR_PHY_DX8SL3OSC_RESERVED_8_7_SHIFT
+#undef DDR_PHY_DX8SL3OSC_RESERVED_8_7_MASK
 #define DDR_PHY_DX8SL3OSC_RESERVED_8_7_DEFVAL                  0x00019FFE
 #define DDR_PHY_DX8SL3OSC_RESERVED_8_7_SHIFT                   7
 #define DDR_PHY_DX8SL3OSC_RESERVED_8_7_MASK                    0x00000180U
@@ -20099,9 +20099,9 @@
 /*
 * Oscillator Mode Write-Leveling Delay Line Select
 */
-#undef DDR_PHY_DX8SL3OSC_OSCWDL_DEFVAL 
-#undef DDR_PHY_DX8SL3OSC_OSCWDL_SHIFT 
-#undef DDR_PHY_DX8SL3OSC_OSCWDL_MASK 
+#undef DDR_PHY_DX8SL3OSC_OSCWDL_DEFVAL
+#undef DDR_PHY_DX8SL3OSC_OSCWDL_SHIFT
+#undef DDR_PHY_DX8SL3OSC_OSCWDL_MASK
 #define DDR_PHY_DX8SL3OSC_OSCWDL_DEFVAL                        0x00019FFE
 #define DDR_PHY_DX8SL3OSC_OSCWDL_SHIFT                         5
 #define DDR_PHY_DX8SL3OSC_OSCWDL_MASK                          0x00000060U
@@ -20109,9 +20109,9 @@
 /*
 * Oscillator Mode Division
 */
-#undef DDR_PHY_DX8SL3OSC_OSCDIV_DEFVAL 
-#undef DDR_PHY_DX8SL3OSC_OSCDIV_SHIFT 
-#undef DDR_PHY_DX8SL3OSC_OSCDIV_MASK 
+#undef DDR_PHY_DX8SL3OSC_OSCDIV_DEFVAL
+#undef DDR_PHY_DX8SL3OSC_OSCDIV_SHIFT
+#undef DDR_PHY_DX8SL3OSC_OSCDIV_MASK
 #define DDR_PHY_DX8SL3OSC_OSCDIV_DEFVAL                        0x00019FFE
 #define DDR_PHY_DX8SL3OSC_OSCDIV_SHIFT                         1
 #define DDR_PHY_DX8SL3OSC_OSCDIV_MASK                          0x0000001EU
@@ -20119,9 +20119,9 @@
 /*
 * Oscillator Enable
 */
-#undef DDR_PHY_DX8SL3OSC_OSCEN_DEFVAL 
-#undef DDR_PHY_DX8SL3OSC_OSCEN_SHIFT 
-#undef DDR_PHY_DX8SL3OSC_OSCEN_MASK 
+#undef DDR_PHY_DX8SL3OSC_OSCEN_DEFVAL
+#undef DDR_PHY_DX8SL3OSC_OSCEN_SHIFT
+#undef DDR_PHY_DX8SL3OSC_OSCEN_MASK
 #define DDR_PHY_DX8SL3OSC_OSCEN_DEFVAL                         0x00019FFE
 #define DDR_PHY_DX8SL3OSC_OSCEN_SHIFT                          0
 #define DDR_PHY_DX8SL3OSC_OSCEN_MASK                           0x00000001U
@@ -20129,9 +20129,9 @@
 /*
 * PLL Bypass
 */
-#undef DDR_PHY_DX8SL3PLLCR0_PLLBYP_DEFVAL 
-#undef DDR_PHY_DX8SL3PLLCR0_PLLBYP_SHIFT 
-#undef DDR_PHY_DX8SL3PLLCR0_PLLBYP_MASK 
+#undef DDR_PHY_DX8SL3PLLCR0_PLLBYP_DEFVAL
+#undef DDR_PHY_DX8SL3PLLCR0_PLLBYP_SHIFT
+#undef DDR_PHY_DX8SL3PLLCR0_PLLBYP_MASK
 #define DDR_PHY_DX8SL3PLLCR0_PLLBYP_DEFVAL                     0x001C0000
 #define DDR_PHY_DX8SL3PLLCR0_PLLBYP_SHIFT                      31
 #define DDR_PHY_DX8SL3PLLCR0_PLLBYP_MASK                       0x80000000U
@@ -20139,9 +20139,9 @@
 /*
 * PLL Reset
 */
-#undef DDR_PHY_DX8SL3PLLCR0_PLLRST_DEFVAL 
-#undef DDR_PHY_DX8SL3PLLCR0_PLLRST_SHIFT 
-#undef DDR_PHY_DX8SL3PLLCR0_PLLRST_MASK 
+#undef DDR_PHY_DX8SL3PLLCR0_PLLRST_DEFVAL
+#undef DDR_PHY_DX8SL3PLLCR0_PLLRST_SHIFT
+#undef DDR_PHY_DX8SL3PLLCR0_PLLRST_MASK
 #define DDR_PHY_DX8SL3PLLCR0_PLLRST_DEFVAL                     0x001C0000
 #define DDR_PHY_DX8SL3PLLCR0_PLLRST_SHIFT                      30
 #define DDR_PHY_DX8SL3PLLCR0_PLLRST_MASK                       0x40000000U
@@ -20149,9 +20149,9 @@
 /*
 * PLL Power Down
 */
-#undef DDR_PHY_DX8SL3PLLCR0_PLLPD_DEFVAL 
-#undef DDR_PHY_DX8SL3PLLCR0_PLLPD_SHIFT 
-#undef DDR_PHY_DX8SL3PLLCR0_PLLPD_MASK 
+#undef DDR_PHY_DX8SL3PLLCR0_PLLPD_DEFVAL
+#undef DDR_PHY_DX8SL3PLLCR0_PLLPD_SHIFT
+#undef DDR_PHY_DX8SL3PLLCR0_PLLPD_MASK
 #define DDR_PHY_DX8SL3PLLCR0_PLLPD_DEFVAL                      0x001C0000
 #define DDR_PHY_DX8SL3PLLCR0_PLLPD_SHIFT                       29
 #define DDR_PHY_DX8SL3PLLCR0_PLLPD_MASK                        0x20000000U
@@ -20159,9 +20159,9 @@
 /*
 * Reference Stop Mode
 */
-#undef DDR_PHY_DX8SL3PLLCR0_RSTOPM_DEFVAL 
-#undef DDR_PHY_DX8SL3PLLCR0_RSTOPM_SHIFT 
-#undef DDR_PHY_DX8SL3PLLCR0_RSTOPM_MASK 
+#undef DDR_PHY_DX8SL3PLLCR0_RSTOPM_DEFVAL
+#undef DDR_PHY_DX8SL3PLLCR0_RSTOPM_SHIFT
+#undef DDR_PHY_DX8SL3PLLCR0_RSTOPM_MASK
 #define DDR_PHY_DX8SL3PLLCR0_RSTOPM_DEFVAL                     0x001C0000
 #define DDR_PHY_DX8SL3PLLCR0_RSTOPM_SHIFT                      28
 #define DDR_PHY_DX8SL3PLLCR0_RSTOPM_MASK                       0x10000000U
@@ -20169,9 +20169,9 @@
 /*
 * PLL Frequency Select
 */
-#undef DDR_PHY_DX8SL3PLLCR0_FRQSEL_DEFVAL 
-#undef DDR_PHY_DX8SL3PLLCR0_FRQSEL_SHIFT 
-#undef DDR_PHY_DX8SL3PLLCR0_FRQSEL_MASK 
+#undef DDR_PHY_DX8SL3PLLCR0_FRQSEL_DEFVAL
+#undef DDR_PHY_DX8SL3PLLCR0_FRQSEL_SHIFT
+#undef DDR_PHY_DX8SL3PLLCR0_FRQSEL_MASK
 #define DDR_PHY_DX8SL3PLLCR0_FRQSEL_DEFVAL                     0x001C0000
 #define DDR_PHY_DX8SL3PLLCR0_FRQSEL_SHIFT                      24
 #define DDR_PHY_DX8SL3PLLCR0_FRQSEL_MASK                       0x0F000000U
@@ -20179,9 +20179,9 @@
 /*
 * Relock Mode
 */
-#undef DDR_PHY_DX8SL3PLLCR0_RLOCKM_DEFVAL 
-#undef DDR_PHY_DX8SL3PLLCR0_RLOCKM_SHIFT 
-#undef DDR_PHY_DX8SL3PLLCR0_RLOCKM_MASK 
+#undef DDR_PHY_DX8SL3PLLCR0_RLOCKM_DEFVAL
+#undef DDR_PHY_DX8SL3PLLCR0_RLOCKM_SHIFT
+#undef DDR_PHY_DX8SL3PLLCR0_RLOCKM_MASK
 #define DDR_PHY_DX8SL3PLLCR0_RLOCKM_DEFVAL                     0x001C0000
 #define DDR_PHY_DX8SL3PLLCR0_RLOCKM_SHIFT                      23
 #define DDR_PHY_DX8SL3PLLCR0_RLOCKM_MASK                       0x00800000U
@@ -20189,9 +20189,9 @@
 /*
 * Charge Pump Proportional Current Control
 */
-#undef DDR_PHY_DX8SL3PLLCR0_CPPC_DEFVAL 
-#undef DDR_PHY_DX8SL3PLLCR0_CPPC_SHIFT 
-#undef DDR_PHY_DX8SL3PLLCR0_CPPC_MASK 
+#undef DDR_PHY_DX8SL3PLLCR0_CPPC_DEFVAL
+#undef DDR_PHY_DX8SL3PLLCR0_CPPC_SHIFT
+#undef DDR_PHY_DX8SL3PLLCR0_CPPC_MASK
 #define DDR_PHY_DX8SL3PLLCR0_CPPC_DEFVAL                       0x001C0000
 #define DDR_PHY_DX8SL3PLLCR0_CPPC_SHIFT                        17
 #define DDR_PHY_DX8SL3PLLCR0_CPPC_MASK                         0x007E0000U
@@ -20199,9 +20199,9 @@
 /*
 * Charge Pump Integrating Current Control
 */
-#undef DDR_PHY_DX8SL3PLLCR0_CPIC_DEFVAL 
-#undef DDR_PHY_DX8SL3PLLCR0_CPIC_SHIFT 
-#undef DDR_PHY_DX8SL3PLLCR0_CPIC_MASK 
+#undef DDR_PHY_DX8SL3PLLCR0_CPIC_DEFVAL
+#undef DDR_PHY_DX8SL3PLLCR0_CPIC_SHIFT
+#undef DDR_PHY_DX8SL3PLLCR0_CPIC_MASK
 #define DDR_PHY_DX8SL3PLLCR0_CPIC_DEFVAL                       0x001C0000
 #define DDR_PHY_DX8SL3PLLCR0_CPIC_SHIFT                        13
 #define DDR_PHY_DX8SL3PLLCR0_CPIC_MASK                         0x0001E000U
@@ -20209,9 +20209,9 @@
 /*
 * Gear Shift
 */
-#undef DDR_PHY_DX8SL3PLLCR0_GSHIFT_DEFVAL 
-#undef DDR_PHY_DX8SL3PLLCR0_GSHIFT_SHIFT 
-#undef DDR_PHY_DX8SL3PLLCR0_GSHIFT_MASK 
+#undef DDR_PHY_DX8SL3PLLCR0_GSHIFT_DEFVAL
+#undef DDR_PHY_DX8SL3PLLCR0_GSHIFT_SHIFT
+#undef DDR_PHY_DX8SL3PLLCR0_GSHIFT_MASK
 #define DDR_PHY_DX8SL3PLLCR0_GSHIFT_DEFVAL                     0x001C0000
 #define DDR_PHY_DX8SL3PLLCR0_GSHIFT_SHIFT                      12
 #define DDR_PHY_DX8SL3PLLCR0_GSHIFT_MASK                       0x00001000U
@@ -20219,9 +20219,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9_DEFVAL 
-#undef DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9_SHIFT 
-#undef DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9_MASK 
+#undef DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9_DEFVAL
+#undef DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9_SHIFT
+#undef DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9_MASK
 #define DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9_DEFVAL              0x001C0000
 #define DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9_SHIFT               9
 #define DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9_MASK                0x00000E00U
@@ -20229,9 +20229,9 @@
 /*
 * Analog Test Enable (ATOEN)
 */
-#undef DDR_PHY_DX8SL3PLLCR0_ATOEN_DEFVAL 
-#undef DDR_PHY_DX8SL3PLLCR0_ATOEN_SHIFT 
-#undef DDR_PHY_DX8SL3PLLCR0_ATOEN_MASK 
+#undef DDR_PHY_DX8SL3PLLCR0_ATOEN_DEFVAL
+#undef DDR_PHY_DX8SL3PLLCR0_ATOEN_SHIFT
+#undef DDR_PHY_DX8SL3PLLCR0_ATOEN_MASK
 #define DDR_PHY_DX8SL3PLLCR0_ATOEN_DEFVAL                      0x001C0000
 #define DDR_PHY_DX8SL3PLLCR0_ATOEN_SHIFT                       8
 #define DDR_PHY_DX8SL3PLLCR0_ATOEN_MASK                        0x00000100U
@@ -20239,9 +20239,9 @@
 /*
 * Analog Test Control
 */
-#undef DDR_PHY_DX8SL3PLLCR0_ATC_DEFVAL 
-#undef DDR_PHY_DX8SL3PLLCR0_ATC_SHIFT 
-#undef DDR_PHY_DX8SL3PLLCR0_ATC_MASK 
+#undef DDR_PHY_DX8SL3PLLCR0_ATC_DEFVAL
+#undef DDR_PHY_DX8SL3PLLCR0_ATC_SHIFT
+#undef DDR_PHY_DX8SL3PLLCR0_ATC_MASK
 #define DDR_PHY_DX8SL3PLLCR0_ATC_DEFVAL                        0x001C0000
 #define DDR_PHY_DX8SL3PLLCR0_ATC_SHIFT                         4
 #define DDR_PHY_DX8SL3PLLCR0_ATC_MASK                          0x000000F0U
@@ -20249,9 +20249,9 @@
 /*
 * Digital Test Control
 */
-#undef DDR_PHY_DX8SL3PLLCR0_DTC_DEFVAL 
-#undef DDR_PHY_DX8SL3PLLCR0_DTC_SHIFT 
-#undef DDR_PHY_DX8SL3PLLCR0_DTC_MASK 
+#undef DDR_PHY_DX8SL3PLLCR0_DTC_DEFVAL
+#undef DDR_PHY_DX8SL3PLLCR0_DTC_SHIFT
+#undef DDR_PHY_DX8SL3PLLCR0_DTC_MASK
 #define DDR_PHY_DX8SL3PLLCR0_DTC_DEFVAL                        0x001C0000
 #define DDR_PHY_DX8SL3PLLCR0_DTC_SHIFT                         0
 #define DDR_PHY_DX8SL3PLLCR0_DTC_MASK                          0x0000000FU
@@ -20259,9 +20259,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_DEFVAL 
-#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_SHIFT 
-#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_MASK 
+#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_DEFVAL
+#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_SHIFT
+#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_MASK
 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_DEFVAL             0x01264000
 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_SHIFT              25
 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_MASK               0xFE000000U
@@ -20269,9 +20269,9 @@
 /*
 * Read Path Rise-to-Rise Mode
 */
-#undef DDR_PHY_DX8SL3DQSCTL_RRRMODE_DEFVAL 
-#undef DDR_PHY_DX8SL3DQSCTL_RRRMODE_SHIFT 
-#undef DDR_PHY_DX8SL3DQSCTL_RRRMODE_MASK 
+#undef DDR_PHY_DX8SL3DQSCTL_RRRMODE_DEFVAL
+#undef DDR_PHY_DX8SL3DQSCTL_RRRMODE_SHIFT
+#undef DDR_PHY_DX8SL3DQSCTL_RRRMODE_MASK
 #define DDR_PHY_DX8SL3DQSCTL_RRRMODE_DEFVAL                    0x01264000
 #define DDR_PHY_DX8SL3DQSCTL_RRRMODE_SHIFT                     24
 #define DDR_PHY_DX8SL3DQSCTL_RRRMODE_MASK                      0x01000000U
@@ -20279,9 +20279,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_DEFVAL 
-#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_SHIFT 
-#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_MASK 
+#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_DEFVAL
+#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_SHIFT
+#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_MASK
 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_DEFVAL             0x01264000
 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_SHIFT              22
 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_MASK               0x00C00000U
@@ -20289,9 +20289,9 @@
 /*
 * Write Path Rise-to-Rise Mode
 */
-#undef DDR_PHY_DX8SL3DQSCTL_WRRMODE_DEFVAL 
-#undef DDR_PHY_DX8SL3DQSCTL_WRRMODE_SHIFT 
-#undef DDR_PHY_DX8SL3DQSCTL_WRRMODE_MASK 
+#undef DDR_PHY_DX8SL3DQSCTL_WRRMODE_DEFVAL
+#undef DDR_PHY_DX8SL3DQSCTL_WRRMODE_SHIFT
+#undef DDR_PHY_DX8SL3DQSCTL_WRRMODE_MASK
 #define DDR_PHY_DX8SL3DQSCTL_WRRMODE_DEFVAL                    0x01264000
 #define DDR_PHY_DX8SL3DQSCTL_WRRMODE_SHIFT                     21
 #define DDR_PHY_DX8SL3DQSCTL_WRRMODE_MASK                      0x00200000U
@@ -20299,9 +20299,9 @@
 /*
 * DQS Gate Extension
 */
-#undef DDR_PHY_DX8SL3DQSCTL_DQSGX_DEFVAL 
-#undef DDR_PHY_DX8SL3DQSCTL_DQSGX_SHIFT 
-#undef DDR_PHY_DX8SL3DQSCTL_DQSGX_MASK 
+#undef DDR_PHY_DX8SL3DQSCTL_DQSGX_DEFVAL
+#undef DDR_PHY_DX8SL3DQSCTL_DQSGX_SHIFT
+#undef DDR_PHY_DX8SL3DQSCTL_DQSGX_MASK
 #define DDR_PHY_DX8SL3DQSCTL_DQSGX_DEFVAL                      0x01264000
 #define DDR_PHY_DX8SL3DQSCTL_DQSGX_SHIFT                       19
 #define DDR_PHY_DX8SL3DQSCTL_DQSGX_MASK                        0x00180000U
@@ -20309,9 +20309,9 @@
 /*
 * Low Power PLL Power Down
 */
-#undef DDR_PHY_DX8SL3DQSCTL_LPPLLPD_DEFVAL 
-#undef DDR_PHY_DX8SL3DQSCTL_LPPLLPD_SHIFT 
-#undef DDR_PHY_DX8SL3DQSCTL_LPPLLPD_MASK 
+#undef DDR_PHY_DX8SL3DQSCTL_LPPLLPD_DEFVAL
+#undef DDR_PHY_DX8SL3DQSCTL_LPPLLPD_SHIFT
+#undef DDR_PHY_DX8SL3DQSCTL_LPPLLPD_MASK
 #define DDR_PHY_DX8SL3DQSCTL_LPPLLPD_DEFVAL                    0x01264000
 #define DDR_PHY_DX8SL3DQSCTL_LPPLLPD_SHIFT                     18
 #define DDR_PHY_DX8SL3DQSCTL_LPPLLPD_MASK                      0x00040000U
@@ -20319,9 +20319,9 @@
 /*
 * Low Power I/O Power Down
 */
-#undef DDR_PHY_DX8SL3DQSCTL_LPIOPD_DEFVAL 
-#undef DDR_PHY_DX8SL3DQSCTL_LPIOPD_SHIFT 
-#undef DDR_PHY_DX8SL3DQSCTL_LPIOPD_MASK 
+#undef DDR_PHY_DX8SL3DQSCTL_LPIOPD_DEFVAL
+#undef DDR_PHY_DX8SL3DQSCTL_LPIOPD_SHIFT
+#undef DDR_PHY_DX8SL3DQSCTL_LPIOPD_MASK
 #define DDR_PHY_DX8SL3DQSCTL_LPIOPD_DEFVAL                     0x01264000
 #define DDR_PHY_DX8SL3DQSCTL_LPIOPD_SHIFT                      17
 #define DDR_PHY_DX8SL3DQSCTL_LPIOPD_MASK                       0x00020000U
@@ -20329,9 +20329,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_DEFVAL 
-#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_SHIFT 
-#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_MASK 
+#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_DEFVAL
+#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_SHIFT
+#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_MASK
 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_DEFVAL             0x01264000
 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_SHIFT              15
 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_MASK               0x00018000U
@@ -20339,9 +20339,9 @@
 /*
 * QS Counter Enable
 */
-#undef DDR_PHY_DX8SL3DQSCTL_QSCNTEN_DEFVAL 
-#undef DDR_PHY_DX8SL3DQSCTL_QSCNTEN_SHIFT 
-#undef DDR_PHY_DX8SL3DQSCTL_QSCNTEN_MASK 
+#undef DDR_PHY_DX8SL3DQSCTL_QSCNTEN_DEFVAL
+#undef DDR_PHY_DX8SL3DQSCTL_QSCNTEN_SHIFT
+#undef DDR_PHY_DX8SL3DQSCTL_QSCNTEN_MASK
 #define DDR_PHY_DX8SL3DQSCTL_QSCNTEN_DEFVAL                    0x01264000
 #define DDR_PHY_DX8SL3DQSCTL_QSCNTEN_SHIFT                     14
 #define DDR_PHY_DX8SL3DQSCTL_QSCNTEN_MASK                      0x00004000U
@@ -20349,9 +20349,9 @@
 /*
 * Unused DQ I/O Mode
 */
-#undef DDR_PHY_DX8SL3DQSCTL_UDQIOM_DEFVAL 
-#undef DDR_PHY_DX8SL3DQSCTL_UDQIOM_SHIFT 
-#undef DDR_PHY_DX8SL3DQSCTL_UDQIOM_MASK 
+#undef DDR_PHY_DX8SL3DQSCTL_UDQIOM_DEFVAL
+#undef DDR_PHY_DX8SL3DQSCTL_UDQIOM_SHIFT
+#undef DDR_PHY_DX8SL3DQSCTL_UDQIOM_MASK
 #define DDR_PHY_DX8SL3DQSCTL_UDQIOM_DEFVAL                     0x01264000
 #define DDR_PHY_DX8SL3DQSCTL_UDQIOM_SHIFT                      13
 #define DDR_PHY_DX8SL3DQSCTL_UDQIOM_MASK                       0x00002000U
@@ -20359,9 +20359,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_DEFVAL 
-#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_SHIFT 
-#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_MASK 
+#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_DEFVAL
+#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_SHIFT
+#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_MASK
 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_DEFVAL             0x01264000
 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_SHIFT              10
 #define DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_MASK               0x00001C00U
@@ -20369,9 +20369,9 @@
 /*
 * Data Slew Rate
 */
-#undef DDR_PHY_DX8SL3DQSCTL_DXSR_DEFVAL 
-#undef DDR_PHY_DX8SL3DQSCTL_DXSR_SHIFT 
-#undef DDR_PHY_DX8SL3DQSCTL_DXSR_MASK 
+#undef DDR_PHY_DX8SL3DQSCTL_DXSR_DEFVAL
+#undef DDR_PHY_DX8SL3DQSCTL_DXSR_SHIFT
+#undef DDR_PHY_DX8SL3DQSCTL_DXSR_MASK
 #define DDR_PHY_DX8SL3DQSCTL_DXSR_DEFVAL                       0x01264000
 #define DDR_PHY_DX8SL3DQSCTL_DXSR_SHIFT                        8
 #define DDR_PHY_DX8SL3DQSCTL_DXSR_MASK                         0x00000300U
@@ -20379,9 +20379,9 @@
 /*
 * DQS_N Resistor
 */
-#undef DDR_PHY_DX8SL3DQSCTL_DQSNRES_DEFVAL 
-#undef DDR_PHY_DX8SL3DQSCTL_DQSNRES_SHIFT 
-#undef DDR_PHY_DX8SL3DQSCTL_DQSNRES_MASK 
+#undef DDR_PHY_DX8SL3DQSCTL_DQSNRES_DEFVAL
+#undef DDR_PHY_DX8SL3DQSCTL_DQSNRES_SHIFT
+#undef DDR_PHY_DX8SL3DQSCTL_DQSNRES_MASK
 #define DDR_PHY_DX8SL3DQSCTL_DQSNRES_DEFVAL                    0x01264000
 #define DDR_PHY_DX8SL3DQSCTL_DQSNRES_SHIFT                     4
 #define DDR_PHY_DX8SL3DQSCTL_DQSNRES_MASK                      0x000000F0U
@@ -20389,9 +20389,9 @@
 /*
 * DQS Resistor
 */
-#undef DDR_PHY_DX8SL3DQSCTL_DQSRES_DEFVAL 
-#undef DDR_PHY_DX8SL3DQSCTL_DQSRES_SHIFT 
-#undef DDR_PHY_DX8SL3DQSCTL_DQSRES_MASK 
+#undef DDR_PHY_DX8SL3DQSCTL_DQSRES_DEFVAL
+#undef DDR_PHY_DX8SL3DQSCTL_DQSRES_SHIFT
+#undef DDR_PHY_DX8SL3DQSCTL_DQSRES_MASK
 #define DDR_PHY_DX8SL3DQSCTL_DQSRES_DEFVAL                     0x01264000
 #define DDR_PHY_DX8SL3DQSCTL_DQSRES_SHIFT                      0
 #define DDR_PHY_DX8SL3DQSCTL_DQSRES_MASK                       0x0000000FU
@@ -20399,9 +20399,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_DEFVAL 
-#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_SHIFT 
-#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_MASK 
+#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_DEFVAL
+#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_SHIFT
+#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_MASK
 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_DEFVAL             0x00141800
 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_SHIFT              24
 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_MASK               0xFF000000U
@@ -20409,9 +20409,9 @@
 /*
 * Configurable Read Data Enable
 */
-#undef DDR_PHY_DX8SL3DXCTL2_CRDEN_DEFVAL 
-#undef DDR_PHY_DX8SL3DXCTL2_CRDEN_SHIFT 
-#undef DDR_PHY_DX8SL3DXCTL2_CRDEN_MASK 
+#undef DDR_PHY_DX8SL3DXCTL2_CRDEN_DEFVAL
+#undef DDR_PHY_DX8SL3DXCTL2_CRDEN_SHIFT
+#undef DDR_PHY_DX8SL3DXCTL2_CRDEN_MASK
 #define DDR_PHY_DX8SL3DXCTL2_CRDEN_DEFVAL                      0x00141800
 #define DDR_PHY_DX8SL3DXCTL2_CRDEN_SHIFT                       23
 #define DDR_PHY_DX8SL3DXCTL2_CRDEN_MASK                        0x00800000U
@@ -20419,9 +20419,9 @@
 /*
 * OX Extension during Post-amble
 */
-#undef DDR_PHY_DX8SL3DXCTL2_POSOEX_DEFVAL 
-#undef DDR_PHY_DX8SL3DXCTL2_POSOEX_SHIFT 
-#undef DDR_PHY_DX8SL3DXCTL2_POSOEX_MASK 
+#undef DDR_PHY_DX8SL3DXCTL2_POSOEX_DEFVAL
+#undef DDR_PHY_DX8SL3DXCTL2_POSOEX_SHIFT
+#undef DDR_PHY_DX8SL3DXCTL2_POSOEX_MASK
 #define DDR_PHY_DX8SL3DXCTL2_POSOEX_DEFVAL                     0x00141800
 #define DDR_PHY_DX8SL3DXCTL2_POSOEX_SHIFT                      20
 #define DDR_PHY_DX8SL3DXCTL2_POSOEX_MASK                       0x00700000U
@@ -20429,9 +20429,9 @@
 /*
 * OE Extension during Pre-amble
 */
-#undef DDR_PHY_DX8SL3DXCTL2_PREOEX_DEFVAL 
-#undef DDR_PHY_DX8SL3DXCTL2_PREOEX_SHIFT 
-#undef DDR_PHY_DX8SL3DXCTL2_PREOEX_MASK 
+#undef DDR_PHY_DX8SL3DXCTL2_PREOEX_DEFVAL
+#undef DDR_PHY_DX8SL3DXCTL2_PREOEX_SHIFT
+#undef DDR_PHY_DX8SL3DXCTL2_PREOEX_MASK
 #define DDR_PHY_DX8SL3DXCTL2_PREOEX_DEFVAL                     0x00141800
 #define DDR_PHY_DX8SL3DXCTL2_PREOEX_SHIFT                      18
 #define DDR_PHY_DX8SL3DXCTL2_PREOEX_MASK                       0x000C0000U
@@ -20439,9 +20439,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_17_DEFVAL 
-#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_17_SHIFT 
-#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_17_MASK 
+#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_17_DEFVAL
+#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_17_SHIFT
+#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_17_MASK
 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_17_DEFVAL                0x00141800
 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_17_SHIFT                 17
 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_17_MASK                  0x00020000U
@@ -20449,9 +20449,9 @@
 /*
 * I/O Assisted Gate Select
 */
-#undef DDR_PHY_DX8SL3DXCTL2_IOAG_DEFVAL 
-#undef DDR_PHY_DX8SL3DXCTL2_IOAG_SHIFT 
-#undef DDR_PHY_DX8SL3DXCTL2_IOAG_MASK 
+#undef DDR_PHY_DX8SL3DXCTL2_IOAG_DEFVAL
+#undef DDR_PHY_DX8SL3DXCTL2_IOAG_SHIFT
+#undef DDR_PHY_DX8SL3DXCTL2_IOAG_MASK
 #define DDR_PHY_DX8SL3DXCTL2_IOAG_DEFVAL                       0x00141800
 #define DDR_PHY_DX8SL3DXCTL2_IOAG_SHIFT                        16
 #define DDR_PHY_DX8SL3DXCTL2_IOAG_MASK                         0x00010000U
@@ -20459,9 +20459,9 @@
 /*
 * I/O Loopback Select
 */
-#undef DDR_PHY_DX8SL3DXCTL2_IOLB_DEFVAL 
-#undef DDR_PHY_DX8SL3DXCTL2_IOLB_SHIFT 
-#undef DDR_PHY_DX8SL3DXCTL2_IOLB_MASK 
+#undef DDR_PHY_DX8SL3DXCTL2_IOLB_DEFVAL
+#undef DDR_PHY_DX8SL3DXCTL2_IOLB_SHIFT
+#undef DDR_PHY_DX8SL3DXCTL2_IOLB_MASK
 #define DDR_PHY_DX8SL3DXCTL2_IOLB_DEFVAL                       0x00141800
 #define DDR_PHY_DX8SL3DXCTL2_IOLB_SHIFT                        15
 #define DDR_PHY_DX8SL3DXCTL2_IOLB_MASK                         0x00008000U
@@ -20469,9 +20469,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_DEFVAL 
-#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_SHIFT 
-#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_MASK 
+#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_DEFVAL
+#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_SHIFT
+#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_MASK
 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_DEFVAL             0x00141800
 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_SHIFT              13
 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_MASK               0x00006000U
@@ -20479,9 +20479,9 @@
 /*
 * Low Power Wakeup Threshold
 */
-#undef DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_DEFVAL 
-#undef DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_SHIFT 
-#undef DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_MASK 
+#undef DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_DEFVAL
+#undef DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_SHIFT
+#undef DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_MASK
 #define DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_DEFVAL             0x00141800
 #define DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_SHIFT              9
 #define DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_MASK               0x00001E00U
@@ -20489,9 +20489,9 @@
 /*
 * Read Data Bus Inversion Enable
 */
-#undef DDR_PHY_DX8SL3DXCTL2_RDBI_DEFVAL 
-#undef DDR_PHY_DX8SL3DXCTL2_RDBI_SHIFT 
-#undef DDR_PHY_DX8SL3DXCTL2_RDBI_MASK 
+#undef DDR_PHY_DX8SL3DXCTL2_RDBI_DEFVAL
+#undef DDR_PHY_DX8SL3DXCTL2_RDBI_SHIFT
+#undef DDR_PHY_DX8SL3DXCTL2_RDBI_MASK
 #define DDR_PHY_DX8SL3DXCTL2_RDBI_DEFVAL                       0x00141800
 #define DDR_PHY_DX8SL3DXCTL2_RDBI_SHIFT                        8
 #define DDR_PHY_DX8SL3DXCTL2_RDBI_MASK                         0x00000100U
@@ -20499,9 +20499,9 @@
 /*
 * Write Data Bus Inversion Enable
 */
-#undef DDR_PHY_DX8SL3DXCTL2_WDBI_DEFVAL 
-#undef DDR_PHY_DX8SL3DXCTL2_WDBI_SHIFT 
-#undef DDR_PHY_DX8SL3DXCTL2_WDBI_MASK 
+#undef DDR_PHY_DX8SL3DXCTL2_WDBI_DEFVAL
+#undef DDR_PHY_DX8SL3DXCTL2_WDBI_SHIFT
+#undef DDR_PHY_DX8SL3DXCTL2_WDBI_MASK
 #define DDR_PHY_DX8SL3DXCTL2_WDBI_DEFVAL                       0x00141800
 #define DDR_PHY_DX8SL3DXCTL2_WDBI_SHIFT                        7
 #define DDR_PHY_DX8SL3DXCTL2_WDBI_MASK                         0x00000080U
@@ -20509,9 +20509,9 @@
 /*
 * PUB Read FIFO Bypass
 */
-#undef DDR_PHY_DX8SL3DXCTL2_PRFBYP_DEFVAL 
-#undef DDR_PHY_DX8SL3DXCTL2_PRFBYP_SHIFT 
-#undef DDR_PHY_DX8SL3DXCTL2_PRFBYP_MASK 
+#undef DDR_PHY_DX8SL3DXCTL2_PRFBYP_DEFVAL
+#undef DDR_PHY_DX8SL3DXCTL2_PRFBYP_SHIFT
+#undef DDR_PHY_DX8SL3DXCTL2_PRFBYP_MASK
 #define DDR_PHY_DX8SL3DXCTL2_PRFBYP_DEFVAL                     0x00141800
 #define DDR_PHY_DX8SL3DXCTL2_PRFBYP_SHIFT                      6
 #define DDR_PHY_DX8SL3DXCTL2_PRFBYP_MASK                       0x00000040U
@@ -20519,9 +20519,9 @@
 /*
 * DATX8 Receive FIFO Read Mode
 */
-#undef DDR_PHY_DX8SL3DXCTL2_RDMODE_DEFVAL 
-#undef DDR_PHY_DX8SL3DXCTL2_RDMODE_SHIFT 
-#undef DDR_PHY_DX8SL3DXCTL2_RDMODE_MASK 
+#undef DDR_PHY_DX8SL3DXCTL2_RDMODE_DEFVAL
+#undef DDR_PHY_DX8SL3DXCTL2_RDMODE_SHIFT
+#undef DDR_PHY_DX8SL3DXCTL2_RDMODE_MASK
 #define DDR_PHY_DX8SL3DXCTL2_RDMODE_DEFVAL                     0x00141800
 #define DDR_PHY_DX8SL3DXCTL2_RDMODE_SHIFT                      4
 #define DDR_PHY_DX8SL3DXCTL2_RDMODE_MASK                       0x00000030U
@@ -20529,9 +20529,9 @@
 /*
 * Disables the Read FIFO Reset
 */
-#undef DDR_PHY_DX8SL3DXCTL2_DISRST_DEFVAL 
-#undef DDR_PHY_DX8SL3DXCTL2_DISRST_SHIFT 
-#undef DDR_PHY_DX8SL3DXCTL2_DISRST_MASK 
+#undef DDR_PHY_DX8SL3DXCTL2_DISRST_DEFVAL
+#undef DDR_PHY_DX8SL3DXCTL2_DISRST_SHIFT
+#undef DDR_PHY_DX8SL3DXCTL2_DISRST_MASK
 #define DDR_PHY_DX8SL3DXCTL2_DISRST_DEFVAL                     0x00141800
 #define DDR_PHY_DX8SL3DXCTL2_DISRST_SHIFT                      3
 #define DDR_PHY_DX8SL3DXCTL2_DISRST_MASK                       0x00000008U
@@ -20539,9 +20539,9 @@
 /*
 * Read DQS Gate I/O Loopback
 */
-#undef DDR_PHY_DX8SL3DXCTL2_DQSGLB_DEFVAL 
-#undef DDR_PHY_DX8SL3DXCTL2_DQSGLB_SHIFT 
-#undef DDR_PHY_DX8SL3DXCTL2_DQSGLB_MASK 
+#undef DDR_PHY_DX8SL3DXCTL2_DQSGLB_DEFVAL
+#undef DDR_PHY_DX8SL3DXCTL2_DQSGLB_SHIFT
+#undef DDR_PHY_DX8SL3DXCTL2_DQSGLB_MASK
 #define DDR_PHY_DX8SL3DXCTL2_DQSGLB_DEFVAL                     0x00141800
 #define DDR_PHY_DX8SL3DXCTL2_DQSGLB_SHIFT                      1
 #define DDR_PHY_DX8SL3DXCTL2_DQSGLB_MASK                       0x00000006U
@@ -20549,9 +20549,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_0_DEFVAL 
-#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_0_SHIFT 
-#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_0_MASK 
+#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_0_DEFVAL
+#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_0_SHIFT
+#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_0_MASK
 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_0_DEFVAL                 0x00141800
 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_0_SHIFT                  0
 #define DDR_PHY_DX8SL3DXCTL2_RESERVED_0_MASK                   0x00000001U
@@ -20559,9 +20559,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SL3IOCR_RESERVED_31_DEFVAL 
-#undef DDR_PHY_DX8SL3IOCR_RESERVED_31_SHIFT 
-#undef DDR_PHY_DX8SL3IOCR_RESERVED_31_MASK 
+#undef DDR_PHY_DX8SL3IOCR_RESERVED_31_DEFVAL
+#undef DDR_PHY_DX8SL3IOCR_RESERVED_31_SHIFT
+#undef DDR_PHY_DX8SL3IOCR_RESERVED_31_MASK
 #define DDR_PHY_DX8SL3IOCR_RESERVED_31_DEFVAL                  0x00000000
 #define DDR_PHY_DX8SL3IOCR_RESERVED_31_SHIFT                   31
 #define DDR_PHY_DX8SL3IOCR_RESERVED_31_MASK                    0x80000000U
@@ -20569,9 +20569,9 @@
 /*
 * PVREF_DAC REFSEL range select
 */
-#undef DDR_PHY_DX8SL3IOCR_DXDACRANGE_DEFVAL 
-#undef DDR_PHY_DX8SL3IOCR_DXDACRANGE_SHIFT 
-#undef DDR_PHY_DX8SL3IOCR_DXDACRANGE_MASK 
+#undef DDR_PHY_DX8SL3IOCR_DXDACRANGE_DEFVAL
+#undef DDR_PHY_DX8SL3IOCR_DXDACRANGE_SHIFT
+#undef DDR_PHY_DX8SL3IOCR_DXDACRANGE_MASK
 #define DDR_PHY_DX8SL3IOCR_DXDACRANGE_DEFVAL                   0x00000000
 #define DDR_PHY_DX8SL3IOCR_DXDACRANGE_SHIFT                    28
 #define DDR_PHY_DX8SL3IOCR_DXDACRANGE_MASK                     0x70000000U
@@ -20579,9 +20579,9 @@
 /*
 * IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
 */
-#undef DDR_PHY_DX8SL3IOCR_DXVREFIOM_DEFVAL 
-#undef DDR_PHY_DX8SL3IOCR_DXVREFIOM_SHIFT 
-#undef DDR_PHY_DX8SL3IOCR_DXVREFIOM_MASK 
+#undef DDR_PHY_DX8SL3IOCR_DXVREFIOM_DEFVAL
+#undef DDR_PHY_DX8SL3IOCR_DXVREFIOM_SHIFT
+#undef DDR_PHY_DX8SL3IOCR_DXVREFIOM_MASK
 #define DDR_PHY_DX8SL3IOCR_DXVREFIOM_DEFVAL                    0x00000000
 #define DDR_PHY_DX8SL3IOCR_DXVREFIOM_SHIFT                     25
 #define DDR_PHY_DX8SL3IOCR_DXVREFIOM_MASK                      0x0E000000U
@@ -20589,9 +20589,9 @@
 /*
 * DX IO Mode
 */
-#undef DDR_PHY_DX8SL3IOCR_DXIOM_DEFVAL 
-#undef DDR_PHY_DX8SL3IOCR_DXIOM_SHIFT 
-#undef DDR_PHY_DX8SL3IOCR_DXIOM_MASK 
+#undef DDR_PHY_DX8SL3IOCR_DXIOM_DEFVAL
+#undef DDR_PHY_DX8SL3IOCR_DXIOM_SHIFT
+#undef DDR_PHY_DX8SL3IOCR_DXIOM_MASK
 #define DDR_PHY_DX8SL3IOCR_DXIOM_DEFVAL                        0x00000000
 #define DDR_PHY_DX8SL3IOCR_DXIOM_SHIFT                         22
 #define DDR_PHY_DX8SL3IOCR_DXIOM_MASK                          0x01C00000U
@@ -20599,9 +20599,9 @@
 /*
 * DX IO Transmitter Mode
 */
-#undef DDR_PHY_DX8SL3IOCR_DXTXM_DEFVAL 
-#undef DDR_PHY_DX8SL3IOCR_DXTXM_SHIFT 
-#undef DDR_PHY_DX8SL3IOCR_DXTXM_MASK 
+#undef DDR_PHY_DX8SL3IOCR_DXTXM_DEFVAL
+#undef DDR_PHY_DX8SL3IOCR_DXTXM_SHIFT
+#undef DDR_PHY_DX8SL3IOCR_DXTXM_MASK
 #define DDR_PHY_DX8SL3IOCR_DXTXM_DEFVAL                        0x00000000
 #define DDR_PHY_DX8SL3IOCR_DXTXM_SHIFT                         11
 #define DDR_PHY_DX8SL3IOCR_DXTXM_MASK                          0x003FF800U
@@ -20609,9 +20609,9 @@
 /*
 * DX IO Receiver Mode
 */
-#undef DDR_PHY_DX8SL3IOCR_DXRXM_DEFVAL 
-#undef DDR_PHY_DX8SL3IOCR_DXRXM_SHIFT 
-#undef DDR_PHY_DX8SL3IOCR_DXRXM_MASK 
+#undef DDR_PHY_DX8SL3IOCR_DXRXM_DEFVAL
+#undef DDR_PHY_DX8SL3IOCR_DXRXM_SHIFT
+#undef DDR_PHY_DX8SL3IOCR_DXRXM_MASK
 #define DDR_PHY_DX8SL3IOCR_DXRXM_DEFVAL                        0x00000000
 #define DDR_PHY_DX8SL3IOCR_DXRXM_SHIFT                         0
 #define DDR_PHY_DX8SL3IOCR_DXRXM_MASK                          0x000007FFU
@@ -20619,9 +20619,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SL4OSC_RESERVED_31_30_DEFVAL 
-#undef DDR_PHY_DX8SL4OSC_RESERVED_31_30_SHIFT 
-#undef DDR_PHY_DX8SL4OSC_RESERVED_31_30_MASK 
+#undef DDR_PHY_DX8SL4OSC_RESERVED_31_30_DEFVAL
+#undef DDR_PHY_DX8SL4OSC_RESERVED_31_30_SHIFT
+#undef DDR_PHY_DX8SL4OSC_RESERVED_31_30_MASK
 #define DDR_PHY_DX8SL4OSC_RESERVED_31_30_DEFVAL                0x00019FFE
 #define DDR_PHY_DX8SL4OSC_RESERVED_31_30_SHIFT                 30
 #define DDR_PHY_DX8SL4OSC_RESERVED_31_30_MASK                  0xC0000000U
@@ -20629,9 +20629,9 @@
 /*
 * Enable Clock Gating for DX ddr_clk
 */
-#undef DDR_PHY_DX8SL4OSC_GATEDXRDCLK_DEFVAL 
-#undef DDR_PHY_DX8SL4OSC_GATEDXRDCLK_SHIFT 
-#undef DDR_PHY_DX8SL4OSC_GATEDXRDCLK_MASK 
+#undef DDR_PHY_DX8SL4OSC_GATEDXRDCLK_DEFVAL
+#undef DDR_PHY_DX8SL4OSC_GATEDXRDCLK_SHIFT
+#undef DDR_PHY_DX8SL4OSC_GATEDXRDCLK_MASK
 #define DDR_PHY_DX8SL4OSC_GATEDXRDCLK_DEFVAL                   0x00019FFE
 #define DDR_PHY_DX8SL4OSC_GATEDXRDCLK_SHIFT                    28
 #define DDR_PHY_DX8SL4OSC_GATEDXRDCLK_MASK                     0x30000000U
@@ -20639,9 +20639,9 @@
 /*
 * Enable Clock Gating for DX ctl_rd_clk
 */
-#undef DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_DEFVAL 
-#undef DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_SHIFT 
-#undef DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_MASK 
+#undef DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_DEFVAL
+#undef DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_SHIFT
+#undef DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_MASK
 #define DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_DEFVAL                  0x00019FFE
 #define DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_SHIFT                   26
 #define DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_MASK                    0x0C000000U
@@ -20649,9 +20649,9 @@
 /*
 * Enable Clock Gating for DX ctl_clk
 */
-#undef DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_DEFVAL 
-#undef DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_SHIFT 
-#undef DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_MASK 
+#undef DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_DEFVAL
+#undef DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_SHIFT
+#undef DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_MASK
 #define DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_DEFVAL                  0x00019FFE
 #define DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_SHIFT                   24
 #define DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_MASK                    0x03000000U
@@ -20660,9 +20660,9 @@
 * Selects the level to which clocks will be stalled when clock gating is e
     * nabled.
 */
-#undef DDR_PHY_DX8SL4OSC_CLKLEVEL_DEFVAL 
-#undef DDR_PHY_DX8SL4OSC_CLKLEVEL_SHIFT 
-#undef DDR_PHY_DX8SL4OSC_CLKLEVEL_MASK 
+#undef DDR_PHY_DX8SL4OSC_CLKLEVEL_DEFVAL
+#undef DDR_PHY_DX8SL4OSC_CLKLEVEL_SHIFT
+#undef DDR_PHY_DX8SL4OSC_CLKLEVEL_MASK
 #define DDR_PHY_DX8SL4OSC_CLKLEVEL_DEFVAL                      0x00019FFE
 #define DDR_PHY_DX8SL4OSC_CLKLEVEL_SHIFT                       22
 #define DDR_PHY_DX8SL4OSC_CLKLEVEL_MASK                        0x00C00000U
@@ -20670,9 +20670,9 @@
 /*
 * Loopback Mode
 */
-#undef DDR_PHY_DX8SL4OSC_LBMODE_DEFVAL 
-#undef DDR_PHY_DX8SL4OSC_LBMODE_SHIFT 
-#undef DDR_PHY_DX8SL4OSC_LBMODE_MASK 
+#undef DDR_PHY_DX8SL4OSC_LBMODE_DEFVAL
+#undef DDR_PHY_DX8SL4OSC_LBMODE_SHIFT
+#undef DDR_PHY_DX8SL4OSC_LBMODE_MASK
 #define DDR_PHY_DX8SL4OSC_LBMODE_DEFVAL                        0x00019FFE
 #define DDR_PHY_DX8SL4OSC_LBMODE_SHIFT                         21
 #define DDR_PHY_DX8SL4OSC_LBMODE_MASK                          0x00200000U
@@ -20680,9 +20680,9 @@
 /*
 * Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
 */
-#undef DDR_PHY_DX8SL4OSC_LBGSDQS_DEFVAL 
-#undef DDR_PHY_DX8SL4OSC_LBGSDQS_SHIFT 
-#undef DDR_PHY_DX8SL4OSC_LBGSDQS_MASK 
+#undef DDR_PHY_DX8SL4OSC_LBGSDQS_DEFVAL
+#undef DDR_PHY_DX8SL4OSC_LBGSDQS_SHIFT
+#undef DDR_PHY_DX8SL4OSC_LBGSDQS_MASK
 #define DDR_PHY_DX8SL4OSC_LBGSDQS_DEFVAL                       0x00019FFE
 #define DDR_PHY_DX8SL4OSC_LBGSDQS_SHIFT                        20
 #define DDR_PHY_DX8SL4OSC_LBGSDQS_MASK                         0x00100000U
@@ -20690,9 +20690,9 @@
 /*
 * Loopback DQS Gating
 */
-#undef DDR_PHY_DX8SL4OSC_LBGDQS_DEFVAL 
-#undef DDR_PHY_DX8SL4OSC_LBGDQS_SHIFT 
-#undef DDR_PHY_DX8SL4OSC_LBGDQS_MASK 
+#undef DDR_PHY_DX8SL4OSC_LBGDQS_DEFVAL
+#undef DDR_PHY_DX8SL4OSC_LBGDQS_SHIFT
+#undef DDR_PHY_DX8SL4OSC_LBGDQS_MASK
 #define DDR_PHY_DX8SL4OSC_LBGDQS_DEFVAL                        0x00019FFE
 #define DDR_PHY_DX8SL4OSC_LBGDQS_SHIFT                         18
 #define DDR_PHY_DX8SL4OSC_LBGDQS_MASK                          0x000C0000U
@@ -20700,9 +20700,9 @@
 /*
 * Loopback DQS Shift
 */
-#undef DDR_PHY_DX8SL4OSC_LBDQSS_DEFVAL 
-#undef DDR_PHY_DX8SL4OSC_LBDQSS_SHIFT 
-#undef DDR_PHY_DX8SL4OSC_LBDQSS_MASK 
+#undef DDR_PHY_DX8SL4OSC_LBDQSS_DEFVAL
+#undef DDR_PHY_DX8SL4OSC_LBDQSS_SHIFT
+#undef DDR_PHY_DX8SL4OSC_LBDQSS_MASK
 #define DDR_PHY_DX8SL4OSC_LBDQSS_DEFVAL                        0x00019FFE
 #define DDR_PHY_DX8SL4OSC_LBDQSS_SHIFT                         17
 #define DDR_PHY_DX8SL4OSC_LBDQSS_MASK                          0x00020000U
@@ -20710,9 +20710,9 @@
 /*
 * PHY High-Speed Reset
 */
-#undef DDR_PHY_DX8SL4OSC_PHYHRST_DEFVAL 
-#undef DDR_PHY_DX8SL4OSC_PHYHRST_SHIFT 
-#undef DDR_PHY_DX8SL4OSC_PHYHRST_MASK 
+#undef DDR_PHY_DX8SL4OSC_PHYHRST_DEFVAL
+#undef DDR_PHY_DX8SL4OSC_PHYHRST_SHIFT
+#undef DDR_PHY_DX8SL4OSC_PHYHRST_MASK
 #define DDR_PHY_DX8SL4OSC_PHYHRST_DEFVAL                       0x00019FFE
 #define DDR_PHY_DX8SL4OSC_PHYHRST_SHIFT                        16
 #define DDR_PHY_DX8SL4OSC_PHYHRST_MASK                         0x00010000U
@@ -20720,9 +20720,9 @@
 /*
 * PHY FIFO Reset
 */
-#undef DDR_PHY_DX8SL4OSC_PHYFRST_DEFVAL 
-#undef DDR_PHY_DX8SL4OSC_PHYFRST_SHIFT 
-#undef DDR_PHY_DX8SL4OSC_PHYFRST_MASK 
+#undef DDR_PHY_DX8SL4OSC_PHYFRST_DEFVAL
+#undef DDR_PHY_DX8SL4OSC_PHYFRST_SHIFT
+#undef DDR_PHY_DX8SL4OSC_PHYFRST_MASK
 #define DDR_PHY_DX8SL4OSC_PHYFRST_DEFVAL                       0x00019FFE
 #define DDR_PHY_DX8SL4OSC_PHYFRST_SHIFT                        15
 #define DDR_PHY_DX8SL4OSC_PHYFRST_MASK                         0x00008000U
@@ -20730,9 +20730,9 @@
 /*
 * Delay Line Test Start
 */
-#undef DDR_PHY_DX8SL4OSC_DLTST_DEFVAL 
-#undef DDR_PHY_DX8SL4OSC_DLTST_SHIFT 
-#undef DDR_PHY_DX8SL4OSC_DLTST_MASK 
+#undef DDR_PHY_DX8SL4OSC_DLTST_DEFVAL
+#undef DDR_PHY_DX8SL4OSC_DLTST_SHIFT
+#undef DDR_PHY_DX8SL4OSC_DLTST_MASK
 #define DDR_PHY_DX8SL4OSC_DLTST_DEFVAL                         0x00019FFE
 #define DDR_PHY_DX8SL4OSC_DLTST_SHIFT                          14
 #define DDR_PHY_DX8SL4OSC_DLTST_MASK                           0x00004000U
@@ -20740,9 +20740,9 @@
 /*
 * Delay Line Test Mode
 */
-#undef DDR_PHY_DX8SL4OSC_DLTMODE_DEFVAL 
-#undef DDR_PHY_DX8SL4OSC_DLTMODE_SHIFT 
-#undef DDR_PHY_DX8SL4OSC_DLTMODE_MASK 
+#undef DDR_PHY_DX8SL4OSC_DLTMODE_DEFVAL
+#undef DDR_PHY_DX8SL4OSC_DLTMODE_SHIFT
+#undef DDR_PHY_DX8SL4OSC_DLTMODE_MASK
 #define DDR_PHY_DX8SL4OSC_DLTMODE_DEFVAL                       0x00019FFE
 #define DDR_PHY_DX8SL4OSC_DLTMODE_SHIFT                        13
 #define DDR_PHY_DX8SL4OSC_DLTMODE_MASK                         0x00002000U
@@ -20750,9 +20750,9 @@
 /*
 * Reserved. Caution, do not write to this register field.
 */
-#undef DDR_PHY_DX8SL4OSC_RESERVED_12_11_DEFVAL 
-#undef DDR_PHY_DX8SL4OSC_RESERVED_12_11_SHIFT 
-#undef DDR_PHY_DX8SL4OSC_RESERVED_12_11_MASK 
+#undef DDR_PHY_DX8SL4OSC_RESERVED_12_11_DEFVAL
+#undef DDR_PHY_DX8SL4OSC_RESERVED_12_11_SHIFT
+#undef DDR_PHY_DX8SL4OSC_RESERVED_12_11_MASK
 #define DDR_PHY_DX8SL4OSC_RESERVED_12_11_DEFVAL                0x00019FFE
 #define DDR_PHY_DX8SL4OSC_RESERVED_12_11_SHIFT                 11
 #define DDR_PHY_DX8SL4OSC_RESERVED_12_11_MASK                  0x00001800U
@@ -20760,9 +20760,9 @@
 /*
 * Oscillator Mode Write-Data Delay Line Select
 */
-#undef DDR_PHY_DX8SL4OSC_OSCWDDL_DEFVAL 
-#undef DDR_PHY_DX8SL4OSC_OSCWDDL_SHIFT 
-#undef DDR_PHY_DX8SL4OSC_OSCWDDL_MASK 
+#undef DDR_PHY_DX8SL4OSC_OSCWDDL_DEFVAL
+#undef DDR_PHY_DX8SL4OSC_OSCWDDL_SHIFT
+#undef DDR_PHY_DX8SL4OSC_OSCWDDL_MASK
 #define DDR_PHY_DX8SL4OSC_OSCWDDL_DEFVAL                       0x00019FFE
 #define DDR_PHY_DX8SL4OSC_OSCWDDL_SHIFT                        9
 #define DDR_PHY_DX8SL4OSC_OSCWDDL_MASK                         0x00000600U
@@ -20770,9 +20770,9 @@
 /*
 * Reserved. Caution, do not write to this register field.
 */
-#undef DDR_PHY_DX8SL4OSC_RESERVED_8_7_DEFVAL 
-#undef DDR_PHY_DX8SL4OSC_RESERVED_8_7_SHIFT 
-#undef DDR_PHY_DX8SL4OSC_RESERVED_8_7_MASK 
+#undef DDR_PHY_DX8SL4OSC_RESERVED_8_7_DEFVAL
+#undef DDR_PHY_DX8SL4OSC_RESERVED_8_7_SHIFT
+#undef DDR_PHY_DX8SL4OSC_RESERVED_8_7_MASK
 #define DDR_PHY_DX8SL4OSC_RESERVED_8_7_DEFVAL                  0x00019FFE
 #define DDR_PHY_DX8SL4OSC_RESERVED_8_7_SHIFT                   7
 #define DDR_PHY_DX8SL4OSC_RESERVED_8_7_MASK                    0x00000180U
@@ -20780,9 +20780,9 @@
 /*
 * Oscillator Mode Write-Leveling Delay Line Select
 */
-#undef DDR_PHY_DX8SL4OSC_OSCWDL_DEFVAL 
-#undef DDR_PHY_DX8SL4OSC_OSCWDL_SHIFT 
-#undef DDR_PHY_DX8SL4OSC_OSCWDL_MASK 
+#undef DDR_PHY_DX8SL4OSC_OSCWDL_DEFVAL
+#undef DDR_PHY_DX8SL4OSC_OSCWDL_SHIFT
+#undef DDR_PHY_DX8SL4OSC_OSCWDL_MASK
 #define DDR_PHY_DX8SL4OSC_OSCWDL_DEFVAL                        0x00019FFE
 #define DDR_PHY_DX8SL4OSC_OSCWDL_SHIFT                         5
 #define DDR_PHY_DX8SL4OSC_OSCWDL_MASK                          0x00000060U
@@ -20790,9 +20790,9 @@
 /*
 * Oscillator Mode Division
 */
-#undef DDR_PHY_DX8SL4OSC_OSCDIV_DEFVAL 
-#undef DDR_PHY_DX8SL4OSC_OSCDIV_SHIFT 
-#undef DDR_PHY_DX8SL4OSC_OSCDIV_MASK 
+#undef DDR_PHY_DX8SL4OSC_OSCDIV_DEFVAL
+#undef DDR_PHY_DX8SL4OSC_OSCDIV_SHIFT
+#undef DDR_PHY_DX8SL4OSC_OSCDIV_MASK
 #define DDR_PHY_DX8SL4OSC_OSCDIV_DEFVAL                        0x00019FFE
 #define DDR_PHY_DX8SL4OSC_OSCDIV_SHIFT                         1
 #define DDR_PHY_DX8SL4OSC_OSCDIV_MASK                          0x0000001EU
@@ -20800,9 +20800,9 @@
 /*
 * Oscillator Enable
 */
-#undef DDR_PHY_DX8SL4OSC_OSCEN_DEFVAL 
-#undef DDR_PHY_DX8SL4OSC_OSCEN_SHIFT 
-#undef DDR_PHY_DX8SL4OSC_OSCEN_MASK 
+#undef DDR_PHY_DX8SL4OSC_OSCEN_DEFVAL
+#undef DDR_PHY_DX8SL4OSC_OSCEN_SHIFT
+#undef DDR_PHY_DX8SL4OSC_OSCEN_MASK
 #define DDR_PHY_DX8SL4OSC_OSCEN_DEFVAL                         0x00019FFE
 #define DDR_PHY_DX8SL4OSC_OSCEN_SHIFT                          0
 #define DDR_PHY_DX8SL4OSC_OSCEN_MASK                           0x00000001U
@@ -20810,9 +20810,9 @@
 /*
 * PLL Bypass
 */
-#undef DDR_PHY_DX8SL4PLLCR0_PLLBYP_DEFVAL 
-#undef DDR_PHY_DX8SL4PLLCR0_PLLBYP_SHIFT 
-#undef DDR_PHY_DX8SL4PLLCR0_PLLBYP_MASK 
+#undef DDR_PHY_DX8SL4PLLCR0_PLLBYP_DEFVAL
+#undef DDR_PHY_DX8SL4PLLCR0_PLLBYP_SHIFT
+#undef DDR_PHY_DX8SL4PLLCR0_PLLBYP_MASK
 #define DDR_PHY_DX8SL4PLLCR0_PLLBYP_DEFVAL                     0x001C0000
 #define DDR_PHY_DX8SL4PLLCR0_PLLBYP_SHIFT                      31
 #define DDR_PHY_DX8SL4PLLCR0_PLLBYP_MASK                       0x80000000U
@@ -20820,9 +20820,9 @@
 /*
 * PLL Reset
 */
-#undef DDR_PHY_DX8SL4PLLCR0_PLLRST_DEFVAL 
-#undef DDR_PHY_DX8SL4PLLCR0_PLLRST_SHIFT 
-#undef DDR_PHY_DX8SL4PLLCR0_PLLRST_MASK 
+#undef DDR_PHY_DX8SL4PLLCR0_PLLRST_DEFVAL
+#undef DDR_PHY_DX8SL4PLLCR0_PLLRST_SHIFT
+#undef DDR_PHY_DX8SL4PLLCR0_PLLRST_MASK
 #define DDR_PHY_DX8SL4PLLCR0_PLLRST_DEFVAL                     0x001C0000
 #define DDR_PHY_DX8SL4PLLCR0_PLLRST_SHIFT                      30
 #define DDR_PHY_DX8SL4PLLCR0_PLLRST_MASK                       0x40000000U
@@ -20830,9 +20830,9 @@
 /*
 * PLL Power Down
 */
-#undef DDR_PHY_DX8SL4PLLCR0_PLLPD_DEFVAL 
-#undef DDR_PHY_DX8SL4PLLCR0_PLLPD_SHIFT 
-#undef DDR_PHY_DX8SL4PLLCR0_PLLPD_MASK 
+#undef DDR_PHY_DX8SL4PLLCR0_PLLPD_DEFVAL
+#undef DDR_PHY_DX8SL4PLLCR0_PLLPD_SHIFT
+#undef DDR_PHY_DX8SL4PLLCR0_PLLPD_MASK
 #define DDR_PHY_DX8SL4PLLCR0_PLLPD_DEFVAL                      0x001C0000
 #define DDR_PHY_DX8SL4PLLCR0_PLLPD_SHIFT                       29
 #define DDR_PHY_DX8SL4PLLCR0_PLLPD_MASK                        0x20000000U
@@ -20840,9 +20840,9 @@
 /*
 * Reference Stop Mode
 */
-#undef DDR_PHY_DX8SL4PLLCR0_RSTOPM_DEFVAL 
-#undef DDR_PHY_DX8SL4PLLCR0_RSTOPM_SHIFT 
-#undef DDR_PHY_DX8SL4PLLCR0_RSTOPM_MASK 
+#undef DDR_PHY_DX8SL4PLLCR0_RSTOPM_DEFVAL
+#undef DDR_PHY_DX8SL4PLLCR0_RSTOPM_SHIFT
+#undef DDR_PHY_DX8SL4PLLCR0_RSTOPM_MASK
 #define DDR_PHY_DX8SL4PLLCR0_RSTOPM_DEFVAL                     0x001C0000
 #define DDR_PHY_DX8SL4PLLCR0_RSTOPM_SHIFT                      28
 #define DDR_PHY_DX8SL4PLLCR0_RSTOPM_MASK                       0x10000000U
@@ -20850,9 +20850,9 @@
 /*
 * PLL Frequency Select
 */
-#undef DDR_PHY_DX8SL4PLLCR0_FRQSEL_DEFVAL 
-#undef DDR_PHY_DX8SL4PLLCR0_FRQSEL_SHIFT 
-#undef DDR_PHY_DX8SL4PLLCR0_FRQSEL_MASK 
+#undef DDR_PHY_DX8SL4PLLCR0_FRQSEL_DEFVAL
+#undef DDR_PHY_DX8SL4PLLCR0_FRQSEL_SHIFT
+#undef DDR_PHY_DX8SL4PLLCR0_FRQSEL_MASK
 #define DDR_PHY_DX8SL4PLLCR0_FRQSEL_DEFVAL                     0x001C0000
 #define DDR_PHY_DX8SL4PLLCR0_FRQSEL_SHIFT                      24
 #define DDR_PHY_DX8SL4PLLCR0_FRQSEL_MASK                       0x0F000000U
@@ -20860,9 +20860,9 @@
 /*
 * Relock Mode
 */
-#undef DDR_PHY_DX8SL4PLLCR0_RLOCKM_DEFVAL 
-#undef DDR_PHY_DX8SL4PLLCR0_RLOCKM_SHIFT 
-#undef DDR_PHY_DX8SL4PLLCR0_RLOCKM_MASK 
+#undef DDR_PHY_DX8SL4PLLCR0_RLOCKM_DEFVAL
+#undef DDR_PHY_DX8SL4PLLCR0_RLOCKM_SHIFT
+#undef DDR_PHY_DX8SL4PLLCR0_RLOCKM_MASK
 #define DDR_PHY_DX8SL4PLLCR0_RLOCKM_DEFVAL                     0x001C0000
 #define DDR_PHY_DX8SL4PLLCR0_RLOCKM_SHIFT                      23
 #define DDR_PHY_DX8SL4PLLCR0_RLOCKM_MASK                       0x00800000U
@@ -20870,9 +20870,9 @@
 /*
 * Charge Pump Proportional Current Control
 */
-#undef DDR_PHY_DX8SL4PLLCR0_CPPC_DEFVAL 
-#undef DDR_PHY_DX8SL4PLLCR0_CPPC_SHIFT 
-#undef DDR_PHY_DX8SL4PLLCR0_CPPC_MASK 
+#undef DDR_PHY_DX8SL4PLLCR0_CPPC_DEFVAL
+#undef DDR_PHY_DX8SL4PLLCR0_CPPC_SHIFT
+#undef DDR_PHY_DX8SL4PLLCR0_CPPC_MASK
 #define DDR_PHY_DX8SL4PLLCR0_CPPC_DEFVAL                       0x001C0000
 #define DDR_PHY_DX8SL4PLLCR0_CPPC_SHIFT                        17
 #define DDR_PHY_DX8SL4PLLCR0_CPPC_MASK                         0x007E0000U
@@ -20880,9 +20880,9 @@
 /*
 * Charge Pump Integrating Current Control
 */
-#undef DDR_PHY_DX8SL4PLLCR0_CPIC_DEFVAL 
-#undef DDR_PHY_DX8SL4PLLCR0_CPIC_SHIFT 
-#undef DDR_PHY_DX8SL4PLLCR0_CPIC_MASK 
+#undef DDR_PHY_DX8SL4PLLCR0_CPIC_DEFVAL
+#undef DDR_PHY_DX8SL4PLLCR0_CPIC_SHIFT
+#undef DDR_PHY_DX8SL4PLLCR0_CPIC_MASK
 #define DDR_PHY_DX8SL4PLLCR0_CPIC_DEFVAL                       0x001C0000
 #define DDR_PHY_DX8SL4PLLCR0_CPIC_SHIFT                        13
 #define DDR_PHY_DX8SL4PLLCR0_CPIC_MASK                         0x0001E000U
@@ -20890,9 +20890,9 @@
 /*
 * Gear Shift
 */
-#undef DDR_PHY_DX8SL4PLLCR0_GSHIFT_DEFVAL 
-#undef DDR_PHY_DX8SL4PLLCR0_GSHIFT_SHIFT 
-#undef DDR_PHY_DX8SL4PLLCR0_GSHIFT_MASK 
+#undef DDR_PHY_DX8SL4PLLCR0_GSHIFT_DEFVAL
+#undef DDR_PHY_DX8SL4PLLCR0_GSHIFT_SHIFT
+#undef DDR_PHY_DX8SL4PLLCR0_GSHIFT_MASK
 #define DDR_PHY_DX8SL4PLLCR0_GSHIFT_DEFVAL                     0x001C0000
 #define DDR_PHY_DX8SL4PLLCR0_GSHIFT_SHIFT                      12
 #define DDR_PHY_DX8SL4PLLCR0_GSHIFT_MASK                       0x00001000U
@@ -20900,9 +20900,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9_DEFVAL 
-#undef DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9_SHIFT 
-#undef DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9_MASK 
+#undef DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9_DEFVAL
+#undef DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9_SHIFT
+#undef DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9_MASK
 #define DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9_DEFVAL              0x001C0000
 #define DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9_SHIFT               9
 #define DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9_MASK                0x00000E00U
@@ -20910,9 +20910,9 @@
 /*
 * Analog Test Enable (ATOEN)
 */
-#undef DDR_PHY_DX8SL4PLLCR0_ATOEN_DEFVAL 
-#undef DDR_PHY_DX8SL4PLLCR0_ATOEN_SHIFT 
-#undef DDR_PHY_DX8SL4PLLCR0_ATOEN_MASK 
+#undef DDR_PHY_DX8SL4PLLCR0_ATOEN_DEFVAL
+#undef DDR_PHY_DX8SL4PLLCR0_ATOEN_SHIFT
+#undef DDR_PHY_DX8SL4PLLCR0_ATOEN_MASK
 #define DDR_PHY_DX8SL4PLLCR0_ATOEN_DEFVAL                      0x001C0000
 #define DDR_PHY_DX8SL4PLLCR0_ATOEN_SHIFT                       8
 #define DDR_PHY_DX8SL4PLLCR0_ATOEN_MASK                        0x00000100U
@@ -20920,9 +20920,9 @@
 /*
 * Analog Test Control
 */
-#undef DDR_PHY_DX8SL4PLLCR0_ATC_DEFVAL 
-#undef DDR_PHY_DX8SL4PLLCR0_ATC_SHIFT 
-#undef DDR_PHY_DX8SL4PLLCR0_ATC_MASK 
+#undef DDR_PHY_DX8SL4PLLCR0_ATC_DEFVAL
+#undef DDR_PHY_DX8SL4PLLCR0_ATC_SHIFT
+#undef DDR_PHY_DX8SL4PLLCR0_ATC_MASK
 #define DDR_PHY_DX8SL4PLLCR0_ATC_DEFVAL                        0x001C0000
 #define DDR_PHY_DX8SL4PLLCR0_ATC_SHIFT                         4
 #define DDR_PHY_DX8SL4PLLCR0_ATC_MASK                          0x000000F0U
@@ -20930,9 +20930,9 @@
 /*
 * Digital Test Control
 */
-#undef DDR_PHY_DX8SL4PLLCR0_DTC_DEFVAL 
-#undef DDR_PHY_DX8SL4PLLCR0_DTC_SHIFT 
-#undef DDR_PHY_DX8SL4PLLCR0_DTC_MASK 
+#undef DDR_PHY_DX8SL4PLLCR0_DTC_DEFVAL
+#undef DDR_PHY_DX8SL4PLLCR0_DTC_SHIFT
+#undef DDR_PHY_DX8SL4PLLCR0_DTC_MASK
 #define DDR_PHY_DX8SL4PLLCR0_DTC_DEFVAL                        0x001C0000
 #define DDR_PHY_DX8SL4PLLCR0_DTC_SHIFT                         0
 #define DDR_PHY_DX8SL4PLLCR0_DTC_MASK                          0x0000000FU
@@ -20940,9 +20940,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_DEFVAL 
-#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_SHIFT 
-#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_MASK 
+#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_DEFVAL
+#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_SHIFT
+#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_MASK
 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_DEFVAL             0x01264000
 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_SHIFT              25
 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_MASK               0xFE000000U
@@ -20950,9 +20950,9 @@
 /*
 * Read Path Rise-to-Rise Mode
 */
-#undef DDR_PHY_DX8SL4DQSCTL_RRRMODE_DEFVAL 
-#undef DDR_PHY_DX8SL4DQSCTL_RRRMODE_SHIFT 
-#undef DDR_PHY_DX8SL4DQSCTL_RRRMODE_MASK 
+#undef DDR_PHY_DX8SL4DQSCTL_RRRMODE_DEFVAL
+#undef DDR_PHY_DX8SL4DQSCTL_RRRMODE_SHIFT
+#undef DDR_PHY_DX8SL4DQSCTL_RRRMODE_MASK
 #define DDR_PHY_DX8SL4DQSCTL_RRRMODE_DEFVAL                    0x01264000
 #define DDR_PHY_DX8SL4DQSCTL_RRRMODE_SHIFT                     24
 #define DDR_PHY_DX8SL4DQSCTL_RRRMODE_MASK                      0x01000000U
@@ -20960,9 +20960,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_DEFVAL 
-#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_SHIFT 
-#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_MASK 
+#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_DEFVAL
+#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_SHIFT
+#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_MASK
 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_DEFVAL             0x01264000
 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_SHIFT              22
 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_MASK               0x00C00000U
@@ -20970,9 +20970,9 @@
 /*
 * Write Path Rise-to-Rise Mode
 */
-#undef DDR_PHY_DX8SL4DQSCTL_WRRMODE_DEFVAL 
-#undef DDR_PHY_DX8SL4DQSCTL_WRRMODE_SHIFT 
-#undef DDR_PHY_DX8SL4DQSCTL_WRRMODE_MASK 
+#undef DDR_PHY_DX8SL4DQSCTL_WRRMODE_DEFVAL
+#undef DDR_PHY_DX8SL4DQSCTL_WRRMODE_SHIFT
+#undef DDR_PHY_DX8SL4DQSCTL_WRRMODE_MASK
 #define DDR_PHY_DX8SL4DQSCTL_WRRMODE_DEFVAL                    0x01264000
 #define DDR_PHY_DX8SL4DQSCTL_WRRMODE_SHIFT                     21
 #define DDR_PHY_DX8SL4DQSCTL_WRRMODE_MASK                      0x00200000U
@@ -20980,9 +20980,9 @@
 /*
 * DQS Gate Extension
 */
-#undef DDR_PHY_DX8SL4DQSCTL_DQSGX_DEFVAL 
-#undef DDR_PHY_DX8SL4DQSCTL_DQSGX_SHIFT 
-#undef DDR_PHY_DX8SL4DQSCTL_DQSGX_MASK 
+#undef DDR_PHY_DX8SL4DQSCTL_DQSGX_DEFVAL
+#undef DDR_PHY_DX8SL4DQSCTL_DQSGX_SHIFT
+#undef DDR_PHY_DX8SL4DQSCTL_DQSGX_MASK
 #define DDR_PHY_DX8SL4DQSCTL_DQSGX_DEFVAL                      0x01264000
 #define DDR_PHY_DX8SL4DQSCTL_DQSGX_SHIFT                       19
 #define DDR_PHY_DX8SL4DQSCTL_DQSGX_MASK                        0x00180000U
@@ -20990,9 +20990,9 @@
 /*
 * Low Power PLL Power Down
 */
-#undef DDR_PHY_DX8SL4DQSCTL_LPPLLPD_DEFVAL 
-#undef DDR_PHY_DX8SL4DQSCTL_LPPLLPD_SHIFT 
-#undef DDR_PHY_DX8SL4DQSCTL_LPPLLPD_MASK 
+#undef DDR_PHY_DX8SL4DQSCTL_LPPLLPD_DEFVAL
+#undef DDR_PHY_DX8SL4DQSCTL_LPPLLPD_SHIFT
+#undef DDR_PHY_DX8SL4DQSCTL_LPPLLPD_MASK
 #define DDR_PHY_DX8SL4DQSCTL_LPPLLPD_DEFVAL                    0x01264000
 #define DDR_PHY_DX8SL4DQSCTL_LPPLLPD_SHIFT                     18
 #define DDR_PHY_DX8SL4DQSCTL_LPPLLPD_MASK                      0x00040000U
@@ -21000,9 +21000,9 @@
 /*
 * Low Power I/O Power Down
 */
-#undef DDR_PHY_DX8SL4DQSCTL_LPIOPD_DEFVAL 
-#undef DDR_PHY_DX8SL4DQSCTL_LPIOPD_SHIFT 
-#undef DDR_PHY_DX8SL4DQSCTL_LPIOPD_MASK 
+#undef DDR_PHY_DX8SL4DQSCTL_LPIOPD_DEFVAL
+#undef DDR_PHY_DX8SL4DQSCTL_LPIOPD_SHIFT
+#undef DDR_PHY_DX8SL4DQSCTL_LPIOPD_MASK
 #define DDR_PHY_DX8SL4DQSCTL_LPIOPD_DEFVAL                     0x01264000
 #define DDR_PHY_DX8SL4DQSCTL_LPIOPD_SHIFT                      17
 #define DDR_PHY_DX8SL4DQSCTL_LPIOPD_MASK                       0x00020000U
@@ -21010,9 +21010,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_DEFVAL 
-#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_SHIFT 
-#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_MASK 
+#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_DEFVAL
+#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_SHIFT
+#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_MASK
 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_DEFVAL             0x01264000
 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_SHIFT              15
 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_MASK               0x00018000U
@@ -21020,9 +21020,9 @@
 /*
 * QS Counter Enable
 */
-#undef DDR_PHY_DX8SL4DQSCTL_QSCNTEN_DEFVAL 
-#undef DDR_PHY_DX8SL4DQSCTL_QSCNTEN_SHIFT 
-#undef DDR_PHY_DX8SL4DQSCTL_QSCNTEN_MASK 
+#undef DDR_PHY_DX8SL4DQSCTL_QSCNTEN_DEFVAL
+#undef DDR_PHY_DX8SL4DQSCTL_QSCNTEN_SHIFT
+#undef DDR_PHY_DX8SL4DQSCTL_QSCNTEN_MASK
 #define DDR_PHY_DX8SL4DQSCTL_QSCNTEN_DEFVAL                    0x01264000
 #define DDR_PHY_DX8SL4DQSCTL_QSCNTEN_SHIFT                     14
 #define DDR_PHY_DX8SL4DQSCTL_QSCNTEN_MASK                      0x00004000U
@@ -21030,9 +21030,9 @@
 /*
 * Unused DQ I/O Mode
 */
-#undef DDR_PHY_DX8SL4DQSCTL_UDQIOM_DEFVAL 
-#undef DDR_PHY_DX8SL4DQSCTL_UDQIOM_SHIFT 
-#undef DDR_PHY_DX8SL4DQSCTL_UDQIOM_MASK 
+#undef DDR_PHY_DX8SL4DQSCTL_UDQIOM_DEFVAL
+#undef DDR_PHY_DX8SL4DQSCTL_UDQIOM_SHIFT
+#undef DDR_PHY_DX8SL4DQSCTL_UDQIOM_MASK
 #define DDR_PHY_DX8SL4DQSCTL_UDQIOM_DEFVAL                     0x01264000
 #define DDR_PHY_DX8SL4DQSCTL_UDQIOM_SHIFT                      13
 #define DDR_PHY_DX8SL4DQSCTL_UDQIOM_MASK                       0x00002000U
@@ -21040,9 +21040,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_DEFVAL 
-#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_SHIFT 
-#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_MASK 
+#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_DEFVAL
+#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_SHIFT
+#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_MASK
 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_DEFVAL             0x01264000
 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_SHIFT              10
 #define DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_MASK               0x00001C00U
@@ -21050,9 +21050,9 @@
 /*
 * Data Slew Rate
 */
-#undef DDR_PHY_DX8SL4DQSCTL_DXSR_DEFVAL 
-#undef DDR_PHY_DX8SL4DQSCTL_DXSR_SHIFT 
-#undef DDR_PHY_DX8SL4DQSCTL_DXSR_MASK 
+#undef DDR_PHY_DX8SL4DQSCTL_DXSR_DEFVAL
+#undef DDR_PHY_DX8SL4DQSCTL_DXSR_SHIFT
+#undef DDR_PHY_DX8SL4DQSCTL_DXSR_MASK
 #define DDR_PHY_DX8SL4DQSCTL_DXSR_DEFVAL                       0x01264000
 #define DDR_PHY_DX8SL4DQSCTL_DXSR_SHIFT                        8
 #define DDR_PHY_DX8SL4DQSCTL_DXSR_MASK                         0x00000300U
@@ -21060,9 +21060,9 @@
 /*
 * DQS_N Resistor
 */
-#undef DDR_PHY_DX8SL4DQSCTL_DQSNRES_DEFVAL 
-#undef DDR_PHY_DX8SL4DQSCTL_DQSNRES_SHIFT 
-#undef DDR_PHY_DX8SL4DQSCTL_DQSNRES_MASK 
+#undef DDR_PHY_DX8SL4DQSCTL_DQSNRES_DEFVAL
+#undef DDR_PHY_DX8SL4DQSCTL_DQSNRES_SHIFT
+#undef DDR_PHY_DX8SL4DQSCTL_DQSNRES_MASK
 #define DDR_PHY_DX8SL4DQSCTL_DQSNRES_DEFVAL                    0x01264000
 #define DDR_PHY_DX8SL4DQSCTL_DQSNRES_SHIFT                     4
 #define DDR_PHY_DX8SL4DQSCTL_DQSNRES_MASK                      0x000000F0U
@@ -21070,9 +21070,9 @@
 /*
 * DQS Resistor
 */
-#undef DDR_PHY_DX8SL4DQSCTL_DQSRES_DEFVAL 
-#undef DDR_PHY_DX8SL4DQSCTL_DQSRES_SHIFT 
-#undef DDR_PHY_DX8SL4DQSCTL_DQSRES_MASK 
+#undef DDR_PHY_DX8SL4DQSCTL_DQSRES_DEFVAL
+#undef DDR_PHY_DX8SL4DQSCTL_DQSRES_SHIFT
+#undef DDR_PHY_DX8SL4DQSCTL_DQSRES_MASK
 #define DDR_PHY_DX8SL4DQSCTL_DQSRES_DEFVAL                     0x01264000
 #define DDR_PHY_DX8SL4DQSCTL_DQSRES_SHIFT                      0
 #define DDR_PHY_DX8SL4DQSCTL_DQSRES_MASK                       0x0000000FU
@@ -21080,9 +21080,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_DEFVAL 
-#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_SHIFT 
-#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_MASK 
+#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_DEFVAL
+#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_SHIFT
+#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_MASK
 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_DEFVAL             0x00141800
 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_SHIFT              24
 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_MASK               0xFF000000U
@@ -21090,9 +21090,9 @@
 /*
 * Configurable Read Data Enable
 */
-#undef DDR_PHY_DX8SL4DXCTL2_CRDEN_DEFVAL 
-#undef DDR_PHY_DX8SL4DXCTL2_CRDEN_SHIFT 
-#undef DDR_PHY_DX8SL4DXCTL2_CRDEN_MASK 
+#undef DDR_PHY_DX8SL4DXCTL2_CRDEN_DEFVAL
+#undef DDR_PHY_DX8SL4DXCTL2_CRDEN_SHIFT
+#undef DDR_PHY_DX8SL4DXCTL2_CRDEN_MASK
 #define DDR_PHY_DX8SL4DXCTL2_CRDEN_DEFVAL                      0x00141800
 #define DDR_PHY_DX8SL4DXCTL2_CRDEN_SHIFT                       23
 #define DDR_PHY_DX8SL4DXCTL2_CRDEN_MASK                        0x00800000U
@@ -21100,9 +21100,9 @@
 /*
 * OX Extension during Post-amble
 */
-#undef DDR_PHY_DX8SL4DXCTL2_POSOEX_DEFVAL 
-#undef DDR_PHY_DX8SL4DXCTL2_POSOEX_SHIFT 
-#undef DDR_PHY_DX8SL4DXCTL2_POSOEX_MASK 
+#undef DDR_PHY_DX8SL4DXCTL2_POSOEX_DEFVAL
+#undef DDR_PHY_DX8SL4DXCTL2_POSOEX_SHIFT
+#undef DDR_PHY_DX8SL4DXCTL2_POSOEX_MASK
 #define DDR_PHY_DX8SL4DXCTL2_POSOEX_DEFVAL                     0x00141800
 #define DDR_PHY_DX8SL4DXCTL2_POSOEX_SHIFT                      20
 #define DDR_PHY_DX8SL4DXCTL2_POSOEX_MASK                       0x00700000U
@@ -21110,9 +21110,9 @@
 /*
 * OE Extension during Pre-amble
 */
-#undef DDR_PHY_DX8SL4DXCTL2_PREOEX_DEFVAL 
-#undef DDR_PHY_DX8SL4DXCTL2_PREOEX_SHIFT 
-#undef DDR_PHY_DX8SL4DXCTL2_PREOEX_MASK 
+#undef DDR_PHY_DX8SL4DXCTL2_PREOEX_DEFVAL
+#undef DDR_PHY_DX8SL4DXCTL2_PREOEX_SHIFT
+#undef DDR_PHY_DX8SL4DXCTL2_PREOEX_MASK
 #define DDR_PHY_DX8SL4DXCTL2_PREOEX_DEFVAL                     0x00141800
 #define DDR_PHY_DX8SL4DXCTL2_PREOEX_SHIFT                      18
 #define DDR_PHY_DX8SL4DXCTL2_PREOEX_MASK                       0x000C0000U
@@ -21120,9 +21120,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_17_DEFVAL 
-#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_17_SHIFT 
-#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_17_MASK 
+#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_17_DEFVAL
+#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_17_SHIFT
+#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_17_MASK
 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_17_DEFVAL                0x00141800
 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_17_SHIFT                 17
 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_17_MASK                  0x00020000U
@@ -21130,9 +21130,9 @@
 /*
 * I/O Assisted Gate Select
 */
-#undef DDR_PHY_DX8SL4DXCTL2_IOAG_DEFVAL 
-#undef DDR_PHY_DX8SL4DXCTL2_IOAG_SHIFT 
-#undef DDR_PHY_DX8SL4DXCTL2_IOAG_MASK 
+#undef DDR_PHY_DX8SL4DXCTL2_IOAG_DEFVAL
+#undef DDR_PHY_DX8SL4DXCTL2_IOAG_SHIFT
+#undef DDR_PHY_DX8SL4DXCTL2_IOAG_MASK
 #define DDR_PHY_DX8SL4DXCTL2_IOAG_DEFVAL                       0x00141800
 #define DDR_PHY_DX8SL4DXCTL2_IOAG_SHIFT                        16
 #define DDR_PHY_DX8SL4DXCTL2_IOAG_MASK                         0x00010000U
@@ -21140,9 +21140,9 @@
 /*
 * I/O Loopback Select
 */
-#undef DDR_PHY_DX8SL4DXCTL2_IOLB_DEFVAL 
-#undef DDR_PHY_DX8SL4DXCTL2_IOLB_SHIFT 
-#undef DDR_PHY_DX8SL4DXCTL2_IOLB_MASK 
+#undef DDR_PHY_DX8SL4DXCTL2_IOLB_DEFVAL
+#undef DDR_PHY_DX8SL4DXCTL2_IOLB_SHIFT
+#undef DDR_PHY_DX8SL4DXCTL2_IOLB_MASK
 #define DDR_PHY_DX8SL4DXCTL2_IOLB_DEFVAL                       0x00141800
 #define DDR_PHY_DX8SL4DXCTL2_IOLB_SHIFT                        15
 #define DDR_PHY_DX8SL4DXCTL2_IOLB_MASK                         0x00008000U
@@ -21150,9 +21150,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_DEFVAL 
-#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_SHIFT 
-#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_MASK 
+#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_DEFVAL
+#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_SHIFT
+#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_MASK
 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_DEFVAL             0x00141800
 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_SHIFT              13
 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_MASK               0x00006000U
@@ -21160,9 +21160,9 @@
 /*
 * Low Power Wakeup Threshold
 */
-#undef DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_DEFVAL 
-#undef DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_SHIFT 
-#undef DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_MASK 
+#undef DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_DEFVAL
+#undef DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_SHIFT
+#undef DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_MASK
 #define DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_DEFVAL             0x00141800
 #define DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_SHIFT              9
 #define DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_MASK               0x00001E00U
@@ -21170,9 +21170,9 @@
 /*
 * Read Data Bus Inversion Enable
 */
-#undef DDR_PHY_DX8SL4DXCTL2_RDBI_DEFVAL 
-#undef DDR_PHY_DX8SL4DXCTL2_RDBI_SHIFT 
-#undef DDR_PHY_DX8SL4DXCTL2_RDBI_MASK 
+#undef DDR_PHY_DX8SL4DXCTL2_RDBI_DEFVAL
+#undef DDR_PHY_DX8SL4DXCTL2_RDBI_SHIFT
+#undef DDR_PHY_DX8SL4DXCTL2_RDBI_MASK
 #define DDR_PHY_DX8SL4DXCTL2_RDBI_DEFVAL                       0x00141800
 #define DDR_PHY_DX8SL4DXCTL2_RDBI_SHIFT                        8
 #define DDR_PHY_DX8SL4DXCTL2_RDBI_MASK                         0x00000100U
@@ -21180,9 +21180,9 @@
 /*
 * Write Data Bus Inversion Enable
 */
-#undef DDR_PHY_DX8SL4DXCTL2_WDBI_DEFVAL 
-#undef DDR_PHY_DX8SL4DXCTL2_WDBI_SHIFT 
-#undef DDR_PHY_DX8SL4DXCTL2_WDBI_MASK 
+#undef DDR_PHY_DX8SL4DXCTL2_WDBI_DEFVAL
+#undef DDR_PHY_DX8SL4DXCTL2_WDBI_SHIFT
+#undef DDR_PHY_DX8SL4DXCTL2_WDBI_MASK
 #define DDR_PHY_DX8SL4DXCTL2_WDBI_DEFVAL                       0x00141800
 #define DDR_PHY_DX8SL4DXCTL2_WDBI_SHIFT                        7
 #define DDR_PHY_DX8SL4DXCTL2_WDBI_MASK                         0x00000080U
@@ -21190,9 +21190,9 @@
 /*
 * PUB Read FIFO Bypass
 */
-#undef DDR_PHY_DX8SL4DXCTL2_PRFBYP_DEFVAL 
-#undef DDR_PHY_DX8SL4DXCTL2_PRFBYP_SHIFT 
-#undef DDR_PHY_DX8SL4DXCTL2_PRFBYP_MASK 
+#undef DDR_PHY_DX8SL4DXCTL2_PRFBYP_DEFVAL
+#undef DDR_PHY_DX8SL4DXCTL2_PRFBYP_SHIFT
+#undef DDR_PHY_DX8SL4DXCTL2_PRFBYP_MASK
 #define DDR_PHY_DX8SL4DXCTL2_PRFBYP_DEFVAL                     0x00141800
 #define DDR_PHY_DX8SL4DXCTL2_PRFBYP_SHIFT                      6
 #define DDR_PHY_DX8SL4DXCTL2_PRFBYP_MASK                       0x00000040U
@@ -21200,9 +21200,9 @@
 /*
 * DATX8 Receive FIFO Read Mode
 */
-#undef DDR_PHY_DX8SL4DXCTL2_RDMODE_DEFVAL 
-#undef DDR_PHY_DX8SL4DXCTL2_RDMODE_SHIFT 
-#undef DDR_PHY_DX8SL4DXCTL2_RDMODE_MASK 
+#undef DDR_PHY_DX8SL4DXCTL2_RDMODE_DEFVAL
+#undef DDR_PHY_DX8SL4DXCTL2_RDMODE_SHIFT
+#undef DDR_PHY_DX8SL4DXCTL2_RDMODE_MASK
 #define DDR_PHY_DX8SL4DXCTL2_RDMODE_DEFVAL                     0x00141800
 #define DDR_PHY_DX8SL4DXCTL2_RDMODE_SHIFT                      4
 #define DDR_PHY_DX8SL4DXCTL2_RDMODE_MASK                       0x00000030U
@@ -21210,9 +21210,9 @@
 /*
 * Disables the Read FIFO Reset
 */
-#undef DDR_PHY_DX8SL4DXCTL2_DISRST_DEFVAL 
-#undef DDR_PHY_DX8SL4DXCTL2_DISRST_SHIFT 
-#undef DDR_PHY_DX8SL4DXCTL2_DISRST_MASK 
+#undef DDR_PHY_DX8SL4DXCTL2_DISRST_DEFVAL
+#undef DDR_PHY_DX8SL4DXCTL2_DISRST_SHIFT
+#undef DDR_PHY_DX8SL4DXCTL2_DISRST_MASK
 #define DDR_PHY_DX8SL4DXCTL2_DISRST_DEFVAL                     0x00141800
 #define DDR_PHY_DX8SL4DXCTL2_DISRST_SHIFT                      3
 #define DDR_PHY_DX8SL4DXCTL2_DISRST_MASK                       0x00000008U
@@ -21220,9 +21220,9 @@
 /*
 * Read DQS Gate I/O Loopback
 */
-#undef DDR_PHY_DX8SL4DXCTL2_DQSGLB_DEFVAL 
-#undef DDR_PHY_DX8SL4DXCTL2_DQSGLB_SHIFT 
-#undef DDR_PHY_DX8SL4DXCTL2_DQSGLB_MASK 
+#undef DDR_PHY_DX8SL4DXCTL2_DQSGLB_DEFVAL
+#undef DDR_PHY_DX8SL4DXCTL2_DQSGLB_SHIFT
+#undef DDR_PHY_DX8SL4DXCTL2_DQSGLB_MASK
 #define DDR_PHY_DX8SL4DXCTL2_DQSGLB_DEFVAL                     0x00141800
 #define DDR_PHY_DX8SL4DXCTL2_DQSGLB_SHIFT                      1
 #define DDR_PHY_DX8SL4DXCTL2_DQSGLB_MASK                       0x00000006U
@@ -21230,9 +21230,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_0_DEFVAL 
-#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_0_SHIFT 
-#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_0_MASK 
+#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_0_DEFVAL
+#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_0_SHIFT
+#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_0_MASK
 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_0_DEFVAL                 0x00141800
 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_0_SHIFT                  0
 #define DDR_PHY_DX8SL4DXCTL2_RESERVED_0_MASK                   0x00000001U
@@ -21240,9 +21240,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SL4IOCR_RESERVED_31_DEFVAL 
-#undef DDR_PHY_DX8SL4IOCR_RESERVED_31_SHIFT 
-#undef DDR_PHY_DX8SL4IOCR_RESERVED_31_MASK 
+#undef DDR_PHY_DX8SL4IOCR_RESERVED_31_DEFVAL
+#undef DDR_PHY_DX8SL4IOCR_RESERVED_31_SHIFT
+#undef DDR_PHY_DX8SL4IOCR_RESERVED_31_MASK
 #define DDR_PHY_DX8SL4IOCR_RESERVED_31_DEFVAL                  0x00000000
 #define DDR_PHY_DX8SL4IOCR_RESERVED_31_SHIFT                   31
 #define DDR_PHY_DX8SL4IOCR_RESERVED_31_MASK                    0x80000000U
@@ -21250,9 +21250,9 @@
 /*
 * PVREF_DAC REFSEL range select
 */
-#undef DDR_PHY_DX8SL4IOCR_DXDACRANGE_DEFVAL 
-#undef DDR_PHY_DX8SL4IOCR_DXDACRANGE_SHIFT 
-#undef DDR_PHY_DX8SL4IOCR_DXDACRANGE_MASK 
+#undef DDR_PHY_DX8SL4IOCR_DXDACRANGE_DEFVAL
+#undef DDR_PHY_DX8SL4IOCR_DXDACRANGE_SHIFT
+#undef DDR_PHY_DX8SL4IOCR_DXDACRANGE_MASK
 #define DDR_PHY_DX8SL4IOCR_DXDACRANGE_DEFVAL                   0x00000000
 #define DDR_PHY_DX8SL4IOCR_DXDACRANGE_SHIFT                    28
 #define DDR_PHY_DX8SL4IOCR_DXDACRANGE_MASK                     0x70000000U
@@ -21260,9 +21260,9 @@
 /*
 * IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
 */
-#undef DDR_PHY_DX8SL4IOCR_DXVREFIOM_DEFVAL 
-#undef DDR_PHY_DX8SL4IOCR_DXVREFIOM_SHIFT 
-#undef DDR_PHY_DX8SL4IOCR_DXVREFIOM_MASK 
+#undef DDR_PHY_DX8SL4IOCR_DXVREFIOM_DEFVAL
+#undef DDR_PHY_DX8SL4IOCR_DXVREFIOM_SHIFT
+#undef DDR_PHY_DX8SL4IOCR_DXVREFIOM_MASK
 #define DDR_PHY_DX8SL4IOCR_DXVREFIOM_DEFVAL                    0x00000000
 #define DDR_PHY_DX8SL4IOCR_DXVREFIOM_SHIFT                     25
 #define DDR_PHY_DX8SL4IOCR_DXVREFIOM_MASK                      0x0E000000U
@@ -21270,9 +21270,9 @@
 /*
 * DX IO Mode
 */
-#undef DDR_PHY_DX8SL4IOCR_DXIOM_DEFVAL 
-#undef DDR_PHY_DX8SL4IOCR_DXIOM_SHIFT 
-#undef DDR_PHY_DX8SL4IOCR_DXIOM_MASK 
+#undef DDR_PHY_DX8SL4IOCR_DXIOM_DEFVAL
+#undef DDR_PHY_DX8SL4IOCR_DXIOM_SHIFT
+#undef DDR_PHY_DX8SL4IOCR_DXIOM_MASK
 #define DDR_PHY_DX8SL4IOCR_DXIOM_DEFVAL                        0x00000000
 #define DDR_PHY_DX8SL4IOCR_DXIOM_SHIFT                         22
 #define DDR_PHY_DX8SL4IOCR_DXIOM_MASK                          0x01C00000U
@@ -21280,9 +21280,9 @@
 /*
 * DX IO Transmitter Mode
 */
-#undef DDR_PHY_DX8SL4IOCR_DXTXM_DEFVAL 
-#undef DDR_PHY_DX8SL4IOCR_DXTXM_SHIFT 
-#undef DDR_PHY_DX8SL4IOCR_DXTXM_MASK 
+#undef DDR_PHY_DX8SL4IOCR_DXTXM_DEFVAL
+#undef DDR_PHY_DX8SL4IOCR_DXTXM_SHIFT
+#undef DDR_PHY_DX8SL4IOCR_DXTXM_MASK
 #define DDR_PHY_DX8SL4IOCR_DXTXM_DEFVAL                        0x00000000
 #define DDR_PHY_DX8SL4IOCR_DXTXM_SHIFT                         11
 #define DDR_PHY_DX8SL4IOCR_DXTXM_MASK                          0x003FF800U
@@ -21290,9 +21290,9 @@
 /*
 * DX IO Receiver Mode
 */
-#undef DDR_PHY_DX8SL4IOCR_DXRXM_DEFVAL 
-#undef DDR_PHY_DX8SL4IOCR_DXRXM_SHIFT 
-#undef DDR_PHY_DX8SL4IOCR_DXRXM_MASK 
+#undef DDR_PHY_DX8SL4IOCR_DXRXM_DEFVAL
+#undef DDR_PHY_DX8SL4IOCR_DXRXM_SHIFT
+#undef DDR_PHY_DX8SL4IOCR_DXRXM_MASK
 #define DDR_PHY_DX8SL4IOCR_DXRXM_DEFVAL                        0x00000000
 #define DDR_PHY_DX8SL4IOCR_DXRXM_SHIFT                         0
 #define DDR_PHY_DX8SL4IOCR_DXRXM_MASK                          0x000007FFU
@@ -21300,9 +21300,9 @@
 /*
 * PLL Bypass
 */
-#undef DDR_PHY_DX8SLBPLLCR0_PLLBYP_DEFVAL 
-#undef DDR_PHY_DX8SLBPLLCR0_PLLBYP_SHIFT 
-#undef DDR_PHY_DX8SLBPLLCR0_PLLBYP_MASK 
+#undef DDR_PHY_DX8SLBPLLCR0_PLLBYP_DEFVAL
+#undef DDR_PHY_DX8SLBPLLCR0_PLLBYP_SHIFT
+#undef DDR_PHY_DX8SLBPLLCR0_PLLBYP_MASK
 #define DDR_PHY_DX8SLBPLLCR0_PLLBYP_DEFVAL                     0x00000000
 #define DDR_PHY_DX8SLBPLLCR0_PLLBYP_SHIFT                      31
 #define DDR_PHY_DX8SLBPLLCR0_PLLBYP_MASK                       0x80000000U
@@ -21310,9 +21310,9 @@
 /*
 * PLL Reset
 */
-#undef DDR_PHY_DX8SLBPLLCR0_PLLRST_DEFVAL 
-#undef DDR_PHY_DX8SLBPLLCR0_PLLRST_SHIFT 
-#undef DDR_PHY_DX8SLBPLLCR0_PLLRST_MASK 
+#undef DDR_PHY_DX8SLBPLLCR0_PLLRST_DEFVAL
+#undef DDR_PHY_DX8SLBPLLCR0_PLLRST_SHIFT
+#undef DDR_PHY_DX8SLBPLLCR0_PLLRST_MASK
 #define DDR_PHY_DX8SLBPLLCR0_PLLRST_DEFVAL                     0x00000000
 #define DDR_PHY_DX8SLBPLLCR0_PLLRST_SHIFT                      30
 #define DDR_PHY_DX8SLBPLLCR0_PLLRST_MASK                       0x40000000U
@@ -21320,9 +21320,9 @@
 /*
 * PLL Power Down
 */
-#undef DDR_PHY_DX8SLBPLLCR0_PLLPD_DEFVAL 
-#undef DDR_PHY_DX8SLBPLLCR0_PLLPD_SHIFT 
-#undef DDR_PHY_DX8SLBPLLCR0_PLLPD_MASK 
+#undef DDR_PHY_DX8SLBPLLCR0_PLLPD_DEFVAL
+#undef DDR_PHY_DX8SLBPLLCR0_PLLPD_SHIFT
+#undef DDR_PHY_DX8SLBPLLCR0_PLLPD_MASK
 #define DDR_PHY_DX8SLBPLLCR0_PLLPD_DEFVAL                      0x00000000
 #define DDR_PHY_DX8SLBPLLCR0_PLLPD_SHIFT                       29
 #define DDR_PHY_DX8SLBPLLCR0_PLLPD_MASK                        0x20000000U
@@ -21330,9 +21330,9 @@
 /*
 * Reference Stop Mode
 */
-#undef DDR_PHY_DX8SLBPLLCR0_RSTOPM_DEFVAL 
-#undef DDR_PHY_DX8SLBPLLCR0_RSTOPM_SHIFT 
-#undef DDR_PHY_DX8SLBPLLCR0_RSTOPM_MASK 
+#undef DDR_PHY_DX8SLBPLLCR0_RSTOPM_DEFVAL
+#undef DDR_PHY_DX8SLBPLLCR0_RSTOPM_SHIFT
+#undef DDR_PHY_DX8SLBPLLCR0_RSTOPM_MASK
 #define DDR_PHY_DX8SLBPLLCR0_RSTOPM_DEFVAL                     0x00000000
 #define DDR_PHY_DX8SLBPLLCR0_RSTOPM_SHIFT                      28
 #define DDR_PHY_DX8SLBPLLCR0_RSTOPM_MASK                       0x10000000U
@@ -21340,9 +21340,9 @@
 /*
 * PLL Frequency Select
 */
-#undef DDR_PHY_DX8SLBPLLCR0_FRQSEL_DEFVAL 
-#undef DDR_PHY_DX8SLBPLLCR0_FRQSEL_SHIFT 
-#undef DDR_PHY_DX8SLBPLLCR0_FRQSEL_MASK 
+#undef DDR_PHY_DX8SLBPLLCR0_FRQSEL_DEFVAL
+#undef DDR_PHY_DX8SLBPLLCR0_FRQSEL_SHIFT
+#undef DDR_PHY_DX8SLBPLLCR0_FRQSEL_MASK
 #define DDR_PHY_DX8SLBPLLCR0_FRQSEL_DEFVAL                     0x00000000
 #define DDR_PHY_DX8SLBPLLCR0_FRQSEL_SHIFT                      24
 #define DDR_PHY_DX8SLBPLLCR0_FRQSEL_MASK                       0x0F000000U
@@ -21350,9 +21350,9 @@
 /*
 * Relock Mode
 */
-#undef DDR_PHY_DX8SLBPLLCR0_RLOCKM_DEFVAL 
-#undef DDR_PHY_DX8SLBPLLCR0_RLOCKM_SHIFT 
-#undef DDR_PHY_DX8SLBPLLCR0_RLOCKM_MASK 
+#undef DDR_PHY_DX8SLBPLLCR0_RLOCKM_DEFVAL
+#undef DDR_PHY_DX8SLBPLLCR0_RLOCKM_SHIFT
+#undef DDR_PHY_DX8SLBPLLCR0_RLOCKM_MASK
 #define DDR_PHY_DX8SLBPLLCR0_RLOCKM_DEFVAL                     0x00000000
 #define DDR_PHY_DX8SLBPLLCR0_RLOCKM_SHIFT                      23
 #define DDR_PHY_DX8SLBPLLCR0_RLOCKM_MASK                       0x00800000U
@@ -21360,9 +21360,9 @@
 /*
 * Charge Pump Proportional Current Control
 */
-#undef DDR_PHY_DX8SLBPLLCR0_CPPC_DEFVAL 
-#undef DDR_PHY_DX8SLBPLLCR0_CPPC_SHIFT 
-#undef DDR_PHY_DX8SLBPLLCR0_CPPC_MASK 
+#undef DDR_PHY_DX8SLBPLLCR0_CPPC_DEFVAL
+#undef DDR_PHY_DX8SLBPLLCR0_CPPC_SHIFT
+#undef DDR_PHY_DX8SLBPLLCR0_CPPC_MASK
 #define DDR_PHY_DX8SLBPLLCR0_CPPC_DEFVAL                       0x00000000
 #define DDR_PHY_DX8SLBPLLCR0_CPPC_SHIFT                        17
 #define DDR_PHY_DX8SLBPLLCR0_CPPC_MASK                         0x007E0000U
@@ -21370,9 +21370,9 @@
 /*
 * Charge Pump Integrating Current Control
 */
-#undef DDR_PHY_DX8SLBPLLCR0_CPIC_DEFVAL 
-#undef DDR_PHY_DX8SLBPLLCR0_CPIC_SHIFT 
-#undef DDR_PHY_DX8SLBPLLCR0_CPIC_MASK 
+#undef DDR_PHY_DX8SLBPLLCR0_CPIC_DEFVAL
+#undef DDR_PHY_DX8SLBPLLCR0_CPIC_SHIFT
+#undef DDR_PHY_DX8SLBPLLCR0_CPIC_MASK
 #define DDR_PHY_DX8SLBPLLCR0_CPIC_DEFVAL                       0x00000000
 #define DDR_PHY_DX8SLBPLLCR0_CPIC_SHIFT                        13
 #define DDR_PHY_DX8SLBPLLCR0_CPIC_MASK                         0x0001E000U
@@ -21380,9 +21380,9 @@
 /*
 * Gear Shift
 */
-#undef DDR_PHY_DX8SLBPLLCR0_GSHIFT_DEFVAL 
-#undef DDR_PHY_DX8SLBPLLCR0_GSHIFT_SHIFT 
-#undef DDR_PHY_DX8SLBPLLCR0_GSHIFT_MASK 
+#undef DDR_PHY_DX8SLBPLLCR0_GSHIFT_DEFVAL
+#undef DDR_PHY_DX8SLBPLLCR0_GSHIFT_SHIFT
+#undef DDR_PHY_DX8SLBPLLCR0_GSHIFT_MASK
 #define DDR_PHY_DX8SLBPLLCR0_GSHIFT_DEFVAL                     0x00000000
 #define DDR_PHY_DX8SLBPLLCR0_GSHIFT_SHIFT                      12
 #define DDR_PHY_DX8SLBPLLCR0_GSHIFT_MASK                       0x00001000U
@@ -21390,9 +21390,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SLBPLLCR0_RESERVED_11_9_DEFVAL 
-#undef DDR_PHY_DX8SLBPLLCR0_RESERVED_11_9_SHIFT 
-#undef DDR_PHY_DX8SLBPLLCR0_RESERVED_11_9_MASK 
+#undef DDR_PHY_DX8SLBPLLCR0_RESERVED_11_9_DEFVAL
+#undef DDR_PHY_DX8SLBPLLCR0_RESERVED_11_9_SHIFT
+#undef DDR_PHY_DX8SLBPLLCR0_RESERVED_11_9_MASK
 #define DDR_PHY_DX8SLBPLLCR0_RESERVED_11_9_DEFVAL              0x00000000
 #define DDR_PHY_DX8SLBPLLCR0_RESERVED_11_9_SHIFT               9
 #define DDR_PHY_DX8SLBPLLCR0_RESERVED_11_9_MASK                0x00000E00U
@@ -21400,9 +21400,9 @@
 /*
 * Analog Test Enable (ATOEN)
 */
-#undef DDR_PHY_DX8SLBPLLCR0_ATOEN_DEFVAL 
-#undef DDR_PHY_DX8SLBPLLCR0_ATOEN_SHIFT 
-#undef DDR_PHY_DX8SLBPLLCR0_ATOEN_MASK 
+#undef DDR_PHY_DX8SLBPLLCR0_ATOEN_DEFVAL
+#undef DDR_PHY_DX8SLBPLLCR0_ATOEN_SHIFT
+#undef DDR_PHY_DX8SLBPLLCR0_ATOEN_MASK
 #define DDR_PHY_DX8SLBPLLCR0_ATOEN_DEFVAL                      0x00000000
 #define DDR_PHY_DX8SLBPLLCR0_ATOEN_SHIFT                       8
 #define DDR_PHY_DX8SLBPLLCR0_ATOEN_MASK                        0x00000100U
@@ -21410,9 +21410,9 @@
 /*
 * Analog Test Control
 */
-#undef DDR_PHY_DX8SLBPLLCR0_ATC_DEFVAL 
-#undef DDR_PHY_DX8SLBPLLCR0_ATC_SHIFT 
-#undef DDR_PHY_DX8SLBPLLCR0_ATC_MASK 
+#undef DDR_PHY_DX8SLBPLLCR0_ATC_DEFVAL
+#undef DDR_PHY_DX8SLBPLLCR0_ATC_SHIFT
+#undef DDR_PHY_DX8SLBPLLCR0_ATC_MASK
 #define DDR_PHY_DX8SLBPLLCR0_ATC_DEFVAL                        0x00000000
 #define DDR_PHY_DX8SLBPLLCR0_ATC_SHIFT                         4
 #define DDR_PHY_DX8SLBPLLCR0_ATC_MASK                          0x000000F0U
@@ -21420,9 +21420,9 @@
 /*
 * Digital Test Control
 */
-#undef DDR_PHY_DX8SLBPLLCR0_DTC_DEFVAL 
-#undef DDR_PHY_DX8SLBPLLCR0_DTC_SHIFT 
-#undef DDR_PHY_DX8SLBPLLCR0_DTC_MASK 
+#undef DDR_PHY_DX8SLBPLLCR0_DTC_DEFVAL
+#undef DDR_PHY_DX8SLBPLLCR0_DTC_SHIFT
+#undef DDR_PHY_DX8SLBPLLCR0_DTC_MASK
 #define DDR_PHY_DX8SLBPLLCR0_DTC_DEFVAL                        0x00000000
 #define DDR_PHY_DX8SLBPLLCR0_DTC_SHIFT                         0
 #define DDR_PHY_DX8SLBPLLCR0_DTC_MASK                          0x0000000FU
@@ -21430,9 +21430,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_DEFVAL 
-#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_SHIFT 
-#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_MASK 
+#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_DEFVAL
+#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_SHIFT
+#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_MASK
 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_DEFVAL             0x00000000
 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_SHIFT              25
 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_MASK               0xFE000000U
@@ -21440,9 +21440,9 @@
 /*
 * Read Path Rise-to-Rise Mode
 */
-#undef DDR_PHY_DX8SLBDQSCTL_RRRMODE_DEFVAL 
-#undef DDR_PHY_DX8SLBDQSCTL_RRRMODE_SHIFT 
-#undef DDR_PHY_DX8SLBDQSCTL_RRRMODE_MASK 
+#undef DDR_PHY_DX8SLBDQSCTL_RRRMODE_DEFVAL
+#undef DDR_PHY_DX8SLBDQSCTL_RRRMODE_SHIFT
+#undef DDR_PHY_DX8SLBDQSCTL_RRRMODE_MASK
 #define DDR_PHY_DX8SLBDQSCTL_RRRMODE_DEFVAL                    0x00000000
 #define DDR_PHY_DX8SLBDQSCTL_RRRMODE_SHIFT                     24
 #define DDR_PHY_DX8SLBDQSCTL_RRRMODE_MASK                      0x01000000U
@@ -21450,9 +21450,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_DEFVAL 
-#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_SHIFT 
-#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_MASK 
+#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_DEFVAL
+#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_SHIFT
+#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_MASK
 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_DEFVAL             0x00000000
 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_SHIFT              22
 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_MASK               0x00C00000U
@@ -21460,9 +21460,9 @@
 /*
 * Write Path Rise-to-Rise Mode
 */
-#undef DDR_PHY_DX8SLBDQSCTL_WRRMODE_DEFVAL 
-#undef DDR_PHY_DX8SLBDQSCTL_WRRMODE_SHIFT 
-#undef DDR_PHY_DX8SLBDQSCTL_WRRMODE_MASK 
+#undef DDR_PHY_DX8SLBDQSCTL_WRRMODE_DEFVAL
+#undef DDR_PHY_DX8SLBDQSCTL_WRRMODE_SHIFT
+#undef DDR_PHY_DX8SLBDQSCTL_WRRMODE_MASK
 #define DDR_PHY_DX8SLBDQSCTL_WRRMODE_DEFVAL                    0x00000000
 #define DDR_PHY_DX8SLBDQSCTL_WRRMODE_SHIFT                     21
 #define DDR_PHY_DX8SLBDQSCTL_WRRMODE_MASK                      0x00200000U
@@ -21470,9 +21470,9 @@
 /*
 * DQS Gate Extension
 */
-#undef DDR_PHY_DX8SLBDQSCTL_DQSGX_DEFVAL 
-#undef DDR_PHY_DX8SLBDQSCTL_DQSGX_SHIFT 
-#undef DDR_PHY_DX8SLBDQSCTL_DQSGX_MASK 
+#undef DDR_PHY_DX8SLBDQSCTL_DQSGX_DEFVAL
+#undef DDR_PHY_DX8SLBDQSCTL_DQSGX_SHIFT
+#undef DDR_PHY_DX8SLBDQSCTL_DQSGX_MASK
 #define DDR_PHY_DX8SLBDQSCTL_DQSGX_DEFVAL                      0x00000000
 #define DDR_PHY_DX8SLBDQSCTL_DQSGX_SHIFT                       19
 #define DDR_PHY_DX8SLBDQSCTL_DQSGX_MASK                        0x00180000U
@@ -21480,9 +21480,9 @@
 /*
 * Low Power PLL Power Down
 */
-#undef DDR_PHY_DX8SLBDQSCTL_LPPLLPD_DEFVAL 
-#undef DDR_PHY_DX8SLBDQSCTL_LPPLLPD_SHIFT 
-#undef DDR_PHY_DX8SLBDQSCTL_LPPLLPD_MASK 
+#undef DDR_PHY_DX8SLBDQSCTL_LPPLLPD_DEFVAL
+#undef DDR_PHY_DX8SLBDQSCTL_LPPLLPD_SHIFT
+#undef DDR_PHY_DX8SLBDQSCTL_LPPLLPD_MASK
 #define DDR_PHY_DX8SLBDQSCTL_LPPLLPD_DEFVAL                    0x00000000
 #define DDR_PHY_DX8SLBDQSCTL_LPPLLPD_SHIFT                     18
 #define DDR_PHY_DX8SLBDQSCTL_LPPLLPD_MASK                      0x00040000U
@@ -21490,9 +21490,9 @@
 /*
 * Low Power I/O Power Down
 */
-#undef DDR_PHY_DX8SLBDQSCTL_LPIOPD_DEFVAL 
-#undef DDR_PHY_DX8SLBDQSCTL_LPIOPD_SHIFT 
-#undef DDR_PHY_DX8SLBDQSCTL_LPIOPD_MASK 
+#undef DDR_PHY_DX8SLBDQSCTL_LPIOPD_DEFVAL
+#undef DDR_PHY_DX8SLBDQSCTL_LPIOPD_SHIFT
+#undef DDR_PHY_DX8SLBDQSCTL_LPIOPD_MASK
 #define DDR_PHY_DX8SLBDQSCTL_LPIOPD_DEFVAL                     0x00000000
 #define DDR_PHY_DX8SLBDQSCTL_LPIOPD_SHIFT                      17
 #define DDR_PHY_DX8SLBDQSCTL_LPIOPD_MASK                       0x00020000U
@@ -21500,9 +21500,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_DEFVAL 
-#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_SHIFT 
-#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_MASK 
+#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_DEFVAL
+#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_SHIFT
+#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_MASK
 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_DEFVAL             0x00000000
 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_SHIFT              15
 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_MASK               0x00018000U
@@ -21510,9 +21510,9 @@
 /*
 * QS Counter Enable
 */
-#undef DDR_PHY_DX8SLBDQSCTL_QSCNTEN_DEFVAL 
-#undef DDR_PHY_DX8SLBDQSCTL_QSCNTEN_SHIFT 
-#undef DDR_PHY_DX8SLBDQSCTL_QSCNTEN_MASK 
+#undef DDR_PHY_DX8SLBDQSCTL_QSCNTEN_DEFVAL
+#undef DDR_PHY_DX8SLBDQSCTL_QSCNTEN_SHIFT
+#undef DDR_PHY_DX8SLBDQSCTL_QSCNTEN_MASK
 #define DDR_PHY_DX8SLBDQSCTL_QSCNTEN_DEFVAL                    0x00000000
 #define DDR_PHY_DX8SLBDQSCTL_QSCNTEN_SHIFT                     14
 #define DDR_PHY_DX8SLBDQSCTL_QSCNTEN_MASK                      0x00004000U
@@ -21520,9 +21520,9 @@
 /*
 * Unused DQ I/O Mode
 */
-#undef DDR_PHY_DX8SLBDQSCTL_UDQIOM_DEFVAL 
-#undef DDR_PHY_DX8SLBDQSCTL_UDQIOM_SHIFT 
-#undef DDR_PHY_DX8SLBDQSCTL_UDQIOM_MASK 
+#undef DDR_PHY_DX8SLBDQSCTL_UDQIOM_DEFVAL
+#undef DDR_PHY_DX8SLBDQSCTL_UDQIOM_SHIFT
+#undef DDR_PHY_DX8SLBDQSCTL_UDQIOM_MASK
 #define DDR_PHY_DX8SLBDQSCTL_UDQIOM_DEFVAL                     0x00000000
 #define DDR_PHY_DX8SLBDQSCTL_UDQIOM_SHIFT                      13
 #define DDR_PHY_DX8SLBDQSCTL_UDQIOM_MASK                       0x00002000U
@@ -21530,9 +21530,9 @@
 /*
 * Reserved. Return zeroes on reads.
 */
-#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_DEFVAL 
-#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_SHIFT 
-#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_MASK 
+#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_DEFVAL
+#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_SHIFT
+#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_MASK
 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_DEFVAL             0x00000000
 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_SHIFT              10
 #define DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_MASK               0x00001C00U
@@ -21540,9 +21540,9 @@
 /*
 * Data Slew Rate
 */
-#undef DDR_PHY_DX8SLBDQSCTL_DXSR_DEFVAL 
-#undef DDR_PHY_DX8SLBDQSCTL_DXSR_SHIFT 
-#undef DDR_PHY_DX8SLBDQSCTL_DXSR_MASK 
+#undef DDR_PHY_DX8SLBDQSCTL_DXSR_DEFVAL
+#undef DDR_PHY_DX8SLBDQSCTL_DXSR_SHIFT
+#undef DDR_PHY_DX8SLBDQSCTL_DXSR_MASK
 #define DDR_PHY_DX8SLBDQSCTL_DXSR_DEFVAL                       0x00000000
 #define DDR_PHY_DX8SLBDQSCTL_DXSR_SHIFT                        8
 #define DDR_PHY_DX8SLBDQSCTL_DXSR_MASK                         0x00000300U
@@ -21550,9 +21550,9 @@
 /*
 * DQS# Resistor
 */
-#undef DDR_PHY_DX8SLBDQSCTL_DQSNRES_DEFVAL 
-#undef DDR_PHY_DX8SLBDQSCTL_DQSNRES_SHIFT 
-#undef DDR_PHY_DX8SLBDQSCTL_DQSNRES_MASK 
+#undef DDR_PHY_DX8SLBDQSCTL_DQSNRES_DEFVAL
+#undef DDR_PHY_DX8SLBDQSCTL_DQSNRES_SHIFT
+#undef DDR_PHY_DX8SLBDQSCTL_DQSNRES_MASK
 #define DDR_PHY_DX8SLBDQSCTL_DQSNRES_DEFVAL                    0x00000000
 #define DDR_PHY_DX8SLBDQSCTL_DQSNRES_SHIFT                     4
 #define DDR_PHY_DX8SLBDQSCTL_DQSNRES_MASK                      0x000000F0U
@@ -21560,166 +21560,166 @@
 /*
 * DQS Resistor
 */
-#undef DDR_PHY_DX8SLBDQSCTL_DQSRES_DEFVAL 
-#undef DDR_PHY_DX8SLBDQSCTL_DQSRES_SHIFT 
-#undef DDR_PHY_DX8SLBDQSCTL_DQSRES_MASK 
+#undef DDR_PHY_DX8SLBDQSCTL_DQSRES_DEFVAL
+#undef DDR_PHY_DX8SLBDQSCTL_DQSRES_SHIFT
+#undef DDR_PHY_DX8SLBDQSCTL_DQSRES_MASK
 #define DDR_PHY_DX8SLBDQSCTL_DQSRES_DEFVAL                     0x00000000
 #define DDR_PHY_DX8SLBDQSCTL_DQSRES_SHIFT                      0
 #define DDR_PHY_DX8SLBDQSCTL_DQSRES_MASK                       0x0000000FU
-#undef IOU_SLCR_MIO_PIN_0_OFFSET 
+#undef IOU_SLCR_MIO_PIN_0_OFFSET
 #define IOU_SLCR_MIO_PIN_0_OFFSET                                                  0XFF180000
-#undef IOU_SLCR_MIO_PIN_1_OFFSET 
+#undef IOU_SLCR_MIO_PIN_1_OFFSET
 #define IOU_SLCR_MIO_PIN_1_OFFSET                                                  0XFF180004
-#undef IOU_SLCR_MIO_PIN_2_OFFSET 
+#undef IOU_SLCR_MIO_PIN_2_OFFSET
 #define IOU_SLCR_MIO_PIN_2_OFFSET                                                  0XFF180008
-#undef IOU_SLCR_MIO_PIN_3_OFFSET 
+#undef IOU_SLCR_MIO_PIN_3_OFFSET
 #define IOU_SLCR_MIO_PIN_3_OFFSET                                                  0XFF18000C
-#undef IOU_SLCR_MIO_PIN_4_OFFSET 
+#undef IOU_SLCR_MIO_PIN_4_OFFSET
 #define IOU_SLCR_MIO_PIN_4_OFFSET                                                  0XFF180010
-#undef IOU_SLCR_MIO_PIN_5_OFFSET 
+#undef IOU_SLCR_MIO_PIN_5_OFFSET
 #define IOU_SLCR_MIO_PIN_5_OFFSET                                                  0XFF180014
-#undef IOU_SLCR_MIO_PIN_16_OFFSET 
+#undef IOU_SLCR_MIO_PIN_16_OFFSET
 #define IOU_SLCR_MIO_PIN_16_OFFSET                                                 0XFF180040
-#undef IOU_SLCR_MIO_PIN_17_OFFSET 
+#undef IOU_SLCR_MIO_PIN_17_OFFSET
 #define IOU_SLCR_MIO_PIN_17_OFFSET                                                 0XFF180044
-#undef IOU_SLCR_MIO_PIN_18_OFFSET 
+#undef IOU_SLCR_MIO_PIN_18_OFFSET
 #define IOU_SLCR_MIO_PIN_18_OFFSET                                                 0XFF180048
-#undef IOU_SLCR_MIO_PIN_19_OFFSET 
+#undef IOU_SLCR_MIO_PIN_19_OFFSET
 #define IOU_SLCR_MIO_PIN_19_OFFSET                                                 0XFF18004C
-#undef IOU_SLCR_MIO_PIN_20_OFFSET 
+#undef IOU_SLCR_MIO_PIN_20_OFFSET
 #define IOU_SLCR_MIO_PIN_20_OFFSET                                                 0XFF180050
-#undef IOU_SLCR_MIO_PIN_21_OFFSET 
+#undef IOU_SLCR_MIO_PIN_21_OFFSET
 #define IOU_SLCR_MIO_PIN_21_OFFSET                                                 0XFF180054
-#undef IOU_SLCR_MIO_PIN_24_OFFSET 
+#undef IOU_SLCR_MIO_PIN_24_OFFSET
 #define IOU_SLCR_MIO_PIN_24_OFFSET                                                 0XFF180060
-#undef IOU_SLCR_MIO_PIN_25_OFFSET 
+#undef IOU_SLCR_MIO_PIN_25_OFFSET
 #define IOU_SLCR_MIO_PIN_25_OFFSET                                                 0XFF180064
-#undef IOU_SLCR_MIO_PIN_27_OFFSET 
+#undef IOU_SLCR_MIO_PIN_27_OFFSET
 #define IOU_SLCR_MIO_PIN_27_OFFSET                                                 0XFF18006C
-#undef IOU_SLCR_MIO_PIN_28_OFFSET 
+#undef IOU_SLCR_MIO_PIN_28_OFFSET
 #define IOU_SLCR_MIO_PIN_28_OFFSET                                                 0XFF180070
-#undef IOU_SLCR_MIO_PIN_29_OFFSET 
+#undef IOU_SLCR_MIO_PIN_29_OFFSET
 #define IOU_SLCR_MIO_PIN_29_OFFSET                                                 0XFF180074
-#undef IOU_SLCR_MIO_PIN_30_OFFSET 
+#undef IOU_SLCR_MIO_PIN_30_OFFSET
 #define IOU_SLCR_MIO_PIN_30_OFFSET                                                 0XFF180078
-#undef IOU_SLCR_MIO_PIN_45_OFFSET 
+#undef IOU_SLCR_MIO_PIN_45_OFFSET
 #define IOU_SLCR_MIO_PIN_45_OFFSET                                                 0XFF1800B4
-#undef IOU_SLCR_MIO_PIN_46_OFFSET 
+#undef IOU_SLCR_MIO_PIN_46_OFFSET
 #define IOU_SLCR_MIO_PIN_46_OFFSET                                                 0XFF1800B8
-#undef IOU_SLCR_MIO_PIN_47_OFFSET 
+#undef IOU_SLCR_MIO_PIN_47_OFFSET
 #define IOU_SLCR_MIO_PIN_47_OFFSET                                                 0XFF1800BC
-#undef IOU_SLCR_MIO_PIN_48_OFFSET 
+#undef IOU_SLCR_MIO_PIN_48_OFFSET
 #define IOU_SLCR_MIO_PIN_48_OFFSET                                                 0XFF1800C0
-#undef IOU_SLCR_MIO_PIN_49_OFFSET 
+#undef IOU_SLCR_MIO_PIN_49_OFFSET
 #define IOU_SLCR_MIO_PIN_49_OFFSET                                                 0XFF1800C4
-#undef IOU_SLCR_MIO_PIN_50_OFFSET 
+#undef IOU_SLCR_MIO_PIN_50_OFFSET
 #define IOU_SLCR_MIO_PIN_50_OFFSET                                                 0XFF1800C8
-#undef IOU_SLCR_MIO_PIN_51_OFFSET 
+#undef IOU_SLCR_MIO_PIN_51_OFFSET
 #define IOU_SLCR_MIO_PIN_51_OFFSET                                                 0XFF1800CC
-#undef IOU_SLCR_MIO_PIN_52_OFFSET 
+#undef IOU_SLCR_MIO_PIN_52_OFFSET
 #define IOU_SLCR_MIO_PIN_52_OFFSET                                                 0XFF1800D0
-#undef IOU_SLCR_MIO_PIN_53_OFFSET 
+#undef IOU_SLCR_MIO_PIN_53_OFFSET
 #define IOU_SLCR_MIO_PIN_53_OFFSET                                                 0XFF1800D4
-#undef IOU_SLCR_MIO_PIN_54_OFFSET 
+#undef IOU_SLCR_MIO_PIN_54_OFFSET
 #define IOU_SLCR_MIO_PIN_54_OFFSET                                                 0XFF1800D8
-#undef IOU_SLCR_MIO_PIN_55_OFFSET 
+#undef IOU_SLCR_MIO_PIN_55_OFFSET
 #define IOU_SLCR_MIO_PIN_55_OFFSET                                                 0XFF1800DC
-#undef IOU_SLCR_MIO_PIN_56_OFFSET 
+#undef IOU_SLCR_MIO_PIN_56_OFFSET
 #define IOU_SLCR_MIO_PIN_56_OFFSET                                                 0XFF1800E0
-#undef IOU_SLCR_MIO_PIN_57_OFFSET 
+#undef IOU_SLCR_MIO_PIN_57_OFFSET
 #define IOU_SLCR_MIO_PIN_57_OFFSET                                                 0XFF1800E4
-#undef IOU_SLCR_MIO_PIN_58_OFFSET 
+#undef IOU_SLCR_MIO_PIN_58_OFFSET
 #define IOU_SLCR_MIO_PIN_58_OFFSET                                                 0XFF1800E8
-#undef IOU_SLCR_MIO_PIN_59_OFFSET 
+#undef IOU_SLCR_MIO_PIN_59_OFFSET
 #define IOU_SLCR_MIO_PIN_59_OFFSET                                                 0XFF1800EC
-#undef IOU_SLCR_MIO_PIN_60_OFFSET 
+#undef IOU_SLCR_MIO_PIN_60_OFFSET
 #define IOU_SLCR_MIO_PIN_60_OFFSET                                                 0XFF1800F0
-#undef IOU_SLCR_MIO_PIN_61_OFFSET 
+#undef IOU_SLCR_MIO_PIN_61_OFFSET
 #define IOU_SLCR_MIO_PIN_61_OFFSET                                                 0XFF1800F4
-#undef IOU_SLCR_MIO_PIN_62_OFFSET 
+#undef IOU_SLCR_MIO_PIN_62_OFFSET
 #define IOU_SLCR_MIO_PIN_62_OFFSET                                                 0XFF1800F8
-#undef IOU_SLCR_MIO_PIN_63_OFFSET 
+#undef IOU_SLCR_MIO_PIN_63_OFFSET
 #define IOU_SLCR_MIO_PIN_63_OFFSET                                                 0XFF1800FC
-#undef IOU_SLCR_MIO_PIN_64_OFFSET 
+#undef IOU_SLCR_MIO_PIN_64_OFFSET
 #define IOU_SLCR_MIO_PIN_64_OFFSET                                                 0XFF180100
-#undef IOU_SLCR_MIO_PIN_65_OFFSET 
+#undef IOU_SLCR_MIO_PIN_65_OFFSET
 #define IOU_SLCR_MIO_PIN_65_OFFSET                                                 0XFF180104
-#undef IOU_SLCR_MIO_PIN_66_OFFSET 
+#undef IOU_SLCR_MIO_PIN_66_OFFSET
 #define IOU_SLCR_MIO_PIN_66_OFFSET                                                 0XFF180108
-#undef IOU_SLCR_MIO_PIN_67_OFFSET 
+#undef IOU_SLCR_MIO_PIN_67_OFFSET
 #define IOU_SLCR_MIO_PIN_67_OFFSET                                                 0XFF18010C
-#undef IOU_SLCR_MIO_PIN_68_OFFSET 
+#undef IOU_SLCR_MIO_PIN_68_OFFSET
 #define IOU_SLCR_MIO_PIN_68_OFFSET                                                 0XFF180110
-#undef IOU_SLCR_MIO_PIN_69_OFFSET 
+#undef IOU_SLCR_MIO_PIN_69_OFFSET
 #define IOU_SLCR_MIO_PIN_69_OFFSET                                                 0XFF180114
-#undef IOU_SLCR_MIO_PIN_70_OFFSET 
+#undef IOU_SLCR_MIO_PIN_70_OFFSET
 #define IOU_SLCR_MIO_PIN_70_OFFSET                                                 0XFF180118
-#undef IOU_SLCR_MIO_PIN_71_OFFSET 
+#undef IOU_SLCR_MIO_PIN_71_OFFSET
 #define IOU_SLCR_MIO_PIN_71_OFFSET                                                 0XFF18011C
-#undef IOU_SLCR_MIO_PIN_72_OFFSET 
+#undef IOU_SLCR_MIO_PIN_72_OFFSET
 #define IOU_SLCR_MIO_PIN_72_OFFSET                                                 0XFF180120
-#undef IOU_SLCR_MIO_PIN_73_OFFSET 
+#undef IOU_SLCR_MIO_PIN_73_OFFSET
 #define IOU_SLCR_MIO_PIN_73_OFFSET                                                 0XFF180124
-#undef IOU_SLCR_MIO_PIN_74_OFFSET 
+#undef IOU_SLCR_MIO_PIN_74_OFFSET
 #define IOU_SLCR_MIO_PIN_74_OFFSET                                                 0XFF180128
-#undef IOU_SLCR_MIO_PIN_75_OFFSET 
+#undef IOU_SLCR_MIO_PIN_75_OFFSET
 #define IOU_SLCR_MIO_PIN_75_OFFSET                                                 0XFF18012C
-#undef IOU_SLCR_MIO_PIN_76_OFFSET 
+#undef IOU_SLCR_MIO_PIN_76_OFFSET
 #define IOU_SLCR_MIO_PIN_76_OFFSET                                                 0XFF180130
-#undef IOU_SLCR_MIO_PIN_77_OFFSET 
+#undef IOU_SLCR_MIO_PIN_77_OFFSET
 #define IOU_SLCR_MIO_PIN_77_OFFSET                                                 0XFF180134
-#undef IOU_SLCR_MIO_MST_TRI0_OFFSET 
+#undef IOU_SLCR_MIO_MST_TRI0_OFFSET
 #define IOU_SLCR_MIO_MST_TRI0_OFFSET                                               0XFF180204
-#undef IOU_SLCR_MIO_MST_TRI1_OFFSET 
+#undef IOU_SLCR_MIO_MST_TRI1_OFFSET
 #define IOU_SLCR_MIO_MST_TRI1_OFFSET                                               0XFF180208
-#undef IOU_SLCR_MIO_MST_TRI2_OFFSET 
+#undef IOU_SLCR_MIO_MST_TRI2_OFFSET
 #define IOU_SLCR_MIO_MST_TRI2_OFFSET                                               0XFF18020C
-#undef IOU_SLCR_BANK0_CTRL0_OFFSET 
+#undef IOU_SLCR_BANK0_CTRL0_OFFSET
 #define IOU_SLCR_BANK0_CTRL0_OFFSET                                                0XFF180138
-#undef IOU_SLCR_BANK0_CTRL1_OFFSET 
+#undef IOU_SLCR_BANK0_CTRL1_OFFSET
 #define IOU_SLCR_BANK0_CTRL1_OFFSET                                                0XFF18013C
-#undef IOU_SLCR_BANK0_CTRL3_OFFSET 
+#undef IOU_SLCR_BANK0_CTRL3_OFFSET
 #define IOU_SLCR_BANK0_CTRL3_OFFSET                                                0XFF180140
-#undef IOU_SLCR_BANK0_CTRL4_OFFSET 
+#undef IOU_SLCR_BANK0_CTRL4_OFFSET
 #define IOU_SLCR_BANK0_CTRL4_OFFSET                                                0XFF180144
-#undef IOU_SLCR_BANK0_CTRL5_OFFSET 
+#undef IOU_SLCR_BANK0_CTRL5_OFFSET
 #define IOU_SLCR_BANK0_CTRL5_OFFSET                                                0XFF180148
-#undef IOU_SLCR_BANK0_CTRL6_OFFSET 
+#undef IOU_SLCR_BANK0_CTRL6_OFFSET
 #define IOU_SLCR_BANK0_CTRL6_OFFSET                                                0XFF18014C
-#undef IOU_SLCR_BANK1_CTRL0_OFFSET 
+#undef IOU_SLCR_BANK1_CTRL0_OFFSET
 #define IOU_SLCR_BANK1_CTRL0_OFFSET                                                0XFF180154
-#undef IOU_SLCR_BANK1_CTRL1_OFFSET 
+#undef IOU_SLCR_BANK1_CTRL1_OFFSET
 #define IOU_SLCR_BANK1_CTRL1_OFFSET                                                0XFF180158
-#undef IOU_SLCR_BANK1_CTRL3_OFFSET 
+#undef IOU_SLCR_BANK1_CTRL3_OFFSET
 #define IOU_SLCR_BANK1_CTRL3_OFFSET                                                0XFF18015C
-#undef IOU_SLCR_BANK1_CTRL4_OFFSET 
+#undef IOU_SLCR_BANK1_CTRL4_OFFSET
 #define IOU_SLCR_BANK1_CTRL4_OFFSET                                                0XFF180160
-#undef IOU_SLCR_BANK1_CTRL5_OFFSET 
+#undef IOU_SLCR_BANK1_CTRL5_OFFSET
 #define IOU_SLCR_BANK1_CTRL5_OFFSET                                                0XFF180164
-#undef IOU_SLCR_BANK1_CTRL6_OFFSET 
+#undef IOU_SLCR_BANK1_CTRL6_OFFSET
 #define IOU_SLCR_BANK1_CTRL6_OFFSET                                                0XFF180168
-#undef IOU_SLCR_BANK2_CTRL0_OFFSET 
+#undef IOU_SLCR_BANK2_CTRL0_OFFSET
 #define IOU_SLCR_BANK2_CTRL0_OFFSET                                                0XFF180170
-#undef IOU_SLCR_BANK2_CTRL1_OFFSET 
+#undef IOU_SLCR_BANK2_CTRL1_OFFSET
 #define IOU_SLCR_BANK2_CTRL1_OFFSET                                                0XFF180174
-#undef IOU_SLCR_BANK2_CTRL3_OFFSET 
+#undef IOU_SLCR_BANK2_CTRL3_OFFSET
 #define IOU_SLCR_BANK2_CTRL3_OFFSET                                                0XFF180178
-#undef IOU_SLCR_BANK2_CTRL4_OFFSET 
+#undef IOU_SLCR_BANK2_CTRL4_OFFSET
 #define IOU_SLCR_BANK2_CTRL4_OFFSET                                                0XFF18017C
-#undef IOU_SLCR_BANK2_CTRL5_OFFSET 
+#undef IOU_SLCR_BANK2_CTRL5_OFFSET
 #define IOU_SLCR_BANK2_CTRL5_OFFSET                                                0XFF180180
-#undef IOU_SLCR_BANK2_CTRL6_OFFSET 
+#undef IOU_SLCR_BANK2_CTRL6_OFFSET
 #define IOU_SLCR_BANK2_CTRL6_OFFSET                                                0XFF180184
-#undef IOU_SLCR_MIO_LOOPBACK_OFFSET 
+#undef IOU_SLCR_MIO_LOOPBACK_OFFSET
 #define IOU_SLCR_MIO_LOOPBACK_OFFSET                                               0XFF180200
 
 /*
 * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out-
     *  (QSPI Clock)
 */
-#undef IOU_SLCR_MIO_PIN_0_L0_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_0_L0_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_0_L0_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_0_L0_SEL_MASK
 #define IOU_SLCR_MIO_PIN_0_L0_SEL_DEFVAL                       0x00000000
 #define IOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT                        1
 #define IOU_SLCR_MIO_PIN_0_L0_SEL_MASK                         0x00000002U
@@ -21727,9 +21727,9 @@
 /*
 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_0_L1_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_0_L1_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_0_L1_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_0_L1_SEL_MASK
 #define IOU_SLCR_MIO_PIN_0_L1_SEL_DEFVAL                       0x00000000
 #define IOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT                        2
 #define IOU_SLCR_MIO_PIN_0_L1_SEL_MASK                         0x00000004U
@@ -21739,9 +21739,9 @@
     * , test_scan_in[0]- (Test Scan Port) = test_scan, Output, test_scan_out[0
     * ]- (Test Scan Port) 3= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_0_L2_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_0_L2_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_0_L2_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_0_L2_SEL_MASK
 #define IOU_SLCR_MIO_PIN_0_L2_SEL_DEFVAL                       0x00000000
 #define IOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT                        3
 #define IOU_SLCR_MIO_PIN_0_L2_SEL_MASK                         0x00000018U
@@ -21756,9 +21756,9 @@
     * put, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_c
     * lk- (Trace Port Clock)
 */
-#undef IOU_SLCR_MIO_PIN_0_L3_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_0_L3_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_0_L3_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_0_L3_SEL_MASK
 #define IOU_SLCR_MIO_PIN_0_L3_SEL_DEFVAL                       0x00000000
 #define IOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT                        5
 #define IOU_SLCR_MIO_PIN_0_L3_SEL_MASK                         0x000000E0U
@@ -21767,9 +21767,9 @@
 * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (Q
     * SPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus)
 */
-#undef IOU_SLCR_MIO_PIN_1_L0_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_1_L0_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_1_L0_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_1_L0_SEL_MASK
 #define IOU_SLCR_MIO_PIN_1_L0_SEL_DEFVAL                       0x00000000
 #define IOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT                        1
 #define IOU_SLCR_MIO_PIN_1_L0_SEL_MASK                         0x00000002U
@@ -21777,9 +21777,9 @@
 /*
 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_1_L1_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_1_L1_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_1_L1_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_1_L1_SEL_MASK
 #define IOU_SLCR_MIO_PIN_1_L1_SEL_DEFVAL                       0x00000000
 #define IOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT                        2
 #define IOU_SLCR_MIO_PIN_1_L1_SEL_MASK                         0x00000004U
@@ -21789,9 +21789,9 @@
     * , test_scan_in[1]- (Test Scan Port) = test_scan, Output, test_scan_out[1
     * ]- (Test Scan Port) 3= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_1_L2_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_1_L2_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_1_L2_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_1_L2_SEL_MASK
 #define IOU_SLCR_MIO_PIN_1_L2_SEL_DEFVAL                       0x00000000
 #define IOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT                        3
 #define IOU_SLCR_MIO_PIN_1_L2_SEL_MASK                         0x00000018U
@@ -21806,9 +21806,9 @@
     * receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control
     * Signal)
 */
-#undef IOU_SLCR_MIO_PIN_1_L3_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_1_L3_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_1_L3_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_1_L3_SEL_MASK
 #define IOU_SLCR_MIO_PIN_1_L3_SEL_DEFVAL                       0x00000000
 #define IOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT                        5
 #define IOU_SLCR_MIO_PIN_1_L3_SEL_MASK                         0x000000E0U
@@ -21817,9 +21817,9 @@
 * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI
     *  Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus)
 */
-#undef IOU_SLCR_MIO_PIN_2_L0_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_2_L0_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_2_L0_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_2_L0_SEL_MASK
 #define IOU_SLCR_MIO_PIN_2_L0_SEL_DEFVAL                       0x00000000
 #define IOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT                        1
 #define IOU_SLCR_MIO_PIN_2_L0_SEL_MASK                         0x00000002U
@@ -21827,9 +21827,9 @@
 /*
 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_2_L1_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_2_L1_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_2_L1_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_2_L1_SEL_MASK
 #define IOU_SLCR_MIO_PIN_2_L1_SEL_DEFVAL                       0x00000000
 #define IOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT                        2
 #define IOU_SLCR_MIO_PIN_2_L1_SEL_MASK                         0x00000004U
@@ -21839,9 +21839,9 @@
     * , test_scan_in[2]- (Test Scan Port) = test_scan, Output, test_scan_out[2
     * ]- (Test Scan Port) 3= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_2_L2_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_2_L2_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_2_L2_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_2_L2_SEL_MASK
 #define IOU_SLCR_MIO_PIN_2_L2_SEL_DEFVAL                       0x00000000
 #define IOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT                        3
 #define IOU_SLCR_MIO_PIN_2_L2_SEL_MASK                         0x00000018U
@@ -21855,9 +21855,9 @@
     * nput, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver se
     * rial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)
 */
-#undef IOU_SLCR_MIO_PIN_2_L3_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_2_L3_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_2_L3_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_2_L3_SEL_MASK
 #define IOU_SLCR_MIO_PIN_2_L3_SEL_DEFVAL                       0x00000000
 #define IOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT                        5
 #define IOU_SLCR_MIO_PIN_2_L3_SEL_MASK                         0x000000E0U
@@ -21866,9 +21866,9 @@
 * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI
     *  Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus)
 */
-#undef IOU_SLCR_MIO_PIN_3_L0_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_3_L0_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_3_L0_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_3_L0_SEL_MASK
 #define IOU_SLCR_MIO_PIN_3_L0_SEL_DEFVAL                       0x00000000
 #define IOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT                        1
 #define IOU_SLCR_MIO_PIN_3_L0_SEL_MASK                         0x00000002U
@@ -21876,9 +21876,9 @@
 /*
 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_3_L1_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_3_L1_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_3_L1_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_3_L1_SEL_MASK
 #define IOU_SLCR_MIO_PIN_3_L1_SEL_DEFVAL                       0x00000000
 #define IOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT                        2
 #define IOU_SLCR_MIO_PIN_3_L1_SEL_MASK                         0x00000004U
@@ -21888,9 +21888,9 @@
     * , test_scan_in[3]- (Test Scan Port) = test_scan, Output, test_scan_out[3
     * ]- (Test Scan Port) 3= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_3_L2_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_3_L2_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_3_L2_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_3_L2_SEL_MASK
 #define IOU_SLCR_MIO_PIN_3_L2_SEL_DEFVAL                       0x00000000
 #define IOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT                        3
 #define IOU_SLCR_MIO_PIN_3_L2_SEL_MASK                         0x00000018U
@@ -21905,9 +21905,9 @@
     *  (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial
     * output) 7= trace, Output, tracedq[1]- (Trace Port Databus)
 */
-#undef IOU_SLCR_MIO_PIN_3_L3_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_3_L3_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_3_L3_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_3_L3_SEL_MASK
 #define IOU_SLCR_MIO_PIN_3_L3_SEL_DEFVAL                       0x00000000
 #define IOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT                        5
 #define IOU_SLCR_MIO_PIN_3_L3_SEL_MASK                         0x000000E0U
@@ -21916,9 +21916,9 @@
 * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (
     * QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus)
 */
-#undef IOU_SLCR_MIO_PIN_4_L0_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_4_L0_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_4_L0_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_4_L0_SEL_MASK
 #define IOU_SLCR_MIO_PIN_4_L0_SEL_DEFVAL                       0x00000000
 #define IOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT                        1
 #define IOU_SLCR_MIO_PIN_4_L0_SEL_MASK                         0x00000002U
@@ -21926,9 +21926,9 @@
 /*
 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_4_L1_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_4_L1_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_4_L1_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_4_L1_SEL_MASK
 #define IOU_SLCR_MIO_PIN_4_L1_SEL_DEFVAL                       0x00000000
 #define IOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT                        2
 #define IOU_SLCR_MIO_PIN_4_L1_SEL_MASK                         0x00000004U
@@ -21938,9 +21938,9 @@
     * , test_scan_in[4]- (Test Scan Port) = test_scan, Output, test_scan_out[4
     * ]- (Test Scan Port) 3= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_4_L2_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_4_L2_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_4_L2_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_4_L2_SEL_MASK
 #define IOU_SLCR_MIO_PIN_4_L2_SEL_DEFVAL                       0x00000000
 #define IOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT                        3
 #define IOU_SLCR_MIO_PIN_4_L2_SEL_MASK                         0x00000018U
@@ -21955,9 +21955,9 @@
     * k) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, O
     * utput, tracedq[2]- (Trace Port Databus)
 */
-#undef IOU_SLCR_MIO_PIN_4_L3_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_4_L3_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_4_L3_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_4_L3_SEL_MASK
 #define IOU_SLCR_MIO_PIN_4_L3_SEL_DEFVAL                       0x00000000
 #define IOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT                        5
 #define IOU_SLCR_MIO_PIN_4_L3_SEL_MASK                         0x000000E0U
@@ -21966,9 +21966,9 @@
 * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out-
     *  (QSPI Slave Select)
 */
-#undef IOU_SLCR_MIO_PIN_5_L0_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_5_L0_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_5_L0_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_5_L0_SEL_MASK
 #define IOU_SLCR_MIO_PIN_5_L0_SEL_DEFVAL                       0x00000000
 #define IOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT                        1
 #define IOU_SLCR_MIO_PIN_5_L0_SEL_MASK                         0x00000002U
@@ -21976,9 +21976,9 @@
 /*
 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_5_L1_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_5_L1_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_5_L1_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_5_L1_SEL_MASK
 #define IOU_SLCR_MIO_PIN_5_L1_SEL_DEFVAL                       0x00000000
 #define IOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT                        2
 #define IOU_SLCR_MIO_PIN_5_L1_SEL_MASK                         0x00000004U
@@ -21988,9 +21988,9 @@
     * , test_scan_in[5]- (Test Scan Port) = test_scan, Output, test_scan_out[5
     * ]- (Test Scan Port) 3= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_5_L2_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_5_L2_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_5_L2_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_5_L2_SEL_MASK
 #define IOU_SLCR_MIO_PIN_5_L2_SEL_DEFVAL                       0x00000000
 #define IOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT                        3
 #define IOU_SLCR_MIO_PIN_5_L2_SEL_MASK                         0x00000018U
@@ -22005,9 +22005,9 @@
     *  Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7=
     *  trace, Output, tracedq[3]- (Trace Port Databus)
 */
-#undef IOU_SLCR_MIO_PIN_5_L3_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_5_L3_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_5_L3_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_5_L3_SEL_MASK
 #define IOU_SLCR_MIO_PIN_5_L3_SEL_DEFVAL                       0x00000000
 #define IOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT                        5
 #define IOU_SLCR_MIO_PIN_5_L3_SEL_MASK                         0x000000E0U
@@ -22015,9 +22015,9 @@
 /*
 * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_16_L0_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_16_L0_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_16_L0_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_16_L0_SEL_MASK
 #define IOU_SLCR_MIO_PIN_16_L0_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT                       1
 #define IOU_SLCR_MIO_PIN_16_L0_SEL_MASK                        0x00000002U
@@ -22026,9 +22026,9 @@
 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[0]- (
     * NAND Data Bus) 1= nand, Output, nfc_dq_out[0]- (NAND Data Bus)
 */
-#undef IOU_SLCR_MIO_PIN_16_L1_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_16_L1_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_16_L1_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_16_L1_SEL_MASK
 #define IOU_SLCR_MIO_PIN_16_L1_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT                       2
 #define IOU_SLCR_MIO_PIN_16_L1_SEL_MASK                        0x00000004U
@@ -22039,9 +22039,9 @@
     * est_scan, Input, test_scan_in[16]- (Test Scan Port) = test_scan, Output,
     *  test_scan_out[16]- (Test Scan Port) 3= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_16_L2_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_16_L2_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_16_L2_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_16_L2_SEL_MASK
 #define IOU_SLCR_MIO_PIN_16_L2_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT                       3
 #define IOU_SLCR_MIO_PIN_16_L2_SEL_MASK                        0x00000018U
@@ -22056,9 +22056,9 @@
     * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace,
     *  Output, tracedq[14]- (Trace Port Databus)
 */
-#undef IOU_SLCR_MIO_PIN_16_L3_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_16_L3_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_16_L3_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_16_L3_SEL_MASK
 #define IOU_SLCR_MIO_PIN_16_L3_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT                       5
 #define IOU_SLCR_MIO_PIN_16_L3_SEL_MASK                        0x000000E0U
@@ -22066,9 +22066,9 @@
 /*
 * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_17_L0_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_17_L0_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_17_L0_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_17_L0_SEL_MASK
 #define IOU_SLCR_MIO_PIN_17_L0_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT                       1
 #define IOU_SLCR_MIO_PIN_17_L0_SEL_MASK                        0x00000002U
@@ -22077,9 +22077,9 @@
 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[1]- (
     * NAND Data Bus) 1= nand, Output, nfc_dq_out[1]- (NAND Data Bus)
 */
-#undef IOU_SLCR_MIO_PIN_17_L1_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_17_L1_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_17_L1_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_17_L1_SEL_MASK
 #define IOU_SLCR_MIO_PIN_17_L1_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT                       2
 #define IOU_SLCR_MIO_PIN_17_L1_SEL_MASK                        0x00000004U
@@ -22090,9 +22090,9 @@
     * est_scan, Input, test_scan_in[17]- (Test Scan Port) = test_scan, Output,
     *  test_scan_out[17]- (Test Scan Port) 3= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_17_L2_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_17_L2_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_17_L2_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_17_L2_SEL_MASK
 #define IOU_SLCR_MIO_PIN_17_L2_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT                       3
 #define IOU_SLCR_MIO_PIN_17_L2_SEL_MASK                        0x00000018U
@@ -22107,9 +22107,9 @@
     * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
     * 7= trace, Output, tracedq[15]- (Trace Port Databus)
 */
-#undef IOU_SLCR_MIO_PIN_17_L3_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_17_L3_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_17_L3_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_17_L3_SEL_MASK
 #define IOU_SLCR_MIO_PIN_17_L3_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT                       5
 #define IOU_SLCR_MIO_PIN_17_L3_SEL_MASK                        0x000000E0U
@@ -22117,9 +22117,9 @@
 /*
 * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_18_L0_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_18_L0_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_18_L0_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_18_L0_SEL_MASK
 #define IOU_SLCR_MIO_PIN_18_L0_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT                       1
 #define IOU_SLCR_MIO_PIN_18_L0_SEL_MASK                        0x00000002U
@@ -22128,9 +22128,9 @@
 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[2]- (
     * NAND Data Bus) 1= nand, Output, nfc_dq_out[2]- (NAND Data Bus)
 */
-#undef IOU_SLCR_MIO_PIN_18_L1_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_18_L1_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_18_L1_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_18_L1_SEL_MASK
 #define IOU_SLCR_MIO_PIN_18_L1_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT                       2
 #define IOU_SLCR_MIO_PIN_18_L1_SEL_MASK                        0x00000004U
@@ -22142,9 +22142,9 @@
     *  test_scan_out[18]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU
     *  Ext Tamper)
 */
-#undef IOU_SLCR_MIO_PIN_18_L2_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_18_L2_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_18_L2_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_18_L2_SEL_MASK
 #define IOU_SLCR_MIO_PIN_18_L2_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT                       3
 #define IOU_SLCR_MIO_PIN_18_L2_SEL_MASK                        0x00000018U
@@ -22158,9 +22158,9 @@
     * i1, Output, spi1_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo
     * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_18_L3_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_18_L3_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_18_L3_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_18_L3_SEL_MASK
 #define IOU_SLCR_MIO_PIN_18_L3_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT                       5
 #define IOU_SLCR_MIO_PIN_18_L3_SEL_MASK                        0x000000E0U
@@ -22168,9 +22168,9 @@
 /*
 * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_19_L0_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_19_L0_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_19_L0_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_19_L0_SEL_MASK
 #define IOU_SLCR_MIO_PIN_19_L0_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT                       1
 #define IOU_SLCR_MIO_PIN_19_L0_SEL_MASK                        0x00000002U
@@ -22179,9 +22179,9 @@
 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[3]- (
     * NAND Data Bus) 1= nand, Output, nfc_dq_out[3]- (NAND Data Bus)
 */
-#undef IOU_SLCR_MIO_PIN_19_L1_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_19_L1_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_19_L1_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_19_L1_SEL_MASK
 #define IOU_SLCR_MIO_PIN_19_L1_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT                       2
 #define IOU_SLCR_MIO_PIN_19_L1_SEL_MASK                        0x00000004U
@@ -22193,9 +22193,9 @@
     *  test_scan_out[19]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU
     *  Ext Tamper)
 */
-#undef IOU_SLCR_MIO_PIN_19_L2_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_19_L2_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_19_L2_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_19_L2_SEL_MASK
 #define IOU_SLCR_MIO_PIN_19_L2_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT                       3
 #define IOU_SLCR_MIO_PIN_19_L2_SEL_MASK                        0x00000018U
@@ -22209,9 +22209,9 @@
     * Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6=
     * ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_19_L3_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_19_L3_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_19_L3_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_19_L3_SEL_MASK
 #define IOU_SLCR_MIO_PIN_19_L3_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT                       5
 #define IOU_SLCR_MIO_PIN_19_L3_SEL_MASK                        0x000000E0U
@@ -22219,9 +22219,9 @@
 /*
 * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_20_L0_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_20_L0_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_20_L0_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_20_L0_SEL_MASK
 #define IOU_SLCR_MIO_PIN_20_L0_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT                       1
 #define IOU_SLCR_MIO_PIN_20_L0_SEL_MASK                        0x00000002U
@@ -22230,9 +22230,9 @@
 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[4]- (
     * NAND Data Bus) 1= nand, Output, nfc_dq_out[4]- (NAND Data Bus)
 */
-#undef IOU_SLCR_MIO_PIN_20_L1_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_20_L1_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_20_L1_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_20_L1_SEL_MASK
 #define IOU_SLCR_MIO_PIN_20_L1_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT                       2
 #define IOU_SLCR_MIO_PIN_20_L1_SEL_MASK                        0x00000004U
@@ -22244,9 +22244,9 @@
     *  test_scan_out[20]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU
     *  Ext Tamper)
 */
-#undef IOU_SLCR_MIO_PIN_20_L2_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_20_L2_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_20_L2_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_20_L2_SEL_MASK
 #define IOU_SLCR_MIO_PIN_20_L2_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT                       3
 #define IOU_SLCR_MIO_PIN_20_L2_SEL_MASK                        0x00000018U
@@ -22260,9 +22260,9 @@
     * ter Selects) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua
     * 1_txd- (UART transmitter serial output) 7= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_20_L3_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_20_L3_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_20_L3_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_20_L3_SEL_MASK
 #define IOU_SLCR_MIO_PIN_20_L3_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT                       5
 #define IOU_SLCR_MIO_PIN_20_L3_SEL_MASK                        0x000000E0U
@@ -22270,9 +22270,9 @@
 /*
 * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_21_L0_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_21_L0_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_21_L0_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_21_L0_SEL_MASK
 #define IOU_SLCR_MIO_PIN_21_L0_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT                       1
 #define IOU_SLCR_MIO_PIN_21_L0_SEL_MASK                        0x00000002U
@@ -22281,9 +22281,9 @@
 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[5]- (
     * NAND Data Bus) 1= nand, Output, nfc_dq_out[5]- (NAND Data Bus)
 */
-#undef IOU_SLCR_MIO_PIN_21_L1_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_21_L1_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_21_L1_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_21_L1_SEL_MASK
 #define IOU_SLCR_MIO_PIN_21_L1_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT                       2
 #define IOU_SLCR_MIO_PIN_21_L1_SEL_MASK                        0x00000004U
@@ -22295,9 +22295,9 @@
     * est_scan_out[21]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU E
     * xt Tamper)
 */
-#undef IOU_SLCR_MIO_PIN_21_L2_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_21_L2_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_21_L2_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_21_L2_SEL_MASK
 #define IOU_SLCR_MIO_PIN_21_L2_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT                       3
 #define IOU_SLCR_MIO_PIN_21_L2_SEL_MASK                        0x00000018U
@@ -22312,9 +22312,9 @@
     * 1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (
     * UART receiver serial input) 7= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_21_L3_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_21_L3_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_21_L3_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_21_L3_SEL_MASK
 #define IOU_SLCR_MIO_PIN_21_L3_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT                       5
 #define IOU_SLCR_MIO_PIN_21_L3_SEL_MASK                        0x000000E0U
@@ -22322,9 +22322,9 @@
 /*
 * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_24_L0_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_24_L0_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_24_L0_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_24_L0_SEL_MASK
 #define IOU_SLCR_MIO_PIN_24_L0_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT                       1
 #define IOU_SLCR_MIO_PIN_24_L0_SEL_MASK                        0x00000002U
@@ -22333,9 +22333,9 @@
 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[7]- (
     * NAND Data Bus) 1= nand, Output, nfc_dq_out[7]- (NAND Data Bus)
 */
-#undef IOU_SLCR_MIO_PIN_24_L1_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_24_L1_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_24_L1_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_24_L1_SEL_MASK
 #define IOU_SLCR_MIO_PIN_24_L1_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT                       2
 #define IOU_SLCR_MIO_PIN_24_L1_SEL_MASK                        0x00000004U
@@ -22346,9 +22346,9 @@
     *  Scan Port) = test_scan, Output, test_scan_out[24]- (Test Scan Port) 3=
     * csu, Input, csu_ext_tamper- (CSU Ext Tamper)
 */
-#undef IOU_SLCR_MIO_PIN_24_L2_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_24_L2_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_24_L2_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_24_L2_SEL_MASK
 #define IOU_SLCR_MIO_PIN_24_L2_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT                       3
 #define IOU_SLCR_MIO_PIN_24_L2_SEL_MASK                        0x00000018U
@@ -22362,9 +22362,9 @@
     * TC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= N
     * ot Used
 */
-#undef IOU_SLCR_MIO_PIN_24_L3_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_24_L3_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_24_L3_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_24_L3_SEL_MASK
 #define IOU_SLCR_MIO_PIN_24_L3_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT                       5
 #define IOU_SLCR_MIO_PIN_24_L3_SEL_MASK                        0x000000E0U
@@ -22372,9 +22372,9 @@
 /*
 * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_25_L0_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_25_L0_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_25_L0_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_25_L0_SEL_MASK
 #define IOU_SLCR_MIO_PIN_25_L0_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT                       1
 #define IOU_SLCR_MIO_PIN_25_L0_SEL_MASK                        0x00000002U
@@ -22383,9 +22383,9 @@
 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_re_n- (NAN
     * D Read Enable)
 */
-#undef IOU_SLCR_MIO_PIN_25_L1_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_25_L1_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_25_L1_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_25_L1_SEL_MASK
 #define IOU_SLCR_MIO_PIN_25_L1_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT                       2
 #define IOU_SLCR_MIO_PIN_25_L1_SEL_MASK                        0x00000004U
@@ -22396,9 +22396,9 @@
     * (Test Scan Port) = test_scan, Output, test_scan_out[25]- (Test Scan Port
     * ) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
 */
-#undef IOU_SLCR_MIO_PIN_25_L2_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_25_L2_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_25_L2_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_25_L2_SEL_MASK
 #define IOU_SLCR_MIO_PIN_25_L2_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT                       3
 #define IOU_SLCR_MIO_PIN_25_L2_SEL_MASK                        0x00000018U
@@ -22412,9 +22412,9 @@
     * t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial in
     * put) 7= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_25_L3_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_25_L3_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_25_L3_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_25_L3_SEL_MASK
 #define IOU_SLCR_MIO_PIN_25_L3_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT                       5
 #define IOU_SLCR_MIO_PIN_25_L3_SEL_MASK                        0x000000E0U
@@ -22423,9 +22423,9 @@
 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd
     * [0]- (TX RGMII data)
 */
-#undef IOU_SLCR_MIO_PIN_27_L0_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_27_L0_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_27_L0_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_27_L0_SEL_MASK
 #define IOU_SLCR_MIO_PIN_27_L0_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT                       1
 #define IOU_SLCR_MIO_PIN_27_L0_SEL_MASK                        0x00000002U
@@ -22434,9 +22434,9 @@
 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (N
     * AND Ready/Busy)
 */
-#undef IOU_SLCR_MIO_PIN_27_L1_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_27_L1_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_27_L1_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_27_L1_SEL_MASK
 #define IOU_SLCR_MIO_PIN_27_L1_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT                       2
 #define IOU_SLCR_MIO_PIN_27_L1_SEL_MASK                        0x00000004U
@@ -22447,9 +22447,9 @@
     * n, Output, test_scan_out[27]- (Test Scan Port) 3= dpaux, Input, dp_aux_d
     * ata_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data)
 */
-#undef IOU_SLCR_MIO_PIN_27_L2_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_27_L2_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_27_L2_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_27_L2_SEL_MASK
 #define IOU_SLCR_MIO_PIN_27_L2_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT                       3
 #define IOU_SLCR_MIO_PIN_27_L2_SEL_MASK                        0x00000018U
@@ -22464,9 +22464,9 @@
     * T transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port D
     * atabus)
 */
-#undef IOU_SLCR_MIO_PIN_27_L3_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_27_L3_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_27_L3_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_27_L3_SEL_MASK
 #define IOU_SLCR_MIO_PIN_27_L3_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT                       5
 #define IOU_SLCR_MIO_PIN_27_L3_SEL_MASK                        0x000000E0U
@@ -22475,9 +22475,9 @@
 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd
     * [1]- (TX RGMII data)
 */
-#undef IOU_SLCR_MIO_PIN_28_L0_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_28_L0_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_28_L0_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_28_L0_SEL_MASK
 #define IOU_SLCR_MIO_PIN_28_L0_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT                       1
 #define IOU_SLCR_MIO_PIN_28_L0_SEL_MASK                        0x00000002U
@@ -22486,9 +22486,9 @@
 * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (N
     * AND Ready/Busy)
 */
-#undef IOU_SLCR_MIO_PIN_28_L1_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_28_L1_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_28_L1_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_28_L1_SEL_MASK
 #define IOU_SLCR_MIO_PIN_28_L1_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT                       2
 #define IOU_SLCR_MIO_PIN_28_L1_SEL_MASK                        0x00000004U
@@ -22499,9 +22499,9 @@
     * n, Output, test_scan_out[28]- (Test Scan Port) 3= dpaux, Input, dp_hot_p
     * lug_detect- (Dp Aux Hot Plug)
 */
-#undef IOU_SLCR_MIO_PIN_28_L2_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_28_L2_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_28_L2_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_28_L2_SEL_MASK
 #define IOU_SLCR_MIO_PIN_28_L2_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT                       3
 #define IOU_SLCR_MIO_PIN_28_L2_SEL_MASK                        0x00000018U
@@ -22515,9 +22515,9 @@
     * Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitt
     * er serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)
 */
-#undef IOU_SLCR_MIO_PIN_28_L3_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_28_L3_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_28_L3_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_28_L3_SEL_MASK
 #define IOU_SLCR_MIO_PIN_28_L3_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT                       5
 #define IOU_SLCR_MIO_PIN_28_L3_SEL_MASK                        0x000000E0U
@@ -22526,9 +22526,9 @@
 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd
     * [2]- (TX RGMII data)
 */
-#undef IOU_SLCR_MIO_PIN_29_L0_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_29_L0_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_29_L0_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_29_L0_SEL_MASK
 #define IOU_SLCR_MIO_PIN_29_L0_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT                       1
 #define IOU_SLCR_MIO_PIN_29_L0_SEL_MASK                        0x00000002U
@@ -22537,9 +22537,9 @@
 * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (
     * PCIE Reset signal)
 */
-#undef IOU_SLCR_MIO_PIN_29_L1_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_29_L1_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_29_L1_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_29_L1_SEL_MASK
 #define IOU_SLCR_MIO_PIN_29_L1_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT                       2
 #define IOU_SLCR_MIO_PIN_29_L1_SEL_MASK                        0x00000004U
@@ -22550,9 +22550,9 @@
     * n, Output, test_scan_out[29]- (Test Scan Port) 3= dpaux, Input, dp_aux_d
     * ata_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data)
 */
-#undef IOU_SLCR_MIO_PIN_29_L2_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_29_L2_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_29_L2_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_29_L2_SEL_MASK
 #define IOU_SLCR_MIO_PIN_29_L2_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT                       3
 #define IOU_SLCR_MIO_PIN_29_L2_SEL_MASK                        0x00000018U
@@ -22567,9 +22567,9 @@
     * (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input
     * ) 7= trace, Output, tracedq[7]- (Trace Port Databus)
 */
-#undef IOU_SLCR_MIO_PIN_29_L3_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_29_L3_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_29_L3_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_29_L3_SEL_MASK
 #define IOU_SLCR_MIO_PIN_29_L3_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT                       5
 #define IOU_SLCR_MIO_PIN_29_L3_SEL_MASK                        0x000000E0U
@@ -22578,9 +22578,9 @@
 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd
     * [3]- (TX RGMII data)
 */
-#undef IOU_SLCR_MIO_PIN_30_L0_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_30_L0_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_30_L0_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_30_L0_SEL_MASK
 #define IOU_SLCR_MIO_PIN_30_L0_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT                       1
 #define IOU_SLCR_MIO_PIN_30_L0_SEL_MASK                        0x00000002U
@@ -22589,9 +22589,9 @@
 * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (
     * PCIE Reset signal)
 */
-#undef IOU_SLCR_MIO_PIN_30_L1_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_30_L1_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_30_L1_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_30_L1_SEL_MASK
 #define IOU_SLCR_MIO_PIN_30_L1_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT                       2
 #define IOU_SLCR_MIO_PIN_30_L1_SEL_MASK                        0x00000004U
@@ -22602,9 +22602,9 @@
     * n, Output, test_scan_out[30]- (Test Scan Port) 3= dpaux, Input, dp_hot_p
     * lug_detect- (Dp Aux Hot Plug)
 */
-#undef IOU_SLCR_MIO_PIN_30_L2_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_30_L2_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_30_L2_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_30_L2_SEL_MASK
 #define IOU_SLCR_MIO_PIN_30_L2_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT                       3
 #define IOU_SLCR_MIO_PIN_30_L2_SEL_MASK                        0x00000018U
@@ -22619,9 +22619,9 @@
     * ) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output,
     *  tracedq[8]- (Trace Port Databus)
 */
-#undef IOU_SLCR_MIO_PIN_30_L3_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_30_L3_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_30_L3_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_30_L3_SEL_MASK
 #define IOU_SLCR_MIO_PIN_30_L3_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT                       5
 #define IOU_SLCR_MIO_PIN_30_L3_SEL_MASK                        0x000000E0U
@@ -22630,9 +22630,9 @@
 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[
     * 0]- (RX RGMII data)
 */
-#undef IOU_SLCR_MIO_PIN_45_L0_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_45_L0_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_45_L0_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_45_L0_SEL_MASK
 #define IOU_SLCR_MIO_PIN_45_L0_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT                       1
 #define IOU_SLCR_MIO_PIN_45_L0_SEL_MASK                        0x00000002U
@@ -22640,9 +22640,9 @@
 /*
 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_45_L1_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_45_L1_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_45_L1_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_45_L1_SEL_MASK
 #define IOU_SLCR_MIO_PIN_45_L1_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT                       2
 #define IOU_SLCR_MIO_PIN_45_L1_SEL_MASK                        0x00000004U
@@ -22652,9 +22652,9 @@
     * (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= s
     * d1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_45_L2_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_45_L2_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_45_L2_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_45_L2_SEL_MASK
 #define IOU_SLCR_MIO_PIN_45_L2_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT                       3
 #define IOU_SLCR_MIO_PIN_45_L2_SEL_MASK                        0x00000018U
@@ -22668,9 +22668,9 @@
     * aster Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= u
     * a1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_45_L3_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_45_L3_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_45_L3_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_45_L3_SEL_MASK
 #define IOU_SLCR_MIO_PIN_45_L3_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT                       5
 #define IOU_SLCR_MIO_PIN_45_L3_SEL_MASK                        0x000000E0U
@@ -22679,9 +22679,9 @@
 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[
     * 1]- (RX RGMII data)
 */
-#undef IOU_SLCR_MIO_PIN_46_L0_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_46_L0_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_46_L0_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_46_L0_SEL_MASK
 #define IOU_SLCR_MIO_PIN_46_L0_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT                       1
 #define IOU_SLCR_MIO_PIN_46_L0_SEL_MASK                        0x00000002U
@@ -22689,9 +22689,9 @@
 /*
 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_46_L1_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_46_L1_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_46_L1_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_46_L1_SEL_MASK
 #define IOU_SLCR_MIO_PIN_46_L1_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT                       2
 #define IOU_SLCR_MIO_PIN_46_L1_SEL_MASK                        0x00000004U
@@ -22702,9 +22702,9 @@
     * d1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_ou
     * t[0]- (8-bit Data bus) 3= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_46_L2_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_46_L2_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_46_L2_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_46_L2_SEL_MASK
 #define IOU_SLCR_MIO_PIN_46_L2_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT                       3
 #define IOU_SLCR_MIO_PIN_46_L2_SEL_MASK                        0x00000018U
@@ -22718,9 +22718,9 @@
     * er Selects) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_
     * rxd- (UART receiver serial input) 7= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_46_L3_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_46_L3_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_46_L3_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_46_L3_SEL_MASK
 #define IOU_SLCR_MIO_PIN_46_L3_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT                       5
 #define IOU_SLCR_MIO_PIN_46_L3_SEL_MASK                        0x000000E0U
@@ -22729,9 +22729,9 @@
 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[
     * 2]- (RX RGMII data)
 */
-#undef IOU_SLCR_MIO_PIN_47_L0_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_47_L0_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_47_L0_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_47_L0_SEL_MASK
 #define IOU_SLCR_MIO_PIN_47_L0_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT                       1
 #define IOU_SLCR_MIO_PIN_47_L0_SEL_MASK                        0x00000002U
@@ -22739,9 +22739,9 @@
 /*
 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_47_L1_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_47_L1_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_47_L1_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_47_L1_SEL_MASK
 #define IOU_SLCR_MIO_PIN_47_L1_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT                       2
 #define IOU_SLCR_MIO_PIN_47_L1_SEL_MASK                        0x00000004U
@@ -22752,9 +22752,9 @@
     * d1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_ou
     * t[1]- (8-bit Data bus) 3= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_47_L2_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_47_L2_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_47_L2_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_47_L2_SEL_MASK
 #define IOU_SLCR_MIO_PIN_47_L2_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT                       3
 #define IOU_SLCR_MIO_PIN_47_L2_SEL_MASK                        0x00000018U
@@ -22769,9 +22769,9 @@
     * c0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd-
     *  (UART transmitter serial output) 7= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_47_L3_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_47_L3_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_47_L3_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_47_L3_SEL_MASK
 #define IOU_SLCR_MIO_PIN_47_L3_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT                       5
 #define IOU_SLCR_MIO_PIN_47_L3_SEL_MASK                        0x000000E0U
@@ -22780,9 +22780,9 @@
 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[
     * 3]- (RX RGMII data)
 */
-#undef IOU_SLCR_MIO_PIN_48_L0_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_48_L0_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_48_L0_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_48_L0_SEL_MASK
 #define IOU_SLCR_MIO_PIN_48_L0_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT                       1
 #define IOU_SLCR_MIO_PIN_48_L0_SEL_MASK                        0x00000002U
@@ -22790,9 +22790,9 @@
 /*
 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_48_L1_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_48_L1_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_48_L1_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_48_L1_SEL_MASK
 #define IOU_SLCR_MIO_PIN_48_L1_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT                       2
 #define IOU_SLCR_MIO_PIN_48_L1_SEL_MASK                        0x00000004U
@@ -22803,9 +22803,9 @@
     * d1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_ou
     * t[2]- (8-bit Data bus) 3= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_48_L2_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_48_L2_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_48_L2_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_48_L2_SEL_MASK
 #define IOU_SLCR_MIO_PIN_48_L2_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT                       3
 #define IOU_SLCR_MIO_PIN_48_L2_SEL_MASK                        0x00000018U
@@ -22820,9 +22820,9 @@
     * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Us
     * ed
 */
-#undef IOU_SLCR_MIO_PIN_48_L3_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_48_L3_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_48_L3_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_48_L3_SEL_MASK
 #define IOU_SLCR_MIO_PIN_48_L3_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT                       5
 #define IOU_SLCR_MIO_PIN_48_L3_SEL_MASK                        0x000000E0U
@@ -22831,9 +22831,9 @@
 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_c
     * tl- (RX RGMII control )
 */
-#undef IOU_SLCR_MIO_PIN_49_L0_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_49_L0_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_49_L0_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_49_L0_SEL_MASK
 #define IOU_SLCR_MIO_PIN_49_L0_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT                       1
 #define IOU_SLCR_MIO_PIN_49_L0_SEL_MASK                        0x00000002U
@@ -22841,9 +22841,9 @@
 /*
 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_49_L1_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_49_L1_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_49_L1_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_49_L1_SEL_MASK
 #define IOU_SLCR_MIO_PIN_49_L1_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT                       2
 #define IOU_SLCR_MIO_PIN_49_L1_SEL_MASK                        0x00000004U
@@ -22853,9 +22853,9 @@
     * (SD card bus power) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd
     * 1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_49_L2_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_49_L2_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_49_L2_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_49_L2_SEL_MASK
 #define IOU_SLCR_MIO_PIN_49_L2_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT                       3
 #define IOU_SLCR_MIO_PIN_49_L2_SEL_MASK                        0x00000018U
@@ -22870,9 +22870,9 @@
     * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
     * 7= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_49_L3_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_49_L3_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_49_L3_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_49_L3_SEL_MASK
 #define IOU_SLCR_MIO_PIN_49_L3_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT                       5
 #define IOU_SLCR_MIO_PIN_49_L3_SEL_MASK                        0x000000E0U
@@ -22881,9 +22881,9 @@
 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk-
     *  (TSU clock)
 */
-#undef IOU_SLCR_MIO_PIN_50_L0_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_50_L0_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_50_L0_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_50_L0_SEL_MASK
 #define IOU_SLCR_MIO_PIN_50_L0_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT                       1
 #define IOU_SLCR_MIO_PIN_50_L0_SEL_MASK                        0x00000002U
@@ -22891,9 +22891,9 @@
 /*
 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_50_L1_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_50_L1_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_50_L1_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_50_L1_SEL_MASK
 #define IOU_SLCR_MIO_PIN_50_L1_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT                       2
 #define IOU_SLCR_MIO_PIN_50_L1_SEL_MASK                        0x00000004U
@@ -22903,9 +22903,9 @@
     * rd write protect from connector) 2= sd1, Input, sd1_cmd_in- (Command Ind
     * icator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_50_L2_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_50_L2_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_50_L2_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_50_L2_SEL_MASK
 #define IOU_SLCR_MIO_PIN_50_L2_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT                       3
 #define IOU_SLCR_MIO_PIN_50_L2_SEL_MASK                        0x00000018U
@@ -22919,9 +22919,9 @@
     * ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART rece
     * iver serial input) 7= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_50_L3_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_50_L3_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_50_L3_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_50_L3_SEL_MASK
 #define IOU_SLCR_MIO_PIN_50_L3_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT                       5
 #define IOU_SLCR_MIO_PIN_50_L3_SEL_MASK                        0x000000E0U
@@ -22930,9 +22930,9 @@
 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk-
     *  (TSU clock)
 */
-#undef IOU_SLCR_MIO_PIN_51_L0_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_51_L0_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_51_L0_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_51_L0_SEL_MASK
 #define IOU_SLCR_MIO_PIN_51_L0_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT                       1
 #define IOU_SLCR_MIO_PIN_51_L0_SEL_MASK                        0x00000002U
@@ -22940,9 +22940,9 @@
 /*
 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_51_L1_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_51_L1_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_51_L1_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_51_L1_SEL_MASK
 #define IOU_SLCR_MIO_PIN_51_L1_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT                       2
 #define IOU_SLCR_MIO_PIN_51_L1_SEL_MASK                        0x00000004U
@@ -22951,9 +22951,9 @@
 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Output, sdi
     * o1_clk_out- (SDSDIO clock) 3= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_51_L2_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_51_L2_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_51_L2_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_51_L2_SEL_MASK
 #define IOU_SLCR_MIO_PIN_51_L2_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT                       3
 #define IOU_SLCR_MIO_PIN_51_L2_SEL_MASK                        0x00000018U
@@ -22968,9 +22968,9 @@
     * ve_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter
     * serial output) 7= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_51_L3_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_51_L3_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_51_L3_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_51_L3_SEL_MASK
 #define IOU_SLCR_MIO_PIN_51_L3_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT                       5
 #define IOU_SLCR_MIO_PIN_51_L3_SEL_MASK                        0x000000E0U
@@ -22979,9 +22979,9 @@
 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_
     * clk- (TX RGMII clock)
 */
-#undef IOU_SLCR_MIO_PIN_52_L0_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_52_L0_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_52_L0_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_52_L0_SEL_MASK
 #define IOU_SLCR_MIO_PIN_52_L0_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT                       1
 #define IOU_SLCR_MIO_PIN_52_L0_SEL_MASK                        0x00000002U
@@ -22990,9 +22990,9 @@
 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_clk_i
     * n- (ULPI Clock)
 */
-#undef IOU_SLCR_MIO_PIN_52_L1_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_52_L1_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_52_L1_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_52_L1_SEL_MASK
 #define IOU_SLCR_MIO_PIN_52_L1_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT                       2
 #define IOU_SLCR_MIO_PIN_52_L1_SEL_MASK                        0x00000004U
@@ -23001,9 +23001,9 @@
 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
     * Used
 */
-#undef IOU_SLCR_MIO_PIN_52_L2_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_52_L2_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_52_L2_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_52_L2_SEL_MASK
 #define IOU_SLCR_MIO_PIN_52_L2_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT                       3
 #define IOU_SLCR_MIO_PIN_52_L2_SEL_MASK                        0x00000018U
@@ -23018,9 +23018,9 @@
     * put, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_c
     * lk- (Trace Port Clock)
 */
-#undef IOU_SLCR_MIO_PIN_52_L3_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_52_L3_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_52_L3_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_52_L3_SEL_MASK
 #define IOU_SLCR_MIO_PIN_52_L3_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT                       5
 #define IOU_SLCR_MIO_PIN_52_L3_SEL_MASK                        0x000000E0U
@@ -23029,9 +23029,9 @@
 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd
     * [0]- (TX RGMII data)
 */
-#undef IOU_SLCR_MIO_PIN_53_L0_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_53_L0_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_53_L0_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_53_L0_SEL_MASK
 #define IOU_SLCR_MIO_PIN_53_L0_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT                       1
 #define IOU_SLCR_MIO_PIN_53_L0_SEL_MASK                        0x00000002U
@@ -23040,9 +23040,9 @@
 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir-
     * (Data bus direction control)
 */
-#undef IOU_SLCR_MIO_PIN_53_L1_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_53_L1_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_53_L1_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_53_L1_SEL_MASK
 #define IOU_SLCR_MIO_PIN_53_L1_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT                       2
 #define IOU_SLCR_MIO_PIN_53_L1_SEL_MASK                        0x00000004U
@@ -23051,9 +23051,9 @@
 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
     * Used
 */
-#undef IOU_SLCR_MIO_PIN_53_L2_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_53_L2_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_53_L2_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_53_L2_SEL_MASK
 #define IOU_SLCR_MIO_PIN_53_L2_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT                       3
 #define IOU_SLCR_MIO_PIN_53_L2_SEL_MASK                        0x00000018U
@@ -23068,9 +23068,9 @@
     * receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control
     * Signal)
 */
-#undef IOU_SLCR_MIO_PIN_53_L3_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_53_L3_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_53_L3_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_53_L3_SEL_MASK
 #define IOU_SLCR_MIO_PIN_53_L3_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT                       5
 #define IOU_SLCR_MIO_PIN_53_L3_SEL_MASK                        0x000000E0U
@@ -23079,9 +23079,9 @@
 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd
     * [1]- (TX RGMII data)
 */
-#undef IOU_SLCR_MIO_PIN_54_L0_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_54_L0_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_54_L0_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_54_L0_SEL_MASK
 #define IOU_SLCR_MIO_PIN_54_L0_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT                       1
 #define IOU_SLCR_MIO_PIN_54_L0_SEL_MASK                        0x00000002U
@@ -23091,9 +23091,9 @@
     * ta[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[2]- (ULPI data
     *  bus)
 */
-#undef IOU_SLCR_MIO_PIN_54_L1_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_54_L1_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_54_L1_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_54_L1_SEL_MASK
 #define IOU_SLCR_MIO_PIN_54_L1_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT                       2
 #define IOU_SLCR_MIO_PIN_54_L1_SEL_MASK                        0x00000004U
@@ -23102,9 +23102,9 @@
 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
     * Used
 */
-#undef IOU_SLCR_MIO_PIN_54_L2_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_54_L2_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_54_L2_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_54_L2_SEL_MASK
 #define IOU_SLCR_MIO_PIN_54_L2_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT                       3
 #define IOU_SLCR_MIO_PIN_54_L2_SEL_MASK                        0x00000018U
@@ -23118,9 +23118,9 @@
     * nput, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver se
     * rial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)
 */
-#undef IOU_SLCR_MIO_PIN_54_L3_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_54_L3_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_54_L3_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_54_L3_SEL_MASK
 #define IOU_SLCR_MIO_PIN_54_L3_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT                       5
 #define IOU_SLCR_MIO_PIN_54_L3_SEL_MASK                        0x000000E0U
@@ -23129,9 +23129,9 @@
 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd
     * [2]- (TX RGMII data)
 */
-#undef IOU_SLCR_MIO_PIN_55_L0_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_55_L0_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_55_L0_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_55_L0_SEL_MASK
 #define IOU_SLCR_MIO_PIN_55_L0_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT                       1
 #define IOU_SLCR_MIO_PIN_55_L0_SEL_MASK                        0x00000002U
@@ -23140,9 +23140,9 @@
 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt-
     * (Data flow control signal from the PHY)
 */
-#undef IOU_SLCR_MIO_PIN_55_L1_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_55_L1_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_55_L1_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_55_L1_SEL_MASK
 #define IOU_SLCR_MIO_PIN_55_L1_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT                       2
 #define IOU_SLCR_MIO_PIN_55_L1_SEL_MASK                        0x00000004U
@@ -23151,9 +23151,9 @@
 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
     * Used
 */
-#undef IOU_SLCR_MIO_PIN_55_L2_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_55_L2_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_55_L2_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_55_L2_SEL_MASK
 #define IOU_SLCR_MIO_PIN_55_L2_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT                       3
 #define IOU_SLCR_MIO_PIN_55_L2_SEL_MASK                        0x00000018U
@@ -23168,9 +23168,9 @@
     *  (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial
     * output) 7= trace, Output, tracedq[1]- (Trace Port Databus)
 */
-#undef IOU_SLCR_MIO_PIN_55_L3_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_55_L3_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_55_L3_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_55_L3_SEL_MASK
 #define IOU_SLCR_MIO_PIN_55_L3_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT                       5
 #define IOU_SLCR_MIO_PIN_55_L3_SEL_MASK                        0x000000E0U
@@ -23179,9 +23179,9 @@
 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd
     * [3]- (TX RGMII data)
 */
-#undef IOU_SLCR_MIO_PIN_56_L0_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_56_L0_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_56_L0_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_56_L0_SEL_MASK
 #define IOU_SLCR_MIO_PIN_56_L0_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT                       1
 #define IOU_SLCR_MIO_PIN_56_L0_SEL_MASK                        0x00000002U
@@ -23191,9 +23191,9 @@
     * ta[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[0]- (ULPI data
     *  bus)
 */
-#undef IOU_SLCR_MIO_PIN_56_L1_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_56_L1_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_56_L1_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_56_L1_SEL_MASK
 #define IOU_SLCR_MIO_PIN_56_L1_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT                       2
 #define IOU_SLCR_MIO_PIN_56_L1_SEL_MASK                        0x00000004U
@@ -23202,9 +23202,9 @@
 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
     * Used
 */
-#undef IOU_SLCR_MIO_PIN_56_L2_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_56_L2_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_56_L2_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_56_L2_SEL_MASK
 #define IOU_SLCR_MIO_PIN_56_L2_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT                       3
 #define IOU_SLCR_MIO_PIN_56_L2_SEL_MASK                        0x00000018U
@@ -23219,9 +23219,9 @@
     * k) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, O
     * utput, tracedq[2]- (Trace Port Databus)
 */
-#undef IOU_SLCR_MIO_PIN_56_L3_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_56_L3_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_56_L3_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_56_L3_SEL_MASK
 #define IOU_SLCR_MIO_PIN_56_L3_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT                       5
 #define IOU_SLCR_MIO_PIN_56_L3_SEL_MASK                        0x000000E0U
@@ -23230,9 +23230,9 @@
 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_
     * ctl- (TX RGMII control)
 */
-#undef IOU_SLCR_MIO_PIN_57_L0_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_57_L0_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_57_L0_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_57_L0_SEL_MASK
 #define IOU_SLCR_MIO_PIN_57_L0_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT                       1
 #define IOU_SLCR_MIO_PIN_57_L0_SEL_MASK                        0x00000002U
@@ -23242,9 +23242,9 @@
     * ta[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[1]- (ULPI data
     *  bus)
 */
-#undef IOU_SLCR_MIO_PIN_57_L1_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_57_L1_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_57_L1_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_57_L1_SEL_MASK
 #define IOU_SLCR_MIO_PIN_57_L1_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT                       2
 #define IOU_SLCR_MIO_PIN_57_L1_SEL_MASK                        0x00000004U
@@ -23253,9 +23253,9 @@
 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
     * Used
 */
-#undef IOU_SLCR_MIO_PIN_57_L2_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_57_L2_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_57_L2_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_57_L2_SEL_MASK
 #define IOU_SLCR_MIO_PIN_57_L2_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT                       3
 #define IOU_SLCR_MIO_PIN_57_L2_SEL_MASK                        0x00000018U
@@ -23270,9 +23270,9 @@
     *  Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7=
     *  trace, Output, tracedq[3]- (Trace Port Databus)
 */
-#undef IOU_SLCR_MIO_PIN_57_L3_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_57_L3_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_57_L3_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_57_L3_SEL_MASK
 #define IOU_SLCR_MIO_PIN_57_L3_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT                       5
 #define IOU_SLCR_MIO_PIN_57_L3_SEL_MASK                        0x000000E0U
@@ -23281,9 +23281,9 @@
 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_c
     * lk- (RX RGMII clock)
 */
-#undef IOU_SLCR_MIO_PIN_58_L0_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_58_L0_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_58_L0_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_58_L0_SEL_MASK
 #define IOU_SLCR_MIO_PIN_58_L0_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT                       1
 #define IOU_SLCR_MIO_PIN_58_L0_SEL_MASK                        0x00000002U
@@ -23292,9 +23292,9 @@
 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp-
     *  (Asserted to end or interrupt transfers)
 */
-#undef IOU_SLCR_MIO_PIN_58_L1_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_58_L1_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_58_L1_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_58_L1_SEL_MASK
 #define IOU_SLCR_MIO_PIN_58_L1_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT                       2
 #define IOU_SLCR_MIO_PIN_58_L1_SEL_MASK                        0x00000004U
@@ -23303,9 +23303,9 @@
 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
     * Used
 */
-#undef IOU_SLCR_MIO_PIN_58_L2_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_58_L2_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_58_L2_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_58_L2_SEL_MASK
 #define IOU_SLCR_MIO_PIN_58_L2_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT                       3
 #define IOU_SLCR_MIO_PIN_58_L2_SEL_MASK                        0x00000018U
@@ -23320,9 +23320,9 @@
     * t, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- (
     * Trace Port Databus)
 */
-#undef IOU_SLCR_MIO_PIN_58_L3_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_58_L3_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_58_L3_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_58_L3_SEL_MASK
 #define IOU_SLCR_MIO_PIN_58_L3_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT                       5
 #define IOU_SLCR_MIO_PIN_58_L3_SEL_MASK                        0x000000E0U
@@ -23331,9 +23331,9 @@
 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[
     * 0]- (RX RGMII data)
 */
-#undef IOU_SLCR_MIO_PIN_59_L0_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_59_L0_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_59_L0_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_59_L0_SEL_MASK
 #define IOU_SLCR_MIO_PIN_59_L0_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT                       1
 #define IOU_SLCR_MIO_PIN_59_L0_SEL_MASK                        0x00000002U
@@ -23343,9 +23343,9 @@
     * ta[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[3]- (ULPI data
     *  bus)
 */
-#undef IOU_SLCR_MIO_PIN_59_L1_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_59_L1_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_59_L1_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_59_L1_SEL_MASK
 #define IOU_SLCR_MIO_PIN_59_L1_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT                       2
 #define IOU_SLCR_MIO_PIN_59_L1_SEL_MASK                        0x00000004U
@@ -23354,9 +23354,9 @@
 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
     * Used
 */
-#undef IOU_SLCR_MIO_PIN_59_L2_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_59_L2_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_59_L2_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_59_L2_SEL_MASK
 #define IOU_SLCR_MIO_PIN_59_L2_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT                       3
 #define IOU_SLCR_MIO_PIN_59_L2_SEL_MASK                        0x00000018U
@@ -23371,9 +23371,9 @@
     * T transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port D
     * atabus)
 */
-#undef IOU_SLCR_MIO_PIN_59_L3_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_59_L3_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_59_L3_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_59_L3_SEL_MASK
 #define IOU_SLCR_MIO_PIN_59_L3_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT                       5
 #define IOU_SLCR_MIO_PIN_59_L3_SEL_MASK                        0x000000E0U
@@ -23382,9 +23382,9 @@
 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[
     * 1]- (RX RGMII data)
 */
-#undef IOU_SLCR_MIO_PIN_60_L0_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_60_L0_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_60_L0_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_60_L0_SEL_MASK
 #define IOU_SLCR_MIO_PIN_60_L0_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT                       1
 #define IOU_SLCR_MIO_PIN_60_L0_SEL_MASK                        0x00000002U
@@ -23394,9 +23394,9 @@
     * ta[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[4]- (ULPI data
     *  bus)
 */
-#undef IOU_SLCR_MIO_PIN_60_L1_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_60_L1_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_60_L1_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_60_L1_SEL_MASK
 #define IOU_SLCR_MIO_PIN_60_L1_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT                       2
 #define IOU_SLCR_MIO_PIN_60_L1_SEL_MASK                        0x00000004U
@@ -23405,9 +23405,9 @@
 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
     * Used
 */
-#undef IOU_SLCR_MIO_PIN_60_L2_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_60_L2_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_60_L2_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_60_L2_SEL_MASK
 #define IOU_SLCR_MIO_PIN_60_L2_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT                       3
 #define IOU_SLCR_MIO_PIN_60_L2_SEL_MASK                        0x00000018U
@@ -23421,9 +23421,9 @@
     * Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitt
     * er serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)
 */
-#undef IOU_SLCR_MIO_PIN_60_L3_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_60_L3_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_60_L3_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_60_L3_SEL_MASK
 #define IOU_SLCR_MIO_PIN_60_L3_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT                       5
 #define IOU_SLCR_MIO_PIN_60_L3_SEL_MASK                        0x000000E0U
@@ -23432,9 +23432,9 @@
 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[
     * 2]- (RX RGMII data)
 */
-#undef IOU_SLCR_MIO_PIN_61_L0_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_61_L0_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_61_L0_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_61_L0_SEL_MASK
 #define IOU_SLCR_MIO_PIN_61_L0_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT                       1
 #define IOU_SLCR_MIO_PIN_61_L0_SEL_MASK                        0x00000002U
@@ -23444,9 +23444,9 @@
     * ta[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[5]- (ULPI data
     *  bus)
 */
-#undef IOU_SLCR_MIO_PIN_61_L1_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_61_L1_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_61_L1_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_61_L1_SEL_MASK
 #define IOU_SLCR_MIO_PIN_61_L1_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT                       2
 #define IOU_SLCR_MIO_PIN_61_L1_SEL_MASK                        0x00000004U
@@ -23455,9 +23455,9 @@
 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
     * Used
 */
-#undef IOU_SLCR_MIO_PIN_61_L2_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_61_L2_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_61_L2_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_61_L2_SEL_MASK
 #define IOU_SLCR_MIO_PIN_61_L2_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT                       3
 #define IOU_SLCR_MIO_PIN_61_L2_SEL_MASK                        0x00000018U
@@ -23472,9 +23472,9 @@
     * (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input
     * ) 7= trace, Output, tracedq[7]- (Trace Port Databus)
 */
-#undef IOU_SLCR_MIO_PIN_61_L3_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_61_L3_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_61_L3_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_61_L3_SEL_MASK
 #define IOU_SLCR_MIO_PIN_61_L3_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT                       5
 #define IOU_SLCR_MIO_PIN_61_L3_SEL_MASK                        0x000000E0U
@@ -23483,9 +23483,9 @@
 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[
     * 3]- (RX RGMII data)
 */
-#undef IOU_SLCR_MIO_PIN_62_L0_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_62_L0_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_62_L0_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_62_L0_SEL_MASK
 #define IOU_SLCR_MIO_PIN_62_L0_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT                       1
 #define IOU_SLCR_MIO_PIN_62_L0_SEL_MASK                        0x00000002U
@@ -23495,9 +23495,9 @@
     * ta[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[6]- (ULPI data
     *  bus)
 */
-#undef IOU_SLCR_MIO_PIN_62_L1_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_62_L1_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_62_L1_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_62_L1_SEL_MASK
 #define IOU_SLCR_MIO_PIN_62_L1_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT                       2
 #define IOU_SLCR_MIO_PIN_62_L1_SEL_MASK                        0x00000004U
@@ -23506,9 +23506,9 @@
 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
     * Used
 */
-#undef IOU_SLCR_MIO_PIN_62_L2_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_62_L2_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_62_L2_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_62_L2_SEL_MASK
 #define IOU_SLCR_MIO_PIN_62_L2_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT                       3
 #define IOU_SLCR_MIO_PIN_62_L2_SEL_MASK                        0x00000018U
@@ -23523,9 +23523,9 @@
     * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu
     * t, tracedq[8]- (Trace Port Databus)
 */
-#undef IOU_SLCR_MIO_PIN_62_L3_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_62_L3_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_62_L3_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_62_L3_SEL_MASK
 #define IOU_SLCR_MIO_PIN_62_L3_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT                       5
 #define IOU_SLCR_MIO_PIN_62_L3_SEL_MASK                        0x000000E0U
@@ -23534,9 +23534,9 @@
 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_c
     * tl- (RX RGMII control )
 */
-#undef IOU_SLCR_MIO_PIN_63_L0_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_63_L0_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_63_L0_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_63_L0_SEL_MASK
 #define IOU_SLCR_MIO_PIN_63_L0_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT                       1
 #define IOU_SLCR_MIO_PIN_63_L0_SEL_MASK                        0x00000002U
@@ -23546,9 +23546,9 @@
     * ta[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[7]- (ULPI data
     *  bus)
 */
-#undef IOU_SLCR_MIO_PIN_63_L1_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_63_L1_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_63_L1_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_63_L1_SEL_MASK
 #define IOU_SLCR_MIO_PIN_63_L1_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT                       2
 #define IOU_SLCR_MIO_PIN_63_L1_SEL_MASK                        0x00000004U
@@ -23557,9 +23557,9 @@
 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not
     * Used
 */
-#undef IOU_SLCR_MIO_PIN_63_L2_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_63_L2_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_63_L2_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_63_L2_SEL_MASK
 #define IOU_SLCR_MIO_PIN_63_L2_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT                       3
 #define IOU_SLCR_MIO_PIN_63_L2_SEL_MASK                        0x00000018U
@@ -23574,9 +23574,9 @@
     * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou
     * tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)
 */
-#undef IOU_SLCR_MIO_PIN_63_L3_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_63_L3_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_63_L3_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_63_L3_SEL_MASK
 #define IOU_SLCR_MIO_PIN_63_L3_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT                       5
 #define IOU_SLCR_MIO_PIN_63_L3_SEL_MASK                        0x000000E0U
@@ -23585,9 +23585,9 @@
 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_
     * clk- (TX RGMII clock)
 */
-#undef IOU_SLCR_MIO_PIN_64_L0_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_64_L0_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_64_L0_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_64_L0_SEL_MASK
 #define IOU_SLCR_MIO_PIN_64_L0_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT                       1
 #define IOU_SLCR_MIO_PIN_64_L0_SEL_MASK                        0x00000002U
@@ -23596,9 +23596,9 @@
 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_clk_i
     * n- (ULPI Clock)
 */
-#undef IOU_SLCR_MIO_PIN_64_L1_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_64_L1_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_64_L1_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_64_L1_SEL_MASK
 #define IOU_SLCR_MIO_PIN_64_L1_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT                       2
 #define IOU_SLCR_MIO_PIN_64_L1_SEL_MASK                        0x00000004U
@@ -23607,9 +23607,9 @@
 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out-
     * (SDSDIO clock) 2= Not Used 3= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_64_L2_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_64_L2_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_64_L2_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_64_L2_SEL_MASK
 #define IOU_SLCR_MIO_PIN_64_L2_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT                       3
 #define IOU_SLCR_MIO_PIN_64_L2_SEL_MASK                        0x00000018U
@@ -23624,9 +23624,9 @@
     * (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7=
     *  trace, Output, tracedq[10]- (Trace Port Databus)
 */
-#undef IOU_SLCR_MIO_PIN_64_L3_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_64_L3_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_64_L3_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_64_L3_SEL_MASK
 #define IOU_SLCR_MIO_PIN_64_L3_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT                       5
 #define IOU_SLCR_MIO_PIN_64_L3_SEL_MASK                        0x000000E0U
@@ -23635,9 +23635,9 @@
 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd
     * [0]- (TX RGMII data)
 */
-#undef IOU_SLCR_MIO_PIN_65_L0_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_65_L0_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_65_L0_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_65_L0_SEL_MASK
 #define IOU_SLCR_MIO_PIN_65_L0_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT                       1
 #define IOU_SLCR_MIO_PIN_65_L0_SEL_MASK                        0x00000002U
@@ -23646,9 +23646,9 @@
 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir-
     * (Data bus direction control)
 */
-#undef IOU_SLCR_MIO_PIN_65_L1_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_65_L1_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_65_L1_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_65_L1_SEL_MASK
 #define IOU_SLCR_MIO_PIN_65_L1_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT                       2
 #define IOU_SLCR_MIO_PIN_65_L1_SEL_MASK                        0x00000004U
@@ -23657,9 +23657,9 @@
 * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD
     * card detect from connector) 2= Not Used 3= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_65_L2_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_65_L2_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_65_L2_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_65_L2_SEL_MASK
 #define IOU_SLCR_MIO_PIN_65_L2_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT                       3
 #define IOU_SLCR_MIO_PIN_65_L2_SEL_MASK                        0x00000018U
@@ -23674,9 +23674,9 @@
     * a1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace
     * dq[11]- (Trace Port Databus)
 */
-#undef IOU_SLCR_MIO_PIN_65_L3_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_65_L3_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_65_L3_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_65_L3_SEL_MASK
 #define IOU_SLCR_MIO_PIN_65_L3_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT                       5
 #define IOU_SLCR_MIO_PIN_65_L3_SEL_MASK                        0x000000E0U
@@ -23685,9 +23685,9 @@
 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd
     * [1]- (TX RGMII data)
 */
-#undef IOU_SLCR_MIO_PIN_66_L0_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_66_L0_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_66_L0_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_66_L0_SEL_MASK
 #define IOU_SLCR_MIO_PIN_66_L0_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT                       1
 #define IOU_SLCR_MIO_PIN_66_L0_SEL_MASK                        0x00000002U
@@ -23697,9 +23697,9 @@
     * ta[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[2]- (ULPI data
     *  bus)
 */
-#undef IOU_SLCR_MIO_PIN_66_L1_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_66_L1_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_66_L1_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_66_L1_SEL_MASK
 #define IOU_SLCR_MIO_PIN_66_L1_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT                       2
 #define IOU_SLCR_MIO_PIN_66_L1_SEL_MASK                        0x00000004U
@@ -23709,9 +23709,9 @@
     * mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= Not
     *  Used 3= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_66_L2_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_66_L2_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_66_L2_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_66_L2_SEL_MASK
 #define IOU_SLCR_MIO_PIN_66_L2_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT                       3
 #define IOU_SLCR_MIO_PIN_66_L2_SEL_MASK                        0x00000018U
@@ -23726,9 +23726,9 @@
     * rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace
     * Port Databus)
 */
-#undef IOU_SLCR_MIO_PIN_66_L3_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_66_L3_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_66_L3_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_66_L3_SEL_MASK
 #define IOU_SLCR_MIO_PIN_66_L3_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT                       5
 #define IOU_SLCR_MIO_PIN_66_L3_SEL_MASK                        0x000000E0U
@@ -23737,9 +23737,9 @@
 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd
     * [2]- (TX RGMII data)
 */
-#undef IOU_SLCR_MIO_PIN_67_L0_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_67_L0_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_67_L0_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_67_L0_SEL_MASK
 #define IOU_SLCR_MIO_PIN_67_L0_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT                       1
 #define IOU_SLCR_MIO_PIN_67_L0_SEL_MASK                        0x00000002U
@@ -23748,9 +23748,9 @@
 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt-
     * (Data flow control signal from the PHY)
 */
-#undef IOU_SLCR_MIO_PIN_67_L1_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_67_L1_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_67_L1_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_67_L1_SEL_MASK
 #define IOU_SLCR_MIO_PIN_67_L1_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT                       2
 #define IOU_SLCR_MIO_PIN_67_L1_SEL_MASK                        0x00000004U
@@ -23760,9 +23760,9 @@
     * (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= N
     * ot Used 3= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_67_L2_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_67_L2_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_67_L2_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_67_L2_SEL_MASK
 #define IOU_SLCR_MIO_PIN_67_L2_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT                       3
 #define IOU_SLCR_MIO_PIN_67_L2_SEL_MASK                        0x00000018U
@@ -23778,9 +23778,9 @@
     *  (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace
     * Port Databus)
 */
-#undef IOU_SLCR_MIO_PIN_67_L3_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_67_L3_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_67_L3_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_67_L3_SEL_MASK
 #define IOU_SLCR_MIO_PIN_67_L3_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT                       5
 #define IOU_SLCR_MIO_PIN_67_L3_SEL_MASK                        0x000000E0U
@@ -23789,9 +23789,9 @@
 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd
     * [3]- (TX RGMII data)
 */
-#undef IOU_SLCR_MIO_PIN_68_L0_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_68_L0_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_68_L0_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_68_L0_SEL_MASK
 #define IOU_SLCR_MIO_PIN_68_L0_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT                       1
 #define IOU_SLCR_MIO_PIN_68_L0_SEL_MASK                        0x00000002U
@@ -23801,9 +23801,9 @@
     * ta[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data
     *  bus)
 */
-#undef IOU_SLCR_MIO_PIN_68_L1_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_68_L1_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_68_L1_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_68_L1_SEL_MASK
 #define IOU_SLCR_MIO_PIN_68_L1_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT                       2
 #define IOU_SLCR_MIO_PIN_68_L1_SEL_MASK                        0x00000004U
@@ -23813,9 +23813,9 @@
     * (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= N
     * ot Used 3= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_68_L2_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_68_L2_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_68_L2_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_68_L2_SEL_MASK
 #define IOU_SLCR_MIO_PIN_68_L2_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT                       3
 #define IOU_SLCR_MIO_PIN_68_L2_SEL_MASK                        0x00000018U
@@ -23830,9 +23830,9 @@
     * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace,
     *  Output, tracedq[14]- (Trace Port Databus)
 */
-#undef IOU_SLCR_MIO_PIN_68_L3_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_68_L3_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_68_L3_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_68_L3_SEL_MASK
 #define IOU_SLCR_MIO_PIN_68_L3_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT                       5
 #define IOU_SLCR_MIO_PIN_68_L3_SEL_MASK                        0x000000E0U
@@ -23841,9 +23841,9 @@
 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_
     * ctl- (TX RGMII control)
 */
-#undef IOU_SLCR_MIO_PIN_69_L0_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_69_L0_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_69_L0_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_69_L0_SEL_MASK
 #define IOU_SLCR_MIO_PIN_69_L0_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT                       1
 #define IOU_SLCR_MIO_PIN_69_L0_SEL_MASK                        0x00000002U
@@ -23853,9 +23853,9 @@
     * ta[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data
     *  bus)
 */
-#undef IOU_SLCR_MIO_PIN_69_L1_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_69_L1_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_69_L1_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_69_L1_SEL_MASK
 #define IOU_SLCR_MIO_PIN_69_L1_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT                       2
 #define IOU_SLCR_MIO_PIN_69_L1_SEL_MASK                        0x00000004U
@@ -23865,9 +23865,9 @@
     * (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= s
     * d1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_69_L2_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_69_L2_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_69_L2_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_69_L2_SEL_MASK
 #define IOU_SLCR_MIO_PIN_69_L2_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT                       3
 #define IOU_SLCR_MIO_PIN_69_L2_SEL_MASK                        0x00000018U
@@ -23882,9 +23882,9 @@
     * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
     * 7= trace, Output, tracedq[15]- (Trace Port Databus)
 */
-#undef IOU_SLCR_MIO_PIN_69_L3_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_69_L3_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_69_L3_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_69_L3_SEL_MASK
 #define IOU_SLCR_MIO_PIN_69_L3_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT                       5
 #define IOU_SLCR_MIO_PIN_69_L3_SEL_MASK                        0x000000E0U
@@ -23893,9 +23893,9 @@
 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_c
     * lk- (RX RGMII clock)
 */
-#undef IOU_SLCR_MIO_PIN_70_L0_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_70_L0_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_70_L0_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_70_L0_SEL_MASK
 #define IOU_SLCR_MIO_PIN_70_L0_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT                       1
 #define IOU_SLCR_MIO_PIN_70_L0_SEL_MASK                        0x00000002U
@@ -23904,9 +23904,9 @@
 * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp-
     *  (Asserted to end or interrupt transfers)
 */
-#undef IOU_SLCR_MIO_PIN_70_L1_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_70_L1_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_70_L1_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_70_L1_SEL_MASK
 #define IOU_SLCR_MIO_PIN_70_L1_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT                       2
 #define IOU_SLCR_MIO_PIN_70_L1_SEL_MASK                        0x00000004U
@@ -23916,9 +23916,9 @@
     * (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= s
     * d1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_70_L2_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_70_L2_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_70_L2_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_70_L2_SEL_MASK
 #define IOU_SLCR_MIO_PIN_70_L2_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT                       3
 #define IOU_SLCR_MIO_PIN_70_L2_SEL_MASK                        0x00000018U
@@ -23933,9 +23933,9 @@
     * TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not U
     * sed
 */
-#undef IOU_SLCR_MIO_PIN_70_L3_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_70_L3_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_70_L3_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_70_L3_SEL_MASK
 #define IOU_SLCR_MIO_PIN_70_L3_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT                       5
 #define IOU_SLCR_MIO_PIN_70_L3_SEL_MASK                        0x000000E0U
@@ -23944,9 +23944,9 @@
 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[
     * 0]- (RX RGMII data)
 */
-#undef IOU_SLCR_MIO_PIN_71_L0_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_71_L0_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_71_L0_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_71_L0_SEL_MASK
 #define IOU_SLCR_MIO_PIN_71_L0_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT                       1
 #define IOU_SLCR_MIO_PIN_71_L0_SEL_MASK                        0x00000002U
@@ -23956,9 +23956,9 @@
     * ta[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[3]- (ULPI data
     *  bus)
 */
-#undef IOU_SLCR_MIO_PIN_71_L1_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_71_L1_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_71_L1_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_71_L1_SEL_MASK
 #define IOU_SLCR_MIO_PIN_71_L1_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT                       2
 #define IOU_SLCR_MIO_PIN_71_L1_SEL_MASK                        0x00000004U
@@ -23969,9 +23969,9 @@
     * d1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_ou
     * t[0]- (8-bit Data bus) 3= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_71_L2_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_71_L2_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_71_L2_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_71_L2_SEL_MASK
 #define IOU_SLCR_MIO_PIN_71_L2_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT                       3
 #define IOU_SLCR_MIO_PIN_71_L2_SEL_MASK                        0x00000018U
@@ -23985,9 +23985,9 @@
     * Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6=
     * ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_71_L3_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_71_L3_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_71_L3_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_71_L3_SEL_MASK
 #define IOU_SLCR_MIO_PIN_71_L3_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT                       5
 #define IOU_SLCR_MIO_PIN_71_L3_SEL_MASK                        0x000000E0U
@@ -23996,9 +23996,9 @@
 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[
     * 1]- (RX RGMII data)
 */
-#undef IOU_SLCR_MIO_PIN_72_L0_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_72_L0_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_72_L0_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_72_L0_SEL_MASK
 #define IOU_SLCR_MIO_PIN_72_L0_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT                       1
 #define IOU_SLCR_MIO_PIN_72_L0_SEL_MASK                        0x00000002U
@@ -24008,9 +24008,9 @@
     * ta[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data
     *  bus)
 */
-#undef IOU_SLCR_MIO_PIN_72_L1_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_72_L1_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_72_L1_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_72_L1_SEL_MASK
 #define IOU_SLCR_MIO_PIN_72_L1_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT                       2
 #define IOU_SLCR_MIO_PIN_72_L1_SEL_MASK                        0x00000004U
@@ -24021,9 +24021,9 @@
     * d1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_ou
     * t[1]- (8-bit Data bus) 3= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_72_L2_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_72_L2_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_72_L2_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_72_L2_SEL_MASK
 #define IOU_SLCR_MIO_PIN_72_L2_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT                       3
 #define IOU_SLCR_MIO_PIN_72_L2_SEL_MASK                        0x00000018U
@@ -24037,9 +24037,9 @@
     * ter Selects) 5= Not Used 6= ua1, Output, ua1_txd- (UART transmitter seri
     * al output) 7= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_72_L3_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_72_L3_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_72_L3_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_72_L3_SEL_MASK
 #define IOU_SLCR_MIO_PIN_72_L3_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT                       5
 #define IOU_SLCR_MIO_PIN_72_L3_SEL_MASK                        0x000000E0U
@@ -24048,9 +24048,9 @@
 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[
     * 2]- (RX RGMII data)
 */
-#undef IOU_SLCR_MIO_PIN_73_L0_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_73_L0_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_73_L0_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_73_L0_SEL_MASK
 #define IOU_SLCR_MIO_PIN_73_L0_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT                       1
 #define IOU_SLCR_MIO_PIN_73_L0_SEL_MASK                        0x00000002U
@@ -24060,9 +24060,9 @@
     * ta[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data
     *  bus)
 */
-#undef IOU_SLCR_MIO_PIN_73_L1_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_73_L1_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_73_L1_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_73_L1_SEL_MASK
 #define IOU_SLCR_MIO_PIN_73_L1_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT                       2
 #define IOU_SLCR_MIO_PIN_73_L1_SEL_MASK                        0x00000004U
@@ -24073,9 +24073,9 @@
     * d1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_ou
     * t[2]- (8-bit Data bus) 3= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_73_L2_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_73_L2_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_73_L2_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_73_L2_SEL_MASK
 #define IOU_SLCR_MIO_PIN_73_L2_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT                       3
 #define IOU_SLCR_MIO_PIN_73_L2_SEL_MASK                        0x00000018U
@@ -24089,9 +24089,9 @@
     *  Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= Not
     *  Used 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_73_L3_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_73_L3_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_73_L3_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_73_L3_SEL_MASK
 #define IOU_SLCR_MIO_PIN_73_L3_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT                       5
 #define IOU_SLCR_MIO_PIN_73_L3_SEL_MASK                        0x000000E0U
@@ -24100,9 +24100,9 @@
 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[
     * 3]- (RX RGMII data)
 */
-#undef IOU_SLCR_MIO_PIN_74_L0_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_74_L0_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_74_L0_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_74_L0_SEL_MASK
 #define IOU_SLCR_MIO_PIN_74_L0_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT                       1
 #define IOU_SLCR_MIO_PIN_74_L0_SEL_MASK                        0x00000002U
@@ -24112,9 +24112,9 @@
     * ta[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[6]- (ULPI data
     *  bus)
 */
-#undef IOU_SLCR_MIO_PIN_74_L1_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_74_L1_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_74_L1_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_74_L1_SEL_MASK
 #define IOU_SLCR_MIO_PIN_74_L1_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT                       2
 #define IOU_SLCR_MIO_PIN_74_L1_SEL_MASK                        0x00000004U
@@ -24125,9 +24125,9 @@
     * d1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_ou
     * t[3]- (8-bit Data bus) 3= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_74_L2_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_74_L2_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_74_L2_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_74_L2_SEL_MASK
 #define IOU_SLCR_MIO_PIN_74_L2_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT                       3
 #define IOU_SLCR_MIO_PIN_74_L2_SEL_MASK                        0x00000018U
@@ -24141,9 +24141,9 @@
     * i1, Output, spi1_so- (MISO signal) 5= Not Used 6= ua0, Input, ua0_rxd- (
     * UART receiver serial input) 7= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_74_L3_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_74_L3_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_74_L3_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_74_L3_SEL_MASK
 #define IOU_SLCR_MIO_PIN_74_L3_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT                       5
 #define IOU_SLCR_MIO_PIN_74_L3_SEL_MASK                        0x000000E0U
@@ -24152,9 +24152,9 @@
 * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_c
     * tl- (RX RGMII control )
 */
-#undef IOU_SLCR_MIO_PIN_75_L0_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_75_L0_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_75_L0_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_75_L0_SEL_MASK
 #define IOU_SLCR_MIO_PIN_75_L0_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT                       1
 #define IOU_SLCR_MIO_PIN_75_L0_SEL_MASK                        0x00000002U
@@ -24164,9 +24164,9 @@
     * ta[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[7]- (ULPI data
     *  bus)
 */
-#undef IOU_SLCR_MIO_PIN_75_L1_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_75_L1_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_75_L1_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_75_L1_SEL_MASK
 #define IOU_SLCR_MIO_PIN_75_L1_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT                       2
 #define IOU_SLCR_MIO_PIN_75_L1_SEL_MASK                        0x00000004U
@@ -24176,9 +24176,9 @@
     * (SD card bus power) 2= sd1, Input, sd1_cmd_in- (Command Indicator) = sd1
     * , Output, sdio1_cmd_out- (Command Indicator) 3= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_75_L2_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_75_L2_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_75_L2_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_75_L2_SEL_MASK
 #define IOU_SLCR_MIO_PIN_75_L2_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT                       3
 #define IOU_SLCR_MIO_PIN_75_L2_SEL_MASK                        0x00000018U
@@ -24192,9 +24192,9 @@
     * 4= spi1, Input, spi1_si- (MOSI signal) 5= Not Used 6= ua0, Output, ua0_t
     * xd- (UART transmitter serial output) 7= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_75_L3_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_75_L3_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_75_L3_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_75_L3_SEL_MASK
 #define IOU_SLCR_MIO_PIN_75_L3_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT                       5
 #define IOU_SLCR_MIO_PIN_75_L3_SEL_MASK                        0x000000E0U
@@ -24202,9 +24202,9 @@
 /*
 * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_76_L0_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_76_L0_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_76_L0_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_76_L0_SEL_MASK
 #define IOU_SLCR_MIO_PIN_76_L0_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT                       1
 #define IOU_SLCR_MIO_PIN_76_L0_SEL_MASK                        0x00000002U
@@ -24212,9 +24212,9 @@
 /*
 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_76_L1_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_76_L1_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_76_L1_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_76_L1_SEL_MASK
 #define IOU_SLCR_MIO_PIN_76_L1_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT                       2
 #define IOU_SLCR_MIO_PIN_76_L1_SEL_MASK                        0x00000004U
@@ -24224,9 +24224,9 @@
     * rd write protect from connector) 2= sd1, Output, sdio1_clk_out- (SDSDIO
     * clock) 3= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_76_L2_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_76_L2_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_76_L2_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_76_L2_SEL_MASK
 #define IOU_SLCR_MIO_PIN_76_L2_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT                       3
 #define IOU_SLCR_MIO_PIN_76_L2_SEL_MASK                        0x00000018U
@@ -24239,9 +24239,9 @@
     * O Clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= mdio2, Output, gem2
     * _mdc- (MDIO Clock) 6= mdio3, Output, gem3_mdc- (MDIO Clock) 7= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_76_L3_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_76_L3_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_76_L3_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_76_L3_SEL_MASK
 #define IOU_SLCR_MIO_PIN_76_L3_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT                       5
 #define IOU_SLCR_MIO_PIN_76_L3_SEL_MASK                        0x000000E0U
@@ -24249,9 +24249,9 @@
 /*
 * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_77_L0_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_77_L0_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_77_L0_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_77_L0_SEL_MASK
 #define IOU_SLCR_MIO_PIN_77_L0_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT                       1
 #define IOU_SLCR_MIO_PIN_77_L0_SEL_MASK                        0x00000002U
@@ -24259,9 +24259,9 @@
 /*
 * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_77_L1_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_77_L1_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_77_L1_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_77_L1_SEL_MASK
 #define IOU_SLCR_MIO_PIN_77_L1_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT                       2
 #define IOU_SLCR_MIO_PIN_77_L1_SEL_MASK                        0x00000004U
@@ -24270,9 +24270,9 @@
 * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Input, sdio
     * 1_cd_n- (SD card detect from connector) 3= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_77_L2_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_77_L2_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_77_L2_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_77_L2_SEL_MASK
 #define IOU_SLCR_MIO_PIN_77_L2_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT                       3
 #define IOU_SLCR_MIO_PIN_77_L2_SEL_MASK                        0x00000018U
@@ -24288,9 +24288,9 @@
     * t- (MDIO Data) 6= mdio3, Input, gem3_mdio_in- (MDIO Data) 6= mdio3, Outp
     * ut, gem3_mdio_out- (MDIO Data) 7= Not Used
 */
-#undef IOU_SLCR_MIO_PIN_77_L3_SEL_DEFVAL 
-#undef IOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT 
-#undef IOU_SLCR_MIO_PIN_77_L3_SEL_MASK 
+#undef IOU_SLCR_MIO_PIN_77_L3_SEL_DEFVAL
+#undef IOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT
+#undef IOU_SLCR_MIO_PIN_77_L3_SEL_MASK
 #define IOU_SLCR_MIO_PIN_77_L3_SEL_DEFVAL                      0x00000000
 #define IOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT                       5
 #define IOU_SLCR_MIO_PIN_77_L3_SEL_MASK                        0x000000E0U
@@ -24298,9 +24298,9 @@
 /*
 * Master Tri-state Enable for pin 0, active high
 */
-#undef IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_DEFVAL 
-#undef IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT 
-#undef IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_DEFVAL
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK
 #define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_DEFVAL                0xFFFFFFFF
 #define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT                 0
 #define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK                  0x00000001U
@@ -24308,9 +24308,9 @@
 /*
 * Master Tri-state Enable for pin 1, active high
 */
-#undef IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_DEFVAL 
-#undef IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT 
-#undef IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_DEFVAL
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK
 #define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_DEFVAL                0xFFFFFFFF
 #define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT                 1
 #define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK                  0x00000002U
@@ -24318,9 +24318,9 @@
 /*
 * Master Tri-state Enable for pin 2, active high
 */
-#undef IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_DEFVAL 
-#undef IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT 
-#undef IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_DEFVAL
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK
 #define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_DEFVAL                0xFFFFFFFF
 #define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT                 2
 #define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK                  0x00000004U
@@ -24328,9 +24328,9 @@
 /*
 * Master Tri-state Enable for pin 3, active high
 */
-#undef IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_DEFVAL 
-#undef IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT 
-#undef IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_DEFVAL
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK
 #define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_DEFVAL                0xFFFFFFFF
 #define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT                 3
 #define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK                  0x00000008U
@@ -24338,9 +24338,9 @@
 /*
 * Master Tri-state Enable for pin 4, active high
 */
-#undef IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_DEFVAL 
-#undef IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT 
-#undef IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_DEFVAL
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK
 #define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_DEFVAL                0xFFFFFFFF
 #define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT                 4
 #define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK                  0x00000010U
@@ -24348,9 +24348,9 @@
 /*
 * Master Tri-state Enable for pin 5, active high
 */
-#undef IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_DEFVAL 
-#undef IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT 
-#undef IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_DEFVAL
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK
 #define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_DEFVAL                0xFFFFFFFF
 #define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT                 5
 #define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK                  0x00000020U
@@ -24358,9 +24358,9 @@
 /*
 * Master Tri-state Enable for pin 16, active high
 */
-#undef IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_DEFVAL 
-#undef IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT 
-#undef IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_DEFVAL
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK
 #define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_DEFVAL                0xFFFFFFFF
 #define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT                 16
 #define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK                  0x00010000U
@@ -24368,9 +24368,9 @@
 /*
 * Master Tri-state Enable for pin 17, active high
 */
-#undef IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_DEFVAL 
-#undef IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT 
-#undef IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_DEFVAL
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK
 #define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_DEFVAL                0xFFFFFFFF
 #define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT                 17
 #define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK                  0x00020000U
@@ -24378,9 +24378,9 @@
 /*
 * Master Tri-state Enable for pin 18, active high
 */
-#undef IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_DEFVAL 
-#undef IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT 
-#undef IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_DEFVAL
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK
 #define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_DEFVAL                0xFFFFFFFF
 #define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT                 18
 #define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK                  0x00040000U
@@ -24388,9 +24388,9 @@
 /*
 * Master Tri-state Enable for pin 19, active high
 */
-#undef IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_DEFVAL 
-#undef IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT 
-#undef IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_DEFVAL
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK
 #define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_DEFVAL                0xFFFFFFFF
 #define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT                 19
 #define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK                  0x00080000U
@@ -24398,9 +24398,9 @@
 /*
 * Master Tri-state Enable for pin 20, active high
 */
-#undef IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_DEFVAL 
-#undef IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT 
-#undef IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_DEFVAL
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK
 #define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_DEFVAL                0xFFFFFFFF
 #define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT                 20
 #define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK                  0x00100000U
@@ -24408,9 +24408,9 @@
 /*
 * Master Tri-state Enable for pin 21, active high
 */
-#undef IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_DEFVAL 
-#undef IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT 
-#undef IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_DEFVAL
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK
 #define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_DEFVAL                0xFFFFFFFF
 #define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT                 21
 #define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK                  0x00200000U
@@ -24418,9 +24418,9 @@
 /*
 * Master Tri-state Enable for pin 24, active high
 */
-#undef IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_DEFVAL 
-#undef IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT 
-#undef IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_DEFVAL
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK
 #define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_DEFVAL                0xFFFFFFFF
 #define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT                 24
 #define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK                  0x01000000U
@@ -24428,9 +24428,9 @@
 /*
 * Master Tri-state Enable for pin 25, active high
 */
-#undef IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_DEFVAL 
-#undef IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT 
-#undef IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_DEFVAL
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK
 #define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_DEFVAL                0xFFFFFFFF
 #define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT                 25
 #define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK                  0x02000000U
@@ -24438,9 +24438,9 @@
 /*
 * Master Tri-state Enable for pin 27, active high
 */
-#undef IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_DEFVAL 
-#undef IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT 
-#undef IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_DEFVAL
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK
 #define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_DEFVAL                0xFFFFFFFF
 #define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT                 27
 #define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK                  0x08000000U
@@ -24448,9 +24448,9 @@
 /*
 * Master Tri-state Enable for pin 28, active high
 */
-#undef IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_DEFVAL 
-#undef IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT 
-#undef IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_DEFVAL
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK
 #define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_DEFVAL                0xFFFFFFFF
 #define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT                 28
 #define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK                  0x10000000U
@@ -24458,9 +24458,9 @@
 /*
 * Master Tri-state Enable for pin 29, active high
 */
-#undef IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_DEFVAL 
-#undef IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT 
-#undef IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_DEFVAL
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK
 #define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_DEFVAL                0xFFFFFFFF
 #define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT                 29
 #define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK                  0x20000000U
@@ -24468,9 +24468,9 @@
 /*
 * Master Tri-state Enable for pin 30, active high
 */
-#undef IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_DEFVAL 
-#undef IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT 
-#undef IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_DEFVAL
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK
 #define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_DEFVAL                0xFFFFFFFF
 #define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT                 30
 #define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK                  0x40000000U
@@ -24478,9 +24478,9 @@
 /*
 * Master Tri-state Enable for pin 45, active high
 */
-#undef IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_DEFVAL 
-#undef IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT 
-#undef IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_DEFVAL
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK
 #define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_DEFVAL                0xFFFFFFFF
 #define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT                 13
 #define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK                  0x00002000U
@@ -24488,9 +24488,9 @@
 /*
 * Master Tri-state Enable for pin 46, active high
 */
-#undef IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_DEFVAL 
-#undef IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT 
-#undef IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_DEFVAL
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK
 #define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_DEFVAL                0xFFFFFFFF
 #define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT                 14
 #define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK                  0x00004000U
@@ -24498,9 +24498,9 @@
 /*
 * Master Tri-state Enable for pin 47, active high
 */
-#undef IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_DEFVAL 
-#undef IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT 
-#undef IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_DEFVAL
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK
 #define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_DEFVAL                0xFFFFFFFF
 #define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT                 15
 #define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK                  0x00008000U
@@ -24508,9 +24508,9 @@
 /*
 * Master Tri-state Enable for pin 48, active high
 */
-#undef IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_DEFVAL 
-#undef IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT 
-#undef IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_DEFVAL
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK
 #define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_DEFVAL                0xFFFFFFFF
 #define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT                 16
 #define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK                  0x00010000U
@@ -24518,9 +24518,9 @@
 /*
 * Master Tri-state Enable for pin 49, active high
 */
-#undef IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_DEFVAL 
-#undef IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT 
-#undef IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_DEFVAL
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK
 #define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_DEFVAL                0xFFFFFFFF
 #define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT                 17
 #define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK                  0x00020000U
@@ -24528,9 +24528,9 @@
 /*
 * Master Tri-state Enable for pin 50, active high
 */
-#undef IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_DEFVAL 
-#undef IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT 
-#undef IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_DEFVAL
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK
 #define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_DEFVAL                0xFFFFFFFF
 #define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT                 18
 #define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK                  0x00040000U
@@ -24538,9 +24538,9 @@
 /*
 * Master Tri-state Enable for pin 51, active high
 */
-#undef IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_DEFVAL 
-#undef IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT 
-#undef IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_DEFVAL
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK
 #define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_DEFVAL                0xFFFFFFFF
 #define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT                 19
 #define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK                  0x00080000U
@@ -24548,9 +24548,9 @@
 /*
 * Master Tri-state Enable for pin 52, active high
 */
-#undef IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_DEFVAL 
-#undef IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT 
-#undef IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_DEFVAL
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK
 #define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_DEFVAL                0xFFFFFFFF
 #define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT                 20
 #define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK                  0x00100000U
@@ -24558,9 +24558,9 @@
 /*
 * Master Tri-state Enable for pin 53, active high
 */
-#undef IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_DEFVAL 
-#undef IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT 
-#undef IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_DEFVAL
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK
 #define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_DEFVAL                0xFFFFFFFF
 #define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT                 21
 #define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK                  0x00200000U
@@ -24568,9 +24568,9 @@
 /*
 * Master Tri-state Enable for pin 54, active high
 */
-#undef IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_DEFVAL 
-#undef IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT 
-#undef IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_DEFVAL
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK
 #define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_DEFVAL                0xFFFFFFFF
 #define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT                 22
 #define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK                  0x00400000U
@@ -24578,9 +24578,9 @@
 /*
 * Master Tri-state Enable for pin 55, active high
 */
-#undef IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_DEFVAL 
-#undef IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT 
-#undef IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_DEFVAL
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK
 #define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_DEFVAL                0xFFFFFFFF
 #define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT                 23
 #define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK                  0x00800000U
@@ -24588,9 +24588,9 @@
 /*
 * Master Tri-state Enable for pin 56, active high
 */
-#undef IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_DEFVAL 
-#undef IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT 
-#undef IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_DEFVAL
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK
 #define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_DEFVAL                0xFFFFFFFF
 #define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT                 24
 #define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK                  0x01000000U
@@ -24598,9 +24598,9 @@
 /*
 * Master Tri-state Enable for pin 57, active high
 */
-#undef IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_DEFVAL 
-#undef IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT 
-#undef IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_DEFVAL
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK
 #define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_DEFVAL                0xFFFFFFFF
 #define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT                 25
 #define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK                  0x02000000U
@@ -24608,9 +24608,9 @@
 /*
 * Master Tri-state Enable for pin 58, active high
 */
-#undef IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_DEFVAL 
-#undef IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT 
-#undef IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_DEFVAL
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK
 #define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_DEFVAL                0xFFFFFFFF
 #define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT                 26
 #define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK                  0x04000000U
@@ -24618,9 +24618,9 @@
 /*
 * Master Tri-state Enable for pin 59, active high
 */
-#undef IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_DEFVAL 
-#undef IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT 
-#undef IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_DEFVAL
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK
 #define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_DEFVAL                0xFFFFFFFF
 #define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT                 27
 #define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK                  0x08000000U
@@ -24628,9 +24628,9 @@
 /*
 * Master Tri-state Enable for pin 60, active high
 */
-#undef IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_DEFVAL 
-#undef IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT 
-#undef IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_DEFVAL
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK
 #define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_DEFVAL                0xFFFFFFFF
 #define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT                 28
 #define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK                  0x10000000U
@@ -24638,9 +24638,9 @@
 /*
 * Master Tri-state Enable for pin 61, active high
 */
-#undef IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_DEFVAL 
-#undef IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT 
-#undef IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_DEFVAL
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK
 #define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_DEFVAL                0xFFFFFFFF
 #define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT                 29
 #define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK                  0x20000000U
@@ -24648,9 +24648,9 @@
 /*
 * Master Tri-state Enable for pin 62, active high
 */
-#undef IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_DEFVAL 
-#undef IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT 
-#undef IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_DEFVAL
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK
 #define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_DEFVAL                0xFFFFFFFF
 #define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT                 30
 #define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK                  0x40000000U
@@ -24658,9 +24658,9 @@
 /*
 * Master Tri-state Enable for pin 63, active high
 */
-#undef IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_DEFVAL 
-#undef IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT 
-#undef IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_DEFVAL
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK
 #define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_DEFVAL                0xFFFFFFFF
 #define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT                 31
 #define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK                  0x80000000U
@@ -24668,9 +24668,9 @@
 /*
 * Master Tri-state Enable for pin 64, active high
 */
-#undef IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_DEFVAL 
-#undef IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT 
-#undef IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_DEFVAL
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK
 #define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_DEFVAL                0x00003FFF
 #define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT                 0
 #define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK                  0x00000001U
@@ -24678,9 +24678,9 @@
 /*
 * Master Tri-state Enable for pin 65, active high
 */
-#undef IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_DEFVAL 
-#undef IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT 
-#undef IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_DEFVAL
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK
 #define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_DEFVAL                0x00003FFF
 #define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT                 1
 #define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK                  0x00000002U
@@ -24688,9 +24688,9 @@
 /*
 * Master Tri-state Enable for pin 66, active high
 */
-#undef IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_DEFVAL 
-#undef IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT 
-#undef IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_DEFVAL
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK
 #define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_DEFVAL                0x00003FFF
 #define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT                 2
 #define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK                  0x00000004U
@@ -24698,9 +24698,9 @@
 /*
 * Master Tri-state Enable for pin 67, active high
 */
-#undef IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_DEFVAL 
-#undef IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT 
-#undef IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_DEFVAL
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK
 #define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_DEFVAL                0x00003FFF
 #define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT                 3
 #define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK                  0x00000008U
@@ -24708,9 +24708,9 @@
 /*
 * Master Tri-state Enable for pin 68, active high
 */
-#undef IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_DEFVAL 
-#undef IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT 
-#undef IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_DEFVAL
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK
 #define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_DEFVAL                0x00003FFF
 #define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT                 4
 #define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK                  0x00000010U
@@ -24718,9 +24718,9 @@
 /*
 * Master Tri-state Enable for pin 69, active high
 */
-#undef IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_DEFVAL 
-#undef IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT 
-#undef IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_DEFVAL
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK
 #define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_DEFVAL                0x00003FFF
 #define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT                 5
 #define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK                  0x00000020U
@@ -24728,9 +24728,9 @@
 /*
 * Master Tri-state Enable for pin 70, active high
 */
-#undef IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_DEFVAL 
-#undef IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT 
-#undef IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_DEFVAL
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK
 #define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_DEFVAL                0x00003FFF
 #define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT                 6
 #define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK                  0x00000040U
@@ -24738,9 +24738,9 @@
 /*
 * Master Tri-state Enable for pin 71, active high
 */
-#undef IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_DEFVAL 
-#undef IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT 
-#undef IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_DEFVAL
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK
 #define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_DEFVAL                0x00003FFF
 #define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT                 7
 #define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK                  0x00000080U
@@ -24748,9 +24748,9 @@
 /*
 * Master Tri-state Enable for pin 72, active high
 */
-#undef IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_DEFVAL 
-#undef IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT 
-#undef IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_DEFVAL
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK
 #define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_DEFVAL                0x00003FFF
 #define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT                 8
 #define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK                  0x00000100U
@@ -24758,9 +24758,9 @@
 /*
 * Master Tri-state Enable for pin 73, active high
 */
-#undef IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_DEFVAL 
-#undef IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT 
-#undef IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_DEFVAL
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK
 #define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_DEFVAL                0x00003FFF
 #define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT                 9
 #define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK                  0x00000200U
@@ -24768,9 +24768,9 @@
 /*
 * Master Tri-state Enable for pin 74, active high
 */
-#undef IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_DEFVAL 
-#undef IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT 
-#undef IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_DEFVAL
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK
 #define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_DEFVAL                0x00003FFF
 #define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT                 10
 #define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK                  0x00000400U
@@ -24778,9 +24778,9 @@
 /*
 * Master Tri-state Enable for pin 75, active high
 */
-#undef IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_DEFVAL 
-#undef IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT 
-#undef IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_DEFVAL
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK
 #define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_DEFVAL                0x00003FFF
 #define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT                 11
 #define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK                  0x00000800U
@@ -24788,9 +24788,9 @@
 /*
 * Master Tri-state Enable for pin 76, active high
 */
-#undef IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_DEFVAL 
-#undef IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT 
-#undef IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_DEFVAL
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK
 #define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_DEFVAL                0x00003FFF
 #define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT                 12
 #define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK                  0x00001000U
@@ -24798,9 +24798,9 @@
 /*
 * Master Tri-state Enable for pin 77, active high
 */
-#undef IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_DEFVAL 
-#undef IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT 
-#undef IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_DEFVAL
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK
 #define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_DEFVAL                0x00003FFF
 #define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT                 13
 #define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK                  0x00002000U
@@ -24808,4680 +24808,4680 @@
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_MASK 
-#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_DEFVAL               
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_SHIFT
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_MASK
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_DEFVAL
 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_SHIFT                0
 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_MASK                 0x00000001U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_MASK 
-#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_DEFVAL               
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_SHIFT
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_MASK
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_DEFVAL
 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_SHIFT                1
 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_MASK                 0x00000002U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_MASK 
-#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_DEFVAL               
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_SHIFT
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_MASK
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_DEFVAL
 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_SHIFT                2
 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_MASK                 0x00000004U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_MASK 
-#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_DEFVAL               
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_SHIFT
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_MASK
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_DEFVAL
 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_SHIFT                3
 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_MASK                 0x00000008U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_MASK 
-#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_DEFVAL               
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_SHIFT
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_MASK
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_DEFVAL
 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_SHIFT                4
 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_MASK                 0x00000010U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_MASK 
-#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_DEFVAL               
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_SHIFT
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_MASK
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_DEFVAL
 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_SHIFT                5
 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_MASK                 0x00000020U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_MASK 
-#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_DEFVAL               
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_SHIFT
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_MASK
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_DEFVAL
 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_SHIFT                6
 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_MASK                 0x00000040U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_MASK 
-#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_DEFVAL               
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_SHIFT
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_MASK
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_DEFVAL
 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_SHIFT                7
 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_MASK                 0x00000080U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_MASK 
-#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_DEFVAL               
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_SHIFT
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_MASK
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_DEFVAL
 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_SHIFT                8
 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_MASK                 0x00000100U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_MASK 
-#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_DEFVAL               
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_SHIFT
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_MASK
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_DEFVAL
 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_SHIFT                9
 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_MASK                 0x00000200U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_MASK 
-#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_DEFVAL              
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_SHIFT
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_MASK
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_DEFVAL
 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_SHIFT               10
 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_MASK                0x00000400U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_MASK 
-#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_DEFVAL              
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_SHIFT
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_MASK
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_DEFVAL
 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_SHIFT               11
 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_MASK                0x00000800U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_MASK 
-#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_DEFVAL              
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_SHIFT
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_MASK
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_DEFVAL
 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_SHIFT               12
 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_MASK                0x00001000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_MASK 
-#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_DEFVAL              
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_SHIFT
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_MASK
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_DEFVAL
 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_SHIFT               13
 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_MASK                0x00002000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_MASK 
-#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_DEFVAL              
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_SHIFT
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_MASK
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_DEFVAL
 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_SHIFT               14
 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_MASK                0x00004000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_MASK 
-#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_DEFVAL              
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_SHIFT
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_MASK
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_DEFVAL
 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_SHIFT               15
 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_MASK                0x00008000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_MASK 
-#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_DEFVAL              
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_SHIFT
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_MASK
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_DEFVAL
 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_SHIFT               16
 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_MASK                0x00010000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_MASK 
-#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_DEFVAL              
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_SHIFT
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_MASK
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_DEFVAL
 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_SHIFT               17
 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_MASK                0x00020000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_MASK 
-#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_DEFVAL              
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_SHIFT
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_MASK
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_DEFVAL
 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_SHIFT               18
 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_MASK                0x00040000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_MASK 
-#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_DEFVAL              
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_SHIFT
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_MASK
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_DEFVAL
 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_SHIFT               19
 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_MASK                0x00080000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_MASK 
-#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_DEFVAL              
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_SHIFT
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_MASK
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_DEFVAL
 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_SHIFT               20
 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_MASK                0x00100000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_MASK 
-#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_DEFVAL              
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_SHIFT
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_MASK
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_DEFVAL
 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_SHIFT               21
 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_MASK                0x00200000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_MASK 
-#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_DEFVAL              
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_SHIFT
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_MASK
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_DEFVAL
 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_SHIFT               22
 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_MASK                0x00400000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_MASK 
-#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_DEFVAL              
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_SHIFT
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_MASK
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_DEFVAL
 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_SHIFT               23
 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_MASK                0x00800000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_MASK 
-#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_DEFVAL              
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_SHIFT
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_MASK
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_DEFVAL
 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_SHIFT               24
 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_MASK                0x01000000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_MASK 
-#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_DEFVAL              
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_SHIFT
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_MASK
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_DEFVAL
 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_SHIFT               25
 #define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_MASK                0x02000000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_MASK 
-#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_DEFVAL               
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_SHIFT
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_MASK
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_DEFVAL
 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_SHIFT                0
 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_MASK                 0x00000001U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_MASK 
-#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_DEFVAL               
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_SHIFT
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_MASK
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_DEFVAL
 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_SHIFT                1
 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_MASK                 0x00000002U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_MASK 
-#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_DEFVAL               
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_SHIFT
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_MASK
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_DEFVAL
 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_SHIFT                2
 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_MASK                 0x00000004U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_MASK 
-#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_DEFVAL               
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_SHIFT
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_MASK
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_DEFVAL
 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_SHIFT                3
 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_MASK                 0x00000008U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_MASK 
-#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_DEFVAL               
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_SHIFT
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_MASK
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_DEFVAL
 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_SHIFT                4
 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_MASK                 0x00000010U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_MASK 
-#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_DEFVAL               
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_SHIFT
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_MASK
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_DEFVAL
 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_SHIFT                5
 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_MASK                 0x00000020U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_MASK 
-#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_DEFVAL               
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_SHIFT
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_MASK
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_DEFVAL
 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_SHIFT                6
 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_MASK                 0x00000040U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_MASK 
-#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_DEFVAL               
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_SHIFT
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_MASK
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_DEFVAL
 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_SHIFT                7
 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_MASK                 0x00000080U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_MASK 
-#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_DEFVAL               
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_SHIFT
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_MASK
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_DEFVAL
 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_SHIFT                8
 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_MASK                 0x00000100U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_MASK 
-#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_DEFVAL               
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_SHIFT
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_MASK
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_DEFVAL
 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_SHIFT                9
 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_MASK                 0x00000200U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_MASK 
-#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_DEFVAL              
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_SHIFT
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_MASK
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_DEFVAL
 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_SHIFT               10
 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_MASK                0x00000400U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_MASK 
-#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_DEFVAL              
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_SHIFT
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_MASK
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_DEFVAL
 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_SHIFT               11
 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_MASK                0x00000800U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_MASK 
-#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_DEFVAL              
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_SHIFT
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_MASK
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_DEFVAL
 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_SHIFT               12
 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_MASK                0x00001000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_MASK 
-#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_DEFVAL              
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_SHIFT
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_MASK
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_DEFVAL
 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_SHIFT               13
 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_MASK                0x00002000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_MASK 
-#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_DEFVAL              
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_SHIFT
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_MASK
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_DEFVAL
 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_SHIFT               14
 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_MASK                0x00004000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_MASK 
-#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_DEFVAL              
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_SHIFT
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_MASK
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_DEFVAL
 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_SHIFT               15
 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_MASK                0x00008000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_MASK 
-#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_DEFVAL              
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_SHIFT
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_MASK
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_DEFVAL
 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_SHIFT               16
 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_MASK                0x00010000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_MASK 
-#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_DEFVAL              
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_SHIFT
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_MASK
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_DEFVAL
 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_SHIFT               17
 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_MASK                0x00020000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_MASK 
-#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_DEFVAL              
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_SHIFT
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_MASK
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_DEFVAL
 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_SHIFT               18
 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_MASK                0x00040000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_MASK 
-#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_DEFVAL              
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_SHIFT
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_MASK
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_DEFVAL
 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_SHIFT               19
 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_MASK                0x00080000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_MASK 
-#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_DEFVAL              
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_SHIFT
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_MASK
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_DEFVAL
 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_SHIFT               20
 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_MASK                0x00100000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_MASK 
-#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_DEFVAL              
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_SHIFT
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_MASK
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_DEFVAL
 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_SHIFT               21
 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_MASK                0x00200000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_MASK 
-#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_DEFVAL              
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_SHIFT
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_MASK
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_DEFVAL
 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_SHIFT               22
 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_MASK                0x00400000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_MASK 
-#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_DEFVAL              
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_SHIFT
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_MASK
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_DEFVAL
 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_SHIFT               23
 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_MASK                0x00800000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_MASK 
-#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_DEFVAL              
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_SHIFT
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_MASK
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_DEFVAL
 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_SHIFT               24
 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_MASK                0x01000000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_MASK 
-#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_DEFVAL              
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_SHIFT
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_MASK
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_DEFVAL
 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_SHIFT               25
 #define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_MASK                0x02000000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK 
-#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL       
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL
 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT        0
 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK         0x00000001U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK 
-#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL       
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL
 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT        1
 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK         0x00000002U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK 
-#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL       
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL
 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT        2
 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK         0x00000004U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK 
-#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL       
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL
 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT        3
 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK         0x00000008U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK 
-#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL       
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL
 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT        4
 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK         0x00000010U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK 
-#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL       
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL
 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT        5
 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK         0x00000020U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK 
-#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL       
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL
 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT        6
 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK         0x00000040U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK 
-#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL       
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL
 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT        7
 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK         0x00000080U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK 
-#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL       
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL
 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT        8
 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK         0x00000100U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK 
-#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL       
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL
 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT        9
 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK         0x00000200U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK 
-#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL      
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL
 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT       10
 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK        0x00000400U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK 
-#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL      
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL
 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT       11
 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK        0x00000800U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK 
-#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL      
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL
 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT       12
 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK        0x00001000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK 
-#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL      
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL
 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT       13
 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK        0x00002000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK 
-#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL      
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL
 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT       14
 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK        0x00004000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK 
-#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL      
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL
 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT       15
 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK        0x00008000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK 
-#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL      
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL
 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT       16
 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK        0x00010000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK 
-#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL      
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL
 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT       17
 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK        0x00020000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK 
-#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL      
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL
 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT       18
 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK        0x00040000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK 
-#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL      
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL
 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT       19
 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK        0x00080000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK 
-#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL      
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL
 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT       20
 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK        0x00100000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK 
-#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL      
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL
 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT       21
 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK        0x00200000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK 
-#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL      
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL
 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT       22
 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK        0x00400000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK 
-#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL      
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL
 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT       23
 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK        0x00800000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK 
-#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL      
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL
 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT       24
 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK        0x01000000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK 
-#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL      
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL
 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT       25
 #define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK        0x02000000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK 
-#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL      
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL
 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT       0
 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK        0x00000001U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK 
-#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL      
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL
 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT       1
 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK        0x00000002U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK 
-#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL      
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL
 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT       2
 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK        0x00000004U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK 
-#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL      
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL
 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT       3
 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK        0x00000008U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK 
-#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL      
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL
 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT       4
 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK        0x00000010U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK 
-#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL      
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL
 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT       5
 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK        0x00000020U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK 
-#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL      
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL
 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT       6
 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK        0x00000040U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK 
-#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL      
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL
 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT       7
 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK        0x00000080U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK 
-#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL      
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL
 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT       8
 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK        0x00000100U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK 
-#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL      
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL
 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT       9
 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK        0x00000200U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK 
-#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL     
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL
 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT      10
 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK       0x00000400U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK 
-#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL     
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL
 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT      11
 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK       0x00000800U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK 
-#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL     
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL
 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT      12
 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK       0x00001000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK 
-#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL     
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL
 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT      13
 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK       0x00002000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK 
-#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL     
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL
 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT      14
 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK       0x00004000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK 
-#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL     
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL
 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT      15
 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK       0x00008000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK 
-#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL     
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL
 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT      16
 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK       0x00010000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK 
-#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL     
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL
 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT      17
 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK       0x00020000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK 
-#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL     
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL
 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT      18
 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK       0x00040000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK 
-#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL     
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL
 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT      19
 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK       0x00080000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK 
-#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL     
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL
 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT      20
 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK       0x00100000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK 
-#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL     
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL
 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT      21
 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK       0x00200000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK 
-#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL     
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL
 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT      22
 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK       0x00400000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK 
-#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL     
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL
 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT      23
 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK       0x00800000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK 
-#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL     
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL
 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT      24
 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK       0x01000000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK 
-#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL     
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL
 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT      25
 #define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK       0x02000000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_MASK 
-#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_DEFVAL          
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_SHIFT
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_MASK
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_DEFVAL
 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_SHIFT           0
 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_MASK            0x00000001U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_MASK 
-#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_DEFVAL          
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_SHIFT
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_MASK
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_DEFVAL
 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_SHIFT           1
 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_MASK            0x00000002U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_MASK 
-#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_DEFVAL          
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_SHIFT
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_MASK
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_DEFVAL
 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_SHIFT           2
 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_MASK            0x00000004U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_MASK 
-#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_DEFVAL          
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_SHIFT
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_MASK
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_DEFVAL
 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_SHIFT           3
 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_MASK            0x00000008U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_MASK 
-#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_DEFVAL          
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_SHIFT
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_MASK
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_DEFVAL
 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_SHIFT           4
 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_MASK            0x00000010U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_MASK 
-#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_DEFVAL          
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_SHIFT
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_MASK
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_DEFVAL
 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_SHIFT           5
 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_MASK            0x00000020U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_MASK 
-#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_DEFVAL          
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_SHIFT
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_MASK
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_DEFVAL
 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_SHIFT           6
 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_MASK            0x00000040U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_MASK 
-#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_DEFVAL          
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_SHIFT
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_MASK
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_DEFVAL
 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_SHIFT           7
 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_MASK            0x00000080U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_MASK 
-#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_DEFVAL          
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_SHIFT
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_MASK
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_DEFVAL
 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_SHIFT           8
 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_MASK            0x00000100U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_MASK 
-#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_DEFVAL          
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_SHIFT
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_MASK
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_DEFVAL
 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_SHIFT           9
 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_MASK            0x00000200U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_MASK 
-#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_DEFVAL         
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_SHIFT
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_MASK
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_DEFVAL
 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_SHIFT          10
 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_MASK           0x00000400U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_MASK 
-#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_DEFVAL         
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_SHIFT
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_MASK
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_DEFVAL
 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_SHIFT          11
 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_MASK           0x00000800U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_MASK 
-#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_DEFVAL         
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_SHIFT
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_MASK
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_DEFVAL
 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_SHIFT          12
 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_MASK           0x00001000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_MASK 
-#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_DEFVAL         
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_SHIFT
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_MASK
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_DEFVAL
 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_SHIFT          13
 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_MASK           0x00002000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_MASK 
-#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_DEFVAL         
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_SHIFT
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_MASK
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_DEFVAL
 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_SHIFT          14
 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_MASK           0x00004000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_MASK 
-#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_DEFVAL         
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_SHIFT
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_MASK
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_DEFVAL
 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_SHIFT          15
 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_MASK           0x00008000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_MASK 
-#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_DEFVAL         
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_SHIFT
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_MASK
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_DEFVAL
 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_SHIFT          16
 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_MASK           0x00010000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_MASK 
-#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_DEFVAL         
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_SHIFT
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_MASK
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_DEFVAL
 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_SHIFT          17
 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_MASK           0x00020000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_MASK 
-#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_DEFVAL         
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_SHIFT
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_MASK
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_DEFVAL
 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_SHIFT          18
 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_MASK           0x00040000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_MASK 
-#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_DEFVAL         
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_SHIFT
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_MASK
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_DEFVAL
 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_SHIFT          19
 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_MASK           0x00080000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_MASK 
-#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_DEFVAL         
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_SHIFT
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_MASK
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_DEFVAL
 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_SHIFT          20
 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_MASK           0x00100000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_MASK 
-#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_DEFVAL         
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_SHIFT
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_MASK
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_DEFVAL
 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_SHIFT          21
 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_MASK           0x00200000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_MASK 
-#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_DEFVAL         
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_SHIFT
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_MASK
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_DEFVAL
 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_SHIFT          22
 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_MASK           0x00400000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_MASK 
-#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_DEFVAL         
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_SHIFT
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_MASK
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_DEFVAL
 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_SHIFT          23
 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_MASK           0x00800000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_MASK 
-#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_DEFVAL         
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_SHIFT
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_MASK
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_DEFVAL
 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_SHIFT          24
 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_MASK           0x01000000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_MASK 
-#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_DEFVAL         
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_SHIFT
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_MASK
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_DEFVAL
 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_SHIFT          25
 #define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_MASK           0x02000000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK 
-#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL     
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL
 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT      0
 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK       0x00000001U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK 
-#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL     
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL
 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT      1
 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK       0x00000002U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK 
-#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL     
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL
 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT      2
 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK       0x00000004U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK 
-#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL     
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL
 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT      3
 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK       0x00000008U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK 
-#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL     
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL
 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT      4
 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK       0x00000010U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK 
-#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL     
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL
 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT      5
 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK       0x00000020U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK 
-#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL     
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL
 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT      6
 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK       0x00000040U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK 
-#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL     
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL
 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT      7
 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK       0x00000080U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK 
-#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL     
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL
 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT      8
 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK       0x00000100U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK 
-#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL     
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL
 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT      9
 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK       0x00000200U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK 
-#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL    
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL
 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT     10
 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK      0x00000400U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK 
-#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL    
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL
 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT     11
 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK      0x00000800U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK 
-#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL    
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL
 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT     12
 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK      0x00001000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK 
-#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL    
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL
 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT     13
 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK      0x00002000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK 
-#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL    
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL
 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT     14
 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK      0x00004000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK 
-#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL    
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL
 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT     15
 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK      0x00008000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK 
-#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL    
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL
 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT     16
 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK      0x00010000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK 
-#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL    
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL
 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT     17
 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK      0x00020000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK 
-#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL    
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL
 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT     18
 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK      0x00040000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK 
-#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL    
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL
 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT     19
 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK      0x00080000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK 
-#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL    
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL
 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT     20
 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK      0x00100000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK 
-#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL    
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL
 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT     21
 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK      0x00200000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK 
-#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL    
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL
 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT     22
 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK      0x00400000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK 
-#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL    
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL
 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT     23
 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK      0x00800000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK 
-#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL    
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL
 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT     24
 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK      0x01000000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[0].
 */
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL 
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT 
-#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK 
-#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL    
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL
 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT     25
 #define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK      0x02000000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_MASK 
-#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_DEFVAL               
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_SHIFT
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_MASK
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_DEFVAL
 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_SHIFT                0
 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_MASK                 0x00000001U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_MASK 
-#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_DEFVAL               
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_SHIFT
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_MASK
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_DEFVAL
 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_SHIFT                1
 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_MASK                 0x00000002U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_MASK 
-#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_DEFVAL               
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_SHIFT
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_MASK
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_DEFVAL
 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_SHIFT                2
 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_MASK                 0x00000004U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_MASK 
-#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_DEFVAL               
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_SHIFT
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_MASK
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_DEFVAL
 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_SHIFT                3
 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_MASK                 0x00000008U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_MASK 
-#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_DEFVAL               
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_SHIFT
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_MASK
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_DEFVAL
 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_SHIFT                4
 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_MASK                 0x00000010U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_MASK 
-#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_DEFVAL               
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_SHIFT
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_MASK
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_DEFVAL
 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_SHIFT                5
 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_MASK                 0x00000020U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_MASK 
-#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_DEFVAL               
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_SHIFT
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_MASK
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_DEFVAL
 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_SHIFT                6
 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_MASK                 0x00000040U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_MASK 
-#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_DEFVAL               
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_SHIFT
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_MASK
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_DEFVAL
 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_SHIFT                7
 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_MASK                 0x00000080U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_MASK 
-#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_DEFVAL               
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_SHIFT
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_MASK
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_DEFVAL
 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_SHIFT                8
 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_MASK                 0x00000100U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_MASK 
-#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_DEFVAL               
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_SHIFT
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_MASK
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_DEFVAL
 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_SHIFT                9
 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_MASK                 0x00000200U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_MASK 
-#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_DEFVAL              
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_SHIFT
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_MASK
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_DEFVAL
 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_SHIFT               10
 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_MASK                0x00000400U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_MASK 
-#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_DEFVAL              
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_SHIFT
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_MASK
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_DEFVAL
 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_SHIFT               11
 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_MASK                0x00000800U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_MASK 
-#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_DEFVAL              
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_SHIFT
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_MASK
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_DEFVAL
 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_SHIFT               12
 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_MASK                0x00001000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_MASK 
-#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_DEFVAL              
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_SHIFT
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_MASK
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_DEFVAL
 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_SHIFT               13
 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_MASK                0x00002000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_MASK 
-#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_DEFVAL              
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_SHIFT
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_MASK
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_DEFVAL
 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_SHIFT               14
 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_MASK                0x00004000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_MASK 
-#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_DEFVAL              
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_SHIFT
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_MASK
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_DEFVAL
 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_SHIFT               15
 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_MASK                0x00008000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_MASK 
-#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_DEFVAL              
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_SHIFT
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_MASK
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_DEFVAL
 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_SHIFT               16
 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_MASK                0x00010000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_MASK 
-#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_DEFVAL              
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_SHIFT
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_MASK
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_DEFVAL
 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_SHIFT               17
 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_MASK                0x00020000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_MASK 
-#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_DEFVAL              
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_SHIFT
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_MASK
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_DEFVAL
 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_SHIFT               18
 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_MASK                0x00040000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_MASK 
-#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_DEFVAL              
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_SHIFT
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_MASK
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_DEFVAL
 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_SHIFT               19
 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_MASK                0x00080000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_MASK 
-#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_DEFVAL              
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_SHIFT
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_MASK
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_DEFVAL
 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_SHIFT               20
 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_MASK                0x00100000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_MASK 
-#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_DEFVAL              
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_SHIFT
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_MASK
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_DEFVAL
 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_SHIFT               21
 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_MASK                0x00200000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_MASK 
-#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_DEFVAL              
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_SHIFT
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_MASK
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_DEFVAL
 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_SHIFT               22
 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_MASK                0x00400000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_MASK 
-#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_DEFVAL              
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_SHIFT
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_MASK
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_DEFVAL
 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_SHIFT               23
 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_MASK                0x00800000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_MASK 
-#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_DEFVAL              
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_SHIFT
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_MASK
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_DEFVAL
 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_SHIFT               24
 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_MASK                0x01000000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_MASK 
-#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_DEFVAL              
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_SHIFT
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_MASK
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_DEFVAL
 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_SHIFT               25
 #define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_MASK                0x02000000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_MASK 
-#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_DEFVAL               
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_SHIFT
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_MASK
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_DEFVAL
 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_SHIFT                0
 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_MASK                 0x00000001U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_MASK 
-#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_DEFVAL               
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_SHIFT
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_MASK
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_DEFVAL
 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_SHIFT                1
 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_MASK                 0x00000002U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_MASK 
-#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_DEFVAL               
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_SHIFT
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_MASK
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_DEFVAL
 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_SHIFT                2
 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_MASK                 0x00000004U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_MASK 
-#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_DEFVAL               
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_SHIFT
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_MASK
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_DEFVAL
 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_SHIFT                3
 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_MASK                 0x00000008U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_MASK 
-#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_DEFVAL               
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_SHIFT
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_MASK
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_DEFVAL
 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_SHIFT                4
 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_MASK                 0x00000010U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_MASK 
-#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_DEFVAL               
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_SHIFT
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_MASK
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_DEFVAL
 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_SHIFT                5
 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_MASK                 0x00000020U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_MASK 
-#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_DEFVAL               
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_SHIFT
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_MASK
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_DEFVAL
 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_SHIFT                6
 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_MASK                 0x00000040U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_MASK 
-#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_DEFVAL               
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_SHIFT
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_MASK
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_DEFVAL
 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_SHIFT                7
 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_MASK                 0x00000080U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_MASK 
-#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_DEFVAL               
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_SHIFT
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_MASK
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_DEFVAL
 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_SHIFT                8
 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_MASK                 0x00000100U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_MASK 
-#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_DEFVAL               
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_SHIFT
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_MASK
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_DEFVAL
 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_SHIFT                9
 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_MASK                 0x00000200U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_MASK 
-#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_DEFVAL              
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_SHIFT
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_MASK
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_DEFVAL
 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_SHIFT               10
 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_MASK                0x00000400U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_MASK 
-#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_DEFVAL              
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_SHIFT
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_MASK
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_DEFVAL
 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_SHIFT               11
 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_MASK                0x00000800U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_MASK 
-#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_DEFVAL              
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_SHIFT
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_MASK
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_DEFVAL
 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_SHIFT               12
 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_MASK                0x00001000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_MASK 
-#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_DEFVAL              
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_SHIFT
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_MASK
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_DEFVAL
 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_SHIFT               13
 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_MASK                0x00002000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_MASK 
-#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_DEFVAL              
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_SHIFT
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_MASK
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_DEFVAL
 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_SHIFT               14
 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_MASK                0x00004000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_MASK 
-#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_DEFVAL              
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_SHIFT
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_MASK
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_DEFVAL
 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_SHIFT               15
 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_MASK                0x00008000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_MASK 
-#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_DEFVAL              
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_SHIFT
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_MASK
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_DEFVAL
 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_SHIFT               16
 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_MASK                0x00010000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_MASK 
-#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_DEFVAL              
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_SHIFT
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_MASK
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_DEFVAL
 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_SHIFT               17
 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_MASK                0x00020000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_MASK 
-#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_DEFVAL              
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_SHIFT
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_MASK
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_DEFVAL
 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_SHIFT               18
 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_MASK                0x00040000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_MASK 
-#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_DEFVAL              
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_SHIFT
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_MASK
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_DEFVAL
 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_SHIFT               19
 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_MASK                0x00080000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_MASK 
-#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_DEFVAL              
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_SHIFT
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_MASK
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_DEFVAL
 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_SHIFT               20
 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_MASK                0x00100000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_MASK 
-#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_DEFVAL              
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_SHIFT
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_MASK
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_DEFVAL
 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_SHIFT               21
 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_MASK                0x00200000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_MASK 
-#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_DEFVAL              
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_SHIFT
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_MASK
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_DEFVAL
 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_SHIFT               22
 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_MASK                0x00400000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_MASK 
-#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_DEFVAL              
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_SHIFT
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_MASK
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_DEFVAL
 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_SHIFT               23
 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_MASK                0x00800000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_MASK 
-#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_DEFVAL              
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_SHIFT
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_MASK
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_DEFVAL
 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_SHIFT               24
 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_MASK                0x01000000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_MASK 
-#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_DEFVAL              
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_SHIFT
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_MASK
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_DEFVAL
 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_SHIFT               25
 #define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_MASK                0x02000000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK 
-#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL       
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL
 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT        0
 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK         0x00000001U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK 
-#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL       
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL
 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT        1
 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK         0x00000002U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK 
-#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL       
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL
 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT        2
 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK         0x00000004U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK 
-#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL       
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL
 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT        3
 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK         0x00000008U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK 
-#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL       
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL
 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT        4
 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK         0x00000010U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK 
-#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL       
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL
 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT        5
 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK         0x00000020U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK 
-#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL       
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL
 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT        6
 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK         0x00000040U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK 
-#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL       
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL
 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT        7
 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK         0x00000080U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK 
-#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL       
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL
 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT        8
 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK         0x00000100U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK 
-#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL       
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL
 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT        9
 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK         0x00000200U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK 
-#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL      
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL
 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT       10
 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK        0x00000400U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK 
-#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL      
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL
 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT       11
 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK        0x00000800U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK 
-#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL      
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL
 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT       12
 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK        0x00001000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK 
-#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL      
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL
 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT       13
 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK        0x00002000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK 
-#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL      
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL
 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT       14
 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK        0x00004000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK 
-#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL      
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL
 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT       15
 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK        0x00008000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK 
-#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL      
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL
 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT       16
 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK        0x00010000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK 
-#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL      
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL
 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT       17
 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK        0x00020000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK 
-#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL      
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL
 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT       18
 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK        0x00040000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK 
-#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL      
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL
 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT       19
 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK        0x00080000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK 
-#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL      
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL
 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT       20
 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK        0x00100000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK 
-#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL      
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL
 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT       21
 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK        0x00200000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK 
-#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL      
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL
 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT       22
 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK        0x00400000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK 
-#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL      
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL
 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT       23
 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK        0x00800000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK 
-#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL      
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL
 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT       24
 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK        0x01000000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK 
-#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL      
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL
 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT       25
 #define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK        0x02000000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK 
-#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL      
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL
 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT       0
 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK        0x00000001U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK 
-#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL      
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL
 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT       1
 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK        0x00000002U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK 
-#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL      
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL
 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT       2
 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK        0x00000004U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK 
-#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL      
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL
 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT       3
 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK        0x00000008U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK 
-#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL      
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL
 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT       4
 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK        0x00000010U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK 
-#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL      
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL
 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT       5
 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK        0x00000020U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK 
-#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL      
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL
 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT       6
 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK        0x00000040U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK 
-#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL      
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL
 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT       7
 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK        0x00000080U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK 
-#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL      
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL
 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT       8
 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK        0x00000100U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK 
-#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL      
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL
 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT       9
 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK        0x00000200U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK 
-#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL     
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL
 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT      10
 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK       0x00000400U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK 
-#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL     
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL
 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT      11
 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK       0x00000800U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK 
-#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL     
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL
 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT      12
 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK       0x00001000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK 
-#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL     
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL
 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT      13
 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK       0x00002000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK 
-#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL     
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL
 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT      14
 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK       0x00004000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK 
-#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL     
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL
 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT      15
 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK       0x00008000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK 
-#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL     
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL
 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT      16
 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK       0x00010000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK 
-#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL     
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL
 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT      17
 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK       0x00020000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK 
-#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL     
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL
 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT      18
 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK       0x00040000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK 
-#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL     
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL
 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT      19
 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK       0x00080000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK 
-#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL     
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL
 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT      20
 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK       0x00100000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK 
-#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL     
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL
 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT      21
 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK       0x00200000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK 
-#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL     
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL
 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT      22
 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK       0x00400000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK 
-#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL     
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL
 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT      23
 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK       0x00800000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK 
-#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL     
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL
 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT      24
 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK       0x01000000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK 
-#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL     
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL
 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT      25
 #define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK       0x02000000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_MASK 
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_DEFVAL          
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_SHIFT
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_MASK
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_DEFVAL
 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_SHIFT           12
 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_MASK            0x00001000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_MASK 
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_DEFVAL          
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_SHIFT
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_MASK
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_DEFVAL
 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_SHIFT           13
 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_MASK            0x00002000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_MASK 
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_DEFVAL          
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_SHIFT
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_MASK
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_DEFVAL
 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_SHIFT           14
 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_MASK            0x00004000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_MASK 
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_DEFVAL          
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_SHIFT
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_MASK
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_DEFVAL
 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_SHIFT           15
 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_MASK            0x00008000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_MASK 
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_DEFVAL          
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_SHIFT
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_MASK
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_DEFVAL
 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_SHIFT           16
 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_MASK            0x00010000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_MASK 
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_DEFVAL          
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_SHIFT
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_MASK
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_DEFVAL
 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_SHIFT           17
 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_MASK            0x00020000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_MASK 
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_DEFVAL          
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_SHIFT
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_MASK
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_DEFVAL
 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_SHIFT           18
 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_MASK            0x00040000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_MASK 
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_DEFVAL          
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_SHIFT
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_MASK
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_DEFVAL
 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_SHIFT           19
 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_MASK            0x00080000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_MASK 
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_DEFVAL          
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_SHIFT
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_MASK
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_DEFVAL
 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_SHIFT           20
 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_MASK            0x00100000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_MASK 
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_DEFVAL          
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_SHIFT
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_MASK
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_DEFVAL
 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_SHIFT           21
 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_MASK            0x00200000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_MASK 
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_DEFVAL         
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_SHIFT
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_MASK
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_DEFVAL
 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_SHIFT          22
 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_MASK           0x00400000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_MASK 
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_DEFVAL         
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_SHIFT
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_MASK
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_DEFVAL
 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_SHIFT          23
 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_MASK           0x00800000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_MASK 
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_DEFVAL         
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_SHIFT
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_MASK
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_DEFVAL
 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_SHIFT          24
 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_MASK           0x01000000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_MASK 
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_DEFVAL         
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_SHIFT
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_MASK
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_DEFVAL
 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_SHIFT          25
 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_MASK           0x02000000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_MASK 
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_DEFVAL         
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_SHIFT
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_MASK
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_DEFVAL
 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_SHIFT          0
 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_MASK           0x00000001U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_MASK 
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_DEFVAL         
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_SHIFT
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_MASK
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_DEFVAL
 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_SHIFT          1
 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_MASK           0x00000002U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_MASK 
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_DEFVAL         
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_SHIFT
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_MASK
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_DEFVAL
 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_SHIFT          2
 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_MASK           0x00000004U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_MASK 
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_DEFVAL         
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_SHIFT
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_MASK
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_DEFVAL
 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_SHIFT          3
 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_MASK           0x00000008U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_MASK 
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_DEFVAL         
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_SHIFT
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_MASK
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_DEFVAL
 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_SHIFT          4
 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_MASK           0x00000010U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_MASK 
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_DEFVAL         
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_SHIFT
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_MASK
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_DEFVAL
 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_SHIFT          5
 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_MASK           0x00000020U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_MASK 
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_DEFVAL         
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_SHIFT
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_MASK
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_DEFVAL
 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_SHIFT          6
 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_MASK           0x00000040U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_MASK 
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_DEFVAL         
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_SHIFT
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_MASK
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_DEFVAL
 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_SHIFT          7
 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_MASK           0x00000080U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_MASK 
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_DEFVAL         
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_SHIFT
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_MASK
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_DEFVAL
 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_SHIFT          8
 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_MASK           0x00000100U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_MASK 
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_DEFVAL         
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_SHIFT
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_MASK
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_DEFVAL
 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_SHIFT          9
 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_MASK           0x00000200U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_MASK 
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_DEFVAL         
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_SHIFT
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_MASK
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_DEFVAL
 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_SHIFT          10
 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_MASK           0x00000400U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_MASK 
-#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_DEFVAL         
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_SHIFT
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_MASK
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_DEFVAL
 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_SHIFT          11
 #define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_MASK           0x00000800U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK 
-#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL     
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL
 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT      0
 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK       0x00000001U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK 
-#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL     
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL
 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT      1
 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK       0x00000002U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK 
-#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL     
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL
 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT      2
 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK       0x00000004U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK 
-#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL     
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL
 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT      3
 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK       0x00000008U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK 
-#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL     
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL
 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT      4
 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK       0x00000010U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK 
-#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL     
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL
 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT      5
 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK       0x00000020U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK 
-#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL     
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL
 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT      6
 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK       0x00000040U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK 
-#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL     
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL
 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT      7
 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK       0x00000080U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK 
-#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL     
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL
 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT      8
 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK       0x00000100U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK 
-#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL     
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL
 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT      9
 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK       0x00000200U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK 
-#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL    
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL
 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT     10
 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK      0x00000400U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK 
-#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL    
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL
 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT     11
 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK      0x00000800U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK 
-#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL    
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL
 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT     12
 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK      0x00001000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK 
-#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL    
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL
 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT     13
 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK      0x00002000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK 
-#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL    
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL
 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT     14
 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK      0x00004000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK 
-#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL    
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL
 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT     15
 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK      0x00008000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK 
-#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL    
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL
 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT     16
 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK      0x00010000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK 
-#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL    
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL
 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT     17
 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK      0x00020000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK 
-#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL    
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL
 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT     18
 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK      0x00040000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK 
-#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL    
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL
 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT     19
 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK      0x00080000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK 
-#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL    
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL
 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT     20
 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK      0x00100000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK 
-#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL    
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL
 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT     21
 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK      0x00200000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK 
-#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL    
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL
 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT     22
 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK      0x00400000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK 
-#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL    
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL
 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT     23
 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK      0x00800000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK 
-#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL    
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL
 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT     24
 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK      0x01000000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[26].
 */
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL 
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT 
-#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK 
-#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL    
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL
 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT     25
 #define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK      0x02000000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_MASK 
-#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_DEFVAL               
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_SHIFT
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_MASK
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_DEFVAL
 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_SHIFT                0
 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_MASK                 0x00000001U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_MASK 
-#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_DEFVAL               
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_SHIFT
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_MASK
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_DEFVAL
 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_SHIFT                1
 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_MASK                 0x00000002U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_MASK 
-#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_DEFVAL               
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_SHIFT
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_MASK
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_DEFVAL
 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_SHIFT                2
 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_MASK                 0x00000004U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_MASK 
-#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_DEFVAL               
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_SHIFT
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_MASK
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_DEFVAL
 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_SHIFT                3
 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_MASK                 0x00000008U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_MASK 
-#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_DEFVAL               
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_SHIFT
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_MASK
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_DEFVAL
 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_SHIFT                4
 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_MASK                 0x00000010U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_MASK 
-#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_DEFVAL               
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_SHIFT
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_MASK
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_DEFVAL
 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_SHIFT                5
 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_MASK                 0x00000020U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_MASK 
-#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_DEFVAL               
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_SHIFT
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_MASK
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_DEFVAL
 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_SHIFT                6
 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_MASK                 0x00000040U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_MASK 
-#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_DEFVAL               
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_SHIFT
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_MASK
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_DEFVAL
 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_SHIFT                7
 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_MASK                 0x00000080U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_MASK 
-#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_DEFVAL               
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_SHIFT
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_MASK
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_DEFVAL
 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_SHIFT                8
 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_MASK                 0x00000100U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_MASK 
-#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_DEFVAL               
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_SHIFT
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_MASK
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_DEFVAL
 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_SHIFT                9
 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_MASK                 0x00000200U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_MASK 
-#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_DEFVAL              
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_SHIFT
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_MASK
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_DEFVAL
 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_SHIFT               10
 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_MASK                0x00000400U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_MASK 
-#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_DEFVAL              
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_SHIFT
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_MASK
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_DEFVAL
 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_SHIFT               11
 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_MASK                0x00000800U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_MASK 
-#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_DEFVAL              
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_SHIFT
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_MASK
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_DEFVAL
 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_SHIFT               12
 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_MASK                0x00001000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_MASK 
-#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_DEFVAL              
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_SHIFT
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_MASK
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_DEFVAL
 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_SHIFT               13
 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_MASK                0x00002000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_MASK 
-#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_DEFVAL              
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_SHIFT
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_MASK
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_DEFVAL
 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_SHIFT               14
 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_MASK                0x00004000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_MASK 
-#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_DEFVAL              
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_SHIFT
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_MASK
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_DEFVAL
 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_SHIFT               15
 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_MASK                0x00008000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_MASK 
-#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_DEFVAL              
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_SHIFT
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_MASK
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_DEFVAL
 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_SHIFT               16
 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_MASK                0x00010000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_MASK 
-#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_DEFVAL              
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_SHIFT
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_MASK
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_DEFVAL
 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_SHIFT               17
 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_MASK                0x00020000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_MASK 
-#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_DEFVAL              
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_SHIFT
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_MASK
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_DEFVAL
 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_SHIFT               18
 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_MASK                0x00040000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_MASK 
-#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_DEFVAL              
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_SHIFT
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_MASK
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_DEFVAL
 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_SHIFT               19
 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_MASK                0x00080000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_MASK 
-#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_DEFVAL              
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_SHIFT
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_MASK
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_DEFVAL
 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_SHIFT               20
 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_MASK                0x00100000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_MASK 
-#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_DEFVAL              
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_SHIFT
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_MASK
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_DEFVAL
 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_SHIFT               21
 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_MASK                0x00200000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_MASK 
-#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_DEFVAL              
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_SHIFT
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_MASK
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_DEFVAL
 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_SHIFT               22
 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_MASK                0x00400000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_MASK 
-#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_DEFVAL              
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_SHIFT
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_MASK
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_DEFVAL
 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_SHIFT               23
 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_MASK                0x00800000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_MASK 
-#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_DEFVAL              
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_SHIFT
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_MASK
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_DEFVAL
 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_SHIFT               24
 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_MASK                0x01000000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_MASK 
-#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_DEFVAL              
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_SHIFT
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_MASK
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_DEFVAL
 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_SHIFT               25
 #define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_MASK                0x02000000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_MASK 
-#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_DEFVAL               
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_SHIFT
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_MASK
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_DEFVAL
 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_SHIFT                0
 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_MASK                 0x00000001U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_MASK 
-#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_DEFVAL               
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_SHIFT
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_MASK
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_DEFVAL
 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_SHIFT                1
 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_MASK                 0x00000002U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_MASK 
-#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_DEFVAL               
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_SHIFT
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_MASK
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_DEFVAL
 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_SHIFT                2
 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_MASK                 0x00000004U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_MASK 
-#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_DEFVAL               
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_SHIFT
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_MASK
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_DEFVAL
 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_SHIFT                3
 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_MASK                 0x00000008U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_MASK 
-#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_DEFVAL               
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_SHIFT
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_MASK
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_DEFVAL
 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_SHIFT                4
 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_MASK                 0x00000010U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_MASK 
-#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_DEFVAL               
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_SHIFT
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_MASK
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_DEFVAL
 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_SHIFT                5
 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_MASK                 0x00000020U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_MASK 
-#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_DEFVAL               
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_SHIFT
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_MASK
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_DEFVAL
 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_SHIFT                6
 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_MASK                 0x00000040U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_MASK 
-#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_DEFVAL               
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_SHIFT
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_MASK
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_DEFVAL
 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_SHIFT                7
 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_MASK                 0x00000080U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_MASK 
-#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_DEFVAL               
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_SHIFT
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_MASK
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_DEFVAL
 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_SHIFT                8
 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_MASK                 0x00000100U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_MASK 
-#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_DEFVAL               
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_SHIFT
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_MASK
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_DEFVAL
 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_SHIFT                9
 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_MASK                 0x00000200U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_MASK 
-#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_DEFVAL              
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_SHIFT
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_MASK
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_DEFVAL
 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_SHIFT               10
 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_MASK                0x00000400U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_MASK 
-#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_DEFVAL              
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_SHIFT
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_MASK
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_DEFVAL
 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_SHIFT               11
 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_MASK                0x00000800U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_MASK 
-#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_DEFVAL              
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_SHIFT
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_MASK
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_DEFVAL
 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_SHIFT               12
 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_MASK                0x00001000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_MASK 
-#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_DEFVAL              
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_SHIFT
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_MASK
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_DEFVAL
 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_SHIFT               13
 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_MASK                0x00002000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_MASK 
-#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_DEFVAL              
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_SHIFT
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_MASK
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_DEFVAL
 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_SHIFT               14
 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_MASK                0x00004000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_MASK 
-#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_DEFVAL              
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_SHIFT
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_MASK
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_DEFVAL
 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_SHIFT               15
 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_MASK                0x00008000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_MASK 
-#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_DEFVAL              
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_SHIFT
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_MASK
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_DEFVAL
 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_SHIFT               16
 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_MASK                0x00010000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_MASK 
-#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_DEFVAL              
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_SHIFT
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_MASK
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_DEFVAL
 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_SHIFT               17
 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_MASK                0x00020000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_MASK 
-#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_DEFVAL              
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_SHIFT
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_MASK
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_DEFVAL
 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_SHIFT               18
 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_MASK                0x00040000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_MASK 
-#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_DEFVAL              
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_SHIFT
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_MASK
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_DEFVAL
 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_SHIFT               19
 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_MASK                0x00080000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_MASK 
-#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_DEFVAL              
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_SHIFT
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_MASK
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_DEFVAL
 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_SHIFT               20
 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_MASK                0x00100000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_MASK 
-#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_DEFVAL              
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_SHIFT
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_MASK
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_DEFVAL
 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_SHIFT               21
 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_MASK                0x00200000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_MASK 
-#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_DEFVAL              
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_SHIFT
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_MASK
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_DEFVAL
 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_SHIFT               22
 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_MASK                0x00400000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_MASK 
-#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_DEFVAL              
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_SHIFT
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_MASK
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_DEFVAL
 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_SHIFT               23
 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_MASK                0x00800000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_MASK 
-#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_DEFVAL              
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_SHIFT
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_MASK
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_DEFVAL
 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_SHIFT               24
 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_MASK                0x01000000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_MASK 
-#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_DEFVAL              
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_SHIFT
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_MASK
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_DEFVAL
 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_SHIFT               25
 #define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_MASK                0x02000000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK 
-#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL       
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL
 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT        0
 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK         0x00000001U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK 
-#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL       
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL
 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT        1
 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK         0x00000002U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK 
-#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL       
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL
 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT        2
 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK         0x00000004U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK 
-#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL       
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL
 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT        3
 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK         0x00000008U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK 
-#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL       
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL
 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT        4
 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK         0x00000010U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK 
-#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL       
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL
 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT        5
 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK         0x00000020U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK 
-#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL       
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL
 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT        6
 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK         0x00000040U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK 
-#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL       
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL
 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT        7
 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK         0x00000080U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK 
-#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL       
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL
 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT        8
 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK         0x00000100U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK 
-#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL       
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL
 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT        9
 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK         0x00000200U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK 
-#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL      
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL
 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT       10
 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK        0x00000400U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK 
-#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL      
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL
 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT       11
 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK        0x00000800U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK 
-#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL      
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL
 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT       12
 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK        0x00001000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK 
-#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL      
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL
 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT       13
 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK        0x00002000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK 
-#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL      
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL
 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT       14
 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK        0x00004000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK 
-#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL      
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL
 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT       15
 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK        0x00008000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK 
-#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL      
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL
 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT       16
 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK        0x00010000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK 
-#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL      
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL
 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT       17
 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK        0x00020000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK 
-#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL      
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL
 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT       18
 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK        0x00040000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK 
-#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL      
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL
 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT       19
 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK        0x00080000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK 
-#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL      
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL
 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT       20
 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK        0x00100000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK 
-#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL      
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL
 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT       21
 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK        0x00200000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK 
-#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL      
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL
 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT       22
 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK        0x00400000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK 
-#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL      
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL
 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT       23
 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK        0x00800000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK 
-#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL      
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL
 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT       24
 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK        0x01000000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK 
-#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL      
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL
 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT       25
 #define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK        0x02000000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK 
-#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL      
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL
 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT       0
 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK        0x00000001U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK 
-#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL      
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL
 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT       1
 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK        0x00000002U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK 
-#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL      
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL
 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT       2
 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK        0x00000004U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK 
-#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL      
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL
 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT       3
 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK        0x00000008U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK 
-#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL      
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL
 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT       4
 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK        0x00000010U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK 
-#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL      
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL
 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT       5
 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK        0x00000020U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK 
-#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL      
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL
 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT       6
 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK        0x00000040U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK 
-#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL      
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL
 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT       7
 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK        0x00000080U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK 
-#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL      
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL
 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT       8
 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK        0x00000100U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK 
-#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL      
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL
 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT       9
 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK        0x00000200U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK 
-#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL     
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL
 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT      10
 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK       0x00000400U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK 
-#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL     
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL
 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT      11
 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK       0x00000800U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK 
-#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL     
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL
 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT      12
 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK       0x00001000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK 
-#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL     
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL
 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT      13
 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK       0x00002000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK 
-#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL     
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL
 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT      14
 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK       0x00004000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK 
-#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL     
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL
 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT      15
 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK       0x00008000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK 
-#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL     
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL
 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT      16
 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK       0x00010000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK 
-#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL     
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL
 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT      17
 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK       0x00020000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK 
-#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL     
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL
 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT      18
 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK       0x00040000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK 
-#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL     
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL
 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT      19
 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK       0x00080000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK 
-#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL     
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL
 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT      20
 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK       0x00100000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK 
-#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL     
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL
 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT      21
 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK       0x00200000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK 
-#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL     
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL
 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT      22
 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK       0x00400000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK 
-#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL     
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL
 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT      23
 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK       0x00800000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK 
-#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL     
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL
 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT      24
 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK       0x01000000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK 
-#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL     
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL
 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT      25
 #define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK       0x02000000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_MASK 
-#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_DEFVAL          
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_SHIFT
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_MASK
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_DEFVAL
 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_SHIFT           0
 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_MASK            0x00000001U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_MASK 
-#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_DEFVAL          
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_SHIFT
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_MASK
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_DEFVAL
 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_SHIFT           1
 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_MASK            0x00000002U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_MASK 
-#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_DEFVAL          
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_SHIFT
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_MASK
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_DEFVAL
 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_SHIFT           2
 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_MASK            0x00000004U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_MASK 
-#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_DEFVAL          
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_SHIFT
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_MASK
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_DEFVAL
 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_SHIFT           3
 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_MASK            0x00000008U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_MASK 
-#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_DEFVAL          
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_SHIFT
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_MASK
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_DEFVAL
 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_SHIFT           4
 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_MASK            0x00000010U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_MASK 
-#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_DEFVAL          
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_SHIFT
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_MASK
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_DEFVAL
 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_SHIFT           5
 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_MASK            0x00000020U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_MASK 
-#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_DEFVAL          
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_SHIFT
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_MASK
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_DEFVAL
 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_SHIFT           6
 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_MASK            0x00000040U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_MASK 
-#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_DEFVAL          
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_SHIFT
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_MASK
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_DEFVAL
 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_SHIFT           7
 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_MASK            0x00000080U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_MASK 
-#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_DEFVAL          
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_SHIFT
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_MASK
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_DEFVAL
 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_SHIFT           8
 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_MASK            0x00000100U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_MASK 
-#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_DEFVAL          
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_SHIFT
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_MASK
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_DEFVAL
 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_SHIFT           9
 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_MASK            0x00000200U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_MASK 
-#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_DEFVAL         
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_SHIFT
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_MASK
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_DEFVAL
 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_SHIFT          10
 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_MASK           0x00000400U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_MASK 
-#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_DEFVAL         
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_SHIFT
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_MASK
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_DEFVAL
 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_SHIFT          11
 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_MASK           0x00000800U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_MASK 
-#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_DEFVAL         
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_SHIFT
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_MASK
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_DEFVAL
 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_SHIFT          12
 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_MASK           0x00001000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_MASK 
-#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_DEFVAL         
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_SHIFT
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_MASK
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_DEFVAL
 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_SHIFT          13
 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_MASK           0x00002000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_MASK 
-#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_DEFVAL         
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_SHIFT
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_MASK
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_DEFVAL
 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_SHIFT          14
 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_MASK           0x00004000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_MASK 
-#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_DEFVAL         
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_SHIFT
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_MASK
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_DEFVAL
 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_SHIFT          15
 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_MASK           0x00008000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_MASK 
-#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_DEFVAL         
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_SHIFT
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_MASK
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_DEFVAL
 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_SHIFT          16
 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_MASK           0x00010000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_MASK 
-#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_DEFVAL         
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_SHIFT
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_MASK
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_DEFVAL
 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_SHIFT          17
 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_MASK           0x00020000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_MASK 
-#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_DEFVAL         
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_SHIFT
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_MASK
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_DEFVAL
 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_SHIFT          18
 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_MASK           0x00040000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_MASK 
-#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_DEFVAL         
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_SHIFT
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_MASK
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_DEFVAL
 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_SHIFT          19
 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_MASK           0x00080000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_MASK 
-#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_DEFVAL         
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_SHIFT
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_MASK
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_DEFVAL
 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_SHIFT          20
 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_MASK           0x00100000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_MASK 
-#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_DEFVAL         
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_SHIFT
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_MASK
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_DEFVAL
 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_SHIFT          21
 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_MASK           0x00200000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_MASK 
-#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_DEFVAL         
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_SHIFT
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_MASK
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_DEFVAL
 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_SHIFT          22
 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_MASK           0x00400000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_MASK 
-#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_DEFVAL         
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_SHIFT
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_MASK
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_DEFVAL
 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_SHIFT          23
 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_MASK           0x00800000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_MASK 
-#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_DEFVAL         
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_SHIFT
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_MASK
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_DEFVAL
 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_SHIFT          24
 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_MASK           0x01000000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_MASK 
-#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_DEFVAL         
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_SHIFT
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_MASK
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_DEFVAL
 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_SHIFT          25
 #define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_MASK           0x02000000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK 
-#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL     
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL
 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT      0
 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK       0x00000001U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK 
-#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL     
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL
 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT      1
 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK       0x00000002U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK 
-#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL     
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL
 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT      2
 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK       0x00000004U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK 
-#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL     
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL
 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT      3
 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK       0x00000008U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK 
-#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL     
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL
 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT      4
 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK       0x00000010U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK 
-#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL     
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL
 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT      5
 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK       0x00000020U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK 
-#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL     
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL
 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT      6
 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK       0x00000040U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK 
-#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL     
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL
 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT      7
 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK       0x00000080U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK 
-#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL     
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL
 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT      8
 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK       0x00000100U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK 
-#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL     
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL
 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT      9
 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK       0x00000200U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK 
-#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL    
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL
 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT     10
 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK      0x00000400U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK 
-#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL    
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL
 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT     11
 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK      0x00000800U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK 
-#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL    
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL
 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT     12
 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK      0x00001000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK 
-#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL    
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL
 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT     13
 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK      0x00002000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK 
-#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL    
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL
 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT     14
 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK      0x00004000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK 
-#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL    
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL
 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT     15
 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK      0x00008000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK 
-#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL    
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL
 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT     16
 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK      0x00010000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK 
-#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL    
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL
 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT     17
 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK      0x00020000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK 
-#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL    
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL
 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT     18
 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK      0x00040000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK 
-#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL    
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL
 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT     19
 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK      0x00080000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK 
-#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL    
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL
 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT     20
 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK      0x00100000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK 
-#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL    
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL
 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT     21
 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK      0x00200000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK 
-#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL    
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL
 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT     22
 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK      0x00400000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK 
-#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL    
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL
 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT     23
 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK      0x00800000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK 
-#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL    
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL
 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT     24
 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK      0x01000000U
 
 /*
 * Each bit applies to a single IO. Bit 0 for MIO[52].
 */
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL 
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT 
-#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK 
-#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL    
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL
 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT     25
 #define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK      0x02000000U
 
@@ -29490,9 +29490,9 @@
     *  = Loop I2C 0 outputs to I2C 1 inputs, and I2C 1 outputs to I2C 0 inputs
     * .
 */
-#undef IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_DEFVAL 
-#undef IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_SHIFT 
-#undef IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_MASK 
+#undef IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_DEFVAL
+#undef IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_SHIFT
+#undef IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_MASK
 #define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_DEFVAL            0x00000000
 #define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_SHIFT             3
 #define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_MASK              0x00000008U
@@ -29501,9 +29501,9 @@
 * CAN Loopback Control. 0 = Connect CAN inputs according to MIO mapping. 1
     *  = Loop CAN 0 Tx to CAN 1 Rx, and CAN 1 Tx to CAN 0 Rx.
 */
-#undef IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_DEFVAL 
-#undef IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_SHIFT 
-#undef IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_MASK 
+#undef IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_DEFVAL
+#undef IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_SHIFT
+#undef IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_MASK
 #define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_DEFVAL            0x00000000
 #define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_SHIFT             2
 #define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_MASK              0x00000004U
@@ -29514,9 +29514,9 @@
     * inputs. RXD/TXD cross-connected. RTS/CTS cross-connected. DSR, DTR, DCD
     * and RI not used.
 */
-#undef IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_DEFVAL 
-#undef IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_SHIFT 
-#undef IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_MASK 
+#undef IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_DEFVAL
+#undef IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_SHIFT
+#undef IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_MASK
 #define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_DEFVAL              0x00000000
 #define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_SHIFT               1
 #define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_MASK                0x00000002U
@@ -29526,85 +29526,87 @@
     *  = Loop SPI 0 outputs to SPI 1 inputs, and SPI 1 outputs to SPI 0 inputs
     * . The other SPI core will appear on the LS Slave Select.
 */
-#undef IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_DEFVAL 
-#undef IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_SHIFT 
-#undef IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_MASK 
+#undef IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_DEFVAL
+#undef IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_SHIFT
+#undef IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_MASK
 #define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_DEFVAL            0x00000000
 #define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_SHIFT             0
 #define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_MASK              0x00000001U
-#undef CRF_APB_RST_FPD_TOP_OFFSET 
+#undef CRF_APB_RST_FPD_TOP_OFFSET
 #define CRF_APB_RST_FPD_TOP_OFFSET                                                 0XFD1A0100
-#undef CRL_APB_RST_LPD_IOU2_OFFSET 
+#undef CRL_APB_RST_LPD_IOU2_OFFSET
 #define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
-#undef CRL_APB_RST_LPD_TOP_OFFSET 
+#undef CRL_APB_RST_LPD_TOP_OFFSET
 #define CRL_APB_RST_LPD_TOP_OFFSET                                                 0XFF5E023C
-#undef CRL_APB_RST_LPD_IOU0_OFFSET 
+#undef CRL_APB_RST_LPD_IOU0_OFFSET
 #define CRL_APB_RST_LPD_IOU0_OFFSET                                                0XFF5E0230
-#undef CRL_APB_RST_LPD_IOU2_OFFSET 
+#undef CRL_APB_RST_LPD_IOU2_OFFSET
 #define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
-#undef IOU_SLCR_IOU_TAPDLY_BYPASS_OFFSET 
+#undef IOU_SLCR_IOU_TAPDLY_BYPASS_OFFSET
 #define IOU_SLCR_IOU_TAPDLY_BYPASS_OFFSET                                          0XFF180390
-#undef CRL_APB_RST_LPD_TOP_OFFSET 
+#undef CRL_APB_RST_LPD_TOP_OFFSET
 #define CRL_APB_RST_LPD_TOP_OFFSET                                                 0XFF5E023C
-#undef CRL_APB_RST_LPD_IOU2_OFFSET 
+#undef CRL_APB_RST_LPD_IOU2_OFFSET
 #define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
-#undef IOU_SLCR_CTRL_REG_SD_OFFSET 
+#undef IOU_SLCR_CTRL_REG_SD_OFFSET
 #define IOU_SLCR_CTRL_REG_SD_OFFSET                                                0XFF180310
-#undef IOU_SLCR_SD_CONFIG_REG2_OFFSET 
+#undef IOU_SLCR_SD_CONFIG_REG2_OFFSET
 #define IOU_SLCR_SD_CONFIG_REG2_OFFSET                                             0XFF180320
-#undef IOU_SLCR_SD_CONFIG_REG1_OFFSET 
+#undef IOU_SLCR_SD_CONFIG_REG1_OFFSET
 #define IOU_SLCR_SD_CONFIG_REG1_OFFSET                                             0XFF18031C
-#undef IOU_SLCR_SD_DLL_CTRL_OFFSET 
+#undef IOU_SLCR_SD_DLL_CTRL_OFFSET
 #define IOU_SLCR_SD_DLL_CTRL_OFFSET                                                0XFF180358
-#undef IOU_SLCR_SD_CONFIG_REG3_OFFSET 
+#undef IOU_SLCR_SD_CONFIG_REG3_OFFSET
 #define IOU_SLCR_SD_CONFIG_REG3_OFFSET                                             0XFF180324
-#undef CRL_APB_RST_LPD_IOU2_OFFSET 
+#undef CRL_APB_RST_LPD_IOU2_OFFSET
 #define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
-#undef CRL_APB_RST_LPD_IOU2_OFFSET 
+#undef CRL_APB_RST_LPD_IOU2_OFFSET
 #define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
-#undef CRL_APB_RST_LPD_IOU2_OFFSET 
+#undef CRL_APB_RST_LPD_IOU2_OFFSET
 #define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
-#undef CRL_APB_RST_LPD_IOU2_OFFSET 
+#undef CRL_APB_RST_LPD_IOU2_OFFSET
 #define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
-#undef CRL_APB_RST_LPD_IOU2_OFFSET 
+#undef CRL_APB_RST_LPD_IOU2_OFFSET
 #define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
-#undef UART0_BAUD_RATE_DIVIDER_REG0_OFFSET 
+#undef DP_AV_BUF_AUD_VID_CLK_SOURCE_OFFSET
+#define DP_AV_BUF_AUD_VID_CLK_SOURCE_OFFSET                                        0XFD4AB120
+#undef UART0_BAUD_RATE_DIVIDER_REG0_OFFSET
 #define UART0_BAUD_RATE_DIVIDER_REG0_OFFSET                                        0XFF000034
-#undef UART0_BAUD_RATE_GEN_REG0_OFFSET 
+#undef UART0_BAUD_RATE_GEN_REG0_OFFSET
 #define UART0_BAUD_RATE_GEN_REG0_OFFSET                                            0XFF000018
-#undef UART0_CONTROL_REG0_OFFSET 
+#undef UART0_CONTROL_REG0_OFFSET
 #define UART0_CONTROL_REG0_OFFSET                                                  0XFF000000
-#undef UART0_MODE_REG0_OFFSET 
+#undef UART0_MODE_REG0_OFFSET
 #define UART0_MODE_REG0_OFFSET                                                     0XFF000004
-#undef UART1_BAUD_RATE_DIVIDER_REG0_OFFSET 
+#undef UART1_BAUD_RATE_DIVIDER_REG0_OFFSET
 #define UART1_BAUD_RATE_DIVIDER_REG0_OFFSET                                        0XFF010034
-#undef UART1_BAUD_RATE_GEN_REG0_OFFSET 
+#undef UART1_BAUD_RATE_GEN_REG0_OFFSET
 #define UART1_BAUD_RATE_GEN_REG0_OFFSET                                            0XFF010018
-#undef UART1_CONTROL_REG0_OFFSET 
+#undef UART1_CONTROL_REG0_OFFSET
 #define UART1_CONTROL_REG0_OFFSET                                                  0XFF010000
-#undef UART1_MODE_REG0_OFFSET 
+#undef UART1_MODE_REG0_OFFSET
 #define UART1_MODE_REG0_OFFSET                                                     0XFF010004
-#undef CRL_APB_RST_LPD_IOU2_OFFSET 
+#undef CRL_APB_RST_LPD_IOU2_OFFSET
 #define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
-#undef LPD_SLCR_SECURE_SLCR_ADMA_OFFSET 
+#undef LPD_SLCR_SECURE_SLCR_ADMA_OFFSET
 #define LPD_SLCR_SECURE_SLCR_ADMA_OFFSET                                           0XFF4B0024
-#undef CSU_TAMPER_STATUS_OFFSET 
+#undef CSU_TAMPER_STATUS_OFFSET
 #define CSU_TAMPER_STATUS_OFFSET                                                   0XFFCA5000
-#undef APU_ACE_CTRL_OFFSET 
+#undef APU_ACE_CTRL_OFFSET
 #define APU_ACE_CTRL_OFFSET                                                        0XFD5C0060
-#undef RTC_CONTROL_OFFSET 
+#undef RTC_CONTROL_OFFSET
 #define RTC_CONTROL_OFFSET                                                         0XFFA60040
-#undef IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_OFFSET 
+#undef IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_OFFSET
 #define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_OFFSET                               0XFF260020
-#undef IOU_SCNTRS_COUNTER_CONTROL_REGISTER_OFFSET 
+#undef IOU_SCNTRS_COUNTER_CONTROL_REGISTER_OFFSET
 #define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_OFFSET                                 0XFF260000
 
 /*
 * Display Port block level reset (includes DPDMA)
 */
-#undef CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL 
-#undef CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT 
-#undef CRF_APB_RST_FPD_TOP_DP_RESET_MASK 
+#undef CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL
+#undef CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT
+#undef CRF_APB_RST_FPD_TOP_DP_RESET_MASK
 #define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL                    0x000F9FFE
 #define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT                     16
 #define CRF_APB_RST_FPD_TOP_DP_RESET_MASK                      0x00010000U
@@ -29612,9 +29614,9 @@
 /*
 * FPD WDT reset
 */
-#undef CRF_APB_RST_FPD_TOP_SWDT_RESET_DEFVAL 
-#undef CRF_APB_RST_FPD_TOP_SWDT_RESET_SHIFT 
-#undef CRF_APB_RST_FPD_TOP_SWDT_RESET_MASK 
+#undef CRF_APB_RST_FPD_TOP_SWDT_RESET_DEFVAL
+#undef CRF_APB_RST_FPD_TOP_SWDT_RESET_SHIFT
+#undef CRF_APB_RST_FPD_TOP_SWDT_RESET_MASK
 #define CRF_APB_RST_FPD_TOP_SWDT_RESET_DEFVAL                  0x000F9FFE
 #define CRF_APB_RST_FPD_TOP_SWDT_RESET_SHIFT                   15
 #define CRF_APB_RST_FPD_TOP_SWDT_RESET_MASK                    0x00008000U
@@ -29622,9 +29624,9 @@
 /*
 * GDMA block level reset
 */
-#undef CRF_APB_RST_FPD_TOP_GDMA_RESET_DEFVAL 
-#undef CRF_APB_RST_FPD_TOP_GDMA_RESET_SHIFT 
-#undef CRF_APB_RST_FPD_TOP_GDMA_RESET_MASK 
+#undef CRF_APB_RST_FPD_TOP_GDMA_RESET_DEFVAL
+#undef CRF_APB_RST_FPD_TOP_GDMA_RESET_SHIFT
+#undef CRF_APB_RST_FPD_TOP_GDMA_RESET_MASK
 #define CRF_APB_RST_FPD_TOP_GDMA_RESET_DEFVAL                  0x000F9FFE
 #define CRF_APB_RST_FPD_TOP_GDMA_RESET_SHIFT                   6
 #define CRF_APB_RST_FPD_TOP_GDMA_RESET_MASK                    0x00000040U
@@ -29632,9 +29634,9 @@
 /*
 * Pixel Processor (submodule of GPU) block level reset
 */
-#undef CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_DEFVAL 
-#undef CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_SHIFT 
-#undef CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_MASK 
+#undef CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_DEFVAL
+#undef CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_SHIFT
+#undef CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_MASK
 #define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_DEFVAL               0x000F9FFE
 #define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_SHIFT                4
 #define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_MASK                 0x00000010U
@@ -29642,9 +29644,9 @@
 /*
 * Pixel Processor (submodule of GPU) block level reset
 */
-#undef CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_DEFVAL 
-#undef CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_SHIFT 
-#undef CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_MASK 
+#undef CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_DEFVAL
+#undef CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_SHIFT
+#undef CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_MASK
 #define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_DEFVAL               0x000F9FFE
 #define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_SHIFT                5
 #define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_MASK                 0x00000020U
@@ -29652,9 +29654,9 @@
 /*
 * GPU block level reset
 */
-#undef CRF_APB_RST_FPD_TOP_GPU_RESET_DEFVAL 
-#undef CRF_APB_RST_FPD_TOP_GPU_RESET_SHIFT 
-#undef CRF_APB_RST_FPD_TOP_GPU_RESET_MASK 
+#undef CRF_APB_RST_FPD_TOP_GPU_RESET_DEFVAL
+#undef CRF_APB_RST_FPD_TOP_GPU_RESET_SHIFT
+#undef CRF_APB_RST_FPD_TOP_GPU_RESET_MASK
 #define CRF_APB_RST_FPD_TOP_GPU_RESET_DEFVAL                   0x000F9FFE
 #define CRF_APB_RST_FPD_TOP_GPU_RESET_SHIFT                    3
 #define CRF_APB_RST_FPD_TOP_GPU_RESET_MASK                     0x00000008U
@@ -29662,9 +29664,9 @@
 /*
 * GT block level reset
 */
-#undef CRF_APB_RST_FPD_TOP_GT_RESET_DEFVAL 
-#undef CRF_APB_RST_FPD_TOP_GT_RESET_SHIFT 
-#undef CRF_APB_RST_FPD_TOP_GT_RESET_MASK 
+#undef CRF_APB_RST_FPD_TOP_GT_RESET_DEFVAL
+#undef CRF_APB_RST_FPD_TOP_GT_RESET_SHIFT
+#undef CRF_APB_RST_FPD_TOP_GT_RESET_MASK
 #define CRF_APB_RST_FPD_TOP_GT_RESET_DEFVAL                    0x000F9FFE
 #define CRF_APB_RST_FPD_TOP_GT_RESET_SHIFT                     2
 #define CRF_APB_RST_FPD_TOP_GT_RESET_MASK                      0x00000004U
@@ -29672,9 +29674,9 @@
 /*
 * Sata block level reset
 */
-#undef CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL 
-#undef CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT 
-#undef CRF_APB_RST_FPD_TOP_SATA_RESET_MASK 
+#undef CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL
+#undef CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT
+#undef CRF_APB_RST_FPD_TOP_SATA_RESET_MASK
 #define CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL                  0x000F9FFE
 #define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT                   1
 #define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK                    0x00000002U
@@ -29682,9 +29684,9 @@
 /*
 * Block level reset
 */
-#undef CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_DEFVAL 
-#undef CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_SHIFT 
-#undef CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_MASK 
+#undef CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_DEFVAL
+#undef CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_SHIFT
+#undef CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_MASK
 #define CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_DEFVAL            0x0017FFFF
 #define CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_SHIFT             20
 #define CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_MASK              0x00100000U
@@ -29692,9 +29694,9 @@
 /*
 * Block level reset
 */
-#undef CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_DEFVAL 
-#undef CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_SHIFT 
-#undef CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_MASK 
+#undef CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_DEFVAL
+#undef CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_SHIFT
+#undef CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_MASK
 #define CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_DEFVAL               0x0017FFFF
 #define CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_SHIFT                19
 #define CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_MASK                 0x00080000U
@@ -29702,9 +29704,9 @@
 /*
 * Block level reset
 */
-#undef CRL_APB_RST_LPD_IOU2_ADMA_RESET_DEFVAL 
-#undef CRL_APB_RST_LPD_IOU2_ADMA_RESET_SHIFT 
-#undef CRL_APB_RST_LPD_IOU2_ADMA_RESET_MASK 
+#undef CRL_APB_RST_LPD_IOU2_ADMA_RESET_DEFVAL
+#undef CRL_APB_RST_LPD_IOU2_ADMA_RESET_SHIFT
+#undef CRL_APB_RST_LPD_IOU2_ADMA_RESET_MASK
 #define CRL_APB_RST_LPD_IOU2_ADMA_RESET_DEFVAL                 0x0017FFFF
 #define CRL_APB_RST_LPD_IOU2_ADMA_RESET_SHIFT                  17
 #define CRL_APB_RST_LPD_IOU2_ADMA_RESET_MASK                   0x00020000U
@@ -29712,9 +29714,9 @@
 /*
 * Reset entire full power domain.
 */
-#undef CRL_APB_RST_LPD_TOP_FPD_RESET_DEFVAL 
-#undef CRL_APB_RST_LPD_TOP_FPD_RESET_SHIFT 
-#undef CRL_APB_RST_LPD_TOP_FPD_RESET_MASK 
+#undef CRL_APB_RST_LPD_TOP_FPD_RESET_DEFVAL
+#undef CRL_APB_RST_LPD_TOP_FPD_RESET_SHIFT
+#undef CRL_APB_RST_LPD_TOP_FPD_RESET_MASK
 #define CRL_APB_RST_LPD_TOP_FPD_RESET_DEFVAL                   0x00188FDF
 #define CRL_APB_RST_LPD_TOP_FPD_RESET_SHIFT                    23
 #define CRL_APB_RST_LPD_TOP_FPD_RESET_MASK                     0x00800000U
@@ -29722,9 +29724,9 @@
 /*
 * LPD SWDT
 */
-#undef CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_DEFVAL 
-#undef CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_SHIFT 
-#undef CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_MASK 
+#undef CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_DEFVAL
+#undef CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_SHIFT
+#undef CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_MASK
 #define CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_DEFVAL              0x00188FDF
 #define CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_SHIFT               20
 #define CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_MASK                0x00100000U
@@ -29732,9 +29734,9 @@
 /*
 * Sysmonitor reset
 */
-#undef CRL_APB_RST_LPD_TOP_SYSMON_RESET_DEFVAL 
-#undef CRL_APB_RST_LPD_TOP_SYSMON_RESET_SHIFT 
-#undef CRL_APB_RST_LPD_TOP_SYSMON_RESET_MASK 
+#undef CRL_APB_RST_LPD_TOP_SYSMON_RESET_DEFVAL
+#undef CRL_APB_RST_LPD_TOP_SYSMON_RESET_SHIFT
+#undef CRL_APB_RST_LPD_TOP_SYSMON_RESET_MASK
 #define CRL_APB_RST_LPD_TOP_SYSMON_RESET_DEFVAL                0x00188FDF
 #define CRL_APB_RST_LPD_TOP_SYSMON_RESET_SHIFT                 17
 #define CRL_APB_RST_LPD_TOP_SYSMON_RESET_MASK                  0x00020000U
@@ -29742,9 +29744,9 @@
 /*
 * Real Time Clock reset
 */
-#undef CRL_APB_RST_LPD_TOP_RTC_RESET_DEFVAL 
-#undef CRL_APB_RST_LPD_TOP_RTC_RESET_SHIFT 
-#undef CRL_APB_RST_LPD_TOP_RTC_RESET_MASK 
+#undef CRL_APB_RST_LPD_TOP_RTC_RESET_DEFVAL
+#undef CRL_APB_RST_LPD_TOP_RTC_RESET_SHIFT
+#undef CRL_APB_RST_LPD_TOP_RTC_RESET_MASK
 #define CRL_APB_RST_LPD_TOP_RTC_RESET_DEFVAL                   0x00188FDF
 #define CRL_APB_RST_LPD_TOP_RTC_RESET_SHIFT                    16
 #define CRL_APB_RST_LPD_TOP_RTC_RESET_MASK                     0x00010000U
@@ -29752,9 +29754,9 @@
 /*
 * APM reset
 */
-#undef CRL_APB_RST_LPD_TOP_APM_RESET_DEFVAL 
-#undef CRL_APB_RST_LPD_TOP_APM_RESET_SHIFT 
-#undef CRL_APB_RST_LPD_TOP_APM_RESET_MASK 
+#undef CRL_APB_RST_LPD_TOP_APM_RESET_DEFVAL
+#undef CRL_APB_RST_LPD_TOP_APM_RESET_SHIFT
+#undef CRL_APB_RST_LPD_TOP_APM_RESET_MASK
 #define CRL_APB_RST_LPD_TOP_APM_RESET_DEFVAL                   0x00188FDF
 #define CRL_APB_RST_LPD_TOP_APM_RESET_SHIFT                    15
 #define CRL_APB_RST_LPD_TOP_APM_RESET_MASK                     0x00008000U
@@ -29762,9 +29764,9 @@
 /*
 * IPI reset
 */
-#undef CRL_APB_RST_LPD_TOP_IPI_RESET_DEFVAL 
-#undef CRL_APB_RST_LPD_TOP_IPI_RESET_SHIFT 
-#undef CRL_APB_RST_LPD_TOP_IPI_RESET_MASK 
+#undef CRL_APB_RST_LPD_TOP_IPI_RESET_DEFVAL
+#undef CRL_APB_RST_LPD_TOP_IPI_RESET_SHIFT
+#undef CRL_APB_RST_LPD_TOP_IPI_RESET_MASK
 #define CRL_APB_RST_LPD_TOP_IPI_RESET_DEFVAL                   0x00188FDF
 #define CRL_APB_RST_LPD_TOP_IPI_RESET_SHIFT                    14
 #define CRL_APB_RST_LPD_TOP_IPI_RESET_MASK                     0x00004000U
@@ -29772,9 +29774,9 @@
 /*
 * reset entire RPU power island
 */
-#undef CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_DEFVAL 
-#undef CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_SHIFT 
-#undef CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_MASK 
+#undef CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_DEFVAL
+#undef CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_SHIFT
+#undef CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_MASK
 #define CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_DEFVAL               0x00188FDF
 #define CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_SHIFT                4
 #define CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_MASK                 0x00000010U
@@ -29782,9 +29784,9 @@
 /*
 * reset ocm
 */
-#undef CRL_APB_RST_LPD_TOP_OCM_RESET_DEFVAL 
-#undef CRL_APB_RST_LPD_TOP_OCM_RESET_SHIFT 
-#undef CRL_APB_RST_LPD_TOP_OCM_RESET_MASK 
+#undef CRL_APB_RST_LPD_TOP_OCM_RESET_DEFVAL
+#undef CRL_APB_RST_LPD_TOP_OCM_RESET_SHIFT
+#undef CRL_APB_RST_LPD_TOP_OCM_RESET_MASK
 #define CRL_APB_RST_LPD_TOP_OCM_RESET_DEFVAL                   0x00188FDF
 #define CRL_APB_RST_LPD_TOP_OCM_RESET_SHIFT                    3
 #define CRL_APB_RST_LPD_TOP_OCM_RESET_MASK                     0x00000008U
@@ -29792,9 +29794,9 @@
 /*
 * GEM 3 reset
 */
-#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL 
-#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT 
-#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK 
+#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL
+#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT
+#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK
 #define CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL                 0x0000000F
 #define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT                  3
 #define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK                   0x00000008U
@@ -29802,9 +29804,9 @@
 /*
 * Block level reset
 */
-#undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_DEFVAL 
-#undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT 
-#undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK 
+#undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_DEFVAL
+#undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT
+#undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK
 #define CRL_APB_RST_LPD_IOU2_QSPI_RESET_DEFVAL                 0x0017FFFF
 #define CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT                  0
 #define CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK                   0x00000001U
@@ -29813,9 +29815,9 @@
 * 0: Do not by pass the tap delays on the Rx clock signal of LQSPI 1: Bypa
     * ss the Tap delay on the Rx clock signal of LQSPI
 */
-#undef IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_DEFVAL 
-#undef IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT 
-#undef IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_MASK 
+#undef IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_DEFVAL
+#undef IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT
+#undef IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_MASK
 #define IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_DEFVAL             0x00000007
 #define IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT              2
 #define IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_MASK               0x00000004U
@@ -29823,9 +29825,9 @@
 /*
 * USB 0 reset for control registers
 */
-#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL 
-#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT 
-#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK 
+#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL
+#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT
+#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK
 #define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL              0x00188FDF
 #define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT               10
 #define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK                0x00000400U
@@ -29833,9 +29835,9 @@
 /*
 * USB 0 sleep circuit reset
 */
-#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL 
-#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT 
-#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK 
+#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL
+#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT
+#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK
 #define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL             0x00188FDF
 #define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT              8
 #define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK               0x00000100U
@@ -29843,9 +29845,9 @@
 /*
 * USB 0 reset
 */
-#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL 
-#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 
-#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK 
+#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL
+#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT
+#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK
 #define CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL              0x00188FDF
 #define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT               6
 #define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK                0x00000040U
@@ -29853,9 +29855,9 @@
 /*
 * Block level reset
 */
-#undef CRL_APB_RST_LPD_IOU2_SDIO1_RESET_DEFVAL 
-#undef CRL_APB_RST_LPD_IOU2_SDIO1_RESET_SHIFT 
-#undef CRL_APB_RST_LPD_IOU2_SDIO1_RESET_MASK 
+#undef CRL_APB_RST_LPD_IOU2_SDIO1_RESET_DEFVAL
+#undef CRL_APB_RST_LPD_IOU2_SDIO1_RESET_SHIFT
+#undef CRL_APB_RST_LPD_IOU2_SDIO1_RESET_MASK
 #define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_DEFVAL                0x0017FFFF
 #define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_SHIFT                 6
 #define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_MASK                  0x00000040U
@@ -29863,9 +29865,9 @@
 /*
 * SD or eMMC selection on SDIO1 0: SD enabled 1: eMMC enabled
 */
-#undef IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_DEFVAL 
-#undef IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_SHIFT 
-#undef IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_MASK 
+#undef IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_DEFVAL
+#undef IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_SHIFT
+#undef IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_MASK
 #define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_DEFVAL               0x00000000
 #define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_SHIFT                15
 #define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_MASK                 0x00008000U
@@ -29874,9 +29876,9 @@
 * Should be set based on the final product usage 00 - Removable SCard Slot
     *  01 - Embedded Slot for One Device 10 - Shared Bus Slot 11 - Reserved
 */
-#undef IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_DEFVAL 
-#undef IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_SHIFT 
-#undef IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_MASK 
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_DEFVAL
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_SHIFT
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_MASK
 #define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_DEFVAL            0x0FFC0FFC
 #define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_SHIFT             28
 #define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_MASK              0x30000000U
@@ -29884,9 +29886,9 @@
 /*
 * 1.8V Support 1: 1.8V supported 0: 1.8V not supported support
 */
-#undef IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_DEFVAL 
-#undef IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_SHIFT 
-#undef IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_MASK 
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_DEFVAL
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_SHIFT
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_MASK
 #define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_DEFVAL                0x0FFC0FFC
 #define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_SHIFT                 25
 #define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_MASK                  0x02000000U
@@ -29894,9 +29896,9 @@
 /*
 * 3.0V Support 1: 3.0V supported 0: 3.0V not supported support
 */
-#undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_DEFVAL 
-#undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_SHIFT 
-#undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_MASK 
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_DEFVAL
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_SHIFT
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_MASK
 #define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_DEFVAL                0x0FFC0FFC
 #define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_SHIFT                 24
 #define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_MASK                  0x01000000U
@@ -29904,9 +29906,9 @@
 /*
 * 3.3V Support 1: 3.3V supported 0: 3.3V not supported support
 */
-#undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_DEFVAL 
-#undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_SHIFT 
-#undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_MASK 
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_DEFVAL
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_SHIFT
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_MASK
 #define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_DEFVAL                0x0FFC0FFC
 #define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_SHIFT                 23
 #define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_MASK                  0x00800000U
@@ -29914,9 +29916,9 @@
 /*
 * Base Clock Frequency for SD Clock. This is the frequency of the xin_clk.
 */
-#undef IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_DEFVAL 
-#undef IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_SHIFT 
-#undef IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_MASK 
+#undef IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_DEFVAL
+#undef IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_SHIFT
+#undef IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_MASK
 #define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_DEFVAL             0x32403240
 #define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_SHIFT              23
 #define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_MASK               0x7F800000U
@@ -29925,9 +29927,9 @@
 * Configures the Number of Taps (Phases) of the rxclk_in that is supported
     * .
 */
-#undef IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT_DEFVAL 
-#undef IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT_SHIFT 
-#undef IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT_MASK 
+#undef IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT_DEFVAL
+#undef IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT_SHIFT
+#undef IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT_MASK
 #define IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT_DEFVAL          0x32403240
 #define IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT_SHIFT           17
 #define IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT_MASK            0x007E0000U
@@ -29935,9 +29937,9 @@
 /*
 * Reserved.
 */
-#undef IOU_SLCR_SD_DLL_CTRL_RESERVED_DEFVAL 
-#undef IOU_SLCR_SD_DLL_CTRL_RESERVED_SHIFT 
-#undef IOU_SLCR_SD_DLL_CTRL_RESERVED_MASK 
+#undef IOU_SLCR_SD_DLL_CTRL_RESERVED_DEFVAL
+#undef IOU_SLCR_SD_DLL_CTRL_RESERVED_SHIFT
+#undef IOU_SLCR_SD_DLL_CTRL_RESERVED_MASK
 #define IOU_SLCR_SD_DLL_CTRL_RESERVED_DEFVAL                   0x00080008
 #define IOU_SLCR_SD_DLL_CTRL_RESERVED_SHIFT                    3
 #define IOU_SLCR_SD_DLL_CTRL_RESERVED_MASK                     0x00000008U
@@ -29948,9 +29950,9 @@
     * source 1h = 1 seconds 2h = 2 seconds 3h = 4 seconds 4h = 8 seconds -- n
     * = 2(n-1) seconds -- Bh = 1024 seconds Fh - Ch = Reserved
 */
-#undef IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_DEFVAL 
-#undef IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_SHIFT 
-#undef IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_MASK 
+#undef IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_DEFVAL
+#undef IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_SHIFT
+#undef IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_MASK
 #define IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_DEFVAL           0x06070607
 #define IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_SHIFT            22
 #define IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_MASK             0x03C00000U
@@ -29958,9 +29960,9 @@
 /*
 * Block level reset
 */
-#undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_DEFVAL 
-#undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_SHIFT 
-#undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_MASK 
+#undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_DEFVAL
+#undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_SHIFT
+#undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_MASK
 #define CRL_APB_RST_LPD_IOU2_CAN1_RESET_DEFVAL                 0x0017FFFF
 #define CRL_APB_RST_LPD_IOU2_CAN1_RESET_SHIFT                  8
 #define CRL_APB_RST_LPD_IOU2_CAN1_RESET_MASK                   0x00000100U
@@ -29968,9 +29970,9 @@
 /*
 * Block level reset
 */
-#undef CRL_APB_RST_LPD_IOU2_I2C1_RESET_DEFVAL 
-#undef CRL_APB_RST_LPD_IOU2_I2C1_RESET_SHIFT 
-#undef CRL_APB_RST_LPD_IOU2_I2C1_RESET_MASK 
+#undef CRL_APB_RST_LPD_IOU2_I2C1_RESET_DEFVAL
+#undef CRL_APB_RST_LPD_IOU2_I2C1_RESET_SHIFT
+#undef CRL_APB_RST_LPD_IOU2_I2C1_RESET_MASK
 #define CRL_APB_RST_LPD_IOU2_I2C1_RESET_DEFVAL                 0x0017FFFF
 #define CRL_APB_RST_LPD_IOU2_I2C1_RESET_SHIFT                  10
 #define CRL_APB_RST_LPD_IOU2_I2C1_RESET_MASK                   0x00000400U
@@ -29978,9 +29980,9 @@
 /*
 * Block level reset
 */
-#undef CRL_APB_RST_LPD_IOU2_SWDT_RESET_DEFVAL 
-#undef CRL_APB_RST_LPD_IOU2_SWDT_RESET_SHIFT 
-#undef CRL_APB_RST_LPD_IOU2_SWDT_RESET_MASK 
+#undef CRL_APB_RST_LPD_IOU2_SWDT_RESET_DEFVAL
+#undef CRL_APB_RST_LPD_IOU2_SWDT_RESET_SHIFT
+#undef CRL_APB_RST_LPD_IOU2_SWDT_RESET_MASK
 #define CRL_APB_RST_LPD_IOU2_SWDT_RESET_DEFVAL                 0x0017FFFF
 #define CRL_APB_RST_LPD_IOU2_SWDT_RESET_SHIFT                  15
 #define CRL_APB_RST_LPD_IOU2_SWDT_RESET_MASK                   0x00008000U
@@ -29988,9 +29990,9 @@
 /*
 * Block level reset
 */
-#undef CRL_APB_RST_LPD_IOU2_TTC0_RESET_DEFVAL 
-#undef CRL_APB_RST_LPD_IOU2_TTC0_RESET_SHIFT 
-#undef CRL_APB_RST_LPD_IOU2_TTC0_RESET_MASK 
+#undef CRL_APB_RST_LPD_IOU2_TTC0_RESET_DEFVAL
+#undef CRL_APB_RST_LPD_IOU2_TTC0_RESET_SHIFT
+#undef CRL_APB_RST_LPD_IOU2_TTC0_RESET_MASK
 #define CRL_APB_RST_LPD_IOU2_TTC0_RESET_DEFVAL                 0x0017FFFF
 #define CRL_APB_RST_LPD_IOU2_TTC0_RESET_SHIFT                  11
 #define CRL_APB_RST_LPD_IOU2_TTC0_RESET_MASK                   0x00000800U
@@ -29998,9 +30000,9 @@
 /*
 * Block level reset
 */
-#undef CRL_APB_RST_LPD_IOU2_TTC1_RESET_DEFVAL 
-#undef CRL_APB_RST_LPD_IOU2_TTC1_RESET_SHIFT 
-#undef CRL_APB_RST_LPD_IOU2_TTC1_RESET_MASK 
+#undef CRL_APB_RST_LPD_IOU2_TTC1_RESET_DEFVAL
+#undef CRL_APB_RST_LPD_IOU2_TTC1_RESET_SHIFT
+#undef CRL_APB_RST_LPD_IOU2_TTC1_RESET_MASK
 #define CRL_APB_RST_LPD_IOU2_TTC1_RESET_DEFVAL                 0x0017FFFF
 #define CRL_APB_RST_LPD_IOU2_TTC1_RESET_SHIFT                  12
 #define CRL_APB_RST_LPD_IOU2_TTC1_RESET_MASK                   0x00001000U
@@ -30008,9 +30010,9 @@
 /*
 * Block level reset
 */
-#undef CRL_APB_RST_LPD_IOU2_TTC2_RESET_DEFVAL 
-#undef CRL_APB_RST_LPD_IOU2_TTC2_RESET_SHIFT 
-#undef CRL_APB_RST_LPD_IOU2_TTC2_RESET_MASK 
+#undef CRL_APB_RST_LPD_IOU2_TTC2_RESET_DEFVAL
+#undef CRL_APB_RST_LPD_IOU2_TTC2_RESET_SHIFT
+#undef CRL_APB_RST_LPD_IOU2_TTC2_RESET_MASK
 #define CRL_APB_RST_LPD_IOU2_TTC2_RESET_DEFVAL                 0x0017FFFF
 #define CRL_APB_RST_LPD_IOU2_TTC2_RESET_SHIFT                  13
 #define CRL_APB_RST_LPD_IOU2_TTC2_RESET_MASK                   0x00002000U
@@ -30018,9 +30020,9 @@
 /*
 * Block level reset
 */
-#undef CRL_APB_RST_LPD_IOU2_TTC3_RESET_DEFVAL 
-#undef CRL_APB_RST_LPD_IOU2_TTC3_RESET_SHIFT 
-#undef CRL_APB_RST_LPD_IOU2_TTC3_RESET_MASK 
+#undef CRL_APB_RST_LPD_IOU2_TTC3_RESET_DEFVAL
+#undef CRL_APB_RST_LPD_IOU2_TTC3_RESET_SHIFT
+#undef CRL_APB_RST_LPD_IOU2_TTC3_RESET_MASK
 #define CRL_APB_RST_LPD_IOU2_TTC3_RESET_DEFVAL                 0x0017FFFF
 #define CRL_APB_RST_LPD_IOU2_TTC3_RESET_SHIFT                  14
 #define CRL_APB_RST_LPD_IOU2_TTC3_RESET_MASK                   0x00004000U
@@ -30028,9 +30030,9 @@
 /*
 * Block level reset
 */
-#undef CRL_APB_RST_LPD_IOU2_UART0_RESET_DEFVAL 
-#undef CRL_APB_RST_LPD_IOU2_UART0_RESET_SHIFT 
-#undef CRL_APB_RST_LPD_IOU2_UART0_RESET_MASK 
+#undef CRL_APB_RST_LPD_IOU2_UART0_RESET_DEFVAL
+#undef CRL_APB_RST_LPD_IOU2_UART0_RESET_SHIFT
+#undef CRL_APB_RST_LPD_IOU2_UART0_RESET_MASK
 #define CRL_APB_RST_LPD_IOU2_UART0_RESET_DEFVAL                0x0017FFFF
 #define CRL_APB_RST_LPD_IOU2_UART0_RESET_SHIFT                 1
 #define CRL_APB_RST_LPD_IOU2_UART0_RESET_MASK                  0x00000002U
@@ -30038,19 +30040,52 @@
 /*
 * Block level reset
 */
-#undef CRL_APB_RST_LPD_IOU2_UART1_RESET_DEFVAL 
-#undef CRL_APB_RST_LPD_IOU2_UART1_RESET_SHIFT 
-#undef CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK 
+#undef CRL_APB_RST_LPD_IOU2_UART1_RESET_DEFVAL
+#undef CRL_APB_RST_LPD_IOU2_UART1_RESET_SHIFT
+#undef CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK
 #define CRL_APB_RST_LPD_IOU2_UART1_RESET_DEFVAL                0x0017FFFF
 #define CRL_APB_RST_LPD_IOU2_UART1_RESET_SHIFT                 2
 #define CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK                  0x00000004U
 
+/*
+* Bits[2] - - 0: Timing from PL (Default) - 1: Internal Timing This bit ca
+    * n be used in case where Internal VTC is clocked using PL clock. Typical
+    * use case is, when Video from memory is blended and output to PL
+*/
+#undef DP_AV_BUF_AUD_VID_CLK_SOURCE_VID_TIMING_SRC_DEFVAL
+#undef DP_AV_BUF_AUD_VID_CLK_SOURCE_VID_TIMING_SRC_SHIFT
+#undef DP_AV_BUF_AUD_VID_CLK_SOURCE_VID_TIMING_SRC_MASK
+#define DP_AV_BUF_AUD_VID_CLK_SOURCE_VID_TIMING_SRC_DEFVAL     0x00000000
+#define DP_AV_BUF_AUD_VID_CLK_SOURCE_VID_TIMING_SRC_SHIFT      2
+#define DP_AV_BUF_AUD_VID_CLK_SOURCE_VID_TIMING_SRC_MASK       0x00000004U
+
+/*
+* Bits[0] - - 0: clock from PL (Default) dp_live_video_in_clk - 1: Clock f
+    * rom PS(dp_vtc_pixel_clk_in)
+*/
+#undef DP_AV_BUF_AUD_VID_CLK_SOURCE_VID_CLK_SRC_DEFVAL
+#undef DP_AV_BUF_AUD_VID_CLK_SOURCE_VID_CLK_SRC_SHIFT
+#undef DP_AV_BUF_AUD_VID_CLK_SOURCE_VID_CLK_SRC_MASK
+#define DP_AV_BUF_AUD_VID_CLK_SOURCE_VID_CLK_SRC_DEFVAL        0x00000000
+#define DP_AV_BUF_AUD_VID_CLK_SOURCE_VID_CLK_SRC_SHIFT         0
+#define DP_AV_BUF_AUD_VID_CLK_SOURCE_VID_CLK_SRC_MASK          0x00000001U
+
+/*
+* Bits[1] - - 0: clock from PL (Default) - 1: Clock from PS
+*/
+#undef DP_AV_BUF_AUD_VID_CLK_SOURCE_AUD_CLK_SRC_DEFVAL
+#undef DP_AV_BUF_AUD_VID_CLK_SOURCE_AUD_CLK_SRC_SHIFT
+#undef DP_AV_BUF_AUD_VID_CLK_SOURCE_AUD_CLK_SRC_MASK
+#define DP_AV_BUF_AUD_VID_CLK_SOURCE_AUD_CLK_SRC_DEFVAL        0x00000000
+#define DP_AV_BUF_AUD_VID_CLK_SOURCE_AUD_CLK_SRC_SHIFT         1
+#define DP_AV_BUF_AUD_VID_CLK_SOURCE_AUD_CLK_SRC_MASK          0x00000002U
+
 /*
 * Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate
 */
-#undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL 
-#undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT 
-#undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_MASK 
+#undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL
+#undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT
+#undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_MASK
 #define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL               0x0000000F
 #define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT                0
 #define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_MASK                 0x000000FFU
@@ -30059,9 +30094,9 @@
 * Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor
     * bypass (baud_sample = sel_clk) 2 - 65535: baud_sample
 */
-#undef UART0_BAUD_RATE_GEN_REG0_CD_DEFVAL 
-#undef UART0_BAUD_RATE_GEN_REG0_CD_SHIFT 
-#undef UART0_BAUD_RATE_GEN_REG0_CD_MASK 
+#undef UART0_BAUD_RATE_GEN_REG0_CD_DEFVAL
+#undef UART0_BAUD_RATE_GEN_REG0_CD_SHIFT
+#undef UART0_BAUD_RATE_GEN_REG0_CD_MASK
 #define UART0_BAUD_RATE_GEN_REG0_CD_DEFVAL                     0x0000028B
 #define UART0_BAUD_RATE_GEN_REG0_CD_SHIFT                      0
 #define UART0_BAUD_RATE_GEN_REG0_CD_MASK                       0x0000FFFFU
@@ -30071,9 +30106,9 @@
     * fter a minimum of one character length and transmit a high level during
     * 12 bit periods. It can be set regardless of the value of STTBRK.
 */
-#undef UART0_CONTROL_REG0_STPBRK_DEFVAL 
-#undef UART0_CONTROL_REG0_STPBRK_SHIFT 
-#undef UART0_CONTROL_REG0_STPBRK_MASK 
+#undef UART0_CONTROL_REG0_STPBRK_DEFVAL
+#undef UART0_CONTROL_REG0_STPBRK_SHIFT
+#undef UART0_CONTROL_REG0_STPBRK_MASK
 #define UART0_CONTROL_REG0_STPBRK_DEFVAL                       0x00000128
 #define UART0_CONTROL_REG0_STPBRK_SHIFT                        8
 #define UART0_CONTROL_REG0_STPBRK_MASK                         0x00000100U
@@ -30084,9 +30119,9 @@
     * ister have been transmitted. It can only be set if STPBRK (Stop transmit
     * ter break) is not high.
 */
-#undef UART0_CONTROL_REG0_STTBRK_DEFVAL 
-#undef UART0_CONTROL_REG0_STTBRK_SHIFT 
-#undef UART0_CONTROL_REG0_STTBRK_MASK 
+#undef UART0_CONTROL_REG0_STTBRK_DEFVAL
+#undef UART0_CONTROL_REG0_STTBRK_SHIFT
+#undef UART0_CONTROL_REG0_STTBRK_MASK
 #define UART0_CONTROL_REG0_STTBRK_DEFVAL                       0x00000128
 #define UART0_CONTROL_REG0_STTBRK_SHIFT                        7
 #define UART0_CONTROL_REG0_STTBRK_MASK                         0x00000080U
@@ -30095,9 +30130,9 @@
 * Restart receiver timeout counter: 1: receiver timeout counter is restart
     * ed. This bit is self clearing once the restart has completed.
 */
-#undef UART0_CONTROL_REG0_RSTTO_DEFVAL 
-#undef UART0_CONTROL_REG0_RSTTO_SHIFT 
-#undef UART0_CONTROL_REG0_RSTTO_MASK 
+#undef UART0_CONTROL_REG0_RSTTO_DEFVAL
+#undef UART0_CONTROL_REG0_RSTTO_SHIFT
+#undef UART0_CONTROL_REG0_RSTTO_MASK
 #define UART0_CONTROL_REG0_RSTTO_DEFVAL                        0x00000128
 #define UART0_CONTROL_REG0_RSTTO_SHIFT                         6
 #define UART0_CONTROL_REG0_RSTTO_MASK                          0x00000040U
@@ -30105,9 +30140,9 @@
 /*
 * Transmit disable: 0: enable transmitter 1: disable transmitter
 */
-#undef UART0_CONTROL_REG0_TXDIS_DEFVAL 
-#undef UART0_CONTROL_REG0_TXDIS_SHIFT 
-#undef UART0_CONTROL_REG0_TXDIS_MASK 
+#undef UART0_CONTROL_REG0_TXDIS_DEFVAL
+#undef UART0_CONTROL_REG0_TXDIS_SHIFT
+#undef UART0_CONTROL_REG0_TXDIS_MASK
 #define UART0_CONTROL_REG0_TXDIS_DEFVAL                        0x00000128
 #define UART0_CONTROL_REG0_TXDIS_SHIFT                         5
 #define UART0_CONTROL_REG0_TXDIS_MASK                          0x00000020U
@@ -30116,9 +30151,9 @@
 * Transmit enable: 0: disable transmitter 1: enable transmitter, provided
     * the TXDIS field is set to 0.
 */
-#undef UART0_CONTROL_REG0_TXEN_DEFVAL 
-#undef UART0_CONTROL_REG0_TXEN_SHIFT 
-#undef UART0_CONTROL_REG0_TXEN_MASK 
+#undef UART0_CONTROL_REG0_TXEN_DEFVAL
+#undef UART0_CONTROL_REG0_TXEN_SHIFT
+#undef UART0_CONTROL_REG0_TXEN_MASK
 #define UART0_CONTROL_REG0_TXEN_DEFVAL                         0x00000128
 #define UART0_CONTROL_REG0_TXEN_SHIFT                          4
 #define UART0_CONTROL_REG0_TXEN_MASK                           0x00000010U
@@ -30126,9 +30161,9 @@
 /*
 * Receive disable: 0: enable 1: disable, regardless of the value of RXEN
 */
-#undef UART0_CONTROL_REG0_RXDIS_DEFVAL 
-#undef UART0_CONTROL_REG0_RXDIS_SHIFT 
-#undef UART0_CONTROL_REG0_RXDIS_MASK 
+#undef UART0_CONTROL_REG0_RXDIS_DEFVAL
+#undef UART0_CONTROL_REG0_RXDIS_SHIFT
+#undef UART0_CONTROL_REG0_RXDIS_MASK
 #define UART0_CONTROL_REG0_RXDIS_DEFVAL                        0x00000128
 #define UART0_CONTROL_REG0_RXDIS_SHIFT                         3
 #define UART0_CONTROL_REG0_RXDIS_MASK                          0x00000008U
@@ -30137,9 +30172,9 @@
 * Receive enable: 0: disable 1: enable When set to one, the receiver logic
     *  is enabled, provided the RXDIS field is set to zero.
 */
-#undef UART0_CONTROL_REG0_RXEN_DEFVAL 
-#undef UART0_CONTROL_REG0_RXEN_SHIFT 
-#undef UART0_CONTROL_REG0_RXEN_MASK 
+#undef UART0_CONTROL_REG0_RXEN_DEFVAL
+#undef UART0_CONTROL_REG0_RXEN_SHIFT
+#undef UART0_CONTROL_REG0_RXEN_MASK
 #define UART0_CONTROL_REG0_RXEN_DEFVAL                         0x00000128
 #define UART0_CONTROL_REG0_RXEN_SHIFT                          2
 #define UART0_CONTROL_REG0_RXEN_MASK                           0x00000004U
@@ -30149,9 +30184,9 @@
     * set and all pending transmitter data is discarded This bit is self clear
     * ing once the reset has completed.
 */
-#undef UART0_CONTROL_REG0_TXRES_DEFVAL 
-#undef UART0_CONTROL_REG0_TXRES_SHIFT 
-#undef UART0_CONTROL_REG0_TXRES_MASK 
+#undef UART0_CONTROL_REG0_TXRES_DEFVAL
+#undef UART0_CONTROL_REG0_TXRES_SHIFT
+#undef UART0_CONTROL_REG0_TXRES_MASK
 #define UART0_CONTROL_REG0_TXRES_DEFVAL                        0x00000128
 #define UART0_CONTROL_REG0_TXRES_SHIFT                         1
 #define UART0_CONTROL_REG0_TXRES_MASK                          0x00000002U
@@ -30161,9 +30196,9 @@
     *  and all pending receiver data is discarded. This bit is self clearing o
     * nce the reset has completed.
 */
-#undef UART0_CONTROL_REG0_RXRES_DEFVAL 
-#undef UART0_CONTROL_REG0_RXRES_SHIFT 
-#undef UART0_CONTROL_REG0_RXRES_MASK 
+#undef UART0_CONTROL_REG0_RXRES_DEFVAL
+#undef UART0_CONTROL_REG0_RXRES_SHIFT
+#undef UART0_CONTROL_REG0_RXRES_MASK
 #define UART0_CONTROL_REG0_RXRES_DEFVAL                        0x00000128
 #define UART0_CONTROL_REG0_RXRES_SHIFT                         0
 #define UART0_CONTROL_REG0_RXRES_MASK                          0x00000001U
@@ -30172,9 +30207,9 @@
 * Channel mode: Defines the mode of operation of the UART. 00: normal 01:
     * automatic echo 10: local loopback 11: remote loopback
 */
-#undef UART0_MODE_REG0_CHMODE_DEFVAL 
-#undef UART0_MODE_REG0_CHMODE_SHIFT 
-#undef UART0_MODE_REG0_CHMODE_MASK 
+#undef UART0_MODE_REG0_CHMODE_DEFVAL
+#undef UART0_MODE_REG0_CHMODE_SHIFT
+#undef UART0_MODE_REG0_CHMODE_MASK
 #define UART0_MODE_REG0_CHMODE_DEFVAL                          0x00000000
 #define UART0_MODE_REG0_CHMODE_SHIFT                           8
 #define UART0_MODE_REG0_CHMODE_MASK                            0x00000300U
@@ -30184,9 +30219,9 @@
     * e and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 st
     * op bits 11: reserved
 */
-#undef UART0_MODE_REG0_NBSTOP_DEFVAL 
-#undef UART0_MODE_REG0_NBSTOP_SHIFT 
-#undef UART0_MODE_REG0_NBSTOP_MASK 
+#undef UART0_MODE_REG0_NBSTOP_DEFVAL
+#undef UART0_MODE_REG0_NBSTOP_SHIFT
+#undef UART0_MODE_REG0_NBSTOP_MASK
 #define UART0_MODE_REG0_NBSTOP_DEFVAL                          0x00000000
 #define UART0_MODE_REG0_NBSTOP_SHIFT                           6
 #define UART0_MODE_REG0_NBSTOP_MASK                            0x000000C0U
@@ -30197,9 +30232,9 @@
     * : forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no pari
     * ty
 */
-#undef UART0_MODE_REG0_PAR_DEFVAL 
-#undef UART0_MODE_REG0_PAR_SHIFT 
-#undef UART0_MODE_REG0_PAR_MASK 
+#undef UART0_MODE_REG0_PAR_DEFVAL
+#undef UART0_MODE_REG0_PAR_SHIFT
+#undef UART0_MODE_REG0_PAR_MASK
 #define UART0_MODE_REG0_PAR_DEFVAL                             0x00000000
 #define UART0_MODE_REG0_PAR_SHIFT                              3
 #define UART0_MODE_REG0_PAR_MASK                               0x00000038U
@@ -30208,9 +30243,9 @@
 * Character length select: Defines the number of bits in each character. 1
     * 1: 6 bits 10: 7 bits 0x: 8 bits
 */
-#undef UART0_MODE_REG0_CHRL_DEFVAL 
-#undef UART0_MODE_REG0_CHRL_SHIFT 
-#undef UART0_MODE_REG0_CHRL_MASK 
+#undef UART0_MODE_REG0_CHRL_DEFVAL
+#undef UART0_MODE_REG0_CHRL_SHIFT
+#undef UART0_MODE_REG0_CHRL_MASK
 #define UART0_MODE_REG0_CHRL_DEFVAL                            0x00000000
 #define UART0_MODE_REG0_CHRL_SHIFT                             1
 #define UART0_MODE_REG0_CHRL_MASK                              0x00000006U
@@ -30220,9 +30255,9 @@
     * lied to the baud rate generator input clock. 0: clock source is uart_ref
     * _clk 1: clock source is uart_ref_clk/8
 */
-#undef UART0_MODE_REG0_CLKS_DEFVAL 
-#undef UART0_MODE_REG0_CLKS_SHIFT 
-#undef UART0_MODE_REG0_CLKS_MASK 
+#undef UART0_MODE_REG0_CLKS_DEFVAL
+#undef UART0_MODE_REG0_CLKS_SHIFT
+#undef UART0_MODE_REG0_CLKS_MASK
 #define UART0_MODE_REG0_CLKS_DEFVAL                            0x00000000
 #define UART0_MODE_REG0_CLKS_SHIFT                             0
 #define UART0_MODE_REG0_CLKS_MASK                              0x00000001U
@@ -30230,9 +30265,9 @@
 /*
 * Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate
 */
-#undef UART1_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL 
-#undef UART1_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT 
-#undef UART1_BAUD_RATE_DIVIDER_REG0_BDIV_MASK 
+#undef UART1_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL
+#undef UART1_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT
+#undef UART1_BAUD_RATE_DIVIDER_REG0_BDIV_MASK
 #define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL               0x0000000F
 #define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT                0
 #define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_MASK                 0x000000FFU
@@ -30241,9 +30276,9 @@
 * Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor
     * bypass (baud_sample = sel_clk) 2 - 65535: baud_sample
 */
-#undef UART1_BAUD_RATE_GEN_REG0_CD_DEFVAL 
-#undef UART1_BAUD_RATE_GEN_REG0_CD_SHIFT 
-#undef UART1_BAUD_RATE_GEN_REG0_CD_MASK 
+#undef UART1_BAUD_RATE_GEN_REG0_CD_DEFVAL
+#undef UART1_BAUD_RATE_GEN_REG0_CD_SHIFT
+#undef UART1_BAUD_RATE_GEN_REG0_CD_MASK
 #define UART1_BAUD_RATE_GEN_REG0_CD_DEFVAL                     0x0000028B
 #define UART1_BAUD_RATE_GEN_REG0_CD_SHIFT                      0
 #define UART1_BAUD_RATE_GEN_REG0_CD_MASK                       0x0000FFFFU
@@ -30253,9 +30288,9 @@
     * fter a minimum of one character length and transmit a high level during
     * 12 bit periods. It can be set regardless of the value of STTBRK.
 */
-#undef UART1_CONTROL_REG0_STPBRK_DEFVAL 
-#undef UART1_CONTROL_REG0_STPBRK_SHIFT 
-#undef UART1_CONTROL_REG0_STPBRK_MASK 
+#undef UART1_CONTROL_REG0_STPBRK_DEFVAL
+#undef UART1_CONTROL_REG0_STPBRK_SHIFT
+#undef UART1_CONTROL_REG0_STPBRK_MASK
 #define UART1_CONTROL_REG0_STPBRK_DEFVAL                       0x00000128
 #define UART1_CONTROL_REG0_STPBRK_SHIFT                        8
 #define UART1_CONTROL_REG0_STPBRK_MASK                         0x00000100U
@@ -30266,9 +30301,9 @@
     * ister have been transmitted. It can only be set if STPBRK (Stop transmit
     * ter break) is not high.
 */
-#undef UART1_CONTROL_REG0_STTBRK_DEFVAL 
-#undef UART1_CONTROL_REG0_STTBRK_SHIFT 
-#undef UART1_CONTROL_REG0_STTBRK_MASK 
+#undef UART1_CONTROL_REG0_STTBRK_DEFVAL
+#undef UART1_CONTROL_REG0_STTBRK_SHIFT
+#undef UART1_CONTROL_REG0_STTBRK_MASK
 #define UART1_CONTROL_REG0_STTBRK_DEFVAL                       0x00000128
 #define UART1_CONTROL_REG0_STTBRK_SHIFT                        7
 #define UART1_CONTROL_REG0_STTBRK_MASK                         0x00000080U
@@ -30277,9 +30312,9 @@
 * Restart receiver timeout counter: 1: receiver timeout counter is restart
     * ed. This bit is self clearing once the restart has completed.
 */
-#undef UART1_CONTROL_REG0_RSTTO_DEFVAL 
-#undef UART1_CONTROL_REG0_RSTTO_SHIFT 
-#undef UART1_CONTROL_REG0_RSTTO_MASK 
+#undef UART1_CONTROL_REG0_RSTTO_DEFVAL
+#undef UART1_CONTROL_REG0_RSTTO_SHIFT
+#undef UART1_CONTROL_REG0_RSTTO_MASK
 #define UART1_CONTROL_REG0_RSTTO_DEFVAL                        0x00000128
 #define UART1_CONTROL_REG0_RSTTO_SHIFT                         6
 #define UART1_CONTROL_REG0_RSTTO_MASK                          0x00000040U
@@ -30287,9 +30322,9 @@
 /*
 * Transmit disable: 0: enable transmitter 1: disable transmitter
 */
-#undef UART1_CONTROL_REG0_TXDIS_DEFVAL 
-#undef UART1_CONTROL_REG0_TXDIS_SHIFT 
-#undef UART1_CONTROL_REG0_TXDIS_MASK 
+#undef UART1_CONTROL_REG0_TXDIS_DEFVAL
+#undef UART1_CONTROL_REG0_TXDIS_SHIFT
+#undef UART1_CONTROL_REG0_TXDIS_MASK
 #define UART1_CONTROL_REG0_TXDIS_DEFVAL                        0x00000128
 #define UART1_CONTROL_REG0_TXDIS_SHIFT                         5
 #define UART1_CONTROL_REG0_TXDIS_MASK                          0x00000020U
@@ -30298,9 +30333,9 @@
 * Transmit enable: 0: disable transmitter 1: enable transmitter, provided
     * the TXDIS field is set to 0.
 */
-#undef UART1_CONTROL_REG0_TXEN_DEFVAL 
-#undef UART1_CONTROL_REG0_TXEN_SHIFT 
-#undef UART1_CONTROL_REG0_TXEN_MASK 
+#undef UART1_CONTROL_REG0_TXEN_DEFVAL
+#undef UART1_CONTROL_REG0_TXEN_SHIFT
+#undef UART1_CONTROL_REG0_TXEN_MASK
 #define UART1_CONTROL_REG0_TXEN_DEFVAL                         0x00000128
 #define UART1_CONTROL_REG0_TXEN_SHIFT                          4
 #define UART1_CONTROL_REG0_TXEN_MASK                           0x00000010U
@@ -30308,9 +30343,9 @@
 /*
 * Receive disable: 0: enable 1: disable, regardless of the value of RXEN
 */
-#undef UART1_CONTROL_REG0_RXDIS_DEFVAL 
-#undef UART1_CONTROL_REG0_RXDIS_SHIFT 
-#undef UART1_CONTROL_REG0_RXDIS_MASK 
+#undef UART1_CONTROL_REG0_RXDIS_DEFVAL
+#undef UART1_CONTROL_REG0_RXDIS_SHIFT
+#undef UART1_CONTROL_REG0_RXDIS_MASK
 #define UART1_CONTROL_REG0_RXDIS_DEFVAL                        0x00000128
 #define UART1_CONTROL_REG0_RXDIS_SHIFT                         3
 #define UART1_CONTROL_REG0_RXDIS_MASK                          0x00000008U
@@ -30319,9 +30354,9 @@
 * Receive enable: 0: disable 1: enable When set to one, the receiver logic
     *  is enabled, provided the RXDIS field is set to zero.
 */
-#undef UART1_CONTROL_REG0_RXEN_DEFVAL 
-#undef UART1_CONTROL_REG0_RXEN_SHIFT 
-#undef UART1_CONTROL_REG0_RXEN_MASK 
+#undef UART1_CONTROL_REG0_RXEN_DEFVAL
+#undef UART1_CONTROL_REG0_RXEN_SHIFT
+#undef UART1_CONTROL_REG0_RXEN_MASK
 #define UART1_CONTROL_REG0_RXEN_DEFVAL                         0x00000128
 #define UART1_CONTROL_REG0_RXEN_SHIFT                          2
 #define UART1_CONTROL_REG0_RXEN_MASK                           0x00000004U
@@ -30331,9 +30366,9 @@
     * set and all pending transmitter data is discarded This bit is self clear
     * ing once the reset has completed.
 */
-#undef UART1_CONTROL_REG0_TXRES_DEFVAL 
-#undef UART1_CONTROL_REG0_TXRES_SHIFT 
-#undef UART1_CONTROL_REG0_TXRES_MASK 
+#undef UART1_CONTROL_REG0_TXRES_DEFVAL
+#undef UART1_CONTROL_REG0_TXRES_SHIFT
+#undef UART1_CONTROL_REG0_TXRES_MASK
 #define UART1_CONTROL_REG0_TXRES_DEFVAL                        0x00000128
 #define UART1_CONTROL_REG0_TXRES_SHIFT                         1
 #define UART1_CONTROL_REG0_TXRES_MASK                          0x00000002U
@@ -30343,9 +30378,9 @@
     *  and all pending receiver data is discarded. This bit is self clearing o
     * nce the reset has completed.
 */
-#undef UART1_CONTROL_REG0_RXRES_DEFVAL 
-#undef UART1_CONTROL_REG0_RXRES_SHIFT 
-#undef UART1_CONTROL_REG0_RXRES_MASK 
+#undef UART1_CONTROL_REG0_RXRES_DEFVAL
+#undef UART1_CONTROL_REG0_RXRES_SHIFT
+#undef UART1_CONTROL_REG0_RXRES_MASK
 #define UART1_CONTROL_REG0_RXRES_DEFVAL                        0x00000128
 #define UART1_CONTROL_REG0_RXRES_SHIFT                         0
 #define UART1_CONTROL_REG0_RXRES_MASK                          0x00000001U
@@ -30354,9 +30389,9 @@
 * Channel mode: Defines the mode of operation of the UART. 00: normal 01:
     * automatic echo 10: local loopback 11: remote loopback
 */
-#undef UART1_MODE_REG0_CHMODE_DEFVAL 
-#undef UART1_MODE_REG0_CHMODE_SHIFT 
-#undef UART1_MODE_REG0_CHMODE_MASK 
+#undef UART1_MODE_REG0_CHMODE_DEFVAL
+#undef UART1_MODE_REG0_CHMODE_SHIFT
+#undef UART1_MODE_REG0_CHMODE_MASK
 #define UART1_MODE_REG0_CHMODE_DEFVAL                          0x00000000
 #define UART1_MODE_REG0_CHMODE_SHIFT                           8
 #define UART1_MODE_REG0_CHMODE_MASK                            0x00000300U
@@ -30366,9 +30401,9 @@
     * e and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 st
     * op bits 11: reserved
 */
-#undef UART1_MODE_REG0_NBSTOP_DEFVAL 
-#undef UART1_MODE_REG0_NBSTOP_SHIFT 
-#undef UART1_MODE_REG0_NBSTOP_MASK 
+#undef UART1_MODE_REG0_NBSTOP_DEFVAL
+#undef UART1_MODE_REG0_NBSTOP_SHIFT
+#undef UART1_MODE_REG0_NBSTOP_MASK
 #define UART1_MODE_REG0_NBSTOP_DEFVAL                          0x00000000
 #define UART1_MODE_REG0_NBSTOP_SHIFT                           6
 #define UART1_MODE_REG0_NBSTOP_MASK                            0x000000C0U
@@ -30379,9 +30414,9 @@
     * : forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no pari
     * ty
 */
-#undef UART1_MODE_REG0_PAR_DEFVAL 
-#undef UART1_MODE_REG0_PAR_SHIFT 
-#undef UART1_MODE_REG0_PAR_MASK 
+#undef UART1_MODE_REG0_PAR_DEFVAL
+#undef UART1_MODE_REG0_PAR_SHIFT
+#undef UART1_MODE_REG0_PAR_MASK
 #define UART1_MODE_REG0_PAR_DEFVAL                             0x00000000
 #define UART1_MODE_REG0_PAR_SHIFT                              3
 #define UART1_MODE_REG0_PAR_MASK                               0x00000038U
@@ -30390,9 +30425,9 @@
 * Character length select: Defines the number of bits in each character. 1
     * 1: 6 bits 10: 7 bits 0x: 8 bits
 */
-#undef UART1_MODE_REG0_CHRL_DEFVAL 
-#undef UART1_MODE_REG0_CHRL_SHIFT 
-#undef UART1_MODE_REG0_CHRL_MASK 
+#undef UART1_MODE_REG0_CHRL_DEFVAL
+#undef UART1_MODE_REG0_CHRL_SHIFT
+#undef UART1_MODE_REG0_CHRL_MASK
 #define UART1_MODE_REG0_CHRL_DEFVAL                            0x00000000
 #define UART1_MODE_REG0_CHRL_SHIFT                             1
 #define UART1_MODE_REG0_CHRL_MASK                              0x00000006U
@@ -30402,9 +30437,9 @@
     * lied to the baud rate generator input clock. 0: clock source is uart_ref
     * _clk 1: clock source is uart_ref_clk/8
 */
-#undef UART1_MODE_REG0_CLKS_DEFVAL 
-#undef UART1_MODE_REG0_CLKS_SHIFT 
-#undef UART1_MODE_REG0_CLKS_MASK 
+#undef UART1_MODE_REG0_CLKS_DEFVAL
+#undef UART1_MODE_REG0_CLKS_SHIFT
+#undef UART1_MODE_REG0_CLKS_MASK
 #define UART1_MODE_REG0_CLKS_DEFVAL                            0x00000000
 #define UART1_MODE_REG0_CLKS_SHIFT                             0
 #define UART1_MODE_REG0_CLKS_MASK                              0x00000001U
@@ -30412,9 +30447,9 @@
 /*
 * Block level reset
 */
-#undef CRL_APB_RST_LPD_IOU2_GPIO_RESET_DEFVAL 
-#undef CRL_APB_RST_LPD_IOU2_GPIO_RESET_SHIFT 
-#undef CRL_APB_RST_LPD_IOU2_GPIO_RESET_MASK 
+#undef CRL_APB_RST_LPD_IOU2_GPIO_RESET_DEFVAL
+#undef CRL_APB_RST_LPD_IOU2_GPIO_RESET_SHIFT
+#undef CRL_APB_RST_LPD_IOU2_GPIO_RESET_MASK
 #define CRL_APB_RST_LPD_IOU2_GPIO_RESET_DEFVAL                 0x0017FFFF
 #define CRL_APB_RST_LPD_IOU2_GPIO_RESET_SHIFT                  18
 #define CRL_APB_RST_LPD_IOU2_GPIO_RESET_MASK                   0x00040000U
@@ -30422,19 +30457,19 @@
 /*
 * TrustZone Classification for ADMA
 */
-#undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL 
-#undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT 
-#undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK 
-#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL                    
+#undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL
+#undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT
+#undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK
+#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL
 #define LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT                     0
 #define LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK                      0x000000FFU
 
 /*
 * CSU regsiter
 */
-#undef CSU_TAMPER_STATUS_TAMPER_0_DEFVAL 
-#undef CSU_TAMPER_STATUS_TAMPER_0_SHIFT 
-#undef CSU_TAMPER_STATUS_TAMPER_0_MASK 
+#undef CSU_TAMPER_STATUS_TAMPER_0_DEFVAL
+#undef CSU_TAMPER_STATUS_TAMPER_0_SHIFT
+#undef CSU_TAMPER_STATUS_TAMPER_0_MASK
 #define CSU_TAMPER_STATUS_TAMPER_0_DEFVAL                      0x00000000
 #define CSU_TAMPER_STATUS_TAMPER_0_SHIFT                       0
 #define CSU_TAMPER_STATUS_TAMPER_0_MASK                        0x00000001U
@@ -30442,9 +30477,9 @@
 /*
 * External MIO
 */
-#undef CSU_TAMPER_STATUS_TAMPER_1_DEFVAL 
-#undef CSU_TAMPER_STATUS_TAMPER_1_SHIFT 
-#undef CSU_TAMPER_STATUS_TAMPER_1_MASK 
+#undef CSU_TAMPER_STATUS_TAMPER_1_DEFVAL
+#undef CSU_TAMPER_STATUS_TAMPER_1_SHIFT
+#undef CSU_TAMPER_STATUS_TAMPER_1_MASK
 #define CSU_TAMPER_STATUS_TAMPER_1_DEFVAL                      0x00000000
 #define CSU_TAMPER_STATUS_TAMPER_1_SHIFT                       1
 #define CSU_TAMPER_STATUS_TAMPER_1_MASK                        0x00000002U
@@ -30452,9 +30487,9 @@
 /*
 * JTAG toggle detect
 */
-#undef CSU_TAMPER_STATUS_TAMPER_2_DEFVAL 
-#undef CSU_TAMPER_STATUS_TAMPER_2_SHIFT 
-#undef CSU_TAMPER_STATUS_TAMPER_2_MASK 
+#undef CSU_TAMPER_STATUS_TAMPER_2_DEFVAL
+#undef CSU_TAMPER_STATUS_TAMPER_2_SHIFT
+#undef CSU_TAMPER_STATUS_TAMPER_2_MASK
 #define CSU_TAMPER_STATUS_TAMPER_2_DEFVAL                      0x00000000
 #define CSU_TAMPER_STATUS_TAMPER_2_SHIFT                       2
 #define CSU_TAMPER_STATUS_TAMPER_2_MASK                        0x00000004U
@@ -30462,9 +30497,9 @@
 /*
 * PL SEU error
 */
-#undef CSU_TAMPER_STATUS_TAMPER_3_DEFVAL 
-#undef CSU_TAMPER_STATUS_TAMPER_3_SHIFT 
-#undef CSU_TAMPER_STATUS_TAMPER_3_MASK 
+#undef CSU_TAMPER_STATUS_TAMPER_3_DEFVAL
+#undef CSU_TAMPER_STATUS_TAMPER_3_SHIFT
+#undef CSU_TAMPER_STATUS_TAMPER_3_MASK
 #define CSU_TAMPER_STATUS_TAMPER_3_DEFVAL                      0x00000000
 #define CSU_TAMPER_STATUS_TAMPER_3_SHIFT                       3
 #define CSU_TAMPER_STATUS_TAMPER_3_MASK                        0x00000008U
@@ -30472,9 +30507,9 @@
 /*
 * AMS over temperature alarm for LPD
 */
-#undef CSU_TAMPER_STATUS_TAMPER_4_DEFVAL 
-#undef CSU_TAMPER_STATUS_TAMPER_4_SHIFT 
-#undef CSU_TAMPER_STATUS_TAMPER_4_MASK 
+#undef CSU_TAMPER_STATUS_TAMPER_4_DEFVAL
+#undef CSU_TAMPER_STATUS_TAMPER_4_SHIFT
+#undef CSU_TAMPER_STATUS_TAMPER_4_MASK
 #define CSU_TAMPER_STATUS_TAMPER_4_DEFVAL                      0x00000000
 #define CSU_TAMPER_STATUS_TAMPER_4_SHIFT                       4
 #define CSU_TAMPER_STATUS_TAMPER_4_MASK                        0x00000010U
@@ -30482,9 +30517,9 @@
 /*
 * AMS over temperature alarm for APU
 */
-#undef CSU_TAMPER_STATUS_TAMPER_5_DEFVAL 
-#undef CSU_TAMPER_STATUS_TAMPER_5_SHIFT 
-#undef CSU_TAMPER_STATUS_TAMPER_5_MASK 
+#undef CSU_TAMPER_STATUS_TAMPER_5_DEFVAL
+#undef CSU_TAMPER_STATUS_TAMPER_5_SHIFT
+#undef CSU_TAMPER_STATUS_TAMPER_5_MASK
 #define CSU_TAMPER_STATUS_TAMPER_5_DEFVAL                      0x00000000
 #define CSU_TAMPER_STATUS_TAMPER_5_SHIFT                       5
 #define CSU_TAMPER_STATUS_TAMPER_5_MASK                        0x00000020U
@@ -30492,9 +30527,9 @@
 /*
 * AMS voltage alarm for VCCPINT_FPD
 */
-#undef CSU_TAMPER_STATUS_TAMPER_6_DEFVAL 
-#undef CSU_TAMPER_STATUS_TAMPER_6_SHIFT 
-#undef CSU_TAMPER_STATUS_TAMPER_6_MASK 
+#undef CSU_TAMPER_STATUS_TAMPER_6_DEFVAL
+#undef CSU_TAMPER_STATUS_TAMPER_6_SHIFT
+#undef CSU_TAMPER_STATUS_TAMPER_6_MASK
 #define CSU_TAMPER_STATUS_TAMPER_6_DEFVAL                      0x00000000
 #define CSU_TAMPER_STATUS_TAMPER_6_SHIFT                       6
 #define CSU_TAMPER_STATUS_TAMPER_6_MASK                        0x00000040U
@@ -30502,9 +30537,9 @@
 /*
 * AMS voltage alarm for VCCPINT_LPD
 */
-#undef CSU_TAMPER_STATUS_TAMPER_7_DEFVAL 
-#undef CSU_TAMPER_STATUS_TAMPER_7_SHIFT 
-#undef CSU_TAMPER_STATUS_TAMPER_7_MASK 
+#undef CSU_TAMPER_STATUS_TAMPER_7_DEFVAL
+#undef CSU_TAMPER_STATUS_TAMPER_7_SHIFT
+#undef CSU_TAMPER_STATUS_TAMPER_7_MASK
 #define CSU_TAMPER_STATUS_TAMPER_7_DEFVAL                      0x00000000
 #define CSU_TAMPER_STATUS_TAMPER_7_SHIFT                       7
 #define CSU_TAMPER_STATUS_TAMPER_7_MASK                        0x00000080U
@@ -30512,9 +30547,9 @@
 /*
 * AMS voltage alarm for VCCPAUX
 */
-#undef CSU_TAMPER_STATUS_TAMPER_8_DEFVAL 
-#undef CSU_TAMPER_STATUS_TAMPER_8_SHIFT 
-#undef CSU_TAMPER_STATUS_TAMPER_8_MASK 
+#undef CSU_TAMPER_STATUS_TAMPER_8_DEFVAL
+#undef CSU_TAMPER_STATUS_TAMPER_8_SHIFT
+#undef CSU_TAMPER_STATUS_TAMPER_8_MASK
 #define CSU_TAMPER_STATUS_TAMPER_8_DEFVAL                      0x00000000
 #define CSU_TAMPER_STATUS_TAMPER_8_SHIFT                       8
 #define CSU_TAMPER_STATUS_TAMPER_8_MASK                        0x00000100U
@@ -30522,9 +30557,9 @@
 /*
 * AMS voltage alarm for DDRPHY
 */
-#undef CSU_TAMPER_STATUS_TAMPER_9_DEFVAL 
-#undef CSU_TAMPER_STATUS_TAMPER_9_SHIFT 
-#undef CSU_TAMPER_STATUS_TAMPER_9_MASK 
+#undef CSU_TAMPER_STATUS_TAMPER_9_DEFVAL
+#undef CSU_TAMPER_STATUS_TAMPER_9_SHIFT
+#undef CSU_TAMPER_STATUS_TAMPER_9_MASK
 #define CSU_TAMPER_STATUS_TAMPER_9_DEFVAL                      0x00000000
 #define CSU_TAMPER_STATUS_TAMPER_9_SHIFT                       9
 #define CSU_TAMPER_STATUS_TAMPER_9_MASK                        0x00000200U
@@ -30532,9 +30567,9 @@
 /*
 * AMS voltage alarm for PSIO bank 0/1/2
 */
-#undef CSU_TAMPER_STATUS_TAMPER_10_DEFVAL 
-#undef CSU_TAMPER_STATUS_TAMPER_10_SHIFT 
-#undef CSU_TAMPER_STATUS_TAMPER_10_MASK 
+#undef CSU_TAMPER_STATUS_TAMPER_10_DEFVAL
+#undef CSU_TAMPER_STATUS_TAMPER_10_SHIFT
+#undef CSU_TAMPER_STATUS_TAMPER_10_MASK
 #define CSU_TAMPER_STATUS_TAMPER_10_DEFVAL                     0x00000000
 #define CSU_TAMPER_STATUS_TAMPER_10_SHIFT                      10
 #define CSU_TAMPER_STATUS_TAMPER_10_MASK                       0x00000400U
@@ -30542,9 +30577,9 @@
 /*
 * AMS voltage alarm for PSIO bank 3 (dedicated pins)
 */
-#undef CSU_TAMPER_STATUS_TAMPER_11_DEFVAL 
-#undef CSU_TAMPER_STATUS_TAMPER_11_SHIFT 
-#undef CSU_TAMPER_STATUS_TAMPER_11_MASK 
+#undef CSU_TAMPER_STATUS_TAMPER_11_DEFVAL
+#undef CSU_TAMPER_STATUS_TAMPER_11_SHIFT
+#undef CSU_TAMPER_STATUS_TAMPER_11_MASK
 #define CSU_TAMPER_STATUS_TAMPER_11_DEFVAL                     0x00000000
 #define CSU_TAMPER_STATUS_TAMPER_11_SHIFT                      11
 #define CSU_TAMPER_STATUS_TAMPER_11_MASK                       0x00000800U
@@ -30552,9 +30587,9 @@
 /*
 * AMS voltaage alarm for GT
 */
-#undef CSU_TAMPER_STATUS_TAMPER_12_DEFVAL 
-#undef CSU_TAMPER_STATUS_TAMPER_12_SHIFT 
-#undef CSU_TAMPER_STATUS_TAMPER_12_MASK 
+#undef CSU_TAMPER_STATUS_TAMPER_12_DEFVAL
+#undef CSU_TAMPER_STATUS_TAMPER_12_SHIFT
+#undef CSU_TAMPER_STATUS_TAMPER_12_MASK
 #define CSU_TAMPER_STATUS_TAMPER_12_DEFVAL                     0x00000000
 #define CSU_TAMPER_STATUS_TAMPER_12_SHIFT                      12
 #define CSU_TAMPER_STATUS_TAMPER_12_MASK                       0x00001000U
@@ -30562,9 +30597,9 @@
 /*
 * Set ACE outgoing AWQOS value
 */
-#undef APU_ACE_CTRL_AWQOS_DEFVAL 
-#undef APU_ACE_CTRL_AWQOS_SHIFT 
-#undef APU_ACE_CTRL_AWQOS_MASK 
+#undef APU_ACE_CTRL_AWQOS_DEFVAL
+#undef APU_ACE_CTRL_AWQOS_SHIFT
+#undef APU_ACE_CTRL_AWQOS_MASK
 #define APU_ACE_CTRL_AWQOS_DEFVAL                              0x000F000F
 #define APU_ACE_CTRL_AWQOS_SHIFT                               16
 #define APU_ACE_CTRL_AWQOS_MASK                                0x000F0000U
@@ -30572,9 +30607,9 @@
 /*
 * Set ACE outgoing ARQOS value
 */
-#undef APU_ACE_CTRL_ARQOS_DEFVAL 
-#undef APU_ACE_CTRL_ARQOS_SHIFT 
-#undef APU_ACE_CTRL_ARQOS_MASK 
+#undef APU_ACE_CTRL_ARQOS_DEFVAL
+#undef APU_ACE_CTRL_ARQOS_SHIFT
+#undef APU_ACE_CTRL_ARQOS_MASK
 #define APU_ACE_CTRL_ARQOS_DEFVAL                              0x000F000F
 #define APU_ACE_CTRL_ARQOS_SHIFT                               0
 #define APU_ACE_CTRL_ARQOS_MASK                                0x0000000FU
@@ -30587,9 +30622,9 @@
     * e it is being configured. If RTC is not used in the design, FSBL will di
     * sable it by writing a 0 to this bit.
 */
-#undef RTC_CONTROL_BATTERY_DISABLE_DEFVAL 
-#undef RTC_CONTROL_BATTERY_DISABLE_SHIFT 
-#undef RTC_CONTROL_BATTERY_DISABLE_MASK 
+#undef RTC_CONTROL_BATTERY_DISABLE_DEFVAL
+#undef RTC_CONTROL_BATTERY_DISABLE_SHIFT
+#undef RTC_CONTROL_BATTERY_DISABLE_MASK
 #define RTC_CONTROL_BATTERY_DISABLE_DEFVAL                     0x01000000
 #define RTC_CONTROL_BATTERY_DISABLE_SHIFT                      31
 #define RTC_CONTROL_BATTERY_DISABLE_MASK                       0x80000000U
@@ -30598,10 +30633,10 @@
 * Frequency in number of ticks per second. Valid range from 10 MHz to 100
     * MHz.
 */
-#undef IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_DEFVAL 
-#undef IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_SHIFT 
-#undef IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_MASK 
-#define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_DEFVAL      
+#undef IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_DEFVAL
+#undef IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_SHIFT
+#undef IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_MASK
+#define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_DEFVAL
 #define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_SHIFT       0
 #define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_MASK        0xFFFFFFFFU
 
@@ -30609,43 +30644,43 @@
 * Enable 0: The counter is disabled and not incrementing. 1: The counter i
     * s enabled and is incrementing.
 */
-#undef IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_DEFVAL 
-#undef IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_SHIFT 
-#undef IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_MASK 
+#undef IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_DEFVAL
+#undef IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_SHIFT
+#undef IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_MASK
 #define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_DEFVAL          0x00000000
 #define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_SHIFT           0
 #define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_MASK            0x00000001U
-#undef FPD_SLCR_SECURE_SLCR_DPDMA_OFFSET 
+#undef FPD_SLCR_SECURE_SLCR_DPDMA_OFFSET
 #define FPD_SLCR_SECURE_SLCR_DPDMA_OFFSET                                          0XFD690040
-#undef FPD_SLCR_SECURE_SLCR_PCIE_OFFSET 
+#undef FPD_SLCR_SECURE_SLCR_PCIE_OFFSET
 #define FPD_SLCR_SECURE_SLCR_PCIE_OFFSET                                           0XFD690030
-#undef LPD_SLCR_SECURE_SLCR_USB_OFFSET 
+#undef LPD_SLCR_SECURE_SLCR_USB_OFFSET
 #define LPD_SLCR_SECURE_SLCR_USB_OFFSET                                            0XFF4B0034
-#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET 
+#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET
 #define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET                                      0XFF240004
-#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET 
+#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET
 #define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET                                      0XFF240000
-#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET 
+#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET
 #define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET                                      0XFF240004
-#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET 
+#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET
 #define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET                                      0XFF240000
-#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET 
+#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET
 #define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET                                      0XFF240000
-#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET 
+#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET
 #define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET                                      0XFF240004
-#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET 
+#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET
 #define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET                                      0XFF240000
-#undef LPD_SLCR_SECURE_SLCR_ADMA_OFFSET 
+#undef LPD_SLCR_SECURE_SLCR_ADMA_OFFSET
 #define LPD_SLCR_SECURE_SLCR_ADMA_OFFSET                                           0XFF4B0024
-#undef FPD_SLCR_SECURE_SLCR_GDMA_OFFSET 
+#undef FPD_SLCR_SECURE_SLCR_GDMA_OFFSET
 #define FPD_SLCR_SECURE_SLCR_GDMA_OFFSET                                           0XFD690050
 
 /*
 * TrustZone classification for DisplayPort DMA
 */
-#undef FPD_SLCR_SECURE_SLCR_DPDMA_TZ_DEFVAL 
-#undef FPD_SLCR_SECURE_SLCR_DPDMA_TZ_SHIFT 
-#undef FPD_SLCR_SECURE_SLCR_DPDMA_TZ_MASK 
+#undef FPD_SLCR_SECURE_SLCR_DPDMA_TZ_DEFVAL
+#undef FPD_SLCR_SECURE_SLCR_DPDMA_TZ_SHIFT
+#undef FPD_SLCR_SECURE_SLCR_DPDMA_TZ_MASK
 #define FPD_SLCR_SECURE_SLCR_DPDMA_TZ_DEFVAL                   0x00000001
 #define FPD_SLCR_SECURE_SLCR_DPDMA_TZ_SHIFT                    0
 #define FPD_SLCR_SECURE_SLCR_DPDMA_TZ_MASK                     0x00000001U
@@ -30653,9 +30688,9 @@
 /*
 * TrustZone classification for DMA Channel 0
 */
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0_DEFVAL 
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0_SHIFT 
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0_MASK 
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0_DEFVAL
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0_SHIFT
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0_MASK
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0_DEFVAL              0x01FFFFFF
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0_SHIFT               21
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0_MASK                0x00200000U
@@ -30663,9 +30698,9 @@
 /*
 * TrustZone classification for DMA Channel 1
 */
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1_DEFVAL 
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1_SHIFT 
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1_MASK 
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1_DEFVAL
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1_SHIFT
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1_MASK
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1_DEFVAL              0x01FFFFFF
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1_SHIFT               22
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1_MASK                0x00400000U
@@ -30673,9 +30708,9 @@
 /*
 * TrustZone classification for DMA Channel 2
 */
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2_DEFVAL 
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2_SHIFT 
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2_MASK 
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2_DEFVAL
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2_SHIFT
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2_MASK
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2_DEFVAL              0x01FFFFFF
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2_SHIFT               23
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2_MASK                0x00800000U
@@ -30683,9 +30718,9 @@
 /*
 * TrustZone classification for DMA Channel 3
 */
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3_DEFVAL 
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3_SHIFT 
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3_MASK 
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3_DEFVAL
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3_SHIFT
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3_MASK
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3_DEFVAL              0x01FFFFFF
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3_SHIFT               24
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3_MASK                0x01000000U
@@ -30693,9 +30728,9 @@
 /*
 * TrustZone classification for Ingress Address Translation 0
 */
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0_DEFVAL 
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0_SHIFT 
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0_MASK 
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0_DEFVAL
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0_SHIFT
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0_MASK
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0_DEFVAL          0x01FFFFFF
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0_SHIFT           13
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0_MASK            0x00002000U
@@ -30703,9 +30738,9 @@
 /*
 * TrustZone classification for Ingress Address Translation 1
 */
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1_DEFVAL 
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1_SHIFT 
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1_MASK 
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1_DEFVAL
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1_SHIFT
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1_MASK
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1_DEFVAL          0x01FFFFFF
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1_SHIFT           14
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1_MASK            0x00004000U
@@ -30713,9 +30748,9 @@
 /*
 * TrustZone classification for Ingress Address Translation 2
 */
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2_DEFVAL 
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2_SHIFT 
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2_MASK 
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2_DEFVAL
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2_SHIFT
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2_MASK
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2_DEFVAL          0x01FFFFFF
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2_SHIFT           15
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2_MASK            0x00008000U
@@ -30723,9 +30758,9 @@
 /*
 * TrustZone classification for Ingress Address Translation 3
 */
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3_DEFVAL 
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3_SHIFT 
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3_MASK 
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3_DEFVAL
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3_SHIFT
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3_MASK
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3_DEFVAL          0x01FFFFFF
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3_SHIFT           16
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3_MASK            0x00010000U
@@ -30733,9 +30768,9 @@
 /*
 * TrustZone classification for Ingress Address Translation 4
 */
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4_DEFVAL 
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4_SHIFT 
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4_MASK 
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4_DEFVAL
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4_SHIFT
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4_MASK
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4_DEFVAL          0x01FFFFFF
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4_SHIFT           17
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4_MASK            0x00020000U
@@ -30743,9 +30778,9 @@
 /*
 * TrustZone classification for Ingress Address Translation 5
 */
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5_DEFVAL 
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5_SHIFT 
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5_MASK 
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5_DEFVAL
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5_SHIFT
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5_MASK
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5_DEFVAL          0x01FFFFFF
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5_SHIFT           18
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5_MASK            0x00040000U
@@ -30753,9 +30788,9 @@
 /*
 * TrustZone classification for Ingress Address Translation 6
 */
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6_DEFVAL 
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6_SHIFT 
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6_MASK 
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6_DEFVAL
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6_SHIFT
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6_MASK
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6_DEFVAL          0x01FFFFFF
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6_SHIFT           19
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6_MASK            0x00080000U
@@ -30763,9 +30798,9 @@
 /*
 * TrustZone classification for Ingress Address Translation 7
 */
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7_DEFVAL 
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7_SHIFT 
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7_MASK 
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7_DEFVAL
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7_SHIFT
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7_MASK
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7_DEFVAL          0x01FFFFFF
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7_SHIFT           20
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7_MASK            0x00100000U
@@ -30773,9 +30808,9 @@
 /*
 * TrustZone classification for Egress Address Translation 0
 */
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0_DEFVAL 
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0_SHIFT 
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0_MASK 
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0_DEFVAL
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0_SHIFT
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0_MASK
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0_DEFVAL           0x01FFFFFF
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0_SHIFT            5
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0_MASK             0x00000020U
@@ -30783,9 +30818,9 @@
 /*
 * TrustZone classification for Egress Address Translation 1
 */
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1_DEFVAL 
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1_SHIFT 
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1_MASK 
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1_DEFVAL
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1_SHIFT
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1_MASK
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1_DEFVAL           0x01FFFFFF
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1_SHIFT            6
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1_MASK             0x00000040U
@@ -30793,9 +30828,9 @@
 /*
 * TrustZone classification for Egress Address Translation 2
 */
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2_DEFVAL 
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2_SHIFT 
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2_MASK 
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2_DEFVAL
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2_SHIFT
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2_MASK
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2_DEFVAL           0x01FFFFFF
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2_SHIFT            7
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2_MASK             0x00000080U
@@ -30803,9 +30838,9 @@
 /*
 * TrustZone classification for Egress Address Translation 3
 */
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3_DEFVAL 
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3_SHIFT 
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3_MASK 
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3_DEFVAL
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3_SHIFT
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3_MASK
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3_DEFVAL           0x01FFFFFF
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3_SHIFT            8
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3_MASK             0x00000100U
@@ -30813,9 +30848,9 @@
 /*
 * TrustZone classification for Egress Address Translation 4
 */
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4_DEFVAL 
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4_SHIFT 
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4_MASK 
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4_DEFVAL
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4_SHIFT
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4_MASK
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4_DEFVAL           0x01FFFFFF
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4_SHIFT            9
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4_MASK             0x00000200U
@@ -30823,9 +30858,9 @@
 /*
 * TrustZone classification for Egress Address Translation 5
 */
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5_DEFVAL 
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5_SHIFT 
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5_MASK 
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5_DEFVAL
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5_SHIFT
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5_MASK
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5_DEFVAL           0x01FFFFFF
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5_SHIFT            10
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5_MASK             0x00000400U
@@ -30833,9 +30868,9 @@
 /*
 * TrustZone classification for Egress Address Translation 6
 */
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6_DEFVAL 
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6_SHIFT 
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6_MASK 
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6_DEFVAL
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6_SHIFT
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6_MASK
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6_DEFVAL           0x01FFFFFF
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6_SHIFT            11
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6_MASK             0x00000800U
@@ -30843,9 +30878,9 @@
 /*
 * TrustZone classification for Egress Address Translation 7
 */
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7_DEFVAL 
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7_SHIFT 
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7_MASK 
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7_DEFVAL
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7_SHIFT
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7_MASK
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7_DEFVAL           0x01FFFFFF
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7_SHIFT            12
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7_MASK             0x00001000U
@@ -30853,9 +30888,9 @@
 /*
 * TrustZone classification for DMA Registers
 */
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS_DEFVAL 
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS_SHIFT 
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS_MASK 
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS_DEFVAL
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS_SHIFT
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS_MASK
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS_DEFVAL           0x01FFFFFF
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS_SHIFT            4
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS_MASK             0x00000010U
@@ -30863,9 +30898,9 @@
 /*
 * TrustZone classification for MSIx Table
 */
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE_DEFVAL 
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE_SHIFT 
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE_MASK 
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE_DEFVAL
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE_SHIFT
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE_MASK
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE_DEFVAL         0x01FFFFFF
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE_SHIFT          2
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE_MASK           0x00000004U
@@ -30873,9 +30908,9 @@
 /*
 * TrustZone classification for MSIx PBA
 */
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA_DEFVAL 
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA_SHIFT 
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA_MASK 
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA_DEFVAL
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA_SHIFT
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA_MASK
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA_DEFVAL           0x01FFFFFF
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA_SHIFT            3
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA_MASK             0x00000008U
@@ -30883,9 +30918,9 @@
 /*
 * TrustZone classification for ECAM
 */
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM_DEFVAL 
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM_SHIFT 
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM_MASK 
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM_DEFVAL
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM_SHIFT
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM_MASK
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM_DEFVAL               0x01FFFFFF
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM_SHIFT                1
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM_MASK                 0x00000002U
@@ -30893,9 +30928,9 @@
 /*
 * TrustZone classification for Bridge Common Registers
 */
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS_DEFVAL 
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS_SHIFT 
-#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS_MASK 
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS_DEFVAL
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS_SHIFT
+#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS_MASK
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS_DEFVAL        0x01FFFFFF
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS_SHIFT         0
 #define FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS_MASK          0x00000001U
@@ -30903,9 +30938,9 @@
 /*
 * TrustZone Classification for USB3_0
 */
-#undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0_DEFVAL 
-#undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0_SHIFT 
-#undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0_MASK 
+#undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0_DEFVAL
+#undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0_SHIFT
+#undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0_MASK
 #define LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0_DEFVAL              0x00000003
 #define LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0_SHIFT               0
 #define LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0_MASK                0x00000001U
@@ -30913,9 +30948,9 @@
 /*
 * TrustZone Classification for USB3_1
 */
-#undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1_DEFVAL 
-#undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1_SHIFT 
-#undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1_MASK 
+#undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1_DEFVAL
+#undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1_SHIFT
+#undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1_MASK
 #define LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1_DEFVAL              0x00000003
 #define LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1_SHIFT               1
 #define LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1_MASK                0x00000002U
@@ -30925,9 +30960,9 @@
     * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
     * ccess [2] = '1'' : Instruction access
 */
-#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT_DEFVAL 
-#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT_SHIFT 
-#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT_MASK 
+#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT_DEFVAL
+#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT_SHIFT
+#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT_MASK
 #define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT_DEFVAL   0x00000000
 #define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT_SHIFT    16
 #define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT_MASK     0x00070000U
@@ -30937,9 +30972,9 @@
     * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
     * ccess [2] = '1'' : Instruction access
 */
-#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT_DEFVAL 
-#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT_SHIFT 
-#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT_MASK 
+#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT_DEFVAL
+#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT_SHIFT
+#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT_MASK
 #define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT_DEFVAL   0x00000000
 #define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT_SHIFT    19
 #define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT_MASK     0x00380000U
@@ -30949,9 +30984,9 @@
     * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
     * ccess [2] = '1'' : Instruction access
 */
-#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT_DEFVAL 
-#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT_SHIFT 
-#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT_MASK 
+#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT_DEFVAL
+#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT_SHIFT
+#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT_MASK
 #define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT_DEFVAL   0x00000000
 #define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT_SHIFT    16
 #define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT_MASK     0x00070000U
@@ -30961,9 +30996,9 @@
     * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
     * ccess [2] = '1'' : Instruction access
 */
-#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT_DEFVAL 
-#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT_SHIFT 
-#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT_MASK 
+#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT_DEFVAL
+#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT_SHIFT
+#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT_MASK
 #define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT_DEFVAL   0x00000000
 #define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT_SHIFT    19
 #define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT_MASK     0x00380000U
@@ -30973,9 +31008,9 @@
     * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
     * ccess [2] = '1'' : Instruction access
 */
-#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT_DEFVAL 
-#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT_SHIFT 
-#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT_MASK 
+#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT_DEFVAL
+#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT_SHIFT
+#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT_MASK
 #define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT_DEFVAL  0x00000000
 #define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT_SHIFT   0
 #define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT_MASK    0x00000007U
@@ -30985,9 +31020,9 @@
     * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
     * ccess [2] = '1'' : Instruction access
 */
-#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT_DEFVAL 
-#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT_SHIFT 
-#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT_MASK 
+#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT_DEFVAL
+#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT_SHIFT
+#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT_MASK
 #define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT_DEFVAL  0x00000000
 #define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT_SHIFT   3
 #define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT_MASK    0x00000038U
@@ -30997,9 +31032,9 @@
     * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
     * ccess [2] = '1'' : Instruction access
 */
-#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT_DEFVAL 
-#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT_SHIFT 
-#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT_MASK 
+#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT_DEFVAL
+#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT_SHIFT
+#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT_MASK
 #define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT_DEFVAL  0x00000000
 #define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT_SHIFT   6
 #define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT_MASK    0x000001C0U
@@ -31009,9 +31044,9 @@
     * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
     * ccess [2] = '1'' : Instruction access
 */
-#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT_DEFVAL 
-#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT_SHIFT 
-#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT_MASK 
+#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT_DEFVAL
+#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT_SHIFT
+#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT_MASK
 #define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT_DEFVAL  0x00000000
 #define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT_SHIFT   9
 #define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT_MASK    0x00000E00U
@@ -31021,9 +31056,9 @@
     * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
     * ccess [2] = '1'' : Instruction access
 */
-#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT_DEFVAL 
-#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT_SHIFT 
-#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT_MASK 
+#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT_DEFVAL
+#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT_SHIFT
+#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT_MASK
 #define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT_DEFVAL  0x00000000
 #define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT_SHIFT   0
 #define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT_MASK    0x00000007U
@@ -31033,9 +31068,9 @@
     * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
     * ccess [2] = '1'' : Instruction access
 */
-#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT_DEFVAL 
-#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT_SHIFT 
-#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT_MASK 
+#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT_DEFVAL
+#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT_SHIFT
+#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT_MASK
 #define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT_DEFVAL  0x00000000
 #define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT_SHIFT   3
 #define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT_MASK    0x00000038U
@@ -31045,9 +31080,9 @@
     * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
     * ccess [2] = '1'' : Instruction access
 */
-#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT_DEFVAL 
-#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT_SHIFT 
-#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT_MASK 
+#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT_DEFVAL
+#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT_SHIFT
+#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT_MASK
 #define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT_DEFVAL  0x00000000
 #define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT_SHIFT   6
 #define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT_MASK    0x000001C0U
@@ -31057,9 +31092,9 @@
     * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
     * ccess [2] = '1'' : Instruction access
 */
-#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT_DEFVAL 
-#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT_SHIFT 
-#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT_MASK 
+#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT_DEFVAL
+#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT_SHIFT
+#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT_MASK
 #define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT_DEFVAL  0x00000000
 #define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT_SHIFT   9
 #define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT_MASK    0x00000E00U
@@ -31069,9 +31104,9 @@
     * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
     * ccess [2] = '1'' : Instruction access
 */
-#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT_DEFVAL 
-#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT_SHIFT 
-#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT_MASK 
+#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT_DEFVAL
+#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT_SHIFT
+#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT_MASK
 #define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT_DEFVAL  0x00000000
 #define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT_SHIFT   25
 #define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT_MASK    0x0E000000U
@@ -31081,9 +31116,9 @@
     * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
     * ccess [2] = '1'' : Instruction access
 */
-#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT_DEFVAL 
-#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT_SHIFT 
-#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT_MASK 
+#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT_DEFVAL
+#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT_SHIFT
+#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT_MASK
 #define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT_DEFVAL  0x00000000
 #define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT_SHIFT   22
 #define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT_MASK    0x01C00000U
@@ -31093,9 +31128,9 @@
     * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a
     * ccess [2] = '1'' : Instruction access
 */
-#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT_DEFVAL 
-#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT_SHIFT 
-#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT_MASK 
+#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT_DEFVAL
+#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT_SHIFT
+#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT_MASK
 #define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT_DEFVAL  0x00000000
 #define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT_SHIFT   22
 #define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT_MASK    0x01C00000U
@@ -31103,249 +31138,249 @@
 /*
 * TrustZone Classification for ADMA
 */
-#undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL 
-#undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT 
-#undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK 
-#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL                    
+#undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL
+#undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT
+#undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK
+#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL
 #define LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT                     0
 #define LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK                      0x000000FFU
 
 /*
 * TrustZone Classification for GDMA
 */
-#undef FPD_SLCR_SECURE_SLCR_GDMA_TZ_DEFVAL 
-#undef FPD_SLCR_SECURE_SLCR_GDMA_TZ_SHIFT 
-#undef FPD_SLCR_SECURE_SLCR_GDMA_TZ_MASK 
-#define FPD_SLCR_SECURE_SLCR_GDMA_TZ_DEFVAL                    
+#undef FPD_SLCR_SECURE_SLCR_GDMA_TZ_DEFVAL
+#undef FPD_SLCR_SECURE_SLCR_GDMA_TZ_SHIFT
+#undef FPD_SLCR_SECURE_SLCR_GDMA_TZ_MASK
+#define FPD_SLCR_SECURE_SLCR_GDMA_TZ_DEFVAL
 #define FPD_SLCR_SECURE_SLCR_GDMA_TZ_SHIFT                     0
 #define FPD_SLCR_SECURE_SLCR_GDMA_TZ_MASK                      0x000000FFU
-#undef SERDES_PLL_REF_SEL0_OFFSET 
+#undef SERDES_PLL_REF_SEL0_OFFSET
 #define SERDES_PLL_REF_SEL0_OFFSET                                                 0XFD410000
-#undef SERDES_PLL_REF_SEL1_OFFSET 
+#undef SERDES_PLL_REF_SEL1_OFFSET
 #define SERDES_PLL_REF_SEL1_OFFSET                                                 0XFD410004
-#undef SERDES_PLL_REF_SEL2_OFFSET 
+#undef SERDES_PLL_REF_SEL2_OFFSET
 #define SERDES_PLL_REF_SEL2_OFFSET                                                 0XFD410008
-#undef SERDES_PLL_REF_SEL3_OFFSET 
+#undef SERDES_PLL_REF_SEL3_OFFSET
 #define SERDES_PLL_REF_SEL3_OFFSET                                                 0XFD41000C
-#undef SERDES_L0_L0_REF_CLK_SEL_OFFSET 
+#undef SERDES_L0_L0_REF_CLK_SEL_OFFSET
 #define SERDES_L0_L0_REF_CLK_SEL_OFFSET                                            0XFD402860
-#undef SERDES_L0_L1_REF_CLK_SEL_OFFSET 
+#undef SERDES_L0_L1_REF_CLK_SEL_OFFSET
 #define SERDES_L0_L1_REF_CLK_SEL_OFFSET                                            0XFD402864
-#undef SERDES_L0_L2_REF_CLK_SEL_OFFSET 
+#undef SERDES_L0_L2_REF_CLK_SEL_OFFSET
 #define SERDES_L0_L2_REF_CLK_SEL_OFFSET                                            0XFD402868
-#undef SERDES_L0_L3_REF_CLK_SEL_OFFSET 
+#undef SERDES_L0_L3_REF_CLK_SEL_OFFSET
 #define SERDES_L0_L3_REF_CLK_SEL_OFFSET                                            0XFD40286C
-#undef SERDES_L2_TM_PLL_DIG_37_OFFSET 
+#undef SERDES_L2_TM_PLL_DIG_37_OFFSET
 #define SERDES_L2_TM_PLL_DIG_37_OFFSET                                             0XFD40A094
-#undef SERDES_L2_PLL_SS_STEPS_0_LSB_OFFSET 
+#undef SERDES_L2_PLL_SS_STEPS_0_LSB_OFFSET
 #define SERDES_L2_PLL_SS_STEPS_0_LSB_OFFSET                                        0XFD40A368
-#undef SERDES_L2_PLL_SS_STEPS_1_MSB_OFFSET 
+#undef SERDES_L2_PLL_SS_STEPS_1_MSB_OFFSET
 #define SERDES_L2_PLL_SS_STEPS_1_MSB_OFFSET                                        0XFD40A36C
-#undef SERDES_L3_PLL_SS_STEPS_0_LSB_OFFSET 
+#undef SERDES_L3_PLL_SS_STEPS_0_LSB_OFFSET
 #define SERDES_L3_PLL_SS_STEPS_0_LSB_OFFSET                                        0XFD40E368
-#undef SERDES_L3_PLL_SS_STEPS_1_MSB_OFFSET 
+#undef SERDES_L3_PLL_SS_STEPS_1_MSB_OFFSET
 #define SERDES_L3_PLL_SS_STEPS_1_MSB_OFFSET                                        0XFD40E36C
-#undef SERDES_L0_PLL_SS_STEPS_0_LSB_OFFSET 
+#undef SERDES_L0_PLL_SS_STEPS_0_LSB_OFFSET
 #define SERDES_L0_PLL_SS_STEPS_0_LSB_OFFSET                                        0XFD402368
-#undef SERDES_L0_PLL_SS_STEPS_1_MSB_OFFSET 
+#undef SERDES_L0_PLL_SS_STEPS_1_MSB_OFFSET
 #define SERDES_L0_PLL_SS_STEPS_1_MSB_OFFSET                                        0XFD40236C
-#undef SERDES_L1_PLL_SS_STEPS_0_LSB_OFFSET 
+#undef SERDES_L1_PLL_SS_STEPS_0_LSB_OFFSET
 #define SERDES_L1_PLL_SS_STEPS_0_LSB_OFFSET                                        0XFD406368
-#undef SERDES_L1_PLL_SS_STEPS_1_MSB_OFFSET 
+#undef SERDES_L1_PLL_SS_STEPS_1_MSB_OFFSET
 #define SERDES_L1_PLL_SS_STEPS_1_MSB_OFFSET                                        0XFD40636C
-#undef SERDES_L0_PLL_SS_STEP_SIZE_0_LSB_OFFSET 
+#undef SERDES_L0_PLL_SS_STEP_SIZE_0_LSB_OFFSET
 #define SERDES_L0_PLL_SS_STEP_SIZE_0_LSB_OFFSET                                    0XFD402370
-#undef SERDES_L0_PLL_SS_STEP_SIZE_1_OFFSET 
+#undef SERDES_L0_PLL_SS_STEP_SIZE_1_OFFSET
 #define SERDES_L0_PLL_SS_STEP_SIZE_1_OFFSET                                        0XFD402374
-#undef SERDES_L0_PLL_SS_STEP_SIZE_2_OFFSET 
+#undef SERDES_L0_PLL_SS_STEP_SIZE_2_OFFSET
 #define SERDES_L0_PLL_SS_STEP_SIZE_2_OFFSET                                        0XFD402378
-#undef SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_OFFSET 
+#undef SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_OFFSET
 #define SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_OFFSET                                    0XFD40237C
-#undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_OFFSET 
+#undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_OFFSET
 #define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_OFFSET                                    0XFD406370
-#undef SERDES_L1_PLL_SS_STEP_SIZE_1_OFFSET 
+#undef SERDES_L1_PLL_SS_STEP_SIZE_1_OFFSET
 #define SERDES_L1_PLL_SS_STEP_SIZE_1_OFFSET                                        0XFD406374
-#undef SERDES_L1_PLL_SS_STEP_SIZE_2_OFFSET 
+#undef SERDES_L1_PLL_SS_STEP_SIZE_2_OFFSET
 #define SERDES_L1_PLL_SS_STEP_SIZE_2_OFFSET                                        0XFD406378
-#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_OFFSET 
+#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_OFFSET
 #define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_OFFSET                                    0XFD40637C
-#undef SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_OFFSET 
+#undef SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_OFFSET
 #define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_OFFSET                                    0XFD40A370
-#undef SERDES_L2_PLL_SS_STEP_SIZE_1_OFFSET 
+#undef SERDES_L2_PLL_SS_STEP_SIZE_1_OFFSET
 #define SERDES_L2_PLL_SS_STEP_SIZE_1_OFFSET                                        0XFD40A374
-#undef SERDES_L2_PLL_SS_STEP_SIZE_2_OFFSET 
+#undef SERDES_L2_PLL_SS_STEP_SIZE_2_OFFSET
 #define SERDES_L2_PLL_SS_STEP_SIZE_2_OFFSET                                        0XFD40A378
-#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_OFFSET 
+#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_OFFSET
 #define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_OFFSET                                    0XFD40A37C
-#undef SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_OFFSET 
+#undef SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_OFFSET
 #define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_OFFSET                                    0XFD40E370
-#undef SERDES_L3_PLL_SS_STEP_SIZE_1_OFFSET 
+#undef SERDES_L3_PLL_SS_STEP_SIZE_1_OFFSET
 #define SERDES_L3_PLL_SS_STEP_SIZE_1_OFFSET                                        0XFD40E374
-#undef SERDES_L3_PLL_SS_STEP_SIZE_2_OFFSET 
+#undef SERDES_L3_PLL_SS_STEP_SIZE_2_OFFSET
 #define SERDES_L3_PLL_SS_STEP_SIZE_2_OFFSET                                        0XFD40E378
-#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_OFFSET 
+#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_OFFSET
 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_OFFSET                                    0XFD40E37C
-#undef SERDES_L2_TM_DIG_6_OFFSET 
+#undef SERDES_L2_TM_DIG_6_OFFSET
 #define SERDES_L2_TM_DIG_6_OFFSET                                                  0XFD40906C
-#undef SERDES_L2_TX_DIG_TM_61_OFFSET 
+#undef SERDES_L2_TX_DIG_TM_61_OFFSET
 #define SERDES_L2_TX_DIG_TM_61_OFFSET                                              0XFD4080F4
-#undef SERDES_L3_PLL_FBDIV_FRAC_3_MSB_OFFSET 
+#undef SERDES_L3_PLL_FBDIV_FRAC_3_MSB_OFFSET
 #define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_OFFSET                                      0XFD40E360
-#undef SERDES_L3_TM_DIG_6_OFFSET 
+#undef SERDES_L3_TM_DIG_6_OFFSET
 #define SERDES_L3_TM_DIG_6_OFFSET                                                  0XFD40D06C
-#undef SERDES_L3_TX_DIG_TM_61_OFFSET 
+#undef SERDES_L3_TX_DIG_TM_61_OFFSET
 #define SERDES_L3_TX_DIG_TM_61_OFFSET                                              0XFD40C0F4
-#undef SERDES_L2_TM_AUX_0_OFFSET 
+#undef SERDES_L2_TM_AUX_0_OFFSET
 #define SERDES_L2_TM_AUX_0_OFFSET                                                  0XFD4090CC
-#undef SERDES_L0_TM_DIG_8_OFFSET 
+#undef SERDES_L0_TM_DIG_8_OFFSET
 #define SERDES_L0_TM_DIG_8_OFFSET                                                  0XFD401074
-#undef SERDES_L1_TM_DIG_8_OFFSET 
+#undef SERDES_L1_TM_DIG_8_OFFSET
 #define SERDES_L1_TM_DIG_8_OFFSET                                                  0XFD405074
-#undef SERDES_L2_TM_DIG_8_OFFSET 
+#undef SERDES_L2_TM_DIG_8_OFFSET
 #define SERDES_L2_TM_DIG_8_OFFSET                                                  0XFD409074
-#undef SERDES_L3_TM_DIG_8_OFFSET 
+#undef SERDES_L3_TM_DIG_8_OFFSET
 #define SERDES_L3_TM_DIG_8_OFFSET                                                  0XFD40D074
-#undef SERDES_L0_TM_ILL13_OFFSET 
+#undef SERDES_L0_TM_ILL13_OFFSET
 #define SERDES_L0_TM_ILL13_OFFSET                                                  0XFD401994
-#undef SERDES_L1_TM_ILL13_OFFSET 
+#undef SERDES_L1_TM_ILL13_OFFSET
 #define SERDES_L1_TM_ILL13_OFFSET                                                  0XFD405994
-#undef SERDES_L2_TM_MISC2_OFFSET 
+#undef SERDES_L2_TM_MISC2_OFFSET
 #define SERDES_L2_TM_MISC2_OFFSET                                                  0XFD40989C
-#undef SERDES_L2_TM_IQ_ILL1_OFFSET 
+#undef SERDES_L2_TM_IQ_ILL1_OFFSET
 #define SERDES_L2_TM_IQ_ILL1_OFFSET                                                0XFD4098F8
-#undef SERDES_L2_TM_IQ_ILL2_OFFSET 
+#undef SERDES_L2_TM_IQ_ILL2_OFFSET
 #define SERDES_L2_TM_IQ_ILL2_OFFSET                                                0XFD4098FC
-#undef SERDES_L2_TM_ILL12_OFFSET 
+#undef SERDES_L2_TM_ILL12_OFFSET
 #define SERDES_L2_TM_ILL12_OFFSET                                                  0XFD409990
-#undef SERDES_L2_TM_E_ILL1_OFFSET 
+#undef SERDES_L2_TM_E_ILL1_OFFSET
 #define SERDES_L2_TM_E_ILL1_OFFSET                                                 0XFD409924
-#undef SERDES_L2_TM_E_ILL2_OFFSET 
+#undef SERDES_L2_TM_E_ILL2_OFFSET
 #define SERDES_L2_TM_E_ILL2_OFFSET                                                 0XFD409928
-#undef SERDES_L2_TM_IQ_ILL3_OFFSET 
+#undef SERDES_L2_TM_IQ_ILL3_OFFSET
 #define SERDES_L2_TM_IQ_ILL3_OFFSET                                                0XFD409900
-#undef SERDES_L2_TM_E_ILL3_OFFSET 
+#undef SERDES_L2_TM_E_ILL3_OFFSET
 #define SERDES_L2_TM_E_ILL3_OFFSET                                                 0XFD40992C
-#undef SERDES_L2_TM_ILL8_OFFSET 
+#undef SERDES_L2_TM_ILL8_OFFSET
 #define SERDES_L2_TM_ILL8_OFFSET                                                   0XFD409980
-#undef SERDES_L2_TM_IQ_ILL8_OFFSET 
+#undef SERDES_L2_TM_IQ_ILL8_OFFSET
 #define SERDES_L2_TM_IQ_ILL8_OFFSET                                                0XFD409914
-#undef SERDES_L2_TM_IQ_ILL9_OFFSET 
+#undef SERDES_L2_TM_IQ_ILL9_OFFSET
 #define SERDES_L2_TM_IQ_ILL9_OFFSET                                                0XFD409918
-#undef SERDES_L2_TM_E_ILL8_OFFSET 
+#undef SERDES_L2_TM_E_ILL8_OFFSET
 #define SERDES_L2_TM_E_ILL8_OFFSET                                                 0XFD409940
-#undef SERDES_L2_TM_E_ILL9_OFFSET 
+#undef SERDES_L2_TM_E_ILL9_OFFSET
 #define SERDES_L2_TM_E_ILL9_OFFSET                                                 0XFD409944
-#undef SERDES_L2_TM_ILL13_OFFSET 
+#undef SERDES_L2_TM_ILL13_OFFSET
 #define SERDES_L2_TM_ILL13_OFFSET                                                  0XFD409994
-#undef SERDES_L3_TM_MISC2_OFFSET 
+#undef SERDES_L3_TM_MISC2_OFFSET
 #define SERDES_L3_TM_MISC2_OFFSET                                                  0XFD40D89C
-#undef SERDES_L3_TM_IQ_ILL1_OFFSET 
+#undef SERDES_L3_TM_IQ_ILL1_OFFSET
 #define SERDES_L3_TM_IQ_ILL1_OFFSET                                                0XFD40D8F8
-#undef SERDES_L3_TM_IQ_ILL2_OFFSET 
+#undef SERDES_L3_TM_IQ_ILL2_OFFSET
 #define SERDES_L3_TM_IQ_ILL2_OFFSET                                                0XFD40D8FC
-#undef SERDES_L3_TM_ILL12_OFFSET 
+#undef SERDES_L3_TM_ILL12_OFFSET
 #define SERDES_L3_TM_ILL12_OFFSET                                                  0XFD40D990
-#undef SERDES_L3_TM_E_ILL1_OFFSET 
+#undef SERDES_L3_TM_E_ILL1_OFFSET
 #define SERDES_L3_TM_E_ILL1_OFFSET                                                 0XFD40D924
-#undef SERDES_L3_TM_E_ILL2_OFFSET 
+#undef SERDES_L3_TM_E_ILL2_OFFSET
 #define SERDES_L3_TM_E_ILL2_OFFSET                                                 0XFD40D928
-#undef SERDES_L3_TM_ILL11_OFFSET 
+#undef SERDES_L3_TM_ILL11_OFFSET
 #define SERDES_L3_TM_ILL11_OFFSET                                                  0XFD40D98C
-#undef SERDES_L3_TM_IQ_ILL3_OFFSET 
+#undef SERDES_L3_TM_IQ_ILL3_OFFSET
 #define SERDES_L3_TM_IQ_ILL3_OFFSET                                                0XFD40D900
-#undef SERDES_L3_TM_E_ILL3_OFFSET 
+#undef SERDES_L3_TM_E_ILL3_OFFSET
 #define SERDES_L3_TM_E_ILL3_OFFSET                                                 0XFD40D92C
-#undef SERDES_L3_TM_ILL8_OFFSET 
+#undef SERDES_L3_TM_ILL8_OFFSET
 #define SERDES_L3_TM_ILL8_OFFSET                                                   0XFD40D980
-#undef SERDES_L3_TM_IQ_ILL8_OFFSET 
+#undef SERDES_L3_TM_IQ_ILL8_OFFSET
 #define SERDES_L3_TM_IQ_ILL8_OFFSET                                                0XFD40D914
-#undef SERDES_L3_TM_IQ_ILL9_OFFSET 
+#undef SERDES_L3_TM_IQ_ILL9_OFFSET
 #define SERDES_L3_TM_IQ_ILL9_OFFSET                                                0XFD40D918
-#undef SERDES_L3_TM_E_ILL8_OFFSET 
+#undef SERDES_L3_TM_E_ILL8_OFFSET
 #define SERDES_L3_TM_E_ILL8_OFFSET                                                 0XFD40D940
-#undef SERDES_L3_TM_E_ILL9_OFFSET 
+#undef SERDES_L3_TM_E_ILL9_OFFSET
 #define SERDES_L3_TM_E_ILL9_OFFSET                                                 0XFD40D944
-#undef SERDES_L3_TM_ILL13_OFFSET 
+#undef SERDES_L3_TM_ILL13_OFFSET
 #define SERDES_L3_TM_ILL13_OFFSET                                                  0XFD40D994
-#undef SERDES_L0_TM_DIG_10_OFFSET 
+#undef SERDES_L0_TM_DIG_10_OFFSET
 #define SERDES_L0_TM_DIG_10_OFFSET                                                 0XFD40107C
-#undef SERDES_L1_TM_DIG_10_OFFSET 
+#undef SERDES_L1_TM_DIG_10_OFFSET
 #define SERDES_L1_TM_DIG_10_OFFSET                                                 0XFD40507C
-#undef SERDES_L2_TM_DIG_10_OFFSET 
+#undef SERDES_L2_TM_DIG_10_OFFSET
 #define SERDES_L2_TM_DIG_10_OFFSET                                                 0XFD40907C
-#undef SERDES_L3_TM_DIG_10_OFFSET 
+#undef SERDES_L3_TM_DIG_10_OFFSET
 #define SERDES_L3_TM_DIG_10_OFFSET                                                 0XFD40D07C
-#undef SERDES_L0_TM_RST_DLY_OFFSET 
+#undef SERDES_L0_TM_RST_DLY_OFFSET
 #define SERDES_L0_TM_RST_DLY_OFFSET                                                0XFD4019A4
-#undef SERDES_L0_TM_ANA_BYP_15_OFFSET 
+#undef SERDES_L0_TM_ANA_BYP_15_OFFSET
 #define SERDES_L0_TM_ANA_BYP_15_OFFSET                                             0XFD401038
-#undef SERDES_L0_TM_ANA_BYP_12_OFFSET 
+#undef SERDES_L0_TM_ANA_BYP_12_OFFSET
 #define SERDES_L0_TM_ANA_BYP_12_OFFSET                                             0XFD40102C
-#undef SERDES_L1_TM_RST_DLY_OFFSET 
+#undef SERDES_L1_TM_RST_DLY_OFFSET
 #define SERDES_L1_TM_RST_DLY_OFFSET                                                0XFD4059A4
-#undef SERDES_L1_TM_ANA_BYP_15_OFFSET 
+#undef SERDES_L1_TM_ANA_BYP_15_OFFSET
 #define SERDES_L1_TM_ANA_BYP_15_OFFSET                                             0XFD405038
-#undef SERDES_L1_TM_ANA_BYP_12_OFFSET 
+#undef SERDES_L1_TM_ANA_BYP_12_OFFSET
 #define SERDES_L1_TM_ANA_BYP_12_OFFSET                                             0XFD40502C
-#undef SERDES_L2_TM_RST_DLY_OFFSET 
+#undef SERDES_L2_TM_RST_DLY_OFFSET
 #define SERDES_L2_TM_RST_DLY_OFFSET                                                0XFD4099A4
-#undef SERDES_L2_TM_ANA_BYP_15_OFFSET 
+#undef SERDES_L2_TM_ANA_BYP_15_OFFSET
 #define SERDES_L2_TM_ANA_BYP_15_OFFSET                                             0XFD409038
-#undef SERDES_L2_TM_ANA_BYP_12_OFFSET 
+#undef SERDES_L2_TM_ANA_BYP_12_OFFSET
 #define SERDES_L2_TM_ANA_BYP_12_OFFSET                                             0XFD40902C
-#undef SERDES_L3_TM_RST_DLY_OFFSET 
+#undef SERDES_L3_TM_RST_DLY_OFFSET
 #define SERDES_L3_TM_RST_DLY_OFFSET                                                0XFD40D9A4
-#undef SERDES_L3_TM_ANA_BYP_15_OFFSET 
+#undef SERDES_L3_TM_ANA_BYP_15_OFFSET
 #define SERDES_L3_TM_ANA_BYP_15_OFFSET                                             0XFD40D038
-#undef SERDES_L3_TM_ANA_BYP_12_OFFSET 
+#undef SERDES_L3_TM_ANA_BYP_12_OFFSET
 #define SERDES_L3_TM_ANA_BYP_12_OFFSET                                             0XFD40D02C
-#undef SERDES_L0_TM_MISC3_OFFSET 
+#undef SERDES_L0_TM_MISC3_OFFSET
 #define SERDES_L0_TM_MISC3_OFFSET                                                  0XFD4019AC
-#undef SERDES_L1_TM_MISC3_OFFSET 
+#undef SERDES_L1_TM_MISC3_OFFSET
 #define SERDES_L1_TM_MISC3_OFFSET                                                  0XFD4059AC
-#undef SERDES_L2_TM_MISC3_OFFSET 
+#undef SERDES_L2_TM_MISC3_OFFSET
 #define SERDES_L2_TM_MISC3_OFFSET                                                  0XFD4099AC
-#undef SERDES_L3_TM_MISC3_OFFSET 
+#undef SERDES_L3_TM_MISC3_OFFSET
 #define SERDES_L3_TM_MISC3_OFFSET                                                  0XFD40D9AC
-#undef SERDES_L0_TM_EQ11_OFFSET 
+#undef SERDES_L0_TM_EQ11_OFFSET
 #define SERDES_L0_TM_EQ11_OFFSET                                                   0XFD401978
-#undef SERDES_L1_TM_EQ11_OFFSET 
+#undef SERDES_L1_TM_EQ11_OFFSET
 #define SERDES_L1_TM_EQ11_OFFSET                                                   0XFD405978
-#undef SERDES_L2_TM_EQ11_OFFSET 
+#undef SERDES_L2_TM_EQ11_OFFSET
 #define SERDES_L2_TM_EQ11_OFFSET                                                   0XFD409978
-#undef SERDES_L3_TM_EQ11_OFFSET 
+#undef SERDES_L3_TM_EQ11_OFFSET
 #define SERDES_L3_TM_EQ11_OFFSET                                                   0XFD40D978
-#undef SERDES_ICM_CFG0_OFFSET 
+#undef SERDES_ICM_CFG0_OFFSET
 #define SERDES_ICM_CFG0_OFFSET                                                     0XFD410010
-#undef SERDES_ICM_CFG1_OFFSET 
+#undef SERDES_ICM_CFG1_OFFSET
 #define SERDES_ICM_CFG1_OFFSET                                                     0XFD410014
-#undef SERDES_L0_TXPMD_TM_45_OFFSET 
+#undef SERDES_L0_TXPMD_TM_45_OFFSET
 #define SERDES_L0_TXPMD_TM_45_OFFSET                                               0XFD400CB4
-#undef SERDES_L1_TXPMD_TM_45_OFFSET 
+#undef SERDES_L1_TXPMD_TM_45_OFFSET
 #define SERDES_L1_TXPMD_TM_45_OFFSET                                               0XFD404CB4
-#undef SERDES_L0_TX_ANA_TM_118_OFFSET 
+#undef SERDES_L0_TX_ANA_TM_118_OFFSET
 #define SERDES_L0_TX_ANA_TM_118_OFFSET                                             0XFD4001D8
-#undef SERDES_L1_TX_ANA_TM_118_OFFSET 
+#undef SERDES_L1_TX_ANA_TM_118_OFFSET
 #define SERDES_L1_TX_ANA_TM_118_OFFSET                                             0XFD4041D8
-#undef SERDES_L3_TX_ANA_TM_118_OFFSET 
+#undef SERDES_L3_TX_ANA_TM_118_OFFSET
 #define SERDES_L3_TX_ANA_TM_118_OFFSET                                             0XFD40C1D8
-#undef SERDES_L3_TM_CDR5_OFFSET 
+#undef SERDES_L3_TM_CDR5_OFFSET
 #define SERDES_L3_TM_CDR5_OFFSET                                                   0XFD40DC14
-#undef SERDES_L3_TM_CDR16_OFFSET 
+#undef SERDES_L3_TM_CDR16_OFFSET
 #define SERDES_L3_TM_CDR16_OFFSET                                                  0XFD40DC40
-#undef SERDES_L3_TM_EQ0_OFFSET 
+#undef SERDES_L3_TM_EQ0_OFFSET
 #define SERDES_L3_TM_EQ0_OFFSET                                                    0XFD40D94C
-#undef SERDES_L3_TM_EQ1_OFFSET 
+#undef SERDES_L3_TM_EQ1_OFFSET
 #define SERDES_L3_TM_EQ1_OFFSET                                                    0XFD40D950
-#undef SERDES_L1_TXPMD_TM_48_OFFSET 
+#undef SERDES_L1_TXPMD_TM_48_OFFSET
 #define SERDES_L1_TXPMD_TM_48_OFFSET                                               0XFD404CC0
-#undef SERDES_L0_TXPMD_TM_48_OFFSET 
+#undef SERDES_L0_TXPMD_TM_48_OFFSET
 #define SERDES_L0_TXPMD_TM_48_OFFSET                                               0XFD400CC0
-#undef SERDES_L1_TX_ANA_TM_18_OFFSET 
+#undef SERDES_L1_TX_ANA_TM_18_OFFSET
 #define SERDES_L1_TX_ANA_TM_18_OFFSET                                              0XFD404048
-#undef SERDES_L0_TX_ANA_TM_18_OFFSET 
+#undef SERDES_L0_TX_ANA_TM_18_OFFSET
 #define SERDES_L0_TX_ANA_TM_18_OFFSET                                              0XFD400048
-#undef SERDES_L3_TX_ANA_TM_18_OFFSET 
+#undef SERDES_L3_TX_ANA_TM_18_OFFSET
 #define SERDES_L3_TX_ANA_TM_18_OFFSET                                              0XFD40C048
 
 /*
@@ -31355,9 +31390,9 @@
     *  - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R
     * eserved
 */
-#undef SERDES_PLL_REF_SEL0_PLLREFSEL0_DEFVAL 
-#undef SERDES_PLL_REF_SEL0_PLLREFSEL0_SHIFT 
-#undef SERDES_PLL_REF_SEL0_PLLREFSEL0_MASK 
+#undef SERDES_PLL_REF_SEL0_PLLREFSEL0_DEFVAL
+#undef SERDES_PLL_REF_SEL0_PLLREFSEL0_SHIFT
+#undef SERDES_PLL_REF_SEL0_PLLREFSEL0_MASK
 #define SERDES_PLL_REF_SEL0_PLLREFSEL0_DEFVAL                  0x0000000D
 #define SERDES_PLL_REF_SEL0_PLLREFSEL0_SHIFT                   0
 #define SERDES_PLL_REF_SEL0_PLLREFSEL0_MASK                    0x0000001FU
@@ -31369,9 +31404,9 @@
     *  - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R
     * eserved
 */
-#undef SERDES_PLL_REF_SEL1_PLLREFSEL1_DEFVAL 
-#undef SERDES_PLL_REF_SEL1_PLLREFSEL1_SHIFT 
-#undef SERDES_PLL_REF_SEL1_PLLREFSEL1_MASK 
+#undef SERDES_PLL_REF_SEL1_PLLREFSEL1_DEFVAL
+#undef SERDES_PLL_REF_SEL1_PLLREFSEL1_SHIFT
+#undef SERDES_PLL_REF_SEL1_PLLREFSEL1_MASK
 #define SERDES_PLL_REF_SEL1_PLLREFSEL1_DEFVAL                  0x00000008
 #define SERDES_PLL_REF_SEL1_PLLREFSEL1_SHIFT                   0
 #define SERDES_PLL_REF_SEL1_PLLREFSEL1_MASK                    0x0000001FU
@@ -31383,9 +31418,9 @@
     *  - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R
     * eserved
 */
-#undef SERDES_PLL_REF_SEL2_PLLREFSEL2_DEFVAL 
-#undef SERDES_PLL_REF_SEL2_PLLREFSEL2_SHIFT 
-#undef SERDES_PLL_REF_SEL2_PLLREFSEL2_MASK 
+#undef SERDES_PLL_REF_SEL2_PLLREFSEL2_DEFVAL
+#undef SERDES_PLL_REF_SEL2_PLLREFSEL2_SHIFT
+#undef SERDES_PLL_REF_SEL2_PLLREFSEL2_MASK
 #define SERDES_PLL_REF_SEL2_PLLREFSEL2_DEFVAL                  0x0000000F
 #define SERDES_PLL_REF_SEL2_PLLREFSEL2_SHIFT                   0
 #define SERDES_PLL_REF_SEL2_PLLREFSEL2_MASK                    0x0000001FU
@@ -31397,9 +31432,9 @@
     *  - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R
     * eserved
 */
-#undef SERDES_PLL_REF_SEL3_PLLREFSEL3_DEFVAL 
-#undef SERDES_PLL_REF_SEL3_PLLREFSEL3_SHIFT 
-#undef SERDES_PLL_REF_SEL3_PLLREFSEL3_MASK 
+#undef SERDES_PLL_REF_SEL3_PLLREFSEL3_DEFVAL
+#undef SERDES_PLL_REF_SEL3_PLLREFSEL3_SHIFT
+#undef SERDES_PLL_REF_SEL3_PLLREFSEL3_MASK
 #define SERDES_PLL_REF_SEL3_PLLREFSEL3_DEFVAL                  0x0000000E
 #define SERDES_PLL_REF_SEL3_PLLREFSEL3_SHIFT                   0
 #define SERDES_PLL_REF_SEL3_PLLREFSEL3_MASK                    0x0000001FU
@@ -31408,9 +31443,9 @@
 * Sel of lane 0 ref clock local mux. Set to 1 to select lane 0 slicer outp
     * ut. Set to 0 to select lane0 ref clock mux output.
 */
-#undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_DEFVAL 
-#undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_SHIFT 
-#undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_MASK 
+#undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_DEFVAL
+#undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_SHIFT
+#undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_MASK
 #define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_DEFVAL     0x00000080
 #define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_SHIFT      7
 #define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_MASK       0x00000080U
@@ -31419,9 +31454,9 @@
 * Bit 3 of lane 0 ref clock mux one hot sel. Set to 1 to select lane 3 sli
     * cer output from ref clock network
 */
-#undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_SEL_3_DEFVAL 
-#undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_SEL_3_SHIFT 
-#undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_SEL_3_MASK 
+#undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_SEL_3_DEFVAL
+#undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_SEL_3_SHIFT
+#undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_SEL_3_MASK
 #define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_SEL_3_DEFVAL       0x00000080
 #define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_SEL_3_SHIFT        3
 #define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_SEL_3_MASK         0x00000008U
@@ -31430,9 +31465,9 @@
 * Sel of lane 1 ref clock local mux. Set to 1 to select lane 1 slicer outp
     * ut. Set to 0 to select lane1 ref clock mux output.
 */
-#undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_DEFVAL 
-#undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_SHIFT 
-#undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_MASK 
+#undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_DEFVAL
+#undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_SHIFT
+#undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_MASK
 #define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_DEFVAL     0x00000080
 #define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_SHIFT      7
 #define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_MASK       0x00000080U
@@ -31441,9 +31476,9 @@
 * Bit 3 of lane 1 ref clock mux one hot sel. Set to 1 to select lane 3 sli
     * cer output from ref clock network
 */
-#undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_DEFVAL 
-#undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_SHIFT 
-#undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_MASK 
+#undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_DEFVAL
+#undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_SHIFT
+#undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_MASK
 #define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_DEFVAL       0x00000080
 #define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_SHIFT        3
 #define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_MASK         0x00000008U
@@ -31452,9 +31487,9 @@
 * Sel of lane 2 ref clock local mux. Set to 1 to select lane 1 slicer outp
     * ut. Set to 0 to select lane2 ref clock mux output.
 */
-#undef SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_DEFVAL 
-#undef SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_SHIFT 
-#undef SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_MASK 
+#undef SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_DEFVAL
+#undef SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_SHIFT
+#undef SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_MASK
 #define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_DEFVAL     0x00000080
 #define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_SHIFT      7
 #define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_MASK       0x00000080U
@@ -31463,9 +31498,9 @@
 * Sel of lane 3 ref clock local mux. Set to 1 to select lane 3 slicer outp
     * ut. Set to 0 to select lane3 ref clock mux output.
 */
-#undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_DEFVAL 
-#undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_SHIFT 
-#undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_MASK 
+#undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_DEFVAL
+#undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_SHIFT
+#undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_MASK
 #define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_DEFVAL     0x00000080
 #define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_SHIFT      7
 #define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_MASK       0x00000080U
@@ -31474,9 +31509,9 @@
 * Bit 1 of lane 3 ref clock mux one hot sel. Set to 1 to select lane 1 sli
     * cer output from ref clock network
 */
-#undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_DEFVAL 
-#undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_SHIFT 
-#undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_MASK 
+#undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_DEFVAL
+#undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_SHIFT
+#undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_MASK
 #define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_DEFVAL       0x00000080
 #define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_SHIFT        1
 #define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_MASK         0x00000002U
@@ -31484,9 +31519,9 @@
 /*
 * Enable/Disable coarse code satureation limiting logic
 */
-#undef SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_DEFVAL 
-#undef SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_SHIFT 
-#undef SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_MASK 
+#undef SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_DEFVAL
+#undef SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_SHIFT
+#undef SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_MASK
 #define SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_DEFVAL  0x00000000
 #define SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_SHIFT  4
 #define SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_MASK  0x00000010U
@@ -31494,9 +31529,9 @@
 /*
 * Spread Spectrum No of Steps [7:0]
 */
-#undef SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL 
-#undef SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT 
-#undef SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK 
+#undef SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL
+#undef SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT
+#undef SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK
 #define SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL  0x00000000
 #define SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT  0
 #define SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK  0x000000FFU
@@ -31504,9 +31539,9 @@
 /*
 * Spread Spectrum No of Steps [10:8]
 */
-#undef SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL 
-#undef SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT 
-#undef SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK 
+#undef SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL
+#undef SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT
+#undef SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK
 #define SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL  0x00000000
 #define SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT  0
 #define SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK  0x00000007U
@@ -31514,9 +31549,9 @@
 /*
 * Spread Spectrum No of Steps [7:0]
 */
-#undef SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL 
-#undef SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT 
-#undef SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK 
+#undef SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL
+#undef SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT
+#undef SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK
 #define SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL  0x00000000
 #define SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT  0
 #define SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK  0x000000FFU
@@ -31524,9 +31559,9 @@
 /*
 * Spread Spectrum No of Steps [10:8]
 */
-#undef SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL 
-#undef SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT 
-#undef SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK 
+#undef SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL
+#undef SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT
+#undef SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK
 #define SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL  0x00000000
 #define SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT  0
 #define SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK  0x00000007U
@@ -31534,9 +31569,9 @@
 /*
 * Spread Spectrum No of Steps [7:0]
 */
-#undef SERDES_L0_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL 
-#undef SERDES_L0_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT 
-#undef SERDES_L0_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK 
+#undef SERDES_L0_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL
+#undef SERDES_L0_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT
+#undef SERDES_L0_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK
 #define SERDES_L0_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL  0x00000000
 #define SERDES_L0_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT  0
 #define SERDES_L0_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK  0x000000FFU
@@ -31544,9 +31579,9 @@
 /*
 * Spread Spectrum No of Steps [10:8]
 */
-#undef SERDES_L0_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL 
-#undef SERDES_L0_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT 
-#undef SERDES_L0_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK 
+#undef SERDES_L0_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL
+#undef SERDES_L0_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT
+#undef SERDES_L0_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK
 #define SERDES_L0_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL  0x00000000
 #define SERDES_L0_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT  0
 #define SERDES_L0_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK  0x00000007U
@@ -31554,9 +31589,9 @@
 /*
 * Spread Spectrum No of Steps [7:0]
 */
-#undef SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL 
-#undef SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT 
-#undef SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK 
+#undef SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL
+#undef SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT
+#undef SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK
 #define SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL  0x00000000
 #define SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT  0
 #define SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK  0x000000FFU
@@ -31564,9 +31599,9 @@
 /*
 * Spread Spectrum No of Steps [10:8]
 */
-#undef SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL 
-#undef SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT 
-#undef SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK 
+#undef SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL
+#undef SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT
+#undef SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK
 #define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL  0x00000000
 #define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT  0
 #define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK  0x00000007U
@@ -31574,9 +31609,9 @@
 /*
 * Step Size for Spread Spectrum [7:0]
 */
-#undef SERDES_L0_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL 
-#undef SERDES_L0_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT 
-#undef SERDES_L0_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK 
+#undef SERDES_L0_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL
+#undef SERDES_L0_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT
+#undef SERDES_L0_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK
 #define SERDES_L0_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL  0x00000000
 #define SERDES_L0_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT  0
 #define SERDES_L0_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK  0x000000FFU
@@ -31584,9 +31619,9 @@
 /*
 * Step Size for Spread Spectrum [15:8]
 */
-#undef SERDES_L0_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL 
-#undef SERDES_L0_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT 
-#undef SERDES_L0_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK 
+#undef SERDES_L0_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL
+#undef SERDES_L0_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT
+#undef SERDES_L0_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK
 #define SERDES_L0_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL     0x00000000
 #define SERDES_L0_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT      0
 #define SERDES_L0_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK       0x000000FFU
@@ -31594,9 +31629,9 @@
 /*
 * Step Size for Spread Spectrum [23:16]
 */
-#undef SERDES_L0_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL 
-#undef SERDES_L0_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT 
-#undef SERDES_L0_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK 
+#undef SERDES_L0_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL
+#undef SERDES_L0_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT
+#undef SERDES_L0_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK
 #define SERDES_L0_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL     0x00000000
 #define SERDES_L0_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT      0
 #define SERDES_L0_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK       0x000000FFU
@@ -31604,9 +31639,9 @@
 /*
 * Step Size for Spread Spectrum [25:24]
 */
-#undef SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL 
-#undef SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT 
-#undef SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK 
+#undef SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL
+#undef SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT
+#undef SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK
 #define SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL  0x00000000
 #define SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT  0
 #define SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK  0x00000003U
@@ -31614,9 +31649,9 @@
 /*
 * Enable/Disable test mode force on SS step size
 */
-#undef SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL 
-#undef SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT 
-#undef SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK 
+#undef SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL
+#undef SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT
+#undef SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK
 #define SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL  0x00000000
 #define SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT  4
 #define SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK  0x00000010U
@@ -31624,9 +31659,9 @@
 /*
 * Enable/Disable test mode force on SS no of steps
 */
-#undef SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL 
-#undef SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT 
-#undef SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK 
+#undef SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL
+#undef SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT
+#undef SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK
 #define SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL  0x00000000
 #define SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT  5
 #define SERDES_L0_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK  0x00000020U
@@ -31634,9 +31669,9 @@
 /*
 * Step Size for Spread Spectrum [7:0]
 */
-#undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL 
-#undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT 
-#undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK 
+#undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL
+#undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT
+#undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK
 #define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL  0x00000000
 #define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT  0
 #define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK  0x000000FFU
@@ -31644,9 +31679,9 @@
 /*
 * Step Size for Spread Spectrum [15:8]
 */
-#undef SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL 
-#undef SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT 
-#undef SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK 
+#undef SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL
+#undef SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT
+#undef SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK
 #define SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL     0x00000000
 #define SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT      0
 #define SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK       0x000000FFU
@@ -31654,9 +31689,9 @@
 /*
 * Step Size for Spread Spectrum [23:16]
 */
-#undef SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL 
-#undef SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT 
-#undef SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK 
+#undef SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL
+#undef SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT
+#undef SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK
 #define SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL     0x00000000
 #define SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT      0
 #define SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK       0x000000FFU
@@ -31664,9 +31699,9 @@
 /*
 * Step Size for Spread Spectrum [25:24]
 */
-#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL 
-#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT 
-#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK 
+#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL
+#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT
+#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK
 #define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL  0x00000000
 #define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT  0
 #define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK  0x00000003U
@@ -31674,9 +31709,9 @@
 /*
 * Enable/Disable test mode force on SS step size
 */
-#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL 
-#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT 
-#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK 
+#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL
+#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT
+#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK
 #define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL  0x00000000
 #define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT  4
 #define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK  0x00000010U
@@ -31684,9 +31719,9 @@
 /*
 * Enable/Disable test mode force on SS no of steps
 */
-#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL 
-#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT 
-#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK 
+#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL
+#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT
+#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK
 #define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL  0x00000000
 #define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT  5
 #define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK  0x00000020U
@@ -31694,9 +31729,9 @@
 /*
 * Step Size for Spread Spectrum [7:0]
 */
-#undef SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL 
-#undef SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT 
-#undef SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK 
+#undef SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL
+#undef SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT
+#undef SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK
 #define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL  0x00000000
 #define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT  0
 #define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK  0x000000FFU
@@ -31704,9 +31739,9 @@
 /*
 * Step Size for Spread Spectrum [15:8]
 */
-#undef SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL 
-#undef SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT 
-#undef SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK 
+#undef SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL
+#undef SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT
+#undef SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK
 #define SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL     0x00000000
 #define SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT      0
 #define SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK       0x000000FFU
@@ -31714,9 +31749,9 @@
 /*
 * Step Size for Spread Spectrum [23:16]
 */
-#undef SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL 
-#undef SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT 
-#undef SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK 
+#undef SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL
+#undef SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT
+#undef SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK
 #define SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL     0x00000000
 #define SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT      0
 #define SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK       0x000000FFU
@@ -31724,9 +31759,9 @@
 /*
 * Step Size for Spread Spectrum [25:24]
 */
-#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL 
-#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT 
-#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK 
+#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL
+#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT
+#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK
 #define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL  0x00000000
 #define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT  0
 #define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK  0x00000003U
@@ -31734,9 +31769,9 @@
 /*
 * Enable/Disable test mode force on SS step size
 */
-#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL 
-#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT 
-#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK 
+#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL
+#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT
+#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK
 #define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL  0x00000000
 #define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT  4
 #define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK  0x00000010U
@@ -31744,9 +31779,9 @@
 /*
 * Enable/Disable test mode force on SS no of steps
 */
-#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL 
-#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT 
-#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK 
+#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL
+#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT
+#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK
 #define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL  0x00000000
 #define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT  5
 #define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK  0x00000020U
@@ -31754,9 +31789,9 @@
 /*
 * Step Size for Spread Spectrum [7:0]
 */
-#undef SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL 
-#undef SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT 
-#undef SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK 
+#undef SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL
+#undef SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT
+#undef SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK
 #define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL  0x00000000
 #define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT  0
 #define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK  0x000000FFU
@@ -31764,9 +31799,9 @@
 /*
 * Step Size for Spread Spectrum [15:8]
 */
-#undef SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL 
-#undef SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT 
-#undef SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK 
+#undef SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL
+#undef SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT
+#undef SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK
 #define SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL     0x00000000
 #define SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT      0
 #define SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK       0x000000FFU
@@ -31774,9 +31809,9 @@
 /*
 * Step Size for Spread Spectrum [23:16]
 */
-#undef SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL 
-#undef SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT 
-#undef SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK 
+#undef SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL
+#undef SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT
+#undef SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK
 #define SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL     0x00000000
 #define SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT      0
 #define SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK       0x000000FFU
@@ -31784,9 +31819,9 @@
 /*
 * Step Size for Spread Spectrum [25:24]
 */
-#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL 
-#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT 
-#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK 
+#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL
+#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT
+#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK
 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL  0x00000000
 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT  0
 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK  0x00000003U
@@ -31794,9 +31829,9 @@
 /*
 * Enable/Disable test mode force on SS step size
 */
-#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL 
-#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT 
-#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK 
+#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL
+#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT
+#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK
 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL  0x00000000
 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT  4
 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK  0x00000010U
@@ -31804,9 +31839,9 @@
 /*
 * Enable/Disable test mode force on SS no of steps
 */
-#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL 
-#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT 
-#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK 
+#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL
+#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT
+#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK
 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL  0x00000000
 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT  5
 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK  0x00000020U
@@ -31814,9 +31849,9 @@
 /*
 * Enable test mode forcing on enable Spread Spectrum
 */
-#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_DEFVAL 
-#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_SHIFT 
-#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_MASK 
+#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_DEFVAL
+#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_SHIFT
+#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_MASK
 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_DEFVAL  0x00000000
 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_SHIFT  7
 #define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_MASK   0x00000080U
@@ -31824,9 +31859,9 @@
 /*
 * Bypass Descrambler
 */
-#undef SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_DEFVAL 
-#undef SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_SHIFT 
-#undef SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_MASK 
+#undef SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_DEFVAL
+#undef SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_SHIFT
+#undef SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_MASK
 #define SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_DEFVAL               0x00000000
 #define SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_SHIFT                1
 #define SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_MASK                 0x00000002U
@@ -31834,9 +31869,9 @@
 /*
 * Enable Bypass for <1> TM_DIG_CTRL_6
 */
-#undef SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL 
-#undef SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT 
-#undef SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK 
+#undef SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL
+#undef SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT
+#undef SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK
 #define SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL         0x00000000
 #define SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT          0
 #define SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK           0x00000001U
@@ -31844,9 +31879,9 @@
 /*
 * Bypass scrambler signal
 */
-#undef SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL 
-#undef SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT 
-#undef SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_MASK 
+#undef SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL
+#undef SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT
+#undef SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_MASK
 #define SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL             0x00000000
 #define SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT              1
 #define SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_MASK               0x00000002U
@@ -31854,9 +31889,9 @@
 /*
 * Enable/disable scrambler bypass signal
 */
-#undef SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL 
-#undef SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT 
-#undef SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK 
+#undef SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL
+#undef SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT
+#undef SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK
 #define SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL       0x00000000
 #define SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT        0
 #define SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK         0x00000001U
@@ -31864,9 +31899,9 @@
 /*
 * Enable test mode force on fractional mode enable
 */
-#undef SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_DEFVAL 
-#undef SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_SHIFT 
-#undef SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_MASK 
+#undef SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_DEFVAL
+#undef SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_SHIFT
+#undef SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_MASK
 #define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_DEFVAL  0x00000000
 #define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_SHIFT  6
 #define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_MASK   0x00000040U
@@ -31874,9 +31909,9 @@
 /*
 * Bypass 8b10b decoder
 */
-#undef SERDES_L3_TM_DIG_6_BYPASS_DECODER_DEFVAL 
-#undef SERDES_L3_TM_DIG_6_BYPASS_DECODER_SHIFT 
-#undef SERDES_L3_TM_DIG_6_BYPASS_DECODER_MASK 
+#undef SERDES_L3_TM_DIG_6_BYPASS_DECODER_DEFVAL
+#undef SERDES_L3_TM_DIG_6_BYPASS_DECODER_SHIFT
+#undef SERDES_L3_TM_DIG_6_BYPASS_DECODER_MASK
 #define SERDES_L3_TM_DIG_6_BYPASS_DECODER_DEFVAL               0x00000000
 #define SERDES_L3_TM_DIG_6_BYPASS_DECODER_SHIFT                3
 #define SERDES_L3_TM_DIG_6_BYPASS_DECODER_MASK                 0x00000008U
@@ -31884,9 +31919,9 @@
 /*
 * Enable Bypass for <3> TM_DIG_CTRL_6
 */
-#undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_DEFVAL 
-#undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_SHIFT 
-#undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_MASK 
+#undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_DEFVAL
+#undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_SHIFT
+#undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_MASK
 #define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_DEFVAL             0x00000000
 #define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_SHIFT              2
 #define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_MASK               0x00000004U
@@ -31894,9 +31929,9 @@
 /*
 * Bypass Descrambler
 */
-#undef SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_DEFVAL 
-#undef SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_SHIFT 
-#undef SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_MASK 
+#undef SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_DEFVAL
+#undef SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_SHIFT
+#undef SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_MASK
 #define SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_DEFVAL               0x00000000
 #define SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_SHIFT                1
 #define SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_MASK                 0x00000002U
@@ -31904,9 +31939,9 @@
 /*
 * Enable Bypass for <1> TM_DIG_CTRL_6
 */
-#undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL 
-#undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT 
-#undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK 
+#undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL
+#undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT
+#undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK
 #define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL         0x00000000
 #define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT          0
 #define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK           0x00000001U
@@ -31914,9 +31949,9 @@
 /*
 * Enable/disable encoder bypass signal
 */
-#undef SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_DEFVAL 
-#undef SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_SHIFT 
-#undef SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_MASK 
+#undef SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_DEFVAL
+#undef SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_SHIFT
+#undef SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_MASK
 #define SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_DEFVAL               0x00000000
 #define SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_SHIFT                3
 #define SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_MASK                 0x00000008U
@@ -31924,9 +31959,9 @@
 /*
 * Bypass scrambler signal
 */
-#undef SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL 
-#undef SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT 
-#undef SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_MASK 
+#undef SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL
+#undef SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT
+#undef SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_MASK
 #define SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL             0x00000000
 #define SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT              1
 #define SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_MASK               0x00000002U
@@ -31934,9 +31969,9 @@
 /*
 * Enable/disable scrambler bypass signal
 */
-#undef SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL 
-#undef SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT 
-#undef SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK 
+#undef SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL
+#undef SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT
+#undef SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK
 #define SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL       0x00000000
 #define SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT        0
 #define SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK         0x00000001U
@@ -31944,9 +31979,9 @@
 /*
 * Spare- not used
 */
-#undef SERDES_L2_TM_AUX_0_BIT_2_DEFVAL 
-#undef SERDES_L2_TM_AUX_0_BIT_2_SHIFT 
-#undef SERDES_L2_TM_AUX_0_BIT_2_MASK 
+#undef SERDES_L2_TM_AUX_0_BIT_2_DEFVAL
+#undef SERDES_L2_TM_AUX_0_BIT_2_SHIFT
+#undef SERDES_L2_TM_AUX_0_BIT_2_MASK
 #define SERDES_L2_TM_AUX_0_BIT_2_DEFVAL                        0x00000000
 #define SERDES_L2_TM_AUX_0_BIT_2_SHIFT                         5
 #define SERDES_L2_TM_AUX_0_BIT_2_MASK                          0x00000020U
@@ -31954,9 +31989,9 @@
 /*
 * Enable Eye Surf
 */
-#undef SERDES_L0_TM_DIG_8_EYESURF_ENABLE_DEFVAL 
-#undef SERDES_L0_TM_DIG_8_EYESURF_ENABLE_SHIFT 
-#undef SERDES_L0_TM_DIG_8_EYESURF_ENABLE_MASK 
+#undef SERDES_L0_TM_DIG_8_EYESURF_ENABLE_DEFVAL
+#undef SERDES_L0_TM_DIG_8_EYESURF_ENABLE_SHIFT
+#undef SERDES_L0_TM_DIG_8_EYESURF_ENABLE_MASK
 #define SERDES_L0_TM_DIG_8_EYESURF_ENABLE_DEFVAL               0x00000000
 #define SERDES_L0_TM_DIG_8_EYESURF_ENABLE_SHIFT                4
 #define SERDES_L0_TM_DIG_8_EYESURF_ENABLE_MASK                 0x00000010U
@@ -31964,9 +31999,9 @@
 /*
 * Enable Eye Surf
 */
-#undef SERDES_L1_TM_DIG_8_EYESURF_ENABLE_DEFVAL 
-#undef SERDES_L1_TM_DIG_8_EYESURF_ENABLE_SHIFT 
-#undef SERDES_L1_TM_DIG_8_EYESURF_ENABLE_MASK 
+#undef SERDES_L1_TM_DIG_8_EYESURF_ENABLE_DEFVAL
+#undef SERDES_L1_TM_DIG_8_EYESURF_ENABLE_SHIFT
+#undef SERDES_L1_TM_DIG_8_EYESURF_ENABLE_MASK
 #define SERDES_L1_TM_DIG_8_EYESURF_ENABLE_DEFVAL               0x00000000
 #define SERDES_L1_TM_DIG_8_EYESURF_ENABLE_SHIFT                4
 #define SERDES_L1_TM_DIG_8_EYESURF_ENABLE_MASK                 0x00000010U
@@ -31974,9 +32009,9 @@
 /*
 * Enable Eye Surf
 */
-#undef SERDES_L2_TM_DIG_8_EYESURF_ENABLE_DEFVAL 
-#undef SERDES_L2_TM_DIG_8_EYESURF_ENABLE_SHIFT 
-#undef SERDES_L2_TM_DIG_8_EYESURF_ENABLE_MASK 
+#undef SERDES_L2_TM_DIG_8_EYESURF_ENABLE_DEFVAL
+#undef SERDES_L2_TM_DIG_8_EYESURF_ENABLE_SHIFT
+#undef SERDES_L2_TM_DIG_8_EYESURF_ENABLE_MASK
 #define SERDES_L2_TM_DIG_8_EYESURF_ENABLE_DEFVAL               0x00000000
 #define SERDES_L2_TM_DIG_8_EYESURF_ENABLE_SHIFT                4
 #define SERDES_L2_TM_DIG_8_EYESURF_ENABLE_MASK                 0x00000010U
@@ -31984,9 +32019,9 @@
 /*
 * Enable Eye Surf
 */
-#undef SERDES_L3_TM_DIG_8_EYESURF_ENABLE_DEFVAL 
-#undef SERDES_L3_TM_DIG_8_EYESURF_ENABLE_SHIFT 
-#undef SERDES_L3_TM_DIG_8_EYESURF_ENABLE_MASK 
+#undef SERDES_L3_TM_DIG_8_EYESURF_ENABLE_DEFVAL
+#undef SERDES_L3_TM_DIG_8_EYESURF_ENABLE_SHIFT
+#undef SERDES_L3_TM_DIG_8_EYESURF_ENABLE_MASK
 #define SERDES_L3_TM_DIG_8_EYESURF_ENABLE_DEFVAL               0x00000000
 #define SERDES_L3_TM_DIG_8_EYESURF_ENABLE_SHIFT                4
 #define SERDES_L3_TM_DIG_8_EYESURF_ENABLE_MASK                 0x00000010U
@@ -31994,9 +32029,9 @@
 /*
 * ILL cal idle val refcnt
 */
-#undef SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL 
-#undef SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT 
-#undef SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK 
+#undef SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL
+#undef SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT
+#undef SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK
 #define SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL      0x00000001
 #define SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT       0
 #define SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK        0x00000007U
@@ -32004,9 +32039,9 @@
 /*
 * ILL cal idle val refcnt
 */
-#undef SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL 
-#undef SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT 
-#undef SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK 
+#undef SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL
+#undef SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT
+#undef SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK
 #define SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL      0x00000001
 #define SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT       0
 #define SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK        0x00000007U
@@ -32014,9 +32049,9 @@
 /*
 * ILL calib counts BYPASSED with calcode bits
 */
-#undef SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL 
-#undef SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT 
-#undef SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK 
+#undef SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL
+#undef SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT
+#undef SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK
 #define SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL        0x00000000
 #define SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT         7
 #define SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK          0x00000080U
@@ -32025,9 +32060,9 @@
 * IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 ,
     * USB3 : SS
 */
-#undef SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL 
-#undef SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT 
-#undef SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK 
+#undef SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL
+#undef SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT
+#undef SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK
 #define SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL   0x00000000
 #define SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT    0
 #define SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK     0x000000FFU
@@ -32035,9 +32070,9 @@
 /*
 * IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
 */
-#undef SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL 
-#undef SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT 
-#undef SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK 
+#undef SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL
+#undef SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT
+#undef SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK
 #define SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL   0x00000000
 #define SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT    0
 #define SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK     0x000000FFU
@@ -32045,9 +32080,9 @@
 /*
 * G1A pll ctr bypass value
 */
-#undef SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL 
-#undef SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT 
-#undef SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK 
+#undef SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL
+#undef SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT
+#undef SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK
 #define SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL          0x00000000
 #define SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT           0
 #define SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK            0x000000FFU
@@ -32056,9 +32091,9 @@
 * E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U
     * SB3 : SS
 */
-#undef SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL 
-#undef SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT 
-#undef SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK 
+#undef SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL
+#undef SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT
+#undef SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK
 #define SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL     0x00000000
 #define SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT      0
 #define SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK       0x000000FFU
@@ -32066,9 +32101,9 @@
 /*
 * E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
 */
-#undef SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL 
-#undef SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT 
-#undef SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK 
+#undef SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL
+#undef SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT
+#undef SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK
 #define SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL     0x00000000
 #define SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT      0
 #define SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK       0x000000FFU
@@ -32076,9 +32111,9 @@
 /*
 * IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
 */
-#undef SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL 
-#undef SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT 
-#undef SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK 
+#undef SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL
+#undef SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT
+#undef SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK
 #define SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL   0x00000000
 #define SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT    0
 #define SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK     0x000000FFU
@@ -32086,9 +32121,9 @@
 /*
 * E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
 */
-#undef SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL 
-#undef SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT 
-#undef SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK 
+#undef SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL
+#undef SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT
+#undef SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK
 #define SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL     0x00000000
 #define SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT      0
 #define SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK       0x000000FFU
@@ -32096,9 +32131,9 @@
 /*
 * ILL calibration code change wait time
 */
-#undef SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL 
-#undef SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT 
-#undef SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_MASK 
+#undef SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL
+#undef SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT
+#undef SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_MASK
 #define SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL             0x00000002
 #define SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT              0
 #define SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_MASK               0x000000FFU
@@ -32106,9 +32141,9 @@
 /*
 * IQ ILL polytrim bypass value
 */
-#undef SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL 
-#undef SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT 
-#undef SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK 
+#undef SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL
+#undef SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT
+#undef SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK
 #define SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL  0x00000000
 #define SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT  0
 #define SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK   0x000000FFU
@@ -32116,9 +32151,9 @@
 /*
 * bypass IQ polytrim
 */
-#undef SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL 
-#undef SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT 
-#undef SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK 
+#undef SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL
+#undef SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT
+#undef SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK
 #define SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL      0x00000000
 #define SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT       0
 #define SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK        0x00000001U
@@ -32126,9 +32161,9 @@
 /*
 * E ILL polytrim bypass value
 */
-#undef SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL 
-#undef SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT 
-#undef SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK 
+#undef SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL
+#undef SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT
+#undef SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK
 #define SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL   0x00000000
 #define SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT    0
 #define SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK     0x000000FFU
@@ -32136,9 +32171,9 @@
 /*
 * bypass E polytrim
 */
-#undef SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL 
-#undef SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT 
-#undef SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK 
+#undef SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL
+#undef SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT
+#undef SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK
 #define SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL        0x00000000
 #define SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT         0
 #define SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK          0x00000001U
@@ -32146,9 +32181,9 @@
 /*
 * ILL cal idle val refcnt
 */
-#undef SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL 
-#undef SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT 
-#undef SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK 
+#undef SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL
+#undef SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT
+#undef SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK
 #define SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL      0x00000001
 #define SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT       0
 #define SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK        0x00000007U
@@ -32156,9 +32191,9 @@
 /*
 * ILL calib counts BYPASSED with calcode bits
 */
-#undef SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL 
-#undef SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT 
-#undef SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK 
+#undef SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL
+#undef SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT
+#undef SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK
 #define SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL        0x00000000
 #define SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT         7
 #define SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK          0x00000080U
@@ -32167,9 +32202,9 @@
 * IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 ,
     * USB3 : SS
 */
-#undef SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL 
-#undef SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT 
-#undef SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK 
+#undef SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL
+#undef SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT
+#undef SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK
 #define SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL   0x00000000
 #define SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT    0
 #define SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK     0x000000FFU
@@ -32177,9 +32212,9 @@
 /*
 * IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
 */
-#undef SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL 
-#undef SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT 
-#undef SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK 
+#undef SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL
+#undef SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT
+#undef SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK
 #define SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL   0x00000000
 #define SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT    0
 #define SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK     0x000000FFU
@@ -32187,9 +32222,9 @@
 /*
 * G1A pll ctr bypass value
 */
-#undef SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL 
-#undef SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT 
-#undef SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK 
+#undef SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL
+#undef SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT
+#undef SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK
 #define SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL          0x00000000
 #define SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT           0
 #define SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK            0x000000FFU
@@ -32198,9 +32233,9 @@
 * E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U
     * SB3 : SS
 */
-#undef SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL 
-#undef SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT 
-#undef SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK 
+#undef SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL
+#undef SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT
+#undef SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK
 #define SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL     0x00000000
 #define SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT      0
 #define SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK       0x000000FFU
@@ -32208,9 +32243,9 @@
 /*
 * E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2
 */
-#undef SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL 
-#undef SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT 
-#undef SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK 
+#undef SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL
+#undef SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT
+#undef SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK
 #define SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL     0x00000000
 #define SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT      0
 #define SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK       0x000000FFU
@@ -32218,9 +32253,9 @@
 /*
 * G2A_PCIe1 PLL ctr bypass value
 */
-#undef SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_DEFVAL 
-#undef SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_SHIFT 
-#undef SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_MASK 
+#undef SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_DEFVAL
+#undef SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_SHIFT
+#undef SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_MASK
 #define SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_DEFVAL  0x00000000
 #define SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_SHIFT  4
 #define SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_MASK  0x000000F0U
@@ -32228,9 +32263,9 @@
 /*
 * IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
 */
-#undef SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL 
-#undef SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT 
-#undef SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK 
+#undef SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL
+#undef SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT
+#undef SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK
 #define SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL   0x00000000
 #define SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT    0
 #define SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK     0x000000FFU
@@ -32238,9 +32273,9 @@
 /*
 * E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3
 */
-#undef SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL 
-#undef SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT 
-#undef SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK 
+#undef SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL
+#undef SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT
+#undef SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK
 #define SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL     0x00000000
 #define SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT      0
 #define SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK       0x000000FFU
@@ -32248,9 +32283,9 @@
 /*
 * ILL calibration code change wait time
 */
-#undef SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL 
-#undef SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT 
-#undef SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_MASK 
+#undef SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL
+#undef SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT
+#undef SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_MASK
 #define SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL             0x00000002
 #define SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT              0
 #define SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_MASK               0x000000FFU
@@ -32258,9 +32293,9 @@
 /*
 * IQ ILL polytrim bypass value
 */
-#undef SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL 
-#undef SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT 
-#undef SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK 
+#undef SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL
+#undef SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT
+#undef SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK
 #define SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL  0x00000000
 #define SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT  0
 #define SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK   0x000000FFU
@@ -32268,9 +32303,9 @@
 /*
 * bypass IQ polytrim
 */
-#undef SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL 
-#undef SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT 
-#undef SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK 
+#undef SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL
+#undef SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT
+#undef SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK
 #define SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL      0x00000000
 #define SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT       0
 #define SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK        0x00000001U
@@ -32278,9 +32313,9 @@
 /*
 * E ILL polytrim bypass value
 */
-#undef SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL 
-#undef SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT 
-#undef SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK 
+#undef SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL
+#undef SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT
+#undef SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK
 #define SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL   0x00000000
 #define SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT    0
 #define SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK     0x000000FFU
@@ -32288,9 +32323,9 @@
 /*
 * bypass E polytrim
 */
-#undef SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL 
-#undef SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT 
-#undef SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK 
+#undef SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL
+#undef SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT
+#undef SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK
 #define SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL        0x00000000
 #define SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT         0
 #define SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK          0x00000001U
@@ -32298,9 +32333,9 @@
 /*
 * ILL cal idle val refcnt
 */
-#undef SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL 
-#undef SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT 
-#undef SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK 
+#undef SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL
+#undef SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT
+#undef SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK
 #define SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL      0x00000001
 #define SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT       0
 #define SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK        0x00000007U
@@ -32308,9 +32343,9 @@
 /*
 * CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001
 */
-#undef SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL 
-#undef SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT 
-#undef SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK 
+#undef SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL
+#undef SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT
+#undef SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK
 #define SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL           0x00000001
 #define SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT            0
 #define SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK             0x0000000FU
@@ -32318,9 +32353,9 @@
 /*
 * CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001
 */
-#undef SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL 
-#undef SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT 
-#undef SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK 
+#undef SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL
+#undef SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT
+#undef SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK
 #define SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL           0x00000001
 #define SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT            0
 #define SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK             0x0000000FU
@@ -32328,9 +32363,9 @@
 /*
 * CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001
 */
-#undef SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL 
-#undef SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT 
-#undef SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK 
+#undef SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL
+#undef SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT
+#undef SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK
 #define SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL           0x00000001
 #define SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT            0
 #define SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK             0x0000000FU
@@ -32338,9 +32373,9 @@
 /*
 * CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001
 */
-#undef SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL 
-#undef SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT 
-#undef SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK 
+#undef SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL
+#undef SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT
+#undef SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK
 #define SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL           0x00000001
 #define SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT            0
 #define SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK             0x0000000FU
@@ -32348,9 +32383,9 @@
 /*
 * Delay apb reset by specified amount
 */
-#undef SERDES_L0_TM_RST_DLY_APB_RST_DLY_DEFVAL 
-#undef SERDES_L0_TM_RST_DLY_APB_RST_DLY_SHIFT 
-#undef SERDES_L0_TM_RST_DLY_APB_RST_DLY_MASK 
+#undef SERDES_L0_TM_RST_DLY_APB_RST_DLY_DEFVAL
+#undef SERDES_L0_TM_RST_DLY_APB_RST_DLY_SHIFT
+#undef SERDES_L0_TM_RST_DLY_APB_RST_DLY_MASK
 #define SERDES_L0_TM_RST_DLY_APB_RST_DLY_DEFVAL                0x00000000
 #define SERDES_L0_TM_RST_DLY_APB_RST_DLY_SHIFT                 0
 #define SERDES_L0_TM_RST_DLY_APB_RST_DLY_MASK                  0x000000FFU
@@ -32358,9 +32393,9 @@
 /*
 * Enable Bypass for <7> of TM_ANA_BYPS_15
 */
-#undef SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 
-#undef SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 
-#undef SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 
+#undef SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL
+#undef SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT
+#undef SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK
 #define SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL  0x00000000
 #define SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT  6
 #define SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK  0x00000040U
@@ -32368,9 +32403,9 @@
 /*
 * Enable Bypass for <7> of TM_ANA_BYPS_12
 */
-#undef SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 
-#undef SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 
-#undef SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 
+#undef SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL
+#undef SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT
+#undef SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK
 #define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL  0x00000000
 #define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT   6
 #define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK    0x00000040U
@@ -32378,9 +32413,9 @@
 /*
 * Delay apb reset by specified amount
 */
-#undef SERDES_L1_TM_RST_DLY_APB_RST_DLY_DEFVAL 
-#undef SERDES_L1_TM_RST_DLY_APB_RST_DLY_SHIFT 
-#undef SERDES_L1_TM_RST_DLY_APB_RST_DLY_MASK 
+#undef SERDES_L1_TM_RST_DLY_APB_RST_DLY_DEFVAL
+#undef SERDES_L1_TM_RST_DLY_APB_RST_DLY_SHIFT
+#undef SERDES_L1_TM_RST_DLY_APB_RST_DLY_MASK
 #define SERDES_L1_TM_RST_DLY_APB_RST_DLY_DEFVAL                0x00000000
 #define SERDES_L1_TM_RST_DLY_APB_RST_DLY_SHIFT                 0
 #define SERDES_L1_TM_RST_DLY_APB_RST_DLY_MASK                  0x000000FFU
@@ -32388,9 +32423,9 @@
 /*
 * Enable Bypass for <7> of TM_ANA_BYPS_15
 */
-#undef SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 
-#undef SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 
-#undef SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 
+#undef SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL
+#undef SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT
+#undef SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK
 #define SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL  0x00000000
 #define SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT  6
 #define SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK  0x00000040U
@@ -32398,9 +32433,9 @@
 /*
 * Enable Bypass for <7> of TM_ANA_BYPS_12
 */
-#undef SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 
-#undef SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 
-#undef SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 
+#undef SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL
+#undef SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT
+#undef SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK
 #define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL  0x00000000
 #define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT   6
 #define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK    0x00000040U
@@ -32408,9 +32443,9 @@
 /*
 * Delay apb reset by specified amount
 */
-#undef SERDES_L2_TM_RST_DLY_APB_RST_DLY_DEFVAL 
-#undef SERDES_L2_TM_RST_DLY_APB_RST_DLY_SHIFT 
-#undef SERDES_L2_TM_RST_DLY_APB_RST_DLY_MASK 
+#undef SERDES_L2_TM_RST_DLY_APB_RST_DLY_DEFVAL
+#undef SERDES_L2_TM_RST_DLY_APB_RST_DLY_SHIFT
+#undef SERDES_L2_TM_RST_DLY_APB_RST_DLY_MASK
 #define SERDES_L2_TM_RST_DLY_APB_RST_DLY_DEFVAL                0x00000000
 #define SERDES_L2_TM_RST_DLY_APB_RST_DLY_SHIFT                 0
 #define SERDES_L2_TM_RST_DLY_APB_RST_DLY_MASK                  0x000000FFU
@@ -32418,9 +32453,9 @@
 /*
 * Enable Bypass for <7> of TM_ANA_BYPS_15
 */
-#undef SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 
-#undef SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 
-#undef SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 
+#undef SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL
+#undef SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT
+#undef SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK
 #define SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL  0x00000000
 #define SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT  6
 #define SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK  0x00000040U
@@ -32428,9 +32463,9 @@
 /*
 * Enable Bypass for <7> of TM_ANA_BYPS_12
 */
-#undef SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 
-#undef SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 
-#undef SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 
+#undef SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL
+#undef SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT
+#undef SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK
 #define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL  0x00000000
 #define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT   6
 #define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK    0x00000040U
@@ -32438,9 +32473,9 @@
 /*
 * Delay apb reset by specified amount
 */
-#undef SERDES_L3_TM_RST_DLY_APB_RST_DLY_DEFVAL 
-#undef SERDES_L3_TM_RST_DLY_APB_RST_DLY_SHIFT 
-#undef SERDES_L3_TM_RST_DLY_APB_RST_DLY_MASK 
+#undef SERDES_L3_TM_RST_DLY_APB_RST_DLY_DEFVAL
+#undef SERDES_L3_TM_RST_DLY_APB_RST_DLY_SHIFT
+#undef SERDES_L3_TM_RST_DLY_APB_RST_DLY_MASK
 #define SERDES_L3_TM_RST_DLY_APB_RST_DLY_DEFVAL                0x00000000
 #define SERDES_L3_TM_RST_DLY_APB_RST_DLY_SHIFT                 0
 #define SERDES_L3_TM_RST_DLY_APB_RST_DLY_MASK                  0x000000FFU
@@ -32448,9 +32483,9 @@
 /*
 * Enable Bypass for <7> of TM_ANA_BYPS_15
 */
-#undef SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 
-#undef SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 
-#undef SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 
+#undef SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL
+#undef SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT
+#undef SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK
 #define SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL  0x00000000
 #define SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT  6
 #define SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK  0x00000040U
@@ -32458,9 +32493,9 @@
 /*
 * Enable Bypass for <7> of TM_ANA_BYPS_12
 */
-#undef SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 
-#undef SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 
-#undef SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 
+#undef SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL
+#undef SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT
+#undef SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK
 #define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL  0x00000000
 #define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT   6
 #define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK    0x00000040U
@@ -32468,9 +32503,9 @@
 /*
 * CDR fast phase lock control
 */
-#undef SERDES_L0_TM_MISC3_CDR_EN_FPL_DEFVAL 
-#undef SERDES_L0_TM_MISC3_CDR_EN_FPL_SHIFT 
-#undef SERDES_L0_TM_MISC3_CDR_EN_FPL_MASK 
+#undef SERDES_L0_TM_MISC3_CDR_EN_FPL_DEFVAL
+#undef SERDES_L0_TM_MISC3_CDR_EN_FPL_SHIFT
+#undef SERDES_L0_TM_MISC3_CDR_EN_FPL_MASK
 #define SERDES_L0_TM_MISC3_CDR_EN_FPL_DEFVAL                   0x00000003
 #define SERDES_L0_TM_MISC3_CDR_EN_FPL_SHIFT                    1
 #define SERDES_L0_TM_MISC3_CDR_EN_FPL_MASK                     0x00000002U
@@ -32478,9 +32513,9 @@
 /*
 * CDR fast frequency lock control
 */
-#undef SERDES_L0_TM_MISC3_CDR_EN_FFL_DEFVAL 
-#undef SERDES_L0_TM_MISC3_CDR_EN_FFL_SHIFT 
-#undef SERDES_L0_TM_MISC3_CDR_EN_FFL_MASK 
+#undef SERDES_L0_TM_MISC3_CDR_EN_FFL_DEFVAL
+#undef SERDES_L0_TM_MISC3_CDR_EN_FFL_SHIFT
+#undef SERDES_L0_TM_MISC3_CDR_EN_FFL_MASK
 #define SERDES_L0_TM_MISC3_CDR_EN_FFL_DEFVAL                   0x00000003
 #define SERDES_L0_TM_MISC3_CDR_EN_FFL_SHIFT                    0
 #define SERDES_L0_TM_MISC3_CDR_EN_FFL_MASK                     0x00000001U
@@ -32488,9 +32523,9 @@
 /*
 * CDR fast phase lock control
 */
-#undef SERDES_L1_TM_MISC3_CDR_EN_FPL_DEFVAL 
-#undef SERDES_L1_TM_MISC3_CDR_EN_FPL_SHIFT 
-#undef SERDES_L1_TM_MISC3_CDR_EN_FPL_MASK 
+#undef SERDES_L1_TM_MISC3_CDR_EN_FPL_DEFVAL
+#undef SERDES_L1_TM_MISC3_CDR_EN_FPL_SHIFT
+#undef SERDES_L1_TM_MISC3_CDR_EN_FPL_MASK
 #define SERDES_L1_TM_MISC3_CDR_EN_FPL_DEFVAL                   0x00000003
 #define SERDES_L1_TM_MISC3_CDR_EN_FPL_SHIFT                    1
 #define SERDES_L1_TM_MISC3_CDR_EN_FPL_MASK                     0x00000002U
@@ -32498,9 +32533,9 @@
 /*
 * CDR fast frequency lock control
 */
-#undef SERDES_L1_TM_MISC3_CDR_EN_FFL_DEFVAL 
-#undef SERDES_L1_TM_MISC3_CDR_EN_FFL_SHIFT 
-#undef SERDES_L1_TM_MISC3_CDR_EN_FFL_MASK 
+#undef SERDES_L1_TM_MISC3_CDR_EN_FFL_DEFVAL
+#undef SERDES_L1_TM_MISC3_CDR_EN_FFL_SHIFT
+#undef SERDES_L1_TM_MISC3_CDR_EN_FFL_MASK
 #define SERDES_L1_TM_MISC3_CDR_EN_FFL_DEFVAL                   0x00000003
 #define SERDES_L1_TM_MISC3_CDR_EN_FFL_SHIFT                    0
 #define SERDES_L1_TM_MISC3_CDR_EN_FFL_MASK                     0x00000001U
@@ -32508,9 +32543,9 @@
 /*
 * CDR fast phase lock control
 */
-#undef SERDES_L2_TM_MISC3_CDR_EN_FPL_DEFVAL 
-#undef SERDES_L2_TM_MISC3_CDR_EN_FPL_SHIFT 
-#undef SERDES_L2_TM_MISC3_CDR_EN_FPL_MASK 
+#undef SERDES_L2_TM_MISC3_CDR_EN_FPL_DEFVAL
+#undef SERDES_L2_TM_MISC3_CDR_EN_FPL_SHIFT
+#undef SERDES_L2_TM_MISC3_CDR_EN_FPL_MASK
 #define SERDES_L2_TM_MISC3_CDR_EN_FPL_DEFVAL                   0x00000003
 #define SERDES_L2_TM_MISC3_CDR_EN_FPL_SHIFT                    1
 #define SERDES_L2_TM_MISC3_CDR_EN_FPL_MASK                     0x00000002U
@@ -32518,9 +32553,9 @@
 /*
 * CDR fast frequency lock control
 */
-#undef SERDES_L2_TM_MISC3_CDR_EN_FFL_DEFVAL 
-#undef SERDES_L2_TM_MISC3_CDR_EN_FFL_SHIFT 
-#undef SERDES_L2_TM_MISC3_CDR_EN_FFL_MASK 
+#undef SERDES_L2_TM_MISC3_CDR_EN_FFL_DEFVAL
+#undef SERDES_L2_TM_MISC3_CDR_EN_FFL_SHIFT
+#undef SERDES_L2_TM_MISC3_CDR_EN_FFL_MASK
 #define SERDES_L2_TM_MISC3_CDR_EN_FFL_DEFVAL                   0x00000003
 #define SERDES_L2_TM_MISC3_CDR_EN_FFL_SHIFT                    0
 #define SERDES_L2_TM_MISC3_CDR_EN_FFL_MASK                     0x00000001U
@@ -32528,9 +32563,9 @@
 /*
 * CDR fast phase lock control
 */
-#undef SERDES_L3_TM_MISC3_CDR_EN_FPL_DEFVAL 
-#undef SERDES_L3_TM_MISC3_CDR_EN_FPL_SHIFT 
-#undef SERDES_L3_TM_MISC3_CDR_EN_FPL_MASK 
+#undef SERDES_L3_TM_MISC3_CDR_EN_FPL_DEFVAL
+#undef SERDES_L3_TM_MISC3_CDR_EN_FPL_SHIFT
+#undef SERDES_L3_TM_MISC3_CDR_EN_FPL_MASK
 #define SERDES_L3_TM_MISC3_CDR_EN_FPL_DEFVAL                   0x00000003
 #define SERDES_L3_TM_MISC3_CDR_EN_FPL_SHIFT                    1
 #define SERDES_L3_TM_MISC3_CDR_EN_FPL_MASK                     0x00000002U
@@ -32538,9 +32573,9 @@
 /*
 * CDR fast frequency lock control
 */
-#undef SERDES_L3_TM_MISC3_CDR_EN_FFL_DEFVAL 
-#undef SERDES_L3_TM_MISC3_CDR_EN_FFL_SHIFT 
-#undef SERDES_L3_TM_MISC3_CDR_EN_FFL_MASK 
+#undef SERDES_L3_TM_MISC3_CDR_EN_FFL_DEFVAL
+#undef SERDES_L3_TM_MISC3_CDR_EN_FFL_SHIFT
+#undef SERDES_L3_TM_MISC3_CDR_EN_FFL_MASK
 #define SERDES_L3_TM_MISC3_CDR_EN_FFL_DEFVAL                   0x00000003
 #define SERDES_L3_TM_MISC3_CDR_EN_FFL_SHIFT                    0
 #define SERDES_L3_TM_MISC3_CDR_EN_FFL_MASK                     0x00000001U
@@ -32548,9 +32583,9 @@
 /*
 * Force EQ offset correction algo off if not forced on
 */
-#undef SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL 
-#undef SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT 
-#undef SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK 
+#undef SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL
+#undef SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT
+#undef SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK
 #define SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL             0x00000000
 #define SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT              4
 #define SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK               0x00000010U
@@ -32558,9 +32593,9 @@
 /*
 * Force EQ offset correction algo off if not forced on
 */
-#undef SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL 
-#undef SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT 
-#undef SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK 
+#undef SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL
+#undef SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT
+#undef SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK
 #define SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL             0x00000000
 #define SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT              4
 #define SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK               0x00000010U
@@ -32568,9 +32603,9 @@
 /*
 * Force EQ offset correction algo off if not forced on
 */
-#undef SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL 
-#undef SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT 
-#undef SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK 
+#undef SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL
+#undef SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT
+#undef SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK
 #define SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL             0x00000000
 #define SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT              4
 #define SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK               0x00000010U
@@ -32578,9 +32613,9 @@
 /*
 * Force EQ offset correction algo off if not forced on
 */
-#undef SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL 
-#undef SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT 
-#undef SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK 
+#undef SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL
+#undef SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT
+#undef SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK
 #define SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL             0x00000000
 #define SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT              4
 #define SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK               0x00000010U
@@ -32589,9 +32624,9 @@
 * Controls UPHY Lane 0 protocol configuration. 0 - PowerDown, 1 - PCIe .0,
     *  2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII0, 6 - Unused, 7 - Unused
 */
-#undef SERDES_ICM_CFG0_L0_ICM_CFG_DEFVAL 
-#undef SERDES_ICM_CFG0_L0_ICM_CFG_SHIFT 
-#undef SERDES_ICM_CFG0_L0_ICM_CFG_MASK 
+#undef SERDES_ICM_CFG0_L0_ICM_CFG_DEFVAL
+#undef SERDES_ICM_CFG0_L0_ICM_CFG_SHIFT
+#undef SERDES_ICM_CFG0_L0_ICM_CFG_MASK
 #define SERDES_ICM_CFG0_L0_ICM_CFG_DEFVAL                      0x00000000
 #define SERDES_ICM_CFG0_L0_ICM_CFG_SHIFT                       0
 #define SERDES_ICM_CFG0_L0_ICM_CFG_MASK                        0x00000007U
@@ -32600,9 +32635,9 @@
 * Controls UPHY Lane 1 protocol configuration. 0 - PowerDown, 1 - PCIe.1,
     * 2 - Sata1, 3 - USB0, 4 - DP.0, 5 - SGMII1, 6 - Unused, 7 - Unused
 */
-#undef SERDES_ICM_CFG0_L1_ICM_CFG_DEFVAL 
-#undef SERDES_ICM_CFG0_L1_ICM_CFG_SHIFT 
-#undef SERDES_ICM_CFG0_L1_ICM_CFG_MASK 
+#undef SERDES_ICM_CFG0_L1_ICM_CFG_DEFVAL
+#undef SERDES_ICM_CFG0_L1_ICM_CFG_SHIFT
+#undef SERDES_ICM_CFG0_L1_ICM_CFG_MASK
 #define SERDES_ICM_CFG0_L1_ICM_CFG_DEFVAL                      0x00000000
 #define SERDES_ICM_CFG0_L1_ICM_CFG_SHIFT                       4
 #define SERDES_ICM_CFG0_L1_ICM_CFG_MASK                        0x00000070U
@@ -32611,9 +32646,9 @@
 * Controls UPHY Lane 2 protocol configuration. 0 - PowerDown, 1 - PCIe.1,
     * 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII2, 6 - Unused, 7 - Unused
 */
-#undef SERDES_ICM_CFG1_L2_ICM_CFG_DEFVAL 
-#undef SERDES_ICM_CFG1_L2_ICM_CFG_SHIFT 
-#undef SERDES_ICM_CFG1_L2_ICM_CFG_MASK 
+#undef SERDES_ICM_CFG1_L2_ICM_CFG_DEFVAL
+#undef SERDES_ICM_CFG1_L2_ICM_CFG_SHIFT
+#undef SERDES_ICM_CFG1_L2_ICM_CFG_MASK
 #define SERDES_ICM_CFG1_L2_ICM_CFG_DEFVAL                      0x00000000
 #define SERDES_ICM_CFG1_L2_ICM_CFG_SHIFT                       0
 #define SERDES_ICM_CFG1_L2_ICM_CFG_MASK                        0x00000007U
@@ -32622,9 +32657,9 @@
 * Controls UPHY Lane 3 protocol configuration. 0 - PowerDown, 1 - PCIe.3,
     * 2 - Sata1, 3 - USB1, 4 - DP.0, 5 - SGMII3, 6 - Unused, 7 - Unused
 */
-#undef SERDES_ICM_CFG1_L3_ICM_CFG_DEFVAL 
-#undef SERDES_ICM_CFG1_L3_ICM_CFG_SHIFT 
-#undef SERDES_ICM_CFG1_L3_ICM_CFG_MASK 
+#undef SERDES_ICM_CFG1_L3_ICM_CFG_DEFVAL
+#undef SERDES_ICM_CFG1_L3_ICM_CFG_SHIFT
+#undef SERDES_ICM_CFG1_L3_ICM_CFG_MASK
 #define SERDES_ICM_CFG1_L3_ICM_CFG_DEFVAL                      0x00000000
 #define SERDES_ICM_CFG1_L3_ICM_CFG_SHIFT                       4
 #define SERDES_ICM_CFG1_L3_ICM_CFG_MASK                        0x00000070U
@@ -32632,9 +32667,9 @@
 /*
 * Enable/disable DP post2 path
 */
-#undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_DEFVAL 
-#undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT 
-#undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK 
+#undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_DEFVAL
+#undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT
+#undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK
 #define SERDES_L0_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_DEFVAL  0x00000000
 #define SERDES_L0_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT  5
 #define SERDES_L0_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK  0x00000020U
@@ -32642,9 +32677,9 @@
 /*
 * Override enable/disable of DP post2 path
 */
-#undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_DEFVAL 
-#undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT 
-#undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK 
+#undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_DEFVAL
+#undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT
+#undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK
 #define SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_DEFVAL  0x00000000
 #define SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT  4
 #define SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK  0x00000010U
@@ -32652,9 +32687,9 @@
 /*
 * Override enable/disable of DP post1 path
 */
-#undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_DEFVAL 
-#undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT 
-#undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK 
+#undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_DEFVAL
+#undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT
+#undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK
 #define SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_DEFVAL  0x00000000
 #define SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT  2
 #define SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK  0x00000004U
@@ -32662,9 +32697,9 @@
 /*
 * Enable/disable DP main path
 */
-#undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_DEFVAL 
-#undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT 
-#undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK 
+#undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_DEFVAL
+#undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT
+#undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK
 #define SERDES_L0_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_DEFVAL  0x00000000
 #define SERDES_L0_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT  1
 #define SERDES_L0_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK  0x00000002U
@@ -32672,9 +32707,9 @@
 /*
 * Override enable/disable of DP main path
 */
-#undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_DEFVAL 
-#undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT 
-#undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK 
+#undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_DEFVAL
+#undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT
+#undef SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK
 #define SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_DEFVAL  0x00000000
 #define SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT  0
 #define SERDES_L0_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK  0x00000001U
@@ -32682,9 +32717,9 @@
 /*
 * Enable/disable DP post2 path
 */
-#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_DEFVAL 
-#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT 
-#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK 
+#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_DEFVAL
+#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT
+#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK
 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_DEFVAL  0x00000000
 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT  5
 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK  0x00000020U
@@ -32692,9 +32727,9 @@
 /*
 * Override enable/disable of DP post2 path
 */
-#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_DEFVAL 
-#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT 
-#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK 
+#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_DEFVAL
+#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT
+#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK
 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_DEFVAL  0x00000000
 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT  4
 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK  0x00000010U
@@ -32702,9 +32737,9 @@
 /*
 * Override enable/disable of DP post1 path
 */
-#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_DEFVAL 
-#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT 
-#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK 
+#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_DEFVAL
+#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT
+#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK
 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_DEFVAL  0x00000000
 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT  2
 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK  0x00000004U
@@ -32712,9 +32747,9 @@
 /*
 * Enable/disable DP main path
 */
-#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_DEFVAL 
-#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT 
-#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK 
+#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_DEFVAL
+#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT
+#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK
 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_DEFVAL  0x00000000
 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT  1
 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK  0x00000002U
@@ -32722,9 +32757,9 @@
 /*
 * Override enable/disable of DP main path
 */
-#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_DEFVAL 
-#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT 
-#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK 
+#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_DEFVAL
+#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT
+#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK
 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_DEFVAL  0x00000000
 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT  0
 #define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK  0x00000001U
@@ -32732,9 +32767,9 @@
 /*
 * Test register force for enabling/disablign TX deemphasis bits <17:0>
 */
-#undef SERDES_L0_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL 
-#undef SERDES_L0_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT 
-#undef SERDES_L0_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK 
+#undef SERDES_L0_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL
+#undef SERDES_L0_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT
+#undef SERDES_L0_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK
 #define SERDES_L0_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL    0x00000000
 #define SERDES_L0_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT     0
 #define SERDES_L0_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK      0x00000001U
@@ -32742,9 +32777,9 @@
 /*
 * Test register force for enabling/disablign TX deemphasis bits <17:0>
 */
-#undef SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL 
-#undef SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT 
-#undef SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK 
+#undef SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL
+#undef SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT
+#undef SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK
 #define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL    0x00000000
 #define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT     0
 #define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK      0x00000001U
@@ -32752,9 +32787,9 @@
 /*
 * Test register force for enabling/disablign TX deemphasis bits <17:0>
 */
-#undef SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL 
-#undef SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT 
-#undef SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK 
+#undef SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL
+#undef SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT
+#undef SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK
 #define SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL    0x00000000
 #define SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT     0
 #define SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK      0x00000001U
@@ -32762,9 +32797,9 @@
 /*
 * FPHL FSM accumulate cycles
 */
-#undef SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_DEFVAL 
-#undef SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_SHIFT 
-#undef SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_MASK 
+#undef SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_DEFVAL
+#undef SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_SHIFT
+#undef SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_MASK
 #define SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_DEFVAL           0x00000000
 #define SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_SHIFT            5
 #define SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_MASK             0x000000E0U
@@ -32772,9 +32807,9 @@
 /*
 * FFL Phase0 int gain aka 2ol SD update rate
 */
-#undef SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_DEFVAL 
-#undef SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_SHIFT 
-#undef SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_MASK 
+#undef SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_DEFVAL
+#undef SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_SHIFT
+#undef SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_MASK
 #define SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_DEFVAL              0x00000000
 #define SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_SHIFT               0
 #define SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_MASK                0x0000001FU
@@ -32782,9 +32817,9 @@
 /*
 * FFL Phase0 prop gain aka 1ol SD update rate
 */
-#undef SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_DEFVAL 
-#undef SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_SHIFT 
-#undef SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_MASK 
+#undef SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_DEFVAL
+#undef SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_SHIFT
+#undef SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_MASK
 #define SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_DEFVAL            0x00000000
 #define SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_SHIFT             0
 #define SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_MASK              0x0000001FU
@@ -32792,9 +32827,9 @@
 /*
 * EQ stg 2 controls BYPASSED
 */
-#undef SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_DEFVAL 
-#undef SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_SHIFT 
-#undef SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_MASK 
+#undef SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_DEFVAL
+#undef SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_SHIFT
+#undef SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_MASK
 #define SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_DEFVAL               0x00000000
 #define SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_SHIFT                5
 #define SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_MASK                 0x00000020U
@@ -32802,9 +32837,9 @@
 /*
 * EQ STG2 RL PROG
 */
-#undef SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_DEFVAL 
-#undef SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_SHIFT 
-#undef SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_MASK 
+#undef SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_DEFVAL
+#undef SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_SHIFT
+#undef SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_MASK
 #define SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_DEFVAL                0x00000000
 #define SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_SHIFT                 0
 #define SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_MASK                  0x00000003U
@@ -32812,9 +32847,9 @@
 /*
 * EQ stg 2 preamp mode val
 */
-#undef SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_DEFVAL 
-#undef SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_SHIFT 
-#undef SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_MASK 
+#undef SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_DEFVAL
+#undef SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_SHIFT
+#undef SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_MASK
 #define SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_DEFVAL        0x00000000
 #define SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_SHIFT         2
 #define SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_MASK          0x00000004U
@@ -32822,9 +32857,9 @@
 /*
 * Margining factor value
 */
-#undef SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_DEFVAL 
-#undef SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT 
-#undef SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_MASK 
+#undef SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_DEFVAL
+#undef SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT
+#undef SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_MASK
 #define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_DEFVAL  0x00000000
 #define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT  0
 #define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_MASK  0x0000001FU
@@ -32832,9 +32867,9 @@
 /*
 * Margining factor value
 */
-#undef SERDES_L0_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_DEFVAL 
-#undef SERDES_L0_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT 
-#undef SERDES_L0_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_MASK 
+#undef SERDES_L0_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_DEFVAL
+#undef SERDES_L0_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT
+#undef SERDES_L0_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_MASK
 #define SERDES_L0_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_DEFVAL  0x00000000
 #define SERDES_L0_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT  0
 #define SERDES_L0_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_MASK  0x0000001FU
@@ -32843,9 +32878,9 @@
 * pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-em
     * phasis, Others: reserved
 */
-#undef SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL 
-#undef SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT 
-#undef SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK 
+#undef SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL
+#undef SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT
+#undef SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK
 #define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL       0x00000002
 #define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT        0
 #define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK         0x000000FFU
@@ -32854,9 +32889,9 @@
 * pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-em
     * phasis, Others: reserved
 */
-#undef SERDES_L0_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL 
-#undef SERDES_L0_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT 
-#undef SERDES_L0_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK 
+#undef SERDES_L0_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL
+#undef SERDES_L0_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT
+#undef SERDES_L0_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK
 #define SERDES_L0_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL       0x00000002
 #define SERDES_L0_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT        0
 #define SERDES_L0_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK         0x000000FFU
@@ -32865,57 +32900,57 @@
 * pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-em
     * phasis, Others: reserved
 */
-#undef SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL 
-#undef SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT 
-#undef SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK 
+#undef SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL
+#undef SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT
+#undef SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK
 #define SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL       0x00000002
 #define SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT        0
 #define SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK         0x000000FFU
-#undef CRL_APB_RST_LPD_TOP_OFFSET 
+#undef CRL_APB_RST_LPD_TOP_OFFSET
 #define CRL_APB_RST_LPD_TOP_OFFSET                                                 0XFF5E023C
-#undef USB3_0_FPD_POWER_PRSNT_OFFSET 
+#undef USB3_0_FPD_POWER_PRSNT_OFFSET
 #define USB3_0_FPD_POWER_PRSNT_OFFSET                                              0XFF9D0080
-#undef USB3_0_FPD_PIPE_CLK_OFFSET 
+#undef USB3_0_FPD_PIPE_CLK_OFFSET
 #define USB3_0_FPD_PIPE_CLK_OFFSET                                                 0XFF9D007C
-#undef CRL_APB_RST_LPD_TOP_OFFSET 
+#undef CRL_APB_RST_LPD_TOP_OFFSET
 #define CRL_APB_RST_LPD_TOP_OFFSET                                                 0XFF5E023C
-#undef CRL_APB_RST_LPD_IOU0_OFFSET 
+#undef CRL_APB_RST_LPD_IOU0_OFFSET
 #define CRL_APB_RST_LPD_IOU0_OFFSET                                                0XFF5E0230
-#undef SIOU_SATA_MISC_CTRL_OFFSET 
+#undef SIOU_SATA_MISC_CTRL_OFFSET
 #define SIOU_SATA_MISC_CTRL_OFFSET                                                 0XFD3D0100
-#undef CRF_APB_RST_FPD_TOP_OFFSET 
+#undef CRF_APB_RST_FPD_TOP_OFFSET
 #define CRF_APB_RST_FPD_TOP_OFFSET                                                 0XFD1A0100
-#undef CRF_APB_RST_FPD_TOP_OFFSET 
+#undef CRF_APB_RST_FPD_TOP_OFFSET
 #define CRF_APB_RST_FPD_TOP_OFFSET                                                 0XFD1A0100
-#undef DP_DP_PHY_RESET_OFFSET 
+#undef DP_DP_PHY_RESET_OFFSET
 #define DP_DP_PHY_RESET_OFFSET                                                     0XFD4A0200
-#undef DP_DP_TX_PHY_POWER_DOWN_OFFSET 
+#undef DP_DP_TX_PHY_POWER_DOWN_OFFSET
 #define DP_DP_TX_PHY_POWER_DOWN_OFFSET                                             0XFD4A0238
-#undef USB3_0_XHCI_GUSB2PHYCFG_OFFSET 
+#undef USB3_0_XHCI_GUSB2PHYCFG_OFFSET
 #define USB3_0_XHCI_GUSB2PHYCFG_OFFSET                                             0XFE20C200
-#undef USB3_0_XHCI_GFLADJ_OFFSET 
+#undef USB3_0_XHCI_GFLADJ_OFFSET
 #define USB3_0_XHCI_GFLADJ_OFFSET                                                  0XFE20C630
-#undef USB3_0_XHCI_GUCTL1_OFFSET 
+#undef USB3_0_XHCI_GUCTL1_OFFSET
 #define USB3_0_XHCI_GUCTL1_OFFSET                                                  0XFE20C11C
-#undef USB3_0_XHCI_GUCTL_OFFSET 
+#undef USB3_0_XHCI_GUCTL_OFFSET
 #define USB3_0_XHCI_GUCTL_OFFSET                                                   0XFE20C12C
-#undef PCIE_ATTRIB_ATTR_25_OFFSET 
+#undef PCIE_ATTRIB_ATTR_25_OFFSET
 #define PCIE_ATTRIB_ATTR_25_OFFSET                                                 0XFD480064
-#undef SATA_AHCI_VENDOR_PP2C_OFFSET 
+#undef SATA_AHCI_VENDOR_PP2C_OFFSET
 #define SATA_AHCI_VENDOR_PP2C_OFFSET                                               0XFD0C00AC
-#undef SATA_AHCI_VENDOR_PP3C_OFFSET 
+#undef SATA_AHCI_VENDOR_PP3C_OFFSET
 #define SATA_AHCI_VENDOR_PP3C_OFFSET                                               0XFD0C00B0
-#undef SATA_AHCI_VENDOR_PP4C_OFFSET 
+#undef SATA_AHCI_VENDOR_PP4C_OFFSET
 #define SATA_AHCI_VENDOR_PP4C_OFFSET                                               0XFD0C00B4
-#undef SATA_AHCI_VENDOR_PP5C_OFFSET 
+#undef SATA_AHCI_VENDOR_PP5C_OFFSET
 #define SATA_AHCI_VENDOR_PP5C_OFFSET                                               0XFD0C00B8
 
 /*
 * USB 0 reset for control registers
 */
-#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL 
-#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT 
-#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK 
+#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL
+#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT
+#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK
 #define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL              0x00188FDF
 #define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT               10
 #define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK                0x00000400U
@@ -32923,10 +32958,10 @@
 /*
 * This bit is used to choose between PIPE power present and 1'b1
 */
-#undef USB3_0_FPD_POWER_PRSNT_OPTION_DEFVAL 
-#undef USB3_0_FPD_POWER_PRSNT_OPTION_SHIFT 
-#undef USB3_0_FPD_POWER_PRSNT_OPTION_MASK 
-#define USB3_0_FPD_POWER_PRSNT_OPTION_DEFVAL                   
+#undef USB3_0_FPD_POWER_PRSNT_OPTION_DEFVAL
+#undef USB3_0_FPD_POWER_PRSNT_OPTION_SHIFT
+#undef USB3_0_FPD_POWER_PRSNT_OPTION_MASK
+#define USB3_0_FPD_POWER_PRSNT_OPTION_DEFVAL
 #define USB3_0_FPD_POWER_PRSNT_OPTION_SHIFT                    0
 #define USB3_0_FPD_POWER_PRSNT_OPTION_MASK                     0x00000001U
 
@@ -32934,19 +32969,19 @@
 * This bit is used to choose between PIPE clock coming from SerDes and the
     *  suspend clk
 */
-#undef USB3_0_FPD_PIPE_CLK_OPTION_DEFVAL 
-#undef USB3_0_FPD_PIPE_CLK_OPTION_SHIFT 
-#undef USB3_0_FPD_PIPE_CLK_OPTION_MASK 
-#define USB3_0_FPD_PIPE_CLK_OPTION_DEFVAL                      
+#undef USB3_0_FPD_PIPE_CLK_OPTION_DEFVAL
+#undef USB3_0_FPD_PIPE_CLK_OPTION_SHIFT
+#undef USB3_0_FPD_PIPE_CLK_OPTION_MASK
+#define USB3_0_FPD_PIPE_CLK_OPTION_DEFVAL
 #define USB3_0_FPD_PIPE_CLK_OPTION_SHIFT                       0
 #define USB3_0_FPD_PIPE_CLK_OPTION_MASK                        0x00000001U
 
 /*
 * USB 0 sleep circuit reset
 */
-#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL 
-#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT 
-#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK 
+#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL
+#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT
+#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK
 #define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL             0x00188FDF
 #define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT              8
 #define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK               0x00000100U
@@ -32954,9 +32989,9 @@
 /*
 * USB 0 reset
 */
-#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL 
-#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 
-#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK 
+#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL
+#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT
+#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK
 #define CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL              0x00188FDF
 #define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT               6
 #define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK                0x00000040U
@@ -32964,9 +32999,9 @@
 /*
 * GEM 3 reset
 */
-#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL 
-#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT 
-#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK 
+#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL
+#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT
+#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK
 #define CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL                 0x0000000F
 #define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT                  3
 #define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK                   0x00000008U
@@ -32974,19 +33009,19 @@
 /*
 * Sata PM clock control select
 */
-#undef SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_DEFVAL 
-#undef SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_SHIFT 
-#undef SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_MASK 
-#define SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_DEFVAL             
+#undef SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_DEFVAL
+#undef SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_SHIFT
+#undef SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_MASK
+#define SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_DEFVAL
 #define SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_SHIFT              0
 #define SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_MASK               0x00000003U
 
 /*
 * Sata block level reset
 */
-#undef CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL 
-#undef CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT 
-#undef CRF_APB_RST_FPD_TOP_SATA_RESET_MASK 
+#undef CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL
+#undef CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT
+#undef CRF_APB_RST_FPD_TOP_SATA_RESET_MASK
 #define CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL                  0x000F9FFE
 #define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT                   1
 #define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK                    0x00000002U
@@ -32994,9 +33029,9 @@
 /*
 * Display Port block level reset (includes DPDMA)
 */
-#undef CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL 
-#undef CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT 
-#undef CRF_APB_RST_FPD_TOP_DP_RESET_MASK 
+#undef CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL
+#undef CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT
+#undef CRF_APB_RST_FPD_TOP_DP_RESET_MASK
 #define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL                    0x000F9FFE
 #define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT                     16
 #define CRF_APB_RST_FPD_TOP_DP_RESET_MASK                      0x00010000U
@@ -33004,9 +33039,9 @@
 /*
 * Set to '1' to hold the GT in reset. Clear to release.
 */
-#undef DP_DP_PHY_RESET_GT_RESET_DEFVAL 
-#undef DP_DP_PHY_RESET_GT_RESET_SHIFT 
-#undef DP_DP_PHY_RESET_GT_RESET_MASK 
+#undef DP_DP_PHY_RESET_GT_RESET_DEFVAL
+#undef DP_DP_PHY_RESET_GT_RESET_SHIFT
+#undef DP_DP_PHY_RESET_GT_RESET_MASK
 #define DP_DP_PHY_RESET_GT_RESET_DEFVAL                        0x00010003
 #define DP_DP_PHY_RESET_GT_RESET_SHIFT                         1
 #define DP_DP_PHY_RESET_GT_RESET_MASK                          0x00000002U
@@ -33016,9 +33051,9 @@
     *  set to 00, GT will be in active state. bits [1:0] - lane0 Bits [3:2] -
     * lane 1
 */
-#undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL 
-#undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT 
-#undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK 
+#undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL
+#undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT
+#undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK
 #define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL               0x00000000
 #define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT                0
 #define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK                 0x0000000FU
@@ -33035,9 +33070,9 @@
     * e is not critical, this field can be set to a larger value. Note: This f
     * ield is valid only in device mode.
 */
-#undef USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_DEFVAL 
-#undef USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_SHIFT 
-#undef USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_MASK 
+#undef USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_DEFVAL
+#undef USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_SHIFT
+#undef USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_MASK
 #define USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_DEFVAL               0x00000000
 #define USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_SHIFT                10
 #define USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_MASK                 0x00003C00U
@@ -33054,9 +33089,9 @@
     * the core does not save and restore this bit value during hibernation. -
     * This bit is valid only in device mode.
 */
-#undef USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_DEFVAL 
-#undef USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_SHIFT 
-#undef USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_MASK 
+#undef USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_DEFVAL
+#undef USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_SHIFT
+#undef USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_MASK
 #define USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_DEFVAL                 0x00000000
 #define USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_SHIFT                  9
 #define USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_MASK                   0x00000200U
@@ -33074,9 +33109,9 @@
     * he device is in L1 state and if mac2_clk (utmi_clk/ulpi_clk) is gated of
     * f, the command will not get completed.
 */
-#undef USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_DEFVAL 
-#undef USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_SHIFT 
-#undef USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_MASK 
+#undef USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_DEFVAL
+#undef USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_SHIFT
+#undef USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_MASK
 #define USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_DEFVAL                0x00000000
 #define USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_SHIFT                 8
 #define USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_MASK                  0x00000100U
@@ -33092,9 +33127,9 @@
     *  active, with Read-Write bit access. Note: USB 1.1 full-serial transceiv
     * er is not supported. This bit always reads as 1'b0.
 */
-#undef USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_DEFVAL 
-#undef USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_SHIFT 
-#undef USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_MASK 
+#undef USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_DEFVAL
+#undef USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_SHIFT
+#undef USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_MASK
 #define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_DEFVAL                  0x00000000
 #define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_SHIFT                   7
 #define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_MASK                    0x00000080U
@@ -33114,9 +33149,9 @@
     * if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get c
     * ompleted.
 */
-#undef USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_DEFVAL 
-#undef USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_SHIFT 
-#undef USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_MASK 
+#undef USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_DEFVAL
+#undef USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_SHIFT
+#undef USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_MASK
 #define USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_DEFVAL            0x00000000
 #define USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_SHIFT             6
 #define USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_MASK              0x00000040U
@@ -33130,9 +33165,9 @@
     * y access. Note: USB 1.1 full-speed serial interface is not supported. Th
     * is bit always reads as 1'b0.
 */
-#undef USB3_0_XHCI_GUSB2PHYCFG_FSINTF_DEFVAL 
-#undef USB3_0_XHCI_GUSB2PHYCFG_FSINTF_SHIFT 
-#undef USB3_0_XHCI_GUSB2PHYCFG_FSINTF_MASK 
+#undef USB3_0_XHCI_GUSB2PHYCFG_FSINTF_DEFVAL
+#undef USB3_0_XHCI_GUSB2PHYCFG_FSINTF_SHIFT
+#undef USB3_0_XHCI_GUSB2PHYCFG_FSINTF_MASK
 #define USB3_0_XHCI_GUSB2PHYCFG_FSINTF_DEFVAL                  0x00000000
 #define USB3_0_XHCI_GUSB2PHYCFG_FSINTF_SHIFT                   5
 #define USB3_0_XHCI_GUSB2PHYCFG_FSINTF_MASK                    0x00000020U
@@ -33145,9 +33180,9 @@
     * INTERFACE = 3). Otherwise, this bit is read-only and the value depends o
     * n the interface selected through DWC_USB3_HSPHY_INTERFACE.
 */
-#undef USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_DEFVAL 
-#undef USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_SHIFT 
-#undef USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_MASK 
+#undef USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_DEFVAL
+#undef USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_SHIFT
+#undef USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_MASK
 #define USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_DEFVAL           0x00000000
 #define USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_SHIFT            4
 #define USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_MASK             0x00000010U
@@ -33163,9 +33198,9 @@
     *  any of the USB 2.0 ports is selected as ULPI port for operation, then a
     * ll the USB 2.0 ports must be operating at 60 MHz.
 */
-#undef USB3_0_XHCI_GUSB2PHYCFG_PHYIF_DEFVAL 
-#undef USB3_0_XHCI_GUSB2PHYCFG_PHYIF_SHIFT 
-#undef USB3_0_XHCI_GUSB2PHYCFG_PHYIF_MASK 
+#undef USB3_0_XHCI_GUSB2PHYCFG_PHYIF_DEFVAL
+#undef USB3_0_XHCI_GUSB2PHYCFG_PHYIF_SHIFT
+#undef USB3_0_XHCI_GUSB2PHYCFG_PHYIF_MASK
 #define USB3_0_XHCI_GUSB2PHYCFG_PHYIF_DEFVAL                   0x00000000
 #define USB3_0_XHCI_GUSB2PHYCFG_PHYIF_SHIFT                    3
 #define USB3_0_XHCI_GUSB2PHYCFG_PHYIF_MASK                     0x00000008U
@@ -33186,9 +33221,9 @@
     * 4 bit times - One 60-MHz PHY clock = 0.2 bit times - One 48-MHz PHY cloc
     * k = 0.25 bit times
 */
-#undef USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_DEFVAL 
-#undef USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_SHIFT 
-#undef USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_MASK 
+#undef USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_DEFVAL
+#undef USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_SHIFT
+#undef USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_MASK
 #define USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_DEFVAL                 0x00000000
 #define USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_SHIFT                  0
 #define USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_MASK                   0x00000007U
@@ -33199,9 +33234,9 @@
     * ge pump (default). - 1'b1: PHY drives VBUS with an external supply. (Onl
     * y when RTL parameter DWC_USB3_HSPHY_INTERFACE = 2 or 3)
 */
-#undef USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV_DEFVAL 
-#undef USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV_SHIFT 
-#undef USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV_MASK 
+#undef USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV_DEFVAL
+#undef USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV_SHIFT
+#undef USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV_MASK
 #define USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV_DEFVAL          0x00000000
 #define USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV_SHIFT           17
 #define USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV_MASK            0x00020000U
@@ -33224,9 +33259,9 @@
     * RIOD = 20 - GFLADJ.GLADJ_REFCLK_FLADJ = ((125000/20)-(125000/20.8333))*2
     * 0.8333 = 5208 (ignoring the fractional value)
 */
-#undef USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_DEFVAL 
-#undef USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT 
-#undef USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK 
+#undef USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_DEFVAL
+#undef USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT
+#undef USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK
 #define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_DEFVAL          0x00000000
 #define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT           8
 #define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK            0x003FFF00U
@@ -33238,9 +33273,9 @@
     * is bit is set to '1', all the termsel, xcvrsel, opmode becomes 0 during
     * end of resume itself (only 1 command will be issued)
 */
-#undef USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY_DEFVAL 
-#undef USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY_SHIFT 
-#undef USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY_MASK 
+#undef USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY_DEFVAL
+#undef USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY_SHIFT
+#undef USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY_MASK
 #define USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY_DEFVAL  0x00000000
 #define USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY_SHIFT  10
 #define USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY_MASK   0x00000400U
@@ -33248,9 +33283,9 @@
 /*
 * Reserved
 */
-#undef USB3_0_XHCI_GUCTL1_RESERVED_9_DEFVAL 
-#undef USB3_0_XHCI_GUCTL1_RESERVED_9_SHIFT 
-#undef USB3_0_XHCI_GUCTL1_RESERVED_9_MASK 
+#undef USB3_0_XHCI_GUCTL1_RESERVED_9_DEFVAL
+#undef USB3_0_XHCI_GUCTL1_RESERVED_9_SHIFT
+#undef USB3_0_XHCI_GUCTL1_RESERVED_9_MASK
 #define USB3_0_XHCI_GUCTL1_RESERVED_9_DEFVAL                   0x00000000
 #define USB3_0_XHCI_GUCTL1_RESERVED_9_SHIFT                    9
 #define USB3_0_XHCI_GUCTL1_RESERVED_9_MASK                     0x00000200U
@@ -33266,9 +33301,9 @@
     * et with Retry = 1 and NumP = 0). - 1'b0: Auto Retry Disabled - 1'b1: Aut
     * o Retry Enabled Note: This bit is also applicable to the device mode.
 */
-#undef USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN_DEFVAL 
-#undef USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN_SHIFT 
-#undef USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN_MASK 
+#undef USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN_DEFVAL
+#undef USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN_SHIFT
+#undef USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN_MASK
 #define USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN_DEFVAL           0x00000000
 #define USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN_SHIFT            14
 #define USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN_MASK             0x00004000U
@@ -33278,9 +33313,9 @@
     * TRUE for Endpoint and either setting allowed for Root ports. Drives Devi
     * ce Capability 2 [4]; EP=0x0001; RP=0x0001
 */
-#undef PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_DEFVAL 
-#undef PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_SHIFT 
-#undef PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_MASK 
+#undef PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_DEFVAL
+#undef PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_SHIFT
+#undef PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_MASK
 #define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_DEFVAL  0x00000905
 #define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_SHIFT  9
 #define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_MASK  0x00000200U
@@ -33288,9 +33323,9 @@
 /*
 * Status Read value of PLL Lock
 */
-#undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 
-#undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 
-#undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 
+#undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL
+#undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT
+#undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK
 #define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL  0x00000001
 #define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT  4
 #define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK  0x00000010U
@@ -33299,9 +33334,9 @@
 /*
 * Status Read value of PLL Lock
 */
-#undef SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 
-#undef SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 
-#undef SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 
+#undef SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL
+#undef SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT
+#undef SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK
 #define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL  0x00000001
 #define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT  4
 #define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK  0x00000010U
@@ -33310,9 +33345,9 @@
 /*
 * Status Read value of PLL Lock
 */
-#undef SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 
-#undef SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 
-#undef SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 
+#undef SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL
+#undef SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT
+#undef SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK
 #define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL  0x00000001
 #define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT  4
 #define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK  0x00000010U
@@ -33321,9 +33356,9 @@
 /*
 * CIBGMN: COMINIT Burst Gap Minimum.
 */
-#undef SATA_AHCI_VENDOR_PP2C_CIBGMN_DEFVAL 
-#undef SATA_AHCI_VENDOR_PP2C_CIBGMN_SHIFT 
-#undef SATA_AHCI_VENDOR_PP2C_CIBGMN_MASK 
+#undef SATA_AHCI_VENDOR_PP2C_CIBGMN_DEFVAL
+#undef SATA_AHCI_VENDOR_PP2C_CIBGMN_SHIFT
+#undef SATA_AHCI_VENDOR_PP2C_CIBGMN_MASK
 #define SATA_AHCI_VENDOR_PP2C_CIBGMN_DEFVAL                    0x28184D1B
 #define SATA_AHCI_VENDOR_PP2C_CIBGMN_SHIFT                     0
 #define SATA_AHCI_VENDOR_PP2C_CIBGMN_MASK                      0x000000FFU
@@ -33331,9 +33366,9 @@
 /*
 * CIBGMX: COMINIT Burst Gap Maximum.
 */
-#undef SATA_AHCI_VENDOR_PP2C_CIBGMX_DEFVAL 
-#undef SATA_AHCI_VENDOR_PP2C_CIBGMX_SHIFT 
-#undef SATA_AHCI_VENDOR_PP2C_CIBGMX_MASK 
+#undef SATA_AHCI_VENDOR_PP2C_CIBGMX_DEFVAL
+#undef SATA_AHCI_VENDOR_PP2C_CIBGMX_SHIFT
+#undef SATA_AHCI_VENDOR_PP2C_CIBGMX_MASK
 #define SATA_AHCI_VENDOR_PP2C_CIBGMX_DEFVAL                    0x28184D1B
 #define SATA_AHCI_VENDOR_PP2C_CIBGMX_SHIFT                     8
 #define SATA_AHCI_VENDOR_PP2C_CIBGMX_MASK                      0x0000FF00U
@@ -33341,9 +33376,9 @@
 /*
 * CIBGN: COMINIT Burst Gap Nominal.
 */
-#undef SATA_AHCI_VENDOR_PP2C_CIBGN_DEFVAL 
-#undef SATA_AHCI_VENDOR_PP2C_CIBGN_SHIFT 
-#undef SATA_AHCI_VENDOR_PP2C_CIBGN_MASK 
+#undef SATA_AHCI_VENDOR_PP2C_CIBGN_DEFVAL
+#undef SATA_AHCI_VENDOR_PP2C_CIBGN_SHIFT
+#undef SATA_AHCI_VENDOR_PP2C_CIBGN_MASK
 #define SATA_AHCI_VENDOR_PP2C_CIBGN_DEFVAL                     0x28184D1B
 #define SATA_AHCI_VENDOR_PP2C_CIBGN_SHIFT                      16
 #define SATA_AHCI_VENDOR_PP2C_CIBGN_MASK                       0x00FF0000U
@@ -33351,9 +33386,9 @@
 /*
 * CINMP: COMINIT Negate Minimum Period.
 */
-#undef SATA_AHCI_VENDOR_PP2C_CINMP_DEFVAL 
-#undef SATA_AHCI_VENDOR_PP2C_CINMP_SHIFT 
-#undef SATA_AHCI_VENDOR_PP2C_CINMP_MASK 
+#undef SATA_AHCI_VENDOR_PP2C_CINMP_DEFVAL
+#undef SATA_AHCI_VENDOR_PP2C_CINMP_SHIFT
+#undef SATA_AHCI_VENDOR_PP2C_CINMP_MASK
 #define SATA_AHCI_VENDOR_PP2C_CINMP_DEFVAL                     0x28184D1B
 #define SATA_AHCI_VENDOR_PP2C_CINMP_SHIFT                      24
 #define SATA_AHCI_VENDOR_PP2C_CINMP_MASK                       0xFF000000U
@@ -33361,9 +33396,9 @@
 /*
 * CWBGMN: COMWAKE Burst Gap Minimum.
 */
-#undef SATA_AHCI_VENDOR_PP3C_CWBGMN_DEFVAL 
-#undef SATA_AHCI_VENDOR_PP3C_CWBGMN_SHIFT 
-#undef SATA_AHCI_VENDOR_PP3C_CWBGMN_MASK 
+#undef SATA_AHCI_VENDOR_PP3C_CWBGMN_DEFVAL
+#undef SATA_AHCI_VENDOR_PP3C_CWBGMN_SHIFT
+#undef SATA_AHCI_VENDOR_PP3C_CWBGMN_MASK
 #define SATA_AHCI_VENDOR_PP3C_CWBGMN_DEFVAL                    0x0E081906
 #define SATA_AHCI_VENDOR_PP3C_CWBGMN_SHIFT                     0
 #define SATA_AHCI_VENDOR_PP3C_CWBGMN_MASK                      0x000000FFU
@@ -33371,9 +33406,9 @@
 /*
 * CWBGMX: COMWAKE Burst Gap Maximum.
 */
-#undef SATA_AHCI_VENDOR_PP3C_CWBGMX_DEFVAL 
-#undef SATA_AHCI_VENDOR_PP3C_CWBGMX_SHIFT 
-#undef SATA_AHCI_VENDOR_PP3C_CWBGMX_MASK 
+#undef SATA_AHCI_VENDOR_PP3C_CWBGMX_DEFVAL
+#undef SATA_AHCI_VENDOR_PP3C_CWBGMX_SHIFT
+#undef SATA_AHCI_VENDOR_PP3C_CWBGMX_MASK
 #define SATA_AHCI_VENDOR_PP3C_CWBGMX_DEFVAL                    0x0E081906
 #define SATA_AHCI_VENDOR_PP3C_CWBGMX_SHIFT                     8
 #define SATA_AHCI_VENDOR_PP3C_CWBGMX_MASK                      0x0000FF00U
@@ -33381,9 +33416,9 @@
 /*
 * CWBGN: COMWAKE Burst Gap Nominal.
 */
-#undef SATA_AHCI_VENDOR_PP3C_CWBGN_DEFVAL 
-#undef SATA_AHCI_VENDOR_PP3C_CWBGN_SHIFT 
-#undef SATA_AHCI_VENDOR_PP3C_CWBGN_MASK 
+#undef SATA_AHCI_VENDOR_PP3C_CWBGN_DEFVAL
+#undef SATA_AHCI_VENDOR_PP3C_CWBGN_SHIFT
+#undef SATA_AHCI_VENDOR_PP3C_CWBGN_MASK
 #define SATA_AHCI_VENDOR_PP3C_CWBGN_DEFVAL                     0x0E081906
 #define SATA_AHCI_VENDOR_PP3C_CWBGN_SHIFT                      16
 #define SATA_AHCI_VENDOR_PP3C_CWBGN_MASK                       0x00FF0000U
@@ -33391,9 +33426,9 @@
 /*
 * CWNMP: COMWAKE Negate Minimum Period.
 */
-#undef SATA_AHCI_VENDOR_PP3C_CWNMP_DEFVAL 
-#undef SATA_AHCI_VENDOR_PP3C_CWNMP_SHIFT 
-#undef SATA_AHCI_VENDOR_PP3C_CWNMP_MASK 
+#undef SATA_AHCI_VENDOR_PP3C_CWNMP_DEFVAL
+#undef SATA_AHCI_VENDOR_PP3C_CWNMP_SHIFT
+#undef SATA_AHCI_VENDOR_PP3C_CWNMP_MASK
 #define SATA_AHCI_VENDOR_PP3C_CWNMP_DEFVAL                     0x0E081906
 #define SATA_AHCI_VENDOR_PP3C_CWNMP_SHIFT                      24
 #define SATA_AHCI_VENDOR_PP3C_CWNMP_MASK                       0xFF000000U
@@ -33401,9 +33436,9 @@
 /*
 * BMX: COM Burst Maximum.
 */
-#undef SATA_AHCI_VENDOR_PP4C_BMX_DEFVAL 
-#undef SATA_AHCI_VENDOR_PP4C_BMX_SHIFT 
-#undef SATA_AHCI_VENDOR_PP4C_BMX_MASK 
+#undef SATA_AHCI_VENDOR_PP4C_BMX_DEFVAL
+#undef SATA_AHCI_VENDOR_PP4C_BMX_SHIFT
+#undef SATA_AHCI_VENDOR_PP4C_BMX_MASK
 #define SATA_AHCI_VENDOR_PP4C_BMX_DEFVAL                       0x064A0813
 #define SATA_AHCI_VENDOR_PP4C_BMX_SHIFT                        0
 #define SATA_AHCI_VENDOR_PP4C_BMX_MASK                         0x000000FFU
@@ -33411,9 +33446,9 @@
 /*
 * BNM: COM Burst Nominal.
 */
-#undef SATA_AHCI_VENDOR_PP4C_BNM_DEFVAL 
-#undef SATA_AHCI_VENDOR_PP4C_BNM_SHIFT 
-#undef SATA_AHCI_VENDOR_PP4C_BNM_MASK 
+#undef SATA_AHCI_VENDOR_PP4C_BNM_DEFVAL
+#undef SATA_AHCI_VENDOR_PP4C_BNM_SHIFT
+#undef SATA_AHCI_VENDOR_PP4C_BNM_MASK
 #define SATA_AHCI_VENDOR_PP4C_BNM_DEFVAL                       0x064A0813
 #define SATA_AHCI_VENDOR_PP4C_BNM_SHIFT                        8
 #define SATA_AHCI_VENDOR_PP4C_BNM_MASK                         0x0000FF00U
@@ -33426,9 +33461,9 @@
     * d on the OOB Detector Clock typically (PMCLK Clock Period) * SFD giving
     * a nominal time of 500ns based on a 150MHz PMCLK.
 */
-#undef SATA_AHCI_VENDOR_PP4C_SFD_DEFVAL 
-#undef SATA_AHCI_VENDOR_PP4C_SFD_SHIFT 
-#undef SATA_AHCI_VENDOR_PP4C_SFD_MASK 
+#undef SATA_AHCI_VENDOR_PP4C_SFD_DEFVAL
+#undef SATA_AHCI_VENDOR_PP4C_SFD_SHIFT
+#undef SATA_AHCI_VENDOR_PP4C_SFD_MASK
 #define SATA_AHCI_VENDOR_PP4C_SFD_DEFVAL                       0x064A0813
 #define SATA_AHCI_VENDOR_PP4C_SFD_SHIFT                        16
 #define SATA_AHCI_VENDOR_PP4C_SFD_MASK                         0x00FF0000U
@@ -33439,9 +33474,9 @@
     *  the system clock divided by 128, total delay = (Sys Clock Period) * PTS
     * T * 128
 */
-#undef SATA_AHCI_VENDOR_PP4C_PTST_DEFVAL 
-#undef SATA_AHCI_VENDOR_PP4C_PTST_SHIFT 
-#undef SATA_AHCI_VENDOR_PP4C_PTST_MASK 
+#undef SATA_AHCI_VENDOR_PP4C_PTST_DEFVAL
+#undef SATA_AHCI_VENDOR_PP4C_PTST_SHIFT
+#undef SATA_AHCI_VENDOR_PP4C_PTST_MASK
 #define SATA_AHCI_VENDOR_PP4C_PTST_DEFVAL                      0x064A0813
 #define SATA_AHCI_VENDOR_PP4C_PTST_SHIFT                       24
 #define SATA_AHCI_VENDOR_PP4C_PTST_MASK                        0xFF000000U
@@ -33450,9 +33485,9 @@
 * RIT: Retry Interval Timer. The calculated value divided by two, the lowe
     * r digit of precision is not needed.
 */
-#undef SATA_AHCI_VENDOR_PP5C_RIT_DEFVAL 
-#undef SATA_AHCI_VENDOR_PP5C_RIT_SHIFT 
-#undef SATA_AHCI_VENDOR_PP5C_RIT_MASK 
+#undef SATA_AHCI_VENDOR_PP5C_RIT_DEFVAL
+#undef SATA_AHCI_VENDOR_PP5C_RIT_SHIFT
+#undef SATA_AHCI_VENDOR_PP5C_RIT_MASK
 #define SATA_AHCI_VENDOR_PP5C_RIT_DEFVAL                       0x3FFC96A4
 #define SATA_AHCI_VENDOR_PP5C_RIT_SHIFT                        0
 #define SATA_AHCI_VENDOR_PP5C_RIT_MASK                         0x000FFFFFU
@@ -33462,31 +33497,31 @@
     * ice will transmit at a fixed rate ALIGNp after OOB has completed, for a
     * fast SERDES it is suggested that this value be 54.2us / 4
 */
-#undef SATA_AHCI_VENDOR_PP5C_RCT_DEFVAL 
-#undef SATA_AHCI_VENDOR_PP5C_RCT_SHIFT 
-#undef SATA_AHCI_VENDOR_PP5C_RCT_MASK 
+#undef SATA_AHCI_VENDOR_PP5C_RCT_DEFVAL
+#undef SATA_AHCI_VENDOR_PP5C_RCT_SHIFT
+#undef SATA_AHCI_VENDOR_PP5C_RCT_MASK
 #define SATA_AHCI_VENDOR_PP5C_RCT_DEFVAL                       0x3FFC96A4
 #define SATA_AHCI_VENDOR_PP5C_RCT_SHIFT                        20
 #define SATA_AHCI_VENDOR_PP5C_RCT_MASK                         0xFFF00000U
-#undef CRL_APB_RST_LPD_TOP_OFFSET 
+#undef CRL_APB_RST_LPD_TOP_OFFSET
 #define CRL_APB_RST_LPD_TOP_OFFSET                                                 0XFF5E023C
-#undef CRL_APB_RST_LPD_IOU0_OFFSET 
+#undef CRL_APB_RST_LPD_IOU0_OFFSET
 #define CRL_APB_RST_LPD_IOU0_OFFSET                                                0XFF5E0230
-#undef CRF_APB_RST_FPD_TOP_OFFSET 
+#undef CRF_APB_RST_FPD_TOP_OFFSET
 #define CRF_APB_RST_FPD_TOP_OFFSET                                                 0XFD1A0100
-#undef DP_DP_TX_PHY_POWER_DOWN_OFFSET 
+#undef DP_DP_TX_PHY_POWER_DOWN_OFFSET
 #define DP_DP_TX_PHY_POWER_DOWN_OFFSET                                             0XFD4A0238
-#undef DP_DP_PHY_RESET_OFFSET 
+#undef DP_DP_PHY_RESET_OFFSET
 #define DP_DP_PHY_RESET_OFFSET                                                     0XFD4A0200
-#undef CRF_APB_RST_FPD_TOP_OFFSET 
+#undef CRF_APB_RST_FPD_TOP_OFFSET
 #define CRF_APB_RST_FPD_TOP_OFFSET                                                 0XFD1A0100
 
 /*
 * USB 0 reset for control registers
 */
-#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL 
-#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT 
-#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK 
+#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL
+#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT
+#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK
 #define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL              0x00188FDF
 #define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT               10
 #define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK                0x00000400U
@@ -33494,9 +33529,9 @@
 /*
 * USB 0 sleep circuit reset
 */
-#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL 
-#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT 
-#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK 
+#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL
+#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT
+#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK
 #define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL             0x00188FDF
 #define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT              8
 #define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK               0x00000100U
@@ -33504,9 +33539,9 @@
 /*
 * USB 0 reset
 */
-#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL 
-#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 
-#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK 
+#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL
+#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT
+#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK
 #define CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL              0x00188FDF
 #define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT               6
 #define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK                0x00000040U
@@ -33514,9 +33549,9 @@
 /*
 * GEM 3 reset
 */
-#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL 
-#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT 
-#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK 
+#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL
+#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT
+#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK
 #define CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL                 0x0000000F
 #define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT                  3
 #define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK                   0x00000008U
@@ -33524,9 +33559,9 @@
 /*
 * Sata block level reset
 */
-#undef CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL 
-#undef CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT 
-#undef CRF_APB_RST_FPD_TOP_SATA_RESET_MASK 
+#undef CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL
+#undef CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT
+#undef CRF_APB_RST_FPD_TOP_SATA_RESET_MASK
 #define CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL                  0x000F9FFE
 #define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT                   1
 #define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK                    0x00000002U
@@ -33536,9 +33571,9 @@
     *  set to 00, GT will be in active state. bits [1:0] - lane0 Bits [3:2] -
     * lane 1
 */
-#undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL 
-#undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT 
-#undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK 
+#undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL
+#undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT
+#undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK
 #define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL               0x00000000
 #define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT                0
 #define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK                 0x0000000FU
@@ -33546,9 +33581,9 @@
 /*
 * Set to '1' to hold the GT in reset. Clear to release.
 */
-#undef DP_DP_PHY_RESET_GT_RESET_DEFVAL 
-#undef DP_DP_PHY_RESET_GT_RESET_SHIFT 
-#undef DP_DP_PHY_RESET_GT_RESET_MASK 
+#undef DP_DP_PHY_RESET_GT_RESET_DEFVAL
+#undef DP_DP_PHY_RESET_GT_RESET_SHIFT
+#undef DP_DP_PHY_RESET_GT_RESET_MASK
 #define DP_DP_PHY_RESET_GT_RESET_DEFVAL                        0x00010003
 #define DP_DP_PHY_RESET_GT_RESET_SHIFT                         1
 #define DP_DP_PHY_RESET_GT_RESET_MASK                          0x00000002U
@@ -33556,23 +33591,23 @@
 /*
 * Display Port block level reset (includes DPDMA)
 */
-#undef CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL 
-#undef CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT 
-#undef CRF_APB_RST_FPD_TOP_DP_RESET_MASK 
+#undef CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL
+#undef CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT
+#undef CRF_APB_RST_FPD_TOP_DP_RESET_MASK
 #define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL                    0x000F9FFE
 #define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT                     16
 #define CRF_APB_RST_FPD_TOP_DP_RESET_MASK                      0x00010000U
-#undef PMU_GLOBAL_REQ_PWRUP_INT_EN_OFFSET 
+#undef PMU_GLOBAL_REQ_PWRUP_INT_EN_OFFSET
 #define PMU_GLOBAL_REQ_PWRUP_INT_EN_OFFSET                                         0XFFD80118
-#undef PMU_GLOBAL_REQ_PWRUP_TRIG_OFFSET 
+#undef PMU_GLOBAL_REQ_PWRUP_TRIG_OFFSET
 #define PMU_GLOBAL_REQ_PWRUP_TRIG_OFFSET                                           0XFFD80120
 
 /*
 * Power-up Request Interrupt Enable for PL
 */
-#undef PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_DEFVAL 
-#undef PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_SHIFT 
-#undef PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_MASK 
+#undef PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_DEFVAL
+#undef PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_SHIFT
+#undef PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_MASK
 #define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_DEFVAL                  0x00000000
 #define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_SHIFT                   23
 #define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_MASK                    0x00800000U
@@ -33580,9 +33615,9 @@
 /*
 * Power-up Request Trigger for PL
 */
-#undef PMU_GLOBAL_REQ_PWRUP_TRIG_PL_DEFVAL 
-#undef PMU_GLOBAL_REQ_PWRUP_TRIG_PL_SHIFT 
-#undef PMU_GLOBAL_REQ_PWRUP_TRIG_PL_MASK 
+#undef PMU_GLOBAL_REQ_PWRUP_TRIG_PL_DEFVAL
+#undef PMU_GLOBAL_REQ_PWRUP_TRIG_PL_SHIFT
+#undef PMU_GLOBAL_REQ_PWRUP_TRIG_PL_MASK
 #define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_DEFVAL                    0x00000000
 #define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_SHIFT                     23
 #define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_MASK                      0x00800000U
@@ -33590,24 +33625,24 @@
 /*
 * Power-up Request Status for PL
 */
-#undef PMU_GLOBAL_REQ_PWRUP_STATUS_PL_DEFVAL 
-#undef PMU_GLOBAL_REQ_PWRUP_STATUS_PL_SHIFT 
-#undef PMU_GLOBAL_REQ_PWRUP_STATUS_PL_MASK 
+#undef PMU_GLOBAL_REQ_PWRUP_STATUS_PL_DEFVAL
+#undef PMU_GLOBAL_REQ_PWRUP_STATUS_PL_SHIFT
+#undef PMU_GLOBAL_REQ_PWRUP_STATUS_PL_MASK
 #define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_DEFVAL                  0x00000000
 #define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_SHIFT                   23
 #define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_MASK                    0x00800000U
 #define PMU_GLOBAL_REQ_PWRUP_STATUS_OFFSET                                         0XFFD80110
-#undef CRF_APB_RST_FPD_TOP_OFFSET 
+#undef CRF_APB_RST_FPD_TOP_OFFSET
 #define CRF_APB_RST_FPD_TOP_OFFSET                                                 0XFD1A0100
-#undef CRL_APB_RST_LPD_TOP_OFFSET 
+#undef CRL_APB_RST_LPD_TOP_OFFSET
 #define CRL_APB_RST_LPD_TOP_OFFSET                                                 0XFF5E023C
 
 /*
 * AF_FM0 block level reset
 */
-#undef CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_DEFVAL 
-#undef CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_SHIFT 
-#undef CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_MASK 
+#undef CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_DEFVAL
+#undef CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_SHIFT
+#undef CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_MASK
 #define CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_DEFVAL               0x000F9FFE
 #define CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_SHIFT                7
 #define CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_MASK                 0x00000080U
@@ -33615,9 +33650,9 @@
 /*
 * AF_FM1 block level reset
 */
-#undef CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_DEFVAL 
-#undef CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_SHIFT 
-#undef CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_MASK 
+#undef CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_DEFVAL
+#undef CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_SHIFT
+#undef CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_MASK
 #define CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_DEFVAL               0x000F9FFE
 #define CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_SHIFT                8
 #define CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_MASK                 0x00000100U
@@ -33625,9 +33660,9 @@
 /*
 * AF_FM2 block level reset
 */
-#undef CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_DEFVAL 
-#undef CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_SHIFT 
-#undef CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_MASK 
+#undef CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_DEFVAL
+#undef CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_SHIFT
+#undef CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_MASK
 #define CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_DEFVAL               0x000F9FFE
 #define CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_SHIFT                9
 #define CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_MASK                 0x00000200U
@@ -33635,9 +33670,9 @@
 /*
 * AF_FM3 block level reset
 */
-#undef CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_DEFVAL 
-#undef CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_SHIFT 
-#undef CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_MASK 
+#undef CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_DEFVAL
+#undef CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_SHIFT
+#undef CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_MASK
 #define CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_DEFVAL               0x000F9FFE
 #define CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_SHIFT                10
 #define CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_MASK                 0x00000400U
@@ -33645,9 +33680,9 @@
 /*
 * AF_FM4 block level reset
 */
-#undef CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_DEFVAL 
-#undef CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_SHIFT 
-#undef CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_MASK 
+#undef CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_DEFVAL
+#undef CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_SHIFT
+#undef CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_MASK
 #define CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_DEFVAL               0x000F9FFE
 #define CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_SHIFT                11
 #define CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_MASK                 0x00000800U
@@ -33655,9 +33690,9 @@
 /*
 * AF_FM5 block level reset
 */
-#undef CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_DEFVAL 
-#undef CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_SHIFT 
-#undef CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_MASK 
+#undef CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_DEFVAL
+#undef CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_SHIFT
+#undef CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_MASK
 #define CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_DEFVAL               0x000F9FFE
 #define CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_SHIFT                12
 #define CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_MASK                 0x00001000U
@@ -33665,31 +33700,31 @@
 /*
 * AFI FM 6
 */
-#undef CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_DEFVAL 
-#undef CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_SHIFT 
-#undef CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_MASK 
+#undef CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_DEFVAL
+#undef CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_SHIFT
+#undef CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_MASK
 #define CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_DEFVAL               0x00188FDF
 #define CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_SHIFT                19
 #define CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_MASK                 0x00080000U
-#undef GPIO_MASK_DATA_5_MSW_OFFSET 
+#undef GPIO_MASK_DATA_5_MSW_OFFSET
 #define GPIO_MASK_DATA_5_MSW_OFFSET                                                0XFF0A002C
-#undef GPIO_DIRM_5_OFFSET 
+#undef GPIO_DIRM_5_OFFSET
 #define GPIO_DIRM_5_OFFSET                                                         0XFF0A0344
-#undef GPIO_OEN_5_OFFSET 
+#undef GPIO_OEN_5_OFFSET
 #define GPIO_OEN_5_OFFSET                                                          0XFF0A0348
-#undef GPIO_DATA_5_OFFSET 
+#undef GPIO_DATA_5_OFFSET
 #define GPIO_DATA_5_OFFSET                                                         0XFF0A0054
-#undef GPIO_DATA_5_OFFSET 
+#undef GPIO_DATA_5_OFFSET
 #define GPIO_DATA_5_OFFSET                                                         0XFF0A0054
-#undef GPIO_DATA_5_OFFSET 
+#undef GPIO_DATA_5_OFFSET
 #define GPIO_DATA_5_OFFSET                                                         0XFF0A0054
 
 /*
 * Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW]
 */
-#undef GPIO_MASK_DATA_5_MSW_MASK_5_MSW_DEFVAL 
-#undef GPIO_MASK_DATA_5_MSW_MASK_5_MSW_SHIFT 
-#undef GPIO_MASK_DATA_5_MSW_MASK_5_MSW_MASK 
+#undef GPIO_MASK_DATA_5_MSW_MASK_5_MSW_DEFVAL
+#undef GPIO_MASK_DATA_5_MSW_MASK_5_MSW_SHIFT
+#undef GPIO_MASK_DATA_5_MSW_MASK_5_MSW_MASK
 #define GPIO_MASK_DATA_5_MSW_MASK_5_MSW_DEFVAL                 0x00000000
 #define GPIO_MASK_DATA_5_MSW_MASK_5_MSW_SHIFT                  16
 #define GPIO_MASK_DATA_5_MSW_MASK_5_MSW_MASK                   0xFFFF0000U
@@ -33697,65 +33732,66 @@
 /*
 * Operation is the same as DIRM_0[DIRECTION_0]
 */
-#undef GPIO_DIRM_5_DIRECTION_5_DEFVAL 
-#undef GPIO_DIRM_5_DIRECTION_5_SHIFT 
-#undef GPIO_DIRM_5_DIRECTION_5_MASK 
-#define GPIO_DIRM_5_DIRECTION_5_DEFVAL                         
+#undef GPIO_DIRM_5_DIRECTION_5_DEFVAL
+#undef GPIO_DIRM_5_DIRECTION_5_SHIFT
+#undef GPIO_DIRM_5_DIRECTION_5_MASK
+#define GPIO_DIRM_5_DIRECTION_5_DEFVAL
 #define GPIO_DIRM_5_DIRECTION_5_SHIFT                          0
 #define GPIO_DIRM_5_DIRECTION_5_MASK                           0xFFFFFFFFU
 
 /*
 * Operation is the same as OEN_0[OP_ENABLE_0]
 */
-#undef GPIO_OEN_5_OP_ENABLE_5_DEFVAL 
-#undef GPIO_OEN_5_OP_ENABLE_5_SHIFT 
-#undef GPIO_OEN_5_OP_ENABLE_5_MASK 
-#define GPIO_OEN_5_OP_ENABLE_5_DEFVAL                          
+#undef GPIO_OEN_5_OP_ENABLE_5_DEFVAL
+#undef GPIO_OEN_5_OP_ENABLE_5_SHIFT
+#undef GPIO_OEN_5_OP_ENABLE_5_MASK
+#define GPIO_OEN_5_OP_ENABLE_5_DEFVAL
 #define GPIO_OEN_5_OP_ENABLE_5_SHIFT                           0
 #define GPIO_OEN_5_OP_ENABLE_5_MASK                            0xFFFFFFFFU
 
 /*
 * Output Data
 */
-#undef GPIO_DATA_5_DATA_5_DEFVAL 
-#undef GPIO_DATA_5_DATA_5_SHIFT 
-#undef GPIO_DATA_5_DATA_5_MASK 
-#define GPIO_DATA_5_DATA_5_DEFVAL                              
+#undef GPIO_DATA_5_DATA_5_DEFVAL
+#undef GPIO_DATA_5_DATA_5_SHIFT
+#undef GPIO_DATA_5_DATA_5_MASK
+#define GPIO_DATA_5_DATA_5_DEFVAL
 #define GPIO_DATA_5_DATA_5_SHIFT                               0
 #define GPIO_DATA_5_DATA_5_MASK                                0xFFFFFFFFU
 
 /*
 * Output Data
 */
-#undef GPIO_DATA_5_DATA_5_DEFVAL 
-#undef GPIO_DATA_5_DATA_5_SHIFT 
-#undef GPIO_DATA_5_DATA_5_MASK 
-#define GPIO_DATA_5_DATA_5_DEFVAL                              
+#undef GPIO_DATA_5_DATA_5_DEFVAL
+#undef GPIO_DATA_5_DATA_5_SHIFT
+#undef GPIO_DATA_5_DATA_5_MASK
+#define GPIO_DATA_5_DATA_5_DEFVAL
 #define GPIO_DATA_5_DATA_5_SHIFT                               0
 #define GPIO_DATA_5_DATA_5_MASK                                0xFFFFFFFFU
 
 /*
 * Output Data
 */
-#undef GPIO_DATA_5_DATA_5_DEFVAL 
-#undef GPIO_DATA_5_DATA_5_SHIFT 
-#undef GPIO_DATA_5_DATA_5_MASK 
-#define GPIO_DATA_5_DATA_5_DEFVAL                              
+#undef GPIO_DATA_5_DATA_5_DEFVAL
+#undef GPIO_DATA_5_DATA_5_SHIFT
+#undef GPIO_DATA_5_DATA_5_MASK
+#define GPIO_DATA_5_DATA_5_DEFVAL
 #define GPIO_DATA_5_DATA_5_SHIFT                               0
 #define GPIO_DATA_5_DATA_5_MASK                                0xFFFFFFFFU
 #ifdef __cplusplus
 extern "C" {
 #endif
- int psu_init (); 
- unsigned long psu_ps_pl_isolation_removal_data(); 
- unsigned long psu_ps_pl_reset_config_data(); 
- int psu_protection(); 
- int psu_fpd_protection(); 
- int psu_ocm_protection(); 
- int psu_ddr_protection(); 
- int psu_lpd_protection(); 
- int psu_protection_lock(); 
- unsigned long psu_apply_master_tz(); 
+ int psu_init ();
+ unsigned long psu_ps_pl_isolation_removal_data();
+ unsigned long psu_ps_pl_reset_config_data();
+ int psu_protection();
+ int psu_fpd_protection();
+ int psu_ocm_protection();
+ int psu_ddr_protection();
+ int psu_lpd_protection();
+ int psu_protection_lock();
+ unsigned long psu_ddr_qos_init_data(void);
+ unsigned long psu_apply_master_tz();
 #ifdef __cplusplus
 }
 #endif
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