]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
arm64: dts: qcom: hamoa: Fix incomplete Root Port property migration
authorZiyue Zhang <ziyue.zhang@oss.qualcomm.com>
Mon, 30 Mar 2026 02:09:34 +0000 (10:09 +0800)
committerBjorn Andersson <andersson@kernel.org>
Mon, 30 Mar 2026 13:08:48 +0000 (08:08 -0500)
Historically, the Qualcomm PCIe controller node (Host bridge) described
all Root Port properties, such as PHY, PERST#, and WAKE#. But to provide
a more accurate hardware description and to support future multi-Root Port
controllers, these properties were moved to the Root Port node in the
devicetree bindings.

Commit 960609b22be5 ("arm64: dts: qcom: hamoa: Move PHY, PERST, and Wake
GPIOs to PCIe port nodes and add port Nodes for all PCIe ports")
initiated this transition for the Hamoa platform by moving the PHY
property to the Root Port node in hamoa.dtsi. However, it only updated
some platform specific DTS files for PERST# and WAKE#, leaving others in
a "mixed" binding state.

While the PCIe controller driver supports both legacy and Root Port
bindings, It cannot correctly handle a mix of both. In these cases, the
driver parses the PHY from the Root Port node, but fails to find the
PERST# property (which it then assumes is not present, as it is optional).
Consequently, the controller probe succeeds, but PERST# remains
uncontrolled, preventing PCIe endpoints from functioning.

So, fix the incomplete migration by moving the PERST# and WAKE# properties
from the controller node to the Root Port node in all remaining Hamoa
platform DTS files.

Fixes: 960609b22be5 ("arm64: dts: qcom: hamoa: Move PHY, PERST, and Wake GPIOs to PCIe port nodes and add port Nodes for all PCIe ports")
Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260330020934.3501247-1-ziyue.zhang@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi
arch/arm64/boot/dts/qcom/x1-crd.dtsi
arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi
arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi
arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi
arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts
arch/arm64/boot/dts/qcom/x1e80100-medion-sprchrgd-14-s1.dts
arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts

index 8e5c5575a5320172caa628db181560f55b688e67..0a382cc9e64315d0f943c17dd702633e30a1e22c 100644 (file)
 };
 
 &pcie4 {
-       perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
-       wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
-
        pinctrl-0 = <&pcie4_default>;
        pinctrl-names = "default";
 
        status = "okay";
 };
 
-&pcie6a {
-       perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
-       wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
+&pcie4_port0 {
+       reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
+       wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
+};
 
+&pcie6a {
        vddpe-3v3-supply = <&vreg_nvme>;
 
        pinctrl-0 = <&pcie6a_default>;
        status = "okay";
 };
 
+&pcie6a_port0 {
+       reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
+       wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
+};
+
 &pm8550_gpios {
        rtmr0_default: rtmr0-reset-n-active-state {
                pins = "gpio10";
index ded96fb43489b9e11ede25e8f6f809a18234977e..2fbf9ec66fb8bbef5394e318a47b5836666eddca 100644 (file)
 };
 
 &pcie4 {
-       perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
-       wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
-
        pinctrl-0 = <&pcie4_default>;
        pinctrl-names = "default";
 
        status = "okay";
 };
 
+&pcie4_port0 {
+       reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
+       wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
+};
+
 &pcie4_phy {
        vdda-phy-supply = <&vreg_l3i_0p8>;
        vdda-pll-supply = <&vreg_l3e_1p2>;
 };
 
 &pcie5 {
-       perst-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;
-       wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
-
        vddpe-3v3-supply = <&vreg_wwan>;
 
        pinctrl-0 = <&pcie5_default>;
        status = "okay";
 };
 
-&pcie6a {
-       perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
-       wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
+&pcie5_port0 {
+       reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;
+       wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
+};
 
+&pcie6a {
        vddpe-3v3-supply = <&vreg_nvme>;
 
        pinctrl-names = "default";
        status = "okay";
 };
 
+&pcie6a_port0 {
+       reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
+       wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
+};
+
 &pm8550_gpios {
        kypd_vol_up_n: kypd-vol-up-n-state {
                pins = "gpio6";
index bf04a12b16bc93a003fa734d75b192ee2e99bbac..217ca8c7d81dae0508fb740a0077abdf81e5a24a 100644 (file)
 };
 
 &pcie4 {
-       perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
-       wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
-
        pinctrl-0 = <&pcie4_default>;
        pinctrl-names = "default";
 
 };
 
 &pcie4_port0 {
+       reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
+       wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
+
        wifi@0 {
                compatible = "pci17cb,1107";
                reg = <0x10000 0x0 0x0 0x0 0x0>;
 };
 
 &pcie6a {
-       perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
-       wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
-
        vddpe-3v3-supply = <&vreg_nvme>;
 
        pinctrl-0 = <&pcie6a_default>;
        status = "okay";
 };
 
+&pcie6a_port0 {
+       reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
+       wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
+};
+
 &pcie6a_phy {
        vdda-phy-supply = <&vreg_l1d_0p8>;
        vdda-pll-supply = <&vreg_l2j_1p2>;
index a4075434162aa01bddd2c6e90f0eb44cd9bd2a7c..41063948c583da1891b8258fd5126dc7f7ec6b8d 100644 (file)
 };
 
 &pcie4 {
-       perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
-       wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
-
        pinctrl-0 = <&pcie4_default>;
        pinctrl-names = "default";
 
 };
 
 &pcie4_port0 {
+       reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
+       wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
+
        wifi@0 {
                compatible = "pci17cb,1107";
                reg = <0x10000 0x0 0x0 0x0 0x0>;
 };
 
 &pcie6a {
-       perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
-       wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
-
        vddpe-3v3-supply = <&vreg_nvme>;
 
        pinctrl-0 = <&pcie6a_default>;
        status = "okay";
 };
 
+&pcie6a_port0 {
+       reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
+       wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
+};
+
 &pcie6a_phy {
        vdda-phy-supply = <&vreg_l1d_0p8>;
        vdda-pll-supply = <&vreg_l2j_1p2>;
index d77be02848b5535e4478b3104ce49423b5df69cb..ba6b7b5a919186276abee0512a629dd8033dee13 100644 (file)
 };
 
 &pcie6a {
-       perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
-       wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
-
        vddpe-3v3-supply = <&vreg_nvme>;
 
        pinctrl-0 = <&pcie6a_default>;
        status = "okay";
 };
 
+&pcie6a_port0 {
+       reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
+       wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
+};
+
 &pm8550_gpios {
        rtmr0_default: rtmr0-reset-n-active-state {
                pins = "gpio10";
index d6472e5a3f9fa74d4ca21e2d3053b3e7ff4f31ff..d7938d3492053bb514ba7a113f3b2bc66464b358 100644 (file)
 };
 
 &pcie4 {
-       perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
-       wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
-
        pinctrl-0 = <&pcie4_default>;
        pinctrl-names = "default";
 
 };
 
 &pcie4_port0 {
+       reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
+       wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
+
        wifi@0 {
                compatible = "pci17cb,1107";
                reg = <0x10000 0x0 0x0 0x0 0x0>;
index 20a33e6f27ee32b22821b39e4acc441fd8ce55b0..eec5f2f1f75d6711e55e96e3b05ac435ea32e93b 100644 (file)
 };
 
 &pcie4 {
-       perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
-       wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
-
        pinctrl-0 = <&pcie4_default>;
        pinctrl-names = "default";
 
 };
 
 &pcie4_port0 {
+       reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
+       wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
+
        wifi@0 {
                compatible = "pci17cb,1107";
                reg = <0x10000 0x0 0x0 0x0 0x0>;
 };
 
 &pcie6a {
-       perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
-
-       wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
-
        vddpe-3v3-supply = <&vreg_nvme>;
 
        pinctrl-0 = <&pcie6a_default>;
        status = "okay";
 };
 
+&pcie6a_port0 {
+       reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
+       wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
+};
+
 &pm8550_gpios {
        rtmr0_default: rtmr0-reset-n-active-state {
                pins = "gpio10";
index 1e5eb8c5dc988c3c4655f0019e53fc19e0884e4e..06747b54a38e4323fda52d5a9e0eb335df33ab1c 100644 (file)
 };
 
 &pcie4 {
-       perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
-       wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
-
        pinctrl-0 = <&pcie4_default>;
        pinctrl-names = "default";
 
 };
 
 &pcie4_port0 {
+       reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
+       wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
+
        wifi@0 {
                compatible = "pci17cb,1107";
                reg = <0x10000 0x0 0x0 0x0 0x0>;
 };
 
 &pcie6a {
-       perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
-       wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
-
        vddpe-3v3-supply = <&vreg_nvme>;
 
        pinctrl-0 = <&pcie6a_default>;
        status = "okay";
 };
 
+&pcie6a_port0 {
+       reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
+       wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
+};
+
 &pm8550_pwm {
        status = "okay";
 };