drm/amd/display: Update DCN401 path for cursor offload

[Description]
The DCN401 cursor offload path needs to take into account
use_mall_for_cursor, and also need to ensure the dcn32
function assigns the cursor cache fields (DCN401 uses the
dcn32 implementation).

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c
index a5f23bb2a76a12356b1a9c2b290082bb03479d07..41c8f78efdc3444ae2f599f4701372f9d5ac9036 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn32/dcn32_hubp.c
@@ -118,29 +118,7 @@ void hubp32_cursor_set_attributes(
        uint32_t cursor_width = ((attr->width + 63) / 64) * 64;
        uint32_t cursor_height = attr->height;
        uint32_t cursor_size = cursor_width * cursor_height;
-
-       hubp->curs_attr = *attr;
-
-       REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH,
-                       CURSOR_SURFACE_ADDRESS_HIGH, attr->address.high_part);
-       REG_UPDATE(CURSOR_SURFACE_ADDRESS,
-                       CURSOR_SURFACE_ADDRESS, attr->address.low_part);
-
-       REG_UPDATE_2(CURSOR_SIZE,
-                       CURSOR_WIDTH, attr->width,
-                       CURSOR_HEIGHT, attr->height);
-
-       REG_UPDATE_4(CURSOR_CONTROL,
-                       CURSOR_MODE, attr->color_format,
-                       CURSOR_2X_MAGNIFY, attr->attribute_flags.bits.ENABLE_MAGNIFICATION,
-                       CURSOR_PITCH, hw_pitch,
-                       CURSOR_LINES_PER_CHUNK, lpc);
-
-       REG_SET_2(CURSOR_SETTINGS, 0,
-                       /* no shift of the cursor HDL schedule */
-                       CURSOR0_DST_Y_OFFSET, 0,
-                        /* used to shift the cursor chunk request deadline */
-                       CURSOR0_CHUNK_HDL_ADJUST, 3);
+       bool use_mall_for_cursor;
 
        switch (attr->color_format) {
        case CURSOR_MODE_MONO:
@@ -158,11 +136,49 @@ void hubp32_cursor_set_attributes(
                cursor_size *= 8;
                break;
        }
+       use_mall_for_cursor = cursor_size > 16384 ? 1 : 0;
+
+       hubp->curs_attr = *attr;
 
-       if (cursor_size > 16384)
-               REG_UPDATE(DCHUBP_MALL_CONFIG, USE_MALL_FOR_CURSOR, true);
-       else
-               REG_UPDATE(DCHUBP_MALL_CONFIG, USE_MALL_FOR_CURSOR, false);
+       if (!hubp->cursor_offload) {
+               REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH,
+                               CURSOR_SURFACE_ADDRESS_HIGH, attr->address.high_part);
+               REG_UPDATE(CURSOR_SURFACE_ADDRESS,
+                               CURSOR_SURFACE_ADDRESS, attr->address.low_part);
+
+               REG_UPDATE_2(CURSOR_SIZE,
+                               CURSOR_WIDTH, attr->width,
+                               CURSOR_HEIGHT, attr->height);
+
+               REG_UPDATE_4(CURSOR_CONTROL,
+                               CURSOR_MODE, attr->color_format,
+                               CURSOR_2X_MAGNIFY, attr->attribute_flags.bits.ENABLE_MAGNIFICATION,
+                               CURSOR_PITCH, hw_pitch,
+                               CURSOR_LINES_PER_CHUNK, lpc);
+
+               REG_SET_2(CURSOR_SETTINGS, 0,
+                               /* no shift of the cursor HDL schedule */
+                               CURSOR0_DST_Y_OFFSET, 0,
+                                /* used to shift the cursor chunk request deadline */
+                               CURSOR0_CHUNK_HDL_ADJUST, 3);
+
+               REG_UPDATE(DCHUBP_MALL_CONFIG, USE_MALL_FOR_CURSOR, use_mall_for_cursor);
+       }
+       hubp->att.SURFACE_ADDR_HIGH  = attr->address.high_part;
+       hubp->att.SURFACE_ADDR       = attr->address.low_part;
+       hubp->att.size.bits.width    = attr->width;
+       hubp->att.size.bits.height   = attr->height;
+       hubp->att.cur_ctl.bits.mode  = attr->color_format;
+
+       hubp->cur_rect.w = attr->width;
+       hubp->cur_rect.h = attr->height;
+
+       hubp->att.cur_ctl.bits.pitch = hw_pitch;
+       hubp->att.cur_ctl.bits.line_per_chunk = lpc;
+       hubp->att.cur_ctl.bits.cur_2x_magnify = attr->attribute_flags.bits.ENABLE_MAGNIFICATION;
+       hubp->att.settings.bits.dst_y_offset  = 0;
+       hubp->att.settings.bits.chunk_hdl_adjust = 3;
+       hubp->use_mall_for_cursor = use_mall_for_cursor;
 }
 void hubp32_init(struct hubp *hubp)
 {

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
index 2b49b83273742cff0a0a6a3c29a4c956d317bd70..41699ff7256f7b222bf904bdfec5e14f952c29dd 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
@@ -2727,6 +2727,7 @@ void dcn401_update_cursor_offload_pipe(struct dc *dc, const struct pipe_ctx *pip
 
        p->HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET = hubp->att.settings.bits.dst_y_offset;
        p->HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST = hubp->att.settings.bits.chunk_hdl_adjust;
+       p->HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR = hubp->use_mall_for_cursor;
 
        cs->offload_streams[stream_idx].payloads[payload_idx].pipe_mask |= (1u << pipe->pipe_idx);
 }

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
index 5998a20a18c4fe56a5d8ba5fa496abbc88f6c883..b0c13b506c11ac97371f7ea0b16f2622cbdda723 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
@@ -132,6 +132,7 @@ struct hubp {
        struct cursor_position_cache_hubp  pos;
        struct cursor_attribute_cache_hubp att;
        struct cursor_rect cur_rect;
+       bool use_mall_for_cursor;
 };
 
 struct surface_flip_registers {