--- /dev/null
+From 4b33b5ffcf68de3a43e7dddc91c5dc86e6ed8587 Mon Sep 17 00:00:00 2001
+From: Saaem Rizvi <SyedSaaem.Rizvi@amd.com>
+Date: Thu, 9 Jun 2022 15:34:43 -0400
+Subject: drm/amd/display: Add SMU logging code
+
+From: Saaem Rizvi <SyedSaaem.Rizvi@amd.com>
+
+commit 4b33b5ffcf68de3a43e7dddc91c5dc86e6ed8587 upstream.
+
+[WHY]
+Logging for SMU response value after the wait allows us to know
+immediately what the response value was. Makes it easier to debug should
+the value be anything other than OK.
+
+[HOW]
+Using the the already available DC SMU logging functions.
+
+Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
+Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
+Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
+Signed-off-by: Saaem Rizvi <SyedSaaem.Rizvi@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c | 12 ++++++++++
+ drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c | 12 ++++++++++
+ drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c | 8 ++++++
+ drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c | 8 ++++++
+ drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c | 8 ++++++
+ 5 files changed, 48 insertions(+)
+
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
+@@ -41,6 +41,12 @@
+ #define FN(reg_name, field) \
+ FD(reg_name##__##field)
+
++#include "logger_types.h"
++#undef DC_LOGGER
++#define DC_LOGGER \
++ CTX->logger
++#define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); }
++
+ #define VBIOSSMC_MSG_TestMessage 0x1
+ #define VBIOSSMC_MSG_GetSmuVersion 0x2
+ #define VBIOSSMC_MSG_PowerUpGfx 0x3
+@@ -97,6 +103,12 @@ static int rn_vbios_smu_send_msg_with_pa
+ result = rn_smu_wait_for_response(clk_mgr, 10, 200000);
+ ASSERT(result == VBIOSSMC_Result_OK);
+
++ smu_print("SMU response after wait: %d\n", result);
++
++ if (result == VBIOSSMC_Status_BUSY) {
++ return -1;
++ }
++
+ /* First clear response register */
+ REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Status_BUSY);
+
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c
+@@ -41,6 +41,12 @@
+ #define FN(reg_name, field) \
+ FD(reg_name##__##field)
+
++#include "logger_types.h"
++#undef DC_LOGGER
++#define DC_LOGGER \
++ CTX->logger
++#define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); }
++
+ #define VBIOSSMC_MSG_GetSmuVersion 0x2
+ #define VBIOSSMC_MSG_SetDispclkFreq 0x4
+ #define VBIOSSMC_MSG_SetDprefclkFreq 0x5
+@@ -96,6 +102,12 @@ static int dcn301_smu_send_msg_with_para
+
+ result = dcn301_smu_wait_for_response(clk_mgr, 10, 200000);
+
++ smu_print("SMU response after wait: %d\n", result);
++
++ if (result == VBIOSSMC_Status_BUSY) {
++ return -1;
++ }
++
+ /* First clear response register */
+ REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Status_BUSY);
+
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
+@@ -40,6 +40,12 @@
+ #define FN(reg_name, field) \
+ FD(reg_name##__##field)
+
++#include "logger_types.h"
++#undef DC_LOGGER
++#define DC_LOGGER \
++ CTX->logger
++#define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); }
++
+ #define VBIOSSMC_MSG_TestMessage 0x1
+ #define VBIOSSMC_MSG_GetSmuVersion 0x2
+ #define VBIOSSMC_MSG_PowerUpGfx 0x3
+@@ -104,6 +110,8 @@ static int dcn31_smu_send_msg_with_param
+ result = dcn31_smu_wait_for_response(clk_mgr, 10, 200000);
+ ASSERT(result == VBIOSSMC_Result_OK);
+
++ smu_print("SMU response after wait: %d\n", result);
++
+ if (result == VBIOSSMC_Status_BUSY) {
+ return -1;
+ }
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c
+@@ -70,6 +70,12 @@ static const struct IP_BASE NBIO_BASE =
+ #define REG_NBIO(reg_name) \
+ (NBIO_BASE.instance[0].segment[regBIF_BX_PF2_ ## reg_name ## _BASE_IDX] + regBIF_BX_PF2_ ## reg_name)
+
++#include "logger_types.h"
++#undef DC_LOGGER
++#define DC_LOGGER \
++ CTX->logger
++#define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); }
++
+ #define mmMP1_C2PMSG_3 0x3B1050C
+
+ #define VBIOSSMC_MSG_TestMessage 0x01 ///< To check if PMFW is alive and responding. Requirement specified by PMFW team
+@@ -132,6 +138,8 @@ static int dcn315_smu_send_msg_with_para
+ result = dcn315_smu_wait_for_response(clk_mgr, 10, 200000);
+ ASSERT(result == VBIOSSMC_Result_OK);
+
++ smu_print("SMU response after wait: %d\n", result);
++
+ if (result == VBIOSSMC_Status_BUSY) {
+ return -1;
+ }
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c
+@@ -58,6 +58,12 @@ static const struct IP_BASE MP0_BASE = {
+ #define FN(reg_name, field) \
+ FD(reg_name##__##field)
+
++#include "logger_types.h"
++#undef DC_LOGGER
++#define DC_LOGGER \
++ CTX->logger
++#define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); }
++
+ #define VBIOSSMC_MSG_TestMessage 0x01 ///< To check if PMFW is alive and responding. Requirement specified by PMFW team
+ #define VBIOSSMC_MSG_GetPmfwVersion 0x02 ///< Get PMFW version
+ #define VBIOSSMC_MSG_Spare0 0x03 ///< Spare0
+@@ -120,6 +126,8 @@ static int dcn316_smu_send_msg_with_para
+ result = dcn316_smu_wait_for_response(clk_mgr, 10, 200000);
+ ASSERT(result == VBIOSSMC_Result_OK);
+
++ smu_print("SMU response after wait: %d\n", result);
++
+ if (result == VBIOSSMC_Status_BUSY) {
+ return -1;
+ }
--- /dev/null
+From 149f6d1a6035a7aa6595ac6eeb9c8f566b2103cd Mon Sep 17 00:00:00 2001
+From: Saaem Rizvi <SyedSaaem.Rizvi@amd.com>
+Date: Mon, 20 Jun 2022 10:25:19 -0400
+Subject: drm/amd/display: Removing assert statements for Linux
+
+From: Saaem Rizvi <SyedSaaem.Rizvi@amd.com>
+
+commit 149f6d1a6035a7aa6595ac6eeb9c8f566b2103cd upstream.
+
+[WHY]
+Assert statements causing several bugs on Linux DM
+
+[HOW]
+Removing assert statement for Linux DM
+(ASSERT(result == VBIOSSMC_Result_OK)). Also adding
+logging statements for setting dcfclk.
+
+Bug: https://bugzilla.kernel.org/show_bug.cgi?id=216092
+Fixes: c1b972a18d05 ("drm/amd/display: Insert pulling smu busy status before sending another request")
+Reviewed-by: Gabe Teeger <Gabe.Teeger@amd.com>
+Acked-by: Solomon Chiu <solomon.chiu@amd.com>
+Signed-off-by: Saaem Rizvi <SyedSaaem.Rizvi@amd.com>
+Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c | 8 ++++++--
+ drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c | 7 ++++++-
+ drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c | 8 ++++++--
+ drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c | 8 ++++++--
+ drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c | 8 ++++++--
+ 5 files changed, 30 insertions(+), 9 deletions(-)
+
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
+@@ -101,9 +101,9 @@ static int rn_vbios_smu_send_msg_with_pa
+ uint32_t result;
+
+ result = rn_smu_wait_for_response(clk_mgr, 10, 200000);
+- ASSERT(result == VBIOSSMC_Result_OK);
+
+- smu_print("SMU response after wait: %d\n", result);
++ if (result != VBIOSSMC_Result_OK)
++ smu_print("SMU Response was not OK. SMU response after wait received is: %d\n", result);
+
+ if (result == VBIOSSMC_Status_BUSY) {
+ return -1;
+@@ -188,6 +188,10 @@ int rn_vbios_smu_set_hard_min_dcfclk(str
+ VBIOSSMC_MSG_SetHardMinDcfclkByFreq,
+ khz_to_mhz_ceil(requested_dcfclk_khz));
+
++#ifdef DBG
++ smu_print("actual_dcfclk_set_mhz %d is set to : %d\n", actual_dcfclk_set_mhz, actual_dcfclk_set_mhz * 1000);
++#endif
++
+ return actual_dcfclk_set_mhz * 1000;
+ }
+
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c
+@@ -102,7 +102,8 @@ static int dcn301_smu_send_msg_with_para
+
+ result = dcn301_smu_wait_for_response(clk_mgr, 10, 200000);
+
+- smu_print("SMU response after wait: %d\n", result);
++ if (result != VBIOSSMC_Result_OK)
++ smu_print("SMU Response was not OK. SMU response after wait received is: %d\n", result);
+
+ if (result == VBIOSSMC_Status_BUSY) {
+ return -1;
+@@ -179,6 +180,10 @@ int dcn301_smu_set_hard_min_dcfclk(struc
+ VBIOSSMC_MSG_SetHardMinDcfclkByFreq,
+ khz_to_mhz_ceil(requested_dcfclk_khz));
+
++#ifdef DBG
++ smu_print("actual_dcfclk_set_mhz %d is set to : %d\n", actual_dcfclk_set_mhz, actual_dcfclk_set_mhz * 1000);
++#endif
++
+ return actual_dcfclk_set_mhz * 1000;
+ }
+
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
+@@ -108,9 +108,9 @@ static int dcn31_smu_send_msg_with_param
+ uint32_t result;
+
+ result = dcn31_smu_wait_for_response(clk_mgr, 10, 200000);
+- ASSERT(result == VBIOSSMC_Result_OK);
+
+- smu_print("SMU response after wait: %d\n", result);
++ if (result != VBIOSSMC_Result_OK)
++ smu_print("SMU Response was not OK. SMU response after wait received is: %d\n", result);
+
+ if (result == VBIOSSMC_Status_BUSY) {
+ return -1;
+@@ -202,6 +202,10 @@ int dcn31_smu_set_hard_min_dcfclk(struct
+ VBIOSSMC_MSG_SetHardMinDcfclkByFreq,
+ khz_to_mhz_ceil(requested_dcfclk_khz));
+
++#ifdef DBG
++ smu_print("actual_dcfclk_set_mhz %d is set to : %d\n", actual_dcfclk_set_mhz, actual_dcfclk_set_mhz * 1000);
++#endif
++
+ return actual_dcfclk_set_mhz * 1000;
+ }
+
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c
+@@ -136,9 +136,9 @@ static int dcn315_smu_send_msg_with_para
+ uint32_t result;
+
+ result = dcn315_smu_wait_for_response(clk_mgr, 10, 200000);
+- ASSERT(result == VBIOSSMC_Result_OK);
+
+- smu_print("SMU response after wait: %d\n", result);
++ if (result != VBIOSSMC_Result_OK)
++ smu_print("SMU Response was not OK. SMU response after wait received is: %d\n", result);
+
+ if (result == VBIOSSMC_Status_BUSY) {
+ return -1;
+@@ -205,6 +205,10 @@ int dcn315_smu_set_hard_min_dcfclk(struc
+ VBIOSSMC_MSG_SetHardMinDcfclkByFreq,
+ khz_to_mhz_ceil(requested_dcfclk_khz));
+
++#ifdef DBG
++ smu_print("actual_dcfclk_set_mhz %d is set to : %d\n", actual_dcfclk_set_mhz, actual_dcfclk_set_mhz * 1000);
++#endif
++
+ return actual_dcfclk_set_mhz * 1000;
+ }
+
+--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c
++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c
+@@ -124,9 +124,9 @@ static int dcn316_smu_send_msg_with_para
+ uint32_t result;
+
+ result = dcn316_smu_wait_for_response(clk_mgr, 10, 200000);
+- ASSERT(result == VBIOSSMC_Result_OK);
+
+- smu_print("SMU response after wait: %d\n", result);
++ if (result != VBIOSSMC_Result_OK)
++ smu_print("SMU Response was not OK. SMU response after wait received is: %d\n", result);
+
+ if (result == VBIOSSMC_Status_BUSY) {
+ return -1;
+@@ -191,6 +191,10 @@ int dcn316_smu_set_hard_min_dcfclk(struc
+ VBIOSSMC_MSG_SetHardMinDcfclkByFreq,
+ khz_to_mhz_ceil(requested_dcfclk_khz));
+
++#ifdef DBG
++ smu_print("actual_dcfclk_set_mhz %d is set to : %d\n", actual_dcfclk_set_mhz, actual_dcfclk_set_mhz * 1000);
++#endif
++
+ return actual_dcfclk_set_mhz * 1000;
+ }
+
iommu-vt-d-correctly-calculate-sagaw-value-of-iommu.patch
iommu-virtio-fix-interaction-with-vfio.patch
iommu-fix-false-ownership-failure-on-amd-systems-with-pasid-activated.patch
+drm-amd-display-add-smu-logging-code.patch
+drm-amd-display-removing-assert-statements-for-linux.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
