drm/amd/display: Control BW allocation in FW side

[Why]
The BW allocation feature should be controlled in FW side.

[How]
Pass the control bit to FW boot option.

Reviewed-by: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Cruise Hung <Cruise.Hung@amd.com>
Signed-off-by: Tom Chung <chiahsuan.chung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index ddd431ec4d5249b7535191ac12bc7218417a8c2d..089ff96b44c1d92a764637eb126b1a2821267531 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -850,8 +850,7 @@ union dpia_debug_options {
                uint32_t enable_force_tbt3_work_around:1; /* bit 4 */
                uint32_t disable_usb4_pm_support:1; /* bit 5 */
                uint32_t enable_usb4_bw_zero_alloc_patch:1; /* bit 6 */
-               uint32_t enable_bw_allocation_mode:1; /* bit 7 */
-               uint32_t reserved:24;
+               uint32_t reserved:25;
        } bits;
        uint32_t raw;
 };

diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c
index b16eb97ae11c92405a0a7d895ccf69735bd5d58e..c958d3f600c8ffeee248880af076a41729120ac0 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c
@@ -225,11 +225,6 @@ bool link_dpia_enable_usb4_dp_bw_alloc_mode(struct dc_link *link)
        bool ret = false;
        uint8_t val;
 
-       if (link->dc->debug.dpia_debug.bits.enable_bw_allocation_mode == false) {
-               DC_LOG_DEBUG("%s:  link[%d] DPTX BW allocation mode disabled", __func__, link->link_index);
-               return false;
-       }
-
        val = DPTX_BW_ALLOC_MODE_ENABLE | DPTX_BW_ALLOC_UNMASK_IRQ;
 
        if (core_link_write_dpcd(link, DPTX_BW_ALLOCATION_MODE_CONTROL, &val, sizeof(uint8_t)) == DC_OK) {

diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
index 9012a7ba1602104c00bcc1b981847b4ecd2797ea..f25c2fc2f98fd787e654b31aaac743142bf2793b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
@@ -318,6 +318,7 @@ struct dmub_srv_hw_params {
        bool enable_non_transparent_setconfig;
        bool lower_hbr3_phy_ssc;
        bool override_hbr3_pll_vco;
+       bool disable_dpia_bw_allocation;
 };
 
 /**

diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
index 4777c7203b2c2deb913197efa914e77918da4aa4..cd04d7c756c3da1c40a90a8d37e2299dcca32545 100644 (file)
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
@@ -380,6 +380,7 @@ void dmub_dcn31_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmu
        boot_options.bits.override_hbr3_pll_vco = params->override_hbr3_pll_vco;
 
        boot_options.bits.sel_mux_phy_c_d_phy_f_g = (dmub->asic == DMUB_ASIC_DCN31B) ? 1 : 0;
+       boot_options.bits.disable_dpia_bw_allocation = params->disable_dpia_bw_allocation;
 
        REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
 }

diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
index 834e5434ccb882ab2c382a4b046bde1249b37824..b40482dbd6ad641850f3b9ecc392fdd91d4b3981 100644 (file)
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
@@ -418,6 +418,7 @@ void dmub_dcn35_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmu
        boot_options.bits.disable_sldo_opt = params->disable_sldo_opt;
        boot_options.bits.enable_non_transparent_setconfig = params->enable_non_transparent_setconfig;
        boot_options.bits.lower_hbr3_phy_ssc = params->lower_hbr3_phy_ssc;
+       boot_options.bits.disable_dpia_bw_allocation = params->disable_dpia_bw_allocation;
 
        REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
 }