arm64: dts: renesas: rzt2h-n2h-evk-common: Add pinctrl for SCI0 node

Add pinctrl for SCI0 node.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250820200659.2048755-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
index 28330ff63b2ba87297535a773fea4edaaec30367..06300f80668533aad389f4274042e5a574722b08 100644 (file)
--- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
@@ -25,6 +25,23 @@
        clock-frequency = <25000000>;
 };
 
+&pinctrl {
+       /*
+        * SCI0 Pin Configuration:
+        * ------------------------
+        * Signal     | Pin     | RZ/T2H (SW4) | RZ/N2H (DSW9)
+        * -----------|---------|--------------|---------------
+        * SCI0_RXD   | P27_4   | 5: ON, 6: OFF| 1: ON, 2: OFF
+        * SCI0_TXD   | P27_5   | 7: ON, 8: OFF| 3: ON, 4: OFF
+        */
+       sci0_pins: sci0-pins {
+               pinmux = <RZT2H_PORT_PINMUX(27, 4, 0x14)>,
+                        <RZT2H_PORT_PINMUX(27, 5, 0x14)>;
+       };
+};
+
 &sci0 {
+       pinctrl-0 = <&sci0_pins>;
+       pinctrl-names = "default";
        status = "okay";
 };