arm64: dts: mediatek: mt7622: introduce nodes for Wireless Ethernet Dispatch

[ Upstream commit e9b65ecb7c3050dd34ee22ce17f1cf95e8405b15 ]

Introduce wed0 and wed1 nodes in order to enable offloading forwarding
between ethernet and wireless devices on the mt7622 chipset.

Signed-off-by: Felix Fietkau <nbd@nbd.name>
Signed-off-by: David S. Miller <davem@davemloft.net>
Stable-dep-of: 3ba5a6159434 ("arm64: dts: mediatek: mt7622: fix clock controllers")
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
index 07b4d3ba5561249107477e577bb8a3f55a1f20e1..ab218229b7ea1bb90e31982126dcf3121bbcfe7f 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
@@ -893,6 +893,11 @@
                };
        };
 
+       hifsys: syscon@1af00000 {
+               compatible = "mediatek,mt7622-hifsys", "syscon";
+               reg = <0 0x1af00000 0 0x70>;
+       };
+
        ethsys: syscon@1b000000 {
                compatible = "mediatek,mt7622-ethsys",
                             "syscon";
@@ -911,6 +916,26 @@
                #dma-cells = <1>;
        };
 
+       pcie_mirror: pcie-mirror@10000400 {
+               compatible = "mediatek,mt7622-pcie-mirror",
+                            "syscon";
+               reg = <0 0x10000400 0 0x10>;
+       };
+
+       wed0: wed@1020a000 {
+               compatible = "mediatek,mt7622-wed",
+                            "syscon";
+               reg = <0 0x1020a000 0 0x1000>;
+               interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_LOW>;
+       };
+
+       wed1: wed@1020b000 {
+               compatible = "mediatek,mt7622-wed",
+                            "syscon";
+               reg = <0 0x1020b000 0 0x1000>;
+               interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_LOW>;
+       };
+
        eth: ethernet@1b100000 {
                compatible = "mediatek,mt7622-eth",
                             "mediatek,mt2701-eth",
@@ -938,6 +963,9 @@
                mediatek,ethsys = <&ethsys>;
                mediatek,sgmiisys = <&sgmiisys>;
                mediatek,cci-control = <&cci_control2>;
+               mediatek,wed = <&wed0>, <&wed1>;
+               mediatek,pcie-mirror = <&pcie_mirror>;
+               mediatek,hifsys = <&hifsys>;
                dma-coherent;
                #address-cells = <1>;
                #size-cells = <0>;