drm/i915/ltphy: Program LT Phy Voltage Swing

Program LT Phy voltage swing using the Swing tables and plug in the
function at encoder->set_signal_level

Bspec: 74493
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-20-suraj.kandpal@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index b0a58432da570c2b9001d9ae197c390fdb386cce..e412e625b666bbeeac084176d607aa03299c8987 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1467,10 +1467,15 @@ static int translate_signal_level(struct intel_dp *intel_dp,
                                  u8 signal_levels)
 {
        struct intel_display *display = to_intel_display(intel_dp);
+       const u8 *signal_array;
+       size_t array_size;
        int i;
 
-       for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
-               if (index_to_dp_signal_levels[i] == signal_levels)
+       signal_array = index_to_dp_signal_levels;
+       array_size = ARRAY_SIZE(index_to_dp_signal_levels);
+
+       for (i = 0; i < array_size; i++) {
+               if (signal_array[i] == signal_levels)
                        return i;
        }
 
@@ -5301,7 +5306,9 @@ void intel_ddi_init(struct intel_display *display,
                encoder->get_config = hsw_ddi_get_config;
        }
 
-       if (DISPLAY_VER(display) >= 14) {
+       if (HAS_LT_PHY(display)) {
+               encoder->set_signal_levels = intel_lt_phy_set_signal_levels;
+       } else if (DISPLAY_VER(display) >= 14) {
                encoder->set_signal_levels = intel_cx0_phy_set_signal_levels;
        } else if (display->platform.dg2) {
                encoder->set_signal_levels = intel_snps_phy_set_signal_levels;

diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index c2615c3c6e07d2f6dadad2b9ce9b6add74ce7c7b..eb6ec4de8045abb1ebb22d2bb6ea64840123e1da 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -9,6 +9,8 @@
 #include "i915_utils.h"
 #include "intel_cx0_phy.h"
 #include "intel_cx0_phy_regs.h"
+#include "intel_ddi.h"
+#include "intel_ddi_buf_trans.h"
 #include "intel_de.h"
 #include "intel_display.h"
 #include "intel_display_types.h"
@@ -1003,6 +1005,12 @@ static void intel_lt_phy_write(struct intel_encoder *encoder,
        intel_cx0_write(encoder, lane_mask, addr, data, committed);
 }
 
+static void intel_lt_phy_rmw(struct intel_encoder *encoder,
+                            u8 lane_mask, u16 addr, u8 clear, u8 set, bool committed)
+{
+       intel_cx0_rmw(encoder, lane_mask, addr, clear, set, committed);
+}
+
 static void intel_lt_phy_clear_status_p2p(struct intel_encoder *encoder,
                                          int lane)
 {
@@ -1706,6 +1714,61 @@ void intel_lt_phy_pll_disable(struct intel_encoder *encoder)
        intel_lt_phy_transaction_end(encoder, wakeref);
 }
 
+void intel_lt_phy_set_signal_levels(struct intel_encoder *encoder,
+                                   const struct intel_crtc_state *crtc_state)
+{
+       struct intel_display *display = to_intel_display(encoder);
+       const struct intel_ddi_buf_trans *trans;
+       u8 owned_lane_mask;
+       intel_wakeref_t wakeref;
+       int n_entries, ln;
+       struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+
+       if (intel_tc_port_in_tbt_alt_mode(dig_port))
+               return;
+
+       owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder);
+
+       wakeref = intel_lt_phy_transaction_begin(encoder);
+
+       trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
+       if (drm_WARN_ON_ONCE(display->drm, !trans)) {
+               intel_lt_phy_transaction_end(encoder, wakeref);
+               return;
+       }
+
+       for (ln = 0; ln < crtc_state->lane_count; ln++) {
+               int level = intel_ddi_level(encoder, crtc_state, ln);
+               int lane = ln / 2;
+               int tx = ln % 2;
+               u8 lane_mask = lane == 0 ? INTEL_LT_PHY_LANE0 : INTEL_LT_PHY_LANE1;
+
+               if (!(lane_mask & owned_lane_mask))
+                       continue;
+
+               intel_lt_phy_rmw(encoder, lane_mask, LT_PHY_TXY_CTL8(tx),
+                                LT_PHY_TX_SWING_LEVEL_MASK | LT_PHY_TX_SWING_MASK,
+                                LT_PHY_TX_SWING_LEVEL(trans->entries[level].lt.txswing_level) |
+                                LT_PHY_TX_SWING(trans->entries[level].lt.txswing),
+                                MB_WRITE_COMMITTED);
+
+               intel_lt_phy_rmw(encoder, lane_mask, LT_PHY_TXY_CTL2(tx),
+                                LT_PHY_TX_CURSOR_MASK,
+                                LT_PHY_TX_CURSOR(trans->entries[level].lt.pre_cursor),
+                                MB_WRITE_COMMITTED);
+               intel_lt_phy_rmw(encoder, lane_mask, LT_PHY_TXY_CTL3(tx),
+                                LT_PHY_TX_CURSOR_MASK,
+                                LT_PHY_TX_CURSOR(trans->entries[level].lt.main_cursor),
+                                MB_WRITE_COMMITTED);
+               intel_lt_phy_rmw(encoder, lane_mask, LT_PHY_TXY_CTL4(tx),
+                                LT_PHY_TX_CURSOR_MASK,
+                                LT_PHY_TX_CURSOR(trans->entries[level].lt.post_cursor),
+                                MB_WRITE_COMMITTED);
+       }
+
+       intel_lt_phy_transaction_end(encoder, wakeref);
+}
+
 void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
                              const struct intel_crtc_state *crtc_state)
 {

diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h
index 15d3d680871ce1286c9c30172cb0d09b107044ec..6e67ae78801cf62573511dd8c1ffca9b3dc69cec 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
@@ -20,6 +20,8 @@ intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
                            struct intel_encoder *encoder);
 int intel_lt_phy_calc_port_clock(struct intel_encoder *encoder,
                                 const struct intel_crtc_state *crtc_state);
+void intel_lt_phy_set_signal_levels(struct intel_encoder *encoder,
+                                   const struct intel_crtc_state *crtc_state);
 void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
                              const struct intel_crtc_state *crtc_state);
 void intel_xe3plpd_pll_disable(struct intel_encoder *encoder);

diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
index 1f4e48177c8b2fe5e3716d94c5add4bd48698597..da83a7c5faa3eb2bed8f58ff4eb4ebf117bf1887 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
@@ -19,6 +19,19 @@
 #define LT_PHY_MAC_VDR                 _MMIO(0xC00)
 #define    LT_PHY_PCLKIN_GATE          REG_BIT8(0)
 
+/* LT Phy Pipe Spec Registers */
+#define LT_PHY_TXY_CTL8(idx)           (0x408 + (0x200 * (idx)))
+#define  LT_PHY_TX_SWING_LEVEL_MASK    REG_GENMASK8(7, 4)
+#define  LT_PHY_TX_SWING_LEVEL(val)    REG_FIELD_PREP8(LT_PHY_TX_SWING_LEVEL_MASK, val)
+#define  LT_PHY_TX_SWING_MASK          REG_BIT8(3)
+#define  LT_PHY_TX_SWING(val)          REG_FIELD_PREP8(LT_PHY_TX_SWING_MASK, val)
+
+#define LT_PHY_TXY_CTL2(idx)           (0x402 + (0x200 * (idx)))
+#define LT_PHY_TXY_CTL3(idx)           (0x403 + (0x200 * (idx)))
+#define LT_PHY_TXY_CTL4(idx)           (0x404 + (0x200 * (idx)))
+#define  LT_PHY_TX_CURSOR_MASK         REG_GENMASK8(5, 0)
+#define  LT_PHY_TX_CURSOR(val)         REG_FIELD_PREP8(LT_PHY_TX_CURSOR_MASK, val)
+
 /* LT Phy Vendor Register */
 #define LT_PHY_VDR_0_CONFIG    0xC02
 #define  LT_PHY_VDR_DP_PLL_ENABLE      REG_BIT(7)